Expose control over take field for all ClockSinkParameters in system #2618
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hcook
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Aug 24, 2020
jerryz123
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Closed due to being included in #2641 |
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This PR exposes control to set the
takefields of all ClockSinks in the system. This lets us programmatically generate PLL models by inspecting all desired frequencies at a singleClockGroupSourceNode.A
clockSinkParamsfield is added toTileParams, and parameterizes theClockSinkNodein theTilePRCIDomain.Additionally, the
CoherenceManagerWrapperis now set with the samedtsFrequencyas theSystemBus, which drives its clocksRelated issue: ucb-bar/chipyard#614
Type of change: feature request
Impact: API addition (no impact on existing code)
Development Phase: implementation
Release Notes