AXI4Deinterleaver: add a buffer when optimized away #2642
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Otherwise, cycle timing of the design can be impacted by the optimization which removes this IP. The new default changes the behaviour to leave the timing unaffected by the optimization, which, while a change, is safer.
hcook
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Sep 19, 2020
terpstra
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Oct 2, 2020
We cannot use '<>' due to the usual chisel3 bug with both sides wires. To appease ':<>', the types must be identical, so we need a cast.
terpstra
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Oct 2, 2020
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Otherwise, cycle timing of the design can be impacted by the optimization
which removes this IP. The new default changes the behaviour to leave the
timing unaffected by the optimization, which, while a change, is safer.
Type of change: bug report
Impact: no functional change
Development Phase: implementation
@hcook I've opted not to try to modify the circuit to make the non-optimized case pass-through. I'd rather spend that mental energy on a better non-store-and-forward deinterleaver.