From 8f880eb9d4f2e1861a87fdb6941fceb07713ea55 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 17 Sep 2020 17:06:25 -0700 Subject: [PATCH 1/2] AXI4Deinterleaver: add a buffer when optimized away Otherwise, cycle timing of the design can be impacted by the optimization which removes this IP. The new default changes the behaviour to leave the timing unaffected by the optimization, which, while a change, is safer. --- src/main/scala/amba/axi4/Deinterleaver.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala index 48158a359c9..47342924a65 100644 --- a/src/main/scala/amba/axi4/Deinterleaver.scala +++ b/src/main/scala/amba/axi4/Deinterleaver.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util.{leftOR, rightOR, UIntToOH1, OH1ToOH} import scala.math.{min,max} -class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyModule +class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { require (maxReadBytes >= 1 && isPow2(maxReadBytes)) @@ -35,7 +35,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM if (beats <= 1) { // Nothing to do if only single-beat R - in.r :<> out.r + in.r <> buffer.irrevocable(out.r) } else { // Queues to buffer R responses val qs = Seq.tabulate(endId) { i => From d6d9dd26418606e20d12bb3a733c4ec6bb994dc6 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 17 Sep 2020 17:29:44 -0700 Subject: [PATCH 2/2] AXI4Deinterleaver: also update companion object --- src/main/scala/amba/axi4/Deinterleaver.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala index 47342924a65..f52edda6cc7 100644 --- a/src/main/scala/amba/axi4/Deinterleaver.scala +++ b/src/main/scala/amba/axi4/Deinterleaver.scala @@ -115,9 +115,9 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d object AXI4Deinterleaver { - def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = + def apply(maxReadBytes: Int, buffer: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = { - val axi4deint = LazyModule(new AXI4Deinterleaver(maxReadBytes)) + val axi4deint = LazyModule(new AXI4Deinterleaver(maxReadBytes, buffer)) axi4deint.node } }