diff --git a/build.sbt b/build.sbt index 4d04cbc6cf8..d1458aef4c8 100644 --- a/build.sbt +++ b/build.sbt @@ -110,6 +110,7 @@ lazy val docs = project .dependsOn(rocketchip) .enablePlugins(MdocPlugin) .settings(commonSettings) + .settings(chiselSettings) .settings( scalacOptions += "-language:reflectiveCalls", mdocIn := file("docs/src"), diff --git a/docs/src/diplomacy/adder_tutorial.md b/docs/src/diplomacy/adder_tutorial.md index 9ab77ff29d5..6a8d4bf6950 100644 --- a/docs/src/diplomacy/adder_tutorial.md +++ b/docs/src/diplomacy/adder_tutorial.md @@ -14,7 +14,7 @@ ## What is Diplomacy? From the [Diplomatic Design Patterns: A TileLink Case Study](https://carrv.github.io/2017/papers/cook-diplomacy-carrv2017.pdf): -> Diplomacy is a parameter negotiation framework for generating parameterized +> Diplomacy is a parameter negotiation framework for generating parameterized protocol implementations. The goal of this walkthrough is to demonstrate an extremely simple Diplomacy @@ -36,7 +36,7 @@ smaller of the two widths from the drivers versus the monitor, which is the oppo behavior of typical Chisel width inference. ```scala mdoc:invisible -import chipsalliance.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import chisel3._ import chisel3.internal.sourceinfo.SourceInfo import chisel3.stage.ChiselStage @@ -247,15 +247,18 @@ signals an error if the `Adder` returns an incorrect result. It has two `AdderMonitorNode` to take in the sum from the `Adder`. ```scala mdoc + +class ErrorIO extends Bundle { + val error = Output(Bool()) +} /** monitor (sink) */ class AdderMonitor(width: Int, numOperands: Int)(implicit p: Parameters) extends LazyModule { val nodeSeq = Seq.fill(numOperands) { new AdderMonitorNode(UpwardParam(width)) } val nodeSum = new AdderMonitorNode(UpwardParam(width)) - lazy val module = new LazyModuleImp(this) { - val io = IO(new Bundle { - val error = Output(Bool()) - }) + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { + val io = IO(new ErrorIO) // print operation printf(nodeSeq.map(node => p"${node.in.head._1}").reduce(_ + p" + " + _) + p" = ${nodeSum.in.head._1}") @@ -294,7 +297,8 @@ class AdderTestHarness()(implicit p: Parameters) extends LazyModule { drivers.zip(monitor.nodeSeq).foreach { case (driver, monitorNode) => monitorNode := driver.node } monitor.nodeSum := adder.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { when(monitor.module.io.error) { printf("something went wrong") } diff --git a/docs/src/diplomacy/select_tutorial.md b/docs/src/diplomacy/select_tutorial.md index cc75aac4626..4c360770b4c 100644 --- a/docs/src/diplomacy/select_tutorial.md +++ b/docs/src/diplomacy/select_tutorial.md @@ -11,7 +11,7 @@ We will use the following `LazyModule`s in the examples below. ```scala mdoc import chisel3.Bool import freechips.rocketchip.aop.Select -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{ BundleBridgeSink, BundleBridgeSource, @@ -27,16 +27,16 @@ class Top(implicit p: Parameters) extends LazyModule { val aInput = BundleBridgeSource[Bool](() => Bool()) a.input := aInput - val aOutput = a.output.makeSink + val aOutput = a.output.makeSink() val fooInput = BundleBridgeSource[Bool](() => Bool()) foo.input := fooInput - val fooOutput = foo.output.makeSink + val fooOutput = foo.output.makeSink() lazy val module = new LazyModuleImp(this) { - aInput.makeIO - fooOutput.makeIO + aInput.makeIO() + fooOutput.makeIO() fooInput.bundle := aOutput.bundle } } @@ -55,7 +55,7 @@ class A(implicit p: Parameters) extends LazyModule { val input = b.input val output = c.output - val bOutput = b.output.makeSink + val bOutput = b.output.makeSink() val cInput = BundleBridgeSource[Bool](() => Bool()) c.input := cInput lazy val module = new LazyModuleImp(this) {