From 63a6f7767ee22fa556ccc216dc56169794878395 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Thu, 24 Mar 2022 11:50:13 +0100 Subject: [PATCH 1/2] readme: s/SymbiFlow/F4PGA/ Signed-off-by: Unai Martinez-Corral --- CONTRIBUTING.md | 14 ++++++-------- README.md | 12 ++++++------ .../tests/get_cells/get_cells.tcl | 2 +- .../tests/get_nets/get_nets.tcl | 2 +- .../tests/get_pins/get_pins.tcl | 2 +- .../tests/get_ports/get_ports.tcl | 2 +- sdc-plugin/propagation.cc | 2 +- .../tests/set_clock_groups/set_clock_groups.tcl | 2 +- sdc-plugin/tests/set_false_path/set_false_path.tcl | 2 +- sdc-plugin/tests/set_max_delay/set_max_delay.tcl | 2 +- xdc-plugin/tests/counter-dict/counter-dict.tcl | 2 +- xdc-plugin/tests/counter/counter.tcl | 2 +- xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl | 2 +- .../minilitex_ddr_arty/minilitex_ddr_arty.tcl | 2 +- .../non_zero_port_indexes.tcl | 2 +- .../package_pins-dict-space.tcl | 2 +- xdc-plugin/tests/package_pins/package_pins.tcl | 2 +- xdc-plugin/tests/port_indexes/port_indexes.tcl | 2 +- 18 files changed, 28 insertions(+), 30 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index d5615e493..e92bb22a2 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,18 +1,16 @@ -# Contributing to Yosys SymbiFlow Plugins +# Contributing to Yosys F4PGA Plugins -There are a couple of guidelines when contributing to Yosys SymbiFlow Plugins -which are listed here. +There are a couple of guidelines when contributing to Yosys F4PGA Plugins which are listed here. ### Sending -All contributions should be sent as -[GitHub Pull requests](https://help.github.com/articles/creating-a-pull-request-from-a-fork/). +All contributions should be sent as [GitHub Pull requests](https://help.github.com/articles/creating-a-pull-request-from-a-fork/). ### License -All software (code, associated documentation, support files, etc) in the -Yosys SymbiFlow Plugins repository are licensed under the very permissive -[ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file. +All software (code, associated documentation, support files, etc) in the Yosys F4PGA Plugins repository are licensed +under the very permissive [ISC Licence](COPYING). +A copy can be found in the [`COPYING`](COPYING) file. All new contributions must also be released under this license. diff --git a/README.md b/README.md index 9ca9b69aa..88164e079 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,9 @@ -# Yosys SymbiFlow Plugins +# Yosys F4PGA Plugins -This repository contains plugins for -[Yosys](https://github.com/YosysHQ/yosys.git) developed as -[part of the SymbiFlow project](https://symbiflow.github.io). +This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org). ## List of plugins + 1. [Design introspection](#design-introspection-plugin) 2. [FASM](#fasm-plugin) 3. [Integrate inverters](#integrate-inverters-plugin) @@ -32,7 +31,8 @@ Following commands are added with the plugin: ### FASM plugin -Writes out the design's [fasm features](https://symbiflow.readthedocs.io/en/latest/fasm/docs/specification.html) based on the parameter annotations on a design cell. +Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a +design cell. The plugin adds the following command: * write_fasm @@ -91,7 +91,7 @@ Reads Xilinx Design Constraints (XDC) files and annotates the specified cells pa * DRIVE * IN_TERM * LOC -* PACKAGE_PIN +* PACKAGE_PIN The plugin adds the following commands: * read_xdc diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl index 047b15019..d07792430 100644 --- a/design_introspection-plugin/tests/get_cells/get_cells.tcl +++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl @@ -3,7 +3,7 @@ if { [info procs get_cells] == {} } { plugin -i design_introspection } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp diff --git a/design_introspection-plugin/tests/get_nets/get_nets.tcl b/design_introspection-plugin/tests/get_nets/get_nets.tcl index 6ef242623..5dc7ae454 100644 --- a/design_introspection-plugin/tests/get_nets/get_nets.tcl +++ b/design_introspection-plugin/tests/get_nets/get_nets.tcl @@ -3,7 +3,7 @@ if { [info procs get_nets] == {} } { plugin -i design_introspection } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp diff --git a/design_introspection-plugin/tests/get_pins/get_pins.tcl b/design_introspection-plugin/tests/get_pins/get_pins.tcl index d6a64fe31..43ab60ced 100644 --- a/design_introspection-plugin/tests/get_pins/get_pins.tcl +++ b/design_introspection-plugin/tests/get_pins/get_pins.tcl @@ -3,7 +3,7 @@ if { [info procs get_pins] == {} } { plugin -i design_introspection } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl index 47d8fced9..7724e2867 100644 --- a/design_introspection-plugin/tests/get_ports/get_ports.tcl +++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl @@ -3,7 +3,7 @@ if { [info procs get_ports] == {} } { plugin -i design_introspection } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp help get_ports diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc index cfee89ab2..02fa865fb 100644 --- a/sdc-plugin/propagation.cc +++ b/sdc-plugin/propagation.cc @@ -225,7 +225,7 @@ void ClockDividerPropagation::PropagateClocksForCellType(RTLIL::Wire *driver_wir RTLIL::Wire *wire = FindSinkWireOnPort(cell, output); // Don't add clocks on dangling wires // TODO Remove the workaround with the WireHasSinkCell check once the following issue is fixed: - // https://github.com/SymbiFlow/yosys-symbiflow-plugins/issues/59 + // https://github.com/SymbiFlow/yosys-f4pga-plugins/issues/59 if (wire && WireHasSinkCell(wire)) { float clkout_period(pll.clkout_period.at(output)); float clkout_rising_edge(pll.clkout_rising_edge.at(output)); diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl index cefcaca27..1994806cb 100644 --- a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl +++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl @@ -3,7 +3,7 @@ if { [info procs read_sdc] == {} } { plugin -i sdc } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set_clock_groups -group clk1 clk2 diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl index 29c017817..e755e7e39 100644 --- a/sdc-plugin/tests/set_false_path/set_false_path.tcl +++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl @@ -3,7 +3,7 @@ if { [info procs read_sdc] == {} } { plugin -i sdc } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl index 92d4c55e3..4957485c1 100644 --- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl +++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl @@ -3,7 +3,7 @@ if { [info procs read_sdc] == {} } { plugin -i sdc } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net diff --git a/xdc-plugin/tests/counter-dict/counter-dict.tcl b/xdc-plugin/tests/counter-dict/counter-dict.tcl index 91d462456..b6eb5b5cf 100644 --- a/xdc-plugin/tests/counter-dict/counter-dict.tcl +++ b/xdc-plugin/tests/counter-dict/counter-dict.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl index 0a3a62b6f..9347071e3 100644 --- a/xdc-plugin/tests/counter/counter.tcl +++ b/xdc-plugin/tests/counter/counter.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl index 7d99d29c0..d7f55064d 100644 --- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl +++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl @@ -12,7 +12,7 @@ read_verilog -lib [file dirname $::env(DESIGN_TOP)]/cells_xtra.v hierarchy -check -top top # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -run prepare:check #Read the design constraints diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl index 3c5fcd5f6..df2555c13 100644 --- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl +++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v read_verilog [file dirname [info script]]/VexRiscv_Lite.v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl b/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl index 60552c2db..50872c005 100644 --- a/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl +++ b/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl @@ -11,7 +11,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -top top # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -run prepare:check #Read the design constraints diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl index 506097ad5..7625c92c8 100644 --- a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl +++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl @@ -5,7 +5,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl index 7f059e7d7..90298ebbd 100644 --- a/xdc-plugin/tests/package_pins/package_pins.tcl +++ b/xdc-plugin/tests/package_pins/package_pins.tcl @@ -5,7 +5,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl index 2472ffa6f..c2c148a84 100644 --- a/xdc-plugin/tests/port_indexes/port_indexes.tcl +++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp if {[info procs unknown] != ""} { From 5c9f6383d8fd15cc9d847e034929d2b9753e3cec Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Thu, 24 Mar 2022 11:50:35 +0100 Subject: [PATCH 2/2] readme: remove redundant ToC; style Signed-off-by: Unai Martinez-Corral --- README.md | 51 +++++++++++++++++++++++++-------------------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/README.md b/README.md index 88164e079..ad1cce8c5 100644 --- a/README.md +++ b/README.md @@ -2,26 +2,14 @@ This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org). -## List of plugins +## Design introspection plugin -1. [Design introspection](#design-introspection-plugin) -2. [FASM](#fasm-plugin) -3. [Integrate inverters](#integrate-inverters-plugin) -4. [Parameters](#parameters-plugin) -5. [QuickLogic IOBs](#quicklogic-iob-plugin) -6. [QuickLogic QLF FPGAs](#quicklogic-qlf-plugin) -7. [SDC](#sdc-plugin) -8. [XDC](#xdc-plugin) -9. [SystemVerilog](#systemverilog-plugin) - -## Summary - -### Design introspection plugin - -Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. +Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a +selection of objects. Additionally provides functions to convert selection on TCL lists. Following commands are added with the plugin: + * get_cells * get_nets * get_pins @@ -29,50 +17,58 @@ Following commands are added with the plugin: * get_count * selection_to_tcl_list -### FASM plugin +## FASM plugin Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a design cell. The plugin adds the following command: + * write_fasm -### Integrate inverters plugin +## Integrate inverters plugin Implements a pass that integrates inverters into cells that have ports with the 'invertible_pin' attribute set. The plugin adds the following command: + * integrateinv -### Parameters plugin +## Parameters plugin Reads the specified parameter on a selected object. The plugin adds the following command: + * getparam -### QuickLogic IOB plugin +## QuickLogic IOB plugin -[QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints. Used during synthesis for QuickLogic EOS-S3 architecture. +[QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints. +Used during synthesis for QuickLogic EOS-S3 architecture. The plugin adds the following command: + * quicklogic_iob -### QuickLogic QLF FPGAs plugin +## QuickLogic QLF FPGAs plugin [QuickLogic QLF plugin](./ql-qlf-plugin) extends Yosys with synthesis support for `qlf_k4n8` and `qlf_k6n10` architectures. The plugin adds the following command: + * synth_quicklogic * ql_dsp Detailed help on the supported command(s) can be obtained by running `help ` in Yosys. -### SDC plugin +## SDC plugin -Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information. +Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the +complete SDC information. The plugin adds the following commands: + * read_sdc * write_sdc * create_clock @@ -82,9 +78,10 @@ The plugin adds the following commands: * set_max_delay * set_clock_groups -### XDC plugin +## XDC plugin Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as: + * INTERNAL_VREF * IOSTANDARD * SLEW @@ -94,16 +91,18 @@ Reads Xilinx Design Constraints (XDC) files and annotates the specified cells pa * PACKAGE_PIN The plugin adds the following commands: + * read_xdc * get_iobanks * set_property * get_bank_tiles -### SystemVerilog plugin +## SystemVerilog plugin Reads SystemVerilog and UHDM files and processes them into yosys AST. The plugin adds the following commands: + * read_systemverilog * read_uhdm