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Don't prefix package name in _types package in VHDL #1997

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Nov 11, 2021
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@alex-mckenna alex-mckenna commented Nov 11, 2021

Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

Still TODO:

  • Write a changelog entry (see changelog/README.md)
  • Check copyright notices are up to date in edited files

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@leonschoorl leonschoorl left a comment

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Otherwise LGTM

clash-lib/src/Clash/Backend/VHDL.hs Outdated Show resolved Hide resolved
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.
@alex-mckenna alex-mckenna merged commit 7fdc030 into master Nov 11, 2021
@alex-mckenna alex-mckenna deleted the issue-1996 branch November 11, 2021 14:40
alex-mckenna pushed a commit that referenced this pull request Nov 12, 2021
Don't prefix package name in `_types` package in VHDL (copy #1997)
alex-mckenna pushed a commit that referenced this pull request Nov 15, 2021
Don't prefix package name in `_types` package in VHDL (copy #1997)
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Invalid namespace reference in generated VHDL (for Synplify)
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