From 5fc08c459947256aed3d0a09eaa0eec1f4d75784 Mon Sep 17 00:00:00 2001
From: Jianyong Wu <jianyong.wu@arm.com>
Date: Fri, 16 Jun 2023 09:51:47 +0000
Subject: [PATCH] Serial/AArch64: treat LF as LF + CR

In current implementation of pl011, LF is just as LF. It is not the
rule in Unix-like world which treats LF as CRLF.

See related linux kernel doc [1]

[1] https://www.kernel.org/doc/Documentation/serial/driver

Fixes: #258
Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
---
 src/uart_pl011.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/uart_pl011.rs b/src/uart_pl011.rs
index a2e5173b..0189ebb8 100644
--- a/src/uart_pl011.rs
+++ b/src/uart_pl011.rs
@@ -26,6 +26,10 @@ impl Pl011 {
 impl fmt::Write for Pl011 {
     fn write_str(&mut self, s: &str) -> fmt::Result {
         for byte in s.bytes() {
+            // Unix-like OS treats LF as CRLF
+            if byte == b'\n' {
+                self.send(b'\r');
+            }
             self.send(byte);
         }
         Ok(())