From d56bad2b7f2309e7490720b3b32341de9644096a Mon Sep 17 00:00:00 2001 From: Adeeb Shihadeh Date: Wed, 17 Jul 2024 11:03:04 -0700 Subject: [PATCH] H7 CR3 notes --- board/gdb.sh | 3 +++ board/stm32h7/clock.h | 10 ++++++++++ 2 files changed, 13 insertions(+) create mode 100755 board/gdb.sh diff --git a/board/gdb.sh b/board/gdb.sh new file mode 100755 index 0000000000..3dfe994cdc --- /dev/null +++ b/board/gdb.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +gdb-multiarch --eval-command="target extended-remote localhost:3333" diff --git a/board/stm32h7/clock.h b/board/stm32h7/clock.h index 2e3ab701d8..1ff9421981 100644 --- a/board/stm32h7/clock.h +++ b/board/stm32h7/clock.h @@ -18,6 +18,16 @@ PCLK1: 60MHz (for USART2,3,4,5,7,8) */ void clock_init(void) { + /* + WARNING: PWR->CR3's lower byte can only be written once + * subsequent writes will silently fail + * only cleared with a full power-on-reset, not soft reset or reset pin + * some H7 have a bootrom with a DFU routine that writes (and locks) CR3 + * if the CR3 config doesn't match the HW, the core will deadlock and require immediately going into DFU from a cold boot + + In a normal bootup, the bootstub will be the first to write this. The app section calls clock_init again, but the CR3 write will silently fail. This is fine for most cases, but caution should be taken that the bootstub and app always write the same config. + */ + // Set power mode to direct SMPS power supply(depends on the board layout) #ifndef STM32H723 register_set(&(PWR->CR3), PWR_CR3_SMPSEN, 0xFU); // powered only by SMPS