From b62304b17c9437b54e04a28ab76f9baa052b36fb Mon Sep 17 00:00:00 2001
From: Derek Lockhart <lockhart@csl.cornell.edu>
Date: Wed, 15 Apr 2015 12:19:55 -0400
Subject: [PATCH] [pymtl.tools.transl] add BitStruct tests (issue #133)

---
 .../simulation/SimulationTool_struct_test.py  | 58 ++++++++++++++++++-
 .../translation/verilog_structural_test.py    |  4 ++
 2 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/pymtl/tools/simulation/SimulationTool_struct_test.py b/pymtl/tools/simulation/SimulationTool_struct_test.py
index 43640b2b..c66ac347 100644
--- a/pymtl/tools/simulation/SimulationTool_struct_test.py
+++ b/pymtl/tools/simulation/SimulationTool_struct_test.py
@@ -6,7 +6,8 @@
 import pytest
 import pymtl.model.ConnectionEdge
 
-from pymtl import *
+from random import randrange
+from pymtl  import *
 
 from SimulationTool_comb_test import verify_bit_blast, set_ports
 from SimulationTool_seq_test  import setup_sim, local_setup_sim
@@ -745,6 +746,61 @@ def __init__( s, config ):
     sim.cycle()
     for j in range( 4 ):  model.b[j]      == i+j
 
+#=======================================================================
+# BitStructs
+#=======================================================================
+# Helper classes/methods.
+
+class BitStructGlobal( BitStructDefinition ):
+  def __init__( s, src_nbits, dest_nbits ):
+    s.src  = BitField(  src_nbits )
+    s.dest = BitField( dest_nbits )
+
+class BitStructConnect( Model ):
+  def __init__( s, MsgType ):
+    s.in_ = InPort ( MsgType )
+    s.out = OutPort( MsgType )
+    s.connect( s.in_.src,  s.out.dest )
+    s.connect( s.in_.dest, s.out.src  )
+
+def bitstruct_verifier( model, sim, src, dest ):
+  max_ = 2**src
+  for i in range( 10 ):
+    src, dest = randrange(0,max_), randrange(0,max_)
+    model.in_.src .value = src
+    model.in_.dest.value = dest
+    sim.cycle()
+    print model.in_.src,  model.out.src,  src
+    print model.in_.dest, model.out.dest, dest
+    assert model.out.src  == dest
+    assert model.out.dest == src
+
+#-----------------------------------------------------------------------
+# BitStructGlobal
+#-----------------------------------------------------------------------
+@pytest.mark.parametrize('src,dest', [(8,8),(16,16)])
+def test_BitStructGlobal( setup_sim, src, dest ):
+  model      = BitStructConnect( BitStructGlobal( src, dest ) )
+  model, sim = setup_sim( model )
+  bitstruct_verifier( model, sim, src, dest )
+
+#-----------------------------------------------------------------------
+# BitStructLocal
+#-----------------------------------------------------------------------
+@pytest.mark.parametrize('src,dest', [(8,8),(16,16)])
+def test_BitStructLocal( setup_sim, src, dest ):
+  class BitStructLocal( BitStructDefinition ):
+    def __init__( s, src_nbits, dest_nbits ):
+      s.src  = BitField(  src_nbits )
+      s.dest = BitField( dest_nbits )
+  model      = BitStructConnect( BitStructLocal( src, dest ) )
+  model, sim = setup_sim( model )
+  bitstruct_verifier( model, sim, src, dest )
+
+
+# alejandro innarutu
+# kevin thompson
+
 
 
 
diff --git a/pymtl/tools/translation/verilog_structural_test.py b/pymtl/tools/translation/verilog_structural_test.py
index cc80e077..90ff2287 100644
--- a/pymtl/tools/translation/verilog_structural_test.py
+++ b/pymtl/tools/translation/verilog_structural_test.py
@@ -55,6 +55,10 @@
   # FIXME: wire-to-wire connections do not try to infer directionality
   test_WireToWire2,
 
+  # FIXME: generated verilog wrappers can't import BitStructs defined in
+  #        a nested scope (not global)
+  test_BitStructLocal,
+
 ]]
 
 #-----------------------------------------------------------------------