diff --git a/pymtl/tools/translation/verilog_structural.py b/pymtl/tools/translation/verilog_structural.py
index 91d0d54b..d1daa58c 100644
--- a/pymtl/tools/translation/verilog_structural.py
+++ b/pymtl/tools/translation/verilog_structural.py
@@ -149,7 +149,10 @@ def signal_assignments( model, symtab ):
 wire_delim  = ';' + endl
 assignment  = tab + 'assign {} = {};'
 def declare_bitwidth( nbits ):
-  return nbits_decl.format( nbits ) if nbits else onebit_decl
+  # TODO: need to figure out a way to detect when single-bit wires are
+  #       array indexed to make this swap!
+  #return nbits_decl.format( nbits ) if nbits else onebit_decl
+  return nbits_decl.format( nbits )
 
 #-----------------------------------------------------------------------
 # port_decl