From d10fc581cb4b0f1426865e21d76c9c7c808a0c58 Mon Sep 17 00:00:00 2001 From: Derek Lockhart Date: Mon, 16 Feb 2015 18:34:35 -0500 Subject: [PATCH] [pymtl.tools] undo rm [0:0] from 1-bit wire decl (details) Some parameterizable generated code depends on the ability to slice one-bit wires. For example, accel/mvmult/MatrixVecLaneRTL.py contains a wrapper for a multiply operation we use to enable register retiming for a synthesized multiplier. It has a parametrizable number of register stages, these registers can be enabled individually using the nbit s.enables input port. The bitwidth of s.enables is set by the nstages parameter, and a loop in the posedge_clk block is used with slicing to read each enable bit. This works fine if nstages is > 1 (wire [nstages-1:0] enable), but if nstages is 1 the lack of the [0:0] prevents the wire from being sliced. When we had [0:0] it worked as expected. I tried fixing the code to work around this limitation, but PortBundles currently do not support lists of ports (opened as issue #125). --- pymtl/tools/translation/verilog_structural.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pymtl/tools/translation/verilog_structural.py b/pymtl/tools/translation/verilog_structural.py index 91d0d54b..d1daa58c 100644 --- a/pymtl/tools/translation/verilog_structural.py +++ b/pymtl/tools/translation/verilog_structural.py @@ -149,7 +149,10 @@ def signal_assignments( model, symtab ): wire_delim = ';' + endl assignment = tab + 'assign {} = {};' def declare_bitwidth( nbits ): - return nbits_decl.format( nbits ) if nbits else onebit_decl + # TODO: need to figure out a way to detect when single-bit wires are + # array indexed to make this swap! + #return nbits_decl.format( nbits ) if nbits else onebit_decl + return nbits_decl.format( nbits ) #----------------------------------------------------------------------- # port_decl