Processor [AMD Ryzen 7 5800H with Radeon Graphics] |- Architecture [Zen3/Cezanne] |- Vendor ID [AuthenticAMD] |- Microcode [0x0a50000c] |- Signature [ AF_50] |- Stepping [ 0] |- Online CPU [ 16/ 16] |- Base Clock [ 99.809] |- Frequency (MHz) Ratio Min 1197.70 < 12 > Max 3193.88 < 32 > |- Factory [100.000] 3200 [ 32 ] |- Performance |- P-State TGT 3193.88 < 32 > |- Turbo Boost [ LOCK] XFR 4391.58 [ 44 ] CPB 4391.58 [ 44 ] 1C 1297.51 < 13 > 2C 1197.70 < 12 > |- Uncore [ LOCK] |- TDP Level [ 0:0 ] |- Programmable [ LOCK] Instruction Set Extensions |- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y] |- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N] |- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N] |- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N] |- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] |- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y] |- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y] |- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y] |- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y] |- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y] |- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y] |- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y] |- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y] |- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N] Features |- 1 GB Pages Support 1GB-PAGES [Capable] |- 100 MHz multiplier Control 100MHzSteps [Missing] |- Advanced Configuration & Power Interface ACPI [Capable] |- Advanced Programmable Interrupt Controller APIC [Capable] |- APIC Timer Invariance ARAT [Capable] |- Core Multi-Processing CMP Legacy [Capable] |- L1 Data Cache Context ID CNXT-ID [Missing] |- Collaborative Processor Performance Control CPPC [Capable] |- Direct Cache Access DCA [Missing] |- Debugging Extension DE [Capable] |- Debug Store & Precise Event Based Sampling DS, PEBS [Missing] |- CPL Qualified Debug Store DS-CPL [Missing] |- 64-Bit Debug Store DTES64 [Missing] |- Fast Short REP MOVSB FSRM [Capable] |- Fast-String Operation ERMS [Capable] |- Fused Multiply Add FMA | FMA4 [Capable] |- Hardware Lock Elision HLE [Missing] |- Hardware P-state control HwP [Capable] |- Instruction Based Sampling IBS [Capable] |- Instruction INVLPGB INVLPGB [Missing] |- Instruction INVPCID INVPCID [Capable] |- Long Mode 64 bits IA64 | LM [Capable] |- LightWeight Profiling LWP [Missing] |- Memory Bandwidth Enforcement MBE [Capable] |- Machine-Check Architecture MCA [Capable] |- Instruction MCOMMIT MCOMMIT [Missing] |- Memory Protection Extensions MPX [Missing] |- Model Specific Registers MSR [Capable] |- Memory Type Range Registers MTRR [Capable] |- No-Execute Page Protection NX [Capable] |- OS-Enabled Ext. State Management OSXSAVE [Capable] |- Physical Address Extension PAE [Capable] |- Page Attribute Table PAT [Capable] |- Pending Break Enable PBE [Missing] |- Process Context Identifiers PCID [Missing] |- Perfmon and Debug Capability PDCM [Missing] |- Page Global Enable PGE [Capable] |- Page Size Extension PSE [Capable] |- 36-bit Page Size Extension PSE36 [Capable] |- Processor Serial Number PSN [Missing] |- Resource Director Technology/PQE RDT-A [Capable] |- Resource Director Technology/PQM RDT-M [Capable] |- Read Processor Register at User level RDPRU [Capable] |- Restricted Transactional Memory RTM [Missing] |- Safer Mode Extensions SMX [Missing] |- Self-Snoop SS [Missing] |- Supervisor-Mode Access Prevention SMAP [Capable] |- Supervisor-Mode Execution Prevention SMEP [Capable] |- Time Stamp Counter TSC [Invariant] |- Time Stamp Counter Deadline TSC-DEADLINE [Missing] |- TSX Force Abort MSR Register TSX-ABORT [Missing] |- TSX Suspend Load Address Tracking TSX-LDTRK [Missing] |- User-Mode Instruction Prevention UMIP [Missing] |- Virtual Mode Extension VME [Capable] |- Virtual Machine Extensions VMX [Missing] |- Extended xAPIC Support x2APIC [ x2APIC] |- XSAVE/XSTOR States XSAVE [Capable] |- xTPR Update Control xTPR [Missing] Mitigation mechanisms |- Indirect Branch Restricted Speculation IBRS [Capable] |- IBRS Always-On preferred by processor [Missing] |- IBRS preferred over software solution [Capable] |- IBRS provides same speculation limits [Capable] |- Indirect Branch Prediction Barrier IBPB [Capable] |- Single Thread Indirect Branch Predictor STIBP [ Enable] |- Speculative Store Bypass Disable SSBD [Capable] |- SSBD use VIRT SPEC_CTRL register [Missing] |- SSBD not needed on this processor [Missing] |- Architectural - Predictive Store Forwarding PSFD [Capable] Technologies |- Data Cache Unit |- L1 Prefetcher L1 HW < ON> |- L2 Prefetcher L2 HW < ON> |- System Management Mode SMM-Lock [ ON] |- Simultaneous Multithreading SMT [ ON] |- PowerNow! CnQ [OFF] |- Core C-States CCx [ ON] |- Core Performance Boost CPB < ON> |- Watchdog Timer WDT < ON> |- Virtualization SVM [ ON] |- I/O MMU AMD-V [ ON] |- Version [ 0.1] |- Hypervisor [OFF] |- Vendor ID [ N/A] Performance Monitoring |- Version PM [N/A] |- Counters: General Fixed | { 6, 6, 4 } x 48 bits 3 x 64 bits |- Enhanced Halt State C1E |- C2 UnDemotion C2U < ON> |- C3 UnDemotion C3U < ON> |- Core C6 State CC6 < ON> |- Package C6 State PC6 < ON> |- Legacy Frequency ID control FID [OFF] |- Legacy Voltage ID control VID [OFF] |- P-State Hardware Coordination Feedback MPERF/APERF [ ON] |- Collaborative Processor Performance Control CPPC |- Capabilities (MHz) Ratio Lowest AUTO [ 0 ] Efficient AUTO [ 0 ] Guaranteed AUTO [ 0 ] Highest AUTO [ 0 ] |- Core C-States |- C-States Base Address BAR [ 0x413 ] |- MONITOR/MWAIT |- State index: #0 #1 #2 #3 #4 #5 #6 #7 |- Sub C-State: 1 1 0 0 0 0 0 0 |- Core Cycles [Capable] |- Instructions Retired [Capable] |- Reference Cycles [Capable] |- Last Level Cache References [Capable] |- Global Time Stamp Counter [Missing] |- Data Fabric Performance Counter [Capable] |- Core Performance Counter [Capable] Power, Current & Thermal |- Temperature Offset:Junction TjMax [ 49: 0 C] |- CPPC Energy Preference CPPC [Capable] |- Digital Thermal Sensor DTS [Capable] |- Power Limit Notification PLN [Missing] |- Package Thermal Management PTM [Missing] |- Thermal Monitor 1 TTP [ Enable] |- Thermal Monitor 2 HTC [ Enable] |- Thermal Design Power TDP [Missing] |- Minimum Power Min [Missing] |- Maximum Power Max [ 128 W] |- Thermal Design Power Package [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 0 ns] |- Thermal Design Power Core [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power Uncore [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power DRAM [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Thermal Design Power Platform [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 0 ns] |- Package Power Tracking PPT [Missing] |- Electrical Design Current EDC [Missing] |- Thermal Design Current TDC [Missing] |- Core Thermal Point |- Package Thermal Point |- Thermal Monitor Trip Limit [ 125 C] |- HTC Temperature Limit Limit [ 127 C] |- HTC Temperature Hysteresis Threshold [ 2 C] |- Units |- Power watt [ 0.125000000] |- Energy joule [ 0.000015259] |- Window second [ 0.000976562] CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive # ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way 000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 16384 16w 001: 0 1 0 0 0 1 32 8 32 8 512 8 i 16384 16w 002: 0 2 0 0 1 0 32 8 32 8 512 8 i 16384 16w 003: 0 3 0 0 1 1 32 8 32 8 512 8 i 16384 16w 004: 0 4 0 0 2 0 32 8 32 8 512 8 i 16384 16w 005: 0 5 0 0 2 1 32 8 32 8 512 8 i 16384 16w 006: 0 6 0 0 3 0 32 8 32 8 512 8 i 16384 16w 007: 0 7 0 0 3 1 32 8 32 8 512 8 i 16384 16w 008: 0 8 0 1 4 0 32 8 32 8 512 8 i 16384 16w 009: 0 9 0 1 4 1 32 8 32 8 512 8 i 16384 16w 010: 0 10 0 1 5 0 32 8 32 8 512 8 i 16384 16w 011: 0 11 0 1 5 1 32 8 32 8 512 8 i 16384 16w 012: 0 12 0 1 6 0 32 8 32 8 512 8 i 16384 16w 013: 0 13 0 1 6 1 32 8 32 8 512 8 i 16384 16w 014: 0 14 0 1 7 0 32 8 32 8 512 8 i 16384 16w 015: 0 15 0 1 7 1 32 8 32 8 512 8 i 16384 16w AuthenticAMD [ 0] Controller #0 Disabled