diff --git a/.bazelversion b/.bazelversion new file mode 100644 index 0000000..ba7f754 --- /dev/null +++ b/.bazelversion @@ -0,0 +1 @@ +7.4.0 diff --git a/.gitignore b/.gitignore index f963d2a..1c7f8cc 100644 --- a/.gitignore +++ b/.gitignore @@ -14,3 +14,7 @@ build iseconfig *.a *.bin +bazel-bin +bazel-darkriscv +bazel-out +bazel-testlogs diff --git a/BUILD.bazel b/BUILD.bazel new file mode 100644 index 0000000..de21733 --- /dev/null +++ b/BUILD.bazel @@ -0,0 +1,50 @@ +"""Top level Bazel module, allows access to files by other modules.""" + +exports_files( + glob([ + "rtl/**/*.v", + "rtl/**/*.vh", + ]), + visibility = [":__subpackages__"], +) + +filegroup( + name = "verilog", + srcs = glob( + ["rtl/**/*.v"], + # FIXME delete this on next upgrade of ORFS + exclude = ["rtl/darksocv.v"], + ) + [ + ":darksocv_cleaned", + ], + visibility = [":__subpackages__"], +) + +# FIXME delete this on next upgrade of ORFS, it handles $display() statements +genrule( + name = "darksocv_cleaned", + srcs = [ + ":rtl/darksocv.v", + ":rtl/config.vh", + ], + outs = [ + ":cleaned/rtl/darksocv_cleaned.v", + ":cleaned/rtl/config.vh", + ], + cmd = """ + sed -e "/\\$$display/d" $(location :rtl/darksocv.v) > $(location :cleaned/rtl/darksocv_cleaned.v) + cp $(location :rtl/config.vh) $(location :cleaned/rtl/config.vh) + """, +) + +filegroup( + name = "verilog_include", + srcs = glob(["rtl/**/*.vh"]), + visibility = [":__subpackages__"], +) + +filegroup( + name = "verilog_data", + srcs = glob(["src/**/*.mem"]), + visibility = [":__subpackages__"], +) diff --git a/MODULE.bazel b/MODULE.bazel new file mode 100644 index 0000000..420fbc5 --- /dev/null +++ b/MODULE.bazel @@ -0,0 +1,23 @@ +"""Bazel depedencies""" + +module( + name = "darkriscv", + version = "0.0.1", + compatibility_level = 1, +) + +bazel_dep(name = "bazel-orfs") +git_override( + module_name = "bazel-orfs", + commit = "b16da67e50032682dc6f01252217bfb71cf89260", + remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", +) + +orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") +orfs.default( + # To update, find latest at https://hub.docker.com/r/openroad/orfs/tags + image = "docker.io/openroad/orfs:v3.0-2591-g9bca87d7", + sha256 = "673181c3b49235cf5b43e386e4cf478d676b797c8b7736a3ed79fc90f4c8acb7", +) +use_repo(orfs, "com_github_nixos_patchelf_download") +use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock new file mode 100644 index 0000000..7b87ccb --- /dev/null +++ b/MODULE.bazel.lock @@ -0,0 +1,615 @@ +{ + "lockFileVersion": 11, + "registryFileHashes": { + "https://bcr.bazel.build/bazel_registry.json": "8a28e4aff06ee60aed2a8c281907fb8bcbf3b753c91fb5a5c57da3215d5b3497", + "https://bcr.bazel.build/modules/abseil-cpp/20210324.2/MODULE.bazel": "7cd0312e064fde87c8d1cd79ba06c876bd23630c83466e9500321be55c96ace2", + "https://bcr.bazel.build/modules/abseil-cpp/20211102.0/MODULE.bazel": "70390338f7a5106231d20620712f7cccb659cd0e9d073d1991c038eb9fc57589", + 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+# to reduce the size of the SRAM to something that +# is a bit more reasonable. +orfs_flow( + name = "darkram", + abstract_stage = "cts", + arguments = FASTER | { + "CORE_UTILIZATION": "10", + "SYNTH_MEMORY_MAX_BITS": "65536", + "MACRO_BLOCKAGE_HALO": "0", + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl", + }, + # The width/height of a real SRAM might be, say, + # 25% of that of a flip flop based SRAM. + mock_area = 0.25, + sources = { + "SDC_FILE": [":constraints_darkram.sdc"], + }, + stage_data = { + "synth": [ + "//:verilog_data", + "//:verilog_include", + ], + }, + # OpenROAD version of the darkram.v file + verilog_files = [":darkram.v"], +) + +orfs_flow( + name = "darksocv", + arguments = FASTER | { + "SYNTH_HIERARCHICAL": "1", + #"SYNTH_MINIMUM_KEEP_SIZE": "1", + "CORE_UTILIZATION": "40", + "MIN_ROUTING_LAYER": "M2", + "MAX_ROUTING_LAYER": "M7", + "CORE_MARGIN": "2", + "MACRO_PLACE_HALO": "2 2", + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", + "GDS_ALLOW_EMPTY": "darkram", + }, + macros = ["darkram_generate_abstract"], + sources = { + "SDC_FILE": [":constraints.sdc"], + }, + stage_data = { + "synth": [ + "//:verilog_data", + "//:verilog_include", + ], + }, + verilog_files = [ + "//:verilog", + ], +) diff --git a/boards/openroad/README.md b/boards/openroad/README.md new file mode 100644 index 0000000..e098625 --- /dev/null +++ b/boards/openroad/README.md @@ -0,0 +1,32 @@ +OpenROAD ASAP7 PDK configuration +================================ + +TL;DR Install Bazelisk and run command below to build and view darksocv in the GUI, Bazelisk handles all depedencies. + +Demonstrates how to set up an [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) to build darksocv with [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) + +To build and view [Install Bazelisk](https://bazel.build/install/bazelisk) and run: + + bazelisk run //boards/openroad:darksocv_cts /tmp/cts gui_cts + +Register to register histogram +------------------------------ + +![alt text](reg2reg-histogram.png) + +Estimated routing congestion +---------------------------- + +![alt text](routing-congestion.png) + +Ideas for future work +===================== + +- reduce clock period +- darkram.v should consist of serveral SRAMs connected together to be + a more accurate representation +- create a mock SRAM representation with somewhat realistic timing +- add IO constraints to place pins on one edge of the SRAMs and top level +- reduce area + +[MegaBoom](https://github.com/The-OpenROAD-Project/megaboom) demonstrates a number of techniques to study a design and set up mock SRAMs. diff --git a/boards/openroad/constraints.sdc b/boards/openroad/constraints.sdc new file mode 100644 index 0000000..fc496a0 --- /dev/null +++ b/boards/openroad/constraints.sdc @@ -0,0 +1,5 @@ +set clk_name XCLK +set clk_port_name XCLK +set clk_period 2000 + +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/boards/openroad/constraints_darkram.sdc b/boards/openroad/constraints_darkram.sdc new file mode 100644 index 0000000..11af5c4 --- /dev/null +++ b/boards/openroad/constraints_darkram.sdc @@ -0,0 +1,17 @@ +set sdc_version 2.0 + +set clk_name CLK +set clk_port_name CLK +set clk_period 2000 + +set clk_port [get_ports $clk_port_name] +create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port + +set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] +set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] +set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] +set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] +# group_path -name in2reg -from $non_clk_inputs -to [all_registers] +# group_path -name reg2out -from [all_registers] -to [all_outputs] +# group_path -name in2out -from $non_clk_inputs -to [all_outputs] diff --git a/boards/openroad/darkram.v b/boards/openroad/darkram.v new file mode 100644 index 0000000..6923221 --- /dev/null +++ b/boards/openroad/darkram.v @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2018, Marcelo Samsoniuk + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +`timescale 1ns / 1ps + +// Mock SRAM by using fewer address bits to get some reasonable speed and size +`define MLEN 8 + +module darkram +( + input CLK, // clock + input RES, // reset + input HLT, // halt + + input IDREQ, + input [31:0] IADDR, + output [31:0] IDATA, + output IDACK, + + input XDREQ, + input XRD, + input XWR, + input [3:0] XBE, + input [31:0] XADDR, + input [31:0] XATAI, + output [31:0] XATAO, + output XDACK, + + output [3:0] DEBUG +); + + // ro/rw memories + + reg [31:0] MEM [0:2**`MLEN/4-1]; // ro memory + + // memory initialization + + integer i; + initial + begin + `ifdef SIMULATION + $display("dpram: unified BRAM w/ %0dx32-bit",2**`MLEN/4); + `ifdef __WAITSTATE__ + $display("dpram: waitstates=%0d enabled (default=1)",`__WAITSTATE__); + `endif + `ifdef __RMW_CYCLE__ + $display("dpram: RMW cycle enabled.",); + `endif + + for(i=0;i!=2**`MLEN/4;i=i+1) + begin + MEM[i] = 32'd0; + end + `endif + + // workaround for vivado: no path in simulation and .mem extension + + `ifdef XILINX_SIMULATOR + $readmemh("darksocv.mem",MEM); + `elsif MODEL_TECH + $readmemh("../../../../src/darksocv.mem",MEM); + `else + $readmemh("../../src/darksocv.mem",MEM,0); + `endif + end + + // instruction memory +`ifdef __HARVARD__ +`ifdef __ICACHE__ + + reg [3:0] ITACK = 0; + reg [31:0] ROMFF = 0; + + always@(posedge CLK) + begin + `ifdef __WAITSTATE__ + ITACK <= RES ? 0 : ITACK ? ITACK-1 : IDREQ ? `__WAITSTATE__ : 0; + `else + ITACK <= RES ? 0 : ITACK ? ITACK-1 : IDREQ ? 1 : 0; + `endif + + ROMFF <= MEM[IADDR[`MLEN-1:2]]; + end + + assign IDATA = ROMFF; + assign IDACK = ITACK==1; + +`else + + reg [3:0] ITACK = 0; + reg [31:0] ROMFF = 0; + + always@(posedge CLK) + begin + `ifdef __WAITSTATE__ + ITACK <= RES ? 0 : ITACK ? ITACK-1 : IDREQ ? `__WAITSTATE__ : 0; // i-bus wait-state + `endif + + ROMFF <= MEM[IADDR[`MLEN-1:2]]; + // if(!RES && !HLT) $display("bram: addr=%x inst=%x\n",IADDR,ROMFF); + end + + assign IDATA = ROMFF; + + `ifdef __WAITSTATE__ + assign IDACK = ITACK==1; + `else + assign IDACK = IDREQ; + `endif + +`endif +`endif + + // data memory + + reg [3:0] DTACK = 0; + reg [31:0] RAMFF = 0; + + always@(posedge CLK) // stage #1.0 + begin + `ifdef __RMW_CYCLE__ + `ifdef __WAITSTATE__ + DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && (XRD||XWR) ? `__WAITSTATE__ : 0; + `else + DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && (XRD||XWR) ? 1 : 0; + `endif + `else + `ifdef __WAITSTATE__ + DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && XRD ? `__WAITSTATE__ : 0; + `else + DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && XRD ? 1 : 0; + `endif + `endif + + RAMFF <= MEM[XADDR[`MLEN-1:2]]; + + //individual byte/word/long selection, thanks to HYF! + +`ifdef __RMW_CYCLE__ + + // read-modify-write operation w/ 1 wait-state: + + if(XWR && XDREQ) + begin + MEM[XADDR[`MLEN-1:2]] <= + { + XBE[3] ? XATAI[3 * 8 + 7: 3 * 8] : RAMFF[3 * 8 + 7: 3 * 8], + XBE[2] ? XATAI[2 * 8 + 7: 2 * 8] : RAMFF[2 * 8 + 7: 2 * 8], + XBE[1] ? XATAI[1 * 8 + 7: 1 * 8] : RAMFF[1 * 8 + 7: 1 * 8], + XBE[0] ? XATAI[0 * 8 + 7: 0 * 8] : RAMFF[0 * 8 + 7: 0 * 8] + }; + end + +`else + // write-only operation w/ 0 wait-states: + + if(XWR && XDREQ && XBE[3]) MEM[XADDR[`MLEN-1:2]][3 * 8 + 7: 3 * 8] <= XATAI[3 * 8 + 7: 3 * 8]; + if(XWR && XDREQ && XBE[2]) MEM[XADDR[`MLEN-1:2]][2 * 8 + 7: 2 * 8] <= XATAI[2 * 8 + 7: 2 * 8]; + if(XWR && XDREQ && XBE[1]) MEM[XADDR[`MLEN-1:2]][1 * 8 + 7: 1 * 8] <= XATAI[1 * 8 + 7: 1 * 8]; + if(XWR && XDREQ && XBE[0]) MEM[XADDR[`MLEN-1:2]][0 * 8 + 7: 0 * 8] <= XATAI[0 * 8 + 7: 0 * 8]; +`endif + end + + assign XATAO = RAMFF; + +`ifdef __RMW_CYCLE__ + assign XDACK = DTACK==1; +`else + assign XDACK = DTACK==1 ||(XDREQ&&XWR); +`endif + + assign DEBUG = { XDREQ,XRD,XWR,XDACK }; + +endmodule diff --git a/boards/openroad/reg2reg-histogram.png b/boards/openroad/reg2reg-histogram.png new file mode 100644 index 0000000..fec3bcb Binary files /dev/null and b/boards/openroad/reg2reg-histogram.png differ diff --git a/boards/openroad/routing-congestion.png b/boards/openroad/routing-congestion.png new file mode 100644 index 0000000..52d3796 Binary files /dev/null and b/boards/openroad/routing-congestion.png differ