Skip to content

Commit 33881ab

Browse files
author
Paolo Abeni
committed
Merge branch 'octeontx2-minor-tc-fixes'
Subbaraya Sundeep says: ==================== Octeontx2 minor tc fixes This patch set fixes two problems found in tc code wrt to ratelimiting and when installing UDP/TCP filters. Patch 1: CN10K has different register format compared to CN9xx hence fixes that. Patch 2: Check flow mask also before installing a src/dst port filter, otherwise installing for one port installs for other one too. ==================== Link: https://lore.kernel.org/r/1658650874-16459-1-git-send-email-sbhatta@marvell.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2 parents b89fc26 + 59e1be6 commit 33881ab

File tree

1 file changed

+73
-33
lines changed
  • drivers/net/ethernet/marvell/octeontx2/nic

1 file changed

+73
-33
lines changed

‎drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c‎

Lines changed: 73 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -28,13 +28,19 @@
2828
#define MAX_RATE_EXPONENT 0x0FULL
2929
#define MAX_RATE_MANTISSA 0xFFULL
3030

31+
#define CN10K_MAX_BURST_MANTISSA 0x7FFFULL
32+
#define CN10K_MAX_BURST_SIZE 8453888ULL
33+
3134
/* Bitfields in NIX_TLX_PIR register */
3235
#define TLX_RATE_MANTISSA GENMASK_ULL(8, 1)
3336
#define TLX_RATE_EXPONENT GENMASK_ULL(12, 9)
3437
#define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13)
3538
#define TLX_BURST_MANTISSA GENMASK_ULL(36, 29)
3639
#define TLX_BURST_EXPONENT GENMASK_ULL(40, 37)
3740

41+
#define CN10K_TLX_BURST_MANTISSA GENMASK_ULL(43, 29)
42+
#define CN10K_TLX_BURST_EXPONENT GENMASK_ULL(47, 44)
43+
3844
struct otx2_tc_flow_stats {
3945
u64 bytes;
4046
u64 pkts;
@@ -77,33 +83,42 @@ int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic)
7783
}
7884
EXPORT_SYMBOL(otx2_tc_alloc_ent_bitmap);
7985

80-
static void otx2_get_egress_burst_cfg(u32 burst, u32 *burst_exp,
81-
u32 *burst_mantissa)
86+
static void otx2_get_egress_burst_cfg(struct otx2_nic *nic, u32 burst,
87+
u32 *burst_exp, u32 *burst_mantissa)
8288
{
89+
int max_burst, max_mantissa;
8390
unsigned int tmp;
8491

92+
if (is_dev_otx2(nic->pdev)) {
93+
max_burst = MAX_BURST_SIZE;
94+
max_mantissa = MAX_BURST_MANTISSA;
95+
} else {
96+
max_burst = CN10K_MAX_BURST_SIZE;
97+
max_mantissa = CN10K_MAX_BURST_MANTISSA;
98+
}
99+
85100
/* Burst is calculated as
86101
* ((256 + BURST_MANTISSA) << (1 + BURST_EXPONENT)) / 256
87102
* Max supported burst size is 130,816 bytes.
88103
*/
89-
burst = min_t(u32, burst, MAX_BURST_SIZE);
104+
burst = min_t(u32, burst, max_burst);
90105
if (burst) {
91106
*burst_exp = ilog2(burst) ? ilog2(burst) - 1 : 0;
92107
tmp = burst - rounddown_pow_of_two(burst);
93-
if (burst < MAX_BURST_MANTISSA)
108+
if (burst < max_mantissa)
94109
*burst_mantissa = tmp * 2;
95110
else
96111
*burst_mantissa = tmp / (1ULL << (*burst_exp - 7));
97112
} else {
98113
*burst_exp = MAX_BURST_EXPONENT;
99-
*burst_mantissa = MAX_BURST_MANTISSA;
114+
*burst_mantissa = max_mantissa;
100115
}
101116
}
102117

103-
static void otx2_get_egress_rate_cfg(u32 maxrate, u32 *exp,
118+
static void otx2_get_egress_rate_cfg(u64 maxrate, u32 *exp,
104119
u32 *mantissa, u32 *div_exp)
105120
{
106-
unsigned int tmp;
121+
u64 tmp;
107122

108123
/* Rate calculation by hardware
109124
*
@@ -132,21 +147,44 @@ static void otx2_get_egress_rate_cfg(u32 maxrate, u32 *exp,
132147
}
133148
}
134149

135-
static int otx2_set_matchall_egress_rate(struct otx2_nic *nic, u32 burst, u32 maxrate)
150+
static u64 otx2_get_txschq_rate_regval(struct otx2_nic *nic,
151+
u64 maxrate, u32 burst)
136152
{
137-
struct otx2_hw *hw = &nic->hw;
138-
struct nix_txschq_config *req;
139153
u32 burst_exp, burst_mantissa;
140154
u32 exp, mantissa, div_exp;
155+
u64 regval = 0;
156+
157+
/* Get exponent and mantissa values from the desired rate */
158+
otx2_get_egress_burst_cfg(nic, burst, &burst_exp, &burst_mantissa);
159+
otx2_get_egress_rate_cfg(maxrate, &exp, &mantissa, &div_exp);
160+
161+
if (is_dev_otx2(nic->pdev)) {
162+
regval = FIELD_PREP(TLX_BURST_EXPONENT, (u64)burst_exp) |
163+
FIELD_PREP(TLX_BURST_MANTISSA, (u64)burst_mantissa) |
164+
FIELD_PREP(TLX_RATE_DIVIDER_EXPONENT, div_exp) |
165+
FIELD_PREP(TLX_RATE_EXPONENT, exp) |
166+
FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);
167+
} else {
168+
regval = FIELD_PREP(CN10K_TLX_BURST_EXPONENT, (u64)burst_exp) |
169+
FIELD_PREP(CN10K_TLX_BURST_MANTISSA, (u64)burst_mantissa) |
170+
FIELD_PREP(TLX_RATE_DIVIDER_EXPONENT, div_exp) |
171+
FIELD_PREP(TLX_RATE_EXPONENT, exp) |
172+
FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);
173+
}
174+
175+
return regval;
176+
}
177+
178+
static int otx2_set_matchall_egress_rate(struct otx2_nic *nic,
179+
u32 burst, u64 maxrate)
180+
{
181+
struct otx2_hw *hw = &nic->hw;
182+
struct nix_txschq_config *req;
141183
int txschq, err;
142184

143185
/* All SQs share the same TL4, so pick the first scheduler */
144186
txschq = hw->txschq_list[NIX_TXSCH_LVL_TL4][0];
145187

146-
/* Get exponent and mantissa values from the desired rate */
147-
otx2_get_egress_burst_cfg(burst, &burst_exp, &burst_mantissa);
148-
otx2_get_egress_rate_cfg(maxrate, &exp, &mantissa, &div_exp);
149-
150188
mutex_lock(&nic->mbox.lock);
151189
req = otx2_mbox_alloc_msg_nix_txschq_cfg(&nic->mbox);
152190
if (!req) {
@@ -157,11 +195,7 @@ static int otx2_set_matchall_egress_rate(struct otx2_nic *nic, u32 burst, u32 ma
157195
req->lvl = NIX_TXSCH_LVL_TL4;
158196
req->num_regs = 1;
159197
req->reg[0] = NIX_AF_TL4X_PIR(txschq);
160-
req->regval[0] = FIELD_PREP(TLX_BURST_EXPONENT, burst_exp) |
161-
FIELD_PREP(TLX_BURST_MANTISSA, burst_mantissa) |
162-
FIELD_PREP(TLX_RATE_DIVIDER_EXPONENT, div_exp) |
163-
FIELD_PREP(TLX_RATE_EXPONENT, exp) |
164-
FIELD_PREP(TLX_RATE_MANTISSA, mantissa) | BIT_ULL(0);
198+
req->regval[0] = otx2_get_txschq_rate_regval(nic, maxrate, burst);
165199

166200
err = otx2_sync_mbox_msg(&nic->mbox);
167201
mutex_unlock(&nic->mbox.lock);
@@ -230,7 +264,7 @@ static int otx2_tc_egress_matchall_install(struct otx2_nic *nic,
230264
struct netlink_ext_ack *extack = cls->common.extack;
231265
struct flow_action *actions = &cls->rule->action;
232266
struct flow_action_entry *entry;
233-
u32 rate;
267+
u64 rate;
234268
int err;
235269

236270
err = otx2_tc_validate_flow(nic, actions, extack);
@@ -256,7 +290,7 @@ static int otx2_tc_egress_matchall_install(struct otx2_nic *nic,
256290
}
257291
/* Convert bytes per second to Mbps */
258292
rate = entry->police.rate_bytes_ps * 8;
259-
rate = max_t(u32, rate / 1000000, 1);
293+
rate = max_t(u64, rate / 1000000, 1);
260294
err = otx2_set_matchall_egress_rate(nic, entry->police.burst, rate);
261295
if (err)
262296
return err;
@@ -614,21 +648,27 @@ static int otx2_tc_prepare_flow(struct otx2_nic *nic, struct otx2_tc_flow *node,
614648

615649
flow_spec->dport = match.key->dst;
616650
flow_mask->dport = match.mask->dst;
617-
if (ip_proto == IPPROTO_UDP)
618-
req->features |= BIT_ULL(NPC_DPORT_UDP);
619-
else if (ip_proto == IPPROTO_TCP)
620-
req->features |= BIT_ULL(NPC_DPORT_TCP);
621-
else if (ip_proto == IPPROTO_SCTP)
622-
req->features |= BIT_ULL(NPC_DPORT_SCTP);
651+
652+
if (flow_mask->dport) {
653+
if (ip_proto == IPPROTO_UDP)
654+
req->features |= BIT_ULL(NPC_DPORT_UDP);
655+
else if (ip_proto == IPPROTO_TCP)
656+
req->features |= BIT_ULL(NPC_DPORT_TCP);
657+
else if (ip_proto == IPPROTO_SCTP)
658+
req->features |= BIT_ULL(NPC_DPORT_SCTP);
659+
}
623660

624661
flow_spec->sport = match.key->src;
625662
flow_mask->sport = match.mask->src;
626-
if (ip_proto == IPPROTO_UDP)
627-
req->features |= BIT_ULL(NPC_SPORT_UDP);
628-
else if (ip_proto == IPPROTO_TCP)
629-
req->features |= BIT_ULL(NPC_SPORT_TCP);
630-
else if (ip_proto == IPPROTO_SCTP)
631-
req->features |= BIT_ULL(NPC_SPORT_SCTP);
663+
664+
if (flow_mask->sport) {
665+
if (ip_proto == IPPROTO_UDP)
666+
req->features |= BIT_ULL(NPC_SPORT_UDP);
667+
else if (ip_proto == IPPROTO_TCP)
668+
req->features |= BIT_ULL(NPC_SPORT_TCP);
669+
else if (ip_proto == IPPROTO_SCTP)
670+
req->features |= BIT_ULL(NPC_SPORT_SCTP);
671+
}
632672
}
633673

634674
return otx2_tc_parse_actions(nic, &rule->action, req, f, node);

0 commit comments

Comments
 (0)