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Merge branch 'mt7530-dsa-subdriver-improvements-act-ii'
Arınç ÜNAL says: ==================== MT7530 DSA Subdriver Improvements Act II This is the second patch series with the goal of simplifying the MT7530 DSA subdriver and improving support for MT7530, MT7531, and the switch on the MT7988 SoC. I have done a simple ping test to confirm basic communication on all switch ports on MCM and standalone MT7530, and MT7531 switch with this patch series applied. MT7621 Unielec, MCM MT7530: rgmii-only-gmac0-mt7621-unielec-u7621-06-16m.dtb gmac0-and-gmac1-mt7621-unielec-u7621-06-16m.dtb tftpboot 0x80008000 mips-uzImage.bin; tftpboot 0x83000000 mips-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootm 0x80008000 0x83000000 0x83f00000 MT7622 Bananapi, MT7531: gmac0-and-gmac1-mt7622-bananapi-bpi-r64.dtb tftpboot 0x40000000 arm64-Image; tftpboot 0x45000000 arm64-rootfs.cpio.uboot; tftpboot 0x4a000000 $dtb; booti 0x40000000 0x45000000 0x4a000000 MT7623 Bananapi, standalone MT7530: rgmii-only-gmac0-mt7623n-bananapi-bpi-r2.dtb gmac0-and-gmac1-mt7623n-bananapi-bpi-r2.dtb tftpboot 0x80008000 arm-zImage; tftpboot 0x83000000 arm-rootfs.cpio.uboot; tftpboot 0x83f00000 $dtb; bootz 0x80008000 0x83000000 0x83f00000 This patch series is the continuation of the patch series linked below. https://lore.kernel.org/r/20230522121532.86610-1-arinc.unal@arinc9.com Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> ==================== Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-0-d7d92a185cb1@arinc9.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents c885b95 + b43990b commit a1e55f5

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‎drivers/net/dsa/mt7530.c‎

Lines changed: 53 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -414,83 +414,57 @@ mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds)
414414
}
415415

416416
/* Setup port 6 interface mode and TRGMII TX circuit */
417-
static int
418-
mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
417+
static void
418+
mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)
419419
{
420420
struct mt7530_priv *priv = ds->priv;
421-
u32 ncpo1, ssc_delta, trgint, xtal;
422-
423-
xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
421+
u32 ncpo1, ssc_delta, xtal;
424422

425-
if (xtal == HWTRAP_XTAL_20MHZ) {
426-
dev_err(priv->dev,
427-
"%s: MT7530 with a 20MHz XTAL is not supported!\n",
428-
__func__);
429-
return -EINVAL;
430-
}
423+
/* Disable the MT7530 TRGMII clocks */
424+
core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
431425

432-
switch (interface) {
433-
case PHY_INTERFACE_MODE_RGMII:
434-
trgint = 0;
435-
break;
436-
case PHY_INTERFACE_MODE_TRGMII:
437-
trgint = 1;
438-
if (xtal == HWTRAP_XTAL_25MHZ)
439-
ssc_delta = 0x57;
440-
else
441-
ssc_delta = 0x87;
442-
if (priv->id == ID_MT7621) {
443-
/* PLL frequency: 125MHz: 1.0GBit */
444-
if (xtal == HWTRAP_XTAL_40MHZ)
445-
ncpo1 = 0x0640;
446-
if (xtal == HWTRAP_XTAL_25MHZ)
447-
ncpo1 = 0x0a00;
448-
} else { /* PLL frequency: 250MHz: 2.0Gbit */
449-
if (xtal == HWTRAP_XTAL_40MHZ)
450-
ncpo1 = 0x0c80;
451-
if (xtal == HWTRAP_XTAL_25MHZ)
452-
ncpo1 = 0x1400;
453-
}
454-
break;
455-
default:
456-
dev_err(priv->dev, "xMII interface %d not supported\n",
457-
interface);
458-
return -EINVAL;
426+
if (interface == PHY_INTERFACE_MODE_RGMII) {
427+
mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
428+
P6_INTF_MODE(0));
429+
return;
459430
}
460431

461-
mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
462-
P6_INTF_MODE(trgint));
432+
mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
463433

464-
if (trgint) {
465-
/* Disable the MT7530 TRGMII clocks */
466-
core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
434+
xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
467435

468-
/* Setup the MT7530 TRGMII Tx Clock */
469-
core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
470-
core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
471-
core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
472-
core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
473-
core_write(priv, CORE_PLL_GROUP4,
474-
RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
475-
RG_SYSPLL_BIAS_LPF_EN);
476-
core_write(priv, CORE_PLL_GROUP2,
477-
RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
478-
RG_SYSPLL_POSDIV(1));
479-
core_write(priv, CORE_PLL_GROUP7,
480-
RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
481-
RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
436+
if (xtal == HWTRAP_XTAL_25MHZ)
437+
ssc_delta = 0x57;
438+
else
439+
ssc_delta = 0x87;
482440

483-
/* Enable the MT7530 TRGMII clocks */
484-
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
441+
if (priv->id == ID_MT7621) {
442+
/* PLL frequency: 125MHz: 1.0GBit */
443+
if (xtal == HWTRAP_XTAL_40MHZ)
444+
ncpo1 = 0x0640;
445+
if (xtal == HWTRAP_XTAL_25MHZ)
446+
ncpo1 = 0x0a00;
447+
} else { /* PLL frequency: 250MHz: 2.0Gbit */
448+
if (xtal == HWTRAP_XTAL_40MHZ)
449+
ncpo1 = 0x0c80;
450+
if (xtal == HWTRAP_XTAL_25MHZ)
451+
ncpo1 = 0x1400;
485452
}
486453

487-
return 0;
488-
}
454+
/* Setup the MT7530 TRGMII Tx Clock */
455+
core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
456+
core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
457+
core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
458+
core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
459+
core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
460+
RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
461+
core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
462+
RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
463+
core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
464+
RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
489465

490-
static int
491-
mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
492-
{
493-
return 0;
466+
/* Enable the MT7530 TRGMII clocks */
467+
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
494468
}
495469

496470
static void
@@ -943,9 +917,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
943917
val &= ~MHWTRAP_P5_DIS;
944918
break;
945919
default:
946-
dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
947-
priv->p5_intf_sel);
948-
goto unlock_exit;
920+
break;
949921
}
950922

951923
/* Setup RGMII settings */
@@ -975,7 +947,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
975947
dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
976948
val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
977949

978-
unlock_exit:
979950
mutex_unlock(&priv->reg_mutex);
980951
}
981952

@@ -2262,6 +2233,12 @@ mt7530_setup(struct dsa_switch *ds)
22622233
return -ENODEV;
22632234
}
22642235

2236+
if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
2237+
dev_err(priv->dev,
2238+
"MT7530 with a 20MHz XTAL is not supported!\n");
2239+
return -EINVAL;
2240+
}
2241+
22652242
/* Reset the switch through internal reset */
22662243
mt7530_write(priv, MT7530_SYS_CTRL,
22672244
SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
@@ -2596,11 +2573,9 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
25962573
static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
25972574
struct phylink_config *config)
25982575
{
2599-
phy_interface_zero(config->supported_interfaces);
2600-
26012576
switch (port) {
26022577
/* Ports which are connected to switch PHYs. There is no MII pinout. */
2603-
case 0 ... 4:
2578+
case 0 ... 3:
26042579
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
26052580
config->supported_interfaces);
26062581
break;
@@ -2614,25 +2589,16 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
26142589
}
26152590
}
26162591

2617-
static int
2618-
mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2619-
{
2620-
struct mt7530_priv *priv = ds->priv;
2621-
2622-
return priv->info->pad_setup(ds, state->interface);
2623-
}
2624-
26252592
static int
26262593
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
26272594
phy_interface_t interface)
26282595
{
26292596
struct mt7530_priv *priv = ds->priv;
26302597

2631-
/* Only need to setup port5. */
2632-
if (port != 5)
2633-
return 0;
2634-
2635-
mt7530_setup_port5(priv->ds, interface);
2598+
if (port == 5)
2599+
mt7530_setup_port5(priv->ds, interface);
2600+
else if (port == 6)
2601+
mt7530_setup_port6(priv->ds, interface);
26362602

26372603
return 0;
26382604
}
@@ -2788,8 +2754,6 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
27882754
if (priv->p6_interface == state->interface)
27892755
break;
27902756

2791-
mt753x_pad_setup(ds, state);
2792-
27932757
if (mt753x_mac_config(ds, port, mode, state) < 0)
27942758
goto unsupported;
27952759

@@ -3106,11 +3070,6 @@ mt753x_conduit_state_change(struct dsa_switch *ds,
31063070
mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
31073071
}
31083072

3109-
static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
3110-
{
3111-
return 0;
3112-
}
3113-
31143073
static int mt7988_setup(struct dsa_switch *ds)
31153074
{
31163075
struct mt7530_priv *priv = ds->priv;
@@ -3174,7 +3133,6 @@ const struct mt753x_info mt753x_table[] = {
31743133
.phy_write_c22 = mt7530_phy_write_c22,
31753134
.phy_read_c45 = mt7530_phy_read_c45,
31763135
.phy_write_c45 = mt7530_phy_write_c45,
3177-
.pad_setup = mt7530_pad_clk_setup,
31783136
.mac_port_get_caps = mt7530_mac_port_get_caps,
31793137
.mac_port_config = mt7530_mac_config,
31803138
},
@@ -3186,7 +3144,6 @@ const struct mt753x_info mt753x_table[] = {
31863144
.phy_write_c22 = mt7530_phy_write_c22,
31873145
.phy_read_c45 = mt7530_phy_read_c45,
31883146
.phy_write_c45 = mt7530_phy_write_c45,
3189-
.pad_setup = mt7530_pad_clk_setup,
31903147
.mac_port_get_caps = mt7530_mac_port_get_caps,
31913148
.mac_port_config = mt7530_mac_config,
31923149
},
@@ -3198,7 +3155,6 @@ const struct mt753x_info mt753x_table[] = {
31983155
.phy_write_c22 = mt7531_ind_c22_phy_write,
31993156
.phy_read_c45 = mt7531_ind_c45_phy_read,
32003157
.phy_write_c45 = mt7531_ind_c45_phy_write,
3201-
.pad_setup = mt7531_pad_setup,
32023158
.cpu_port_config = mt7531_cpu_port_config,
32033159
.mac_port_get_caps = mt7531_mac_port_get_caps,
32043160
.mac_port_config = mt7531_mac_config,
@@ -3211,7 +3167,6 @@ const struct mt753x_info mt753x_table[] = {
32113167
.phy_write_c22 = mt7531_ind_c22_phy_write,
32123168
.phy_read_c45 = mt7531_ind_c45_phy_read,
32133169
.phy_write_c45 = mt7531_ind_c45_phy_write,
3214-
.pad_setup = mt7988_pad_setup,
32153170
.cpu_port_config = mt7988_cpu_port_config,
32163171
.mac_port_get_caps = mt7988_mac_port_get_caps,
32173172
.mac_port_config = mt7988_mac_config,
@@ -3241,9 +3196,8 @@ mt7530_probe_common(struct mt7530_priv *priv)
32413196
/* Sanity check if these required device operations are filled
32423197
* properly.
32433198
*/
3244-
if (!priv->info->sw_setup || !priv->info->pad_setup ||
3245-
!priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||
3246-
!priv->info->mac_port_get_caps ||
3199+
if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
3200+
!priv->info->phy_write_c22 || !priv->info->mac_port_get_caps ||
32473201
!priv->info->mac_port_config)
32483202
return -EINVAL;
32493203

‎drivers/net/dsa/mt7530.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -704,8 +704,6 @@ struct mt753x_pcs {
704704
* @phy_write_c22: Holding the way writing PHY port using C22
705705
* @phy_read_c45: Holding the way reading PHY port using C45
706706
* @phy_write_c45: Holding the way writing PHY port using C45
707-
* @pad_setup: Holding the way setting up the bus pad for a certain
708-
* MAC port
709707
* @phy_mode_supported: Check if the PHY type is being supported on a certain
710708
* port
711709
* @mac_port_validate: Holding the way to set addition validate type for a
@@ -726,7 +724,6 @@ struct mt753x_info {
726724
int regnum);
727725
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
728726
int regnum, u16 val);
729-
int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
730727
int (*cpu_port_config)(struct dsa_switch *ds, int port);
731728
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
732729
struct phylink_config *config);

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