1515
1616#define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */
1717
18+ #define AD7616_CONFIGURATION_REGISTER 0x02
19+ #define AD7616_OS_MASK GENMASK(4, 2)
20+ #define AD7616_BURST_MODE BIT(6)
21+ #define AD7616_SEQEN_MODE BIT(5)
22+ #define AD7616_RANGE_CH_A_ADDR_OFF 0x04
23+ #define AD7616_RANGE_CH_B_ADDR_OFF 0x06
24+ /*
25+ * Range of channels from a group are stored in 2 registers.
26+ * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register.
27+ * For channels from second group(8-15) the order is the same, only with
28+ * an offset of 2 for register address.
29+ */
30+ #define AD7616_RANGE_CH_ADDR (ch ) ((ch) >> 2)
31+ /* The range of the channel is stored on 2 bits*/
32+ #define AD7616_RANGE_CH_MSK (ch ) (0b11 << (((ch) & 0b11) * 2))
33+ #define AD7616_RANGE_CH_MODE (ch , mode ) ((mode) << ((((ch) & 0b11)) * 2))
34+ static const struct iio_chan_spec ad7616_sw_channels [] = {
35+ IIO_CHAN_SOFT_TIMESTAMP (16 ),
36+ AD7616_CHANNEL (0 ),
37+ AD7616_CHANNEL (1 ),
38+ AD7616_CHANNEL (2 ),
39+ AD7616_CHANNEL (3 ),
40+ AD7616_CHANNEL (4 ),
41+ AD7616_CHANNEL (5 ),
42+ AD7616_CHANNEL (6 ),
43+ AD7616_CHANNEL (7 ),
44+ AD7616_CHANNEL (8 ),
45+ AD7616_CHANNEL (9 ),
46+ AD7616_CHANNEL (10 ),
47+ AD7616_CHANNEL (11 ),
48+ AD7616_CHANNEL (12 ),
49+ AD7616_CHANNEL (13 ),
50+ AD7616_CHANNEL (14 ),
51+ AD7616_CHANNEL (15 ),
52+ };
53+
54+ static u16 ad7616_spi_rd_wr_cmd (int addr , char isWriteOp )
55+ {
56+ /*
57+ * The address of register consist of one w/r bit
58+ * 6 bits of address followed by one reserved bit.
59+ */
60+ return ((addr & 0x7F ) << 1 ) | ((isWriteOp & 0x1 ) << 7 );
61+ }
62+
1863static int ad7606_spi_read_block (struct device * dev ,
1964 int count , void * buf )
2065{
@@ -35,17 +80,145 @@ static int ad7606_spi_read_block(struct device *dev,
3580 return 0 ;
3681}
3782
83+ static int ad7606_spi_reg_read (struct ad7606_state * st , unsigned int addr )
84+ {
85+ struct spi_device * spi = to_spi_device (st -> dev );
86+ struct spi_transfer t [] = {
87+ {
88+ .tx_buf = & st -> d16 [0 ],
89+ .len = 2 ,
90+ .cs_change = 0 ,
91+ }, {
92+ .rx_buf = & st -> d16 [1 ],
93+ .len = 2 ,
94+ },
95+ };
96+ int ret ;
97+
98+ st -> d16 [0 ] = cpu_to_be16 (st -> bops -> rd_wr_cmd (addr , 0 ) << 8 );
99+
100+ ret = spi_sync_transfer (spi , t , ARRAY_SIZE (t ));
101+ if (ret < 0 )
102+ return ret ;
103+
104+ return be16_to_cpu (st -> d16 [1 ]);
105+ }
106+
107+ static int ad7606_spi_reg_write (struct ad7606_state * st ,
108+ unsigned int addr ,
109+ unsigned int val )
110+ {
111+ struct spi_device * spi = to_spi_device (st -> dev );
112+
113+ st -> d16 [0 ] = cpu_to_be16 ((st -> bops -> rd_wr_cmd (addr , 1 ) << 8 ) |
114+ (val & 0x1FF ));
115+
116+ return spi_write (spi , & st -> d16 [0 ], sizeof (st -> d16 [0 ]));
117+ }
118+
119+ static int ad7606_spi_write_mask (struct ad7606_state * st ,
120+ unsigned int addr ,
121+ unsigned long mask ,
122+ unsigned int val )
123+ {
124+ int readval ;
125+
126+ readval = st -> bops -> reg_read (st , addr );
127+ if (readval < 0 )
128+ return readval ;
129+
130+ readval &= ~mask ;
131+ readval |= val ;
132+
133+ return st -> bops -> reg_write (st , addr , readval );
134+ }
135+
136+ static int ad7616_write_scale_sw (struct iio_dev * indio_dev , int ch , int val )
137+ {
138+ struct ad7606_state * st = iio_priv (indio_dev );
139+ unsigned int ch_addr , mode , ch_index ;
140+
141+
142+ /*
143+ * Ad7616 has 16 channels divided in group A and group B.
144+ * The range of channels from A are stored in registers with address 4
145+ * while channels from B are stored in register with address 6.
146+ * The last bit from channels determines if it is from group A or B
147+ * because the order of channels in iio is 0A, 0B, 1A, 1B...
148+ */
149+ ch_index = ch >> 1 ;
150+
151+ ch_addr = AD7616_RANGE_CH_ADDR (ch_index );
152+
153+ if ((ch & 0x1 ) == 0 ) /* channel A */
154+ ch_addr += AD7616_RANGE_CH_A_ADDR_OFF ;
155+ else /* channel B */
156+ ch_addr += AD7616_RANGE_CH_B_ADDR_OFF ;
157+
158+ /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */
159+ mode = AD7616_RANGE_CH_MODE (ch_index , ((val + 1 ) & 0b11 ));
160+ return st -> bops -> write_mask (st , ch_addr , AD7616_RANGE_CH_MSK (ch_index ),
161+ mode );
162+ }
163+
164+ static int ad7616_write_os_sw (struct iio_dev * indio_dev , int val )
165+ {
166+ struct ad7606_state * st = iio_priv (indio_dev );
167+
168+ return st -> bops -> write_mask (st , AD7616_CONFIGURATION_REGISTER ,
169+ AD7616_OS_MASK , val << 2 );
170+ }
171+
172+ static int ad7616_sw_mode_config (struct iio_dev * indio_dev )
173+ {
174+ struct ad7606_state * st = iio_priv (indio_dev );
175+
176+ /*
177+ * Scale can be configured individually for each channel
178+ * in software mode.
179+ */
180+ indio_dev -> channels = ad7616_sw_channels ;
181+
182+ st -> write_scale = ad7616_write_scale_sw ;
183+ st -> write_os = & ad7616_write_os_sw ;
184+
185+ /* Activate Burst mode and SEQEN MODE */
186+ return st -> bops -> write_mask (st ,
187+ AD7616_CONFIGURATION_REGISTER ,
188+ AD7616_BURST_MODE | AD7616_SEQEN_MODE ,
189+ AD7616_BURST_MODE | AD7616_SEQEN_MODE );
190+ }
191+
38192static const struct ad7606_bus_ops ad7606_spi_bops = {
39193 .read_block = ad7606_spi_read_block ,
40194};
41195
196+ static const struct ad7606_bus_ops ad7616_spi_bops = {
197+ .read_block = ad7606_spi_read_block ,
198+ .reg_read = ad7606_spi_reg_read ,
199+ .reg_write = ad7606_spi_reg_write ,
200+ .write_mask = ad7606_spi_write_mask ,
201+ .rd_wr_cmd = ad7616_spi_rd_wr_cmd ,
202+ .sw_mode_config = ad7616_sw_mode_config ,
203+ };
204+
42205static int ad7606_spi_probe (struct spi_device * spi )
43206{
44207 const struct spi_device_id * id = spi_get_device_id (spi );
208+ const struct ad7606_bus_ops * bops ;
209+
210+ switch (id -> driver_data ) {
211+ case ID_AD7616 :
212+ bops = & ad7616_spi_bops ;
213+ break ;
214+ default :
215+ bops = & ad7606_spi_bops ;
216+ break ;
217+ }
45218
46219 return ad7606_probe (& spi -> dev , spi -> irq , NULL ,
47220 id -> name , id -> driver_data ,
48- & ad7606_spi_bops );
221+ bops );
49222}
50223
51224static const struct spi_device_id ad7606_id_table [] = {
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