Warning: Method `[S.P.CoreLib]System.IO.BinaryReader..ctor(Stream,Encoding,bool)` will always throw because: [TEMPORARY EXCEPTION MESSAGE] InvalidProgramSpecific: Void System.IO.BinaryReader..ctor(System.IO.Stream, System.Text.Encoding, Boolean) ****** START compiling System.Boolean:TryParse(struct,byref):bool (MethodHash=cf443699) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: Jit invoked for ngen OPTIONS: Stack probing is DISABLED IL to import: IL_0000 00 nop IL_0001 72 00 2a 00 70 ldstr 0x70002A00 IL_0006 28 5d 0d 00 06 call 0x6000D5D IL_000b 0a stloc.0 IL_000c 06 ldloc.0 IL_000d 02 ldarg.0 IL_000e 28 52 0d 00 06 call 0x6000D52 IL_0013 0c stloc.2 IL_0014 08 ldloc.2 IL_0015 2c 08 brfalse.s 8 (IL_001f) IL_0017 00 nop IL_0018 03 ldarg.1 IL_0019 17 ldc.i4.1 IL_001a 52 stind.i1 IL_001b 17 ldc.i4.1 IL_001c 0d stloc.3 IL_001d 2b 59 br.s 89 (IL_0078) IL_001f 72 f4 29 00 70 ldstr 0x700029F4 IL_0024 28 5d 0d 00 06 call 0x6000D5D IL_0029 0b stloc.1 IL_002a 07 ldloc.1 IL_002b 02 ldarg.0 IL_002c 28 52 0d 00 06 call 0x6000D52 IL_0031 13 04 stloc.s 0x4 IL_0033 11 04 ldloc.s 0x4 IL_0035 2c 08 brfalse.s 8 (IL_003f) IL_0037 00 nop IL_0038 03 ldarg.1 IL_0039 16 ldc.i4.0 IL_003a 52 stind.i1 IL_003b 17 ldc.i4.1 IL_003c 0d stloc.3 IL_003d 2b 39 br.s 57 (IL_0078) IL_003f 02 ldarg.0 IL_0040 28 8c 08 00 06 call 0x600088C IL_0045 10 00 starg.s 0x0 IL_0047 06 ldloc.0 IL_0048 02 ldarg.0 IL_0049 28 52 0d 00 06 call 0x6000D52 IL_004e 13 05 stloc.s 0x5 IL_0050 11 05 ldloc.s 0x5 IL_0052 2c 08 brfalse.s 8 (IL_005c) IL_0054 00 nop IL_0055 03 ldarg.1 IL_0056 17 ldc.i4.1 IL_0057 52 stind.i1 IL_0058 17 ldc.i4.1 IL_0059 0d stloc.3 IL_005a 2b 1c br.s 28 (IL_0078) IL_005c 07 ldloc.1 IL_005d 02 ldarg.0 IL_005e 28 52 0d 00 06 call 0x6000D52 IL_0063 13 06 stloc.s 0x6 IL_0065 11 06 ldloc.s 0x6 IL_0067 2c 08 brfalse.s 8 (IL_0071) IL_0069 00 nop IL_006a 03 ldarg.1 IL_006b 16 ldc.i4.0 IL_006c 52 stind.i1 IL_006d 17 ldc.i4.1 IL_006e 0d stloc.3 IL_006f 2b 07 br.s 7 (IL_0078) IL_0071 03 ldarg.1 IL_0072 16 ldc.i4.0 IL_0073 52 stind.i1 IL_0074 16 ldc.i4.0 IL_0075 0d stloc.3 IL_0076 2b 00 br.s 0 (IL_0078) IL_0078 09 ldloc.3 IL_0079 2a ret Set preferred register for V00 to [rcx] Arg #0 passed in register(s) rcx Set preferred register for V01 to [rdx] Arg #1 passed in register(s) rdx ; Initial local variable assignments ; ; V00 arg0 struct (16) ; V01 arg1 byref ; V02 loc0 struct (16) ; V03 loc1 struct (16) ; V04 loc2 bool ; V05 loc3 bool ; V06 loc4 bool ; V07 loc5 bool ; V08 loc6 bool *************** In compInitDebuggingInfo() for System.Boolean:TryParse(struct,byref):bool getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 9 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 07Ah 1: 01h 01h V01 arg1 000h 07Ah 2: 02h 02h V02 loc0 000h 07Ah 3: 03h 03h V03 loc1 000h 07Ah 4: 04h 04h V04 loc2 000h 07Ah 5: 05h 05h V05 loc3 000h 07Ah 6: 06h 06h V06 loc4 000h 07Ah 7: 07h 07h V07 loc5 000h 07Ah 8: 08h 08h V08 loc6 000h 07Ah info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Boolean:TryParse(struct,byref):bool Jump targets: IL_001f IL_003f IL_005c IL_0071 IL_0078 multi New Basic Block BB01 [0000] created. BB01 [000..017) New Basic Block BB02 [0001] created. BB02 [017..01F) New Basic Block BB03 [0002] created. BB03 [01F..037) New Basic Block BB04 [0003] created. BB04 [037..03F) New Basic Block BB05 [0004] created. BB05 [03F..054) New Basic Block BB06 [0005] created. BB06 [054..05C) New Basic Block BB07 [0006] created. BB07 [05C..069) New Basic Block BB08 [0007] created. BB08 [069..071) New Basic Block BB09 [0008] created. BB09 [071..078) New Basic Block BB10 [0009] created. BB10 [078..07A) INLINER: during 'prejit' result 'failed this callee' reason 'too many il bytes' for 'n/a' calling 'System.Boolean:TryParse(struct,byref):bool' INLINER: Marking System.Boolean:TryParse(struct,byref):bool as NOINLINE because of too many il bytes INLINER: during 'prejit' result 'failed this callee' reason 'too many il bytes' IL Code Size,Instr 122, 70, Basic Block count 10, Local Variable Num,Ref count 9, 31 for method System.Boolean:TryParse(struct,byref):bool OPTIONS: opts.MinOpts() == false Basic block list for 'System.Boolean:TryParse(struct,byref):bool' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) BB02 [0001] 1 1 [017..01F)-> BB10 (always) BB03 [0002] 1 1 [01F..037)-> BB05 ( cond ) BB04 [0003] 1 1 [037..03F)-> BB10 (always) BB05 [0004] 1 1 [03F..054)-> BB07 ( cond ) BB06 [0005] 1 1 [054..05C)-> BB10 (always) BB07 [0006] 1 1 [05C..069)-> BB09 ( cond ) BB08 [0007] 1 1 [069..071)-> BB10 (always) BB09 [0008] 1 1 [071..078)-> BB10 (always) BB10 [0009] 5 1 [078..07A) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.Boolean:TryParse(struct,byref):bool impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldstr 70002A00 [ 1] 6 (0x006) call 06000D5D In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 [000004] ------------ * STMT void (IL 0x001... ???) [000002] I-C-G------- \--* CALL struct System.MemoryExtensions.AsSpan (exactContextHnd=0x0000000000423089) [000001] ------------ arg0 \--* CNS_STR ref [ 1] 11 (0x00b) stloc.0 [000009] ------------ * STMT void (IL ???... ???) [000005] --C--------- \--* RET_EXPR void (inl return from call [000002]) [ 0] 12 (0x00c) ldloc.0 [ 1] 13 (0x00d) ldarg.0 [ 2] 14 (0x00e) call 06000D52 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000011] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000014] x----------- * OBJ(16) struct [000013] L----------- \--* ADDR byref [000011] ------------ \--* LCL_VAR struct V00 arg0 Calling impNormStructVal on: [000010] ------------ * LCL_VAR struct V02 loc0 resulting tree: [000017] x----------- * OBJ(16) struct [000016] L----------- \--* ADDR byref [000010] ------------ \--* LCL_VAR struct V02 loc0 [000019] ------------ * STMT void (IL 0x00C... ???) [000012] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000017] x----------- arg0 +--* OBJ(16) struct [000016] L----------- | \--* ADDR byref [000010] ------------ | \--* LCL_VAR struct V02 loc0 [000014] x----------- arg1 \--* OBJ(16) struct [000013] L----------- \--* ADDR byref [000011] ------------ \--* LCL_VAR struct V00 arg0 [ 1] 19 (0x013) stloc.2 [000024] ------------ * STMT void (IL ???... ???) [000021] --C--------- | /--* CAST int <- bool <- int [000020] --C--------- | | \--* RET_EXPR int (inl return from call [000012]) [000023] -AC--------- \--* ASG int [000022] D------N---- \--* LCL_VAR int V04 loc2 [ 0] 20 (0x014) ldloc.2 [ 1] 21 (0x015) brfalse.s [000029] ------------ * STMT void (IL 0x014... ???) [000028] ------------ \--* JTRUE void [000026] ------------ | /--* CNS_INT int 0 [000027] ------------ \--* EQ int [000025] ------------ \--* LCL_VAR int V04 loc2 impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=031) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 31 (0x01f) ldstr 700029F4 [ 1] 36 (0x024) call 06000D5D In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 [000034] ------------ * STMT void (IL 0x01F... ???) [000032] I-C-G------- \--* CALL struct System.MemoryExtensions.AsSpan (exactContextHnd=0x0000000000423089) [000031] ------------ arg0 \--* CNS_STR ref [ 1] 41 (0x029) stloc.1 [000039] ------------ * STMT void (IL ???... ???) [000035] --C--------- \--* RET_EXPR void (inl return from call [000032]) [ 0] 42 (0x02a) ldloc.1 [ 1] 43 (0x02b) ldarg.0 [ 2] 44 (0x02c) call 06000D52 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000041] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000044] x----------- * OBJ(16) struct [000043] L----------- \--* ADDR byref [000041] ------------ \--* LCL_VAR struct V00 arg0 Calling impNormStructVal on: [000040] ------------ * LCL_VAR struct V03 loc1 resulting tree: [000047] x----------- * OBJ(16) struct [000046] L----------- \--* ADDR byref [000040] ------------ \--* LCL_VAR struct V03 loc1 [000049] ------------ * STMT void (IL 0x02A... ???) [000042] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000047] x----------- arg0 +--* OBJ(16) struct [000046] L----------- | \--* ADDR byref [000040] ------------ | \--* LCL_VAR struct V03 loc1 [000044] x----------- arg1 \--* OBJ(16) struct [000043] L----------- \--* ADDR byref [000041] ------------ \--* LCL_VAR struct V00 arg0 [ 1] 49 (0x031) stloc.s 4 [000054] ------------ * STMT void (IL ???... ???) [000051] --C--------- | /--* CAST int <- bool <- int [000050] --C--------- | | \--* RET_EXPR int (inl return from call [000042]) [000053] -AC--------- \--* ASG int [000052] D------N---- \--* LCL_VAR int V06 loc4 [ 0] 51 (0x033) ldloc.s 4 [ 1] 53 (0x035) brfalse.s [000059] ------------ * STMT void (IL 0x033... ???) [000058] ------------ \--* JTRUE void [000056] ------------ | /--* CNS_INT int 0 [000057] ------------ \--* EQ int [000055] ------------ \--* LCL_VAR int V06 loc4 impImportBlockPending for BB04 impImportBlockPending for BB05 Importing BB05 (PC=063) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 63 (0x03f) ldarg.0 [ 1] 64 (0x040) call 0600088C In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000061] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000064] x----------- * OBJ(16) struct [000063] L----------- \--* ADDR byref [000061] ------------ \--* LCL_VAR struct V00 arg0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.Boolean:TrimWhiteSpaceAndNull(struct):struct' INLINER: Marking System.Boolean:TrimWhiteSpaceAndNull(struct):struct as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 69 (0x045) starg.s 0 [000069] ------------ * STMT void (IL 0x03F... ???) [000062] S-C-G------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull [000067] L----------- arg0 +--* ADDR byref [000066] ------------ | \--* LCL_VAR struct V00 arg0 [000064] x----------- arg1 \--* OBJ(16) struct [000063] L----------- \--* ADDR byref [000061] ------------ \--* LCL_VAR struct V00 arg0 [ 0] 71 (0x047) ldloc.0 [ 1] 72 (0x048) ldarg.0 [ 2] 73 (0x049) call 06000D52 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000071] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000074] x----------- * OBJ(16) struct [000073] L----------- \--* ADDR byref [000071] ------------ \--* LCL_VAR struct V00 arg0 Calling impNormStructVal on: [000070] ------------ * LCL_VAR struct V02 loc0 resulting tree: [000077] x----------- * OBJ(16) struct [000076] L----------- \--* ADDR byref [000070] ------------ \--* LCL_VAR struct V02 loc0 [000079] ------------ * STMT void (IL 0x047... ???) [000072] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000077] x----------- arg0 +--* OBJ(16) struct [000076] L----------- | \--* ADDR byref [000070] ------------ | \--* LCL_VAR struct V02 loc0 [000074] x----------- arg1 \--* OBJ(16) struct [000073] L----------- \--* ADDR byref [000071] ------------ \--* LCL_VAR struct V00 arg0 [ 1] 78 (0x04e) stloc.s 5 [000084] ------------ * STMT void (IL ???... ???) [000081] --C--------- | /--* CAST int <- bool <- int [000080] --C--------- | | \--* RET_EXPR int (inl return from call [000072]) [000083] -AC--------- \--* ASG int [000082] D------N---- \--* LCL_VAR int V07 loc5 [ 0] 80 (0x050) ldloc.s 5 [ 1] 82 (0x052) brfalse.s [000089] ------------ * STMT void (IL 0x050... ???) [000088] ------------ \--* JTRUE void [000086] ------------ | /--* CNS_INT int 0 [000087] ------------ \--* EQ int [000085] ------------ \--* LCL_VAR int V07 loc5 impImportBlockPending for BB06 impImportBlockPending for BB07 Importing BB07 (PC=092) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 92 (0x05c) ldloc.1 [ 1] 93 (0x05d) ldarg.0 [ 2] 94 (0x05e) call 06000D52 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000092] ------------ * LCL_VAR struct V00 arg0 resulting tree: [000095] x----------- * OBJ(16) struct [000094] L----------- \--* ADDR byref [000092] ------------ \--* LCL_VAR struct V00 arg0 Calling impNormStructVal on: [000091] ------------ * LCL_VAR struct V03 loc1 resulting tree: [000098] x----------- * OBJ(16) struct [000097] L----------- \--* ADDR byref [000091] ------------ \--* LCL_VAR struct V03 loc1 [000100] ------------ * STMT void (IL 0x05C... ???) [000093] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000098] x----------- arg0 +--* OBJ(16) struct [000097] L----------- | \--* ADDR byref [000091] ------------ | \--* LCL_VAR struct V03 loc1 [000095] x----------- arg1 \--* OBJ(16) struct [000094] L----------- \--* ADDR byref [000092] ------------ \--* LCL_VAR struct V00 arg0 [ 1] 99 (0x063) stloc.s 6 [000105] ------------ * STMT void (IL ???... ???) [000102] --C--------- | /--* CAST int <- bool <- int [000101] --C--------- | | \--* RET_EXPR int (inl return from call [000093]) [000104] -AC--------- \--* ASG int [000103] D------N---- \--* LCL_VAR int V08 loc6 [ 0] 101 (0x065) ldloc.s 6 [ 1] 103 (0x067) brfalse.s [000110] ------------ * STMT void (IL 0x065... ???) [000109] ------------ \--* JTRUE void [000107] ------------ | /--* CNS_INT int 0 [000108] ------------ \--* EQ int [000106] ------------ \--* LCL_VAR int V08 loc6 impImportBlockPending for BB08 impImportBlockPending for BB09 Importing BB09 (PC=113) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 113 (0x071) ldarg.1 [ 1] 114 (0x072) ldc.i4.0 0 [ 2] 115 (0x073) stind.i1 [000116] ------------ * STMT void (IL 0x071... ???) [000113] ------------ | /--* CNS_INT int 0 [000115] -A-XG------- \--* ASG byte [000114] *------N---- \--* IND byte [000112] ------------ \--* LCL_VAR byref V01 arg1 [ 0] 116 (0x074) ldc.i4.0 0 [ 1] 117 (0x075) stloc.3 [000120] ------------ * STMT void (IL 0x074... ???) [000117] ------------ | /--* CNS_INT int 0 [000119] -A---------- \--* ASG int [000118] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 118 (0x076) br.s impImportBlockPending for BB10 Importing BB10 (PC=120) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 120 (0x078) ldloc.3 [ 1] 121 (0x079) ret [000124] ------------ * STMT void (IL 0x078... ???) [000123] ------------ \--* RETURN int [000122] ------------ \--* LCL_VAR int V05 loc3 Importing BB08 (PC=105) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 105 (0x069) nop [ 0] 106 (0x06a) ldarg.1 [ 1] 107 (0x06b) ldc.i4.0 0 [ 2] 108 (0x06c) stind.i1 [000130] ------------ * STMT void (IL 0x06A... ???) [000127] ------------ | /--* CNS_INT int 0 [000129] -A-XG------- \--* ASG byte [000128] *------N---- \--* IND byte [000126] ------------ \--* LCL_VAR byref V01 arg1 [ 0] 109 (0x06d) ldc.i4.1 1 [ 1] 110 (0x06e) stloc.3 [000134] ------------ * STMT void (IL 0x06D... ???) [000131] ------------ | /--* CNS_INT int 1 [000133] -A---------- \--* ASG int [000132] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 111 (0x06f) br.s impImportBlockPending for BB10 Importing BB06 (PC=084) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 84 (0x054) nop [ 0] 85 (0x055) ldarg.1 [ 1] 86 (0x056) ldc.i4.1 1 [ 2] 87 (0x057) stind.i1 [000140] ------------ * STMT void (IL 0x055... ???) [000137] ------------ | /--* CNS_INT int 1 [000139] -A-XG------- \--* ASG byte [000138] *------N---- \--* IND byte [000136] ------------ \--* LCL_VAR byref V01 arg1 [ 0] 88 (0x058) ldc.i4.1 1 [ 1] 89 (0x059) stloc.3 [000144] ------------ * STMT void (IL 0x058... ???) [000141] ------------ | /--* CNS_INT int 1 [000143] -A---------- \--* ASG int [000142] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 90 (0x05a) br.s impImportBlockPending for BB10 Importing BB04 (PC=055) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 55 (0x037) nop [ 0] 56 (0x038) ldarg.1 [ 1] 57 (0x039) ldc.i4.0 0 [ 2] 58 (0x03a) stind.i1 [000150] ------------ * STMT void (IL 0x038... ???) [000147] ------------ | /--* CNS_INT int 0 [000149] -A-XG------- \--* ASG byte [000148] *------N---- \--* IND byte [000146] ------------ \--* LCL_VAR byref V01 arg1 [ 0] 59 (0x03b) ldc.i4.1 1 [ 1] 60 (0x03c) stloc.3 [000154] ------------ * STMT void (IL 0x03B... ???) [000151] ------------ | /--* CNS_INT int 1 [000153] -A---------- \--* ASG int [000152] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 61 (0x03d) br.s impImportBlockPending for BB10 Importing BB02 (PC=023) of 'System.Boolean:TryParse(struct,byref):bool' [ 0] 23 (0x017) nop [ 0] 24 (0x018) ldarg.1 [ 1] 25 (0x019) ldc.i4.1 1 [ 2] 26 (0x01a) stind.i1 [000160] ------------ * STMT void (IL 0x018... ???) [000157] ------------ | /--* CNS_INT int 1 [000159] -A-XG------- \--* ASG byte [000158] *------N---- \--* IND byte [000156] ------------ \--* LCL_VAR byref V01 arg1 [ 0] 27 (0x01b) ldc.i4.1 1 [ 1] 28 (0x01c) stloc.3 [000164] ------------ * STMT void (IL 0x01B... ???) [000161] ------------ | /--* CNS_INT int 1 [000163] -A---------- \--* ASG int [000162] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 29 (0x01d) br.s impImportBlockPending for BB10 New BlockSet epoch 1, # of blocks (including unused BB00): 11, bitset array size: 1 (short) *************** In fgMorph() *************** In fgDebugCheckBBlist *************** In fgInline() Expanding INLINE_CANDIDATE in statement [000004] in BB01: [000004] ------------ * STMT void (IL 0x001...0x00B) [000002] I-C-G------- \--* CALL void System.MemoryExtensions.AsSpan (exactContextHnd=0x0000000000423089) [000007] L----------- arg0 +--* ADDR byref [000006] ------------ | \--* LCL_VAR struct V02 loc0 [000001] ------------ arg1 \--* CNS_STR ref Argument #0: is a constant [000001] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:AsSpan(ref):struct set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:AsSpan(ref):struct : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 14 ldnull IL_0003 fe 01 ceq IL_0005 0a stloc.0 IL_0006 06 ldloc.0 IL_0007 2c 0c brfalse.s 12 (IL_0015) IL_0009 12 01 ldloca.s 0x1 IL_000b fe 15 c1 00 00 1b initobj 0x1B0000C1 IL_0011 07 ldloc.1 IL_0012 0c stloc.2 IL_0013 2b 14 br.s 20 (IL_0029) IL_0015 02 ldarg.0 IL_0016 6f 7e 03 00 06 callvirt 0x600037E IL_001b 02 ldarg.0 IL_001c 6f 5d 03 00 06 callvirt 0x600035D IL_0021 73 77 00 00 0a newobj 0xA000077 IL_0026 0c stloc.2 IL_0027 2b 00 br.s 0 (IL_0029) IL_0029 08 ldloc.2 IL_002a 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:AsSpan(ref):struct is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:AsSpan(ref):struct Jump targets: IL_0015 IL_0029 New Basic Block BB11 [0010] created. BB11 [000..009) New Basic Block BB12 [0011] created. BB12 [009..015) New Basic Block BB13 [0012] created. BB13 [015..029) New Basic Block BB14 [0013] created. BB14 [029..02B) Basic block list for 'System.MemoryExtensions:AsSpan(ref):struct' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB11 [0010] 1 1 [000..009)-> BB13 ( cond ) BB12 [0011] 1 1 [009..015)-> BB14 (always) BB13 [0012] 1 1 [015..029) BB14 [0013] 2 1 [029..02B) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:AsSpan(ref):struct impImportBlockPending for BB11 Importing BB11 (PC=000) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldnull [ 2] 3 (0x003) ceq [ 1] 5 (0x005) stloc.0 lvaGrabTemp returning 9 (V09 tmp0) (a long lifetime temp) called for Inline stloc first use temp. [000171] ------------ * STMT void [000167] ------------ | /--* CNS_INT ref null [000168] ------------ | /--* EQ int [000166] ------------ | | \--* CNS_STR ref [000170] -A---------- \--* ASG bool [000169] D------N---- \--* LCL_VAR bool V09 tmp0 [ 0] 6 (0x006) ldloc.0 [ 1] 7 (0x007) brfalse.s [000176] ------------ * STMT void [000175] ------------ \--* JTRUE void [000173] ------------ | /--* CNS_INT int 0 [000174] ------------ \--* EQ int [000172] ------------ \--* LCL_VAR int V09 tmp0 impImportBlockPending for BB12 impImportBlockPending for BB13 Importing BB13 (PC=021) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) callvirt 0600037E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is byref, structSize is 0 [000180] ------------ * STMT void [000179] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000178] ------------ this in rcx \--* CNS_STR ref [ 1] 27 (0x01b) ldarg.0 [ 2] 28 (0x01c) callvirt 0600035D In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 10 (V10 tmp1) called for impAppendStmt. [000187] ------------ * STMT void [000181] --C--------- | /--* RET_EXPR byref (inl return from call [000179]) [000186] -AC--------- \--* ASG byref [000185] D------N---- \--* LCL_VAR byref V10 tmp1 [000184] ------------ * STMT void [000183] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000182] ------------ this in rcx \--* CNS_STR ref [ 2] 33 (0x021) newobj lvaGrabTemp returning 11 (V11 tmp2) called for NewObj constructor temp. [000193] ------------ * STMT void [000191] ------------ | /--* CNS_INT int 0 [000192] IA------R--- \--* ASG struct (init) [000190] D------N---- \--* LCL_VAR struct V11 tmp2 0A000077 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000199] ------------ * STMT void [000196] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000195] L----------- this in rcx +--* ADDR byref [000194] ------------ | \--* LCL_VAR struct V11 tmp2 [000188] ------------ arg1 +--* LCL_VAR byref V10 tmp1 [000189] --C--------- arg2 \--* RET_EXPR int (inl return from call [000183]) [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 12 (V12 tmp3) (a long lifetime temp) called for Inline stloc first use temp. [000204] ------------ * STMT void [000200] ------------ | /--* LCL_VAR struct V11 tmp2 [000203] -A------R--- \--* ASG struct (copy) [000201] D----------- \--* LCL_VAR struct V12 tmp3 [ 0] 39 (0x027) br.s impImportBlockPending for BB14 Importing BB14 (PC=041) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 41 (0x029) ldloc.2 [ 1] 42 (0x02a) ret Inlinee Return expression (before normalization) => [000206] ------------ * LCL_VAR struct V12 tmp3 Importing BB12 (PC=009) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 9 (0x009) ldloca.s 1 lvaGrabTemp returning 13 (V13 tmp4) (a long lifetime temp) called for Inline ldloca(s) first use temp. [ 1] 11 (0x00b) initobj 1B0000C1 [000215] ------------ * STMT void [000213] ------------ | /--* CNS_INT int 0 [000214] IA------R--- \--* ASG struct (init) [000211] D------N---- \--* LCL_VAR struct V13 tmp4 [ 0] 17 (0x011) ldloc.1 [ 1] 18 (0x012) stloc.2 [000220] ------------ * STMT void [000216] ------------ | /--* LCL_VAR struct V13 tmp4 [000219] -A------R--- \--* ASG struct (copy) [000217] D----------- \--* LCL_VAR struct V12 tmp3 [ 0] 19 (0x013) br.s impImportBlockPending for BB14 ----------- Statements (and blocks) added due to the inlining of call [000002] ----------- Arguments setup: Zero init inlinee locals: [000224] ------------ * STMT void (IL 0x001... ???) [000221] ------------ | /--* CNS_INT int 0 [000223] -A---------- \--* ASG bool [000222] D------N---- \--* LCL_VAR bool V09 tmp0 [000224] ------------ * STMT void (IL 0x001... ???) [000221] ------------ | /--* CNS_INT int 0 [000223] -A---------- \--* ASG bool [000222] D------N---- \--* LCL_VAR bool V09 tmp0 [000224] ------------ * STMT void (IL 0x001... ???) [000221] ------------ | /--* CNS_INT int 0 [000223] -A---------- \--* ASG bool [000222] D------N---- \--* LCL_VAR bool V09 tmp0 Inlinee method body:New Basic Block BB15 [0014] created. Convert bbJumpKind of BB14 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB11 [0010] 1 1 [001..002)-> BB13 ( cond ) i BB12 [0011] 1 0.50 [001..002)-> BB14 (always) i BB13 [0012] 1 0.50 [001..002) i BB14 [0013] 2 1 [001..002) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB11 [001..002) -> BB13 (cond), preds={} succs={BB12,BB13} ***** BB11, stmt 1 [000171] ------------ * STMT void (IL 0x001... ???) [000167] ------------ | /--* CNS_INT ref null [000168] ------------ | /--* EQ int [000166] ------------ | | \--* CNS_STR ref [000170] -A---------- \--* ASG bool [000169] D------N---- \--* LCL_VAR bool V09 tmp0 ***** BB11, stmt 2 [000176] ------------ * STMT void (IL 0x001... ???) [000175] ------------ \--* JTRUE void [000173] ------------ | /--* CNS_INT int 0 [000174] ------------ \--* EQ int [000172] ------------ \--* LCL_VAR int V09 tmp0 ------------ BB12 [001..002) -> BB14 (always), preds={} succs={BB14} ***** BB12, stmt 3 [000215] ------------ * STMT void (IL 0x001... ???) [000213] ------------ | /--* CNS_INT int 0 [000214] IA------R--- \--* ASG struct (init) [000211] D------N---- \--* LCL_VAR struct V13 tmp4 ***** BB12, stmt 4 [000220] ------------ * STMT void (IL 0x001... ???) [000216] ------------ | /--* LCL_VAR struct V13 tmp4 [000219] -A------R--- \--* ASG struct (copy) [000217] D----------- \--* LCL_VAR struct V12 tmp3 ------------ BB13 [001..002), preds={} succs={BB14} ***** BB13, stmt 5 [000180] ------------ * STMT void (IL 0x001... ???) [000179] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000178] ------------ this in rcx \--* CNS_STR ref ***** BB13, stmt 6 [000187] ------------ * STMT void (IL 0x001... ???) [000181] --C--------- | /--* RET_EXPR byref (inl return from call [000179]) [000186] -AC--------- \--* ASG byref [000185] D------N---- \--* LCL_VAR byref V10 tmp1 ***** BB13, stmt 7 [000184] ------------ * STMT void (IL 0x001... ???) [000183] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000182] ------------ this in rcx \--* CNS_STR ref ***** BB13, stmt 8 [000193] ------------ * STMT void (IL 0x001... ???) [000191] ------------ | /--* CNS_INT int 0 [000192] IA------R--- \--* ASG struct (init) [000190] D------N---- \--* LCL_VAR struct V11 tmp2 ***** BB13, stmt 9 [000199] ------------ * STMT void (IL 0x001... ???) [000196] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000195] L----------- this in rcx +--* ADDR byref [000194] ------------ | \--* LCL_VAR struct V11 tmp2 [000188] ------------ arg1 +--* LCL_VAR byref V10 tmp1 [000189] --C--------- arg2 \--* RET_EXPR int (inl return from call [000183]) ***** BB13, stmt 10 [000204] ------------ * STMT void (IL 0x001... ???) [000200] ------------ | /--* LCL_VAR struct V11 tmp2 [000203] -A------R--- \--* ASG struct (copy) [000201] D----------- \--* LCL_VAR struct V12 tmp3 ------------ BB14 [001..002), preds={} succs={BB15} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000002] is [000206] ------------ /--* LCL_VAR struct V12 tmp3 [000209] -A------R--- * ASG struct (copy) [000208] D----------- \--* LCL_VAR struct V02 loc0 Successfully inlined System.MemoryExtensions:AsSpan(ref):struct (43 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:AsSpan(ref):struct' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000180] in BB13: [000180] ------------ * STMT void (IL 0x001... ???) [000179] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000178] ------------ this in rcx \--* CNS_STR ref thisArg: is a constant [000178] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.String:GetRawStringData():byref:this set to 0x0000000000420891: Invoking compiler for the inlinee method System.String:GetRawStringData():byref:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 12 01 00 04 ldflda 0x4000112 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.String:GetRawStringData():byref:this is 0x0000000000420891. *************** In fgFindBasicBlocks() for System.String:GetRawStringData():byref:this Jump targets: none New Basic Block BB16 [0015] created. BB16 [000..007) Basic block list for 'System.String:GetRawStringData():byref:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB16 [0015] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.String:GetRawStringData():byref:this impImportBlockPending for BB16 Importing BB16 (PC=000) of 'System.String:GetRawStringData():byref:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 04000112 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000229] ---XG------- * ADDR byref [000228] ---XG------- \--* FIELD ushort _firstChar [000227] ------------ \--* CNS_STR ref Inlinee Return expression (after normalization) => [000229] ---XG------- * ADDR byref [000228] ---XG------- \--* FIELD ushort _firstChar [000227] ------------ \--* CNS_STR ref ----------- Statements (and blocks) added due to the inlining of call [000179] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000179] is [000229] ---XG------- * ADDR byref [000228] ---XG------- \--* FIELD ushort _firstChar [000227] ------------ \--* CNS_STR ref Successfully inlined System.String:GetRawStringData():byref:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.String:GetRawStringData():byref:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000181] with [000229] [000181] --C--------- * RET_EXPR byref (inl return from call [000229]) Inserting the inline return expression [000229] ---XG------- * ADDR byref [000228] ---XG------- \--* FIELD ushort _firstChar [000227] ------------ \--* CNS_STR ref Expanding INLINE_CANDIDATE in statement [000184] in BB13: [000184] ------------ * STMT void (IL 0x001... ???) [000183] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000182] ------------ this in rcx \--* CNS_STR ref thisArg: is a constant [000182] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.String:get_Length():int:this set to 0x0000000000420891: Invoking compiler for the inlinee method System.String:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 11 01 00 04 ldfld 0x4000111 IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.String:get_Length():int:this is 0x0000000000420891. *************** In fgFindBasicBlocks() for System.String:get_Length():int:this Jump targets: none New Basic Block BB17 [0016] created. BB17 [000..00C) Basic block list for 'System.String:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB17 [0016] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.String:get_Length():int:this impImportBlockPending for BB17 Importing BB17 (PC=000) of 'System.String:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 04000111 [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 14 (V14 tmp5) (a long lifetime temp) called for Inline stloc first use temp. [000239] ------------ * STMT void [000236] ---XG------- | /--* FIELD int _stringLength [000235] ------------ | | \--* CNS_STR ref [000238] -A-XG------- \--* ASG int [000237] D------N---- \--* LCL_VAR int V14 tmp5 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000240] ------------ * LCL_VAR int V14 tmp5 Inlinee Return expression (after normalization) => [000240] ------------ * LCL_VAR int V14 tmp5 ----------- Statements (and blocks) added due to the inlining of call [000183] ----------- Arguments setup: Zero init inlinee locals: [000247] ------------ * STMT void (IL 0x001... ???) [000244] ------------ | /--* CNS_INT int 0 [000246] -A---------- \--* ASG int [000245] D------N---- \--* LCL_VAR int V14 tmp5 Inlinee method body: [000239] ------------ * STMT void (IL 0x001... ???) [000236] ---XG------- | /--* FIELD int _stringLength [000235] ------------ | | \--* CNS_STR ref [000238] -A-XG------- \--* ASG int [000237] D------N---- \--* LCL_VAR int V14 tmp5 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000183] is [000240] ------------ * LCL_VAR int V14 tmp5 Successfully inlined System.String:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.String:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement [000199] in BB13: [000199] ------------ * STMT void (IL 0x001... ???) [000196] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000195] L----------- this in rcx +--* ADDR byref [000194] ------------ | \--* LCL_VAR struct V11 tmp2 [000188] ------------ arg1 +--* LCL_VAR byref V10 tmp1 [000189] --C--------- arg2 \--* RET_EXPR int (inl return from call [000240]) thisArg: is a constant is byref to a struct local [000195] L----------- * ADDR byref [000194] ------------ \--* LCL_VAR struct V11 tmp2 Argument #1: is a local var [000188] ------------ * LCL_VAR byref V10 tmp1 Argument #2: is a local var [000240] ------------ * LCL_VAR int V14 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:.ctor(byref,int):this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:.ctor(byref,int):this : IL to import: IL_0000 00 nop IL_0001 04 ldarg.2 IL_0002 16 ldc.i4.0 IL_0003 fe 04 clt IL_0005 16 ldc.i4.0 IL_0006 fe 01 ceq IL_0008 28 c6 24 00 06 call 0x60024C6 IL_000d 00 nop IL_000e 02 ldarg.0 IL_000f 03 ldarg.1 IL_0010 73 30 01 00 0a newobj 0xA000130 IL_0015 7d 31 01 00 0a stfld 0xA000131 IL_001a 02 ldarg.0 IL_001b 04 ldarg.2 IL_001c 7d 2b 01 00 0a stfld 0xA00012B IL_0021 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:.ctor(byref,int):this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:.ctor(byref,int):this Jump targets: none New Basic Block BB18 [0017] created. BB18 [000..022) Basic block list for 'System.ReadOnlySpan`1:.ctor(byref,int):this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB18 [0017] 1 1 [000..022) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:.ctor(byref,int):this impImportBlockPending for BB18 Importing BB18 (PC=000) of 'System.ReadOnlySpan`1:.ctor(byref,int):this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.2 [ 1] 2 (0x002) ldc.i4.0 0 [ 2] 3 (0x003) clt [ 1] 5 (0x005) ldc.i4.0 0 [ 2] 6 (0x006) ceq [ 1] 8 (0x008) call 060024C6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000256] ------------ * STMT void [000254] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000252] ------------ | /--* CNS_INT int 0 [000253] ------------ arg0 \--* EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 [ 0] 13 (0x00d) nop [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldarg.1 [ 2] 16 (0x010) newobj lvaGrabTemp returning 15 (V15 tmp6) called for NewObj constructor temp. [000262] ------------ * STMT void [000260] ------------ | /--* CNS_INT int 0 [000261] IA------R--- \--* ASG struct (init) [000259] D------N---- \--* LCL_VAR struct V15 tmp6 0A000130 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000268] ------------ * STMT void [000188] ------------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---------- \--* ASG byref [000265] -------N---- \--* FIELD byref _value [000264] L----------- \--* ADDR byref [000263] ------------ \--* LCL_VAR struct V15 tmp6 [ 2] 21 (0x015) stfld 0A000131 [000273] ------------ * STMT void [000267] ------------ | /--* LCL_VAR struct V15 tmp6 [000272] -A------R--- \--* ASG struct (copy) [000271] ------------ \--* OBJ(8) struct [000270] ------------ \--* ADDR byref [000269] ------------ \--* FIELD struct _pointer [000257] L----------- \--* ADDR byref [000258] ------------ \--* LCL_VAR struct V11 tmp2 [ 0] 26 (0x01a) ldarg.0 [ 1] 27 (0x01b) ldarg.2 [ 2] 28 (0x01c) stfld 0A00012B [000279] ------------ * STMT void [000276] ------------ | /--* LCL_VAR int V14 tmp5 [000278] -A---------- \--* ASG int [000277] -------N---- \--* FIELD int _length [000274] L----------- \--* ADDR byref [000275] ------------ \--* LCL_VAR struct V11 tmp2 [ 0] 33 (0x021) ret ----------- Statements (and blocks) added due to the inlining of call [000196] ----------- Arguments setup: Inlinee method body: [000256] ------------ * STMT void (IL 0x001... ???) [000254] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000252] ------------ | /--* CNS_INT int 0 [000253] ------------ arg0 \--* EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 [000262] ------------ * STMT void (IL 0x001... ???) [000260] ------------ | /--* CNS_INT int 0 [000261] IA------R--- \--* ASG struct (init) [000259] D------N---- \--* LCL_VAR struct V15 tmp6 [000268] ------------ * STMT void (IL 0x001... ???) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---------- \--* ASG byref [000265] -------N---- \--* FIELD byref _value [000264] L----------- \--* ADDR byref [000263] ------------ \--* LCL_VAR struct V15 tmp6 [000273] ------------ * STMT void (IL 0x001... ???) [000267] ------------ | /--* LCL_VAR struct V15 tmp6 [000272] -A------R--- \--* ASG struct (copy) [000271] ------------ \--* OBJ(8) struct [000270] ------------ \--* ADDR byref [000269] ------------ \--* FIELD struct _pointer [000257] L----------- \--* ADDR byref [000258] ------------ \--* LCL_VAR struct V11 tmp2 [000279] ------------ * STMT void (IL 0x001... ???) [000276] ------------ | /--* LCL_VAR int V14 tmp5 [000278] -A---------- \--* ASG int [000277] -------N---- \--* FIELD int _length [000274] L----------- \--* ADDR byref [000275] ------------ \--* LCL_VAR struct V11 tmp2 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1:.ctor(byref,int):this (34 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:.ctor(byref,int):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000256] in BB13: [000256] ------------ * STMT void (IL 0x001... ???) [000254] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000252] ------------ | /--* CNS_INT int 0 [000253] ------------ arg0 \--* EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 Argument #0: [000252] ------------ /--* CNS_INT int 0 [000253] ------------ * EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x0000000000422319: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7e 13 01 00 04 ldsfld 0x4000113 IL_0007 7e 13 01 00 04 ldsfld 0x4000113 IL_000c 28 c8 24 00 06 call 0x60024C8 IL_0011 00 nop IL_0012 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x0000000000422319. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 65 : state 2 [ noshow ] weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 65 : state 2 [ noshow ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=556 callsiteNativeSizeEstimate=85 benefit multiplier=1.3 threshold=110 Native estimate for function size exceeds threshold for inlining 55.6 > 11 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000005] with [000209] [000005] --C--------- * RET_EXPR void (inl return from call [000209]) Inserting the inline return expression [000206] ------------ /--* LCL_VAR struct V12 tmp3 [000209] -A------R--- * ASG struct (copy) [000208] D----------- \--* LCL_VAR struct V02 loc0 Expanding INLINE_CANDIDATE in statement [000019] in BB15: [000019] ------------ * STMT void (IL 0x00C...0x013) [000012] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000017] x----------- arg0 +--* OBJ(16) struct [000016] L----------- | \--* ADDR byref [000010] ------------ | \--* LCL_VAR struct V02 loc0 [000014] x----------- arg1 \--* OBJ(16) struct [000013] L----------- \--* ADDR byref [000011] ------------ \--* LCL_VAR struct V00 arg0 Argument #0: [000017] x----------- * OBJ(16) struct [000016] L----------- \--* ADDR byref [000010] ------------ \--* LCL_VAR struct V02 loc0 Argument #1: [000014] x----------- * OBJ(16) struct [000013] L----------- \--* ADDR byref [000011] ------------ \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool : IL to import: IL_0000 00 nop IL_0001 0f 00 ldarga.s 0x0 IL_0003 28 55 00 00 0a call 0xA000055 IL_0008 0f 01 ldarga.s 0x1 IL_000a 28 55 00 00 0a call 0xA000055 IL_000f fe 01 ceq IL_0011 16 ldc.i4.0 IL_0012 fe 01 ceq IL_0014 0a stloc.0 IL_0015 06 ldloc.0 IL_0016 2c 04 brfalse.s 4 (IL_001c) IL_0018 16 ldc.i4.0 IL_0019 0b stloc.1 IL_001a 2b 1f br.s 31 (IL_003b) IL_001c 0f 01 ldarga.s 0x1 IL_001e 28 55 00 00 0a call 0xA000055 IL_0023 16 ldc.i4.0 IL_0024 fe 01 ceq IL_0026 0c stloc.2 IL_0027 08 ldloc.2 IL_0028 2c 04 brfalse.s 4 (IL_002e) IL_002a 17 ldc.i4.1 IL_002b 0b stloc.1 IL_002c 2b 0d br.s 13 (IL_003b) IL_002e 02 ldarg.0 IL_002f 03 ldarg.1 IL_0030 28 ff 20 00 06 call 0x60020FF IL_0035 16 ldc.i4.0 IL_0036 fe 01 ceq IL_0038 0b stloc.1 IL_0039 2b 00 br.s 0 (IL_003b) IL_003b 07 ldloc.1 IL_003c 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool Jump targets: IL_001c IL_002e IL_003b multi New Basic Block BB19 [0018] created. BB19 [000..018) New Basic Block BB20 [0019] created. BB20 [018..01C) New Basic Block BB21 [0020] created. BB21 [01C..02A) New Basic Block BB22 [0021] created. BB22 [02A..02E) New Basic Block BB23 [0022] created. BB23 [02E..03B) New Basic Block BB24 [0023] created. BB24 [03B..03D) Basic block list for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB19 [0018] 1 1 [000..018)-> BB21 ( cond ) BB20 [0019] 1 1 [018..01C)-> BB24 (always) BB21 [0020] 1 1 [01C..02A)-> BB23 ( cond ) BB22 [0021] 1 1 [02A..02E)-> BB24 (always) BB23 [0022] 1 1 [02E..03B) BB24 [0023] 3 1 [03B..03D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool impImportBlockPending for BB19 Importing BB19 (PC=000) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarga.s 0 lvaGrabTemp returning 16 (V16 tmp7) called for Inlining Arg. [ 1] 3 (0x003) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000286] ------------ * STMT void [000285] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000284] L----------- this in rcx \--* ADDR byref [000283] ------------ \--* LCL_VAR struct V16 tmp7 [ 1] 8 (0x008) ldarga.s 1 lvaGrabTemp returning 17 (V17 tmp8) called for Inlining Arg. [ 2] 10 (0x00a) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 18 (V18 tmp9) called for impAppendStmt. [000294] ------------ * STMT void [000287] --C--------- | /--* RET_EXPR int (inl return from call [000285]) [000293] -AC--------- \--* ASG int [000292] D------N---- \--* LCL_VAR int V18 tmp9 [000291] ------------ * STMT void [000290] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000289] L----------- this in rcx \--* ADDR byref [000288] ------------ \--* LCL_VAR struct V17 tmp8 [ 2] 15 (0x00f) ceq [ 1] 17 (0x011) ldc.i4.0 0 [ 2] 18 (0x012) ceq [ 1] 20 (0x014) stloc.0 lvaGrabTemp returning 19 (V19 tmp10) (a long lifetime temp) called for Inline stloc first use temp. [000302] ------------ * STMT void [000298] ------------ | /--* CNS_INT int 0 [000299] --C--------- | /--* EQ int [000296] --C--------- | | | /--* RET_EXPR int (inl return from call [000290]) [000297] --C--------- | | \--* EQ int [000295] ------------ | | \--* LCL_VAR int V18 tmp9 [000301] -AC--------- \--* ASG bool [000300] D------N---- \--* LCL_VAR bool V19 tmp10 [ 0] 21 (0x015) ldloc.0 [ 1] 22 (0x016) brfalse.s [000307] ------------ * STMT void [000306] ------------ \--* JTRUE void [000304] ------------ | /--* CNS_INT int 0 [000305] ------------ \--* EQ int [000303] ------------ \--* LCL_VAR int V19 tmp10 impImportBlockPending for BB20 impImportBlockPending for BB21 Importing BB21 (PC=028) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 28 (0x01c) ldarga.s 1 [ 1] 30 (0x01e) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000312] ------------ * STMT void [000311] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000310] L----------- this in rcx \--* ADDR byref [000309] ------------ \--* LCL_VAR struct V17 tmp8 [ 1] 35 (0x023) ldc.i4.0 0 [ 2] 36 (0x024) ceq [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 20 (V20 tmp11) (a long lifetime temp) called for Inline stloc first use temp. [000318] ------------ * STMT void [000314] ------------ | /--* CNS_INT int 0 [000315] --C--------- | /--* EQ int [000313] --C--------- | | \--* RET_EXPR int (inl return from call [000311]) [000317] -AC--------- \--* ASG bool [000316] D------N---- \--* LCL_VAR bool V20 tmp11 [ 0] 39 (0x027) ldloc.2 [ 1] 40 (0x028) brfalse.s [000323] ------------ * STMT void [000322] ------------ \--* JTRUE void [000320] ------------ | /--* CNS_INT int 0 [000321] ------------ \--* EQ int [000319] ------------ \--* LCL_VAR int V20 tmp11 impImportBlockPending for BB22 impImportBlockPending for BB23 Importing BB23 (PC=046) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 46 (0x02e) ldarg.0 [ 1] 47 (0x02f) ldarg.1 [ 2] 48 (0x030) call 060020FF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000326] ------------ * LCL_VAR struct V17 tmp8 resulting tree: [000329] x----------- * OBJ(16) struct [000328] L----------- \--* ADDR byref [000326] ------------ \--* LCL_VAR struct V17 tmp8 Calling impNormStructVal on: [000325] ------------ * LCL_VAR struct V16 tmp7 resulting tree: [000332] x----------- * OBJ(16) struct [000331] L----------- \--* ADDR byref [000325] ------------ \--* LCL_VAR struct V16 tmp7 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' calling 'System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int' INLINER: Marking System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 53 (0x035) ldc.i4.0 0 [ 2] 54 (0x036) ceq [ 1] 56 (0x038) stloc.1 lvaGrabTemp returning 21 (V21 tmp12) (a long lifetime temp) called for Inline stloc first use temp. [000338] ------------ * STMT void [000334] ------------ | /--* CNS_INT int 0 [000335] --C-G------- | /--* EQ int [000327] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000332] x----------- arg0 | | +--* OBJ(16) struct [000331] L----------- | | | \--* ADDR byref [000325] ------------ | | | \--* LCL_VAR struct V16 tmp7 [000329] x----------- arg1 | | \--* OBJ(16) struct [000328] L----------- | | \--* ADDR byref [000326] ------------ | | \--* LCL_VAR struct V17 tmp8 [000337] -AC-G------- \--* ASG bool [000336] D------N---- \--* LCL_VAR bool V21 tmp12 [ 0] 57 (0x039) br.s impImportBlockPending for BB24 Importing BB24 (PC=059) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 59 (0x03b) ldloc.1 [ 1] 60 (0x03c) ret Inlinee Return expression (before normalization) => [000340] ------------ * LCL_VAR int V21 tmp12 Inlinee Return expression (after normalization) => [000341] ------------ * CAST int <- bool <- int [000340] ------------ \--* LCL_VAR int V21 tmp12 Importing BB22 (PC=042) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 42 (0x02a) ldc.i4.1 1 [ 1] 43 (0x02b) stloc.1 [000346] ------------ * STMT void [000343] ------------ | /--* CNS_INT int 1 [000345] -A---------- \--* ASG bool [000344] D------N---- \--* LCL_VAR bool V21 tmp12 [ 0] 44 (0x02c) br.s impImportBlockPending for BB24 Importing BB20 (PC=024) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 24 (0x018) ldc.i4.0 0 [ 1] 25 (0x019) stloc.1 [000351] ------------ * STMT void [000348] ------------ | /--* CNS_INT int 0 [000350] -A---------- \--* ASG bool [000349] D------N---- \--* LCL_VAR bool V21 tmp12 [ 0] 26 (0x01a) br.s impImportBlockPending for BB24 ----------- Statements (and blocks) added due to the inlining of call [000012] ----------- Arguments setup: [000355] ------------ * STMT void (IL 0x00C... ???) [000017] x----------- | /--* OBJ(16) struct [000016] L----------- | | \--* ADDR byref [000010] ------------ | | \--* LCL_VAR struct V02 loc0 [000354] -A------R--- \--* ASG struct (copy) [000352] D----------- \--* LCL_VAR struct V16 tmp7 [000359] ------------ * STMT void (IL 0x00C... ???) [000014] x----------- | /--* OBJ(16) struct [000013] L----------- | | \--* ADDR byref [000011] ------------ | | \--* LCL_VAR struct V00 arg0 [000358] -A------R--- \--* ASG struct (copy) [000356] D----------- \--* LCL_VAR struct V17 tmp8 Zero init inlinee locals: [000363] ------------ * STMT void (IL 0x00C... ???) [000360] ------------ | /--* CNS_INT int 0 [000362] -A---------- \--* ASG bool [000361] D------N---- \--* LCL_VAR bool V19 tmp10 [000367] ------------ * STMT void (IL 0x00C... ???) [000364] ------------ | /--* CNS_INT int 0 [000366] -A---------- \--* ASG bool [000365] D------N---- \--* LCL_VAR bool V21 tmp12 [000371] ------------ * STMT void (IL 0x00C... ???) [000368] ------------ | /--* CNS_INT int 0 [000370] -A---------- \--* ASG bool [000369] D------N---- \--* LCL_VAR bool V20 tmp11 Inlinee method body:New Basic Block BB25 [0024] created. Convert bbJumpKind of BB24 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB19 [0018] 1 1 [00C..00D)-> BB21 ( cond ) i BB20 [0019] 1 0.50 [00C..00D)-> BB24 (always) i BB21 [0020] 1 0.50 [00C..00D)-> BB23 ( cond ) i BB22 [0021] 1 0.50 [00C..00D)-> BB24 (always) i BB23 [0022] 1 0.50 [00C..00D) i BB24 [0023] 3 1 [00C..00D) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB19 [00C..00D) -> BB21 (cond), preds={} succs={BB20,BB21} ***** BB19, stmt 1 [000286] ------------ * STMT void (IL 0x00C... ???) [000285] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000284] L----------- this in rcx \--* ADDR byref [000283] ------------ \--* LCL_VAR struct V16 tmp7 ***** BB19, stmt 2 [000294] ------------ * STMT void (IL 0x00C... ???) [000287] --C--------- | /--* RET_EXPR int (inl return from call [000285]) [000293] -AC--------- \--* ASG int [000292] D------N---- \--* LCL_VAR int V18 tmp9 ***** BB19, stmt 3 [000291] ------------ * STMT void (IL 0x00C... ???) [000290] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000289] L----------- this in rcx \--* ADDR byref [000288] ------------ \--* LCL_VAR struct V17 tmp8 ***** BB19, stmt 4 [000302] ------------ * STMT void (IL 0x00C... ???) [000298] ------------ | /--* CNS_INT int 0 [000299] --C--------- | /--* EQ int [000296] --C--------- | | | /--* RET_EXPR int (inl return from call [000290]) [000297] --C--------- | | \--* EQ int [000295] ------------ | | \--* LCL_VAR int V18 tmp9 [000301] -AC--------- \--* ASG bool [000300] D------N---- \--* LCL_VAR bool V19 tmp10 ***** BB19, stmt 5 [000307] ------------ * STMT void (IL 0x00C... ???) [000306] ------------ \--* JTRUE void [000304] ------------ | /--* CNS_INT int 0 [000305] ------------ \--* EQ int [000303] ------------ \--* LCL_VAR int V19 tmp10 ------------ BB20 [00C..00D) -> BB24 (always), preds={} succs={BB24} ***** BB20, stmt 6 [000351] ------------ * STMT void (IL 0x00C... ???) [000348] ------------ | /--* CNS_INT int 0 [000350] -A---------- \--* ASG bool [000349] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB21 [00C..00D) -> BB23 (cond), preds={} succs={BB22,BB23} ***** BB21, stmt 7 [000312] ------------ * STMT void (IL 0x00C... ???) [000311] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000310] L----------- this in rcx \--* ADDR byref [000309] ------------ \--* LCL_VAR struct V17 tmp8 ***** BB21, stmt 8 [000318] ------------ * STMT void (IL 0x00C... ???) [000314] ------------ | /--* CNS_INT int 0 [000315] --C--------- | /--* EQ int [000313] --C--------- | | \--* RET_EXPR int (inl return from call [000311]) [000317] -AC--------- \--* ASG bool [000316] D------N---- \--* LCL_VAR bool V20 tmp11 ***** BB21, stmt 9 [000323] ------------ * STMT void (IL 0x00C... ???) [000322] ------------ \--* JTRUE void [000320] ------------ | /--* CNS_INT int 0 [000321] ------------ \--* EQ int [000319] ------------ \--* LCL_VAR int V20 tmp11 ------------ BB22 [00C..00D) -> BB24 (always), preds={} succs={BB24} ***** BB22, stmt 10 [000346] ------------ * STMT void (IL 0x00C... ???) [000343] ------------ | /--* CNS_INT int 1 [000345] -A---------- \--* ASG bool [000344] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB23 [00C..00D), preds={} succs={BB24} ***** BB23, stmt 11 [000338] ------------ * STMT void (IL 0x00C... ???) [000334] ------------ | /--* CNS_INT int 0 [000335] --C-G------- | /--* EQ int [000327] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000332] x----------- arg0 | | +--* OBJ(16) struct [000331] L----------- | | | \--* ADDR byref [000325] ------------ | | | \--* LCL_VAR struct V16 tmp7 [000329] x----------- arg1 | | \--* OBJ(16) struct [000328] L----------- | | \--* ADDR byref [000326] ------------ | | \--* LCL_VAR struct V17 tmp8 [000337] -AC-G------- \--* ASG bool [000336] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB24 [00C..00D), preds={} succs={BB25} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000012] is [000341] ------------ * CAST int <- bool <- int [000340] ------------ \--* LCL_VAR int V21 tmp12 Successfully inlined System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool (61 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000286] in BB19: [000286] ------------ * STMT void (IL 0x00C... ???) [000285] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000284] L----------- this in rcx \--* ADDR byref [000283] ------------ \--* LCL_VAR struct V16 tmp7 thisArg: is a constant is byref to a struct local [000284] L----------- * ADDR byref [000283] ------------ \--* LCL_VAR struct V16 tmp7 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB26 [0025] created. BB26 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB26 [0025] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB26 Importing BB26 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 22 (V22 tmp13) (a long lifetime temp) called for Inline stloc first use temp. [000379] ------------ * STMT void [000376] ------------ | /--* FIELD int _length [000374] L----------- | | \--* ADDR byref [000375] ------------ | | \--* LCL_VAR struct V16 tmp7 [000378] -A---------- \--* ASG int [000377] D------N---- \--* LCL_VAR int V22 tmp13 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000380] ------------ * LCL_VAR int V22 tmp13 Inlinee Return expression (after normalization) => [000380] ------------ * LCL_VAR int V22 tmp13 ----------- Statements (and blocks) added due to the inlining of call [000285] ----------- Arguments setup: Zero init inlinee locals: [000384] ------------ * STMT void (IL 0x00C... ???) [000381] ------------ | /--* CNS_INT int 0 [000383] -A---------- \--* ASG int [000382] D------N---- \--* LCL_VAR int V22 tmp13 Inlinee method body: [000379] ------------ * STMT void (IL 0x00C... ???) [000376] ------------ | /--* FIELD int _length [000374] L----------- | | \--* ADDR byref [000375] ------------ | | \--* LCL_VAR struct V16 tmp7 [000378] -A---------- \--* ASG int [000377] D------N---- \--* LCL_VAR int V22 tmp13 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000285] is [000380] ------------ * LCL_VAR int V22 tmp13 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000287] with [000380] [000287] --C--------- * RET_EXPR int (inl return from call [000380]) Inserting the inline return expression [000380] ------------ * LCL_VAR int V22 tmp13 Expanding INLINE_CANDIDATE in statement [000291] in BB19: [000291] ------------ * STMT void (IL 0x00C... ???) [000290] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000289] L----------- this in rcx \--* ADDR byref [000288] ------------ \--* LCL_VAR struct V17 tmp8 thisArg: is a constant is byref to a struct local [000289] L----------- * ADDR byref [000288] ------------ \--* LCL_VAR struct V17 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB27 [0026] created. BB27 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB27 [0026] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB27 Importing BB27 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 23 (V23 tmp14) (a long lifetime temp) called for Inline stloc first use temp. [000392] ------------ * STMT void [000389] ------------ | /--* FIELD int _length [000387] L----------- | | \--* ADDR byref [000388] ------------ | | \--* LCL_VAR struct V17 tmp8 [000391] -A---------- \--* ASG int [000390] D------N---- \--* LCL_VAR int V23 tmp14 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000393] ------------ * LCL_VAR int V23 tmp14 Inlinee Return expression (after normalization) => [000393] ------------ * LCL_VAR int V23 tmp14 ----------- Statements (and blocks) added due to the inlining of call [000290] ----------- Arguments setup: Zero init inlinee locals: [000397] ------------ * STMT void (IL 0x00C... ???) [000394] ------------ | /--* CNS_INT int 0 [000396] -A---------- \--* ASG int [000395] D------N---- \--* LCL_VAR int V23 tmp14 Inlinee method body: [000392] ------------ * STMT void (IL 0x00C... ???) [000389] ------------ | /--* FIELD int _length [000387] L----------- | | \--* ADDR byref [000388] ------------ | | \--* LCL_VAR struct V17 tmp8 [000391] -A---------- \--* ASG int [000390] D------N---- \--* LCL_VAR int V23 tmp14 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000290] is [000393] ------------ * LCL_VAR int V23 tmp14 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000296] with [000393] [000296] --C--------- * RET_EXPR int (inl return from call [000393]) Inserting the inline return expression [000393] ------------ * LCL_VAR int V23 tmp14 Expanding INLINE_CANDIDATE in statement [000312] in BB21: [000312] ------------ * STMT void (IL 0x00C... ???) [000311] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000310] L----------- this in rcx \--* ADDR byref [000309] ------------ \--* LCL_VAR struct V17 tmp8 thisArg: is a constant is byref to a struct local [000310] L----------- * ADDR byref [000309] ------------ \--* LCL_VAR struct V17 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB28 [0027] created. BB28 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB28 [0027] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB28 Importing BB28 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 24 (V24 tmp15) (a long lifetime temp) called for Inline stloc first use temp. [000405] ------------ * STMT void [000402] ------------ | /--* FIELD int _length [000400] L----------- | | \--* ADDR byref [000401] ------------ | | \--* LCL_VAR struct V17 tmp8 [000404] -A---------- \--* ASG int [000403] D------N---- \--* LCL_VAR int V24 tmp15 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000406] ------------ * LCL_VAR int V24 tmp15 Inlinee Return expression (after normalization) => [000406] ------------ * LCL_VAR int V24 tmp15 ----------- Statements (and blocks) added due to the inlining of call [000311] ----------- Arguments setup: Zero init inlinee locals: [000410] ------------ * STMT void (IL 0x00C... ???) [000407] ------------ | /--* CNS_INT int 0 [000409] -A---------- \--* ASG int [000408] D------N---- \--* LCL_VAR int V24 tmp15 Inlinee method body: [000405] ------------ * STMT void (IL 0x00C... ???) [000402] ------------ | /--* FIELD int _length [000400] L----------- | | \--* ADDR byref [000401] ------------ | | \--* LCL_VAR struct V17 tmp8 [000404] -A---------- \--* ASG int [000403] D------N---- \--* LCL_VAR int V24 tmp15 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000311] is [000406] ------------ * LCL_VAR int V24 tmp15 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000313] with [000406] [000313] --C--------- * RET_EXPR int (inl return from call [000406]) Inserting the inline return expression [000406] ------------ * LCL_VAR int V24 tmp15 Replacing the return expression placeholder [000020] with [000341] [000020] --C--------- * RET_EXPR int (inl return from call [000341]) Inserting the inline return expression [000341] ------------ * CAST int <- bool <- int [000340] ------------ \--* LCL_VAR int V21 tmp12 Expanding INLINE_CANDIDATE in statement [000034] in BB03: [000034] ------------ * STMT void (IL 0x01F...0x029) [000032] I-C-G------- \--* CALL void System.MemoryExtensions.AsSpan (exactContextHnd=0x0000000000423089) [000037] L----------- arg0 +--* ADDR byref [000036] ------------ | \--* LCL_VAR struct V03 loc1 [000031] ------------ arg1 \--* CNS_STR ref Argument #0: is a constant [000031] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:AsSpan(ref):struct set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:AsSpan(ref):struct : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 14 ldnull IL_0003 fe 01 ceq IL_0005 0a stloc.0 IL_0006 06 ldloc.0 IL_0007 2c 0c brfalse.s 12 (IL_0015) IL_0009 12 01 ldloca.s 0x1 IL_000b fe 15 c1 00 00 1b initobj 0x1B0000C1 IL_0011 07 ldloc.1 IL_0012 0c stloc.2 IL_0013 2b 14 br.s 20 (IL_0029) IL_0015 02 ldarg.0 IL_0016 6f 7e 03 00 06 callvirt 0x600037E IL_001b 02 ldarg.0 IL_001c 6f 5d 03 00 06 callvirt 0x600035D IL_0021 73 77 00 00 0a newobj 0xA000077 IL_0026 0c stloc.2 IL_0027 2b 00 br.s 0 (IL_0029) IL_0029 08 ldloc.2 IL_002a 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:AsSpan(ref):struct is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:AsSpan(ref):struct Jump targets: IL_0015 IL_0029 New Basic Block BB29 [0028] created. BB29 [000..009) New Basic Block BB30 [0029] created. BB30 [009..015) New Basic Block BB31 [0030] created. BB31 [015..029) New Basic Block BB32 [0031] created. BB32 [029..02B) Basic block list for 'System.MemoryExtensions:AsSpan(ref):struct' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB29 [0028] 1 1 [000..009)-> BB31 ( cond ) BB30 [0029] 1 1 [009..015)-> BB32 (always) BB31 [0030] 1 1 [015..029) BB32 [0031] 2 1 [029..02B) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:AsSpan(ref):struct impImportBlockPending for BB29 Importing BB29 (PC=000) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldnull [ 2] 3 (0x003) ceq [ 1] 5 (0x005) stloc.0 lvaGrabTemp returning 25 (V25 tmp16) (a long lifetime temp) called for Inline stloc first use temp. [000418] ------------ * STMT void [000414] ------------ | /--* CNS_INT ref null [000415] ------------ | /--* EQ int [000413] ------------ | | \--* CNS_STR ref [000417] -A---------- \--* ASG bool [000416] D------N---- \--* LCL_VAR bool V25 tmp16 [ 0] 6 (0x006) ldloc.0 [ 1] 7 (0x007) brfalse.s [000423] ------------ * STMT void [000422] ------------ \--* JTRUE void [000420] ------------ | /--* CNS_INT int 0 [000421] ------------ \--* EQ int [000419] ------------ \--* LCL_VAR int V25 tmp16 impImportBlockPending for BB30 impImportBlockPending for BB31 Importing BB31 (PC=021) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) callvirt 0600037E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is byref, structSize is 0 [000427] ------------ * STMT void [000426] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000425] ------------ this in rcx \--* CNS_STR ref [ 1] 27 (0x01b) ldarg.0 [ 2] 28 (0x01c) callvirt 0600035D In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 26 (V26 tmp17) called for impAppendStmt. [000434] ------------ * STMT void [000428] --C--------- | /--* RET_EXPR byref (inl return from call [000426]) [000433] -AC--------- \--* ASG byref [000432] D------N---- \--* LCL_VAR byref V26 tmp17 [000431] ------------ * STMT void [000430] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000429] ------------ this in rcx \--* CNS_STR ref [ 2] 33 (0x021) newobj lvaGrabTemp returning 27 (V27 tmp18) called for NewObj constructor temp. [000440] ------------ * STMT void [000438] ------------ | /--* CNS_INT int 0 [000439] IA------R--- \--* ASG struct (init) [000437] D------N---- \--* LCL_VAR struct V27 tmp18 0A000077 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000446] ------------ * STMT void [000443] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000442] L----------- this in rcx +--* ADDR byref [000441] ------------ | \--* LCL_VAR struct V27 tmp18 [000435] ------------ arg1 +--* LCL_VAR byref V26 tmp17 [000436] --C--------- arg2 \--* RET_EXPR int (inl return from call [000430]) [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 28 (V28 tmp19) (a long lifetime temp) called for Inline stloc first use temp. [000451] ------------ * STMT void [000447] ------------ | /--* LCL_VAR struct V27 tmp18 [000450] -A------R--- \--* ASG struct (copy) [000448] D----------- \--* LCL_VAR struct V28 tmp19 [ 0] 39 (0x027) br.s impImportBlockPending for BB32 Importing BB32 (PC=041) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 41 (0x029) ldloc.2 [ 1] 42 (0x02a) ret Inlinee Return expression (before normalization) => [000453] ------------ * LCL_VAR struct V28 tmp19 Importing BB30 (PC=009) of 'System.MemoryExtensions:AsSpan(ref):struct' [ 0] 9 (0x009) ldloca.s 1 lvaGrabTemp returning 29 (V29 tmp20) (a long lifetime temp) called for Inline ldloca(s) first use temp. [ 1] 11 (0x00b) initobj 1B0000C1 [000462] ------------ * STMT void [000460] ------------ | /--* CNS_INT int 0 [000461] IA------R--- \--* ASG struct (init) [000458] D------N---- \--* LCL_VAR struct V29 tmp20 [ 0] 17 (0x011) ldloc.1 [ 1] 18 (0x012) stloc.2 [000467] ------------ * STMT void [000463] ------------ | /--* LCL_VAR struct V29 tmp20 [000466] -A------R--- \--* ASG struct (copy) [000464] D----------- \--* LCL_VAR struct V28 tmp19 [ 0] 19 (0x013) br.s impImportBlockPending for BB32 ----------- Statements (and blocks) added due to the inlining of call [000032] ----------- Arguments setup: Zero init inlinee locals: [000471] ------------ * STMT void (IL 0x01F... ???) [000468] ------------ | /--* CNS_INT int 0 [000470] -A---------- \--* ASG bool [000469] D------N---- \--* LCL_VAR bool V25 tmp16 [000471] ------------ * STMT void (IL 0x01F... ???) [000468] ------------ | /--* CNS_INT int 0 [000470] -A---------- \--* ASG bool [000469] D------N---- \--* LCL_VAR bool V25 tmp16 [000471] ------------ * STMT void (IL 0x01F... ???) [000468] ------------ | /--* CNS_INT int 0 [000470] -A---------- \--* ASG bool [000469] D------N---- \--* LCL_VAR bool V25 tmp16 Inlinee method body:New Basic Block BB33 [0032] created. Convert bbJumpKind of BB32 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB29 [0028] 1 1 [01F..020)-> BB31 ( cond ) i BB30 [0029] 1 0.50 [01F..020)-> BB32 (always) i BB31 [0030] 1 0.50 [01F..020) i BB32 [0031] 2 1 [01F..020) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB29 [01F..020) -> BB31 (cond), preds={} succs={BB30,BB31} ***** BB29, stmt 1 [000418] ------------ * STMT void (IL 0x01F... ???) [000414] ------------ | /--* CNS_INT ref null [000415] ------------ | /--* EQ int [000413] ------------ | | \--* CNS_STR ref [000417] -A---------- \--* ASG bool [000416] D------N---- \--* LCL_VAR bool V25 tmp16 ***** BB29, stmt 2 [000423] ------------ * STMT void (IL 0x01F... ???) [000422] ------------ \--* JTRUE void [000420] ------------ | /--* CNS_INT int 0 [000421] ------------ \--* EQ int [000419] ------------ \--* LCL_VAR int V25 tmp16 ------------ BB30 [01F..020) -> BB32 (always), preds={} succs={BB32} ***** BB30, stmt 3 [000462] ------------ * STMT void (IL 0x01F... ???) [000460] ------------ | /--* CNS_INT int 0 [000461] IA------R--- \--* ASG struct (init) [000458] D------N---- \--* LCL_VAR struct V29 tmp20 ***** BB30, stmt 4 [000467] ------------ * STMT void (IL 0x01F... ???) [000463] ------------ | /--* LCL_VAR struct V29 tmp20 [000466] -A------R--- \--* ASG struct (copy) [000464] D----------- \--* LCL_VAR struct V28 tmp19 ------------ BB31 [01F..020), preds={} succs={BB32} ***** BB31, stmt 5 [000427] ------------ * STMT void (IL 0x01F... ???) [000426] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000425] ------------ this in rcx \--* CNS_STR ref ***** BB31, stmt 6 [000434] ------------ * STMT void (IL 0x01F... ???) [000428] --C--------- | /--* RET_EXPR byref (inl return from call [000426]) [000433] -AC--------- \--* ASG byref [000432] D------N---- \--* LCL_VAR byref V26 tmp17 ***** BB31, stmt 7 [000431] ------------ * STMT void (IL 0x01F... ???) [000430] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000429] ------------ this in rcx \--* CNS_STR ref ***** BB31, stmt 8 [000440] ------------ * STMT void (IL 0x01F... ???) [000438] ------------ | /--* CNS_INT int 0 [000439] IA------R--- \--* ASG struct (init) [000437] D------N---- \--* LCL_VAR struct V27 tmp18 ***** BB31, stmt 9 [000446] ------------ * STMT void (IL 0x01F... ???) [000443] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000442] L----------- this in rcx +--* ADDR byref [000441] ------------ | \--* LCL_VAR struct V27 tmp18 [000435] ------------ arg1 +--* LCL_VAR byref V26 tmp17 [000436] --C--------- arg2 \--* RET_EXPR int (inl return from call [000430]) ***** BB31, stmt 10 [000451] ------------ * STMT void (IL 0x01F... ???) [000447] ------------ | /--* LCL_VAR struct V27 tmp18 [000450] -A------R--- \--* ASG struct (copy) [000448] D----------- \--* LCL_VAR struct V28 tmp19 ------------ BB32 [01F..020), preds={} succs={BB33} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000032] is [000453] ------------ /--* LCL_VAR struct V28 tmp19 [000456] -A------R--- * ASG struct (copy) [000455] D----------- \--* LCL_VAR struct V03 loc1 Successfully inlined System.MemoryExtensions:AsSpan(ref):struct (43 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:AsSpan(ref):struct' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000427] in BB31: [000427] ------------ * STMT void (IL 0x01F... ???) [000426] I-C-G------- \--* CALL nullcheck byref System.String.GetRawStringData (exactContextHnd=0x0000000000420891) [000425] ------------ this in rcx \--* CNS_STR ref thisArg: is a constant [000425] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.String:GetRawStringData():byref:this set to 0x0000000000420891: Invoking compiler for the inlinee method System.String:GetRawStringData():byref:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 12 01 00 04 ldflda 0x4000112 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.String:GetRawStringData():byref:this is 0x0000000000420891. *************** In fgFindBasicBlocks() for System.String:GetRawStringData():byref:this Jump targets: none New Basic Block BB34 [0033] created. BB34 [000..007) Basic block list for 'System.String:GetRawStringData():byref:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB34 [0033] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.String:GetRawStringData():byref:this impImportBlockPending for BB34 Importing BB34 (PC=000) of 'System.String:GetRawStringData():byref:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 04000112 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000476] ---XG------- * ADDR byref [000475] ---XG------- \--* FIELD ushort _firstChar [000474] ------------ \--* CNS_STR ref Inlinee Return expression (after normalization) => [000476] ---XG------- * ADDR byref [000475] ---XG------- \--* FIELD ushort _firstChar [000474] ------------ \--* CNS_STR ref ----------- Statements (and blocks) added due to the inlining of call [000426] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000426] is [000476] ---XG------- * ADDR byref [000475] ---XG------- \--* FIELD ushort _firstChar [000474] ------------ \--* CNS_STR ref Successfully inlined System.String:GetRawStringData():byref:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.String:GetRawStringData():byref:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000428] with [000476] [000428] --C--------- * RET_EXPR byref (inl return from call [000476]) Inserting the inline return expression [000476] ---XG------- * ADDR byref [000475] ---XG------- \--* FIELD ushort _firstChar [000474] ------------ \--* CNS_STR ref Expanding INLINE_CANDIDATE in statement [000431] in BB31: [000431] ------------ * STMT void (IL 0x01F... ???) [000430] I-C-G------- \--* CALL nullcheck int System.String.get_Length (exactContextHnd=0x0000000000420891) [000429] ------------ this in rcx \--* CNS_STR ref thisArg: is a constant [000429] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.String:get_Length():int:this set to 0x0000000000420891: Invoking compiler for the inlinee method System.String:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 11 01 00 04 ldfld 0x4000111 IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.String:get_Length():int:this is 0x0000000000420891. *************** In fgFindBasicBlocks() for System.String:get_Length():int:this Jump targets: none New Basic Block BB35 [0034] created. BB35 [000..00C) Basic block list for 'System.String:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB35 [0034] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.String:get_Length():int:this impImportBlockPending for BB35 Importing BB35 (PC=000) of 'System.String:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 04000111 [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 30 (V30 tmp21) (a long lifetime temp) called for Inline stloc first use temp. [000486] ------------ * STMT void [000483] ---XG------- | /--* FIELD int _stringLength [000482] ------------ | | \--* CNS_STR ref [000485] -A-XG------- \--* ASG int [000484] D------N---- \--* LCL_VAR int V30 tmp21 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000487] ------------ * LCL_VAR int V30 tmp21 Inlinee Return expression (after normalization) => [000487] ------------ * LCL_VAR int V30 tmp21 ----------- Statements (and blocks) added due to the inlining of call [000430] ----------- Arguments setup: Zero init inlinee locals: [000494] ------------ * STMT void (IL 0x01F... ???) [000491] ------------ | /--* CNS_INT int 0 [000493] -A---------- \--* ASG int [000492] D------N---- \--* LCL_VAR int V30 tmp21 Inlinee method body: [000486] ------------ * STMT void (IL 0x01F... ???) [000483] ---XG------- | /--* FIELD int _stringLength [000482] ------------ | | \--* CNS_STR ref [000485] -A-XG------- \--* ASG int [000484] D------N---- \--* LCL_VAR int V30 tmp21 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000430] is [000487] ------------ * LCL_VAR int V30 tmp21 Successfully inlined System.String:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.String:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement [000446] in BB31: [000446] ------------ * STMT void (IL 0x01F... ???) [000443] I-C-G------- \--* CALL void System.ReadOnlySpan`1..ctor (exactContextHnd=0x0000000000421A31) [000442] L----------- this in rcx +--* ADDR byref [000441] ------------ | \--* LCL_VAR struct V27 tmp18 [000435] ------------ arg1 +--* LCL_VAR byref V26 tmp17 [000436] --C--------- arg2 \--* RET_EXPR int (inl return from call [000487]) thisArg: is a constant is byref to a struct local [000442] L----------- * ADDR byref [000441] ------------ \--* LCL_VAR struct V27 tmp18 Argument #1: is a local var [000435] ------------ * LCL_VAR byref V26 tmp17 Argument #2: is a local var [000487] ------------ * LCL_VAR int V30 tmp21 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:.ctor(byref,int):this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:.ctor(byref,int):this : IL to import: IL_0000 00 nop IL_0001 04 ldarg.2 IL_0002 16 ldc.i4.0 IL_0003 fe 04 clt IL_0005 16 ldc.i4.0 IL_0006 fe 01 ceq IL_0008 28 c6 24 00 06 call 0x60024C6 IL_000d 00 nop IL_000e 02 ldarg.0 IL_000f 03 ldarg.1 IL_0010 73 30 01 00 0a newobj 0xA000130 IL_0015 7d 31 01 00 0a stfld 0xA000131 IL_001a 02 ldarg.0 IL_001b 04 ldarg.2 IL_001c 7d 2b 01 00 0a stfld 0xA00012B IL_0021 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:.ctor(byref,int):this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:.ctor(byref,int):this Jump targets: none New Basic Block BB36 [0035] created. BB36 [000..022) Basic block list for 'System.ReadOnlySpan`1:.ctor(byref,int):this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB36 [0035] 1 1 [000..022) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:.ctor(byref,int):this impImportBlockPending for BB36 Importing BB36 (PC=000) of 'System.ReadOnlySpan`1:.ctor(byref,int):this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.2 [ 1] 2 (0x002) ldc.i4.0 0 [ 2] 3 (0x003) clt [ 1] 5 (0x005) ldc.i4.0 0 [ 2] 6 (0x006) ceq [ 1] 8 (0x008) call 060024C6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000503] ------------ * STMT void [000501] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000499] ------------ | /--* CNS_INT int 0 [000500] ------------ arg0 \--* EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 [ 0] 13 (0x00d) nop [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldarg.1 [ 2] 16 (0x010) newobj lvaGrabTemp returning 31 (V31 tmp22) called for NewObj constructor temp. [000509] ------------ * STMT void [000507] ------------ | /--* CNS_INT int 0 [000508] IA------R--- \--* ASG struct (init) [000506] D------N---- \--* LCL_VAR struct V31 tmp22 0A000130 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000515] ------------ * STMT void [000435] ------------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---------- \--* ASG byref [000512] -------N---- \--* FIELD byref _value [000511] L----------- \--* ADDR byref [000510] ------------ \--* LCL_VAR struct V31 tmp22 [ 2] 21 (0x015) stfld 0A000131 [000520] ------------ * STMT void [000514] ------------ | /--* LCL_VAR struct V31 tmp22 [000519] -A------R--- \--* ASG struct (copy) [000518] ------------ \--* OBJ(8) struct [000517] ------------ \--* ADDR byref [000516] ------------ \--* FIELD struct _pointer [000504] L----------- \--* ADDR byref [000505] ------------ \--* LCL_VAR struct V27 tmp18 [ 0] 26 (0x01a) ldarg.0 [ 1] 27 (0x01b) ldarg.2 [ 2] 28 (0x01c) stfld 0A00012B [000526] ------------ * STMT void [000523] ------------ | /--* LCL_VAR int V30 tmp21 [000525] -A---------- \--* ASG int [000524] -------N---- \--* FIELD int _length [000521] L----------- \--* ADDR byref [000522] ------------ \--* LCL_VAR struct V27 tmp18 [ 0] 33 (0x021) ret ----------- Statements (and blocks) added due to the inlining of call [000443] ----------- Arguments setup: Inlinee method body: [000503] ------------ * STMT void (IL 0x01F... ???) [000501] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000499] ------------ | /--* CNS_INT int 0 [000500] ------------ arg0 \--* EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 [000509] ------------ * STMT void (IL 0x01F... ???) [000507] ------------ | /--* CNS_INT int 0 [000508] IA------R--- \--* ASG struct (init) [000506] D------N---- \--* LCL_VAR struct V31 tmp22 [000515] ------------ * STMT void (IL 0x01F... ???) [000435] ------------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---------- \--* ASG byref [000512] -------N---- \--* FIELD byref _value [000511] L----------- \--* ADDR byref [000510] ------------ \--* LCL_VAR struct V31 tmp22 [000520] ------------ * STMT void (IL 0x01F... ???) [000514] ------------ | /--* LCL_VAR struct V31 tmp22 [000519] -A------R--- \--* ASG struct (copy) [000518] ------------ \--* OBJ(8) struct [000517] ------------ \--* ADDR byref [000516] ------------ \--* FIELD struct _pointer [000504] L----------- \--* ADDR byref [000505] ------------ \--* LCL_VAR struct V27 tmp18 [000526] ------------ * STMT void (IL 0x01F... ???) [000523] ------------ | /--* LCL_VAR int V30 tmp21 [000525] -A---------- \--* ASG int [000524] -------N---- \--* FIELD int _length [000521] L----------- \--* ADDR byref [000522] ------------ \--* LCL_VAR struct V27 tmp18 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1:.ctor(byref,int):this (34 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:.ctor(byref,int):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000503] in BB31: [000503] ------------ * STMT void (IL 0x01F... ???) [000501] I-C-G------- \--* CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x0000000000422319) [000499] ------------ | /--* CNS_INT int 0 [000500] ------------ arg0 \--* EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 Argument #0: [000499] ------------ /--* CNS_INT int 0 [000500] ------------ * EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x0000000000422319: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7e 13 01 00 04 ldsfld 0x4000113 IL_0007 7e 13 01 00 04 ldsfld 0x4000113 IL_000c 28 c8 24 00 06 call 0x60024C8 IL_0011 00 nop IL_0012 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x0000000000422319. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 65 : state 2 [ noshow ] weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 65 : state 2 [ noshow ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=556 callsiteNativeSizeEstimate=85 benefit multiplier=1.3 threshold=110 Native estimate for function size exceeds threshold for inlining 55.6 > 11 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000035] with [000456] [000035] --C--------- * RET_EXPR void (inl return from call [000456]) Inserting the inline return expression [000453] ------------ /--* LCL_VAR struct V28 tmp19 [000456] -A------R--- * ASG struct (copy) [000455] D----------- \--* LCL_VAR struct V03 loc1 Expanding INLINE_CANDIDATE in statement [000049] in BB33: [000049] ------------ * STMT void (IL 0x02A...0x031) [000042] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000047] x----------- arg0 +--* OBJ(16) struct [000046] L----------- | \--* ADDR byref [000040] ------------ | \--* LCL_VAR struct V03 loc1 [000044] x----------- arg1 \--* OBJ(16) struct [000043] L----------- \--* ADDR byref [000041] ------------ \--* LCL_VAR struct V00 arg0 Argument #0: [000047] x----------- * OBJ(16) struct [000046] L----------- \--* ADDR byref [000040] ------------ \--* LCL_VAR struct V03 loc1 Argument #1: [000044] x----------- * OBJ(16) struct [000043] L----------- \--* ADDR byref [000041] ------------ \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool : IL to import: IL_0000 00 nop IL_0001 0f 00 ldarga.s 0x0 IL_0003 28 55 00 00 0a call 0xA000055 IL_0008 0f 01 ldarga.s 0x1 IL_000a 28 55 00 00 0a call 0xA000055 IL_000f fe 01 ceq IL_0011 16 ldc.i4.0 IL_0012 fe 01 ceq IL_0014 0a stloc.0 IL_0015 06 ldloc.0 IL_0016 2c 04 brfalse.s 4 (IL_001c) IL_0018 16 ldc.i4.0 IL_0019 0b stloc.1 IL_001a 2b 1f br.s 31 (IL_003b) IL_001c 0f 01 ldarga.s 0x1 IL_001e 28 55 00 00 0a call 0xA000055 IL_0023 16 ldc.i4.0 IL_0024 fe 01 ceq IL_0026 0c stloc.2 IL_0027 08 ldloc.2 IL_0028 2c 04 brfalse.s 4 (IL_002e) IL_002a 17 ldc.i4.1 IL_002b 0b stloc.1 IL_002c 2b 0d br.s 13 (IL_003b) IL_002e 02 ldarg.0 IL_002f 03 ldarg.1 IL_0030 28 ff 20 00 06 call 0x60020FF IL_0035 16 ldc.i4.0 IL_0036 fe 01 ceq IL_0038 0b stloc.1 IL_0039 2b 00 br.s 0 (IL_003b) IL_003b 07 ldloc.1 IL_003c 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool Jump targets: IL_001c IL_002e IL_003b multi New Basic Block BB37 [0036] created. BB37 [000..018) New Basic Block BB38 [0037] created. BB38 [018..01C) New Basic Block BB39 [0038] created. BB39 [01C..02A) New Basic Block BB40 [0039] created. BB40 [02A..02E) New Basic Block BB41 [0040] created. BB41 [02E..03B) New Basic Block BB42 [0041] created. BB42 [03B..03D) Basic block list for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB37 [0036] 1 1 [000..018)-> BB39 ( cond ) BB38 [0037] 1 1 [018..01C)-> BB42 (always) BB39 [0038] 1 1 [01C..02A)-> BB41 ( cond ) BB40 [0039] 1 1 [02A..02E)-> BB42 (always) BB41 [0040] 1 1 [02E..03B) BB42 [0041] 3 1 [03B..03D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool impImportBlockPending for BB37 Importing BB37 (PC=000) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarga.s 0 lvaGrabTemp returning 32 (V32 tmp23) called for Inlining Arg. [ 1] 3 (0x003) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000533] ------------ * STMT void [000532] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000531] L----------- this in rcx \--* ADDR byref [000530] ------------ \--* LCL_VAR struct V32 tmp23 [ 1] 8 (0x008) ldarga.s 1 lvaGrabTemp returning 33 (V33 tmp24) called for Inlining Arg. [ 2] 10 (0x00a) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 34 (V34 tmp25) called for impAppendStmt. [000541] ------------ * STMT void [000534] --C--------- | /--* RET_EXPR int (inl return from call [000532]) [000540] -AC--------- \--* ASG int [000539] D------N---- \--* LCL_VAR int V34 tmp25 [000538] ------------ * STMT void [000537] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000536] L----------- this in rcx \--* ADDR byref [000535] ------------ \--* LCL_VAR struct V33 tmp24 [ 2] 15 (0x00f) ceq [ 1] 17 (0x011) ldc.i4.0 0 [ 2] 18 (0x012) ceq [ 1] 20 (0x014) stloc.0 lvaGrabTemp returning 35 (V35 tmp26) (a long lifetime temp) called for Inline stloc first use temp. [000549] ------------ * STMT void [000545] ------------ | /--* CNS_INT int 0 [000546] --C--------- | /--* EQ int [000543] --C--------- | | | /--* RET_EXPR int (inl return from call [000537]) [000544] --C--------- | | \--* EQ int [000542] ------------ | | \--* LCL_VAR int V34 tmp25 [000548] -AC--------- \--* ASG bool [000547] D------N---- \--* LCL_VAR bool V35 tmp26 [ 0] 21 (0x015) ldloc.0 [ 1] 22 (0x016) brfalse.s [000554] ------------ * STMT void [000553] ------------ \--* JTRUE void [000551] ------------ | /--* CNS_INT int 0 [000552] ------------ \--* EQ int [000550] ------------ \--* LCL_VAR int V35 tmp26 impImportBlockPending for BB38 impImportBlockPending for BB39 Importing BB39 (PC=028) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 28 (0x01c) ldarga.s 1 [ 1] 30 (0x01e) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000559] ------------ * STMT void [000558] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000557] L----------- this in rcx \--* ADDR byref [000556] ------------ \--* LCL_VAR struct V33 tmp24 [ 1] 35 (0x023) ldc.i4.0 0 [ 2] 36 (0x024) ceq [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 36 (V36 tmp27) (a long lifetime temp) called for Inline stloc first use temp. [000565] ------------ * STMT void [000561] ------------ | /--* CNS_INT int 0 [000562] --C--------- | /--* EQ int [000560] --C--------- | | \--* RET_EXPR int (inl return from call [000558]) [000564] -AC--------- \--* ASG bool [000563] D------N---- \--* LCL_VAR bool V36 tmp27 [ 0] 39 (0x027) ldloc.2 [ 1] 40 (0x028) brfalse.s [000570] ------------ * STMT void [000569] ------------ \--* JTRUE void [000567] ------------ | /--* CNS_INT int 0 [000568] ------------ \--* EQ int [000566] ------------ \--* LCL_VAR int V36 tmp27 impImportBlockPending for BB40 impImportBlockPending for BB41 Importing BB41 (PC=046) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 46 (0x02e) ldarg.0 [ 1] 47 (0x02f) ldarg.1 [ 2] 48 (0x030) call 060020FF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000573] ------------ * LCL_VAR struct V33 tmp24 resulting tree: [000576] x----------- * OBJ(16) struct [000575] L----------- \--* ADDR byref [000573] ------------ \--* LCL_VAR struct V33 tmp24 Calling impNormStructVal on: [000572] ------------ * LCL_VAR struct V32 tmp23 resulting tree: [000579] x----------- * OBJ(16) struct [000578] L----------- \--* ADDR byref [000572] ------------ \--* LCL_VAR struct V32 tmp23 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' calling 'System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int' INLINER: Marking System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 53 (0x035) ldc.i4.0 0 [ 2] 54 (0x036) ceq [ 1] 56 (0x038) stloc.1 lvaGrabTemp returning 37 (V37 tmp28) (a long lifetime temp) called for Inline stloc first use temp. [000585] ------------ * STMT void [000581] ------------ | /--* CNS_INT int 0 [000582] --C-G------- | /--* EQ int [000574] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000579] x----------- arg0 | | +--* OBJ(16) struct [000578] L----------- | | | \--* ADDR byref [000572] ------------ | | | \--* LCL_VAR struct V32 tmp23 [000576] x----------- arg1 | | \--* OBJ(16) struct [000575] L----------- | | \--* ADDR byref [000573] ------------ | | \--* LCL_VAR struct V33 tmp24 [000584] -AC-G------- \--* ASG bool [000583] D------N---- \--* LCL_VAR bool V37 tmp28 [ 0] 57 (0x039) br.s impImportBlockPending for BB42 Importing BB42 (PC=059) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 59 (0x03b) ldloc.1 [ 1] 60 (0x03c) ret Inlinee Return expression (before normalization) => [000587] ------------ * LCL_VAR int V37 tmp28 Inlinee Return expression (after normalization) => [000588] ------------ * CAST int <- bool <- int [000587] ------------ \--* LCL_VAR int V37 tmp28 Importing BB40 (PC=042) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 42 (0x02a) ldc.i4.1 1 [ 1] 43 (0x02b) stloc.1 [000593] ------------ * STMT void [000590] ------------ | /--* CNS_INT int 1 [000592] -A---------- \--* ASG bool [000591] D------N---- \--* LCL_VAR bool V37 tmp28 [ 0] 44 (0x02c) br.s impImportBlockPending for BB42 Importing BB38 (PC=024) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 24 (0x018) ldc.i4.0 0 [ 1] 25 (0x019) stloc.1 [000598] ------------ * STMT void [000595] ------------ | /--* CNS_INT int 0 [000597] -A---------- \--* ASG bool [000596] D------N---- \--* LCL_VAR bool V37 tmp28 [ 0] 26 (0x01a) br.s impImportBlockPending for BB42 ----------- Statements (and blocks) added due to the inlining of call [000042] ----------- Arguments setup: [000602] ------------ * STMT void (IL 0x02A... ???) [000047] x----------- | /--* OBJ(16) struct [000046] L----------- | | \--* ADDR byref [000040] ------------ | | \--* LCL_VAR struct V03 loc1 [000601] -A------R--- \--* ASG struct (copy) [000599] D----------- \--* LCL_VAR struct V32 tmp23 [000606] ------------ * STMT void (IL 0x02A... ???) [000044] x----------- | /--* OBJ(16) struct [000043] L----------- | | \--* ADDR byref [000041] ------------ | | \--* LCL_VAR struct V00 arg0 [000605] -A------R--- \--* ASG struct (copy) [000603] D----------- \--* LCL_VAR struct V33 tmp24 Zero init inlinee locals: [000610] ------------ * STMT void (IL 0x02A... ???) [000607] ------------ | /--* CNS_INT int 0 [000609] -A---------- \--* ASG bool [000608] D------N---- \--* LCL_VAR bool V35 tmp26 [000614] ------------ * STMT void (IL 0x02A... ???) [000611] ------------ | /--* CNS_INT int 0 [000613] -A---------- \--* ASG bool [000612] D------N---- \--* LCL_VAR bool V37 tmp28 [000618] ------------ * STMT void (IL 0x02A... ???) [000615] ------------ | /--* CNS_INT int 0 [000617] -A---------- \--* ASG bool [000616] D------N---- \--* LCL_VAR bool V36 tmp27 Inlinee method body:New Basic Block BB43 [0042] created. Convert bbJumpKind of BB42 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB37 [0036] 1 1 [02A..02B)-> BB39 ( cond ) i BB38 [0037] 1 0.50 [02A..02B)-> BB42 (always) i BB39 [0038] 1 0.50 [02A..02B)-> BB41 ( cond ) i BB40 [0039] 1 0.50 [02A..02B)-> BB42 (always) i BB41 [0040] 1 0.50 [02A..02B) i BB42 [0041] 3 1 [02A..02B) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB37 [02A..02B) -> BB39 (cond), preds={} succs={BB38,BB39} ***** BB37, stmt 1 [000533] ------------ * STMT void (IL 0x02A... ???) [000532] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000531] L----------- this in rcx \--* ADDR byref [000530] ------------ \--* LCL_VAR struct V32 tmp23 ***** BB37, stmt 2 [000541] ------------ * STMT void (IL 0x02A... ???) [000534] --C--------- | /--* RET_EXPR int (inl return from call [000532]) [000540] -AC--------- \--* ASG int [000539] D------N---- \--* LCL_VAR int V34 tmp25 ***** BB37, stmt 3 [000538] ------------ * STMT void (IL 0x02A... ???) [000537] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000536] L----------- this in rcx \--* ADDR byref [000535] ------------ \--* LCL_VAR struct V33 tmp24 ***** BB37, stmt 4 [000549] ------------ * STMT void (IL 0x02A... ???) [000545] ------------ | /--* CNS_INT int 0 [000546] --C--------- | /--* EQ int [000543] --C--------- | | | /--* RET_EXPR int (inl return from call [000537]) [000544] --C--------- | | \--* EQ int [000542] ------------ | | \--* LCL_VAR int V34 tmp25 [000548] -AC--------- \--* ASG bool [000547] D------N---- \--* LCL_VAR bool V35 tmp26 ***** BB37, stmt 5 [000554] ------------ * STMT void (IL 0x02A... ???) [000553] ------------ \--* JTRUE void [000551] ------------ | /--* CNS_INT int 0 [000552] ------------ \--* EQ int [000550] ------------ \--* LCL_VAR int V35 tmp26 ------------ BB38 [02A..02B) -> BB42 (always), preds={} succs={BB42} ***** BB38, stmt 6 [000598] ------------ * STMT void (IL 0x02A... ???) [000595] ------------ | /--* CNS_INT int 0 [000597] -A---------- \--* ASG bool [000596] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB39 [02A..02B) -> BB41 (cond), preds={} succs={BB40,BB41} ***** BB39, stmt 7 [000559] ------------ * STMT void (IL 0x02A... ???) [000558] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000557] L----------- this in rcx \--* ADDR byref [000556] ------------ \--* LCL_VAR struct V33 tmp24 ***** BB39, stmt 8 [000565] ------------ * STMT void (IL 0x02A... ???) [000561] ------------ | /--* CNS_INT int 0 [000562] --C--------- | /--* EQ int [000560] --C--------- | | \--* RET_EXPR int (inl return from call [000558]) [000564] -AC--------- \--* ASG bool [000563] D------N---- \--* LCL_VAR bool V36 tmp27 ***** BB39, stmt 9 [000570] ------------ * STMT void (IL 0x02A... ???) [000569] ------------ \--* JTRUE void [000567] ------------ | /--* CNS_INT int 0 [000568] ------------ \--* EQ int [000566] ------------ \--* LCL_VAR int V36 tmp27 ------------ BB40 [02A..02B) -> BB42 (always), preds={} succs={BB42} ***** BB40, stmt 10 [000593] ------------ * STMT void (IL 0x02A... ???) [000590] ------------ | /--* CNS_INT int 1 [000592] -A---------- \--* ASG bool [000591] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB41 [02A..02B), preds={} succs={BB42} ***** BB41, stmt 11 [000585] ------------ * STMT void (IL 0x02A... ???) [000581] ------------ | /--* CNS_INT int 0 [000582] --C-G------- | /--* EQ int [000574] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000579] x----------- arg0 | | +--* OBJ(16) struct [000578] L----------- | | | \--* ADDR byref [000572] ------------ | | | \--* LCL_VAR struct V32 tmp23 [000576] x----------- arg1 | | \--* OBJ(16) struct [000575] L----------- | | \--* ADDR byref [000573] ------------ | | \--* LCL_VAR struct V33 tmp24 [000584] -AC-G------- \--* ASG bool [000583] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB42 [02A..02B), preds={} succs={BB43} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000042] is [000588] ------------ * CAST int <- bool <- int [000587] ------------ \--* LCL_VAR int V37 tmp28 Successfully inlined System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool (61 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000533] in BB37: [000533] ------------ * STMT void (IL 0x02A... ???) [000532] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000531] L----------- this in rcx \--* ADDR byref [000530] ------------ \--* LCL_VAR struct V32 tmp23 thisArg: is a constant is byref to a struct local [000531] L----------- * ADDR byref [000530] ------------ \--* LCL_VAR struct V32 tmp23 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB44 [0043] created. BB44 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB44 [0043] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB44 Importing BB44 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 38 (V38 tmp29) (a long lifetime temp) called for Inline stloc first use temp. [000626] ------------ * STMT void [000623] ------------ | /--* FIELD int _length [000621] L----------- | | \--* ADDR byref [000622] ------------ | | \--* LCL_VAR struct V32 tmp23 [000625] -A---------- \--* ASG int [000624] D------N---- \--* LCL_VAR int V38 tmp29 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000627] ------------ * LCL_VAR int V38 tmp29 Inlinee Return expression (after normalization) => [000627] ------------ * LCL_VAR int V38 tmp29 ----------- Statements (and blocks) added due to the inlining of call [000532] ----------- Arguments setup: Zero init inlinee locals: [000631] ------------ * STMT void (IL 0x02A... ???) [000628] ------------ | /--* CNS_INT int 0 [000630] -A---------- \--* ASG int [000629] D------N---- \--* LCL_VAR int V38 tmp29 Inlinee method body: [000626] ------------ * STMT void (IL 0x02A... ???) [000623] ------------ | /--* FIELD int _length [000621] L----------- | | \--* ADDR byref [000622] ------------ | | \--* LCL_VAR struct V32 tmp23 [000625] -A---------- \--* ASG int [000624] D------N---- \--* LCL_VAR int V38 tmp29 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000532] is [000627] ------------ * LCL_VAR int V38 tmp29 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000534] with [000627] [000534] --C--------- * RET_EXPR int (inl return from call [000627]) Inserting the inline return expression [000627] ------------ * LCL_VAR int V38 tmp29 Expanding INLINE_CANDIDATE in statement [000538] in BB37: [000538] ------------ * STMT void (IL 0x02A... ???) [000537] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000536] L----------- this in rcx \--* ADDR byref [000535] ------------ \--* LCL_VAR struct V33 tmp24 thisArg: is a constant is byref to a struct local [000536] L----------- * ADDR byref [000535] ------------ \--* LCL_VAR struct V33 tmp24 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB45 [0044] created. BB45 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB45 [0044] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB45 Importing BB45 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 39 (V39 tmp30) (a long lifetime temp) called for Inline stloc first use temp. [000639] ------------ * STMT void [000636] ------------ | /--* FIELD int _length [000634] L----------- | | \--* ADDR byref [000635] ------------ | | \--* LCL_VAR struct V33 tmp24 [000638] -A---------- \--* ASG int [000637] D------N---- \--* LCL_VAR int V39 tmp30 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000640] ------------ * LCL_VAR int V39 tmp30 Inlinee Return expression (after normalization) => [000640] ------------ * LCL_VAR int V39 tmp30 ----------- Statements (and blocks) added due to the inlining of call [000537] ----------- Arguments setup: Zero init inlinee locals: [000644] ------------ * STMT void (IL 0x02A... ???) [000641] ------------ | /--* CNS_INT int 0 [000643] -A---------- \--* ASG int [000642] D------N---- \--* LCL_VAR int V39 tmp30 Inlinee method body: [000639] ------------ * STMT void (IL 0x02A... ???) [000636] ------------ | /--* FIELD int _length [000634] L----------- | | \--* ADDR byref [000635] ------------ | | \--* LCL_VAR struct V33 tmp24 [000638] -A---------- \--* ASG int [000637] D------N---- \--* LCL_VAR int V39 tmp30 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000537] is [000640] ------------ * LCL_VAR int V39 tmp30 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000543] with [000640] [000543] --C--------- * RET_EXPR int (inl return from call [000640]) Inserting the inline return expression [000640] ------------ * LCL_VAR int V39 tmp30 Expanding INLINE_CANDIDATE in statement [000559] in BB39: [000559] ------------ * STMT void (IL 0x02A... ???) [000558] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000557] L----------- this in rcx \--* ADDR byref [000556] ------------ \--* LCL_VAR struct V33 tmp24 thisArg: is a constant is byref to a struct local [000557] L----------- * ADDR byref [000556] ------------ \--* LCL_VAR struct V33 tmp24 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB46 [0045] created. BB46 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB46 [0045] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB46 Importing BB46 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 40 (V40 tmp31) (a long lifetime temp) called for Inline stloc first use temp. [000652] ------------ * STMT void [000649] ------------ | /--* FIELD int _length [000647] L----------- | | \--* ADDR byref [000648] ------------ | | \--* LCL_VAR struct V33 tmp24 [000651] -A---------- \--* ASG int [000650] D------N---- \--* LCL_VAR int V40 tmp31 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000653] ------------ * LCL_VAR int V40 tmp31 Inlinee Return expression (after normalization) => [000653] ------------ * LCL_VAR int V40 tmp31 ----------- Statements (and blocks) added due to the inlining of call [000558] ----------- Arguments setup: Zero init inlinee locals: [000657] ------------ * STMT void (IL 0x02A... ???) [000654] ------------ | /--* CNS_INT int 0 [000656] -A---------- \--* ASG int [000655] D------N---- \--* LCL_VAR int V40 tmp31 Inlinee method body: [000652] ------------ * STMT void (IL 0x02A... ???) [000649] ------------ | /--* FIELD int _length [000647] L----------- | | \--* ADDR byref [000648] ------------ | | \--* LCL_VAR struct V33 tmp24 [000651] -A---------- \--* ASG int [000650] D------N---- \--* LCL_VAR int V40 tmp31 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000558] is [000653] ------------ * LCL_VAR int V40 tmp31 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000560] with [000653] [000560] --C--------- * RET_EXPR int (inl return from call [000653]) Inserting the inline return expression [000653] ------------ * LCL_VAR int V40 tmp31 Replacing the return expression placeholder [000050] with [000588] [000050] --C--------- * RET_EXPR int (inl return from call [000588]) Inserting the inline return expression [000588] ------------ * CAST int <- bool <- int [000587] ------------ \--* LCL_VAR int V37 tmp28 Expanding INLINE_CANDIDATE in statement [000079] in BB05: [000079] ------------ * STMT void (IL 0x047...0x04E) [000072] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000077] x----------- arg0 +--* OBJ(16) struct [000076] L----------- | \--* ADDR byref [000070] ------------ | \--* LCL_VAR struct V02 loc0 [000074] x----------- arg1 \--* OBJ(16) struct [000073] L----------- \--* ADDR byref [000071] ------------ \--* LCL_VAR struct V00 arg0 Argument #0: [000077] x----------- * OBJ(16) struct [000076] L----------- \--* ADDR byref [000070] ------------ \--* LCL_VAR struct V02 loc0 Argument #1: [000074] x----------- * OBJ(16) struct [000073] L----------- \--* ADDR byref [000071] ------------ \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool : IL to import: IL_0000 00 nop IL_0001 0f 00 ldarga.s 0x0 IL_0003 28 55 00 00 0a call 0xA000055 IL_0008 0f 01 ldarga.s 0x1 IL_000a 28 55 00 00 0a call 0xA000055 IL_000f fe 01 ceq IL_0011 16 ldc.i4.0 IL_0012 fe 01 ceq IL_0014 0a stloc.0 IL_0015 06 ldloc.0 IL_0016 2c 04 brfalse.s 4 (IL_001c) IL_0018 16 ldc.i4.0 IL_0019 0b stloc.1 IL_001a 2b 1f br.s 31 (IL_003b) IL_001c 0f 01 ldarga.s 0x1 IL_001e 28 55 00 00 0a call 0xA000055 IL_0023 16 ldc.i4.0 IL_0024 fe 01 ceq IL_0026 0c stloc.2 IL_0027 08 ldloc.2 IL_0028 2c 04 brfalse.s 4 (IL_002e) IL_002a 17 ldc.i4.1 IL_002b 0b stloc.1 IL_002c 2b 0d br.s 13 (IL_003b) IL_002e 02 ldarg.0 IL_002f 03 ldarg.1 IL_0030 28 ff 20 00 06 call 0x60020FF IL_0035 16 ldc.i4.0 IL_0036 fe 01 ceq IL_0038 0b stloc.1 IL_0039 2b 00 br.s 0 (IL_003b) IL_003b 07 ldloc.1 IL_003c 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool Jump targets: IL_001c IL_002e IL_003b multi New Basic Block BB47 [0046] created. BB47 [000..018) New Basic Block BB48 [0047] created. BB48 [018..01C) New Basic Block BB49 [0048] created. BB49 [01C..02A) New Basic Block BB50 [0049] created. BB50 [02A..02E) New Basic Block BB51 [0050] created. BB51 [02E..03B) New Basic Block BB52 [0051] created. BB52 [03B..03D) Basic block list for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB47 [0046] 1 1 [000..018)-> BB49 ( cond ) BB48 [0047] 1 1 [018..01C)-> BB52 (always) BB49 [0048] 1 1 [01C..02A)-> BB51 ( cond ) BB50 [0049] 1 1 [02A..02E)-> BB52 (always) BB51 [0050] 1 1 [02E..03B) BB52 [0051] 3 1 [03B..03D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool impImportBlockPending for BB47 Importing BB47 (PC=000) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarga.s 0 lvaGrabTemp returning 41 (V41 tmp32) called for Inlining Arg. [ 1] 3 (0x003) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000663] ------------ * STMT void [000662] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000661] L----------- this in rcx \--* ADDR byref [000660] ------------ \--* LCL_VAR struct V41 tmp32 [ 1] 8 (0x008) ldarga.s 1 lvaGrabTemp returning 42 (V42 tmp33) called for Inlining Arg. [ 2] 10 (0x00a) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 43 (V43 tmp34) called for impAppendStmt. [000671] ------------ * STMT void [000664] --C--------- | /--* RET_EXPR int (inl return from call [000662]) [000670] -AC--------- \--* ASG int [000669] D------N---- \--* LCL_VAR int V43 tmp34 [000668] ------------ * STMT void [000667] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000666] L----------- this in rcx \--* ADDR byref [000665] ------------ \--* LCL_VAR struct V42 tmp33 [ 2] 15 (0x00f) ceq [ 1] 17 (0x011) ldc.i4.0 0 [ 2] 18 (0x012) ceq [ 1] 20 (0x014) stloc.0 lvaGrabTemp returning 44 (V44 tmp35) (a long lifetime temp) called for Inline stloc first use temp. [000679] ------------ * STMT void [000675] ------------ | /--* CNS_INT int 0 [000676] --C--------- | /--* EQ int [000673] --C--------- | | | /--* RET_EXPR int (inl return from call [000667]) [000674] --C--------- | | \--* EQ int [000672] ------------ | | \--* LCL_VAR int V43 tmp34 [000678] -AC--------- \--* ASG bool [000677] D------N---- \--* LCL_VAR bool V44 tmp35 [ 0] 21 (0x015) ldloc.0 [ 1] 22 (0x016) brfalse.s [000684] ------------ * STMT void [000683] ------------ \--* JTRUE void [000681] ------------ | /--* CNS_INT int 0 [000682] ------------ \--* EQ int [000680] ------------ \--* LCL_VAR int V44 tmp35 impImportBlockPending for BB48 impImportBlockPending for BB49 Importing BB49 (PC=028) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 28 (0x01c) ldarga.s 1 [ 1] 30 (0x01e) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000689] ------------ * STMT void [000688] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000687] L----------- this in rcx \--* ADDR byref [000686] ------------ \--* LCL_VAR struct V42 tmp33 [ 1] 35 (0x023) ldc.i4.0 0 [ 2] 36 (0x024) ceq [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 45 (V45 tmp36) (a long lifetime temp) called for Inline stloc first use temp. [000695] ------------ * STMT void [000691] ------------ | /--* CNS_INT int 0 [000692] --C--------- | /--* EQ int [000690] --C--------- | | \--* RET_EXPR int (inl return from call [000688]) [000694] -AC--------- \--* ASG bool [000693] D------N---- \--* LCL_VAR bool V45 tmp36 [ 0] 39 (0x027) ldloc.2 [ 1] 40 (0x028) brfalse.s [000700] ------------ * STMT void [000699] ------------ \--* JTRUE void [000697] ------------ | /--* CNS_INT int 0 [000698] ------------ \--* EQ int [000696] ------------ \--* LCL_VAR int V45 tmp36 impImportBlockPending for BB50 impImportBlockPending for BB51 Importing BB51 (PC=046) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 46 (0x02e) ldarg.0 [ 1] 47 (0x02f) ldarg.1 [ 2] 48 (0x030) call 060020FF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000703] ------------ * LCL_VAR struct V42 tmp33 resulting tree: [000706] x----------- * OBJ(16) struct [000705] L----------- \--* ADDR byref [000703] ------------ \--* LCL_VAR struct V42 tmp33 Calling impNormStructVal on: [000702] ------------ * LCL_VAR struct V41 tmp32 resulting tree: [000709] x----------- * OBJ(16) struct [000708] L----------- \--* ADDR byref [000702] ------------ \--* LCL_VAR struct V41 tmp32 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' calling 'System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int' INLINER: Marking System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 53 (0x035) ldc.i4.0 0 [ 2] 54 (0x036) ceq [ 1] 56 (0x038) stloc.1 lvaGrabTemp returning 46 (V46 tmp37) (a long lifetime temp) called for Inline stloc first use temp. [000715] ------------ * STMT void [000711] ------------ | /--* CNS_INT int 0 [000712] --C-G------- | /--* EQ int [000704] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000709] x----------- arg0 | | +--* OBJ(16) struct [000708] L----------- | | | \--* ADDR byref [000702] ------------ | | | \--* LCL_VAR struct V41 tmp32 [000706] x----------- arg1 | | \--* OBJ(16) struct [000705] L----------- | | \--* ADDR byref [000703] ------------ | | \--* LCL_VAR struct V42 tmp33 [000714] -AC-G------- \--* ASG bool [000713] D------N---- \--* LCL_VAR bool V46 tmp37 [ 0] 57 (0x039) br.s impImportBlockPending for BB52 Importing BB52 (PC=059) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 59 (0x03b) ldloc.1 [ 1] 60 (0x03c) ret Inlinee Return expression (before normalization) => [000717] ------------ * LCL_VAR int V46 tmp37 Inlinee Return expression (after normalization) => [000718] ------------ * CAST int <- bool <- int [000717] ------------ \--* LCL_VAR int V46 tmp37 Importing BB50 (PC=042) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 42 (0x02a) ldc.i4.1 1 [ 1] 43 (0x02b) stloc.1 [000723] ------------ * STMT void [000720] ------------ | /--* CNS_INT int 1 [000722] -A---------- \--* ASG bool [000721] D------N---- \--* LCL_VAR bool V46 tmp37 [ 0] 44 (0x02c) br.s impImportBlockPending for BB52 Importing BB48 (PC=024) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 24 (0x018) ldc.i4.0 0 [ 1] 25 (0x019) stloc.1 [000728] ------------ * STMT void [000725] ------------ | /--* CNS_INT int 0 [000727] -A---------- \--* ASG bool [000726] D------N---- \--* LCL_VAR bool V46 tmp37 [ 0] 26 (0x01a) br.s impImportBlockPending for BB52 ----------- Statements (and blocks) added due to the inlining of call [000072] ----------- Arguments setup: [000732] ------------ * STMT void (IL 0x047... ???) [000077] x----------- | /--* OBJ(16) struct [000076] L----------- | | \--* ADDR byref [000070] ------------ | | \--* LCL_VAR struct V02 loc0 [000731] -A------R--- \--* ASG struct (copy) [000729] D----------- \--* LCL_VAR struct V41 tmp32 [000736] ------------ * STMT void (IL 0x047... ???) [000074] x----------- | /--* OBJ(16) struct [000073] L----------- | | \--* ADDR byref [000071] ------------ | | \--* LCL_VAR struct V00 arg0 [000735] -A------R--- \--* ASG struct (copy) [000733] D----------- \--* LCL_VAR struct V42 tmp33 Zero init inlinee locals: [000740] ------------ * STMT void (IL 0x047... ???) [000737] ------------ | /--* CNS_INT int 0 [000739] -A---------- \--* ASG bool [000738] D------N---- \--* LCL_VAR bool V44 tmp35 [000744] ------------ * STMT void (IL 0x047... ???) [000741] ------------ | /--* CNS_INT int 0 [000743] -A---------- \--* ASG bool [000742] D------N---- \--* LCL_VAR bool V46 tmp37 [000748] ------------ * STMT void (IL 0x047... ???) [000745] ------------ | /--* CNS_INT int 0 [000747] -A---------- \--* ASG bool [000746] D------N---- \--* LCL_VAR bool V45 tmp36 Inlinee method body:New Basic Block BB53 [0052] created. Convert bbJumpKind of BB52 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB47 [0046] 1 1 [047..048)-> BB49 ( cond ) i BB48 [0047] 1 0.50 [047..048)-> BB52 (always) i BB49 [0048] 1 0.50 [047..048)-> BB51 ( cond ) i BB50 [0049] 1 0.50 [047..048)-> BB52 (always) i BB51 [0050] 1 0.50 [047..048) i BB52 [0051] 3 1 [047..048) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB47 [047..048) -> BB49 (cond), preds={} succs={BB48,BB49} ***** BB47, stmt 1 [000663] ------------ * STMT void (IL 0x047... ???) [000662] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000661] L----------- this in rcx \--* ADDR byref [000660] ------------ \--* LCL_VAR struct V41 tmp32 ***** BB47, stmt 2 [000671] ------------ * STMT void (IL 0x047... ???) [000664] --C--------- | /--* RET_EXPR int (inl return from call [000662]) [000670] -AC--------- \--* ASG int [000669] D------N---- \--* LCL_VAR int V43 tmp34 ***** BB47, stmt 3 [000668] ------------ * STMT void (IL 0x047... ???) [000667] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000666] L----------- this in rcx \--* ADDR byref [000665] ------------ \--* LCL_VAR struct V42 tmp33 ***** BB47, stmt 4 [000679] ------------ * STMT void (IL 0x047... ???) [000675] ------------ | /--* CNS_INT int 0 [000676] --C--------- | /--* EQ int [000673] --C--------- | | | /--* RET_EXPR int (inl return from call [000667]) [000674] --C--------- | | \--* EQ int [000672] ------------ | | \--* LCL_VAR int V43 tmp34 [000678] -AC--------- \--* ASG bool [000677] D------N---- \--* LCL_VAR bool V44 tmp35 ***** BB47, stmt 5 [000684] ------------ * STMT void (IL 0x047... ???) [000683] ------------ \--* JTRUE void [000681] ------------ | /--* CNS_INT int 0 [000682] ------------ \--* EQ int [000680] ------------ \--* LCL_VAR int V44 tmp35 ------------ BB48 [047..048) -> BB52 (always), preds={} succs={BB52} ***** BB48, stmt 6 [000728] ------------ * STMT void (IL 0x047... ???) [000725] ------------ | /--* CNS_INT int 0 [000727] -A---------- \--* ASG bool [000726] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB49 [047..048) -> BB51 (cond), preds={} succs={BB50,BB51} ***** BB49, stmt 7 [000689] ------------ * STMT void (IL 0x047... ???) [000688] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000687] L----------- this in rcx \--* ADDR byref [000686] ------------ \--* LCL_VAR struct V42 tmp33 ***** BB49, stmt 8 [000695] ------------ * STMT void (IL 0x047... ???) [000691] ------------ | /--* CNS_INT int 0 [000692] --C--------- | /--* EQ int [000690] --C--------- | | \--* RET_EXPR int (inl return from call [000688]) [000694] -AC--------- \--* ASG bool [000693] D------N---- \--* LCL_VAR bool V45 tmp36 ***** BB49, stmt 9 [000700] ------------ * STMT void (IL 0x047... ???) [000699] ------------ \--* JTRUE void [000697] ------------ | /--* CNS_INT int 0 [000698] ------------ \--* EQ int [000696] ------------ \--* LCL_VAR int V45 tmp36 ------------ BB50 [047..048) -> BB52 (always), preds={} succs={BB52} ***** BB50, stmt 10 [000723] ------------ * STMT void (IL 0x047... ???) [000720] ------------ | /--* CNS_INT int 1 [000722] -A---------- \--* ASG bool [000721] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB51 [047..048), preds={} succs={BB52} ***** BB51, stmt 11 [000715] ------------ * STMT void (IL 0x047... ???) [000711] ------------ | /--* CNS_INT int 0 [000712] --C-G------- | /--* EQ int [000704] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000709] x----------- arg0 | | +--* OBJ(16) struct [000708] L----------- | | | \--* ADDR byref [000702] ------------ | | | \--* LCL_VAR struct V41 tmp32 [000706] x----------- arg1 | | \--* OBJ(16) struct [000705] L----------- | | \--* ADDR byref [000703] ------------ | | \--* LCL_VAR struct V42 tmp33 [000714] -AC-G------- \--* ASG bool [000713] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB52 [047..048), preds={} succs={BB53} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000072] is [000718] ------------ * CAST int <- bool <- int [000717] ------------ \--* LCL_VAR int V46 tmp37 Successfully inlined System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool (61 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000663] in BB47: [000663] ------------ * STMT void (IL 0x047... ???) [000662] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000661] L----------- this in rcx \--* ADDR byref [000660] ------------ \--* LCL_VAR struct V41 tmp32 thisArg: is a constant is byref to a struct local [000661] L----------- * ADDR byref [000660] ------------ \--* LCL_VAR struct V41 tmp32 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB54 [0053] created. BB54 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB54 [0053] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB54 Importing BB54 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 47 (V47 tmp38) (a long lifetime temp) called for Inline stloc first use temp. [000756] ------------ * STMT void [000753] ------------ | /--* FIELD int _length [000751] L----------- | | \--* ADDR byref [000752] ------------ | | \--* LCL_VAR struct V41 tmp32 [000755] -A---------- \--* ASG int [000754] D------N---- \--* LCL_VAR int V47 tmp38 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000757] ------------ * LCL_VAR int V47 tmp38 Inlinee Return expression (after normalization) => [000757] ------------ * LCL_VAR int V47 tmp38 ----------- Statements (and blocks) added due to the inlining of call [000662] ----------- Arguments setup: Zero init inlinee locals: [000761] ------------ * STMT void (IL 0x047... ???) [000758] ------------ | /--* CNS_INT int 0 [000760] -A---------- \--* ASG int [000759] D------N---- \--* LCL_VAR int V47 tmp38 Inlinee method body: [000756] ------------ * STMT void (IL 0x047... ???) [000753] ------------ | /--* FIELD int _length [000751] L----------- | | \--* ADDR byref [000752] ------------ | | \--* LCL_VAR struct V41 tmp32 [000755] -A---------- \--* ASG int [000754] D------N---- \--* LCL_VAR int V47 tmp38 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000662] is [000757] ------------ * LCL_VAR int V47 tmp38 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000664] with [000757] [000664] --C--------- * RET_EXPR int (inl return from call [000757]) Inserting the inline return expression [000757] ------------ * LCL_VAR int V47 tmp38 Expanding INLINE_CANDIDATE in statement [000668] in BB47: [000668] ------------ * STMT void (IL 0x047... ???) [000667] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000666] L----------- this in rcx \--* ADDR byref [000665] ------------ \--* LCL_VAR struct V42 tmp33 thisArg: is a constant is byref to a struct local [000666] L----------- * ADDR byref [000665] ------------ \--* LCL_VAR struct V42 tmp33 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB55 [0054] created. BB55 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB55 [0054] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB55 Importing BB55 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 48 (V48 tmp39) (a long lifetime temp) called for Inline stloc first use temp. [000769] ------------ * STMT void [000766] ------------ | /--* FIELD int _length [000764] L----------- | | \--* ADDR byref [000765] ------------ | | \--* LCL_VAR struct V42 tmp33 [000768] -A---------- \--* ASG int [000767] D------N---- \--* LCL_VAR int V48 tmp39 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000770] ------------ * LCL_VAR int V48 tmp39 Inlinee Return expression (after normalization) => [000770] ------------ * LCL_VAR int V48 tmp39 ----------- Statements (and blocks) added due to the inlining of call [000667] ----------- Arguments setup: Zero init inlinee locals: [000774] ------------ * STMT void (IL 0x047... ???) [000771] ------------ | /--* CNS_INT int 0 [000773] -A---------- \--* ASG int [000772] D------N---- \--* LCL_VAR int V48 tmp39 Inlinee method body: [000769] ------------ * STMT void (IL 0x047... ???) [000766] ------------ | /--* FIELD int _length [000764] L----------- | | \--* ADDR byref [000765] ------------ | | \--* LCL_VAR struct V42 tmp33 [000768] -A---------- \--* ASG int [000767] D------N---- \--* LCL_VAR int V48 tmp39 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000667] is [000770] ------------ * LCL_VAR int V48 tmp39 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000673] with [000770] [000673] --C--------- * RET_EXPR int (inl return from call [000770]) Inserting the inline return expression [000770] ------------ * LCL_VAR int V48 tmp39 Expanding INLINE_CANDIDATE in statement [000689] in BB49: [000689] ------------ * STMT void (IL 0x047... ???) [000688] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000687] L----------- this in rcx \--* ADDR byref [000686] ------------ \--* LCL_VAR struct V42 tmp33 thisArg: is a constant is byref to a struct local [000687] L----------- * ADDR byref [000686] ------------ \--* LCL_VAR struct V42 tmp33 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB56 [0055] created. BB56 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB56 [0055] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB56 Importing BB56 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 49 (V49 tmp40) (a long lifetime temp) called for Inline stloc first use temp. [000782] ------------ * STMT void [000779] ------------ | /--* FIELD int _length [000777] L----------- | | \--* ADDR byref [000778] ------------ | | \--* LCL_VAR struct V42 tmp33 [000781] -A---------- \--* ASG int [000780] D------N---- \--* LCL_VAR int V49 tmp40 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000783] ------------ * LCL_VAR int V49 tmp40 Inlinee Return expression (after normalization) => [000783] ------------ * LCL_VAR int V49 tmp40 ----------- Statements (and blocks) added due to the inlining of call [000688] ----------- Arguments setup: Zero init inlinee locals: [000787] ------------ * STMT void (IL 0x047... ???) [000784] ------------ | /--* CNS_INT int 0 [000786] -A---------- \--* ASG int [000785] D------N---- \--* LCL_VAR int V49 tmp40 Inlinee method body: [000782] ------------ * STMT void (IL 0x047... ???) [000779] ------------ | /--* FIELD int _length [000777] L----------- | | \--* ADDR byref [000778] ------------ | | \--* LCL_VAR struct V42 tmp33 [000781] -A---------- \--* ASG int [000780] D------N---- \--* LCL_VAR int V49 tmp40 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000688] is [000783] ------------ * LCL_VAR int V49 tmp40 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000690] with [000783] [000690] --C--------- * RET_EXPR int (inl return from call [000783]) Inserting the inline return expression [000783] ------------ * LCL_VAR int V49 tmp40 Replacing the return expression placeholder [000080] with [000718] [000080] --C--------- * RET_EXPR int (inl return from call [000718]) Inserting the inline return expression [000718] ------------ * CAST int <- bool <- int [000717] ------------ \--* LCL_VAR int V46 tmp37 Expanding INLINE_CANDIDATE in statement [000100] in BB07: [000100] ------------ * STMT void (IL 0x05C...0x063) [000093] I-C-G------- \--* CALL int System.MemoryExtensions.EqualsOrdinalIgnoreCase (exactContextHnd=0x0000000000423089) [000098] x----------- arg0 +--* OBJ(16) struct [000097] L----------- | \--* ADDR byref [000091] ------------ | \--* LCL_VAR struct V03 loc1 [000095] x----------- arg1 \--* OBJ(16) struct [000094] L----------- \--* ADDR byref [000092] ------------ \--* LCL_VAR struct V00 arg0 Argument #0: [000098] x----------- * OBJ(16) struct [000097] L----------- \--* ADDR byref [000091] ------------ \--* LCL_VAR struct V03 loc1 Argument #1: [000095] x----------- * OBJ(16) struct [000094] L----------- \--* ADDR byref [000092] ------------ \--* LCL_VAR struct V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool set to 0x0000000000423089: Invoking compiler for the inlinee method System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool : IL to import: IL_0000 00 nop IL_0001 0f 00 ldarga.s 0x0 IL_0003 28 55 00 00 0a call 0xA000055 IL_0008 0f 01 ldarga.s 0x1 IL_000a 28 55 00 00 0a call 0xA000055 IL_000f fe 01 ceq IL_0011 16 ldc.i4.0 IL_0012 fe 01 ceq IL_0014 0a stloc.0 IL_0015 06 ldloc.0 IL_0016 2c 04 brfalse.s 4 (IL_001c) IL_0018 16 ldc.i4.0 IL_0019 0b stloc.1 IL_001a 2b 1f br.s 31 (IL_003b) IL_001c 0f 01 ldarga.s 0x1 IL_001e 28 55 00 00 0a call 0xA000055 IL_0023 16 ldc.i4.0 IL_0024 fe 01 ceq IL_0026 0c stloc.2 IL_0027 08 ldloc.2 IL_0028 2c 04 brfalse.s 4 (IL_002e) IL_002a 17 ldc.i4.1 IL_002b 0b stloc.1 IL_002c 2b 0d br.s 13 (IL_003b) IL_002e 02 ldarg.0 IL_002f 03 ldarg.1 IL_0030 28 ff 20 00 06 call 0x60020FF IL_0035 16 ldc.i4.0 IL_0036 fe 01 ceq IL_0038 0b stloc.1 IL_0039 2b 00 br.s 0 (IL_003b) IL_003b 07 ldloc.1 IL_003c 2a ret INLINER impTokenLookupContextHandle for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool is 0x0000000000423089. *************** In fgFindBasicBlocks() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool Jump targets: IL_001c IL_002e IL_003b multi New Basic Block BB57 [0056] created. BB57 [000..018) New Basic Block BB58 [0057] created. BB58 [018..01C) New Basic Block BB59 [0058] created. BB59 [01C..02A) New Basic Block BB60 [0059] created. BB60 [02A..02E) New Basic Block BB61 [0060] created. BB61 [02E..03B) New Basic Block BB62 [0061] created. BB62 [03B..03D) Basic block list for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB57 [0056] 1 1 [000..018)-> BB59 ( cond ) BB58 [0057] 1 1 [018..01C)-> BB62 (always) BB59 [0058] 1 1 [01C..02A)-> BB61 ( cond ) BB60 [0059] 1 1 [02A..02E)-> BB62 (always) BB61 [0060] 1 1 [02E..03B) BB62 [0061] 3 1 [03B..03D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool impImportBlockPending for BB57 Importing BB57 (PC=000) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarga.s 0 lvaGrabTemp returning 50 (V50 tmp41) called for Inlining Arg. [ 1] 3 (0x003) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000793] ------------ * STMT void [000792] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000791] L----------- this in rcx \--* ADDR byref [000790] ------------ \--* LCL_VAR struct V50 tmp41 [ 1] 8 (0x008) ldarga.s 1 lvaGrabTemp returning 51 (V51 tmp42) called for Inlining Arg. [ 2] 10 (0x00a) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 52 (V52 tmp43) called for impAppendStmt. [000801] ------------ * STMT void [000794] --C--------- | /--* RET_EXPR int (inl return from call [000792]) [000800] -AC--------- \--* ASG int [000799] D------N---- \--* LCL_VAR int V52 tmp43 [000798] ------------ * STMT void [000797] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000796] L----------- this in rcx \--* ADDR byref [000795] ------------ \--* LCL_VAR struct V51 tmp42 [ 2] 15 (0x00f) ceq [ 1] 17 (0x011) ldc.i4.0 0 [ 2] 18 (0x012) ceq [ 1] 20 (0x014) stloc.0 lvaGrabTemp returning 53 (V53 tmp44) (a long lifetime temp) called for Inline stloc first use temp. [000809] ------------ * STMT void [000805] ------------ | /--* CNS_INT int 0 [000806] --C--------- | /--* EQ int [000803] --C--------- | | | /--* RET_EXPR int (inl return from call [000797]) [000804] --C--------- | | \--* EQ int [000802] ------------ | | \--* LCL_VAR int V52 tmp43 [000808] -AC--------- \--* ASG bool [000807] D------N---- \--* LCL_VAR bool V53 tmp44 [ 0] 21 (0x015) ldloc.0 [ 1] 22 (0x016) brfalse.s [000814] ------------ * STMT void [000813] ------------ \--* JTRUE void [000811] ------------ | /--* CNS_INT int 0 [000812] ------------ \--* EQ int [000810] ------------ \--* LCL_VAR int V53 tmp44 impImportBlockPending for BB58 impImportBlockPending for BB59 Importing BB59 (PC=028) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 28 (0x01c) ldarga.s 1 [ 1] 30 (0x01e) call 0A000055 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000819] ------------ * STMT void [000818] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000817] L----------- this in rcx \--* ADDR byref [000816] ------------ \--* LCL_VAR struct V51 tmp42 [ 1] 35 (0x023) ldc.i4.0 0 [ 2] 36 (0x024) ceq [ 1] 38 (0x026) stloc.2 lvaGrabTemp returning 54 (V54 tmp45) (a long lifetime temp) called for Inline stloc first use temp. [000825] ------------ * STMT void [000821] ------------ | /--* CNS_INT int 0 [000822] --C--------- | /--* EQ int [000820] --C--------- | | \--* RET_EXPR int (inl return from call [000818]) [000824] -AC--------- \--* ASG bool [000823] D------N---- \--* LCL_VAR bool V54 tmp45 [ 0] 39 (0x027) ldloc.2 [ 1] 40 (0x028) brfalse.s [000830] ------------ * STMT void [000829] ------------ \--* JTRUE void [000827] ------------ | /--* CNS_INT int 0 [000828] ------------ \--* EQ int [000826] ------------ \--* LCL_VAR int V54 tmp45 impImportBlockPending for BB60 impImportBlockPending for BB61 Importing BB61 (PC=046) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 46 (0x02e) ldarg.0 [ 1] 47 (0x02f) ldarg.1 [ 2] 48 (0x030) call 060020FF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000833] ------------ * LCL_VAR struct V51 tmp42 resulting tree: [000836] x----------- * OBJ(16) struct [000835] L----------- \--* ADDR byref [000833] ------------ \--* LCL_VAR struct V51 tmp42 Calling impNormStructVal on: [000832] ------------ * LCL_VAR struct V50 tmp41 resulting tree: [000839] x----------- * OBJ(16) struct [000838] L----------- \--* ADDR byref [000832] ------------ \--* LCL_VAR struct V50 tmp41 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' calling 'System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int' INLINER: Marking System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 53 (0x035) ldc.i4.0 0 [ 2] 54 (0x036) ceq [ 1] 56 (0x038) stloc.1 lvaGrabTemp returning 55 (V55 tmp46) (a long lifetime temp) called for Inline stloc first use temp. [000845] ------------ * STMT void [000841] ------------ | /--* CNS_INT int 0 [000842] --C-G------- | /--* EQ int [000834] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000839] x----------- arg0 | | +--* OBJ(16) struct [000838] L----------- | | | \--* ADDR byref [000832] ------------ | | | \--* LCL_VAR struct V50 tmp41 [000836] x----------- arg1 | | \--* OBJ(16) struct [000835] L----------- | | \--* ADDR byref [000833] ------------ | | \--* LCL_VAR struct V51 tmp42 [000844] -AC-G------- \--* ASG bool [000843] D------N---- \--* LCL_VAR bool V55 tmp46 [ 0] 57 (0x039) br.s impImportBlockPending for BB62 Importing BB62 (PC=059) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 59 (0x03b) ldloc.1 [ 1] 60 (0x03c) ret Inlinee Return expression (before normalization) => [000847] ------------ * LCL_VAR int V55 tmp46 Inlinee Return expression (after normalization) => [000848] ------------ * CAST int <- bool <- int [000847] ------------ \--* LCL_VAR int V55 tmp46 Importing BB60 (PC=042) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 42 (0x02a) ldc.i4.1 1 [ 1] 43 (0x02b) stloc.1 [000853] ------------ * STMT void [000850] ------------ | /--* CNS_INT int 1 [000852] -A---------- \--* ASG bool [000851] D------N---- \--* LCL_VAR bool V55 tmp46 [ 0] 44 (0x02c) br.s impImportBlockPending for BB62 Importing BB58 (PC=024) of 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' [ 0] 24 (0x018) ldc.i4.0 0 [ 1] 25 (0x019) stloc.1 [000858] ------------ * STMT void [000855] ------------ | /--* CNS_INT int 0 [000857] -A---------- \--* ASG bool [000856] D------N---- \--* LCL_VAR bool V55 tmp46 [ 0] 26 (0x01a) br.s impImportBlockPending for BB62 ----------- Statements (and blocks) added due to the inlining of call [000093] ----------- Arguments setup: [000862] ------------ * STMT void (IL 0x05C... ???) [000098] x----------- | /--* OBJ(16) struct [000097] L----------- | | \--* ADDR byref [000091] ------------ | | \--* LCL_VAR struct V03 loc1 [000861] -A------R--- \--* ASG struct (copy) [000859] D----------- \--* LCL_VAR struct V50 tmp41 [000866] ------------ * STMT void (IL 0x05C... ???) [000095] x----------- | /--* OBJ(16) struct [000094] L----------- | | \--* ADDR byref [000092] ------------ | | \--* LCL_VAR struct V00 arg0 [000865] -A------R--- \--* ASG struct (copy) [000863] D----------- \--* LCL_VAR struct V51 tmp42 Zero init inlinee locals: [000870] ------------ * STMT void (IL 0x05C... ???) [000867] ------------ | /--* CNS_INT int 0 [000869] -A---------- \--* ASG bool [000868] D------N---- \--* LCL_VAR bool V53 tmp44 [000874] ------------ * STMT void (IL 0x05C... ???) [000871] ------------ | /--* CNS_INT int 0 [000873] -A---------- \--* ASG bool [000872] D------N---- \--* LCL_VAR bool V55 tmp46 [000878] ------------ * STMT void (IL 0x05C... ???) [000875] ------------ | /--* CNS_INT int 0 [000877] -A---------- \--* ASG bool [000876] D------N---- \--* LCL_VAR bool V54 tmp45 Inlinee method body:New Basic Block BB63 [0062] created. Convert bbJumpKind of BB62 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB57 [0056] 1 1 [05C..05D)-> BB59 ( cond ) i BB58 [0057] 1 0.50 [05C..05D)-> BB62 (always) i BB59 [0058] 1 0.50 [05C..05D)-> BB61 ( cond ) i BB60 [0059] 1 0.50 [05C..05D)-> BB62 (always) i BB61 [0060] 1 0.50 [05C..05D) i BB62 [0061] 3 1 [05C..05D) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB57 [05C..05D) -> BB59 (cond), preds={} succs={BB58,BB59} ***** BB57, stmt 1 [000793] ------------ * STMT void (IL 0x05C... ???) [000792] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000791] L----------- this in rcx \--* ADDR byref [000790] ------------ \--* LCL_VAR struct V50 tmp41 ***** BB57, stmt 2 [000801] ------------ * STMT void (IL 0x05C... ???) [000794] --C--------- | /--* RET_EXPR int (inl return from call [000792]) [000800] -AC--------- \--* ASG int [000799] D------N---- \--* LCL_VAR int V52 tmp43 ***** BB57, stmt 3 [000798] ------------ * STMT void (IL 0x05C... ???) [000797] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000796] L----------- this in rcx \--* ADDR byref [000795] ------------ \--* LCL_VAR struct V51 tmp42 ***** BB57, stmt 4 [000809] ------------ * STMT void (IL 0x05C... ???) [000805] ------------ | /--* CNS_INT int 0 [000806] --C--------- | /--* EQ int [000803] --C--------- | | | /--* RET_EXPR int (inl return from call [000797]) [000804] --C--------- | | \--* EQ int [000802] ------------ | | \--* LCL_VAR int V52 tmp43 [000808] -AC--------- \--* ASG bool [000807] D------N---- \--* LCL_VAR bool V53 tmp44 ***** BB57, stmt 5 [000814] ------------ * STMT void (IL 0x05C... ???) [000813] ------------ \--* JTRUE void [000811] ------------ | /--* CNS_INT int 0 [000812] ------------ \--* EQ int [000810] ------------ \--* LCL_VAR int V53 tmp44 ------------ BB58 [05C..05D) -> BB62 (always), preds={} succs={BB62} ***** BB58, stmt 6 [000858] ------------ * STMT void (IL 0x05C... ???) [000855] ------------ | /--* CNS_INT int 0 [000857] -A---------- \--* ASG bool [000856] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB59 [05C..05D) -> BB61 (cond), preds={} succs={BB60,BB61} ***** BB59, stmt 7 [000819] ------------ * STMT void (IL 0x05C... ???) [000818] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000817] L----------- this in rcx \--* ADDR byref [000816] ------------ \--* LCL_VAR struct V51 tmp42 ***** BB59, stmt 8 [000825] ------------ * STMT void (IL 0x05C... ???) [000821] ------------ | /--* CNS_INT int 0 [000822] --C--------- | /--* EQ int [000820] --C--------- | | \--* RET_EXPR int (inl return from call [000818]) [000824] -AC--------- \--* ASG bool [000823] D------N---- \--* LCL_VAR bool V54 tmp45 ***** BB59, stmt 9 [000830] ------------ * STMT void (IL 0x05C... ???) [000829] ------------ \--* JTRUE void [000827] ------------ | /--* CNS_INT int 0 [000828] ------------ \--* EQ int [000826] ------------ \--* LCL_VAR int V54 tmp45 ------------ BB60 [05C..05D) -> BB62 (always), preds={} succs={BB62} ***** BB60, stmt 10 [000853] ------------ * STMT void (IL 0x05C... ???) [000850] ------------ | /--* CNS_INT int 1 [000852] -A---------- \--* ASG bool [000851] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB61 [05C..05D), preds={} succs={BB62} ***** BB61, stmt 11 [000845] ------------ * STMT void (IL 0x05C... ???) [000841] ------------ | /--* CNS_INT int 0 [000842] --C-G------- | /--* EQ int [000834] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000839] x----------- arg0 | | +--* OBJ(16) struct [000838] L----------- | | | \--* ADDR byref [000832] ------------ | | | \--* LCL_VAR struct V50 tmp41 [000836] x----------- arg1 | | \--* OBJ(16) struct [000835] L----------- | | \--* ADDR byref [000833] ------------ | | \--* LCL_VAR struct V51 tmp42 [000844] -AC-G------- \--* ASG bool [000843] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB62 [05C..05D), preds={} succs={BB63} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000093] is [000848] ------------ * CAST int <- bool <- int [000847] ------------ \--* LCL_VAR int V55 tmp46 Successfully inlined System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool (61 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000793] in BB57: [000793] ------------ * STMT void (IL 0x05C... ???) [000792] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000791] L----------- this in rcx \--* ADDR byref [000790] ------------ \--* LCL_VAR struct V50 tmp41 thisArg: is a constant is byref to a struct local [000791] L----------- * ADDR byref [000790] ------------ \--* LCL_VAR struct V50 tmp41 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB64 [0063] created. BB64 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB64 [0063] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB64 Importing BB64 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 56 (V56 tmp47) (a long lifetime temp) called for Inline stloc first use temp. [000886] ------------ * STMT void [000883] ------------ | /--* FIELD int _length [000881] L----------- | | \--* ADDR byref [000882] ------------ | | \--* LCL_VAR struct V50 tmp41 [000885] -A---------- \--* ASG int [000884] D------N---- \--* LCL_VAR int V56 tmp47 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000887] ------------ * LCL_VAR int V56 tmp47 Inlinee Return expression (after normalization) => [000887] ------------ * LCL_VAR int V56 tmp47 ----------- Statements (and blocks) added due to the inlining of call [000792] ----------- Arguments setup: Zero init inlinee locals: [000891] ------------ * STMT void (IL 0x05C... ???) [000888] ------------ | /--* CNS_INT int 0 [000890] -A---------- \--* ASG int [000889] D------N---- \--* LCL_VAR int V56 tmp47 Inlinee method body: [000886] ------------ * STMT void (IL 0x05C... ???) [000883] ------------ | /--* FIELD int _length [000881] L----------- | | \--* ADDR byref [000882] ------------ | | \--* LCL_VAR struct V50 tmp41 [000885] -A---------- \--* ASG int [000884] D------N---- \--* LCL_VAR int V56 tmp47 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000792] is [000887] ------------ * LCL_VAR int V56 tmp47 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000794] with [000887] [000794] --C--------- * RET_EXPR int (inl return from call [000887]) Inserting the inline return expression [000887] ------------ * LCL_VAR int V56 tmp47 Expanding INLINE_CANDIDATE in statement [000798] in BB57: [000798] ------------ * STMT void (IL 0x05C... ???) [000797] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000796] L----------- this in rcx \--* ADDR byref [000795] ------------ \--* LCL_VAR struct V51 tmp42 thisArg: is a constant is byref to a struct local [000796] L----------- * ADDR byref [000795] ------------ \--* LCL_VAR struct V51 tmp42 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB65 [0064] created. BB65 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB65 [0064] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB65 Importing BB65 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 57 (V57 tmp48) (a long lifetime temp) called for Inline stloc first use temp. [000899] ------------ * STMT void [000896] ------------ | /--* FIELD int _length [000894] L----------- | | \--* ADDR byref [000895] ------------ | | \--* LCL_VAR struct V51 tmp42 [000898] -A---------- \--* ASG int [000897] D------N---- \--* LCL_VAR int V57 tmp48 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000900] ------------ * LCL_VAR int V57 tmp48 Inlinee Return expression (after normalization) => [000900] ------------ * LCL_VAR int V57 tmp48 ----------- Statements (and blocks) added due to the inlining of call [000797] ----------- Arguments setup: Zero init inlinee locals: [000904] ------------ * STMT void (IL 0x05C... ???) [000901] ------------ | /--* CNS_INT int 0 [000903] -A---------- \--* ASG int [000902] D------N---- \--* LCL_VAR int V57 tmp48 Inlinee method body: [000899] ------------ * STMT void (IL 0x05C... ???) [000896] ------------ | /--* FIELD int _length [000894] L----------- | | \--* ADDR byref [000895] ------------ | | \--* LCL_VAR struct V51 tmp42 [000898] -A---------- \--* ASG int [000897] D------N---- \--* LCL_VAR int V57 tmp48 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000797] is [000900] ------------ * LCL_VAR int V57 tmp48 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000803] with [000900] [000803] --C--------- * RET_EXPR int (inl return from call [000900]) Inserting the inline return expression [000900] ------------ * LCL_VAR int V57 tmp48 Expanding INLINE_CANDIDATE in statement [000819] in BB59: [000819] ------------ * STMT void (IL 0x05C... ???) [000818] I-C-G------- \--* CALL int System.ReadOnlySpan`1.get_Length (exactContextHnd=0x0000000000421A31) [000817] L----------- this in rcx \--* ADDR byref [000816] ------------ \--* LCL_VAR struct V51 tmp42 thisArg: is a constant is byref to a struct local [000817] L----------- * ADDR byref [000816] ------------ \--* LCL_VAR struct V51 tmp42 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this set to 0x0000000000421A31: Invoking compiler for the inlinee method System.ReadOnlySpan`1:get_Length():int:this : IL to import: IL_0000 00 nop IL_0001 02 ldarg.0 IL_0002 7b 2b 01 00 0a ldfld 0xA00012B IL_0007 0a stloc.0 IL_0008 2b 00 br.s 0 (IL_000a) IL_000a 06 ldloc.0 IL_000b 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1:get_Length():int:this is 0x0000000000421A31. *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1:get_Length():int:this Jump targets: none New Basic Block BB66 [0065] created. BB66 [000..00C) Basic block list for 'System.ReadOnlySpan`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB66 [0065] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for System.ReadOnlySpan`1:get_Length():int:this impImportBlockPending for BB66 Importing BB66 (PC=000) of 'System.ReadOnlySpan`1:get_Length():int:this' [ 0] 0 (0x000) nop [ 0] 1 (0x001) ldarg.0 [ 1] 2 (0x002) ldfld 0A00012B [ 1] 7 (0x007) stloc.0 lvaGrabTemp returning 58 (V58 tmp49) (a long lifetime temp) called for Inline stloc first use temp. [000912] ------------ * STMT void [000909] ------------ | /--* FIELD int _length [000907] L----------- | | \--* ADDR byref [000908] ------------ | | \--* LCL_VAR struct V51 tmp42 [000911] -A---------- \--* ASG int [000910] D------N---- \--* LCL_VAR int V58 tmp49 [ 0] 8 (0x008) br.s [ 0] 10 (0x00a) ldloc.0 [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000913] ------------ * LCL_VAR int V58 tmp49 Inlinee Return expression (after normalization) => [000913] ------------ * LCL_VAR int V58 tmp49 ----------- Statements (and blocks) added due to the inlining of call [000818] ----------- Arguments setup: Zero init inlinee locals: [000917] ------------ * STMT void (IL 0x05C... ???) [000914] ------------ | /--* CNS_INT int 0 [000916] -A---------- \--* ASG int [000915] D------N---- \--* LCL_VAR int V58 tmp49 Inlinee method body: [000912] ------------ * STMT void (IL 0x05C... ???) [000909] ------------ | /--* FIELD int _length [000907] L----------- | | \--* ADDR byref [000908] ------------ | | \--* LCL_VAR struct V51 tmp42 [000911] -A---------- \--* ASG int [000910] D------N---- \--* LCL_VAR int V58 tmp49 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000818] is [000913] ------------ * LCL_VAR int V58 tmp49 Successfully inlined System.ReadOnlySpan`1:get_Length():int:this (12 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Boolean:TryParse(struct,byref):bool' calling 'System.ReadOnlySpan`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000820] with [000913] [000820] --C--------- * RET_EXPR int (inl return from call [000913]) Inserting the inline return expression [000913] ------------ * LCL_VAR int V58 tmp49 Replacing the return expression placeholder [000101] with [000848] [000101] --C--------- * RET_EXPR int (inl return from call [000848]) Inserting the inline return expression [000848] ------------ * CAST int <- bool <- int [000847] ------------ \--* LCL_VAR int V55 tmp46 *************** After fgInline() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i BB11 [0010] 1 1 [001..002)-> BB13 ( cond ) i BB12 [0011] 1 0.50 [001..002)-> BB14 (always) i BB13 [0012] 1 0.50 [001..002) i BB14 [0013] 2 1 [001..002) i BB15 [0014] 1 1 [???..???) internal BB19 [0018] 1 1 [00C..00D)-> BB21 ( cond ) i BB20 [0019] 1 0.50 [00C..00D)-> BB24 (always) i BB21 [0020] 1 0.50 [00C..00D)-> BB23 ( cond ) i BB22 [0021] 1 0.50 [00C..00D)-> BB24 (always) i BB23 [0022] 1 0.50 [00C..00D) i BB24 [0023] 3 1 [00C..00D) i BB25 [0024] 1 1 [???..???)-> BB03 ( cond ) internal BB02 [0001] 1 1 [017..01F)-> BB10 (always) i BB03 [0002] 1 1 [01F..037) i BB29 [0028] 1 1 [01F..020)-> BB31 ( cond ) i BB30 [0029] 1 0.50 [01F..020)-> BB32 (always) i BB31 [0030] 1 0.50 [01F..020) i BB32 [0031] 2 1 [01F..020) i BB33 [0032] 1 1 [???..???) internal BB37 [0036] 1 1 [02A..02B)-> BB39 ( cond ) i BB38 [0037] 1 0.50 [02A..02B)-> BB42 (always) i BB39 [0038] 1 0.50 [02A..02B)-> BB41 ( cond ) i BB40 [0039] 1 0.50 [02A..02B)-> BB42 (always) i BB41 [0040] 1 0.50 [02A..02B) i BB42 [0041] 3 1 [02A..02B) i BB43 [0042] 1 1 [???..???)-> BB05 ( cond ) internal BB04 [0003] 1 1 [037..03F)-> BB10 (always) i BB05 [0004] 1 1 [03F..054) i BB47 [0046] 1 1 [047..048)-> BB49 ( cond ) i BB48 [0047] 1 0.50 [047..048)-> BB52 (always) i BB49 [0048] 1 0.50 [047..048)-> BB51 ( cond ) i BB50 [0049] 1 0.50 [047..048)-> BB52 (always) i BB51 [0050] 1 0.50 [047..048) i BB52 [0051] 3 1 [047..048) i BB53 [0052] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [054..05C)-> BB10 (always) i BB07 [0006] 1 1 [05C..069) i BB57 [0056] 1 1 [05C..05D)-> BB59 ( cond ) i BB58 [0057] 1 0.50 [05C..05D)-> BB62 (always) i BB59 [0058] 1 0.50 [05C..05D)-> BB61 ( cond ) i BB60 [0059] 1 0.50 [05C..05D)-> BB62 (always) i BB61 [0060] 1 0.50 [05C..05D) i BB62 [0061] 3 1 [05C..05D) i BB63 [0062] 1 1 [???..???)-> BB09 ( cond ) internal BB08 [0007] 1 1 [069..071)-> BB10 (always) i BB09 [0008] 1 1 [071..078)-> BB10 (always) i BB10 [0009] 5 1 [078..07A) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017), preds={} succs={BB11} ***** BB01, stmt 1 [000224] ------------ * STMT void (IL 0x001... ???) [000221] ------------ | /--* CNS_INT int 0 [000223] -A---------- \--* ASG bool [000222] D------N---- \--* LCL_VAR bool V09 tmp0 ------------ BB11 [001..002) -> BB13 (cond), preds={} succs={BB12,BB13} ***** BB11, stmt 2 [000171] ------------ * STMT void (IL 0x001... ???) [000167] ------------ | /--* CNS_INT ref null [000168] ------------ | /--* EQ int [000166] ------------ | | \--* CNS_STR ref [000170] -A---------- \--* ASG bool [000169] D------N---- \--* LCL_VAR bool V09 tmp0 ***** BB11, stmt 3 [000176] ------------ * STMT void (IL 0x001... ???) [000175] ------------ \--* JTRUE void [000173] ------------ | /--* CNS_INT int 0 [000174] ------------ \--* EQ int [000172] ------------ \--* LCL_VAR int V09 tmp0 ------------ BB12 [001..002) -> BB14 (always), preds={} succs={BB14} ***** BB12, stmt 4 [000215] ------------ * STMT void (IL 0x001... ???) [000213] ------------ | /--* CNS_INT int 0 [000214] IA------R--- \--* ASG struct (init) [000211] D------N---- \--* LCL_VAR struct V13 tmp4 ***** BB12, stmt 5 [000220] ------------ * STMT void (IL 0x001... ???) [000216] ------------ | /--* LCL_VAR struct V13 tmp4 [000219] -A------R--- \--* ASG struct (copy) [000217] D----------- \--* LCL_VAR struct V12 tmp3 ------------ BB13 [001..002), preds={} succs={BB14} ***** BB13, stmt 6 [000232] ------------ * STMT void (IL 0x001... ???) [000231] ---X-------- \--* IND int [000230] ------------ \--* CNS_STR ref ***** BB13, stmt 7 [000187] ------------ * STMT void (IL 0x001... ???) [000229] ---XG------- | /--* ADDR byref [000228] ---XG------- | | \--* FIELD ushort _firstChar [000227] ------------ | | \--* CNS_STR ref [000186] -AC--------- \--* ASG byref [000185] D------N---- \--* LCL_VAR byref V10 tmp1 ***** BB13, stmt 8 [000243] ------------ * STMT void (IL 0x001... ???) [000242] ---X-------- \--* IND int [000241] ------------ \--* CNS_STR ref ***** BB13, stmt 9 [000247] ------------ * STMT void (IL 0x001... ???) [000244] ------------ | /--* CNS_INT int 0 [000246] -A---------- \--* ASG int [000245] D------N---- \--* LCL_VAR int V14 tmp5 ***** BB13, stmt 10 [000239] ------------ * STMT void (IL 0x001... ???) [000236] ---XG------- | /--* FIELD int _stringLength [000235] ------------ | | \--* CNS_STR ref [000238] -A-XG------- \--* ASG int [000237] D------N---- \--* LCL_VAR int V14 tmp5 ***** BB13, stmt 11 [000193] ------------ * STMT void (IL 0x001... ???) [000191] ------------ | /--* CNS_INT int 0 [000192] IA------R--- \--* ASG struct (init) [000190] D------N---- \--* LCL_VAR struct V11 tmp2 ***** BB13, stmt 12 [000256] ------------ * STMT void (IL 0x001... ???) [000254] --C-G------- \--* CALL void System.Diagnostics.Debug.Assert [000252] ------------ | /--* CNS_INT int 0 [000253] ------------ arg0 \--* EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 ***** BB13, stmt 13 [000262] ------------ * STMT void (IL 0x001... ???) [000260] ------------ | /--* CNS_INT int 0 [000261] IA------R--- \--* ASG struct (init) [000259] D------N---- \--* LCL_VAR struct V15 tmp6 ***** BB13, stmt 14 [000268] ------------ * STMT void (IL 0x001... ???) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---------- \--* ASG byref [000265] -------N---- \--* FIELD byref _value [000264] L----------- \--* ADDR byref [000263] ------------ \--* LCL_VAR struct V15 tmp6 ***** BB13, stmt 15 [000273] ------------ * STMT void (IL 0x001... ???) [000267] ------------ | /--* LCL_VAR struct V15 tmp6 [000272] -A------R--- \--* ASG struct (copy) [000271] ------------ \--* OBJ(8) struct [000270] ------------ \--* ADDR byref [000269] ------------ \--* FIELD struct _pointer [000257] L----------- \--* ADDR byref [000258] ------------ \--* LCL_VAR struct V11 tmp2 ***** BB13, stmt 16 [000279] ------------ * STMT void (IL 0x001... ???) [000276] ------------ | /--* LCL_VAR int V14 tmp5 [000278] -A---------- \--* ASG int [000277] -------N---- \--* FIELD int _length [000274] L----------- \--* ADDR byref [000275] ------------ \--* LCL_VAR struct V11 tmp2 ***** BB13, stmt 17 [000204] ------------ * STMT void (IL 0x001... ???) [000200] ------------ | /--* LCL_VAR struct V11 tmp2 [000203] -A------R--- \--* ASG struct (copy) [000201] D----------- \--* LCL_VAR struct V12 tmp3 ------------ BB14 [001..002), preds={} succs={BB15} ------------ BB15 [???..???), preds={} succs={BB19} ***** BB15, stmt 18 [000009] ------------ * STMT void (IL ???... ???) [000206] ------------ | /--* LCL_VAR struct V12 tmp3 [000209] -A------R--- \--* ASG struct (copy) [000208] D----------- \--* LCL_VAR struct V02 loc0 ***** BB15, stmt 19 [000355] ------------ * STMT void (IL 0x00C... ???) [000017] x----------- | /--* OBJ(16) struct [000016] L----------- | | \--* ADDR byref [000010] ------------ | | \--* LCL_VAR struct V02 loc0 [000354] -A------R--- \--* ASG struct (copy) [000352] D----------- \--* LCL_VAR struct V16 tmp7 ***** BB15, stmt 20 [000359] ------------ * STMT void (IL 0x00C... ???) [000014] x----------- | /--* OBJ(16) struct [000013] L----------- | | \--* ADDR byref [000011] ------------ | | \--* LCL_VAR struct V00 arg0 [000358] -A------R--- \--* ASG struct (copy) [000356] D----------- \--* LCL_VAR struct V17 tmp8 ***** BB15, stmt 21 [000363] ------------ * STMT void (IL 0x00C... ???) [000360] ------------ | /--* CNS_INT int 0 [000362] -A---------- \--* ASG bool [000361] D------N---- \--* LCL_VAR bool V19 tmp10 ***** BB15, stmt 22 [000367] ------------ * STMT void (IL 0x00C... ???) [000364] ------------ | /--* CNS_INT int 0 [000366] -A---------- \--* ASG bool [000365] D------N---- \--* LCL_VAR bool V21 tmp12 ***** BB15, stmt 23 [000371] ------------ * STMT void (IL 0x00C... ???) [000368] ------------ | /--* CNS_INT int 0 [000370] -A---------- \--* ASG bool [000369] D------N---- \--* LCL_VAR bool V20 tmp11 ------------ BB19 [00C..00D) -> BB21 (cond), preds={} succs={BB20,BB21} ***** BB19, stmt 24 [000384] ------------ * STMT void (IL 0x00C... ???) [000381] ------------ | /--* CNS_INT int 0 [000383] -A---------- \--* ASG int [000382] D------N---- \--* LCL_VAR int V22 tmp13 ***** BB19, stmt 25 [000379] ------------ * STMT void (IL 0x00C... ???) [000376] ------------ | /--* FIELD int _length [000374] L----------- | | \--* ADDR byref [000375] ------------ | | \--* LCL_VAR struct V16 tmp7 [000378] -A---------- \--* ASG int [000377] D------N---- \--* LCL_VAR int V22 tmp13 ***** BB19, stmt 26 [000294] ------------ * STMT void (IL 0x00C... ???) [000380] ------------ | /--* LCL_VAR int V22 tmp13 [000293] -AC--------- \--* ASG int [000292] D------N---- \--* LCL_VAR int V18 tmp9 ***** BB19, stmt 27 [000397] ------------ * STMT void (IL 0x00C... ???) [000394] ------------ | /--* CNS_INT int 0 [000396] -A---------- \--* ASG int [000395] D------N---- \--* LCL_VAR int V23 tmp14 ***** BB19, stmt 28 [000392] ------------ * STMT void (IL 0x00C... ???) [000389] ------------ | /--* FIELD int _length [000387] L----------- | | \--* ADDR byref [000388] ------------ | | \--* LCL_VAR struct V17 tmp8 [000391] -A---------- \--* ASG int [000390] D------N---- \--* LCL_VAR int V23 tmp14 ***** BB19, stmt 29 [000302] ------------ * STMT void (IL 0x00C... ???) [000298] ------------ | /--* CNS_INT int 0 [000299] --C--------- | /--* EQ int [000393] ------------ | | | /--* LCL_VAR int V23 tmp14 [000297] --C--------- | | \--* EQ int [000295] ------------ | | \--* LCL_VAR int V18 tmp9 [000301] -AC--------- \--* ASG bool [000300] D------N---- \--* LCL_VAR bool V19 tmp10 ***** BB19, stmt 30 [000307] ------------ * STMT void (IL 0x00C... ???) [000306] ------------ \--* JTRUE void [000304] ------------ | /--* CNS_INT int 0 [000305] ------------ \--* EQ int [000303] ------------ \--* LCL_VAR int V19 tmp10 ------------ BB20 [00C..00D) -> BB24 (always), preds={} succs={BB24} ***** BB20, stmt 31 [000351] ------------ * STMT void (IL 0x00C... ???) [000348] ------------ | /--* CNS_INT int 0 [000350] -A---------- \--* ASG bool [000349] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB21 [00C..00D) -> BB23 (cond), preds={} succs={BB22,BB23} ***** BB21, stmt 32 [000410] ------------ * STMT void (IL 0x00C... ???) [000407] ------------ | /--* CNS_INT int 0 [000409] -A---------- \--* ASG int [000408] D------N---- \--* LCL_VAR int V24 tmp15 ***** BB21, stmt 33 [000405] ------------ * STMT void (IL 0x00C... ???) [000402] ------------ | /--* FIELD int _length [000400] L----------- | | \--* ADDR byref [000401] ------------ | | \--* LCL_VAR struct V17 tmp8 [000404] -A---------- \--* ASG int [000403] D------N---- \--* LCL_VAR int V24 tmp15 ***** BB21, stmt 34 [000318] ------------ * STMT void (IL 0x00C... ???) [000314] ------------ | /--* CNS_INT int 0 [000315] --C--------- | /--* EQ int [000406] ------------ | | \--* LCL_VAR int V24 tmp15 [000317] -AC--------- \--* ASG bool [000316] D------N---- \--* LCL_VAR bool V20 tmp11 ***** BB21, stmt 35 [000323] ------------ * STMT void (IL 0x00C... ???) [000322] ------------ \--* JTRUE void [000320] ------------ | /--* CNS_INT int 0 [000321] ------------ \--* EQ int [000319] ------------ \--* LCL_VAR int V20 tmp11 ------------ BB22 [00C..00D) -> BB24 (always), preds={} succs={BB24} ***** BB22, stmt 36 [000346] ------------ * STMT void (IL 0x00C... ???) [000343] ------------ | /--* CNS_INT int 1 [000345] -A---------- \--* ASG bool [000344] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB23 [00C..00D), preds={} succs={BB24} ***** BB23, stmt 37 [000338] ------------ * STMT void (IL 0x00C... ???) [000334] ------------ | /--* CNS_INT int 0 [000335] --C-G------- | /--* EQ int [000327] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000332] x----------- arg0 | | +--* OBJ(16) struct [000331] L----------- | | | \--* ADDR byref [000325] ------------ | | | \--* LCL_VAR struct V16 tmp7 [000329] x----------- arg1 | | \--* OBJ(16) struct [000328] L----------- | | \--* ADDR byref [000326] ------------ | | \--* LCL_VAR struct V17 tmp8 [000337] -AC-G------- \--* ASG bool [000336] D------N---- \--* LCL_VAR bool V21 tmp12 ------------ BB24 [00C..00D), preds={} succs={BB25} ------------ BB25 [???..???) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB25, stmt 38 [000024] ------------ * STMT void (IL ???... ???) [000021] --C--------- | /--* CAST int <- bool <- int [000341] ------------ | | \--* CAST int <- bool <- int [000340] ------------ | | \--* LCL_VAR int V21 tmp12 [000023] -AC--------- \--* ASG int [000022] D------N---- \--* LCL_VAR int V04 loc2 ***** BB25, stmt 39 [000029] ------------ * STMT void (IL 0x014...0x015) [000028] ------------ \--* JTRUE void [000026] ------------ | /--* CNS_INT int 0 [000027] ------------ \--* EQ int [000025] ------------ \--* LCL_VAR int V04 loc2 ------------ BB02 [017..01F) -> BB10 (always), preds={} succs={BB10} ***** BB02, stmt 40 [000160] ------------ * STMT void (IL 0x018...0x01A) [000157] ------------ | /--* CNS_INT int 1 [000159] -A-XG------- \--* ASG byte [000158] *------N---- \--* IND byte [000156] ------------ \--* LCL_VAR byref V01 arg1 ***** BB02, stmt 41 [000164] ------------ * STMT void (IL 0x01B...0x01C) [000161] ------------ | /--* CNS_INT int 1 [000163] -A---------- \--* ASG int [000162] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB03 [01F..037), preds={} succs={BB29} ***** BB03, stmt 42 [000471] ------------ * STMT void (IL 0x01F... ???) [000468] ------------ | /--* CNS_INT int 0 [000470] -A---------- \--* ASG bool [000469] D------N---- \--* LCL_VAR bool V25 tmp16 ------------ BB29 [01F..020) -> BB31 (cond), preds={} succs={BB30,BB31} ***** BB29, stmt 43 [000418] ------------ * STMT void (IL 0x01F... ???) [000414] ------------ | /--* CNS_INT ref null [000415] ------------ | /--* EQ int [000413] ------------ | | \--* CNS_STR ref [000417] -A---------- \--* ASG bool [000416] D------N---- \--* LCL_VAR bool V25 tmp16 ***** BB29, stmt 44 [000423] ------------ * STMT void (IL 0x01F... ???) [000422] ------------ \--* JTRUE void [000420] ------------ | /--* CNS_INT int 0 [000421] ------------ \--* EQ int [000419] ------------ \--* LCL_VAR int V25 tmp16 ------------ BB30 [01F..020) -> BB32 (always), preds={} succs={BB32} ***** BB30, stmt 45 [000462] ------------ * STMT void (IL 0x01F... ???) [000460] ------------ | /--* CNS_INT int 0 [000461] IA------R--- \--* ASG struct (init) [000458] D------N---- \--* LCL_VAR struct V29 tmp20 ***** BB30, stmt 46 [000467] ------------ * STMT void (IL 0x01F... ???) [000463] ------------ | /--* LCL_VAR struct V29 tmp20 [000466] -A------R--- \--* ASG struct (copy) [000464] D----------- \--* LCL_VAR struct V28 tmp19 ------------ BB31 [01F..020), preds={} succs={BB32} ***** BB31, stmt 47 [000479] ------------ * STMT void (IL 0x01F... ???) [000478] ---X-------- \--* IND int [000477] ------------ \--* CNS_STR ref ***** BB31, stmt 48 [000434] ------------ * STMT void (IL 0x01F... ???) [000476] ---XG------- | /--* ADDR byref [000475] ---XG------- | | \--* FIELD ushort _firstChar [000474] ------------ | | \--* CNS_STR ref [000433] -AC--------- \--* ASG byref [000432] D------N---- \--* LCL_VAR byref V26 tmp17 ***** BB31, stmt 49 [000490] ------------ * STMT void (IL 0x01F... ???) [000489] ---X-------- \--* IND int [000488] ------------ \--* CNS_STR ref ***** BB31, stmt 50 [000494] ------------ * STMT void (IL 0x01F... ???) [000491] ------------ | /--* CNS_INT int 0 [000493] -A---------- \--* ASG int [000492] D------N---- \--* LCL_VAR int V30 tmp21 ***** BB31, stmt 51 [000486] ------------ * STMT void (IL 0x01F... ???) [000483] ---XG------- | /--* FIELD int _stringLength [000482] ------------ | | \--* CNS_STR ref [000485] -A-XG------- \--* ASG int [000484] D------N---- \--* LCL_VAR int V30 tmp21 ***** BB31, stmt 52 [000440] ------------ * STMT void (IL 0x01F... ???) [000438] ------------ | /--* CNS_INT int 0 [000439] IA------R--- \--* ASG struct (init) [000437] D------N---- \--* LCL_VAR struct V27 tmp18 ***** BB31, stmt 53 [000503] ------------ * STMT void (IL 0x01F... ???) [000501] --C-G------- \--* CALL void System.Diagnostics.Debug.Assert [000499] ------------ | /--* CNS_INT int 0 [000500] ------------ arg0 \--* EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 ***** BB31, stmt 54 [000509] ------------ * STMT void (IL 0x01F... ???) [000507] ------------ | /--* CNS_INT int 0 [000508] IA------R--- \--* ASG struct (init) [000506] D------N---- \--* LCL_VAR struct V31 tmp22 ***** BB31, stmt 55 [000515] ------------ * STMT void (IL 0x01F... ???) [000435] ------------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---------- \--* ASG byref [000512] -------N---- \--* FIELD byref _value [000511] L----------- \--* ADDR byref [000510] ------------ \--* LCL_VAR struct V31 tmp22 ***** BB31, stmt 56 [000520] ------------ * STMT void (IL 0x01F... ???) [000514] ------------ | /--* LCL_VAR struct V31 tmp22 [000519] -A------R--- \--* ASG struct (copy) [000518] ------------ \--* OBJ(8) struct [000517] ------------ \--* ADDR byref [000516] ------------ \--* FIELD struct _pointer [000504] L----------- \--* ADDR byref [000505] ------------ \--* LCL_VAR struct V27 tmp18 ***** BB31, stmt 57 [000526] ------------ * STMT void (IL 0x01F... ???) [000523] ------------ | /--* LCL_VAR int V30 tmp21 [000525] -A---------- \--* ASG int [000524] -------N---- \--* FIELD int _length [000521] L----------- \--* ADDR byref [000522] ------------ \--* LCL_VAR struct V27 tmp18 ***** BB31, stmt 58 [000451] ------------ * STMT void (IL 0x01F... ???) [000447] ------------ | /--* LCL_VAR struct V27 tmp18 [000450] -A------R--- \--* ASG struct (copy) [000448] D----------- \--* LCL_VAR struct V28 tmp19 ------------ BB32 [01F..020), preds={} succs={BB33} ------------ BB33 [???..???), preds={} succs={BB37} ***** BB33, stmt 59 [000039] ------------ * STMT void (IL ???... ???) [000453] ------------ | /--* LCL_VAR struct V28 tmp19 [000456] -A------R--- \--* ASG struct (copy) [000455] D----------- \--* LCL_VAR struct V03 loc1 ***** BB33, stmt 60 [000602] ------------ * STMT void (IL 0x02A... ???) [000047] x----------- | /--* OBJ(16) struct [000046] L----------- | | \--* ADDR byref [000040] ------------ | | \--* LCL_VAR struct V03 loc1 [000601] -A------R--- \--* ASG struct (copy) [000599] D----------- \--* LCL_VAR struct V32 tmp23 ***** BB33, stmt 61 [000606] ------------ * STMT void (IL 0x02A... ???) [000044] x----------- | /--* OBJ(16) struct [000043] L----------- | | \--* ADDR byref [000041] ------------ | | \--* LCL_VAR struct V00 arg0 [000605] -A------R--- \--* ASG struct (copy) [000603] D----------- \--* LCL_VAR struct V33 tmp24 ***** BB33, stmt 62 [000610] ------------ * STMT void (IL 0x02A... ???) [000607] ------------ | /--* CNS_INT int 0 [000609] -A---------- \--* ASG bool [000608] D------N---- \--* LCL_VAR bool V35 tmp26 ***** BB33, stmt 63 [000614] ------------ * STMT void (IL 0x02A... ???) [000611] ------------ | /--* CNS_INT int 0 [000613] -A---------- \--* ASG bool [000612] D------N---- \--* LCL_VAR bool V37 tmp28 ***** BB33, stmt 64 [000618] ------------ * STMT void (IL 0x02A... ???) [000615] ------------ | /--* CNS_INT int 0 [000617] -A---------- \--* ASG bool [000616] D------N---- \--* LCL_VAR bool V36 tmp27 ------------ BB37 [02A..02B) -> BB39 (cond), preds={} succs={BB38,BB39} ***** BB37, stmt 65 [000631] ------------ * STMT void (IL 0x02A... ???) [000628] ------------ | /--* CNS_INT int 0 [000630] -A---------- \--* ASG int [000629] D------N---- \--* LCL_VAR int V38 tmp29 ***** BB37, stmt 66 [000626] ------------ * STMT void (IL 0x02A... ???) [000623] ------------ | /--* FIELD int _length [000621] L----------- | | \--* ADDR byref [000622] ------------ | | \--* LCL_VAR struct V32 tmp23 [000625] -A---------- \--* ASG int [000624] D------N---- \--* LCL_VAR int V38 tmp29 ***** BB37, stmt 67 [000541] ------------ * STMT void (IL 0x02A... ???) [000627] ------------ | /--* LCL_VAR int V38 tmp29 [000540] -AC--------- \--* ASG int [000539] D------N---- \--* LCL_VAR int V34 tmp25 ***** BB37, stmt 68 [000644] ------------ * STMT void (IL 0x02A... ???) [000641] ------------ | /--* CNS_INT int 0 [000643] -A---------- \--* ASG int [000642] D------N---- \--* LCL_VAR int V39 tmp30 ***** BB37, stmt 69 [000639] ------------ * STMT void (IL 0x02A... ???) [000636] ------------ | /--* FIELD int _length [000634] L----------- | | \--* ADDR byref [000635] ------------ | | \--* LCL_VAR struct V33 tmp24 [000638] -A---------- \--* ASG int [000637] D------N---- \--* LCL_VAR int V39 tmp30 ***** BB37, stmt 70 [000549] ------------ * STMT void (IL 0x02A... ???) [000545] ------------ | /--* CNS_INT int 0 [000546] --C--------- | /--* EQ int [000640] ------------ | | | /--* LCL_VAR int V39 tmp30 [000544] --C--------- | | \--* EQ int [000542] ------------ | | \--* LCL_VAR int V34 tmp25 [000548] -AC--------- \--* ASG bool [000547] D------N---- \--* LCL_VAR bool V35 tmp26 ***** BB37, stmt 71 [000554] ------------ * STMT void (IL 0x02A... ???) [000553] ------------ \--* JTRUE void [000551] ------------ | /--* CNS_INT int 0 [000552] ------------ \--* EQ int [000550] ------------ \--* LCL_VAR int V35 tmp26 ------------ BB38 [02A..02B) -> BB42 (always), preds={} succs={BB42} ***** BB38, stmt 72 [000598] ------------ * STMT void (IL 0x02A... ???) [000595] ------------ | /--* CNS_INT int 0 [000597] -A---------- \--* ASG bool [000596] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB39 [02A..02B) -> BB41 (cond), preds={} succs={BB40,BB41} ***** BB39, stmt 73 [000657] ------------ * STMT void (IL 0x02A... ???) [000654] ------------ | /--* CNS_INT int 0 [000656] -A---------- \--* ASG int [000655] D------N---- \--* LCL_VAR int V40 tmp31 ***** BB39, stmt 74 [000652] ------------ * STMT void (IL 0x02A... ???) [000649] ------------ | /--* FIELD int _length [000647] L----------- | | \--* ADDR byref [000648] ------------ | | \--* LCL_VAR struct V33 tmp24 [000651] -A---------- \--* ASG int [000650] D------N---- \--* LCL_VAR int V40 tmp31 ***** BB39, stmt 75 [000565] ------------ * STMT void (IL 0x02A... ???) [000561] ------------ | /--* CNS_INT int 0 [000562] --C--------- | /--* EQ int [000653] ------------ | | \--* LCL_VAR int V40 tmp31 [000564] -AC--------- \--* ASG bool [000563] D------N---- \--* LCL_VAR bool V36 tmp27 ***** BB39, stmt 76 [000570] ------------ * STMT void (IL 0x02A... ???) [000569] ------------ \--* JTRUE void [000567] ------------ | /--* CNS_INT int 0 [000568] ------------ \--* EQ int [000566] ------------ \--* LCL_VAR int V36 tmp27 ------------ BB40 [02A..02B) -> BB42 (always), preds={} succs={BB42} ***** BB40, stmt 77 [000593] ------------ * STMT void (IL 0x02A... ???) [000590] ------------ | /--* CNS_INT int 1 [000592] -A---------- \--* ASG bool [000591] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB41 [02A..02B), preds={} succs={BB42} ***** BB41, stmt 78 [000585] ------------ * STMT void (IL 0x02A... ???) [000581] ------------ | /--* CNS_INT int 0 [000582] --C-G------- | /--* EQ int [000574] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000579] x----------- arg0 | | +--* OBJ(16) struct [000578] L----------- | | | \--* ADDR byref [000572] ------------ | | | \--* LCL_VAR struct V32 tmp23 [000576] x----------- arg1 | | \--* OBJ(16) struct [000575] L----------- | | \--* ADDR byref [000573] ------------ | | \--* LCL_VAR struct V33 tmp24 [000584] -AC-G------- \--* ASG bool [000583] D------N---- \--* LCL_VAR bool V37 tmp28 ------------ BB42 [02A..02B), preds={} succs={BB43} ------------ BB43 [???..???) -> BB05 (cond), preds={} succs={BB04,BB05} ***** BB43, stmt 79 [000054] ------------ * STMT void (IL ???... ???) [000051] --C--------- | /--* CAST int <- bool <- int [000588] ------------ | | \--* CAST int <- bool <- int [000587] ------------ | | \--* LCL_VAR int V37 tmp28 [000053] -AC--------- \--* ASG int [000052] D------N---- \--* LCL_VAR int V06 loc4 ***** BB43, stmt 80 [000059] ------------ * STMT void (IL 0x033...0x035) [000058] ------------ \--* JTRUE void [000056] ------------ | /--* CNS_INT int 0 [000057] ------------ \--* EQ int [000055] ------------ \--* LCL_VAR int V06 loc4 ------------ BB04 [037..03F) -> BB10 (always), preds={} succs={BB10} ***** BB04, stmt 81 [000150] ------------ * STMT void (IL 0x038...0x03A) [000147] ------------ | /--* CNS_INT int 0 [000149] -A-XG------- \--* ASG byte [000148] *------N---- \--* IND byte [000146] ------------ \--* LCL_VAR byref V01 arg1 ***** BB04, stmt 82 [000154] ------------ * STMT void (IL 0x03B...0x03C) [000151] ------------ | /--* CNS_INT int 1 [000153] -A---------- \--* ASG int [000152] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB05 [03F..054), preds={} succs={BB47} ***** BB05, stmt 83 [000069] ------------ * STMT void (IL 0x03F...0x045) [000062] S-C-G------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull [000067] L----------- arg0 +--* ADDR byref [000066] ------------ | \--* LCL_VAR struct V00 arg0 [000064] x----------- arg1 \--* OBJ(16) struct [000063] L----------- \--* ADDR byref [000061] ------------ \--* LCL_VAR struct V00 arg0 ***** BB05, stmt 84 [000732] ------------ * STMT void (IL 0x047... ???) [000077] x----------- | /--* OBJ(16) struct [000076] L----------- | | \--* ADDR byref [000070] ------------ | | \--* LCL_VAR struct V02 loc0 [000731] -A------R--- \--* ASG struct (copy) [000729] D----------- \--* LCL_VAR struct V41 tmp32 ***** BB05, stmt 85 [000736] ------------ * STMT void (IL 0x047... ???) [000074] x----------- | /--* OBJ(16) struct [000073] L----------- | | \--* ADDR byref [000071] ------------ | | \--* LCL_VAR struct V00 arg0 [000735] -A------R--- \--* ASG struct (copy) [000733] D----------- \--* LCL_VAR struct V42 tmp33 ***** BB05, stmt 86 [000740] ------------ * STMT void (IL 0x047... ???) [000737] ------------ | /--* CNS_INT int 0 [000739] -A---------- \--* ASG bool [000738] D------N---- \--* LCL_VAR bool V44 tmp35 ***** BB05, stmt 87 [000744] ------------ * STMT void (IL 0x047... ???) [000741] ------------ | /--* CNS_INT int 0 [000743] -A---------- \--* ASG bool [000742] D------N---- \--* LCL_VAR bool V46 tmp37 ***** BB05, stmt 88 [000748] ------------ * STMT void (IL 0x047... ???) [000745] ------------ | /--* CNS_INT int 0 [000747] -A---------- \--* ASG bool [000746] D------N---- \--* LCL_VAR bool V45 tmp36 ------------ BB47 [047..048) -> BB49 (cond), preds={} succs={BB48,BB49} ***** BB47, stmt 89 [000761] ------------ * STMT void (IL 0x047... ???) [000758] ------------ | /--* CNS_INT int 0 [000760] -A---------- \--* ASG int [000759] D------N---- \--* LCL_VAR int V47 tmp38 ***** BB47, stmt 90 [000756] ------------ * STMT void (IL 0x047... ???) [000753] ------------ | /--* FIELD int _length [000751] L----------- | | \--* ADDR byref [000752] ------------ | | \--* LCL_VAR struct V41 tmp32 [000755] -A---------- \--* ASG int [000754] D------N---- \--* LCL_VAR int V47 tmp38 ***** BB47, stmt 91 [000671] ------------ * STMT void (IL 0x047... ???) [000757] ------------ | /--* LCL_VAR int V47 tmp38 [000670] -AC--------- \--* ASG int [000669] D------N---- \--* LCL_VAR int V43 tmp34 ***** BB47, stmt 92 [000774] ------------ * STMT void (IL 0x047... ???) [000771] ------------ | /--* CNS_INT int 0 [000773] -A---------- \--* ASG int [000772] D------N---- \--* LCL_VAR int V48 tmp39 ***** BB47, stmt 93 [000769] ------------ * STMT void (IL 0x047... ???) [000766] ------------ | /--* FIELD int _length [000764] L----------- | | \--* ADDR byref [000765] ------------ | | \--* LCL_VAR struct V42 tmp33 [000768] -A---------- \--* ASG int [000767] D------N---- \--* LCL_VAR int V48 tmp39 ***** BB47, stmt 94 [000679] ------------ * STMT void (IL 0x047... ???) [000675] ------------ | /--* CNS_INT int 0 [000676] --C--------- | /--* EQ int [000770] ------------ | | | /--* LCL_VAR int V48 tmp39 [000674] --C--------- | | \--* EQ int [000672] ------------ | | \--* LCL_VAR int V43 tmp34 [000678] -AC--------- \--* ASG bool [000677] D------N---- \--* LCL_VAR bool V44 tmp35 ***** BB47, stmt 95 [000684] ------------ * STMT void (IL 0x047... ???) [000683] ------------ \--* JTRUE void [000681] ------------ | /--* CNS_INT int 0 [000682] ------------ \--* EQ int [000680] ------------ \--* LCL_VAR int V44 tmp35 ------------ BB48 [047..048) -> BB52 (always), preds={} succs={BB52} ***** BB48, stmt 96 [000728] ------------ * STMT void (IL 0x047... ???) [000725] ------------ | /--* CNS_INT int 0 [000727] -A---------- \--* ASG bool [000726] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB49 [047..048) -> BB51 (cond), preds={} succs={BB50,BB51} ***** BB49, stmt 97 [000787] ------------ * STMT void (IL 0x047... ???) [000784] ------------ | /--* CNS_INT int 0 [000786] -A---------- \--* ASG int [000785] D------N---- \--* LCL_VAR int V49 tmp40 ***** BB49, stmt 98 [000782] ------------ * STMT void (IL 0x047... ???) [000779] ------------ | /--* FIELD int _length [000777] L----------- | | \--* ADDR byref [000778] ------------ | | \--* LCL_VAR struct V42 tmp33 [000781] -A---------- \--* ASG int [000780] D------N---- \--* LCL_VAR int V49 tmp40 ***** BB49, stmt 99 [000695] ------------ * STMT void (IL 0x047... ???) [000691] ------------ | /--* CNS_INT int 0 [000692] --C--------- | /--* EQ int [000783] ------------ | | \--* LCL_VAR int V49 tmp40 [000694] -AC--------- \--* ASG bool [000693] D------N---- \--* LCL_VAR bool V45 tmp36 ***** BB49, stmt 100 [000700] ------------ * STMT void (IL 0x047... ???) [000699] ------------ \--* JTRUE void [000697] ------------ | /--* CNS_INT int 0 [000698] ------------ \--* EQ int [000696] ------------ \--* LCL_VAR int V45 tmp36 ------------ BB50 [047..048) -> BB52 (always), preds={} succs={BB52} ***** BB50, stmt 101 [000723] ------------ * STMT void (IL 0x047... ???) [000720] ------------ | /--* CNS_INT int 1 [000722] -A---------- \--* ASG bool [000721] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB51 [047..048), preds={} succs={BB52} ***** BB51, stmt 102 [000715] ------------ * STMT void (IL 0x047... ???) [000711] ------------ | /--* CNS_INT int 0 [000712] --C-G------- | /--* EQ int [000704] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000709] x----------- arg0 | | +--* OBJ(16) struct [000708] L----------- | | | \--* ADDR byref [000702] ------------ | | | \--* LCL_VAR struct V41 tmp32 [000706] x----------- arg1 | | \--* OBJ(16) struct [000705] L----------- | | \--* ADDR byref [000703] ------------ | | \--* LCL_VAR struct V42 tmp33 [000714] -AC-G------- \--* ASG bool [000713] D------N---- \--* LCL_VAR bool V46 tmp37 ------------ BB52 [047..048), preds={} succs={BB53} ------------ BB53 [???..???) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB53, stmt 103 [000084] ------------ * STMT void (IL ???... ???) [000081] --C--------- | /--* CAST int <- bool <- int [000718] ------------ | | \--* CAST int <- bool <- int [000717] ------------ | | \--* LCL_VAR int V46 tmp37 [000083] -AC--------- \--* ASG int [000082] D------N---- \--* LCL_VAR int V07 loc5 ***** BB53, stmt 104 [000089] ------------ * STMT void (IL 0x050...0x052) [000088] ------------ \--* JTRUE void [000086] ------------ | /--* CNS_INT int 0 [000087] ------------ \--* EQ int [000085] ------------ \--* LCL_VAR int V07 loc5 ------------ BB06 [054..05C) -> BB10 (always), preds={} succs={BB10} ***** BB06, stmt 105 [000140] ------------ * STMT void (IL 0x055...0x057) [000137] ------------ | /--* CNS_INT int 1 [000139] -A-XG------- \--* ASG byte [000138] *------N---- \--* IND byte [000136] ------------ \--* LCL_VAR byref V01 arg1 ***** BB06, stmt 106 [000144] ------------ * STMT void (IL 0x058...0x059) [000141] ------------ | /--* CNS_INT int 1 [000143] -A---------- \--* ASG int [000142] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB07 [05C..069), preds={} succs={BB57} ***** BB07, stmt 107 [000862] ------------ * STMT void (IL 0x05C... ???) [000098] x----------- | /--* OBJ(16) struct [000097] L----------- | | \--* ADDR byref [000091] ------------ | | \--* LCL_VAR struct V03 loc1 [000861] -A------R--- \--* ASG struct (copy) [000859] D----------- \--* LCL_VAR struct V50 tmp41 ***** BB07, stmt 108 [000866] ------------ * STMT void (IL 0x05C... ???) [000095] x----------- | /--* OBJ(16) struct [000094] L----------- | | \--* ADDR byref [000092] ------------ | | \--* LCL_VAR struct V00 arg0 [000865] -A------R--- \--* ASG struct (copy) [000863] D----------- \--* LCL_VAR struct V51 tmp42 ***** BB07, stmt 109 [000870] ------------ * STMT void (IL 0x05C... ???) [000867] ------------ | /--* CNS_INT int 0 [000869] -A---------- \--* ASG bool [000868] D------N---- \--* LCL_VAR bool V53 tmp44 ***** BB07, stmt 110 [000874] ------------ * STMT void (IL 0x05C... ???) [000871] ------------ | /--* CNS_INT int 0 [000873] -A---------- \--* ASG bool [000872] D------N---- \--* LCL_VAR bool V55 tmp46 ***** BB07, stmt 111 [000878] ------------ * STMT void (IL 0x05C... ???) [000875] ------------ | /--* CNS_INT int 0 [000877] -A---------- \--* ASG bool [000876] D------N---- \--* LCL_VAR bool V54 tmp45 ------------ BB57 [05C..05D) -> BB59 (cond), preds={} succs={BB58,BB59} ***** BB57, stmt 112 [000891] ------------ * STMT void (IL 0x05C... ???) [000888] ------------ | /--* CNS_INT int 0 [000890] -A---------- \--* ASG int [000889] D------N---- \--* LCL_VAR int V56 tmp47 ***** BB57, stmt 113 [000886] ------------ * STMT void (IL 0x05C... ???) [000883] ------------ | /--* FIELD int _length [000881] L----------- | | \--* ADDR byref [000882] ------------ | | \--* LCL_VAR struct V50 tmp41 [000885] -A---------- \--* ASG int [000884] D------N---- \--* LCL_VAR int V56 tmp47 ***** BB57, stmt 114 [000801] ------------ * STMT void (IL 0x05C... ???) [000887] ------------ | /--* LCL_VAR int V56 tmp47 [000800] -AC--------- \--* ASG int [000799] D------N---- \--* LCL_VAR int V52 tmp43 ***** BB57, stmt 115 [000904] ------------ * STMT void (IL 0x05C... ???) [000901] ------------ | /--* CNS_INT int 0 [000903] -A---------- \--* ASG int [000902] D------N---- \--* LCL_VAR int V57 tmp48 ***** BB57, stmt 116 [000899] ------------ * STMT void (IL 0x05C... ???) [000896] ------------ | /--* FIELD int _length [000894] L----------- | | \--* ADDR byref [000895] ------------ | | \--* LCL_VAR struct V51 tmp42 [000898] -A---------- \--* ASG int [000897] D------N---- \--* LCL_VAR int V57 tmp48 ***** BB57, stmt 117 [000809] ------------ * STMT void (IL 0x05C... ???) [000805] ------------ | /--* CNS_INT int 0 [000806] --C--------- | /--* EQ int [000900] ------------ | | | /--* LCL_VAR int V57 tmp48 [000804] --C--------- | | \--* EQ int [000802] ------------ | | \--* LCL_VAR int V52 tmp43 [000808] -AC--------- \--* ASG bool [000807] D------N---- \--* LCL_VAR bool V53 tmp44 ***** BB57, stmt 118 [000814] ------------ * STMT void (IL 0x05C... ???) [000813] ------------ \--* JTRUE void [000811] ------------ | /--* CNS_INT int 0 [000812] ------------ \--* EQ int [000810] ------------ \--* LCL_VAR int V53 tmp44 ------------ BB58 [05C..05D) -> BB62 (always), preds={} succs={BB62} ***** BB58, stmt 119 [000858] ------------ * STMT void (IL 0x05C... ???) [000855] ------------ | /--* CNS_INT int 0 [000857] -A---------- \--* ASG bool [000856] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB59 [05C..05D) -> BB61 (cond), preds={} succs={BB60,BB61} ***** BB59, stmt 120 [000917] ------------ * STMT void (IL 0x05C... ???) [000914] ------------ | /--* CNS_INT int 0 [000916] -A---------- \--* ASG int [000915] D------N---- \--* LCL_VAR int V58 tmp49 ***** BB59, stmt 121 [000912] ------------ * STMT void (IL 0x05C... ???) [000909] ------------ | /--* FIELD int _length [000907] L----------- | | \--* ADDR byref [000908] ------------ | | \--* LCL_VAR struct V51 tmp42 [000911] -A---------- \--* ASG int [000910] D------N---- \--* LCL_VAR int V58 tmp49 ***** BB59, stmt 122 [000825] ------------ * STMT void (IL 0x05C... ???) [000821] ------------ | /--* CNS_INT int 0 [000822] --C--------- | /--* EQ int [000913] ------------ | | \--* LCL_VAR int V58 tmp49 [000824] -AC--------- \--* ASG bool [000823] D------N---- \--* LCL_VAR bool V54 tmp45 ***** BB59, stmt 123 [000830] ------------ * STMT void (IL 0x05C... ???) [000829] ------------ \--* JTRUE void [000827] ------------ | /--* CNS_INT int 0 [000828] ------------ \--* EQ int [000826] ------------ \--* LCL_VAR int V54 tmp45 ------------ BB60 [05C..05D) -> BB62 (always), preds={} succs={BB62} ***** BB60, stmt 124 [000853] ------------ * STMT void (IL 0x05C... ???) [000850] ------------ | /--* CNS_INT int 1 [000852] -A---------- \--* ASG bool [000851] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB61 [05C..05D), preds={} succs={BB62} ***** BB61, stmt 125 [000845] ------------ * STMT void (IL 0x05C... ???) [000841] ------------ | /--* CNS_INT int 0 [000842] --C-G------- | /--* EQ int [000834] --C-G------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000839] x----------- arg0 | | +--* OBJ(16) struct [000838] L----------- | | | \--* ADDR byref [000832] ------------ | | | \--* LCL_VAR struct V50 tmp41 [000836] x----------- arg1 | | \--* OBJ(16) struct [000835] L----------- | | \--* ADDR byref [000833] ------------ | | \--* LCL_VAR struct V51 tmp42 [000844] -AC-G------- \--* ASG bool [000843] D------N---- \--* LCL_VAR bool V55 tmp46 ------------ BB62 [05C..05D), preds={} succs={BB63} ------------ BB63 [???..???) -> BB09 (cond), preds={} succs={BB08,BB09} ***** BB63, stmt 126 [000105] ------------ * STMT void (IL ???... ???) [000102] --C--------- | /--* CAST int <- bool <- int [000848] ------------ | | \--* CAST int <- bool <- int [000847] ------------ | | \--* LCL_VAR int V55 tmp46 [000104] -AC--------- \--* ASG int [000103] D------N---- \--* LCL_VAR int V08 loc6 ***** BB63, stmt 127 [000110] ------------ * STMT void (IL 0x065...0x067) [000109] ------------ \--* JTRUE void [000107] ------------ | /--* CNS_INT int 0 [000108] ------------ \--* EQ int [000106] ------------ \--* LCL_VAR int V08 loc6 ------------ BB08 [069..071) -> BB10 (always), preds={} succs={BB10} ***** BB08, stmt 128 [000130] ------------ * STMT void (IL 0x06A...0x06C) [000127] ------------ | /--* CNS_INT int 0 [000129] -A-XG------- \--* ASG byte [000128] *------N---- \--* IND byte [000126] ------------ \--* LCL_VAR byref V01 arg1 ***** BB08, stmt 129 [000134] ------------ * STMT void (IL 0x06D...0x06E) [000131] ------------ | /--* CNS_INT int 1 [000133] -A---------- \--* ASG int [000132] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB09 [071..078) -> BB10 (always), preds={} succs={BB10} ***** BB09, stmt 130 [000116] ------------ * STMT void (IL 0x071...0x073) [000113] ------------ | /--* CNS_INT int 0 [000115] -A-XG------- \--* ASG byte [000114] *------N---- \--* IND byte [000112] ------------ \--* LCL_VAR byref V01 arg1 ***** BB09, stmt 131 [000120] ------------ * STMT void (IL 0x074...0x075) [000117] ------------ | /--* CNS_INT int 0 [000119] -A---------- \--* ASG int [000118] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB10 [078..07A) (return), preds={} succs={} ***** BB10, stmt 132 [000124] ------------ * STMT void (IL 0x078...0x079) [000123] ------------ \--* RETURN int [000122] ------------ \--* LCL_VAR int V05 loc3 ------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty **************** Inline Tree Inlines into 0600088B System.Boolean:TryParse(struct,byref):bool [1 IL=0006 TR=000002 06000D5D] [aggressive inline attribute] System.MemoryExtensions:AsSpan(ref):struct [2 IL=0022 TR=000179 0600037E] [below ALWAYS_INLINE size] System.String:GetRawStringData():byref:this [3 IL=0028 TR=000183 0600035D] [below ALWAYS_INLINE size] System.String:get_Length():int:this [4 IL=0033 TR=000196 06000DEF] [aggressive inline attribute] System.ReadOnlySpan`1:.ctor(byref,int):this [0 IL=0008 TR=000254 060024C6] [FAILED: unprofitable inline] System.Diagnostics.Debug:Assert(bool) [5 IL=0014 TR=000012 06000D52] [aggressive inline attribute] System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool [6 IL=0003 TR=000285 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [7 IL=0010 TR=000290 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [8 IL=0030 TR=000311 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [0 IL=0048 TR=000327 060020FF] [FAILED: too many il bytes] System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int [9 IL=0036 TR=000032 06000D5D] [aggressive inline attribute] System.MemoryExtensions:AsSpan(ref):struct [10 IL=0022 TR=000426 0600037E] [below ALWAYS_INLINE size] System.String:GetRawStringData():byref:this [11 IL=0028 TR=000430 0600035D] [below ALWAYS_INLINE size] System.String:get_Length():int:this [12 IL=0033 TR=000443 06000DEF] [aggressive inline attribute] System.ReadOnlySpan`1:.ctor(byref,int):this [0 IL=0008 TR=000501 060024C6] [FAILED: unprofitable inline] System.Diagnostics.Debug:Assert(bool) [13 IL=0044 TR=000042 06000D52] [aggressive inline attribute] System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool [14 IL=0003 TR=000532 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [15 IL=0010 TR=000537 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [16 IL=0030 TR=000558 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [0 IL=0048 TR=000574 060020FF] [FAILED: too many il bytes] System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int [0 IL=0064 TR=000062 0600088C] [FAILED: too many il bytes] System.Boolean:TrimWhiteSpaceAndNull(struct):struct [17 IL=0073 TR=000072 06000D52] [aggressive inline attribute] System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool [18 IL=0003 TR=000662 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [19 IL=0010 TR=000667 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [20 IL=0030 TR=000688 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [0 IL=0048 TR=000704 060020FF] [FAILED: too many il bytes] System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int [21 IL=0094 TR=000093 06000D52] [aggressive inline attribute] System.MemoryExtensions:EqualsOrdinalIgnoreCase(struct,struct):bool [22 IL=0003 TR=000792 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [23 IL=0010 TR=000797 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [24 IL=0030 TR=000818 06000DE3] [below ALWAYS_INLINE size] System.ReadOnlySpan`1:get_Length():int:this [0 IL=0048 TR=000834 060020FF] [FAILED: too many il bytes] System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int Budget: initialTime=426, finalTime=1250, initialBudget=4260, currentBudget=4944 Budget: increased by 684 because of force inlines Budget: initialSize=2912, finalSize=2912 *************** After fgAddInternal() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i BB11 [0010] 1 1 [001..002)-> BB13 ( cond ) i BB12 [0011] 1 0.50 [001..002)-> BB14 (always) i BB13 [0012] 1 0.50 [001..002) i BB14 [0013] 2 1 [001..002) i BB15 [0014] 1 1 [???..???) internal BB19 [0018] 1 1 [00C..00D)-> BB21 ( cond ) i BB20 [0019] 1 0.50 [00C..00D)-> BB24 (always) i BB21 [0020] 1 0.50 [00C..00D)-> BB23 ( cond ) i BB22 [0021] 1 0.50 [00C..00D)-> BB24 (always) i BB23 [0022] 1 0.50 [00C..00D) i BB24 [0023] 3 1 [00C..00D) i BB25 [0024] 1 1 [???..???)-> BB03 ( cond ) internal BB02 [0001] 1 1 [017..01F)-> BB10 (always) i BB03 [0002] 1 1 [01F..037) i BB29 [0028] 1 1 [01F..020)-> BB31 ( cond ) i BB30 [0029] 1 0.50 [01F..020)-> BB32 (always) i BB31 [0030] 1 0.50 [01F..020) i BB32 [0031] 2 1 [01F..020) i BB33 [0032] 1 1 [???..???) internal BB37 [0036] 1 1 [02A..02B)-> BB39 ( cond ) i BB38 [0037] 1 0.50 [02A..02B)-> BB42 (always) i BB39 [0038] 1 0.50 [02A..02B)-> BB41 ( cond ) i BB40 [0039] 1 0.50 [02A..02B)-> BB42 (always) i BB41 [0040] 1 0.50 [02A..02B) i BB42 [0041] 3 1 [02A..02B) i BB43 [0042] 1 1 [???..???)-> BB05 ( cond ) internal BB04 [0003] 1 1 [037..03F)-> BB10 (always) i BB05 [0004] 1 1 [03F..054) i BB47 [0046] 1 1 [047..048)-> BB49 ( cond ) i BB48 [0047] 1 0.50 [047..048)-> BB52 (always) i BB49 [0048] 1 0.50 [047..048)-> BB51 ( cond ) i BB50 [0049] 1 0.50 [047..048)-> BB52 (always) i BB51 [0050] 1 0.50 [047..048) i BB52 [0051] 3 1 [047..048) i BB53 [0052] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [054..05C)-> BB10 (always) i BB07 [0006] 1 1 [05C..069) i BB57 [0056] 1 1 [05C..05D)-> BB59 ( cond ) i BB58 [0057] 1 0.50 [05C..05D)-> BB62 (always) i BB59 [0058] 1 0.50 [05C..05D)-> BB61 ( cond ) i BB60 [0059] 1 0.50 [05C..05D)-> BB62 (always) i BB61 [0060] 1 0.50 [05C..05D) i BB62 [0061] 3 1 [05C..05D) i BB63 [0062] 1 1 [???..???)-> BB09 ( cond ) internal BB08 [0007] 1 1 [069..071)-> BB10 (always) i BB09 [0008] 1 1 [071..078)-> BB10 (always) i BB10 [0009] 5 1 [078..07A) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** In fgRemoveEmptyFinally() No EH in this method, nothing to remove. *************** In fgMergeFinallyChains() No EH in this method, nothing to merge. *************** In fgCloneFinally() No EH in this method, no cloning. *************** In fgMarkImplicitByRefs() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct (16) ; V01 arg1 byref ; V02 loc0 struct (16) ; V03 loc1 struct (16) ; V04 loc2 bool ; V05 loc3 bool ; V06 loc4 bool ; V07 loc5 bool ; V08 loc6 bool ; V09 tmp0 bool ; V10 tmp1 byref ; V11 tmp2 struct (16) ; V12 tmp3 struct (16) ; V13 tmp4 struct (16) ld-addr-op ; V14 tmp5 int ; V15 tmp6 struct ( 8) ; V16 tmp7 struct (16) ld-addr-op ; V17 tmp8 struct (16) ld-addr-op ; V18 tmp9 int ; V19 tmp10 bool ; V20 tmp11 bool ; V21 tmp12 bool ; V22 tmp13 int ; V23 tmp14 int ; V24 tmp15 int ; V25 tmp16 bool ; V26 tmp17 byref ; V27 tmp18 struct (16) ; V28 tmp19 struct (16) ; V29 tmp20 struct (16) ld-addr-op ; V30 tmp21 int ; V31 tmp22 struct ( 8) ; V32 tmp23 struct (16) ld-addr-op ; V33 tmp24 struct (16) ld-addr-op ; V34 tmp25 int ; V35 tmp26 bool ; V36 tmp27 bool ; V37 tmp28 bool ; V38 tmp29 int ; V39 tmp30 int ; V40 tmp31 int ; V41 tmp32 struct (16) ld-addr-op ; V42 tmp33 struct (16) ld-addr-op ; V43 tmp34 int ; V44 tmp35 bool ; V45 tmp36 bool ; V46 tmp37 bool ; V47 tmp38 int ; V48 tmp39 int ; V49 tmp40 int ; V50 tmp41 struct (16) ld-addr-op ; V51 tmp42 struct (16) ld-addr-op ; V52 tmp43 int ; V53 tmp44 bool ; V54 tmp45 bool ; V55 tmp46 bool ; V56 tmp47 int ; V57 tmp48 int ; V58 tmp49 int Promoting struct local V00 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 59 (V59 tmp50) (a long lifetime temp) called for field V00._pointer (fldOffset=0x0). Set preferred register for V59 to [rcx] New refCnts for V59: refCnt = 1, refCntWtd = 1 lvaGrabTemp returning 60 (V60 tmp51) (a long lifetime temp) called for field V00._length (fldOffset=0x8). Set preferred register for V60 to [rcx] New refCnts for V60: refCnt = 1, refCntWtd = 1 Promoting struct local V02 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 61 (V61 tmp52) (a long lifetime temp) called for field V02._pointer (fldOffset=0x0). lvaGrabTemp returning 62 (V62 tmp53) (a long lifetime temp) called for field V02._length (fldOffset=0x8). Promoting struct local V03 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 63 (V63 tmp54) (a long lifetime temp) called for field V03._pointer (fldOffset=0x0). lvaGrabTemp returning 64 (V64 tmp55) (a long lifetime temp) called for field V03._length (fldOffset=0x8). Promoting struct local V11 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 65 (V65 tmp56) (a long lifetime temp) called for field V11._pointer (fldOffset=0x0). lvaGrabTemp returning 66 (V66 tmp57) (a long lifetime temp) called for field V11._length (fldOffset=0x8). Promoting struct local V12 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 67 (V67 tmp58) (a long lifetime temp) called for field V12._pointer (fldOffset=0x0). lvaGrabTemp returning 68 (V68 tmp59) (a long lifetime temp) called for field V12._length (fldOffset=0x8). Promoting struct local V13 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 69 (V69 tmp60) (a long lifetime temp) called for field V13._pointer (fldOffset=0x0). lvaGrabTemp returning 70 (V70 tmp61) (a long lifetime temp) called for field V13._length (fldOffset=0x8). Promoting struct local V15 ([S.P.CoreLib]System.ByReference`1): lvaGrabTemp returning 71 (V71 tmp62) (a long lifetime temp) called for field V15._value (fldOffset=0x0). Promoting struct local V16 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 72 (V72 tmp63) (a long lifetime temp) called for field V16._pointer (fldOffset=0x0). lvaGrabTemp returning 73 (V73 tmp64) (a long lifetime temp) called for field V16._length (fldOffset=0x8). Promoting struct local V17 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 74 (V74 tmp65) (a long lifetime temp) called for field V17._pointer (fldOffset=0x0). lvaGrabTemp returning 75 (V75 tmp66) (a long lifetime temp) called for field V17._length (fldOffset=0x8). Promoting struct local V27 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 76 (V76 tmp67) (a long lifetime temp) called for field V27._pointer (fldOffset=0x0). lvaGrabTemp returning 77 (V77 tmp68) (a long lifetime temp) called for field V27._length (fldOffset=0x8). Promoting struct local V28 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 78 (V78 tmp69) (a long lifetime temp) called for field V28._pointer (fldOffset=0x0). lvaGrabTemp returning 79 (V79 tmp70) (a long lifetime temp) called for field V28._length (fldOffset=0x8). Promoting struct local V29 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 80 (V80 tmp71) (a long lifetime temp) called for field V29._pointer (fldOffset=0x0). lvaGrabTemp returning 81 (V81 tmp72) (a long lifetime temp) called for field V29._length (fldOffset=0x8). Promoting struct local V31 ([S.P.CoreLib]System.ByReference`1): lvaGrabTemp returning 82 (V82 tmp73) (a long lifetime temp) called for field V31._value (fldOffset=0x0). Promoting struct local V32 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 83 (V83 tmp74) (a long lifetime temp) called for field V32._pointer (fldOffset=0x0). lvaGrabTemp returning 84 (V84 tmp75) (a long lifetime temp) called for field V32._length (fldOffset=0x8). Promoting struct local V33 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 85 (V85 tmp76) (a long lifetime temp) called for field V33._pointer (fldOffset=0x0). lvaGrabTemp returning 86 (V86 tmp77) (a long lifetime temp) called for field V33._length (fldOffset=0x8). Promoting struct local V41 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 87 (V87 tmp78) (a long lifetime temp) called for field V41._pointer (fldOffset=0x0). lvaGrabTemp returning 88 (V88 tmp79) (a long lifetime temp) called for field V41._length (fldOffset=0x8). Promoting struct local V42 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 89 (V89 tmp80) (a long lifetime temp) called for field V42._pointer (fldOffset=0x0). lvaGrabTemp returning 90 (V90 tmp81) (a long lifetime temp) called for field V42._length (fldOffset=0x8). Promoting struct local V50 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 91 (V91 tmp82) (a long lifetime temp) called for field V50._pointer (fldOffset=0x0). lvaGrabTemp returning 92 (V92 tmp83) (a long lifetime temp) called for field V50._length (fldOffset=0x8). Promoting struct local V51 ([S.P.CoreLib]System.ReadOnlySpan`1): lvaGrabTemp returning 93 (V93 tmp84) (a long lifetime temp) called for field V51._pointer (fldOffset=0x0). lvaGrabTemp returning 94 (V94 tmp85) (a long lifetime temp) called for field V51._length (fldOffset=0x8). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 struct (16) ; V01 arg1 byref ; V02 loc0 struct (16) ; V03 loc1 struct (16) ; V04 loc2 bool ; V05 loc3 bool ; V06 loc4 bool ; V07 loc5 bool ; V08 loc6 bool ; V09 tmp0 bool ; V10 tmp1 byref ; V11 tmp2 struct (16) ; V12 tmp3 struct (16) ; V13 tmp4 struct (16) ld-addr-op ; V14 tmp5 int ; V15 tmp6 struct ( 8) ; V16 tmp7 struct (16) ld-addr-op ; V17 tmp8 struct (16) ld-addr-op ; V18 tmp9 int ; V19 tmp10 bool ; V20 tmp11 bool ; V21 tmp12 bool ; V22 tmp13 int ; V23 tmp14 int ; V24 tmp15 int ; V25 tmp16 bool ; V26 tmp17 byref ; V27 tmp18 struct (16) ; V28 tmp19 struct (16) ; V29 tmp20 struct (16) ld-addr-op ; V30 tmp21 int ; V31 tmp22 struct ( 8) ; V32 tmp23 struct (16) ld-addr-op ; V33 tmp24 struct (16) ld-addr-op ; V34 tmp25 int ; V35 tmp26 bool ; V36 tmp27 bool ; V37 tmp28 bool ; V38 tmp29 int ; V39 tmp30 int ; V40 tmp31 int ; V41 tmp32 struct (16) ld-addr-op ; V42 tmp33 struct (16) ld-addr-op ; V43 tmp34 int ; V44 tmp35 bool ; V45 tmp36 bool ; V46 tmp37 bool ; V47 tmp38 int ; V48 tmp39 int ; V49 tmp40 int ; V50 tmp41 struct (16) ld-addr-op ; V51 tmp42 struct (16) ld-addr-op ; V52 tmp43 int ; V53 tmp44 bool ; V54 tmp45 bool ; V55 tmp46 bool ; V56 tmp47 int ; V57 tmp48 int ; V58 tmp49 int ; V59 tmp50 byref V00._pointer(offs=0x00) P-INDEP ; V60 tmp51 int V00._length(offs=0x08) P-INDEP ; V61 tmp52 byref V02._pointer(offs=0x00) P-INDEP ; V62 tmp53 int V02._length(offs=0x08) P-INDEP ; V63 tmp54 byref V03._pointer(offs=0x00) P-INDEP ; V64 tmp55 int V03._length(offs=0x08) P-INDEP ; V65 tmp56 byref V11._pointer(offs=0x00) P-INDEP ; V66 tmp57 int V11._length(offs=0x08) P-INDEP ; V67 tmp58 byref V12._pointer(offs=0x00) P-INDEP ; V68 tmp59 int V12._length(offs=0x08) P-INDEP ; V69 tmp60 byref V13._pointer(offs=0x00) P-INDEP ; V70 tmp61 int V13._length(offs=0x08) P-INDEP ; V71 tmp62 byref V15._value(offs=0x00) P-INDEP ; V72 tmp63 byref V16._pointer(offs=0x00) P-INDEP ; V73 tmp64 int V16._length(offs=0x08) P-INDEP ; V74 tmp65 byref V17._pointer(offs=0x00) P-INDEP ; V75 tmp66 int V17._length(offs=0x08) P-INDEP ; V76 tmp67 byref V27._pointer(offs=0x00) P-INDEP ; V77 tmp68 int V27._length(offs=0x08) P-INDEP ; V78 tmp69 byref V28._pointer(offs=0x00) P-INDEP ; V79 tmp70 int V28._length(offs=0x08) P-INDEP ; V80 tmp71 byref V29._pointer(offs=0x00) P-INDEP ; V81 tmp72 int V29._length(offs=0x08) P-INDEP ; V82 tmp73 byref V31._value(offs=0x00) P-INDEP ; V83 tmp74 byref V32._pointer(offs=0x00) P-INDEP ; V84 tmp75 int V32._length(offs=0x08) P-INDEP ; V85 tmp76 byref V33._pointer(offs=0x00) P-INDEP ; V86 tmp77 int V33._length(offs=0x08) P-INDEP ; V87 tmp78 byref V41._pointer(offs=0x00) P-INDEP ; V88 tmp79 int V41._length(offs=0x08) P-INDEP ; V89 tmp80 byref V42._pointer(offs=0x00) P-INDEP ; V90 tmp81 int V42._length(offs=0x08) P-INDEP ; V91 tmp82 byref V50._pointer(offs=0x00) P-INDEP ; V92 tmp83 int V50._length(offs=0x08) P-INDEP ; V93 tmp84 byref V51._pointer(offs=0x00) P-INDEP ; V94 tmp85 int V51._length(offs=0x08) P-INDEP *************** In fgMarkAddressExposedLocals() Replacing the field in promoted struct with a local var: [000188] ------------ /--* LCL_VAR byref V10 tmp1 [000266] -A---------- * ASG byref [000265] D------N---- \--* LCL_VAR byref V71 tmp62 Replacing the field in promoted struct with a local var: [000267] ------------ /--* LCL_VAR struct(P) V15 tmp6 /--* byref V15._value (offs=0x00) -> V71 tmp62 [000272] -A------R--- * ASG struct (copy) [000271] ------------ \--* OBJ(8) struct [000270] ------------ \--* ADDR byref [000269] ------------ \--* LCL_VAR byref V65 tmp56 Replacing the field in promoted struct with a local var: [000276] ------------ /--* LCL_VAR int V14 tmp5 [000278] -A---------- * ASG int [000277] D------N---- \--* LCL_VAR int V66 tmp57 Incrementing ref count from 0 to 1 for V00 in fgMorphStructField Replacing the field in promoted struct with a local var: [000376] ------------ /--* LCL_VAR int V73 tmp64 [000378] -A---------- * ASG int [000377] D------N---- \--* LCL_VAR int V22 tmp13 Replacing the field in promoted struct with a local var: [000389] ------------ /--* LCL_VAR int V75 tmp66 [000391] -A---------- * ASG int [000390] D------N---- \--* LCL_VAR int V23 tmp14 Replacing the field in promoted struct with a local var: [000402] ------------ /--* LCL_VAR int V75 tmp66 [000404] -A---------- * ASG int [000403] D------N---- \--* LCL_VAR int V24 tmp15 Replacing the field in promoted struct with a local var: [000435] ------------ /--* LCL_VAR byref V26 tmp17 [000513] -A---------- * ASG byref [000512] D------N---- \--* LCL_VAR byref V82 tmp73 Replacing the field in promoted struct with a local var: [000514] ------------ /--* LCL_VAR struct(P) V31 tmp22 /--* byref V31._value (offs=0x00) -> V82 tmp73 [000519] -A------R--- * ASG struct (copy) [000518] ------------ \--* OBJ(8) struct [000517] ------------ \--* ADDR byref [000516] ------------ \--* LCL_VAR byref V76 tmp67 Replacing the field in promoted struct with a local var: [000523] ------------ /--* LCL_VAR int V30 tmp21 [000525] -A---------- * ASG int [000524] D------N---- \--* LCL_VAR int V77 tmp68 Incrementing ref count from 1 to 2 for V00 in fgMorphStructField Replacing the field in promoted struct with a local var: [000623] ------------ /--* LCL_VAR int V84 tmp75 [000625] -A---------- * ASG int [000624] D------N---- \--* LCL_VAR int V38 tmp29 Replacing the field in promoted struct with a local var: [000636] ------------ /--* LCL_VAR int V86 tmp77 [000638] -A---------- * ASG int [000637] D------N---- \--* LCL_VAR int V39 tmp30 Replacing the field in promoted struct with a local var: [000649] ------------ /--* LCL_VAR int V86 tmp77 [000651] -A---------- * ASG int [000650] D------N---- \--* LCL_VAR int V40 tmp31 Incrementing ref count from 2 to 3 for V00 in fgMorphStructField Local V59 should not be enregistered because: it is address exposed Local V60 should not be enregistered because: it is address exposed Local V00 should not be enregistered because: it is address exposed Incrementing ref count from 3 to 4 for V00 in fgMorphStructField Incrementing ref count from 4 to 5 for V00 in fgMorphStructField Replacing the field in promoted struct with a local var: [000753] ------------ /--* LCL_VAR int V88 tmp79 [000755] -A---------- * ASG int [000754] D------N---- \--* LCL_VAR int V47 tmp38 Replacing the field in promoted struct with a local var: [000766] ------------ /--* LCL_VAR int V90 tmp81 [000768] -A---------- * ASG int [000767] D------N---- \--* LCL_VAR int V48 tmp39 Replacing the field in promoted struct with a local var: [000779] ------------ /--* LCL_VAR int V90 tmp81 [000781] -A---------- * ASG int [000780] D------N---- \--* LCL_VAR int V49 tmp40 Incrementing ref count from 5 to 6 for V00 in fgMorphStructField Replacing the field in promoted struct with a local var: [000883] ------------ /--* LCL_VAR int V92 tmp83 [000885] -A---------- * ASG int [000884] D------N---- \--* LCL_VAR int V56 tmp47 Replacing the field in promoted struct with a local var: [000896] ------------ /--* LCL_VAR int V94 tmp85 [000898] -A---------- * ASG int [000897] D------N---- \--* LCL_VAR int V57 tmp48 Replacing the field in promoted struct with a local var: [000909] ------------ /--* LCL_VAR int V94 tmp85 [000911] -A---------- * ASG int [000910] D------N---- \--* LCL_VAR int V58 tmp49 *************** In fgRetypeImplicitByRefArgs() lvaGrabTemp returning 95 (V95 tmp86) (a long lifetime temp) called for Promoted implicit byref. Changing the lvType for struct parameter V00 to TYP_BYREF. *************** In fgMorphBlocks() Morphing BB01 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB01, stmt 1 (before) [000221] ------------ /--* CNS_INT int 0 [000223] -A---------- * ASG bool [000222] D------N---- \--* LCL_VAR bool V09 tmp0 GenTreeNode creates assertion: [000223] -A---------- * ASG bool In BB01 New Local Constant Assertion: V09 == 0 index=#01, mask=0000000000000001 Morphing BB11 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB11, stmt 2 (before) [000167] ------------ /--* CNS_INT ref null [000168] ------------ /--* EQ int [000166] ------------ | \--* CNS_STR ref [000170] -A---------- * ASG bool [000169] D------N---- \--* LCL_VAR bool V09 tmp0 GenTreeNode creates assertion: [000170] -A---------- * ASG bool In BB11 New Local Subrange Assertion: V09 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB11, stmt 2 (after) [000167] -----+------ /--* CNS_INT ref null [000168] -----+------ /--* EQ int [000921] -----+------ | \--* NOP ref [000920] -----+------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000170] -A---+------ * ASG bool [000169] D----+-N---- \--* LCL_VAR int V09 tmp0 fgMorphTree BB11, stmt 3 (before) [000175] ------------ * JTRUE void [000173] ------------ | /--* CNS_INT int 0 [000174] ------------ \--* EQ int [000172] ------------ \--* LCL_VAR int V09 tmp0 Morphing BB12 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB12, stmt 4 (before) [000213] ------------ /--* CNS_INT int 0 [000214] IA------R--- * ASG struct (init) [000211] D------N---- \--* LCL_VAR struct(P) V13 tmp4 \--* byref V13._pointer (offs=0x00) -> V69 tmp60 \--* int V13._length (offs=0x08) -> V70 tmp61 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [000924] -A---------- * ASG byref In BB12 New Local Constant Assertion: V69 == 0 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000927] -A---------- * ASG int In BB12 New Local Constant Assertion: V70 == 0 index=#02, mask=0000000000000002 fgMorphInitBlock (after): [000926] ------------ /--* CNS_INT int 0 [000927] -A---------- /--* ASG int [000925] D------N---- | \--* LCL_VAR int V70 tmp61 [000928] -A---+------ * COMMA void [000923] ------------ | /--* CNS_INT byref 0 [000924] -A---------- \--* ASG byref [000922] D------N---- \--* LCL_VAR byref V69 tmp60 fgMorphTree BB12, stmt 4 (after) [000926] ------------ /--* CNS_INT int 0 [000927] -A---------- /--* ASG int [000925] D------N---- | \--* LCL_VAR int V70 tmp61 [000928] -A---+------ * COMMA void [000923] ------------ | /--* CNS_INT byref 0 [000924] -A---------- \--* ASG byref [000922] D------N---- \--* LCL_VAR byref V69 tmp60 fgMorphTree BB12, stmt 5 (before) [000216] ------------ /--* LCL_VAR struct(P) V13 tmp4 /--* byref V13._pointer (offs=0x00) -> V69 tmp60 /--* int V13._length (offs=0x08) -> V70 tmp61 [000219] -A------R--- * ASG struct (copy) [000217] D----------- \--* LCL_VAR struct(P) V12 tmp3 \--* byref V12._pointer (offs=0x00) -> V67 tmp58 \--* int V12._length (offs=0x08) -> V68 tmp59 fgMorphCopyBlock:block assignment to morph: [000216] -----+------ /--* LCL_VAR struct(P) V13 tmp4 /--* byref V13._pointer (offs=0x00) -> V69 tmp60 /--* int V13._length (offs=0x08) -> V70 tmp61 [000219] -A------R--- * ASG struct (copy) [000217] D----+-N---- \--* LCL_VAR struct(P) V12 tmp3 \--* byref V12._pointer (offs=0x00) -> V67 tmp58 \--* int V12._length (offs=0x08) -> V68 tmp59 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000931] -A---------- * ASG byref In BB12 New Local Copy Assertion: V67 == V69 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [000934] -A---------- * ASG int In BB12 New Local Copy Assertion: V68 == V70 index=#04, mask=0000000000000008 fgMorphCopyBlock (after): [000933] -------N---- /--* LCL_VAR int V70 tmp61 [000934] -A---------- /--* ASG int [000932] D------N---- | \--* LCL_VAR int V68 tmp59 [000935] -A---+------ * COMMA void [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 [000931] -A---------- \--* ASG byref [000929] D------N---- \--* LCL_VAR byref V67 tmp58 fgMorphTree BB12, stmt 5 (after) [000933] -------N---- /--* LCL_VAR int V70 tmp61 [000934] -A---------- /--* ASG int [000932] D------N---- | \--* LCL_VAR int V68 tmp59 [000935] -A---+------ * COMMA void [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 [000931] -A---------- \--* ASG byref [000929] D------N---- \--* LCL_VAR byref V67 tmp58 Morphing BB13 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB13, stmt 6 (before) [000231] ---X-------- * IND int [000230] ------------ \--* CNS_STR ref fgMorphTree BB13, stmt 6 (after) [000231] x----+------ * IND int [000937] -----+------ \--* NOP ref [000936] -----+------ \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] Removing statement [000232] in BB13 as useless: [000232] ------------ * STMT void (IL 0x001... ???) [000231] x----+------ \--* IND int [000937] -----+------ \--* NOP ref [000936] -----+------ \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] fgMorphTree BB13, stmt 7 (before) [000229] ---XG------- /--* ADDR byref [000228] ---XG------- | \--* FIELD ushort _firstChar [000227] ------------ | \--* CNS_STR ref [000186] -AC--------- * ASG byref [000185] D------N---- \--* LCL_VAR byref V10 tmp1 Before explicit null check morphing: [000228] ---XG--N---- * FIELD ushort _firstChar [000227] ------------ \--* CNS_STR ref lvaGrabTemp returning 96 (V96 tmp87) (a long lifetime temp) called for Big Offset Morphing. After adding explicit null check: [000228] ---XG--N---- * IND ushort [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [000945] ------------ | /--* ADD byref [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 [000946] -A-X-------- \--* COMMA byref [000941] ---X---N---- | /--* NULLCHECK byte [000940] ------------ | | \--* LCL_VAR ref V96 tmp87 [000942] -A-X-------- \--* COMMA void [000227] ------------ | /--* CNS_STR ref [000939] -A---------- \--* ASG ref [000938] D------N---- \--* LCL_VAR ref V96 tmp87 GenTreeNode creates assertion: [000941] ---X---N---- * NULLCHECK byte In BB13 New Local Constant Assertion: V96 != null index=#01, mask=0000000000000001 fgMorphTree BB13, stmt 7 (after) [000944] -----+------ /--* CNS_INT long 12 field offset Fseq[_firstChar] [000945] -----+------ /--* ADD byref [000943] -----+------ | \--* LCL_VAR ref V96 tmp87 [000946] -A-XG+-N---- /--* COMMA byref [000941] ---X-+-N---- | | /--* NULLCHECK byte [000940] -----+------ | | | \--* LCL_VAR ref V96 tmp87 [000949] -A-X-------- | \--* COMMA void [000948] -----+------ | | /--* NOP ref [000947] -----+------ | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000939] -A---+------ | \--* ASG ref [000938] D----+-N---- | \--* LCL_VAR ref V96 tmp87 [000186] -A-XG+------ * ASG byref [000185] D----+-N---- \--* LCL_VAR byref V10 tmp1 fgMorphTree BB13, stmt 8 (before) [000242] ---X-------- * IND int [000241] ------------ \--* CNS_STR ref fgMorphTree BB13, stmt 8 (after) [000242] x----+------ * IND int [000952] -----+------ \--* NOP ref [000951] -----+------ \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] Removing statement [000243] in BB13 as useless: [000243] ------------ * STMT void (IL 0x001... ???) [000242] x----+------ \--* IND int [000952] -----+------ \--* NOP ref [000951] -----+------ \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] fgMorphTree BB13, stmt 9 (before) [000244] ------------ /--* CNS_INT int 0 [000246] -A---------- * ASG int [000245] D------N---- \--* LCL_VAR int V14 tmp5 GenTreeNode creates assertion: [000246] -A---------- * ASG int In BB13 New Local Constant Assertion: V14 == 0 index=#02, mask=0000000000000002 fgMorphTree BB13, stmt 10 (before) [000236] ---XG------- /--* FIELD int _stringLength [000235] ------------ | \--* CNS_STR ref [000238] -A-XG------- * ASG int [000237] D------N---- \--* LCL_VAR int V14 tmp5 The assignment [000238] using V14 removes: Constant Assertion: V14 == 0 GenTreeNode creates assertion: [000238] -A--G------- * ASG int In BB13 New Local Subrange Assertion: V14 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB13, stmt 10 (after) [000236] x---G+------ /--* IND int [000953] -----+------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [000954] -----+------ | \--* ADD byref [000956] -----+------ | \--* NOP ref [000955] -----+------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000238] -A--G+------ * ASG int [000237] D----+-N---- \--* LCL_VAR int V14 tmp5 fgMorphTree BB13, stmt 11 (before) [000191] ------------ /--* CNS_INT int 0 [000192] IA------R--- * ASG struct (init) [000190] D------N---- \--* LCL_VAR struct(P) V11 tmp2 \--* byref V11._pointer (offs=0x00) -> V65 tmp56 \--* int V11._length (offs=0x08) -> V66 tmp57 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [000959] -A---------- * ASG byref In BB13 New Local Constant Assertion: V65 == 0 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [000962] -A---------- * ASG int In BB13 New Local Constant Assertion: V66 == 0 index=#04, mask=0000000000000008 fgMorphInitBlock (after): [000961] ------------ /--* CNS_INT int 0 [000962] -A---------- /--* ASG int [000960] D------N---- | \--* LCL_VAR int V66 tmp57 [000963] -A---+------ * COMMA void [000958] ------------ | /--* CNS_INT byref 0 [000959] -A---------- \--* ASG byref [000957] D------N---- \--* LCL_VAR byref V65 tmp56 fgMorphTree BB13, stmt 11 (after) [000961] ------------ /--* CNS_INT int 0 [000962] -A---------- /--* ASG int [000960] D------N---- | \--* LCL_VAR int V66 tmp57 [000963] -A---+------ * COMMA void [000958] ------------ | /--* CNS_INT byref 0 [000959] -A---------- \--* ASG byref [000957] D------N---- \--* LCL_VAR byref V65 tmp56 fgMorphTree BB13, stmt 12 (before) [000254] --C-G------- * CALL void System.Diagnostics.Debug.Assert [000252] ------------ | /--* CNS_INT int 0 [000253] ------------ arg0 \--* EQ int [000250] ------------ | /--* CNS_INT int 0 [000251] ------------ \--* LT int [000240] ------------ \--* LCL_VAR int V14 tmp5 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000250] -----+------ /--* CNS_INT int 0 [000251] -----+------ * GE int [000240] -----+------ \--* LCL_VAR int V14 tmp5 Replaced with placeholder node: [000964] ----------L- * ARGPLACE int Shuffled argument table: rcx fgArgTabEntry[arg 0 251.GE, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB13, stmt 12 (after) [000254] --CXG+------ * CALL void System.Diagnostics.Debug.Assert [000250] -----+------ | /--* CNS_INT int 0 [000251] -----+------ arg0 in rcx \--* GE int [000240] -----+------ \--* LCL_VAR int V14 tmp5 fgMorphTree BB13, stmt 13 (before) [000260] ------------ /--* CNS_INT int 0 [000261] IA------R--- * ASG struct (init) [000259] D------N---- \--* LCL_VAR struct(P) V15 tmp6 \--* byref V15._value (offs=0x00) -> V71 tmp62 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [000968] -A---------- * ASG byref In BB13 New Local Constant Assertion: V71 == 0 index=#05, mask=0000000000000010 fgMorphInitBlock (after): [000967] ------------ /--* CNS_INT byref 0 [000968] -A---+------ * ASG byref [000966] D------N---- \--* LCL_VAR byref V71 tmp62 The assignment [000968] using V71 removes: Constant Assertion: V71 == 0 GenTreeNode creates assertion: [000968] -A---+------ * ASG byref In BB13 New Local Constant Assertion: V71 == 0 index=#05, mask=0000000000000010 fgMorphTree BB13, stmt 13 (after) [000967] ------------ /--* CNS_INT byref 0 [000968] -A---+------ * ASG byref [000966] D------N---- \--* LCL_VAR byref V71 tmp62 fgMorphTree BB13, stmt 14 (before) [000188] ------------ /--* LCL_VAR byref V10 tmp1 [000266] -A---------- * ASG byref [000265] D------N---- \--* LCL_VAR byref V71 tmp62 The assignment [000266] using V71 removes: Constant Assertion: V71 == 0 GenTreeNode creates assertion: [000266] -A---------- * ASG byref In BB13 New Local Copy Assertion: V71 == V10 index=#05, mask=0000000000000010 fgMorphTree BB13, stmt 15 (before) [000267] ------------ /--* LCL_VAR struct(P) V15 tmp6 /--* byref V15._value (offs=0x00) -> V71 tmp62 [000272] -A------R--- * ASG struct (copy) [000271] ------------ \--* OBJ(8) struct [000270] ------------ \--* ADDR byref [000269] ------------ \--* LCL_VAR byref V65 tmp56 The assignment [000271] using V65 removes: Constant Assertion: V65 == 0 fgMorphCopyBlock:block assignment to morph: [000267] -----+------ /--* LCL_VAR struct(P) V15 tmp6 /--* byref V15._value (offs=0x00) -> V71 tmp62 [000272] -A------R--- * ASG struct (copy) [000271] x----+------ \--* OBJ(8) struct [000270] -----+------ \--* ADDR byref [000269] D----+-N---- \--* LCL_VAR byref V65 tmp56 (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000971] -A---------- * ASG byref In BB13 New Local Copy Assertion: V65 == V71 index=#05, mask=0000000000000010 fgMorphCopyBlock (after): [000970] -------N---- /--* LCL_VAR byref V71 tmp62 [000971] -A---+------ * ASG byref [000969] D------N---- \--* LCL_VAR byref V65 tmp56 The assignment [000971] using V65 removes: Copy Assertion: V65 == V71 GenTreeNode creates assertion: [000971] -A---+------ * ASG byref In BB13 New Local Copy Assertion: V65 == V71 index=#05, mask=0000000000000010 fgMorphTree BB13, stmt 15 (after) [000970] -------N---- /--* LCL_VAR byref V71 tmp62 [000971] -A---+------ * ASG byref [000969] D------N---- \--* LCL_VAR byref V65 tmp56 fgMorphTree BB13, stmt 16 (before) [000276] ------------ /--* LCL_VAR int V14 tmp5 [000278] -A---------- * ASG int [000277] D------N---- \--* LCL_VAR int V66 tmp57 The assignment [000278] using V66 removes: Constant Assertion: V66 == 0 GenTreeNode creates assertion: [000278] -A---------- * ASG int In BB13 New Local Copy Assertion: V66 == V14 index=#05, mask=0000000000000010 fgMorphTree BB13, stmt 17 (before) [000200] ------------ /--* LCL_VAR struct(P) V11 tmp2 /--* byref V11._pointer (offs=0x00) -> V65 tmp56 /--* int V11._length (offs=0x08) -> V66 tmp57 [000203] -A------R--- * ASG struct (copy) [000201] D----------- \--* LCL_VAR struct(P) V12 tmp3 \--* byref V12._pointer (offs=0x00) -> V67 tmp58 \--* int V12._length (offs=0x08) -> V68 tmp59 fgMorphCopyBlock:block assignment to morph: [000200] -----+------ /--* LCL_VAR struct(P) V11 tmp2 /--* byref V11._pointer (offs=0x00) -> V65 tmp56 /--* int V11._length (offs=0x08) -> V66 tmp57 [000203] -A------R--- * ASG struct (copy) [000201] D----+-N---- \--* LCL_VAR struct(P) V12 tmp3 \--* byref V12._pointer (offs=0x00) -> V67 tmp58 \--* int V12._length (offs=0x08) -> V68 tmp59 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000974] -A---------- * ASG byref In BB13 New Local Copy Assertion: V67 == V65 index=#06, mask=0000000000000020 GenTreeNode creates assertion: [000977] -A---------- * ASG int In BB13 New Local Copy Assertion: V68 == V66 index=#07, mask=0000000000000040 fgMorphCopyBlock (after): [000976] -------N---- /--* LCL_VAR int V66 tmp57 [000977] -A---------- /--* ASG int [000975] D------N---- | \--* LCL_VAR int V68 tmp59 [000978] -A---+------ * COMMA void [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 [000974] -A---------- \--* ASG byref [000972] D------N---- \--* LCL_VAR byref V67 tmp58 fgMorphTree BB13, stmt 17 (after) [000976] -------N---- /--* LCL_VAR int V66 tmp57 [000977] -A---------- /--* ASG int [000975] D------N---- | \--* LCL_VAR int V68 tmp59 [000978] -A---+------ * COMMA void [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 [000974] -A---------- \--* ASG byref [000972] D------N---- \--* LCL_VAR byref V67 tmp58 Morphing BB14 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB15 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB15, stmt 18 (before) [000206] ------------ /--* LCL_VAR struct(P) V12 tmp3 /--* byref V12._pointer (offs=0x00) -> V67 tmp58 /--* int V12._length (offs=0x08) -> V68 tmp59 [000209] -A------R--- * ASG struct (copy) [000208] D----------- \--* LCL_VAR struct(P) V02 loc0 \--* byref V02._pointer (offs=0x00) -> V61 tmp52 \--* int V02._length (offs=0x08) -> V62 tmp53 fgMorphCopyBlock:block assignment to morph: [000206] -----+------ /--* LCL_VAR struct(P) V12 tmp3 /--* byref V12._pointer (offs=0x00) -> V67 tmp58 /--* int V12._length (offs=0x08) -> V68 tmp59 [000209] -A------R--- * ASG struct (copy) [000208] D----+-N---- \--* LCL_VAR struct(P) V02 loc0 \--* byref V02._pointer (offs=0x00) -> V61 tmp52 \--* int V02._length (offs=0x08) -> V62 tmp53 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000981] -A---------- * ASG byref In BB15 New Local Copy Assertion: V61 == V67 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000984] -A---------- * ASG int In BB15 New Local Copy Assertion: V62 == V68 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [000983] -------N---- /--* LCL_VAR int V68 tmp59 [000984] -A---------- /--* ASG int [000982] D------N---- | \--* LCL_VAR int V62 tmp53 [000985] -A---+------ * COMMA void [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 [000981] -A---------- \--* ASG byref [000979] D------N---- \--* LCL_VAR byref V61 tmp52 fgMorphTree BB15, stmt 18 (after) [000983] -------N---- /--* LCL_VAR int V68 tmp59 [000984] -A---------- /--* ASG int [000982] D------N---- | \--* LCL_VAR int V62 tmp53 [000985] -A---+------ * COMMA void [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 [000981] -A---------- \--* ASG byref [000979] D------N---- \--* LCL_VAR byref V61 tmp52 fgMorphTree BB15, stmt 19 (before) [000017] x----------- /--* OBJ(16) struct [000016] L----------- | \--* ADDR byref [000010] ------------ | \--* LCL_VAR struct(P) V02 loc0 | \--* byref V02._pointer (offs=0x00) -> V61 tmp52 | \--* int V02._length (offs=0x08) -> V62 tmp53 [000354] -A------R--- * ASG struct (copy) [000352] D----------- \--* LCL_VAR struct(P) V16 tmp7 \--* byref V16._pointer (offs=0x00) -> V72 tmp63 \--* int V16._length (offs=0x08) -> V73 tmp64 The assignment [000017] using V61 removes: Copy Assertion: V61 == V67 The assignment [000017] using V62 removes: Copy Assertion: V62 == V68 fgMorphCopyBlock:block assignment to morph: [000017] x----+------ /--* OBJ(16) struct [000016] L----+------ | \--* ADDR byref [000010] -----+-N---- | \--* LCL_VAR struct(P) V02 loc0 | \--* byref V02._pointer (offs=0x00) -> V61 tmp52 | \--* int V02._length (offs=0x08) -> V62 tmp53 [000354] -A------R--- * ASG struct (copy) [000352] D----+-N---- \--* LCL_VAR struct(P) V16 tmp7 \--* byref V16._pointer (offs=0x00) -> V72 tmp63 \--* int V16._length (offs=0x08) -> V73 tmp64 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000988] -A---------- * ASG byref In BB15 New Local Copy Assertion: V72 == V61 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000991] -A---------- * ASG int In BB15 New Local Copy Assertion: V73 == V62 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [000990] -------N---- /--* LCL_VAR int V62 tmp53 [000991] -A---------- /--* ASG int [000989] D------N---- | \--* LCL_VAR int V73 tmp64 [000992] -A---+------ * COMMA void [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 [000988] -A---------- \--* ASG byref [000986] D------N---- \--* LCL_VAR byref V72 tmp63 fgMorphTree BB15, stmt 19 (after) [000990] -------N---- /--* LCL_VAR int V62 tmp53 [000991] -A---------- /--* ASG int [000989] D------N---- | \--* LCL_VAR int V73 tmp64 [000992] -A---+------ * COMMA void [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 [000988] -A---------- \--* ASG byref [000986] D------N---- \--* LCL_VAR byref V72 tmp63 fgMorphTree BB15, stmt 20 (before) [000014] x----------- /--* OBJ(16) struct [000013] L----------- | \--* ADDR byref [000011] ------------ | \--* LCL_VAR struct V00 arg0 [000358] -A------R--- * ASG struct (copy) [000356] D----------- \--* LCL_VAR struct(P) V17 tmp8 \--* byref V17._pointer (offs=0x00) -> V74 tmp65 \--* int V17._length (offs=0x08) -> V75 tmp66 Replacing address of implicit by ref struct parameter with byref: [000011] ------------ * LCL_VAR byref V00 arg0 fgMorphCopyBlock:block assignment to morph: [000014] x----+------ /--* OBJ(16) struct [000011] -----+------ | \--* LCL_VAR byref V00 arg0 [000358] -A------R--- * ASG struct (copy) [000356] D----+-N---- \--* LCL_VAR struct(P) V17 tmp8 \--* byref V17._pointer (offs=0x00) -> V74 tmp65 \--* int V17._length (offs=0x08) -> V75 tmp66 (destDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001005] -A---------- * ASG int In BB15 New Local Subrange Assertion: V75 in [-2147483648..2147483647] index=#03, mask=0000000000000004 fgMorphCopyBlock (after): [001004] x----------- /--* IND int [001002] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001003] ------------ | \--* ADD byref [001001] ------------ | \--* LCL_VAR byref V00 arg0 [001005] -A---------- /--* ASG int [001000] D------N---- | \--* LCL_VAR int V75 tmp66 [001006] -A---+------ * COMMA void [000998] x----------- | /--* IND byref [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000997] ------------ | | \--* ADD byref [000995] ------------ | | \--* LCL_VAR byref V00 arg0 [000999] -A---------- \--* ASG byref [000994] D------N---- \--* LCL_VAR byref V74 tmp65 fgMorphTree BB15, stmt 20 (after) [001004] x----------- /--* IND int [001002] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001003] ------------ | \--* ADD byref [001001] ------------ | \--* LCL_VAR byref V00 arg0 [001005] -A---------- /--* ASG int [001000] D------N---- | \--* LCL_VAR int V75 tmp66 [001006] -A---+------ * COMMA void [000998] x----------- | /--* IND byref [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000997] ------------ | | \--* ADD byref [000995] ------------ | | \--* LCL_VAR byref V00 arg0 [000999] -A---------- \--* ASG byref [000994] D------N---- \--* LCL_VAR byref V74 tmp65 fgMorphTree BB15, stmt 21 (before) [000360] ------------ /--* CNS_INT int 0 [000362] -A---------- * ASG bool [000361] D------N---- \--* LCL_VAR bool V19 tmp10 GenTreeNode creates assertion: [000362] -A---------- * ASG bool In BB15 New Local Constant Assertion: V19 == 0 index=#04, mask=0000000000000008 fgMorphTree BB15, stmt 22 (before) [000364] ------------ /--* CNS_INT int 0 [000366] -A---------- * ASG bool [000365] D------N---- \--* LCL_VAR bool V21 tmp12 GenTreeNode creates assertion: [000366] -A---------- * ASG bool In BB15 New Local Constant Assertion: V21 == 0 index=#05, mask=0000000000000010 fgMorphTree BB15, stmt 23 (before) [000368] ------------ /--* CNS_INT int 0 [000370] -A---------- * ASG bool [000369] D------N---- \--* LCL_VAR bool V20 tmp11 GenTreeNode creates assertion: [000370] -A---------- * ASG bool In BB15 New Local Constant Assertion: V20 == 0 index=#06, mask=0000000000000020 Morphing BB19 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB19, stmt 24 (before) [000381] ------------ /--* CNS_INT int 0 [000383] -A---------- * ASG int [000382] D------N---- \--* LCL_VAR int V22 tmp13 GenTreeNode creates assertion: [000383] -A---------- * ASG int In BB19 New Local Constant Assertion: V22 == 0 index=#01, mask=0000000000000001 fgMorphTree BB19, stmt 25 (before) [000376] ------------ /--* LCL_VAR int V73 tmp64 [000378] -A---------- * ASG int [000377] D------N---- \--* LCL_VAR int V22 tmp13 The assignment [000378] using V22 removes: Constant Assertion: V22 == 0 GenTreeNode creates assertion: [000378] -A---------- * ASG int In BB19 New Local Copy Assertion: V22 == V73 index=#01, mask=0000000000000001 fgMorphTree BB19, stmt 26 (before) [000380] ------------ /--* LCL_VAR int V22 tmp13 [000293] -AC--------- * ASG int [000292] D------N---- \--* LCL_VAR int V18 tmp9 Assertion prop in BB19: Copy Assertion: V22 == V73 index=#01, mask=0000000000000001 [000380] ------------ * LCL_VAR int V73 tmp64 GenTreeNode creates assertion: [000293] -A---------- * ASG int In BB19 New Local Copy Assertion: V18 == V73 index=#02, mask=0000000000000002 fgMorphTree BB19, stmt 26 (after) [000380] -----+------ /--* LCL_VAR int V73 tmp64 [000293] -A---+------ * ASG int [000292] D----+-N---- \--* LCL_VAR int V18 tmp9 fgMorphTree BB19, stmt 27 (before) [000394] ------------ /--* CNS_INT int 0 [000396] -A---------- * ASG int [000395] D------N---- \--* LCL_VAR int V23 tmp14 GenTreeNode creates assertion: [000396] -A---------- * ASG int In BB19 New Local Constant Assertion: V23 == 0 index=#03, mask=0000000000000004 fgMorphTree BB19, stmt 28 (before) [000389] ------------ /--* LCL_VAR int V75 tmp66 [000391] -A---------- * ASG int [000390] D------N---- \--* LCL_VAR int V23 tmp14 The assignment [000391] using V23 removes: Constant Assertion: V23 == 0 GenTreeNode creates assertion: [000391] -A---------- * ASG int In BB19 New Local Copy Assertion: V23 == V75 index=#03, mask=0000000000000004 fgMorphTree BB19, stmt 29 (before) [000298] ------------ /--* CNS_INT int 0 [000299] --C--------- /--* EQ int [000393] ------------ | | /--* LCL_VAR int V23 tmp14 [000297] --C--------- | \--* EQ int [000295] ------------ | \--* LCL_VAR int V18 tmp9 [000301] -AC--------- * ASG bool [000300] D------N---- \--* LCL_VAR bool V19 tmp10 Assertion prop in BB19: Copy Assertion: V18 == V73 index=#02, mask=0000000000000002 [000295] ------------ * LCL_VAR int V73 tmp64 Assertion prop in BB19: Copy Assertion: V23 == V75 index=#03, mask=0000000000000004 [000393] ------------ * LCL_VAR int V75 tmp66 GenTreeNode creates assertion: [000301] -A---------- * ASG bool In BB19 New Local Subrange Assertion: V19 in [0..1] index=#04, mask=0000000000000008 fgMorphTree BB19, stmt 29 (after) [000393] -----+------ /--* LCL_VAR int V75 tmp66 [000297] -----+------ /--* NE int [000295] -----+------ | \--* LCL_VAR int V73 tmp64 [000301] -A---+------ * ASG bool [000300] D----+-N---- \--* LCL_VAR int V19 tmp10 fgMorphTree BB19, stmt 30 (before) [000306] ------------ * JTRUE void [000304] ------------ | /--* CNS_INT int 0 [000305] ------------ \--* EQ int [000303] ------------ \--* LCL_VAR int V19 tmp10 Morphing BB20 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB20, stmt 31 (before) [000348] ------------ /--* CNS_INT int 0 [000350] -A---------- * ASG bool [000349] D------N---- \--* LCL_VAR bool V21 tmp12 GenTreeNode creates assertion: [000350] -A---------- * ASG bool In BB20 New Local Constant Assertion: V21 == 0 index=#01, mask=0000000000000001 Morphing BB21 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB21, stmt 32 (before) [000407] ------------ /--* CNS_INT int 0 [000409] -A---------- * ASG int [000408] D------N---- \--* LCL_VAR int V24 tmp15 GenTreeNode creates assertion: [000409] -A---------- * ASG int In BB21 New Local Constant Assertion: V24 == 0 index=#01, mask=0000000000000001 fgMorphTree BB21, stmt 33 (before) [000402] ------------ /--* LCL_VAR int V75 tmp66 [000404] -A---------- * ASG int [000403] D------N---- \--* LCL_VAR int V24 tmp15 The assignment [000404] using V24 removes: Constant Assertion: V24 == 0 GenTreeNode creates assertion: [000404] -A---------- * ASG int In BB21 New Local Copy Assertion: V24 == V75 index=#01, mask=0000000000000001 fgMorphTree BB21, stmt 34 (before) [000314] ------------ /--* CNS_INT int 0 [000315] --C--------- /--* EQ int [000406] ------------ | \--* LCL_VAR int V24 tmp15 [000317] -AC--------- * ASG bool [000316] D------N---- \--* LCL_VAR bool V20 tmp11 Assertion prop in BB21: Copy Assertion: V24 == V75 index=#01, mask=0000000000000001 [000406] ------------ * LCL_VAR int V75 tmp66 GenTreeNode creates assertion: [000317] -A---------- * ASG bool In BB21 New Local Subrange Assertion: V20 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB21, stmt 34 (after) [000314] -----+------ /--* CNS_INT int 0 [000315] -----+------ /--* EQ int [000406] -----+------ | \--* LCL_VAR int V75 tmp66 [000317] -A---+------ * ASG bool [000316] D----+-N---- \--* LCL_VAR int V20 tmp11 fgMorphTree BB21, stmt 35 (before) [000322] ------------ * JTRUE void [000320] ------------ | /--* CNS_INT int 0 [000321] ------------ \--* EQ int [000319] ------------ \--* LCL_VAR int V20 tmp11 Morphing BB22 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB22, stmt 36 (before) [000343] ------------ /--* CNS_INT int 1 [000345] -A---------- * ASG bool [000344] D------N---- \--* LCL_VAR bool V21 tmp12 GenTreeNode creates assertion: [000345] -A---------- * ASG bool In BB22 New Local Constant Assertion: V21 == 1 index=#01, mask=0000000000000001 Morphing BB23 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB23, stmt 37 (before) [000334] ------------ /--* CNS_INT int 0 [000335] --C-G------- /--* EQ int [000327] --C-G------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000332] x----------- arg0 | +--* OBJ(16) struct [000331] L----------- | | \--* ADDR byref [000325] ------------ | | \--* LCL_VAR struct(P) V16 tmp7 | | \--* byref V16._pointer (offs=0x00) -> V72 tmp63 | | \--* int V16._length (offs=0x08) -> V73 tmp64 [000329] x----------- arg1 | \--* OBJ(16) struct [000328] L----------- | \--* ADDR byref [000326] ------------ | \--* LCL_VAR struct(P) V17 tmp8 | \--* byref V17._pointer (offs=0x00) -> V74 tmp65 | \--* int V17._length (offs=0x08) -> V75 tmp66 [000337] -AC-G------- * ASG bool [000336] D------N---- \--* LCL_VAR bool V21 tmp12 lvaGrabTemp returning 97 (V97 tmp88) called for by-value struct argument. New refCnts for V97: refCnt = 1, refCntWtd = 1 fgMorphCopyBlock:block assignment to morph: [000325] -----+-N---- /--* LCL_VAR struct(P) V16 tmp7 /--* byref V16._pointer (offs=0x00) -> V72 tmp63 /--* int V16._length (offs=0x08) -> V73 tmp64 [001013] -A------R--- * ASG struct (copy) [001012] D------N---- \--* LCL_VAR struct V97 tmp88 (srcDoFldAsg=true) using field by field assignments. Local V97 should not be enregistered because: written in a block op lvaGrabTemp returning 98 (V98 tmp89) called for BlockOp address local. Local V97 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001030] -------N---- /--* LCL_VAR int V73 tmp64 [001031] -A---------- /--* ASG int indir assign of V97:ud:0->0 [001029] *------N---- | \--* IND int [001027] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001028] ------------ | \--* ADD byref [001026] ------------ | \--* LCL_VAR byref V98 tmp89 [001032] -A---+------ * COMMA void [001023] -------N---- | /--* LCL_VAR byref V72 tmp63 [001024] -A---------- | /--* ASG byref indir assign of V97:ud:0->0 [001022] *------N---- | | \--* IND byref [001020] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001021] ------------ | | \--* ADD byref [001019] ------------ | | \--* LCL_VAR byref V98 tmp89 [001025] -A---------- \--* COMMA void [001015] L----------- | /--* ADDR byref [001016] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001018] -A---------- \--* ASG byref [001017] D------N---- \--* LCL_VAR byref V98 tmp89 lvaGrabTemp returning 99 (V99 tmp90) called for by-value struct argument. New refCnts for V99: refCnt = 1, refCntWtd = 1 fgMorphCopyBlock:block assignment to morph: [000326] -----+-N---- /--* LCL_VAR struct(P) V17 tmp8 /--* byref V17._pointer (offs=0x00) -> V74 tmp65 /--* int V17._length (offs=0x08) -> V75 tmp66 [001034] -A------R--- * ASG struct (copy) [001033] D------N---- \--* LCL_VAR struct V99 tmp90 (srcDoFldAsg=true) using field by field assignments. Local V99 should not be enregistered because: written in a block op lvaGrabTemp returning 100 (V100 tmp91) called for BlockOp address local. Local V99 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001051] -------N---- /--* LCL_VAR int V75 tmp66 [001052] -A---------- /--* ASG int indir assign of V99:ud:0->0 [001050] *------N---- | \--* IND int [001048] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001049] ------------ | \--* ADD byref [001047] ------------ | \--* LCL_VAR byref V100 tmp91 [001053] -A---+------ * COMMA void [001044] -------N---- | /--* LCL_VAR byref V74 tmp65 [001045] -A---------- | /--* ASG byref indir assign of V99:ud:0->0 [001043] *------N---- | | \--* IND byref [001041] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001042] ------------ | | \--* ADD byref [001040] ------------ | | \--* LCL_VAR byref V100 tmp91 [001046] -A---------- \--* COMMA void [001036] L----------- | /--* ADDR byref [001037] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [001039] -A---------- \--* ASG byref [001038] D------N---- \--* LCL_VAR byref V100 tmp91 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Local V97 should not be enregistered because: it is address exposed Local V99 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 1055.ADDR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V97, isTmp, processed] fgArgTabEntry[arg 1 1058.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V99, isTmp, processed] GenTreeNode creates assertion: [000337] -ACXG------- * ASG bool In BB23 New Local Subrange Assertion: V21 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB23, stmt 37 (after) [000334] -----+------ /--* CNS_INT int 0 [000335] -ACXG+------ /--* EQ int [000327] -ACXG+------ | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001030] -------N---- | | /--* LCL_VAR int V73 tmp64 [001031] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 [001029] *------N---- | | | \--* IND int [001027] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001028] ------------ | | | \--* ADD byref [001026] ------------ | | | \--* LCL_VAR byref V98 tmp89 [001032] -A---+----L- arg0 SETUP | +--* COMMA void [001023] -------N---- | | | /--* LCL_VAR byref V72 tmp63 [001024] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 [001022] *------N---- | | | | \--* IND byref [001020] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001021] ------------ | | | | \--* ADD byref [001019] ------------ | | | | \--* LCL_VAR byref V98 tmp89 [001025] -A---------- | | \--* COMMA void [001015] L----------- | | | /--* ADDR byref [001016] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001018] -A---------- | | \--* ASG byref [001017] D------N---- | | \--* LCL_VAR byref V98 tmp89 [001051] -------N---- | | /--* LCL_VAR int V75 tmp66 [001052] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 [001050] *------N---- | | | \--* IND int [001048] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001049] ------------ | | | \--* ADD byref [001047] ------------ | | | \--* LCL_VAR byref V100 tmp91 [001053] -A---+----L- arg1 SETUP | +--* COMMA void [001044] -------N---- | | | /--* LCL_VAR byref V74 tmp65 [001045] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 [001043] *------N---- | | | | \--* IND byref [001041] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001042] ------------ | | | | \--* ADD byref [001040] ------------ | | | | \--* LCL_VAR byref V100 tmp91 [001046] -A---------- | | \--* COMMA void [001036] L----------- | | | /--* ADDR byref [001037] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001039] -A---------- | | \--* ASG byref [001038] D------N---- | | \--* LCL_VAR byref V100 tmp91 [001055] L----------- arg0 in rcx | +--* ADDR byref [001054] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001058] L----------- arg1 in rdx | \--* ADDR byref [001057] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 [000337] -ACXG+------ * ASG bool [000336] D----+-N---- \--* LCL_VAR int V21 tmp12 Morphing BB24 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB25 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB25, stmt 38 (before) [000021] --C--------- /--* CAST int <- bool <- int [000341] ------------ | \--* CAST int <- bool <- int [000340] ------------ | \--* LCL_VAR int V21 tmp12 [000023] -AC--------- * ASG int [000022] D------N---- \--* LCL_VAR int V04 loc2 GenTreeNode creates assertion: [000023] -A---------- * ASG int In BB25 New Local Copy Assertion: V04 == V21 index=#01, mask=0000000000000001 fgMorphTree BB25, stmt 38 (after) [000340] -----+------ /--* LCL_VAR int V21 tmp12 [000023] -A---+------ * ASG int [000022] D----+-N---- \--* LCL_VAR int V04 loc2 fgMorphTree BB25, stmt 39 (before) [000028] ------------ * JTRUE void [000026] ------------ | /--* CNS_INT int 0 [000027] ------------ \--* EQ int [000025] ------------ \--* LCL_VAR int V04 loc2 Assertion prop in BB25: Copy Assertion: V04 == V21 index=#01, mask=0000000000000001 [000025] ------------ * LCL_VAR int V21 tmp12 fgMorphTree BB25, stmt 39 (after) [000028] -----+------ * JTRUE void [000026] -----+------ | /--* CNS_INT int 0 [000027] J----+-N---- \--* EQ int [000025] -----+------ \--* LCL_VAR int V21 tmp12 Morphing BB02 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB02, stmt 40 (before) [000157] ------------ /--* CNS_INT int 1 [000159] -A-XG------- * ASG byte [000158] *------N---- \--* IND byte [000156] ------------ \--* LCL_VAR byref V01 arg1 fgMorphTree BB02, stmt 41 (before) [000161] ------------ /--* CNS_INT int 1 [000163] -A---------- * ASG int [000162] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000163] -A---------- * ASG int In BB02 New Local Constant Assertion: V05 == 1 index=#01, mask=0000000000000001 Morphing BB03 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB03, stmt 42 (before) [000468] ------------ /--* CNS_INT int 0 [000470] -A---------- * ASG bool [000469] D------N---- \--* LCL_VAR bool V25 tmp16 GenTreeNode creates assertion: [000470] -A---------- * ASG bool In BB03 New Local Constant Assertion: V25 == 0 index=#01, mask=0000000000000001 Morphing BB29 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB29, stmt 43 (before) [000414] ------------ /--* CNS_INT ref null [000415] ------------ /--* EQ int [000413] ------------ | \--* CNS_STR ref [000417] -A---------- * ASG bool [000416] D------N---- \--* LCL_VAR bool V25 tmp16 GenTreeNode creates assertion: [000417] -A---------- * ASG bool In BB29 New Local Subrange Assertion: V25 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB29, stmt 43 (after) [000414] -----+------ /--* CNS_INT ref null [000415] -----+------ /--* EQ int [001063] -----+------ | \--* NOP ref [001062] -----+------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000417] -A---+------ * ASG bool [000416] D----+-N---- \--* LCL_VAR int V25 tmp16 fgMorphTree BB29, stmt 44 (before) [000422] ------------ * JTRUE void [000420] ------------ | /--* CNS_INT int 0 [000421] ------------ \--* EQ int [000419] ------------ \--* LCL_VAR int V25 tmp16 Morphing BB30 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB30, stmt 45 (before) [000460] ------------ /--* CNS_INT int 0 [000461] IA------R--- * ASG struct (init) [000458] D------N---- \--* LCL_VAR struct(P) V29 tmp20 \--* byref V29._pointer (offs=0x00) -> V80 tmp71 \--* int V29._length (offs=0x08) -> V81 tmp72 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [001066] -A---------- * ASG byref In BB30 New Local Constant Assertion: V80 == 0 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [001069] -A---------- * ASG int In BB30 New Local Constant Assertion: V81 == 0 index=#02, mask=0000000000000002 fgMorphInitBlock (after): [001068] ------------ /--* CNS_INT int 0 [001069] -A---------- /--* ASG int [001067] D------N---- | \--* LCL_VAR int V81 tmp72 [001070] -A---+------ * COMMA void [001065] ------------ | /--* CNS_INT byref 0 [001066] -A---------- \--* ASG byref [001064] D------N---- \--* LCL_VAR byref V80 tmp71 fgMorphTree BB30, stmt 45 (after) [001068] ------------ /--* CNS_INT int 0 [001069] -A---------- /--* ASG int [001067] D------N---- | \--* LCL_VAR int V81 tmp72 [001070] -A---+------ * COMMA void [001065] ------------ | /--* CNS_INT byref 0 [001066] -A---------- \--* ASG byref [001064] D------N---- \--* LCL_VAR byref V80 tmp71 fgMorphTree BB30, stmt 46 (before) [000463] ------------ /--* LCL_VAR struct(P) V29 tmp20 /--* byref V29._pointer (offs=0x00) -> V80 tmp71 /--* int V29._length (offs=0x08) -> V81 tmp72 [000466] -A------R--- * ASG struct (copy) [000464] D----------- \--* LCL_VAR struct(P) V28 tmp19 \--* byref V28._pointer (offs=0x00) -> V78 tmp69 \--* int V28._length (offs=0x08) -> V79 tmp70 fgMorphCopyBlock:block assignment to morph: [000463] -----+------ /--* LCL_VAR struct(P) V29 tmp20 /--* byref V29._pointer (offs=0x00) -> V80 tmp71 /--* int V29._length (offs=0x08) -> V81 tmp72 [000466] -A------R--- * ASG struct (copy) [000464] D----+-N---- \--* LCL_VAR struct(P) V28 tmp19 \--* byref V28._pointer (offs=0x00) -> V78 tmp69 \--* int V28._length (offs=0x08) -> V79 tmp70 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001073] -A---------- * ASG byref In BB30 New Local Copy Assertion: V78 == V80 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [001076] -A---------- * ASG int In BB30 New Local Copy Assertion: V79 == V81 index=#04, mask=0000000000000008 fgMorphCopyBlock (after): [001075] -------N---- /--* LCL_VAR int V81 tmp72 [001076] -A---------- /--* ASG int [001074] D------N---- | \--* LCL_VAR int V79 tmp70 [001077] -A---+------ * COMMA void [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 [001073] -A---------- \--* ASG byref [001071] D------N---- \--* LCL_VAR byref V78 tmp69 fgMorphTree BB30, stmt 46 (after) [001075] -------N---- /--* LCL_VAR int V81 tmp72 [001076] -A---------- /--* ASG int [001074] D------N---- | \--* LCL_VAR int V79 tmp70 [001077] -A---+------ * COMMA void [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 [001073] -A---------- \--* ASG byref [001071] D------N---- \--* LCL_VAR byref V78 tmp69 Morphing BB31 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB31, stmt 47 (before) [000478] ---X-------- * IND int [000477] ------------ \--* CNS_STR ref fgMorphTree BB31, stmt 47 (after) [000478] x----+------ * IND int [001079] -----+------ \--* NOP ref [001078] -----+------ \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] Removing statement [000479] in BB31 as useless: [000479] ------------ * STMT void (IL 0x01F... ???) [000478] x----+------ \--* IND int [001079] -----+------ \--* NOP ref [001078] -----+------ \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] fgMorphTree BB31, stmt 48 (before) [000476] ---XG------- /--* ADDR byref [000475] ---XG------- | \--* FIELD ushort _firstChar [000474] ------------ | \--* CNS_STR ref [000433] -AC--------- * ASG byref [000432] D------N---- \--* LCL_VAR byref V26 tmp17 Before explicit null check morphing: [000475] ---XG--N---- * FIELD ushort _firstChar [000474] ------------ \--* CNS_STR ref After adding explicit null check: [000475] ---XG--N---- * IND ushort [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [001087] ------------ | /--* ADD byref [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 [001088] -A-X-------- \--* COMMA byref [001083] ---X---N---- | /--* NULLCHECK byte [001082] ------------ | | \--* LCL_VAR ref V96 tmp87 [001084] -A-X-------- \--* COMMA void [000474] ------------ | /--* CNS_STR ref [001081] -A---------- \--* ASG ref [001080] D------N---- \--* LCL_VAR ref V96 tmp87 GenTreeNode creates assertion: [001083] ---X---N---- * NULLCHECK byte In BB31 New Local Constant Assertion: V96 != null index=#01, mask=0000000000000001 fgMorphTree BB31, stmt 48 (after) [001086] -----+------ /--* CNS_INT long 12 field offset Fseq[_firstChar] [001087] -----+------ /--* ADD byref [001085] -----+------ | \--* LCL_VAR ref V96 tmp87 [001088] -A-XG+-N---- /--* COMMA byref [001083] ---X-+-N---- | | /--* NULLCHECK byte [001082] -----+------ | | | \--* LCL_VAR ref V96 tmp87 [001091] -A-X-------- | \--* COMMA void [001090] -----+------ | | /--* NOP ref [001089] -----+------ | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [001081] -A---+------ | \--* ASG ref [001080] D----+-N---- | \--* LCL_VAR ref V96 tmp87 [000433] -A-XG+------ * ASG byref [000432] D----+-N---- \--* LCL_VAR byref V26 tmp17 fgMorphTree BB31, stmt 49 (before) [000489] ---X-------- * IND int [000488] ------------ \--* CNS_STR ref fgMorphTree BB31, stmt 49 (after) [000489] x----+------ * IND int [001094] -----+------ \--* NOP ref [001093] -----+------ \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] Removing statement [000490] in BB31 as useless: [000490] ------------ * STMT void (IL 0x01F... ???) [000489] x----+------ \--* IND int [001094] -----+------ \--* NOP ref [001093] -----+------ \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] fgMorphTree BB31, stmt 50 (before) [000491] ------------ /--* CNS_INT int 0 [000493] -A---------- * ASG int [000492] D------N---- \--* LCL_VAR int V30 tmp21 GenTreeNode creates assertion: [000493] -A---------- * ASG int In BB31 New Local Constant Assertion: V30 == 0 index=#02, mask=0000000000000002 fgMorphTree BB31, stmt 51 (before) [000483] ---XG------- /--* FIELD int _stringLength [000482] ------------ | \--* CNS_STR ref [000485] -A-XG------- * ASG int [000484] D------N---- \--* LCL_VAR int V30 tmp21 The assignment [000485] using V30 removes: Constant Assertion: V30 == 0 GenTreeNode creates assertion: [000485] -A--G------- * ASG int In BB31 New Local Subrange Assertion: V30 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB31, stmt 51 (after) [000483] x---G+------ /--* IND int [001095] -----+------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [001096] -----+------ | \--* ADD byref [001098] -----+------ | \--* NOP ref [001097] -----+------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000485] -A--G+------ * ASG int [000484] D----+-N---- \--* LCL_VAR int V30 tmp21 fgMorphTree BB31, stmt 52 (before) [000438] ------------ /--* CNS_INT int 0 [000439] IA------R--- * ASG struct (init) [000437] D------N---- \--* LCL_VAR struct(P) V27 tmp18 \--* byref V27._pointer (offs=0x00) -> V76 tmp67 \--* int V27._length (offs=0x08) -> V77 tmp68 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [001101] -A---------- * ASG byref In BB31 New Local Constant Assertion: V76 == 0 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [001104] -A---------- * ASG int In BB31 New Local Constant Assertion: V77 == 0 index=#04, mask=0000000000000008 fgMorphInitBlock (after): [001103] ------------ /--* CNS_INT int 0 [001104] -A---------- /--* ASG int [001102] D------N---- | \--* LCL_VAR int V77 tmp68 [001105] -A---+------ * COMMA void [001100] ------------ | /--* CNS_INT byref 0 [001101] -A---------- \--* ASG byref [001099] D------N---- \--* LCL_VAR byref V76 tmp67 fgMorphTree BB31, stmt 52 (after) [001103] ------------ /--* CNS_INT int 0 [001104] -A---------- /--* ASG int [001102] D------N---- | \--* LCL_VAR int V77 tmp68 [001105] -A---+------ * COMMA void [001100] ------------ | /--* CNS_INT byref 0 [001101] -A---------- \--* ASG byref [001099] D------N---- \--* LCL_VAR byref V76 tmp67 fgMorphTree BB31, stmt 53 (before) [000501] --C-G------- * CALL void System.Diagnostics.Debug.Assert [000499] ------------ | /--* CNS_INT int 0 [000500] ------------ arg0 \--* EQ int [000497] ------------ | /--* CNS_INT int 0 [000498] ------------ \--* LT int [000487] ------------ \--* LCL_VAR int V30 tmp21 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000497] -----+------ /--* CNS_INT int 0 [000498] -----+------ * GE int [000487] -----+------ \--* LCL_VAR int V30 tmp21 Replaced with placeholder node: [001106] ----------L- * ARGPLACE int Shuffled argument table: rcx fgArgTabEntry[arg 0 498.GE, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB31, stmt 53 (after) [000501] --CXG+------ * CALL void System.Diagnostics.Debug.Assert [000497] -----+------ | /--* CNS_INT int 0 [000498] -----+------ arg0 in rcx \--* GE int [000487] -----+------ \--* LCL_VAR int V30 tmp21 fgMorphTree BB31, stmt 54 (before) [000507] ------------ /--* CNS_INT int 0 [000508] IA------R--- * ASG struct (init) [000506] D------N---- \--* LCL_VAR struct(P) V31 tmp22 \--* byref V31._value (offs=0x00) -> V82 tmp73 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [001110] -A---------- * ASG byref In BB31 New Local Constant Assertion: V82 == 0 index=#05, mask=0000000000000010 fgMorphInitBlock (after): [001109] ------------ /--* CNS_INT byref 0 [001110] -A---+------ * ASG byref [001108] D------N---- \--* LCL_VAR byref V82 tmp73 The assignment [001110] using V82 removes: Constant Assertion: V82 == 0 GenTreeNode creates assertion: [001110] -A---+------ * ASG byref In BB31 New Local Constant Assertion: V82 == 0 index=#05, mask=0000000000000010 fgMorphTree BB31, stmt 54 (after) [001109] ------------ /--* CNS_INT byref 0 [001110] -A---+------ * ASG byref [001108] D------N---- \--* LCL_VAR byref V82 tmp73 fgMorphTree BB31, stmt 55 (before) [000435] ------------ /--* LCL_VAR byref V26 tmp17 [000513] -A---------- * ASG byref [000512] D------N---- \--* LCL_VAR byref V82 tmp73 The assignment [000513] using V82 removes: Constant Assertion: V82 == 0 GenTreeNode creates assertion: [000513] -A---------- * ASG byref In BB31 New Local Copy Assertion: V82 == V26 index=#05, mask=0000000000000010 fgMorphTree BB31, stmt 56 (before) [000514] ------------ /--* LCL_VAR struct(P) V31 tmp22 /--* byref V31._value (offs=0x00) -> V82 tmp73 [000519] -A------R--- * ASG struct (copy) [000518] ------------ \--* OBJ(8) struct [000517] ------------ \--* ADDR byref [000516] ------------ \--* LCL_VAR byref V76 tmp67 The assignment [000518] using V76 removes: Constant Assertion: V76 == 0 fgMorphCopyBlock:block assignment to morph: [000514] -----+------ /--* LCL_VAR struct(P) V31 tmp22 /--* byref V31._value (offs=0x00) -> V82 tmp73 [000519] -A------R--- * ASG struct (copy) [000518] x----+------ \--* OBJ(8) struct [000517] -----+------ \--* ADDR byref [000516] D----+-N---- \--* LCL_VAR byref V76 tmp67 (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001113] -A---------- * ASG byref In BB31 New Local Copy Assertion: V76 == V82 index=#05, mask=0000000000000010 fgMorphCopyBlock (after): [001112] -------N---- /--* LCL_VAR byref V82 tmp73 [001113] -A---+------ * ASG byref [001111] D------N---- \--* LCL_VAR byref V76 tmp67 The assignment [001113] using V76 removes: Copy Assertion: V76 == V82 GenTreeNode creates assertion: [001113] -A---+------ * ASG byref In BB31 New Local Copy Assertion: V76 == V82 index=#05, mask=0000000000000010 fgMorphTree BB31, stmt 56 (after) [001112] -------N---- /--* LCL_VAR byref V82 tmp73 [001113] -A---+------ * ASG byref [001111] D------N---- \--* LCL_VAR byref V76 tmp67 fgMorphTree BB31, stmt 57 (before) [000523] ------------ /--* LCL_VAR int V30 tmp21 [000525] -A---------- * ASG int [000524] D------N---- \--* LCL_VAR int V77 tmp68 The assignment [000525] using V77 removes: Constant Assertion: V77 == 0 GenTreeNode creates assertion: [000525] -A---------- * ASG int In BB31 New Local Copy Assertion: V77 == V30 index=#05, mask=0000000000000010 fgMorphTree BB31, stmt 58 (before) [000447] ------------ /--* LCL_VAR struct(P) V27 tmp18 /--* byref V27._pointer (offs=0x00) -> V76 tmp67 /--* int V27._length (offs=0x08) -> V77 tmp68 [000450] -A------R--- * ASG struct (copy) [000448] D----------- \--* LCL_VAR struct(P) V28 tmp19 \--* byref V28._pointer (offs=0x00) -> V78 tmp69 \--* int V28._length (offs=0x08) -> V79 tmp70 fgMorphCopyBlock:block assignment to morph: [000447] -----+------ /--* LCL_VAR struct(P) V27 tmp18 /--* byref V27._pointer (offs=0x00) -> V76 tmp67 /--* int V27._length (offs=0x08) -> V77 tmp68 [000450] -A------R--- * ASG struct (copy) [000448] D----+-N---- \--* LCL_VAR struct(P) V28 tmp19 \--* byref V28._pointer (offs=0x00) -> V78 tmp69 \--* int V28._length (offs=0x08) -> V79 tmp70 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001116] -A---------- * ASG byref In BB31 New Local Copy Assertion: V78 == V76 index=#06, mask=0000000000000020 GenTreeNode creates assertion: [001119] -A---------- * ASG int In BB31 New Local Copy Assertion: V79 == V77 index=#07, mask=0000000000000040 fgMorphCopyBlock (after): [001118] -------N---- /--* LCL_VAR int V77 tmp68 [001119] -A---------- /--* ASG int [001117] D------N---- | \--* LCL_VAR int V79 tmp70 [001120] -A---+------ * COMMA void [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 [001116] -A---------- \--* ASG byref [001114] D------N---- \--* LCL_VAR byref V78 tmp69 fgMorphTree BB31, stmt 58 (after) [001118] -------N---- /--* LCL_VAR int V77 tmp68 [001119] -A---------- /--* ASG int [001117] D------N---- | \--* LCL_VAR int V79 tmp70 [001120] -A---+------ * COMMA void [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 [001116] -A---------- \--* ASG byref [001114] D------N---- \--* LCL_VAR byref V78 tmp69 Morphing BB32 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB33 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB33, stmt 59 (before) [000453] ------------ /--* LCL_VAR struct(P) V28 tmp19 /--* byref V28._pointer (offs=0x00) -> V78 tmp69 /--* int V28._length (offs=0x08) -> V79 tmp70 [000456] -A------R--- * ASG struct (copy) [000455] D----------- \--* LCL_VAR struct(P) V03 loc1 \--* byref V03._pointer (offs=0x00) -> V63 tmp54 \--* int V03._length (offs=0x08) -> V64 tmp55 fgMorphCopyBlock:block assignment to morph: [000453] -----+------ /--* LCL_VAR struct(P) V28 tmp19 /--* byref V28._pointer (offs=0x00) -> V78 tmp69 /--* int V28._length (offs=0x08) -> V79 tmp70 [000456] -A------R--- * ASG struct (copy) [000455] D----+-N---- \--* LCL_VAR struct(P) V03 loc1 \--* byref V03._pointer (offs=0x00) -> V63 tmp54 \--* int V03._length (offs=0x08) -> V64 tmp55 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001123] -A---------- * ASG byref In BB33 New Local Copy Assertion: V63 == V78 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [001126] -A---------- * ASG int In BB33 New Local Copy Assertion: V64 == V79 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [001125] -------N---- /--* LCL_VAR int V79 tmp70 [001126] -A---------- /--* ASG int [001124] D------N---- | \--* LCL_VAR int V64 tmp55 [001127] -A---+------ * COMMA void [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 [001123] -A---------- \--* ASG byref [001121] D------N---- \--* LCL_VAR byref V63 tmp54 fgMorphTree BB33, stmt 59 (after) [001125] -------N---- /--* LCL_VAR int V79 tmp70 [001126] -A---------- /--* ASG int [001124] D------N---- | \--* LCL_VAR int V64 tmp55 [001127] -A---+------ * COMMA void [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 [001123] -A---------- \--* ASG byref [001121] D------N---- \--* LCL_VAR byref V63 tmp54 fgMorphTree BB33, stmt 60 (before) [000047] x----------- /--* OBJ(16) struct [000046] L----------- | \--* ADDR byref [000040] ------------ | \--* LCL_VAR struct(P) V03 loc1 | \--* byref V03._pointer (offs=0x00) -> V63 tmp54 | \--* int V03._length (offs=0x08) -> V64 tmp55 [000601] -A------R--- * ASG struct (copy) [000599] D----------- \--* LCL_VAR struct(P) V32 tmp23 \--* byref V32._pointer (offs=0x00) -> V83 tmp74 \--* int V32._length (offs=0x08) -> V84 tmp75 The assignment [000047] using V63 removes: Copy Assertion: V63 == V78 The assignment [000047] using V64 removes: Copy Assertion: V64 == V79 fgMorphCopyBlock:block assignment to morph: [000047] x----+------ /--* OBJ(16) struct [000046] L----+------ | \--* ADDR byref [000040] -----+-N---- | \--* LCL_VAR struct(P) V03 loc1 | \--* byref V03._pointer (offs=0x00) -> V63 tmp54 | \--* int V03._length (offs=0x08) -> V64 tmp55 [000601] -A------R--- * ASG struct (copy) [000599] D----+-N---- \--* LCL_VAR struct(P) V32 tmp23 \--* byref V32._pointer (offs=0x00) -> V83 tmp74 \--* int V32._length (offs=0x08) -> V84 tmp75 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001130] -A---------- * ASG byref In BB33 New Local Copy Assertion: V83 == V63 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [001133] -A---------- * ASG int In BB33 New Local Copy Assertion: V84 == V64 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [001132] -------N---- /--* LCL_VAR int V64 tmp55 [001133] -A---------- /--* ASG int [001131] D------N---- | \--* LCL_VAR int V84 tmp75 [001134] -A---+------ * COMMA void [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 [001130] -A---------- \--* ASG byref [001128] D------N---- \--* LCL_VAR byref V83 tmp74 fgMorphTree BB33, stmt 60 (after) [001132] -------N---- /--* LCL_VAR int V64 tmp55 [001133] -A---------- /--* ASG int [001131] D------N---- | \--* LCL_VAR int V84 tmp75 [001134] -A---+------ * COMMA void [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 [001130] -A---------- \--* ASG byref [001128] D------N---- \--* LCL_VAR byref V83 tmp74 fgMorphTree BB33, stmt 61 (before) [000044] x----------- /--* OBJ(16) struct [000043] L----------- | \--* ADDR byref [000041] ------------ | \--* LCL_VAR struct V00 arg0 [000605] -A------R--- * ASG struct (copy) [000603] D----------- \--* LCL_VAR struct(P) V33 tmp24 \--* byref V33._pointer (offs=0x00) -> V85 tmp76 \--* int V33._length (offs=0x08) -> V86 tmp77 Replacing address of implicit by ref struct parameter with byref: [000041] ------------ * LCL_VAR byref V00 arg0 fgMorphCopyBlock:block assignment to morph: [000044] x----+------ /--* OBJ(16) struct [000041] -----+------ | \--* LCL_VAR byref V00 arg0 [000605] -A------R--- * ASG struct (copy) [000603] D----+-N---- \--* LCL_VAR struct(P) V33 tmp24 \--* byref V33._pointer (offs=0x00) -> V85 tmp76 \--* int V33._length (offs=0x08) -> V86 tmp77 (destDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001147] -A---------- * ASG int In BB33 New Local Subrange Assertion: V86 in [-2147483648..2147483647] index=#03, mask=0000000000000004 fgMorphCopyBlock (after): [001146] x----------- /--* IND int [001144] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001145] ------------ | \--* ADD byref [001143] ------------ | \--* LCL_VAR byref V00 arg0 [001147] -A---------- /--* ASG int [001142] D------N---- | \--* LCL_VAR int V86 tmp77 [001148] -A---+------ * COMMA void [001140] x----------- | /--* IND byref [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001139] ------------ | | \--* ADD byref [001137] ------------ | | \--* LCL_VAR byref V00 arg0 [001141] -A---------- \--* ASG byref [001136] D------N---- \--* LCL_VAR byref V85 tmp76 fgMorphTree BB33, stmt 61 (after) [001146] x----------- /--* IND int [001144] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001145] ------------ | \--* ADD byref [001143] ------------ | \--* LCL_VAR byref V00 arg0 [001147] -A---------- /--* ASG int [001142] D------N---- | \--* LCL_VAR int V86 tmp77 [001148] -A---+------ * COMMA void [001140] x----------- | /--* IND byref [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001139] ------------ | | \--* ADD byref [001137] ------------ | | \--* LCL_VAR byref V00 arg0 [001141] -A---------- \--* ASG byref [001136] D------N---- \--* LCL_VAR byref V85 tmp76 fgMorphTree BB33, stmt 62 (before) [000607] ------------ /--* CNS_INT int 0 [000609] -A---------- * ASG bool [000608] D------N---- \--* LCL_VAR bool V35 tmp26 GenTreeNode creates assertion: [000609] -A---------- * ASG bool In BB33 New Local Constant Assertion: V35 == 0 index=#04, mask=0000000000000008 fgMorphTree BB33, stmt 63 (before) [000611] ------------ /--* CNS_INT int 0 [000613] -A---------- * ASG bool [000612] D------N---- \--* LCL_VAR bool V37 tmp28 GenTreeNode creates assertion: [000613] -A---------- * ASG bool In BB33 New Local Constant Assertion: V37 == 0 index=#05, mask=0000000000000010 fgMorphTree BB33, stmt 64 (before) [000615] ------------ /--* CNS_INT int 0 [000617] -A---------- * ASG bool [000616] D------N---- \--* LCL_VAR bool V36 tmp27 GenTreeNode creates assertion: [000617] -A---------- * ASG bool In BB33 New Local Constant Assertion: V36 == 0 index=#06, mask=0000000000000020 Morphing BB37 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB37, stmt 65 (before) [000628] ------------ /--* CNS_INT int 0 [000630] -A---------- * ASG int [000629] D------N---- \--* LCL_VAR int V38 tmp29 GenTreeNode creates assertion: [000630] -A---------- * ASG int In BB37 New Local Constant Assertion: V38 == 0 index=#01, mask=0000000000000001 fgMorphTree BB37, stmt 66 (before) [000623] ------------ /--* LCL_VAR int V84 tmp75 [000625] -A---------- * ASG int [000624] D------N---- \--* LCL_VAR int V38 tmp29 The assignment [000625] using V38 removes: Constant Assertion: V38 == 0 GenTreeNode creates assertion: [000625] -A---------- * ASG int In BB37 New Local Copy Assertion: V38 == V84 index=#01, mask=0000000000000001 fgMorphTree BB37, stmt 67 (before) [000627] ------------ /--* LCL_VAR int V38 tmp29 [000540] -AC--------- * ASG int [000539] D------N---- \--* LCL_VAR int V34 tmp25 Assertion prop in BB37: Copy Assertion: V38 == V84 index=#01, mask=0000000000000001 [000627] ------------ * LCL_VAR int V84 tmp75 GenTreeNode creates assertion: [000540] -A---------- * ASG int In BB37 New Local Copy Assertion: V34 == V84 index=#02, mask=0000000000000002 fgMorphTree BB37, stmt 67 (after) [000627] -----+------ /--* LCL_VAR int V84 tmp75 [000540] -A---+------ * ASG int [000539] D----+-N---- \--* LCL_VAR int V34 tmp25 fgMorphTree BB37, stmt 68 (before) [000641] ------------ /--* CNS_INT int 0 [000643] -A---------- * ASG int [000642] D------N---- \--* LCL_VAR int V39 tmp30 GenTreeNode creates assertion: [000643] -A---------- * ASG int In BB37 New Local Constant Assertion: V39 == 0 index=#03, mask=0000000000000004 fgMorphTree BB37, stmt 69 (before) [000636] ------------ /--* LCL_VAR int V86 tmp77 [000638] -A---------- * ASG int [000637] D------N---- \--* LCL_VAR int V39 tmp30 The assignment [000638] using V39 removes: Constant Assertion: V39 == 0 GenTreeNode creates assertion: [000638] -A---------- * ASG int In BB37 New Local Copy Assertion: V39 == V86 index=#03, mask=0000000000000004 fgMorphTree BB37, stmt 70 (before) [000545] ------------ /--* CNS_INT int 0 [000546] --C--------- /--* EQ int [000640] ------------ | | /--* LCL_VAR int V39 tmp30 [000544] --C--------- | \--* EQ int [000542] ------------ | \--* LCL_VAR int V34 tmp25 [000548] -AC--------- * ASG bool [000547] D------N---- \--* LCL_VAR bool V35 tmp26 Assertion prop in BB37: Copy Assertion: V34 == V84 index=#02, mask=0000000000000002 [000542] ------------ * LCL_VAR int V84 tmp75 Assertion prop in BB37: Copy Assertion: V39 == V86 index=#03, mask=0000000000000004 [000640] ------------ * LCL_VAR int V86 tmp77 GenTreeNode creates assertion: [000548] -A---------- * ASG bool In BB37 New Local Subrange Assertion: V35 in [0..1] index=#04, mask=0000000000000008 fgMorphTree BB37, stmt 70 (after) [000640] -----+------ /--* LCL_VAR int V86 tmp77 [000544] -----+------ /--* NE int [000542] -----+------ | \--* LCL_VAR int V84 tmp75 [000548] -A---+------ * ASG bool [000547] D----+-N---- \--* LCL_VAR int V35 tmp26 fgMorphTree BB37, stmt 71 (before) [000553] ------------ * JTRUE void [000551] ------------ | /--* CNS_INT int 0 [000552] ------------ \--* EQ int [000550] ------------ \--* LCL_VAR int V35 tmp26 Morphing BB38 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB38, stmt 72 (before) [000595] ------------ /--* CNS_INT int 0 [000597] -A---------- * ASG bool [000596] D------N---- \--* LCL_VAR bool V37 tmp28 GenTreeNode creates assertion: [000597] -A---------- * ASG bool In BB38 New Local Constant Assertion: V37 == 0 index=#01, mask=0000000000000001 Morphing BB39 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB39, stmt 73 (before) [000654] ------------ /--* CNS_INT int 0 [000656] -A---------- * ASG int [000655] D------N---- \--* LCL_VAR int V40 tmp31 GenTreeNode creates assertion: [000656] -A---------- * ASG int In BB39 New Local Constant Assertion: V40 == 0 index=#01, mask=0000000000000001 fgMorphTree BB39, stmt 74 (before) [000649] ------------ /--* LCL_VAR int V86 tmp77 [000651] -A---------- * ASG int [000650] D------N---- \--* LCL_VAR int V40 tmp31 The assignment [000651] using V40 removes: Constant Assertion: V40 == 0 GenTreeNode creates assertion: [000651] -A---------- * ASG int In BB39 New Local Copy Assertion: V40 == V86 index=#01, mask=0000000000000001 fgMorphTree BB39, stmt 75 (before) [000561] ------------ /--* CNS_INT int 0 [000562] --C--------- /--* EQ int [000653] ------------ | \--* LCL_VAR int V40 tmp31 [000564] -AC--------- * ASG bool [000563] D------N---- \--* LCL_VAR bool V36 tmp27 Assertion prop in BB39: Copy Assertion: V40 == V86 index=#01, mask=0000000000000001 [000653] ------------ * LCL_VAR int V86 tmp77 GenTreeNode creates assertion: [000564] -A---------- * ASG bool In BB39 New Local Subrange Assertion: V36 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB39, stmt 75 (after) [000561] -----+------ /--* CNS_INT int 0 [000562] -----+------ /--* EQ int [000653] -----+------ | \--* LCL_VAR int V86 tmp77 [000564] -A---+------ * ASG bool [000563] D----+-N---- \--* LCL_VAR int V36 tmp27 fgMorphTree BB39, stmt 76 (before) [000569] ------------ * JTRUE void [000567] ------------ | /--* CNS_INT int 0 [000568] ------------ \--* EQ int [000566] ------------ \--* LCL_VAR int V36 tmp27 Morphing BB40 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB40, stmt 77 (before) [000590] ------------ /--* CNS_INT int 1 [000592] -A---------- * ASG bool [000591] D------N---- \--* LCL_VAR bool V37 tmp28 GenTreeNode creates assertion: [000592] -A---------- * ASG bool In BB40 New Local Constant Assertion: V37 == 1 index=#01, mask=0000000000000001 Morphing BB41 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB41, stmt 78 (before) [000581] ------------ /--* CNS_INT int 0 [000582] --C-G------- /--* EQ int [000574] --C-G------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000579] x----------- arg0 | +--* OBJ(16) struct [000578] L----------- | | \--* ADDR byref [000572] ------------ | | \--* LCL_VAR struct(P) V32 tmp23 | | \--* byref V32._pointer (offs=0x00) -> V83 tmp74 | | \--* int V32._length (offs=0x08) -> V84 tmp75 [000576] x----------- arg1 | \--* OBJ(16) struct [000575] L----------- | \--* ADDR byref [000573] ------------ | \--* LCL_VAR struct(P) V33 tmp24 | \--* byref V33._pointer (offs=0x00) -> V85 tmp76 | \--* int V33._length (offs=0x08) -> V86 tmp77 [000584] -AC-G------- * ASG bool [000583] D------N---- \--* LCL_VAR bool V37 tmp28 reusing outgoing struct argNew refCnts for V97: refCnt = 2, refCntWtd = 2 fgMorphCopyBlock:block assignment to morph: [000572] -----+-N---- /--* LCL_VAR struct(P) V32 tmp23 /--* byref V32._pointer (offs=0x00) -> V83 tmp74 /--* int V32._length (offs=0x08) -> V84 tmp75 [001155] -A------R--- * ASG struct (copy) [001154] D------N---- \--* LCL_VAR struct(AX) V97 tmp88 (srcDoFldAsg=true) using field by field assignments. Local V97 should not be enregistered because: written in a block op lvaGrabTemp returning 101 (V101 tmp92) called for BlockOp address local. Local V97 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001172] -------N---- /--* LCL_VAR int V84 tmp75 [001173] -A---------- /--* ASG int indir assign of V97:ud:0->0 [001171] *------N---- | \--* IND int [001169] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001170] ------------ | \--* ADD byref [001168] ------------ | \--* LCL_VAR byref V101 tmp92 [001174] -A---+------ * COMMA void [001165] -------N---- | /--* LCL_VAR byref V83 tmp74 [001166] -A---------- | /--* ASG byref indir assign of V97:ud:0->0 [001164] *------N---- | | \--* IND byref [001162] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001163] ------------ | | \--* ADD byref [001161] ------------ | | \--* LCL_VAR byref V101 tmp92 [001167] -A---------- \--* COMMA void [001157] L----------- | /--* ADDR byref [001158] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001160] -A---------- \--* ASG byref [001159] D------N---- \--* LCL_VAR byref V101 tmp92 reusing outgoing struct argNew refCnts for V99: refCnt = 2, refCntWtd = 2 fgMorphCopyBlock:block assignment to morph: [000573] -----+-N---- /--* LCL_VAR struct(P) V33 tmp24 /--* byref V33._pointer (offs=0x00) -> V85 tmp76 /--* int V33._length (offs=0x08) -> V86 tmp77 [001176] -A------R--- * ASG struct (copy) [001175] D------N---- \--* LCL_VAR struct(AX) V99 tmp90 (srcDoFldAsg=true) using field by field assignments. Local V99 should not be enregistered because: written in a block op lvaGrabTemp returning 102 (V102 tmp93) called for BlockOp address local. Local V99 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001193] -------N---- /--* LCL_VAR int V86 tmp77 [001194] -A---------- /--* ASG int indir assign of V99:ud:0->0 [001192] *------N---- | \--* IND int [001190] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001191] ------------ | \--* ADD byref [001189] ------------ | \--* LCL_VAR byref V102 tmp93 [001195] -A---+------ * COMMA void [001186] -------N---- | /--* LCL_VAR byref V85 tmp76 [001187] -A---------- | /--* ASG byref indir assign of V99:ud:0->0 [001185] *------N---- | | \--* IND byref [001183] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001184] ------------ | | \--* ADD byref [001182] ------------ | | \--* LCL_VAR byref V102 tmp93 [001188] -A---------- \--* COMMA void [001178] L----------- | /--* ADDR byref [001179] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [001181] -A---------- \--* ASG byref [001180] D------N---- \--* LCL_VAR byref V102 tmp93 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Local V97 should not be enregistered because: it is address exposed Local V99 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 1197.ADDR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V97, isTmp, processed] fgArgTabEntry[arg 1 1200.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V99, isTmp, processed] GenTreeNode creates assertion: [000584] -ACXG------- * ASG bool In BB41 New Local Subrange Assertion: V37 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB41, stmt 78 (after) [000581] -----+------ /--* CNS_INT int 0 [000582] -ACXG+------ /--* EQ int [000574] -ACXG+------ | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001172] -------N---- | | /--* LCL_VAR int V84 tmp75 [001173] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 [001171] *------N---- | | | \--* IND int [001169] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001170] ------------ | | | \--* ADD byref [001168] ------------ | | | \--* LCL_VAR byref V101 tmp92 [001174] -A---+----L- arg0 SETUP | +--* COMMA void [001165] -------N---- | | | /--* LCL_VAR byref V83 tmp74 [001166] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 [001164] *------N---- | | | | \--* IND byref [001162] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001163] ------------ | | | | \--* ADD byref [001161] ------------ | | | | \--* LCL_VAR byref V101 tmp92 [001167] -A---------- | | \--* COMMA void [001157] L----------- | | | /--* ADDR byref [001158] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001160] -A---------- | | \--* ASG byref [001159] D------N---- | | \--* LCL_VAR byref V101 tmp92 [001193] -------N---- | | /--* LCL_VAR int V86 tmp77 [001194] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 [001192] *------N---- | | | \--* IND int [001190] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001191] ------------ | | | \--* ADD byref [001189] ------------ | | | \--* LCL_VAR byref V102 tmp93 [001195] -A---+----L- arg1 SETUP | +--* COMMA void [001186] -------N---- | | | /--* LCL_VAR byref V85 tmp76 [001187] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 [001185] *------N---- | | | | \--* IND byref [001183] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001184] ------------ | | | | \--* ADD byref [001182] ------------ | | | | \--* LCL_VAR byref V102 tmp93 [001188] -A---------- | | \--* COMMA void [001178] L----------- | | | /--* ADDR byref [001179] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001181] -A---------- | | \--* ASG byref [001180] D------N---- | | \--* LCL_VAR byref V102 tmp93 [001197] L----------- arg0 in rcx | +--* ADDR byref [001196] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001200] L----------- arg1 in rdx | \--* ADDR byref [001199] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 [000584] -ACXG+------ * ASG bool [000583] D----+-N---- \--* LCL_VAR int V37 tmp28 Morphing BB42 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB43 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB43, stmt 79 (before) [000051] --C--------- /--* CAST int <- bool <- int [000588] ------------ | \--* CAST int <- bool <- int [000587] ------------ | \--* LCL_VAR int V37 tmp28 [000053] -AC--------- * ASG int [000052] D------N---- \--* LCL_VAR int V06 loc4 GenTreeNode creates assertion: [000053] -A---------- * ASG int In BB43 New Local Copy Assertion: V06 == V37 index=#01, mask=0000000000000001 fgMorphTree BB43, stmt 79 (after) [000587] -----+------ /--* LCL_VAR int V37 tmp28 [000053] -A---+------ * ASG int [000052] D----+-N---- \--* LCL_VAR int V06 loc4 fgMorphTree BB43, stmt 80 (before) [000058] ------------ * JTRUE void [000056] ------------ | /--* CNS_INT int 0 [000057] ------------ \--* EQ int [000055] ------------ \--* LCL_VAR int V06 loc4 Assertion prop in BB43: Copy Assertion: V06 == V37 index=#01, mask=0000000000000001 [000055] ------------ * LCL_VAR int V37 tmp28 fgMorphTree BB43, stmt 80 (after) [000058] -----+------ * JTRUE void [000056] -----+------ | /--* CNS_INT int 0 [000057] J----+-N---- \--* EQ int [000055] -----+------ \--* LCL_VAR int V37 tmp28 Morphing BB04 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB04, stmt 81 (before) [000147] ------------ /--* CNS_INT int 0 [000149] -A-XG------- * ASG byte [000148] *------N---- \--* IND byte [000146] ------------ \--* LCL_VAR byref V01 arg1 fgMorphTree BB04, stmt 82 (before) [000151] ------------ /--* CNS_INT int 1 [000153] -A---------- * ASG int [000152] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000153] -A---------- * ASG int In BB04 New Local Constant Assertion: V05 == 1 index=#01, mask=0000000000000001 Morphing BB05 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB05, stmt 83 (before) [000062] S-C-G------- * CALL void System.Boolean.TrimWhiteSpaceAndNull [000067] L----------- arg0 +--* ADDR byref [000066] ------------ | \--* LCL_VAR struct V00 arg0 [000064] x----------- arg1 \--* OBJ(16) struct [000063] L----------- \--* ADDR byref [000061] ------------ \--* LCL_VAR struct V00 arg0 Replacing address of implicit by ref struct parameter with byref: [000066] ------------ * LCL_VAR byref V00 arg0 Replacing address of implicit by ref struct parameter with byref: [000061] ------------ * LCL_VAR byref V00 arg0 reusing outgoing struct argNew refCnts for V97: refCnt = 3, refCntWtd = 4 fgMorphCopyBlock:block assignment to morph: [000064] x----+-N---- /--* OBJ(16) struct [000061] -----+------ | \--* LCL_VAR byref V00 arg0 [001204] -A------R--- * ASG struct (copy) [001203] D------N---- \--* LCL_VAR struct(AX) V97 tmp88 with no promoted structs this requires a CopyBlock. Local V97 should not be enregistered because: written in a block op argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000066] -----+------ * LCL_VAR byref V00 arg0 lvaGrabTemp returning 103 (V103 tmp94) called for argument with side effect. Evaluate to a temp: [000066] -----+------ /--* LCL_VAR byref V00 arg0 [001206] -A--------L- * ASG byref [001205] D------N---- \--* LCL_VAR byref V103 tmp94 Local V97 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 1207.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V103, isTmp, processed] fgArgTabEntry[arg 1 1210.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V97, isTmp, processed] fgMorphTree BB05, stmt 83 (after) [000062] SACXG+------ * CALL void System.Boolean.TrimWhiteSpaceAndNull [000066] -----+------ | /--* LCL_VAR byref V00 arg0 [001206] -A--------L- arg0 SETUP +--* ASG byref [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 [000064] x----+-N---- | /--* IND struct [000061] -----+------ | | \--* LCL_VAR byref V00 arg0 [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 [001210] L----------- arg1 in rdx \--* ADDR byref [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 fgMorphTree BB05, stmt 84 (before) [000077] x----------- /--* OBJ(16) struct [000076] L----------- | \--* ADDR byref [000070] ------------ | \--* LCL_VAR struct(P) V02 loc0 | \--* byref V02._pointer (offs=0x00) -> V61 tmp52 | \--* int V02._length (offs=0x08) -> V62 tmp53 [000731] -A------R--- * ASG struct (copy) [000729] D----------- \--* LCL_VAR struct(P) V41 tmp32 \--* byref V41._pointer (offs=0x00) -> V87 tmp78 \--* int V41._length (offs=0x08) -> V88 tmp79 fgMorphCopyBlock:block assignment to morph: [000077] x----+------ /--* OBJ(16) struct [000076] L----+------ | \--* ADDR byref [000070] -----+-N---- | \--* LCL_VAR struct(P) V02 loc0 | \--* byref V02._pointer (offs=0x00) -> V61 tmp52 | \--* int V02._length (offs=0x08) -> V62 tmp53 [000731] -A------R--- * ASG struct (copy) [000729] D----+-N---- \--* LCL_VAR struct(P) V41 tmp32 \--* byref V41._pointer (offs=0x00) -> V87 tmp78 \--* int V41._length (offs=0x08) -> V88 tmp79 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001214] -A---------- * ASG byref In BB05 New Local Copy Assertion: V87 == V61 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [001217] -A---------- * ASG int In BB05 New Local Copy Assertion: V88 == V62 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [001216] -------N---- /--* LCL_VAR int V62 tmp53 [001217] -A---------- /--* ASG int [001215] D------N---- | \--* LCL_VAR int V88 tmp79 [001218] -A---+------ * COMMA void [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 [001214] -A---------- \--* ASG byref [001212] D------N---- \--* LCL_VAR byref V87 tmp78 fgMorphTree BB05, stmt 84 (after) [001216] -------N---- /--* LCL_VAR int V62 tmp53 [001217] -A---------- /--* ASG int [001215] D------N---- | \--* LCL_VAR int V88 tmp79 [001218] -A---+------ * COMMA void [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 [001214] -A---------- \--* ASG byref [001212] D------N---- \--* LCL_VAR byref V87 tmp78 fgMorphTree BB05, stmt 85 (before) [000074] x----------- /--* OBJ(16) struct [000073] L----------- | \--* ADDR byref [000071] ------------ | \--* LCL_VAR struct V00 arg0 [000735] -A------R--- * ASG struct (copy) [000733] D----------- \--* LCL_VAR struct(P) V42 tmp33 \--* byref V42._pointer (offs=0x00) -> V89 tmp80 \--* int V42._length (offs=0x08) -> V90 tmp81 Replacing address of implicit by ref struct parameter with byref: [000071] ------------ * LCL_VAR byref V00 arg0 fgMorphCopyBlock:block assignment to morph: [000074] x----+------ /--* OBJ(16) struct [000071] -----+------ | \--* LCL_VAR byref V00 arg0 [000735] -A------R--- * ASG struct (copy) [000733] D----+-N---- \--* LCL_VAR struct(P) V42 tmp33 \--* byref V42._pointer (offs=0x00) -> V89 tmp80 \--* int V42._length (offs=0x08) -> V90 tmp81 (destDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001231] -A---------- * ASG int In BB05 New Local Subrange Assertion: V90 in [-2147483648..2147483647] index=#03, mask=0000000000000004 fgMorphCopyBlock (after): [001230] x----------- /--* IND int [001228] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001229] ------------ | \--* ADD byref [001227] ------------ | \--* LCL_VAR byref V00 arg0 [001231] -A---------- /--* ASG int [001226] D------N---- | \--* LCL_VAR int V90 tmp81 [001232] -A---+------ * COMMA void [001224] x----------- | /--* IND byref [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001223] ------------ | | \--* ADD byref [001221] ------------ | | \--* LCL_VAR byref V00 arg0 [001225] -A---------- \--* ASG byref [001220] D------N---- \--* LCL_VAR byref V89 tmp80 fgMorphTree BB05, stmt 85 (after) [001230] x----------- /--* IND int [001228] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001229] ------------ | \--* ADD byref [001227] ------------ | \--* LCL_VAR byref V00 arg0 [001231] -A---------- /--* ASG int [001226] D------N---- | \--* LCL_VAR int V90 tmp81 [001232] -A---+------ * COMMA void [001224] x----------- | /--* IND byref [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001223] ------------ | | \--* ADD byref [001221] ------------ | | \--* LCL_VAR byref V00 arg0 [001225] -A---------- \--* ASG byref [001220] D------N---- \--* LCL_VAR byref V89 tmp80 fgMorphTree BB05, stmt 86 (before) [000737] ------------ /--* CNS_INT int 0 [000739] -A---------- * ASG bool [000738] D------N---- \--* LCL_VAR bool V44 tmp35 GenTreeNode creates assertion: [000739] -A---------- * ASG bool In BB05 New Local Constant Assertion: V44 == 0 index=#04, mask=0000000000000008 fgMorphTree BB05, stmt 87 (before) [000741] ------------ /--* CNS_INT int 0 [000743] -A---------- * ASG bool [000742] D------N---- \--* LCL_VAR bool V46 tmp37 GenTreeNode creates assertion: [000743] -A---------- * ASG bool In BB05 New Local Constant Assertion: V46 == 0 index=#05, mask=0000000000000010 fgMorphTree BB05, stmt 88 (before) [000745] ------------ /--* CNS_INT int 0 [000747] -A---------- * ASG bool [000746] D------N---- \--* LCL_VAR bool V45 tmp36 GenTreeNode creates assertion: [000747] -A---------- * ASG bool In BB05 New Local Constant Assertion: V45 == 0 index=#06, mask=0000000000000020 Morphing BB47 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB47, stmt 89 (before) [000758] ------------ /--* CNS_INT int 0 [000760] -A---------- * ASG int [000759] D------N---- \--* LCL_VAR int V47 tmp38 GenTreeNode creates assertion: [000760] -A---------- * ASG int In BB47 New Local Constant Assertion: V47 == 0 index=#01, mask=0000000000000001 fgMorphTree BB47, stmt 90 (before) [000753] ------------ /--* LCL_VAR int V88 tmp79 [000755] -A---------- * ASG int [000754] D------N---- \--* LCL_VAR int V47 tmp38 The assignment [000755] using V47 removes: Constant Assertion: V47 == 0 GenTreeNode creates assertion: [000755] -A---------- * ASG int In BB47 New Local Copy Assertion: V47 == V88 index=#01, mask=0000000000000001 fgMorphTree BB47, stmt 91 (before) [000757] ------------ /--* LCL_VAR int V47 tmp38 [000670] -AC--------- * ASG int [000669] D------N---- \--* LCL_VAR int V43 tmp34 Assertion prop in BB47: Copy Assertion: V47 == V88 index=#01, mask=0000000000000001 [000757] ------------ * LCL_VAR int V88 tmp79 GenTreeNode creates assertion: [000670] -A---------- * ASG int In BB47 New Local Copy Assertion: V43 == V88 index=#02, mask=0000000000000002 fgMorphTree BB47, stmt 91 (after) [000757] -----+------ /--* LCL_VAR int V88 tmp79 [000670] -A---+------ * ASG int [000669] D----+-N---- \--* LCL_VAR int V43 tmp34 fgMorphTree BB47, stmt 92 (before) [000771] ------------ /--* CNS_INT int 0 [000773] -A---------- * ASG int [000772] D------N---- \--* LCL_VAR int V48 tmp39 GenTreeNode creates assertion: [000773] -A---------- * ASG int In BB47 New Local Constant Assertion: V48 == 0 index=#03, mask=0000000000000004 fgMorphTree BB47, stmt 93 (before) [000766] ------------ /--* LCL_VAR int V90 tmp81 [000768] -A---------- * ASG int [000767] D------N---- \--* LCL_VAR int V48 tmp39 The assignment [000768] using V48 removes: Constant Assertion: V48 == 0 GenTreeNode creates assertion: [000768] -A---------- * ASG int In BB47 New Local Copy Assertion: V48 == V90 index=#03, mask=0000000000000004 fgMorphTree BB47, stmt 94 (before) [000675] ------------ /--* CNS_INT int 0 [000676] --C--------- /--* EQ int [000770] ------------ | | /--* LCL_VAR int V48 tmp39 [000674] --C--------- | \--* EQ int [000672] ------------ | \--* LCL_VAR int V43 tmp34 [000678] -AC--------- * ASG bool [000677] D------N---- \--* LCL_VAR bool V44 tmp35 Assertion prop in BB47: Copy Assertion: V43 == V88 index=#02, mask=0000000000000002 [000672] ------------ * LCL_VAR int V88 tmp79 Assertion prop in BB47: Copy Assertion: V48 == V90 index=#03, mask=0000000000000004 [000770] ------------ * LCL_VAR int V90 tmp81 GenTreeNode creates assertion: [000678] -A---------- * ASG bool In BB47 New Local Subrange Assertion: V44 in [0..1] index=#04, mask=0000000000000008 fgMorphTree BB47, stmt 94 (after) [000770] -----+------ /--* LCL_VAR int V90 tmp81 [000674] -----+------ /--* NE int [000672] -----+------ | \--* LCL_VAR int V88 tmp79 [000678] -A---+------ * ASG bool [000677] D----+-N---- \--* LCL_VAR int V44 tmp35 fgMorphTree BB47, stmt 95 (before) [000683] ------------ * JTRUE void [000681] ------------ | /--* CNS_INT int 0 [000682] ------------ \--* EQ int [000680] ------------ \--* LCL_VAR int V44 tmp35 Morphing BB48 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB48, stmt 96 (before) [000725] ------------ /--* CNS_INT int 0 [000727] -A---------- * ASG bool [000726] D------N---- \--* LCL_VAR bool V46 tmp37 GenTreeNode creates assertion: [000727] -A---------- * ASG bool In BB48 New Local Constant Assertion: V46 == 0 index=#01, mask=0000000000000001 Morphing BB49 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB49, stmt 97 (before) [000784] ------------ /--* CNS_INT int 0 [000786] -A---------- * ASG int [000785] D------N---- \--* LCL_VAR int V49 tmp40 GenTreeNode creates assertion: [000786] -A---------- * ASG int In BB49 New Local Constant Assertion: V49 == 0 index=#01, mask=0000000000000001 fgMorphTree BB49, stmt 98 (before) [000779] ------------ /--* LCL_VAR int V90 tmp81 [000781] -A---------- * ASG int [000780] D------N---- \--* LCL_VAR int V49 tmp40 The assignment [000781] using V49 removes: Constant Assertion: V49 == 0 GenTreeNode creates assertion: [000781] -A---------- * ASG int In BB49 New Local Copy Assertion: V49 == V90 index=#01, mask=0000000000000001 fgMorphTree BB49, stmt 99 (before) [000691] ------------ /--* CNS_INT int 0 [000692] --C--------- /--* EQ int [000783] ------------ | \--* LCL_VAR int V49 tmp40 [000694] -AC--------- * ASG bool [000693] D------N---- \--* LCL_VAR bool V45 tmp36 Assertion prop in BB49: Copy Assertion: V49 == V90 index=#01, mask=0000000000000001 [000783] ------------ * LCL_VAR int V90 tmp81 GenTreeNode creates assertion: [000694] -A---------- * ASG bool In BB49 New Local Subrange Assertion: V45 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB49, stmt 99 (after) [000691] -----+------ /--* CNS_INT int 0 [000692] -----+------ /--* EQ int [000783] -----+------ | \--* LCL_VAR int V90 tmp81 [000694] -A---+------ * ASG bool [000693] D----+-N---- \--* LCL_VAR int V45 tmp36 fgMorphTree BB49, stmt 100 (before) [000699] ------------ * JTRUE void [000697] ------------ | /--* CNS_INT int 0 [000698] ------------ \--* EQ int [000696] ------------ \--* LCL_VAR int V45 tmp36 Morphing BB50 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB50, stmt 101 (before) [000720] ------------ /--* CNS_INT int 1 [000722] -A---------- * ASG bool [000721] D------N---- \--* LCL_VAR bool V46 tmp37 GenTreeNode creates assertion: [000722] -A---------- * ASG bool In BB50 New Local Constant Assertion: V46 == 1 index=#01, mask=0000000000000001 Morphing BB51 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB51, stmt 102 (before) [000711] ------------ /--* CNS_INT int 0 [000712] --C-G------- /--* EQ int [000704] --C-G------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000709] x----------- arg0 | +--* OBJ(16) struct [000708] L----------- | | \--* ADDR byref [000702] ------------ | | \--* LCL_VAR struct(P) V41 tmp32 | | \--* byref V41._pointer (offs=0x00) -> V87 tmp78 | | \--* int V41._length (offs=0x08) -> V88 tmp79 [000706] x----------- arg1 | \--* OBJ(16) struct [000705] L----------- | \--* ADDR byref [000703] ------------ | \--* LCL_VAR struct(P) V42 tmp33 | \--* byref V42._pointer (offs=0x00) -> V89 tmp80 | \--* int V42._length (offs=0x08) -> V90 tmp81 [000714] -AC-G------- * ASG bool [000713] D------N---- \--* LCL_VAR bool V46 tmp37 reusing outgoing struct argNew refCnts for V97: refCnt = 4, refCntWtd = 5 fgMorphCopyBlock:block assignment to morph: [000702] -----+-N---- /--* LCL_VAR struct(P) V41 tmp32 /--* byref V41._pointer (offs=0x00) -> V87 tmp78 /--* int V41._length (offs=0x08) -> V88 tmp79 [001239] -A------R--- * ASG struct (copy) [001238] D------N---- \--* LCL_VAR struct(AX) V97 tmp88 (srcDoFldAsg=true) using field by field assignments. Local V97 should not be enregistered because: written in a block op lvaGrabTemp returning 104 (V104 tmp95) called for BlockOp address local. Local V97 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001256] -------N---- /--* LCL_VAR int V88 tmp79 [001257] -A---------- /--* ASG int indir assign of V97:ud:0->0 [001255] *------N---- | \--* IND int [001253] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001254] ------------ | \--* ADD byref [001252] ------------ | \--* LCL_VAR byref V104 tmp95 [001258] -A---+------ * COMMA void [001249] -------N---- | /--* LCL_VAR byref V87 tmp78 [001250] -A---------- | /--* ASG byref indir assign of V97:ud:0->0 [001248] *------N---- | | \--* IND byref [001246] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001247] ------------ | | \--* ADD byref [001245] ------------ | | \--* LCL_VAR byref V104 tmp95 [001251] -A---------- \--* COMMA void [001241] L----------- | /--* ADDR byref [001242] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001244] -A---------- \--* ASG byref [001243] D------N---- \--* LCL_VAR byref V104 tmp95 reusing outgoing struct argNew refCnts for V99: refCnt = 3, refCntWtd = 3 fgMorphCopyBlock:block assignment to morph: [000703] -----+-N---- /--* LCL_VAR struct(P) V42 tmp33 /--* byref V42._pointer (offs=0x00) -> V89 tmp80 /--* int V42._length (offs=0x08) -> V90 tmp81 [001260] -A------R--- * ASG struct (copy) [001259] D------N---- \--* LCL_VAR struct(AX) V99 tmp90 (srcDoFldAsg=true) using field by field assignments. Local V99 should not be enregistered because: written in a block op lvaGrabTemp returning 105 (V105 tmp96) called for BlockOp address local. Local V99 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001277] -------N---- /--* LCL_VAR int V90 tmp81 [001278] -A---------- /--* ASG int indir assign of V99:ud:0->0 [001276] *------N---- | \--* IND int [001274] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001275] ------------ | \--* ADD byref [001273] ------------ | \--* LCL_VAR byref V105 tmp96 [001279] -A---+------ * COMMA void [001270] -------N---- | /--* LCL_VAR byref V89 tmp80 [001271] -A---------- | /--* ASG byref indir assign of V99:ud:0->0 [001269] *------N---- | | \--* IND byref [001267] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001268] ------------ | | \--* ADD byref [001266] ------------ | | \--* LCL_VAR byref V105 tmp96 [001272] -A---------- \--* COMMA void [001262] L----------- | /--* ADDR byref [001263] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [001265] -A---------- \--* ASG byref [001264] D------N---- \--* LCL_VAR byref V105 tmp96 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Local V97 should not be enregistered because: it is address exposed Local V99 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 1281.ADDR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V97, isTmp, processed] fgArgTabEntry[arg 1 1284.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V99, isTmp, processed] GenTreeNode creates assertion: [000714] -ACXG------- * ASG bool In BB51 New Local Subrange Assertion: V46 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB51, stmt 102 (after) [000711] -----+------ /--* CNS_INT int 0 [000712] -ACXG+------ /--* EQ int [000704] -ACXG+------ | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001256] -------N---- | | /--* LCL_VAR int V88 tmp79 [001257] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 [001255] *------N---- | | | \--* IND int [001253] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001254] ------------ | | | \--* ADD byref [001252] ------------ | | | \--* LCL_VAR byref V104 tmp95 [001258] -A---+----L- arg0 SETUP | +--* COMMA void [001249] -------N---- | | | /--* LCL_VAR byref V87 tmp78 [001250] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 [001248] *------N---- | | | | \--* IND byref [001246] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001247] ------------ | | | | \--* ADD byref [001245] ------------ | | | | \--* LCL_VAR byref V104 tmp95 [001251] -A---------- | | \--* COMMA void [001241] L----------- | | | /--* ADDR byref [001242] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001244] -A---------- | | \--* ASG byref [001243] D------N---- | | \--* LCL_VAR byref V104 tmp95 [001277] -------N---- | | /--* LCL_VAR int V90 tmp81 [001278] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 [001276] *------N---- | | | \--* IND int [001274] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001275] ------------ | | | \--* ADD byref [001273] ------------ | | | \--* LCL_VAR byref V105 tmp96 [001279] -A---+----L- arg1 SETUP | +--* COMMA void [001270] -------N---- | | | /--* LCL_VAR byref V89 tmp80 [001271] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 [001269] *------N---- | | | | \--* IND byref [001267] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001268] ------------ | | | | \--* ADD byref [001266] ------------ | | | | \--* LCL_VAR byref V105 tmp96 [001272] -A---------- | | \--* COMMA void [001262] L----------- | | | /--* ADDR byref [001263] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001265] -A---------- | | \--* ASG byref [001264] D------N---- | | \--* LCL_VAR byref V105 tmp96 [001281] L----------- arg0 in rcx | +--* ADDR byref [001280] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001284] L----------- arg1 in rdx | \--* ADDR byref [001283] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 [000714] -ACXG+------ * ASG bool [000713] D----+-N---- \--* LCL_VAR int V46 tmp37 Morphing BB52 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB53 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB53, stmt 103 (before) [000081] --C--------- /--* CAST int <- bool <- int [000718] ------------ | \--* CAST int <- bool <- int [000717] ------------ | \--* LCL_VAR int V46 tmp37 [000083] -AC--------- * ASG int [000082] D------N---- \--* LCL_VAR int V07 loc5 GenTreeNode creates assertion: [000083] -A---------- * ASG int In BB53 New Local Copy Assertion: V07 == V46 index=#01, mask=0000000000000001 fgMorphTree BB53, stmt 103 (after) [000717] -----+------ /--* LCL_VAR int V46 tmp37 [000083] -A---+------ * ASG int [000082] D----+-N---- \--* LCL_VAR int V07 loc5 fgMorphTree BB53, stmt 104 (before) [000088] ------------ * JTRUE void [000086] ------------ | /--* CNS_INT int 0 [000087] ------------ \--* EQ int [000085] ------------ \--* LCL_VAR int V07 loc5 Assertion prop in BB53: Copy Assertion: V07 == V46 index=#01, mask=0000000000000001 [000085] ------------ * LCL_VAR int V46 tmp37 fgMorphTree BB53, stmt 104 (after) [000088] -----+------ * JTRUE void [000086] -----+------ | /--* CNS_INT int 0 [000087] J----+-N---- \--* EQ int [000085] -----+------ \--* LCL_VAR int V46 tmp37 Morphing BB06 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB06, stmt 105 (before) [000137] ------------ /--* CNS_INT int 1 [000139] -A-XG------- * ASG byte [000138] *------N---- \--* IND byte [000136] ------------ \--* LCL_VAR byref V01 arg1 fgMorphTree BB06, stmt 106 (before) [000141] ------------ /--* CNS_INT int 1 [000143] -A---------- * ASG int [000142] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000143] -A---------- * ASG int In BB06 New Local Constant Assertion: V05 == 1 index=#01, mask=0000000000000001 Morphing BB07 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB07, stmt 107 (before) [000098] x----------- /--* OBJ(16) struct [000097] L----------- | \--* ADDR byref [000091] ------------ | \--* LCL_VAR struct(P) V03 loc1 | \--* byref V03._pointer (offs=0x00) -> V63 tmp54 | \--* int V03._length (offs=0x08) -> V64 tmp55 [000861] -A------R--- * ASG struct (copy) [000859] D----------- \--* LCL_VAR struct(P) V50 tmp41 \--* byref V50._pointer (offs=0x00) -> V91 tmp82 \--* int V50._length (offs=0x08) -> V92 tmp83 fgMorphCopyBlock:block assignment to morph: [000098] x----+------ /--* OBJ(16) struct [000097] L----+------ | \--* ADDR byref [000091] -----+-N---- | \--* LCL_VAR struct(P) V03 loc1 | \--* byref V03._pointer (offs=0x00) -> V63 tmp54 | \--* int V03._length (offs=0x08) -> V64 tmp55 [000861] -A------R--- * ASG struct (copy) [000859] D----+-N---- \--* LCL_VAR struct(P) V50 tmp41 \--* byref V50._pointer (offs=0x00) -> V91 tmp82 \--* int V50._length (offs=0x08) -> V92 tmp83 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001289] -A---------- * ASG byref In BB07 New Local Copy Assertion: V91 == V63 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [001292] -A---------- * ASG int In BB07 New Local Copy Assertion: V92 == V64 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [001291] -------N---- /--* LCL_VAR int V64 tmp55 [001292] -A---------- /--* ASG int [001290] D------N---- | \--* LCL_VAR int V92 tmp83 [001293] -A---+------ * COMMA void [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 [001289] -A---------- \--* ASG byref [001287] D------N---- \--* LCL_VAR byref V91 tmp82 fgMorphTree BB07, stmt 107 (after) [001291] -------N---- /--* LCL_VAR int V64 tmp55 [001292] -A---------- /--* ASG int [001290] D------N---- | \--* LCL_VAR int V92 tmp83 [001293] -A---+------ * COMMA void [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 [001289] -A---------- \--* ASG byref [001287] D------N---- \--* LCL_VAR byref V91 tmp82 fgMorphTree BB07, stmt 108 (before) [000095] x----------- /--* OBJ(16) struct [000094] L----------- | \--* ADDR byref [000092] ------------ | \--* LCL_VAR struct V00 arg0 [000865] -A------R--- * ASG struct (copy) [000863] D----------- \--* LCL_VAR struct(P) V51 tmp42 \--* byref V51._pointer (offs=0x00) -> V93 tmp84 \--* int V51._length (offs=0x08) -> V94 tmp85 Replacing address of implicit by ref struct parameter with byref: [000092] ------------ * LCL_VAR byref V00 arg0 fgMorphCopyBlock:block assignment to morph: [000095] x----+------ /--* OBJ(16) struct [000092] -----+------ | \--* LCL_VAR byref V00 arg0 [000865] -A------R--- * ASG struct (copy) [000863] D----+-N---- \--* LCL_VAR struct(P) V51 tmp42 \--* byref V51._pointer (offs=0x00) -> V93 tmp84 \--* int V51._length (offs=0x08) -> V94 tmp85 (destDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [001306] -A---------- * ASG int In BB07 New Local Subrange Assertion: V94 in [-2147483648..2147483647] index=#03, mask=0000000000000004 fgMorphCopyBlock (after): [001305] x----------- /--* IND int [001303] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001304] ------------ | \--* ADD byref [001302] ------------ | \--* LCL_VAR byref V00 arg0 [001306] -A---------- /--* ASG int [001301] D------N---- | \--* LCL_VAR int V94 tmp85 [001307] -A---+------ * COMMA void [001299] x----------- | /--* IND byref [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001298] ------------ | | \--* ADD byref [001296] ------------ | | \--* LCL_VAR byref V00 arg0 [001300] -A---------- \--* ASG byref [001295] D------N---- \--* LCL_VAR byref V93 tmp84 fgMorphTree BB07, stmt 108 (after) [001305] x----------- /--* IND int [001303] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001304] ------------ | \--* ADD byref [001302] ------------ | \--* LCL_VAR byref V00 arg0 [001306] -A---------- /--* ASG int [001301] D------N---- | \--* LCL_VAR int V94 tmp85 [001307] -A---+------ * COMMA void [001299] x----------- | /--* IND byref [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001298] ------------ | | \--* ADD byref [001296] ------------ | | \--* LCL_VAR byref V00 arg0 [001300] -A---------- \--* ASG byref [001295] D------N---- \--* LCL_VAR byref V93 tmp84 fgMorphTree BB07, stmt 109 (before) [000867] ------------ /--* CNS_INT int 0 [000869] -A---------- * ASG bool [000868] D------N---- \--* LCL_VAR bool V53 tmp44 GenTreeNode creates assertion: [000869] -A---------- * ASG bool In BB07 New Local Constant Assertion: V53 == 0 index=#04, mask=0000000000000008 fgMorphTree BB07, stmt 110 (before) [000871] ------------ /--* CNS_INT int 0 [000873] -A---------- * ASG bool [000872] D------N---- \--* LCL_VAR bool V55 tmp46 GenTreeNode creates assertion: [000873] -A---------- * ASG bool In BB07 New Local Constant Assertion: V55 == 0 index=#05, mask=0000000000000010 fgMorphTree BB07, stmt 111 (before) [000875] ------------ /--* CNS_INT int 0 [000877] -A---------- * ASG bool [000876] D------N---- \--* LCL_VAR bool V54 tmp45 GenTreeNode creates assertion: [000877] -A---------- * ASG bool In BB07 New Local Constant Assertion: V54 == 0 index=#06, mask=0000000000000020 Morphing BB57 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB57, stmt 112 (before) [000888] ------------ /--* CNS_INT int 0 [000890] -A---------- * ASG int [000889] D------N---- \--* LCL_VAR int V56 tmp47 GenTreeNode creates assertion: [000890] -A---------- * ASG int In BB57 New Local Constant Assertion: V56 == 0 index=#01, mask=0000000000000001 fgMorphTree BB57, stmt 113 (before) [000883] ------------ /--* LCL_VAR int V92 tmp83 [000885] -A---------- * ASG int [000884] D------N---- \--* LCL_VAR int V56 tmp47 The assignment [000885] using V56 removes: Constant Assertion: V56 == 0 GenTreeNode creates assertion: [000885] -A---------- * ASG int In BB57 New Local Copy Assertion: V56 == V92 index=#01, mask=0000000000000001 fgMorphTree BB57, stmt 114 (before) [000887] ------------ /--* LCL_VAR int V56 tmp47 [000800] -AC--------- * ASG int [000799] D------N---- \--* LCL_VAR int V52 tmp43 Assertion prop in BB57: Copy Assertion: V56 == V92 index=#01, mask=0000000000000001 [000887] ------------ * LCL_VAR int V92 tmp83 GenTreeNode creates assertion: [000800] -A---------- * ASG int In BB57 New Local Copy Assertion: V52 == V92 index=#02, mask=0000000000000002 fgMorphTree BB57, stmt 114 (after) [000887] -----+------ /--* LCL_VAR int V92 tmp83 [000800] -A---+------ * ASG int [000799] D----+-N---- \--* LCL_VAR int V52 tmp43 fgMorphTree BB57, stmt 115 (before) [000901] ------------ /--* CNS_INT int 0 [000903] -A---------- * ASG int [000902] D------N---- \--* LCL_VAR int V57 tmp48 GenTreeNode creates assertion: [000903] -A---------- * ASG int In BB57 New Local Constant Assertion: V57 == 0 index=#03, mask=0000000000000004 fgMorphTree BB57, stmt 116 (before) [000896] ------------ /--* LCL_VAR int V94 tmp85 [000898] -A---------- * ASG int [000897] D------N---- \--* LCL_VAR int V57 tmp48 The assignment [000898] using V57 removes: Constant Assertion: V57 == 0 GenTreeNode creates assertion: [000898] -A---------- * ASG int In BB57 New Local Copy Assertion: V57 == V94 index=#03, mask=0000000000000004 fgMorphTree BB57, stmt 117 (before) [000805] ------------ /--* CNS_INT int 0 [000806] --C--------- /--* EQ int [000900] ------------ | | /--* LCL_VAR int V57 tmp48 [000804] --C--------- | \--* EQ int [000802] ------------ | \--* LCL_VAR int V52 tmp43 [000808] -AC--------- * ASG bool [000807] D------N---- \--* LCL_VAR bool V53 tmp44 Assertion prop in BB57: Copy Assertion: V52 == V92 index=#02, mask=0000000000000002 [000802] ------------ * LCL_VAR int V92 tmp83 Assertion prop in BB57: Copy Assertion: V57 == V94 index=#03, mask=0000000000000004 [000900] ------------ * LCL_VAR int V94 tmp85 GenTreeNode creates assertion: [000808] -A---------- * ASG bool In BB57 New Local Subrange Assertion: V53 in [0..1] index=#04, mask=0000000000000008 fgMorphTree BB57, stmt 117 (after) [000900] -----+------ /--* LCL_VAR int V94 tmp85 [000804] -----+------ /--* NE int [000802] -----+------ | \--* LCL_VAR int V92 tmp83 [000808] -A---+------ * ASG bool [000807] D----+-N---- \--* LCL_VAR int V53 tmp44 fgMorphTree BB57, stmt 118 (before) [000813] ------------ * JTRUE void [000811] ------------ | /--* CNS_INT int 0 [000812] ------------ \--* EQ int [000810] ------------ \--* LCL_VAR int V53 tmp44 Morphing BB58 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB58, stmt 119 (before) [000855] ------------ /--* CNS_INT int 0 [000857] -A---------- * ASG bool [000856] D------N---- \--* LCL_VAR bool V55 tmp46 GenTreeNode creates assertion: [000857] -A---------- * ASG bool In BB58 New Local Constant Assertion: V55 == 0 index=#01, mask=0000000000000001 Morphing BB59 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB59, stmt 120 (before) [000914] ------------ /--* CNS_INT int 0 [000916] -A---------- * ASG int [000915] D------N---- \--* LCL_VAR int V58 tmp49 GenTreeNode creates assertion: [000916] -A---------- * ASG int In BB59 New Local Constant Assertion: V58 == 0 index=#01, mask=0000000000000001 fgMorphTree BB59, stmt 121 (before) [000909] ------------ /--* LCL_VAR int V94 tmp85 [000911] -A---------- * ASG int [000910] D------N---- \--* LCL_VAR int V58 tmp49 The assignment [000911] using V58 removes: Constant Assertion: V58 == 0 GenTreeNode creates assertion: [000911] -A---------- * ASG int In BB59 New Local Copy Assertion: V58 == V94 index=#01, mask=0000000000000001 fgMorphTree BB59, stmt 122 (before) [000821] ------------ /--* CNS_INT int 0 [000822] --C--------- /--* EQ int [000913] ------------ | \--* LCL_VAR int V58 tmp49 [000824] -AC--------- * ASG bool [000823] D------N---- \--* LCL_VAR bool V54 tmp45 Assertion prop in BB59: Copy Assertion: V58 == V94 index=#01, mask=0000000000000001 [000913] ------------ * LCL_VAR int V94 tmp85 GenTreeNode creates assertion: [000824] -A---------- * ASG bool In BB59 New Local Subrange Assertion: V54 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB59, stmt 122 (after) [000821] -----+------ /--* CNS_INT int 0 [000822] -----+------ /--* EQ int [000913] -----+------ | \--* LCL_VAR int V94 tmp85 [000824] -A---+------ * ASG bool [000823] D----+-N---- \--* LCL_VAR int V54 tmp45 fgMorphTree BB59, stmt 123 (before) [000829] ------------ * JTRUE void [000827] ------------ | /--* CNS_INT int 0 [000828] ------------ \--* EQ int [000826] ------------ \--* LCL_VAR int V54 tmp45 Morphing BB60 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB60, stmt 124 (before) [000850] ------------ /--* CNS_INT int 1 [000852] -A---------- * ASG bool [000851] D------N---- \--* LCL_VAR bool V55 tmp46 GenTreeNode creates assertion: [000852] -A---------- * ASG bool In BB60 New Local Constant Assertion: V55 == 1 index=#01, mask=0000000000000001 Morphing BB61 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB61, stmt 125 (before) [000841] ------------ /--* CNS_INT int 0 [000842] --C-G------- /--* EQ int [000834] --C-G------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [000839] x----------- arg0 | +--* OBJ(16) struct [000838] L----------- | | \--* ADDR byref [000832] ------------ | | \--* LCL_VAR struct(P) V50 tmp41 | | \--* byref V50._pointer (offs=0x00) -> V91 tmp82 | | \--* int V50._length (offs=0x08) -> V92 tmp83 [000836] x----------- arg1 | \--* OBJ(16) struct [000835] L----------- | \--* ADDR byref [000833] ------------ | \--* LCL_VAR struct(P) V51 tmp42 | \--* byref V51._pointer (offs=0x00) -> V93 tmp84 | \--* int V51._length (offs=0x08) -> V94 tmp85 [000844] -AC-G------- * ASG bool [000843] D------N---- \--* LCL_VAR bool V55 tmp46 reusing outgoing struct argNew refCnts for V97: refCnt = 5, refCntWtd = 6 fgMorphCopyBlock:block assignment to morph: [000832] -----+-N---- /--* LCL_VAR struct(P) V50 tmp41 /--* byref V50._pointer (offs=0x00) -> V91 tmp82 /--* int V50._length (offs=0x08) -> V92 tmp83 [001314] -A------R--- * ASG struct (copy) [001313] D------N---- \--* LCL_VAR struct(AX) V97 tmp88 (srcDoFldAsg=true) using field by field assignments. Local V97 should not be enregistered because: written in a block op lvaGrabTemp returning 106 (V106 tmp97) called for BlockOp address local. Local V97 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001331] -------N---- /--* LCL_VAR int V92 tmp83 [001332] -A---------- /--* ASG int indir assign of V97:ud:0->0 [001330] *------N---- | \--* IND int [001328] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001329] ------------ | \--* ADD byref [001327] ------------ | \--* LCL_VAR byref V106 tmp97 [001333] -A---+------ * COMMA void [001324] -------N---- | /--* LCL_VAR byref V91 tmp82 [001325] -A---------- | /--* ASG byref indir assign of V97:ud:0->0 [001323] *------N---- | | \--* IND byref [001321] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001322] ------------ | | \--* ADD byref [001320] ------------ | | \--* LCL_VAR byref V106 tmp97 [001326] -A---------- \--* COMMA void [001316] L----------- | /--* ADDR byref [001317] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001319] -A---------- \--* ASG byref [001318] D------N---- \--* LCL_VAR byref V106 tmp97 reusing outgoing struct argNew refCnts for V99: refCnt = 4, refCntWtd = 4 fgMorphCopyBlock:block assignment to morph: [000833] -----+-N---- /--* LCL_VAR struct(P) V51 tmp42 /--* byref V51._pointer (offs=0x00) -> V93 tmp84 /--* int V51._length (offs=0x08) -> V94 tmp85 [001335] -A------R--- * ASG struct (copy) [001334] D------N---- \--* LCL_VAR struct(AX) V99 tmp90 (srcDoFldAsg=true) using field by field assignments. Local V99 should not be enregistered because: written in a block op lvaGrabTemp returning 107 (V107 tmp98) called for BlockOp address local. Local V99 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [001352] -------N---- /--* LCL_VAR int V94 tmp85 [001353] -A---------- /--* ASG int indir assign of V99:ud:0->0 [001351] *------N---- | \--* IND int [001349] ------------ | | /--* CNS_INT long 8 Fseq[_length] [001350] ------------ | \--* ADD byref [001348] ------------ | \--* LCL_VAR byref V107 tmp98 [001354] -A---+------ * COMMA void [001345] -------N---- | /--* LCL_VAR byref V93 tmp84 [001346] -A---------- | /--* ASG byref indir assign of V99:ud:0->0 [001344] *------N---- | | \--* IND byref [001342] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001343] ------------ | | \--* ADD byref [001341] ------------ | | \--* LCL_VAR byref V107 tmp98 [001347] -A---------- \--* COMMA void [001337] L----------- | /--* ADDR byref [001338] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [001340] -A---------- \--* ASG byref [001339] D------N---- \--* LCL_VAR byref V107 tmp98 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Local V97 should not be enregistered because: it is address exposed Local V99 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 1356.ADDR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V97, isTmp, processed] fgArgTabEntry[arg 1 1359.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V99, isTmp, processed] GenTreeNode creates assertion: [000844] -ACXG------- * ASG bool In BB61 New Local Subrange Assertion: V55 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB61, stmt 125 (after) [000841] -----+------ /--* CNS_INT int 0 [000842] -ACXG+------ /--* EQ int [000834] -ACXG+------ | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001331] -------N---- | | /--* LCL_VAR int V92 tmp83 [001332] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 [001330] *------N---- | | | \--* IND int [001328] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001329] ------------ | | | \--* ADD byref [001327] ------------ | | | \--* LCL_VAR byref V106 tmp97 [001333] -A---+----L- arg0 SETUP | +--* COMMA void [001324] -------N---- | | | /--* LCL_VAR byref V91 tmp82 [001325] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 [001323] *------N---- | | | | \--* IND byref [001321] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001322] ------------ | | | | \--* ADD byref [001320] ------------ | | | | \--* LCL_VAR byref V106 tmp97 [001326] -A---------- | | \--* COMMA void [001316] L----------- | | | /--* ADDR byref [001317] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001319] -A---------- | | \--* ASG byref [001318] D------N---- | | \--* LCL_VAR byref V106 tmp97 [001352] -------N---- | | /--* LCL_VAR int V94 tmp85 [001353] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 [001351] *------N---- | | | \--* IND int [001349] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] [001350] ------------ | | | \--* ADD byref [001348] ------------ | | | \--* LCL_VAR byref V107 tmp98 [001354] -A---+----L- arg1 SETUP | +--* COMMA void [001345] -------N---- | | | /--* LCL_VAR byref V93 tmp84 [001346] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 [001344] *------N---- | | | | \--* IND byref [001342] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001343] ------------ | | | | \--* ADD byref [001341] ------------ | | | | \--* LCL_VAR byref V107 tmp98 [001347] -A---------- | | \--* COMMA void [001337] L----------- | | | /--* ADDR byref [001338] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001340] -A---------- | | \--* ASG byref [001339] D------N---- | | \--* LCL_VAR byref V107 tmp98 [001356] L----------- arg0 in rcx | +--* ADDR byref [001355] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 [001359] L----------- arg1 in rdx | \--* ADDR byref [001358] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 [000844] -ACXG+------ * ASG bool [000843] D----+-N---- \--* LCL_VAR int V55 tmp46 Morphing BB62 of 'System.Boolean:TryParse(struct,byref):bool' Morphing BB63 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB63, stmt 126 (before) [000102] --C--------- /--* CAST int <- bool <- int [000848] ------------ | \--* CAST int <- bool <- int [000847] ------------ | \--* LCL_VAR int V55 tmp46 [000104] -AC--------- * ASG int [000103] D------N---- \--* LCL_VAR int V08 loc6 GenTreeNode creates assertion: [000104] -A---------- * ASG int In BB63 New Local Copy Assertion: V08 == V55 index=#01, mask=0000000000000001 fgMorphTree BB63, stmt 126 (after) [000847] -----+------ /--* LCL_VAR int V55 tmp46 [000104] -A---+------ * ASG int [000103] D----+-N---- \--* LCL_VAR int V08 loc6 fgMorphTree BB63, stmt 127 (before) [000109] ------------ * JTRUE void [000107] ------------ | /--* CNS_INT int 0 [000108] ------------ \--* EQ int [000106] ------------ \--* LCL_VAR int V08 loc6 Assertion prop in BB63: Copy Assertion: V08 == V55 index=#01, mask=0000000000000001 [000106] ------------ * LCL_VAR int V55 tmp46 fgMorphTree BB63, stmt 127 (after) [000109] -----+------ * JTRUE void [000107] -----+------ | /--* CNS_INT int 0 [000108] J----+-N---- \--* EQ int [000106] -----+------ \--* LCL_VAR int V55 tmp46 Morphing BB08 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB08, stmt 128 (before) [000127] ------------ /--* CNS_INT int 0 [000129] -A-XG------- * ASG byte [000128] *------N---- \--* IND byte [000126] ------------ \--* LCL_VAR byref V01 arg1 fgMorphTree BB08, stmt 129 (before) [000131] ------------ /--* CNS_INT int 1 [000133] -A---------- * ASG int [000132] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000133] -A---------- * ASG int In BB08 New Local Constant Assertion: V05 == 1 index=#01, mask=0000000000000001 Morphing BB09 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB09, stmt 130 (before) [000113] ------------ /--* CNS_INT int 0 [000115] -A-XG------- * ASG byte [000114] *------N---- \--* IND byte [000112] ------------ \--* LCL_VAR byref V01 arg1 fgMorphTree BB09, stmt 131 (before) [000117] ------------ /--* CNS_INT int 0 [000119] -A---------- * ASG int [000118] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000119] -A---------- * ASG int In BB09 New Local Constant Assertion: V05 == 0 index=#01, mask=0000000000000001 Morphing BB10 of 'System.Boolean:TryParse(struct,byref):bool' fgMorphTree BB10, stmt 132 (before) [000123] ------------ * RETURN int [000122] ------------ \--* LCL_VAR int V05 loc3 Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i BB11 [0010] 1 1 [001..002)-> BB13 ( cond ) i BB12 [0011] 1 0.50 [001..002)-> BB14 (always) i BB13 [0012] 1 0.50 [001..002) i gcsafe BB14 [0013] 2 1 [001..002) i BB15 [0014] 1 1 [???..???) internal BB19 [0018] 1 1 [00C..00D)-> BB21 ( cond ) i BB20 [0019] 1 0.50 [00C..00D)-> BB24 (always) i BB21 [0020] 1 0.50 [00C..00D)-> BB23 ( cond ) i BB22 [0021] 1 0.50 [00C..00D)-> BB24 (always) i BB23 [0022] 1 0.50 [00C..00D) i gcsafe BB24 [0023] 3 1 [00C..00D) i BB25 [0024] 1 1 [???..???)-> BB03 ( cond ) internal BB02 [0001] 1 1 [017..01F)-> BB10 (always) i BB03 [0002] 1 1 [01F..037) i BB29 [0028] 1 1 [01F..020)-> BB31 ( cond ) i BB30 [0029] 1 0.50 [01F..020)-> BB32 (always) i BB31 [0030] 1 0.50 [01F..020) i gcsafe BB32 [0031] 2 1 [01F..020) i BB33 [0032] 1 1 [???..???) internal BB37 [0036] 1 1 [02A..02B)-> BB39 ( cond ) i BB38 [0037] 1 0.50 [02A..02B)-> BB42 (always) i BB39 [0038] 1 0.50 [02A..02B)-> BB41 ( cond ) i BB40 [0039] 1 0.50 [02A..02B)-> BB42 (always) i BB41 [0040] 1 0.50 [02A..02B) i gcsafe BB42 [0041] 3 1 [02A..02B) i BB43 [0042] 1 1 [???..???)-> BB05 ( cond ) internal BB04 [0003] 1 1 [037..03F)-> BB10 (always) i BB05 [0004] 1 1 [03F..054) i gcsafe BB47 [0046] 1 1 [047..048)-> BB49 ( cond ) i BB48 [0047] 1 0.50 [047..048)-> BB52 (always) i BB49 [0048] 1 0.50 [047..048)-> BB51 ( cond ) i BB50 [0049] 1 0.50 [047..048)-> BB52 (always) i BB51 [0050] 1 0.50 [047..048) i gcsafe BB52 [0051] 3 1 [047..048) i BB53 [0052] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [054..05C)-> BB10 (always) i BB07 [0006] 1 1 [05C..069) i BB57 [0056] 1 1 [05C..05D)-> BB59 ( cond ) i BB58 [0057] 1 0.50 [05C..05D)-> BB62 (always) i BB59 [0058] 1 0.50 [05C..05D)-> BB61 ( cond ) i BB60 [0059] 1 0.50 [05C..05D)-> BB62 (always) i BB61 [0060] 1 0.50 [05C..05D) i gcsafe BB62 [0061] 3 1 [05C..05D) i BB63 [0062] 1 1 [???..???)-> BB09 ( cond ) internal BB08 [0007] 1 1 [069..071)-> BB10 (always) i BB09 [0008] 1 1 [071..078)-> BB10 (always) i BB10 [0009] 5 1 [078..07A) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB11 to BB02 Renumber BB12 to BB03 Renumber BB13 to BB04 Renumber BB14 to BB05 Renumber BB15 to BB06 Renumber BB19 to BB07 Renumber BB20 to BB08 Renumber BB21 to BB09 Renumber BB22 to BB10 Renumber BB23 to BB11 Renumber BB24 to BB12 Renumber BB25 to BB13 Renumber BB02 to BB14 Renumber BB03 to BB15 Renumber BB29 to BB16 Renumber BB30 to BB17 Renumber BB31 to BB18 Renumber BB32 to BB19 Renumber BB33 to BB20 Renumber BB37 to BB21 Renumber BB38 to BB22 Renumber BB39 to BB23 Renumber BB40 to BB24 Renumber BB41 to BB25 Renumber BB42 to BB26 Renumber BB43 to BB27 Renumber BB04 to BB28 Renumber BB05 to BB29 Renumber BB47 to BB30 Renumber BB48 to BB31 Renumber BB49 to BB32 Renumber BB50 to BB33 Renumber BB51 to BB34 Renumber BB52 to BB35 Renumber BB53 to BB36 Renumber BB06 to BB37 Renumber BB07 to BB38 Renumber BB57 to BB39 Renumber BB58 to BB40 Renumber BB59 to BB41 Renumber BB60 to BB42 Renumber BB61 to BB43 Renumber BB62 to BB44 Renumber BB63 to BB45 Renumber BB08 to BB46 Renumber BB09 to BB47 Renumber BB10 to BB48 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i BB02 [0010] 1 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 0.50 [001..002) i gcsafe BB05 [0013] 2 1 [001..002) i BB06 [0014] 1 1 [???..???) internal BB07 [0018] 1 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 0.50 [00C..00D)-> BB11 ( cond ) i BB10 [0021] 1 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 0.50 [00C..00D) i gcsafe BB12 [0023] 3 1 [00C..00D) i BB13 [0024] 1 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 1 [01F..037) i BB16 [0028] 1 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 0.50 [01F..020) i gcsafe BB19 [0031] 2 1 [01F..020) i BB20 [0032] 1 1 [???..???) internal BB21 [0036] 1 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 0.50 [02A..02B)-> BB25 ( cond ) i BB24 [0039] 1 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 0.50 [02A..02B) i gcsafe BB26 [0041] 3 1 [02A..02B) i BB27 [0042] 1 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 1 [03F..054) i gcsafe BB30 [0046] 1 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 0.50 [047..048)-> BB34 ( cond ) i BB33 [0049] 1 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 0.50 [047..048) i gcsafe BB35 [0051] 3 1 [047..048) i BB36 [0052] 1 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 1 [05C..069) i BB39 [0056] 1 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 0.50 [05C..05D)-> BB43 ( cond ) i BB42 [0059] 1 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 0.50 [05C..05D) i gcsafe BB44 [0061] 3 1 [05C..05D) i BB45 [0062] 1 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 1 [069..071)-> BB48 (always) i BB47 [0008] 1 1 [071..078)-> BB48 (always) i BB48 [0009] 5 1 [078..07A) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 49, bitset array size: 1 (short) *************** In fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i BB02 [0010] 1 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 0.50 [001..002) i gcsafe BB05 [0013] 2 1 [001..002) i BB06 [0014] 1 1 [???..???) internal BB07 [0018] 1 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 0.50 [00C..00D)-> BB11 ( cond ) i BB10 [0021] 1 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 0.50 [00C..00D) i gcsafe BB12 [0023] 3 1 [00C..00D) i BB13 [0024] 1 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 1 [01F..037) i BB16 [0028] 1 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 0.50 [01F..020) i gcsafe BB19 [0031] 2 1 [01F..020) i BB20 [0032] 1 1 [???..???) internal BB21 [0036] 1 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 0.50 [02A..02B)-> BB25 ( cond ) i BB24 [0039] 1 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 0.50 [02A..02B) i gcsafe BB26 [0041] 3 1 [02A..02B) i BB27 [0042] 1 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 1 [03F..054) i gcsafe BB30 [0046] 1 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 0.50 [047..048)-> BB34 ( cond ) i BB33 [0049] 1 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 0.50 [047..048) i gcsafe BB35 [0051] 3 1 [047..048) i BB36 [0052] 1 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 1 [05C..069) i BB39 [0056] 1 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 0.50 [05C..05D)-> BB43 ( cond ) i BB42 [0059] 1 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 0.50 [05C..05D) i gcsafe BB44 [0061] 3 1 [05C..05D) i BB45 [0062] 1 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 1 [069..071)-> BB48 (always) i BB47 [0008] 1 1 [071..078)-> BB48 (always) i BB48 [0009] 5 1 [078..07A) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i label target BB02 [0010] 1 BB01 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 BB02 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB02 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..002) i label target BB06 [0014] 1 BB05 1 [???..???) internal BB07 [0018] 1 BB06 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 BB07 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB07 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D) i label target BB13 [0024] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 BB13 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB13 1 [01F..037) i label target BB16 [0028] 1 BB15 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 BB16 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB16 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..020) i label target BB20 [0032] 1 BB19 1 [???..???) internal BB21 [0036] 1 BB20 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 BB21 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB21 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B) i label target BB27 [0042] 1 BB26 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 BB27 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB27 1 [03F..054) i label target gcsafe BB30 [0046] 1 BB29 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 BB30 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB30 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048) i label target BB36 [0052] 1 BB35 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 BB36 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB36 1 [05C..069) i label target BB39 [0056] 1 BB38 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 BB39 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB39 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D) i label target BB45 [0062] 1 BB44 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 BB45 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB45 1 [071..078)-> BB48 (always) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgComputeEdgeWeights() fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i label target BB02 [0010] 1 BB01 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 BB02 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB02 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..002) i label target BB06 [0014] 1 BB05 1 [???..???) internal BB07 [0018] 1 BB06 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 BB07 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB07 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D) i label target BB13 [0024] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 BB13 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB13 1 [01F..037) i label target BB16 [0028] 1 BB15 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 BB16 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB16 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..020) i label target BB20 [0032] 1 BB19 1 [???..???) internal BB21 [0036] 1 BB20 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 BB21 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB21 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B) i label target BB27 [0042] 1 BB26 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 BB27 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB27 1 [03F..054) i label target gcsafe BB30 [0046] 1 BB29 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 BB30 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB30 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048) i label target BB36 [0052] 1 BB35 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 BB36 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB36 1 [05C..069) i label target BB39 [0056] 1 BB38 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 BB39 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB39 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D) i label target BB45 [0062] 1 BB44 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 BB45 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB45 1 [071..078)-> BB48 (always) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** In fgCreateFunclets() After fgCreateFunclets() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i label target BB02 [0010] 1 BB01 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 BB02 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB02 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..002) i label target BB06 [0014] 1 BB05 1 [???..???) internal BB07 [0018] 1 BB06 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 BB07 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB07 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D) i label target BB13 [0024] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 BB13 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB13 1 [01F..037) i label target BB16 [0028] 1 BB15 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 BB16 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB16 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..020) i label target BB20 [0032] 1 BB19 1 [???..???) internal BB21 [0036] 1 BB20 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 BB21 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB21 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B) i label target BB27 [0042] 1 BB26 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 BB27 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB27 1 [03F..054) i label target gcsafe BB30 [0046] 1 BB29 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 BB30 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB30 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048) i label target BB36 [0052] 1 BB35 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 BB36 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB36 1 [05C..069) i label target BB39 [0056] 1 BB38 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 BB39 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB39 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D) i label target BB45 [0062] 1 BB44 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 BB45 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB45 1 [071..078)-> BB48 (always) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017) i label target BB02 [0010] 1 BB01 1 [001..002)-> BB04 ( cond ) i BB03 [0011] 1 BB02 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB02 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..002) i label target BB06 [0014] 1 BB05 1 [???..???) internal BB07 [0018] 1 BB06 1 [00C..00D)-> BB09 ( cond ) i BB08 [0019] 1 BB07 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB07 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D) i label target BB13 [0024] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0001] 1 BB13 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB13 1 [01F..037) i label target BB16 [0028] 1 BB15 1 [01F..020)-> BB18 ( cond ) i BB17 [0029] 1 BB16 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB16 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..020) i label target BB20 [0032] 1 BB19 1 [???..???) internal BB21 [0036] 1 BB20 1 [02A..02B)-> BB23 ( cond ) i BB22 [0037] 1 BB21 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB21 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B) i label target BB27 [0042] 1 BB26 1 [???..???)-> BB29 ( cond ) internal BB28 [0003] 1 BB27 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB27 1 [03F..054) i label target gcsafe BB30 [0046] 1 BB29 1 [047..048)-> BB32 ( cond ) i BB31 [0047] 1 BB30 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB30 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048) i label target BB36 [0052] 1 BB35 1 [???..???)-> BB38 ( cond ) internal BB37 [0005] 1 BB36 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB36 1 [05C..069) i label target BB39 [0056] 1 BB38 1 [05C..05D)-> BB41 ( cond ) i BB40 [0057] 1 BB39 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB39 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D) i label target BB45 [0062] 1 BB44 1 [???..???)-> BB47 ( cond ) internal BB46 [0007] 1 BB45 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB45 1 [071..078)-> BB48 (always) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB01 and BB02: *************** In fgDebugCheckBBlist Compacting blocks BB05 and BB06: *************** In fgDebugCheckBBlist Compacting blocks BB05 and BB07: *************** In fgDebugCheckBBlist Compacting blocks BB12 and BB13: *************** In fgDebugCheckBBlist Compacting blocks BB15 and BB16: *************** In fgDebugCheckBBlist Compacting blocks BB19 and BB20: *************** In fgDebugCheckBBlist Compacting blocks BB19 and BB21: *************** In fgDebugCheckBBlist Compacting blocks BB26 and BB27: *************** In fgDebugCheckBBlist Compacting blocks BB29 and BB30: *************** In fgDebugCheckBBlist Compacting blocks BB35 and BB36: *************** In fgDebugCheckBBlist Compacting blocks BB38 and BB39: *************** In fgDebugCheckBBlist Compacting blocks BB44 and BB45: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB47 -> BB48) (converted BB47 to fall-through) After updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB04 ( cond ) i label target BB03 [0011] 1 BB01 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..00D)-> BB09 ( cond ) i label target BB08 [0019] 1 BB05 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB05 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D)-> BB15 ( cond ) i label target BB14 [0001] 1 BB12 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB12 1 [01F..037)-> BB18 ( cond ) i label target BB17 [0029] 1 BB15 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB15 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..02B)-> BB23 ( cond ) i label target BB22 [0037] 1 BB19 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB19 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B)-> BB29 ( cond ) i label target BB28 [0003] 1 BB26 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB26 1 [03F..054)-> BB32 ( cond ) i label target gcsafe BB31 [0047] 1 BB29 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB29 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048)-> BB38 ( cond ) i label target BB37 [0005] 1 BB35 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB35 1 [05C..069)-> BB41 ( cond ) i label target BB40 [0057] 1 BB38 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB38 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D)-> BB47 ( cond ) i label target BB46 [0007] 1 BB44 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB44 1 [071..078) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB04 ( cond ) i label target BB03 [0011] 1 BB01 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..00D)-> BB09 ( cond ) i label target BB08 [0019] 1 BB05 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB05 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D)-> BB15 ( cond ) i label target BB14 [0001] 1 BB12 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB12 1 [01F..037)-> BB18 ( cond ) i label target BB17 [0029] 1 BB15 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB15 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..02B)-> BB23 ( cond ) i label target BB22 [0037] 1 BB19 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB19 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B)-> BB29 ( cond ) i label target BB28 [0003] 1 BB26 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB26 1 [03F..054)-> BB32 ( cond ) i label target gcsafe BB31 [0047] 1 BB29 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB29 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048)-> BB38 ( cond ) i label target BB37 [0005] 1 BB35 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB35 1 [05C..069)-> BB41 ( cond ) i label target BB40 [0057] 1 BB38 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB38 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D)-> BB47 ( cond ) i label target BB46 [0007] 1 BB44 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB44 1 [071..078) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB04 ( cond ) i label target BB03 [0011] 1 BB01 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..00D)-> BB09 ( cond ) i label target BB08 [0019] 1 BB05 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB05 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D)-> BB15 ( cond ) i label target BB14 [0001] 1 BB12 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB12 1 [01F..037)-> BB18 ( cond ) i label target BB17 [0029] 1 BB15 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB15 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..02B)-> BB23 ( cond ) i label target BB22 [0037] 1 BB19 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB19 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B)-> BB29 ( cond ) i label target BB28 [0003] 1 BB26 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB26 1 [03F..054)-> BB32 ( cond ) i label target gcsafe BB31 [0047] 1 BB29 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB29 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048)-> BB38 ( cond ) i label target BB37 [0005] 1 BB35 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB35 1 [05C..069)-> BB41 ( cond ) i label target BB40 [0057] 1 BB38 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB38 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D)-> BB47 ( cond ) i label target BB46 [0007] 1 BB44 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB44 1 [071..078) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB04 ( cond ) i label target BB03 [0011] 1 BB01 0.50 [001..002)-> BB05 (always) i BB04 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB05 [0013] 2 BB03,BB04 1 [001..00D)-> BB09 ( cond ) i label target BB08 [0019] 1 BB05 0.50 [00C..00D)-> BB12 (always) i BB09 [0020] 1 BB05 0.50 [00C..00D)-> BB11 ( cond ) i label target BB10 [0021] 1 BB09 0.50 [00C..00D)-> BB12 (always) i BB11 [0022] 1 BB09 0.50 [00C..00D) i label target gcsafe BB12 [0023] 3 BB08,BB10,BB11 1 [00C..00D)-> BB15 ( cond ) i label target BB14 [0001] 1 BB12 1 [017..01F)-> BB48 (always) i BB15 [0002] 1 BB12 1 [01F..037)-> BB18 ( cond ) i label target BB17 [0029] 1 BB15 0.50 [01F..020)-> BB19 (always) i BB18 [0030] 1 BB15 0.50 [01F..020) i label target gcsafe BB19 [0031] 2 BB17,BB18 1 [01F..02B)-> BB23 ( cond ) i label target BB22 [0037] 1 BB19 0.50 [02A..02B)-> BB26 (always) i BB23 [0038] 1 BB19 0.50 [02A..02B)-> BB25 ( cond ) i label target BB24 [0039] 1 BB23 0.50 [02A..02B)-> BB26 (always) i BB25 [0040] 1 BB23 0.50 [02A..02B) i label target gcsafe BB26 [0041] 3 BB22,BB24,BB25 1 [02A..02B)-> BB29 ( cond ) i label target BB28 [0003] 1 BB26 1 [037..03F)-> BB48 (always) i BB29 [0004] 1 BB26 1 [03F..054)-> BB32 ( cond ) i label target gcsafe BB31 [0047] 1 BB29 0.50 [047..048)-> BB35 (always) i BB32 [0048] 1 BB29 0.50 [047..048)-> BB34 ( cond ) i label target BB33 [0049] 1 BB32 0.50 [047..048)-> BB35 (always) i BB34 [0050] 1 BB32 0.50 [047..048) i label target gcsafe BB35 [0051] 3 BB31,BB33,BB34 1 [047..048)-> BB38 ( cond ) i label target BB37 [0005] 1 BB35 1 [054..05C)-> BB48 (always) i BB38 [0006] 1 BB35 1 [05C..069)-> BB41 ( cond ) i label target BB40 [0057] 1 BB38 0.50 [05C..05D)-> BB44 (always) i BB41 [0058] 1 BB38 0.50 [05C..05D)-> BB43 ( cond ) i label target BB42 [0059] 1 BB41 0.50 [05C..05D)-> BB44 (always) i BB43 [0060] 1 BB41 0.50 [05C..05D) i label target gcsafe BB44 [0061] 3 BB40,BB42,BB43 1 [05C..05D)-> BB47 ( cond ) i label target BB46 [0007] 1 BB44 1 [069..071)-> BB48 (always) i BB47 [0008] 1 BB44 1 [071..078) i label target BB48 [0009] 5 BB14,BB28,BB37,BB46,BB47 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB03 to BB02 Renumber BB04 to BB03 Renumber BB05 to BB04 Renumber BB08 to BB05 Renumber BB09 to BB06 Renumber BB10 to BB07 Renumber BB11 to BB08 Renumber BB12 to BB09 Renumber BB14 to BB10 Renumber BB15 to BB11 Renumber BB17 to BB12 Renumber BB18 to BB13 Renumber BB19 to BB14 Renumber BB22 to BB15 Renumber BB23 to BB16 Renumber BB24 to BB17 Renumber BB25 to BB18 Renumber BB26 to BB19 Renumber BB28 to BB20 Renumber BB29 to BB21 Renumber BB31 to BB22 Renumber BB32 to BB23 Renumber BB33 to BB24 Renumber BB34 to BB25 Renumber BB35 to BB26 Renumber BB37 to BB27 Renumber BB38 to BB28 Renumber BB40 to BB29 Renumber BB41 to BB30 Renumber BB42 to BB31 Renumber BB43 to BB32 Renumber BB44 to BB33 Renumber BB46 to BB34 Renumber BB47 to BB35 Renumber BB48 to BB36 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.50 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.50 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.50 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.50 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.50 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 1 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 1 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.50 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.50 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 1 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.50 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.50 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.50 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.50 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 1 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 1 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 1 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.50 [047..048)-> BB26 (always) i BB23 [0048] 1 BB21 0.50 [047..048)-> BB25 ( cond ) i label target BB24 [0049] 1 BB23 0.50 [047..048)-> BB26 (always) i BB25 [0050] 1 BB23 0.50 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 1 [047..048)-> BB28 ( cond ) i label target BB27 [0005] 1 BB26 1 [054..05C)-> BB36 (always) i BB28 [0006] 1 BB26 1 [05C..069)-> BB30 ( cond ) i label target BB29 [0057] 1 BB28 0.50 [05C..05D)-> BB33 (always) i BB30 [0058] 1 BB28 0.50 [05C..05D)-> BB32 ( cond ) i label target BB31 [0059] 1 BB30 0.50 [05C..05D)-> BB33 (always) i BB32 [0060] 1 BB30 0.50 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 1 [05C..05D)-> BB35 ( cond ) i label target BB34 [0007] 1 BB33 1 [069..071)-> BB36 (always) i BB35 [0008] 1 BB33 1 [071..078) i label target BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 37, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB03 BB04 : BB01 BB02 BB03 BB04 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 : BB01 BB02 BB03 BB04 BB06 BB07 : BB01 BB02 BB03 BB04 BB06 BB07 BB08 : BB01 BB02 BB03 BB04 BB06 BB08 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB13 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB16 BB17 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB16 BB17 BB18 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB16 BB18 BB19 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB23 BB24 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB23 BB24 BB25 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB23 BB25 BB26 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB27 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 BB30 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB32 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB32 BB33 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 BB30 BB31 BB32 BB33 BB34 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 BB30 BB31 BB32 BB33 BB35 BB36 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 After computing reachability: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.50 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.50 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.50 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.50 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.50 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 1 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 1 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.50 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.50 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 1 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.50 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.50 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.50 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.50 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 1 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 1 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 1 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.50 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.50 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.50 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.50 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 1 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 1 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 1 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.50 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.50 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.50 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.50 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 1 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 1 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 1 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB01 BB04: BB04 BB01 BB05: BB05 BB04 BB01 BB06: BB06 BB04 BB01 BB07: BB07 BB06 BB04 BB01 BB08: BB08 BB06 BB04 BB01 BB09: BB09 BB04 BB01 BB10: BB10 BB09 BB04 BB01 BB11: BB11 BB09 BB04 BB01 BB12: BB12 BB11 BB09 BB04 BB01 BB13: BB13 BB11 BB09 BB04 BB01 BB14: BB14 BB11 BB09 BB04 BB01 BB15: BB15 BB14 BB11 BB09 BB04 BB01 BB16: BB16 BB14 BB11 BB09 BB04 BB01 BB17: BB17 BB16 BB14 BB11 BB09 BB04 BB01 BB18: BB18 BB16 BB14 BB11 BB09 BB04 BB01 BB19: BB19 BB14 BB11 BB09 BB04 BB01 BB20: BB20 BB19 BB14 BB11 BB09 BB04 BB01 BB21: BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB22: BB22 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB23: BB23 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB24: BB24 BB23 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB25: BB25 BB23 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB26: BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB27: BB27 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB28: BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB29: BB29 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB30: BB30 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB31: BB31 BB30 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB32: BB32 BB30 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB33: BB33 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB34: BB34 BB33 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB35: BB35 BB33 BB28 BB26 BB21 BB19 BB14 BB11 BB09 BB04 BB01 BB36: BB36 BB09 BB04 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB04 BB03 BB02 BB04 : BB09 BB06 BB05 BB06 : BB08 BB07 BB09 : BB36 BB11 BB10 BB11 : BB14 BB13 BB12 BB14 : BB19 BB16 BB15 BB16 : BB18 BB17 BB19 : BB21 BB20 BB21 : BB26 BB23 BB22 BB23 : BB25 BB24 BB26 : BB28 BB27 BB28 : BB33 BB30 BB29 BB30 : BB32 BB31 BB33 : BB35 BB34 *************** In Allocate Objects Trees before Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.50 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.50 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.50 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.50 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.50 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 1 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 1 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.50 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.50 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 1 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.50 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.50 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.50 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.50 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 1 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 1 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 1 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.50 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.50 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.50 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.50 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 1 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 1 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 1 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.50 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.50 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.50 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.50 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 1 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 1 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 1 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 [000224] ------------ * STMT void (IL 0x001... ???) [000221] -----+------ | /--* CNS_INT int 0 [000223] -A---+------ \--* ASG bool [000222] D----+-N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 2 [000171] ------------ * STMT void (IL 0x001... ???) [000167] -----+------ | /--* CNS_INT ref null [000168] -----+------ | /--* EQ int [000921] -----+------ | | \--* NOP ref [000920] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000170] -A---+------ \--* ASG bool [000169] D----+-N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 3 [000176] ------------ * STMT void (IL 0x001... ???) [000175] -----+------ \--* JTRUE void [000173] -----+------ | /--* CNS_INT int 0 [000174] J----+-N---- \--* EQ int [000172] -----+------ \--* LCL_VAR int V09 tmp0 ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 4 [000215] ------------ * STMT void (IL 0x001... ???) [000926] ------------ | /--* CNS_INT int 0 [000927] -A---------- | /--* ASG int [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 [000928] -A---+------ \--* COMMA void [000923] ------------ | /--* CNS_INT byref 0 [000924] -A---------- \--* ASG byref [000922] D------N---- \--* LCL_VAR byref V69 tmp60 ***** BB02, stmt 5 [000220] ------------ * STMT void (IL 0x001... ???) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 [000934] -A---------- | /--* ASG int [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 [000935] -A---+------ \--* COMMA void [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 [000931] -A---------- \--* ASG byref [000929] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 6 [000187] ------------ * STMT void (IL 0x001... ???) [000944] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [000945] -----+------ | /--* ADD byref [000943] -----+------ | | \--* LCL_VAR ref V96 tmp87 [000946] -A-XG+-N---- | /--* COMMA byref [000941] ---X-+-N---- | | | /--* NULLCHECK byte [000940] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [000949] -A-X-------- | | \--* COMMA void [000948] -----+------ | | | /--* NOP ref [000947] -----+------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000939] -A---+------ | | \--* ASG ref [000938] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000186] -A-XG+------ \--* ASG byref [000185] D----+-N---- \--* LCL_VAR byref V10 tmp1 ***** BB03, stmt 7 [000247] ------------ * STMT void (IL 0x001... ???) [000244] -----+------ | /--* CNS_INT int 0 [000246] -A---+------ \--* ASG int [000245] D----+-N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 8 [000239] ------------ * STMT void (IL 0x001... ???) [000236] x---G+------ | /--* IND int [000953] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [000954] -----+------ | | \--* ADD byref [000956] -----+------ | | \--* NOP ref [000955] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000238] -A--G+------ \--* ASG int [000237] D----+-N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 9 [000193] ------------ * STMT void (IL 0x001... ???) [000961] ------------ | /--* CNS_INT int 0 [000962] -A---------- | /--* ASG int [000960] D------N---- | | \--* LCL_VAR int V66 tmp57 [000963] -A---+------ \--* COMMA void [000958] ------------ | /--* CNS_INT byref 0 [000959] -A---------- \--* ASG byref [000957] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 10 [000256] ------------ * STMT void (IL 0x001... ???) [000254] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000250] -----+------ | /--* CNS_INT int 0 [000251] -----+------ arg0 in rcx \--* GE int [000240] -----+------ \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 11 [000262] ------------ * STMT void (IL 0x001... ???) [000967] ------------ | /--* CNS_INT byref 0 [000968] -A---+------ \--* ASG byref [000966] D------N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 12 [000268] ------------ * STMT void (IL 0x001... ???) [000188] -----+------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---+------ \--* ASG byref [000265] D----+-N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 13 [000273] ------------ * STMT void (IL 0x001... ???) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 [000971] -A---+------ \--* ASG byref [000969] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 14 [000279] ------------ * STMT void (IL 0x001... ???) [000276] -----+------ | /--* LCL_VAR int V14 tmp5 [000278] -A---+------ \--* ASG int [000277] D----+-N---- \--* LCL_VAR int V66 tmp57 ***** BB03, stmt 15 [000204] ------------ * STMT void (IL 0x001... ???) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 [000977] -A---------- | /--* ASG int [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 [000978] -A---+------ \--* COMMA void [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 [000974] -A---------- \--* ASG byref [000972] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 16 [000009] ------------ * STMT void (IL ???... ???) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 [000984] -A---------- | /--* ASG int [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 [000985] -A---+------ \--* COMMA void [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 [000981] -A---------- \--* ASG byref [000979] D------N---- \--* LCL_VAR byref V61 tmp52 ***** BB04, stmt 17 [000355] ------------ * STMT void (IL 0x00C... ???) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 [000991] -A---------- | /--* ASG int [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 [000992] -A---+------ \--* COMMA void [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 [000988] -A---------- \--* ASG byref [000986] D------N---- \--* LCL_VAR byref V72 tmp63 ***** BB04, stmt 18 [000359] ------------ * STMT void (IL 0x00C... ???) [001004] x----------- | /--* IND int [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001003] ------------ | | \--* ADD byref [001001] ------------ | | \--* LCL_VAR byref V00 arg0 [001005] -A---------- | /--* ASG int [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 [001006] -A---+------ \--* COMMA void [000998] x----------- | /--* IND byref [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000997] ------------ | | \--* ADD byref [000995] ------------ | | \--* LCL_VAR byref V00 arg0 [000999] -A---------- \--* ASG byref [000994] D------N---- \--* LCL_VAR byref V74 tmp65 ***** BB04, stmt 19 [000363] ------------ * STMT void (IL 0x00C... ???) [000360] -----+------ | /--* CNS_INT int 0 [000362] -A---+------ \--* ASG bool [000361] D----+-N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 20 [000367] ------------ * STMT void (IL 0x00C... ???) [000364] -----+------ | /--* CNS_INT int 0 [000366] -A---+------ \--* ASG bool [000365] D----+-N---- \--* LCL_VAR int V21 tmp12 ***** BB04, stmt 21 [000371] ------------ * STMT void (IL 0x00C... ???) [000368] -----+------ | /--* CNS_INT int 0 [000370] -A---+------ \--* ASG bool [000369] D----+-N---- \--* LCL_VAR int V20 tmp11 ***** BB04, stmt 22 [000384] ------------ * STMT void (IL 0x00C... ???) [000381] -----+------ | /--* CNS_INT int 0 [000383] -A---+------ \--* ASG int [000382] D----+-N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 23 [000379] ------------ * STMT void (IL 0x00C... ???) [000376] -----+------ | /--* LCL_VAR int V73 tmp64 [000378] -A---+------ \--* ASG int [000377] D----+-N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 24 [000294] ------------ * STMT void (IL 0x00C... ???) [000380] -----+------ | /--* LCL_VAR int V73 tmp64 [000293] -A---+------ \--* ASG int [000292] D----+-N---- \--* LCL_VAR int V18 tmp9 ***** BB04, stmt 25 [000397] ------------ * STMT void (IL 0x00C... ???) [000394] -----+------ | /--* CNS_INT int 0 [000396] -A---+------ \--* ASG int [000395] D----+-N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 26 [000392] ------------ * STMT void (IL 0x00C... ???) [000389] -----+------ | /--* LCL_VAR int V75 tmp66 [000391] -A---+------ \--* ASG int [000390] D----+-N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 27 [000302] ------------ * STMT void (IL 0x00C... ???) [000393] -----+------ | /--* LCL_VAR int V75 tmp66 [000297] -----+------ | /--* NE int [000295] -----+------ | | \--* LCL_VAR int V73 tmp64 [000301] -A---+------ \--* ASG bool [000300] D----+-N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 28 [000307] ------------ * STMT void (IL 0x00C... ???) [000306] -----+------ \--* JTRUE void [000304] -----+------ | /--* CNS_INT int 0 [000305] J----+-N---- \--* EQ int [000303] -----+------ \--* LCL_VAR int V19 tmp10 ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 29 [000351] ------------ * STMT void (IL 0x00C... ???) [000348] -----+------ | /--* CNS_INT int 0 [000350] -A---+------ \--* ASG bool [000349] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 30 [000410] ------------ * STMT void (IL 0x00C... ???) [000407] -----+------ | /--* CNS_INT int 0 [000409] -A---+------ \--* ASG int [000408] D----+-N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 31 [000405] ------------ * STMT void (IL 0x00C... ???) [000402] -----+------ | /--* LCL_VAR int V75 tmp66 [000404] -A---+------ \--* ASG int [000403] D----+-N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 32 [000318] ------------ * STMT void (IL 0x00C... ???) [000314] -----+------ | /--* CNS_INT int 0 [000315] -----+------ | /--* EQ int [000406] -----+------ | | \--* LCL_VAR int V75 tmp66 [000317] -A---+------ \--* ASG bool [000316] D----+-N---- \--* LCL_VAR int V20 tmp11 ***** BB06, stmt 33 [000323] ------------ * STMT void (IL 0x00C... ???) [000322] -----+------ \--* JTRUE void [000320] -----+------ | /--* CNS_INT int 0 [000321] J----+-N---- \--* EQ int [000319] -----+------ \--* LCL_VAR int V20 tmp11 ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 34 [000346] ------------ * STMT void (IL 0x00C... ???) [000343] -----+------ | /--* CNS_INT int 1 [000345] -A---+------ \--* ASG bool [000344] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 35 [000338] ------------ * STMT void (IL 0x00C... ???) [000334] -----+------ | /--* CNS_INT int 0 [000335] -ACXG+------ | /--* EQ int [000327] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001029] *------N---- | | | | \--* IND int [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001028] ------------ | | | | \--* ADD byref [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 [001032] -A---+----L- arg0 SETUP | | +--* COMMA void [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001022] *------N---- | | | | | \--* IND byref [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001021] ------------ | | | | | \--* ADD byref [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 [001025] -A---------- | | | \--* COMMA void [001015] L----------- | | | | /--* ADDR byref [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001018] -A---------- | | | \--* ASG byref [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001050] *------N---- | | | | \--* IND int [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001049] ------------ | | | | \--* ADD byref [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 [001053] -A---+----L- arg1 SETUP | | +--* COMMA void [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001043] *------N---- | | | | | \--* IND byref [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001042] ------------ | | | | | \--* ADD byref [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 [001046] -A---------- | | | \--* COMMA void [001036] L----------- | | | | /--* ADDR byref [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001039] -A---------- | | | \--* ASG byref [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 [001055] L----------- arg0 in rcx | | +--* ADDR byref [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001058] L----------- arg1 in rdx | | \--* ADDR byref [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000337] -ACXG+------ \--* ASG bool [000336] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 36 [000024] ------------ * STMT void (IL ???... ???) [000340] -----+------ | /--* LCL_VAR int V21 tmp12 [000023] -A---+------ \--* ASG int [000022] D----+-N---- \--* LCL_VAR int V04 loc2 ***** BB09, stmt 37 [000029] ------------ * STMT void (IL 0x014...0x015) [000028] -----+------ \--* JTRUE void [000026] -----+------ | /--* CNS_INT int 0 [000027] J----+-N---- \--* EQ int [000025] -----+------ \--* LCL_VAR int V21 tmp12 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 38 [000160] ------------ * STMT void (IL 0x018...0x01A) [000157] -----+------ | /--* CNS_INT int 1 [000159] -A-XG+------ \--* ASG byte [000158] *--X-+-N---- \--* IND byte [000156] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB10, stmt 39 [000164] ------------ * STMT void (IL 0x01B...0x01C) [000161] -----+------ | /--* CNS_INT int 1 [000163] -A---+------ \--* ASG int [000162] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 40 [000471] ------------ * STMT void (IL 0x01F... ???) [000468] -----+------ | /--* CNS_INT int 0 [000470] -A---+------ \--* ASG bool [000469] D----+-N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 41 [000418] ------------ * STMT void (IL 0x01F... ???) [000414] -----+------ | /--* CNS_INT ref null [000415] -----+------ | /--* EQ int [001063] -----+------ | | \--* NOP ref [001062] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000417] -A---+------ \--* ASG bool [000416] D----+-N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 42 [000423] ------------ * STMT void (IL 0x01F... ???) [000422] -----+------ \--* JTRUE void [000420] -----+------ | /--* CNS_INT int 0 [000421] J----+-N---- \--* EQ int [000419] -----+------ \--* LCL_VAR int V25 tmp16 ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 43 [000462] ------------ * STMT void (IL 0x01F... ???) [001068] ------------ | /--* CNS_INT int 0 [001069] -A---------- | /--* ASG int [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 [001070] -A---+------ \--* COMMA void [001065] ------------ | /--* CNS_INT byref 0 [001066] -A---------- \--* ASG byref [001064] D------N---- \--* LCL_VAR byref V80 tmp71 ***** BB12, stmt 44 [000467] ------------ * STMT void (IL 0x01F... ???) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 [001076] -A---------- | /--* ASG int [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 [001077] -A---+------ \--* COMMA void [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 [001073] -A---------- \--* ASG byref [001071] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 45 [000434] ------------ * STMT void (IL 0x01F... ???) [001086] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [001087] -----+------ | /--* ADD byref [001085] -----+------ | | \--* LCL_VAR ref V96 tmp87 [001088] -A-XG+-N---- | /--* COMMA byref [001083] ---X-+-N---- | | | /--* NULLCHECK byte [001082] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [001091] -A-X-------- | | \--* COMMA void [001090] -----+------ | | | /--* NOP ref [001089] -----+------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [001081] -A---+------ | | \--* ASG ref [001080] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000433] -A-XG+------ \--* ASG byref [000432] D----+-N---- \--* LCL_VAR byref V26 tmp17 ***** BB13, stmt 46 [000494] ------------ * STMT void (IL 0x01F... ???) [000491] -----+------ | /--* CNS_INT int 0 [000493] -A---+------ \--* ASG int [000492] D----+-N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 47 [000486] ------------ * STMT void (IL 0x01F... ???) [000483] x---G+------ | /--* IND int [001095] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [001096] -----+------ | | \--* ADD byref [001098] -----+------ | | \--* NOP ref [001097] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000485] -A--G+------ \--* ASG int [000484] D----+-N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 48 [000440] ------------ * STMT void (IL 0x01F... ???) [001103] ------------ | /--* CNS_INT int 0 [001104] -A---------- | /--* ASG int [001102] D------N---- | | \--* LCL_VAR int V77 tmp68 [001105] -A---+------ \--* COMMA void [001100] ------------ | /--* CNS_INT byref 0 [001101] -A---------- \--* ASG byref [001099] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 49 [000503] ------------ * STMT void (IL 0x01F... ???) [000501] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000497] -----+------ | /--* CNS_INT int 0 [000498] -----+------ arg0 in rcx \--* GE int [000487] -----+------ \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 50 [000509] ------------ * STMT void (IL 0x01F... ???) [001109] ------------ | /--* CNS_INT byref 0 [001110] -A---+------ \--* ASG byref [001108] D------N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 51 [000515] ------------ * STMT void (IL 0x01F... ???) [000435] -----+------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---+------ \--* ASG byref [000512] D----+-N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 52 [000520] ------------ * STMT void (IL 0x01F... ???) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 [001113] -A---+------ \--* ASG byref [001111] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 53 [000526] ------------ * STMT void (IL 0x01F... ???) [000523] -----+------ | /--* LCL_VAR int V30 tmp21 [000525] -A---+------ \--* ASG int [000524] D----+-N---- \--* LCL_VAR int V77 tmp68 ***** BB13, stmt 54 [000451] ------------ * STMT void (IL 0x01F... ???) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 [001119] -A---------- | /--* ASG int [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 [001120] -A---+------ \--* COMMA void [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 [001116] -A---------- \--* ASG byref [001114] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 55 [000039] ------------ * STMT void (IL ???... ???) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 [001126] -A---------- | /--* ASG int [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 [001127] -A---+------ \--* COMMA void [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 [001123] -A---------- \--* ASG byref [001121] D------N---- \--* LCL_VAR byref V63 tmp54 ***** BB14, stmt 56 [000602] ------------ * STMT void (IL 0x02A... ???) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 [001133] -A---------- | /--* ASG int [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 [001134] -A---+------ \--* COMMA void [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 [001130] -A---------- \--* ASG byref [001128] D------N---- \--* LCL_VAR byref V83 tmp74 ***** BB14, stmt 57 [000606] ------------ * STMT void (IL 0x02A... ???) [001146] x----------- | /--* IND int [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001145] ------------ | | \--* ADD byref [001143] ------------ | | \--* LCL_VAR byref V00 arg0 [001147] -A---------- | /--* ASG int [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 [001148] -A---+------ \--* COMMA void [001140] x----------- | /--* IND byref [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001139] ------------ | | \--* ADD byref [001137] ------------ | | \--* LCL_VAR byref V00 arg0 [001141] -A---------- \--* ASG byref [001136] D------N---- \--* LCL_VAR byref V85 tmp76 ***** BB14, stmt 58 [000610] ------------ * STMT void (IL 0x02A... ???) [000607] -----+------ | /--* CNS_INT int 0 [000609] -A---+------ \--* ASG bool [000608] D----+-N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 59 [000614] ------------ * STMT void (IL 0x02A... ???) [000611] -----+------ | /--* CNS_INT int 0 [000613] -A---+------ \--* ASG bool [000612] D----+-N---- \--* LCL_VAR int V37 tmp28 ***** BB14, stmt 60 [000618] ------------ * STMT void (IL 0x02A... ???) [000615] -----+------ | /--* CNS_INT int 0 [000617] -A---+------ \--* ASG bool [000616] D----+-N---- \--* LCL_VAR int V36 tmp27 ***** BB14, stmt 61 [000631] ------------ * STMT void (IL 0x02A... ???) [000628] -----+------ | /--* CNS_INT int 0 [000630] -A---+------ \--* ASG int [000629] D----+-N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 62 [000626] ------------ * STMT void (IL 0x02A... ???) [000623] -----+------ | /--* LCL_VAR int V84 tmp75 [000625] -A---+------ \--* ASG int [000624] D----+-N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 63 [000541] ------------ * STMT void (IL 0x02A... ???) [000627] -----+------ | /--* LCL_VAR int V84 tmp75 [000540] -A---+------ \--* ASG int [000539] D----+-N---- \--* LCL_VAR int V34 tmp25 ***** BB14, stmt 64 [000644] ------------ * STMT void (IL 0x02A... ???) [000641] -----+------ | /--* CNS_INT int 0 [000643] -A---+------ \--* ASG int [000642] D----+-N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 65 [000639] ------------ * STMT void (IL 0x02A... ???) [000636] -----+------ | /--* LCL_VAR int V86 tmp77 [000638] -A---+------ \--* ASG int [000637] D----+-N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 66 [000549] ------------ * STMT void (IL 0x02A... ???) [000640] -----+------ | /--* LCL_VAR int V86 tmp77 [000544] -----+------ | /--* NE int [000542] -----+------ | | \--* LCL_VAR int V84 tmp75 [000548] -A---+------ \--* ASG bool [000547] D----+-N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 67 [000554] ------------ * STMT void (IL 0x02A... ???) [000553] -----+------ \--* JTRUE void [000551] -----+------ | /--* CNS_INT int 0 [000552] J----+-N---- \--* EQ int [000550] -----+------ \--* LCL_VAR int V35 tmp26 ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 68 [000598] ------------ * STMT void (IL 0x02A... ???) [000595] -----+------ | /--* CNS_INT int 0 [000597] -A---+------ \--* ASG bool [000596] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 69 [000657] ------------ * STMT void (IL 0x02A... ???) [000654] -----+------ | /--* CNS_INT int 0 [000656] -A---+------ \--* ASG int [000655] D----+-N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 70 [000652] ------------ * STMT void (IL 0x02A... ???) [000649] -----+------ | /--* LCL_VAR int V86 tmp77 [000651] -A---+------ \--* ASG int [000650] D----+-N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 71 [000565] ------------ * STMT void (IL 0x02A... ???) [000561] -----+------ | /--* CNS_INT int 0 [000562] -----+------ | /--* EQ int [000653] -----+------ | | \--* LCL_VAR int V86 tmp77 [000564] -A---+------ \--* ASG bool [000563] D----+-N---- \--* LCL_VAR int V36 tmp27 ***** BB16, stmt 72 [000570] ------------ * STMT void (IL 0x02A... ???) [000569] -----+------ \--* JTRUE void [000567] -----+------ | /--* CNS_INT int 0 [000568] J----+-N---- \--* EQ int [000566] -----+------ \--* LCL_VAR int V36 tmp27 ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 73 [000593] ------------ * STMT void (IL 0x02A... ???) [000590] -----+------ | /--* CNS_INT int 1 [000592] -A---+------ \--* ASG bool [000591] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 74 [000585] ------------ * STMT void (IL 0x02A... ???) [000581] -----+------ | /--* CNS_INT int 0 [000582] -ACXG+------ | /--* EQ int [000574] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001171] *------N---- | | | | \--* IND int [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001170] ------------ | | | | \--* ADD byref [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 [001174] -A---+----L- arg0 SETUP | | +--* COMMA void [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001164] *------N---- | | | | | \--* IND byref [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001163] ------------ | | | | | \--* ADD byref [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 [001167] -A---------- | | | \--* COMMA void [001157] L----------- | | | | /--* ADDR byref [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001160] -A---------- | | | \--* ASG byref [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001192] *------N---- | | | | \--* IND int [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001191] ------------ | | | | \--* ADD byref [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 [001195] -A---+----L- arg1 SETUP | | +--* COMMA void [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001185] *------N---- | | | | | \--* IND byref [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001184] ------------ | | | | | \--* ADD byref [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 [001188] -A---------- | | | \--* COMMA void [001178] L----------- | | | | /--* ADDR byref [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001181] -A---------- | | | \--* ASG byref [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 [001197] L----------- arg0 in rcx | | +--* ADDR byref [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001200] L----------- arg1 in rdx | | \--* ADDR byref [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000584] -ACXG+------ \--* ASG bool [000583] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 75 [000054] ------------ * STMT void (IL ???... ???) [000587] -----+------ | /--* LCL_VAR int V37 tmp28 [000053] -A---+------ \--* ASG int [000052] D----+-N---- \--* LCL_VAR int V06 loc4 ***** BB19, stmt 76 [000059] ------------ * STMT void (IL 0x033...0x035) [000058] -----+------ \--* JTRUE void [000056] -----+------ | /--* CNS_INT int 0 [000057] J----+-N---- \--* EQ int [000055] -----+------ \--* LCL_VAR int V37 tmp28 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 77 [000150] ------------ * STMT void (IL 0x038...0x03A) [000147] -----+------ | /--* CNS_INT int 0 [000149] -A-XG+------ \--* ASG byte [000148] *--X-+-N---- \--* IND byte [000146] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB20, stmt 78 [000154] ------------ * STMT void (IL 0x03B...0x03C) [000151] -----+------ | /--* CNS_INT int 1 [000153] -A---+------ \--* ASG int [000152] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 79 [000069] ------------ * STMT void (IL 0x03F...0x045) [000062] SACXG+------ \--* CALL void System.Boolean.TrimWhiteSpaceAndNull [000066] -----+------ | /--* LCL_VAR byref V00 arg0 [001206] -A--------L- arg0 SETUP +--* ASG byref [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 [000064] x----+-N---- | /--* IND struct [000061] -----+------ | | \--* LCL_VAR byref V00 arg0 [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 [001210] L----------- arg1 in rdx \--* ADDR byref [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 ***** BB21, stmt 80 [000732] ------------ * STMT void (IL 0x047... ???) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 [001217] -A---------- | /--* ASG int [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 [001218] -A---+------ \--* COMMA void [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 [001214] -A---------- \--* ASG byref [001212] D------N---- \--* LCL_VAR byref V87 tmp78 ***** BB21, stmt 81 [000736] ------------ * STMT void (IL 0x047... ???) [001230] x----------- | /--* IND int [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001229] ------------ | | \--* ADD byref [001227] ------------ | | \--* LCL_VAR byref V00 arg0 [001231] -A---------- | /--* ASG int [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 [001232] -A---+------ \--* COMMA void [001224] x----------- | /--* IND byref [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001223] ------------ | | \--* ADD byref [001221] ------------ | | \--* LCL_VAR byref V00 arg0 [001225] -A---------- \--* ASG byref [001220] D------N---- \--* LCL_VAR byref V89 tmp80 ***** BB21, stmt 82 [000740] ------------ * STMT void (IL 0x047... ???) [000737] -----+------ | /--* CNS_INT int 0 [000739] -A---+------ \--* ASG bool [000738] D----+-N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 83 [000744] ------------ * STMT void (IL 0x047... ???) [000741] -----+------ | /--* CNS_INT int 0 [000743] -A---+------ \--* ASG bool [000742] D----+-N---- \--* LCL_VAR int V46 tmp37 ***** BB21, stmt 84 [000748] ------------ * STMT void (IL 0x047... ???) [000745] -----+------ | /--* CNS_INT int 0 [000747] -A---+------ \--* ASG bool [000746] D----+-N---- \--* LCL_VAR int V45 tmp36 ***** BB21, stmt 85 [000761] ------------ * STMT void (IL 0x047... ???) [000758] -----+------ | /--* CNS_INT int 0 [000760] -A---+------ \--* ASG int [000759] D----+-N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 86 [000756] ------------ * STMT void (IL 0x047... ???) [000753] -----+------ | /--* LCL_VAR int V88 tmp79 [000755] -A---+------ \--* ASG int [000754] D----+-N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 87 [000671] ------------ * STMT void (IL 0x047... ???) [000757] -----+------ | /--* LCL_VAR int V88 tmp79 [000670] -A---+------ \--* ASG int [000669] D----+-N---- \--* LCL_VAR int V43 tmp34 ***** BB21, stmt 88 [000774] ------------ * STMT void (IL 0x047... ???) [000771] -----+------ | /--* CNS_INT int 0 [000773] -A---+------ \--* ASG int [000772] D----+-N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 89 [000769] ------------ * STMT void (IL 0x047... ???) [000766] -----+------ | /--* LCL_VAR int V90 tmp81 [000768] -A---+------ \--* ASG int [000767] D----+-N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 90 [000679] ------------ * STMT void (IL 0x047... ???) [000770] -----+------ | /--* LCL_VAR int V90 tmp81 [000674] -----+------ | /--* NE int [000672] -----+------ | | \--* LCL_VAR int V88 tmp79 [000678] -A---+------ \--* ASG bool [000677] D----+-N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 91 [000684] ------------ * STMT void (IL 0x047... ???) [000683] -----+------ \--* JTRUE void [000681] -----+------ | /--* CNS_INT int 0 [000682] J----+-N---- \--* EQ int [000680] -----+------ \--* LCL_VAR int V44 tmp35 ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 92 [000728] ------------ * STMT void (IL 0x047... ???) [000725] -----+------ | /--* CNS_INT int 0 [000727] -A---+------ \--* ASG bool [000726] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 93 [000787] ------------ * STMT void (IL 0x047... ???) [000784] -----+------ | /--* CNS_INT int 0 [000786] -A---+------ \--* ASG int [000785] D----+-N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 94 [000782] ------------ * STMT void (IL 0x047... ???) [000779] -----+------ | /--* LCL_VAR int V90 tmp81 [000781] -A---+------ \--* ASG int [000780] D----+-N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 95 [000695] ------------ * STMT void (IL 0x047... ???) [000691] -----+------ | /--* CNS_INT int 0 [000692] -----+------ | /--* EQ int [000783] -----+------ | | \--* LCL_VAR int V90 tmp81 [000694] -A---+------ \--* ASG bool [000693] D----+-N---- \--* LCL_VAR int V45 tmp36 ***** BB23, stmt 96 [000700] ------------ * STMT void (IL 0x047... ???) [000699] -----+------ \--* JTRUE void [000697] -----+------ | /--* CNS_INT int 0 [000698] J----+-N---- \--* EQ int [000696] -----+------ \--* LCL_VAR int V45 tmp36 ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 97 [000723] ------------ * STMT void (IL 0x047... ???) [000720] -----+------ | /--* CNS_INT int 1 [000722] -A---+------ \--* ASG bool [000721] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 98 [000715] ------------ * STMT void (IL 0x047... ???) [000711] -----+------ | /--* CNS_INT int 0 [000712] -ACXG+------ | /--* EQ int [000704] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001255] *------N---- | | | | \--* IND int [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001254] ------------ | | | | \--* ADD byref [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 [001258] -A---+----L- arg0 SETUP | | +--* COMMA void [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001248] *------N---- | | | | | \--* IND byref [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001247] ------------ | | | | | \--* ADD byref [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 [001251] -A---------- | | | \--* COMMA void [001241] L----------- | | | | /--* ADDR byref [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001244] -A---------- | | | \--* ASG byref [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001276] *------N---- | | | | \--* IND int [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001275] ------------ | | | | \--* ADD byref [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 [001279] -A---+----L- arg1 SETUP | | +--* COMMA void [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001269] *------N---- | | | | | \--* IND byref [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001268] ------------ | | | | | \--* ADD byref [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 [001272] -A---------- | | | \--* COMMA void [001262] L----------- | | | | /--* ADDR byref [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001265] -A---------- | | | \--* ASG byref [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 [001281] L----------- arg0 in rcx | | +--* ADDR byref [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001284] L----------- arg1 in rdx | | \--* ADDR byref [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000714] -ACXG+------ \--* ASG bool [000713] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 99 [000084] ------------ * STMT void (IL ???... ???) [000717] -----+------ | /--* LCL_VAR int V46 tmp37 [000083] -A---+------ \--* ASG int [000082] D----+-N---- \--* LCL_VAR int V07 loc5 ***** BB26, stmt 100 [000089] ------------ * STMT void (IL 0x050...0x052) [000088] -----+------ \--* JTRUE void [000086] -----+------ | /--* CNS_INT int 0 [000087] J----+-N---- \--* EQ int [000085] -----+------ \--* LCL_VAR int V46 tmp37 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 101 [000140] ------------ * STMT void (IL 0x055...0x057) [000137] -----+------ | /--* CNS_INT int 1 [000139] -A-XG+------ \--* ASG byte [000138] *--X-+-N---- \--* IND byte [000136] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB27, stmt 102 [000144] ------------ * STMT void (IL 0x058...0x059) [000141] -----+------ | /--* CNS_INT int 1 [000143] -A---+------ \--* ASG int [000142] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 103 [000862] ------------ * STMT void (IL 0x05C... ???) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 [001292] -A---------- | /--* ASG int [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 [001293] -A---+------ \--* COMMA void [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 [001289] -A---------- \--* ASG byref [001287] D------N---- \--* LCL_VAR byref V91 tmp82 ***** BB28, stmt 104 [000866] ------------ * STMT void (IL 0x05C... ???) [001305] x----------- | /--* IND int [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001304] ------------ | | \--* ADD byref [001302] ------------ | | \--* LCL_VAR byref V00 arg0 [001306] -A---------- | /--* ASG int [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 [001307] -A---+------ \--* COMMA void [001299] x----------- | /--* IND byref [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001298] ------------ | | \--* ADD byref [001296] ------------ | | \--* LCL_VAR byref V00 arg0 [001300] -A---------- \--* ASG byref [001295] D------N---- \--* LCL_VAR byref V93 tmp84 ***** BB28, stmt 105 [000870] ------------ * STMT void (IL 0x05C... ???) [000867] -----+------ | /--* CNS_INT int 0 [000869] -A---+------ \--* ASG bool [000868] D----+-N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 106 [000874] ------------ * STMT void (IL 0x05C... ???) [000871] -----+------ | /--* CNS_INT int 0 [000873] -A---+------ \--* ASG bool [000872] D----+-N---- \--* LCL_VAR int V55 tmp46 ***** BB28, stmt 107 [000878] ------------ * STMT void (IL 0x05C... ???) [000875] -----+------ | /--* CNS_INT int 0 [000877] -A---+------ \--* ASG bool [000876] D----+-N---- \--* LCL_VAR int V54 tmp45 ***** BB28, stmt 108 [000891] ------------ * STMT void (IL 0x05C... ???) [000888] -----+------ | /--* CNS_INT int 0 [000890] -A---+------ \--* ASG int [000889] D----+-N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 109 [000886] ------------ * STMT void (IL 0x05C... ???) [000883] -----+------ | /--* LCL_VAR int V92 tmp83 [000885] -A---+------ \--* ASG int [000884] D----+-N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 110 [000801] ------------ * STMT void (IL 0x05C... ???) [000887] -----+------ | /--* LCL_VAR int V92 tmp83 [000800] -A---+------ \--* ASG int [000799] D----+-N---- \--* LCL_VAR int V52 tmp43 ***** BB28, stmt 111 [000904] ------------ * STMT void (IL 0x05C... ???) [000901] -----+------ | /--* CNS_INT int 0 [000903] -A---+------ \--* ASG int [000902] D----+-N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 112 [000899] ------------ * STMT void (IL 0x05C... ???) [000896] -----+------ | /--* LCL_VAR int V94 tmp85 [000898] -A---+------ \--* ASG int [000897] D----+-N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 113 [000809] ------------ * STMT void (IL 0x05C... ???) [000900] -----+------ | /--* LCL_VAR int V94 tmp85 [000804] -----+------ | /--* NE int [000802] -----+------ | | \--* LCL_VAR int V92 tmp83 [000808] -A---+------ \--* ASG bool [000807] D----+-N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 114 [000814] ------------ * STMT void (IL 0x05C... ???) [000813] -----+------ \--* JTRUE void [000811] -----+------ | /--* CNS_INT int 0 [000812] J----+-N---- \--* EQ int [000810] -----+------ \--* LCL_VAR int V53 tmp44 ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 115 [000858] ------------ * STMT void (IL 0x05C... ???) [000855] -----+------ | /--* CNS_INT int 0 [000857] -A---+------ \--* ASG bool [000856] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 116 [000917] ------------ * STMT void (IL 0x05C... ???) [000914] -----+------ | /--* CNS_INT int 0 [000916] -A---+------ \--* ASG int [000915] D----+-N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 117 [000912] ------------ * STMT void (IL 0x05C... ???) [000909] -----+------ | /--* LCL_VAR int V94 tmp85 [000911] -A---+------ \--* ASG int [000910] D----+-N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 118 [000825] ------------ * STMT void (IL 0x05C... ???) [000821] -----+------ | /--* CNS_INT int 0 [000822] -----+------ | /--* EQ int [000913] -----+------ | | \--* LCL_VAR int V94 tmp85 [000824] -A---+------ \--* ASG bool [000823] D----+-N---- \--* LCL_VAR int V54 tmp45 ***** BB30, stmt 119 [000830] ------------ * STMT void (IL 0x05C... ???) [000829] -----+------ \--* JTRUE void [000827] -----+------ | /--* CNS_INT int 0 [000828] J----+-N---- \--* EQ int [000826] -----+------ \--* LCL_VAR int V54 tmp45 ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 120 [000853] ------------ * STMT void (IL 0x05C... ???) [000850] -----+------ | /--* CNS_INT int 1 [000852] -A---+------ \--* ASG bool [000851] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 121 [000845] ------------ * STMT void (IL 0x05C... ???) [000841] -----+------ | /--* CNS_INT int 0 [000842] -ACXG+------ | /--* EQ int [000834] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001330] *------N---- | | | | \--* IND int [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001329] ------------ | | | | \--* ADD byref [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 [001333] -A---+----L- arg0 SETUP | | +--* COMMA void [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001323] *------N---- | | | | | \--* IND byref [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001322] ------------ | | | | | \--* ADD byref [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 [001326] -A---------- | | | \--* COMMA void [001316] L----------- | | | | /--* ADDR byref [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001319] -A---------- | | | \--* ASG byref [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001351] *------N---- | | | | \--* IND int [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001350] ------------ | | | | \--* ADD byref [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 [001354] -A---+----L- arg1 SETUP | | +--* COMMA void [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001344] *------N---- | | | | | \--* IND byref [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001343] ------------ | | | | | \--* ADD byref [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 [001347] -A---------- | | | \--* COMMA void [001337] L----------- | | | | /--* ADDR byref [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001340] -A---------- | | | \--* ASG byref [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 [001356] L----------- arg0 in rcx | | +--* ADDR byref [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001359] L----------- arg1 in rdx | | \--* ADDR byref [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000844] -ACXG+------ \--* ASG bool [000843] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 122 [000105] ------------ * STMT void (IL ???... ???) [000847] -----+------ | /--* LCL_VAR int V55 tmp46 [000104] -A---+------ \--* ASG int [000103] D----+-N---- \--* LCL_VAR int V08 loc6 ***** BB33, stmt 123 [000110] ------------ * STMT void (IL 0x065...0x067) [000109] -----+------ \--* JTRUE void [000107] -----+------ | /--* CNS_INT int 0 [000108] J----+-N---- \--* EQ int [000106] -----+------ \--* LCL_VAR int V55 tmp46 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 124 [000130] ------------ * STMT void (IL 0x06A...0x06C) [000127] -----+------ | /--* CNS_INT int 0 [000129] -A-XG+------ \--* ASG byte [000128] *--X-+-N---- \--* IND byte [000126] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB34, stmt 125 [000134] ------------ * STMT void (IL 0x06D...0x06E) [000131] -----+------ | /--* CNS_INT int 1 [000133] -A---+------ \--* ASG int [000132] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 126 [000116] ------------ * STMT void (IL 0x071...0x073) [000113] -----+------ | /--* CNS_INT int 0 [000115] -A-XG+------ \--* ASG byte [000114] *--X-+-N---- \--* IND byte [000112] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB35, stmt 127 [000120] ------------ * STMT void (IL 0x074...0x075) [000117] -----+------ | /--* CNS_INT int 0 [000119] -A---+------ \--* ASG int [000118] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 128 [000124] ------------ * STMT void (IL 0x078...0x079) [000123] -----+------ \--* RETURN int [000122] -----+------ \--* LCL_VAR int V05 loc3 ------------------------------------------------------------------------------------------------------------------- *************** Exiting Allocate Objects Trees after Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.50 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.50 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.50 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.50 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.50 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.50 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 1 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 1 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.50 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.50 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 1 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.50 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.50 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.50 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.50 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 1 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 1 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 1 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.50 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.50 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.50 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.50 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 1 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 1 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 1 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.50 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.50 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.50 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.50 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 1 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 1 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 1 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 [000224] ------------ * STMT void (IL 0x001... ???) [000221] -----+------ | /--* CNS_INT int 0 [000223] -A---+------ \--* ASG bool [000222] D----+-N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 2 [000171] ------------ * STMT void (IL 0x001... ???) [000167] -----+------ | /--* CNS_INT ref null [000168] -----+------ | /--* EQ int [000921] -----+------ | | \--* NOP ref [000920] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000170] -A---+------ \--* ASG bool [000169] D----+-N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 3 [000176] ------------ * STMT void (IL 0x001... ???) [000175] -----+------ \--* JTRUE void [000173] -----+------ | /--* CNS_INT int 0 [000174] J----+-N---- \--* EQ int [000172] -----+------ \--* LCL_VAR int V09 tmp0 ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 4 [000215] ------------ * STMT void (IL 0x001... ???) [000926] ------------ | /--* CNS_INT int 0 [000927] -A---------- | /--* ASG int [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 [000928] -A---+------ \--* COMMA void [000923] ------------ | /--* CNS_INT byref 0 [000924] -A---------- \--* ASG byref [000922] D------N---- \--* LCL_VAR byref V69 tmp60 ***** BB02, stmt 5 [000220] ------------ * STMT void (IL 0x001... ???) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 [000934] -A---------- | /--* ASG int [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 [000935] -A---+------ \--* COMMA void [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 [000931] -A---------- \--* ASG byref [000929] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 6 [000187] ------------ * STMT void (IL 0x001... ???) [000944] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [000945] -----+------ | /--* ADD byref [000943] -----+------ | | \--* LCL_VAR ref V96 tmp87 [000946] -A-XG+-N---- | /--* COMMA byref [000941] ---X-+-N---- | | | /--* NULLCHECK byte [000940] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [000949] -A-X-------- | | \--* COMMA void [000948] -----+------ | | | /--* NOP ref [000947] -----+------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000939] -A---+------ | | \--* ASG ref [000938] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000186] -A-XG+------ \--* ASG byref [000185] D----+-N---- \--* LCL_VAR byref V10 tmp1 ***** BB03, stmt 7 [000247] ------------ * STMT void (IL 0x001... ???) [000244] -----+------ | /--* CNS_INT int 0 [000246] -A---+------ \--* ASG int [000245] D----+-N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 8 [000239] ------------ * STMT void (IL 0x001... ???) [000236] x---G+------ | /--* IND int [000953] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [000954] -----+------ | | \--* ADD byref [000956] -----+------ | | \--* NOP ref [000955] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000238] -A--G+------ \--* ASG int [000237] D----+-N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 9 [000193] ------------ * STMT void (IL 0x001... ???) [000961] ------------ | /--* CNS_INT int 0 [000962] -A---------- | /--* ASG int [000960] D------N---- | | \--* LCL_VAR int V66 tmp57 [000963] -A---+------ \--* COMMA void [000958] ------------ | /--* CNS_INT byref 0 [000959] -A---------- \--* ASG byref [000957] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 10 [000256] ------------ * STMT void (IL 0x001... ???) [000254] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000250] -----+------ | /--* CNS_INT int 0 [000251] -----+------ arg0 in rcx \--* GE int [000240] -----+------ \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 11 [000262] ------------ * STMT void (IL 0x001... ???) [000967] ------------ | /--* CNS_INT byref 0 [000968] -A---+------ \--* ASG byref [000966] D------N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 12 [000268] ------------ * STMT void (IL 0x001... ???) [000188] -----+------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---+------ \--* ASG byref [000265] D----+-N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 13 [000273] ------------ * STMT void (IL 0x001... ???) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 [000971] -A---+------ \--* ASG byref [000969] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 14 [000279] ------------ * STMT void (IL 0x001... ???) [000276] -----+------ | /--* LCL_VAR int V14 tmp5 [000278] -A---+------ \--* ASG int [000277] D----+-N---- \--* LCL_VAR int V66 tmp57 ***** BB03, stmt 15 [000204] ------------ * STMT void (IL 0x001... ???) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 [000977] -A---------- | /--* ASG int [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 [000978] -A---+------ \--* COMMA void [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 [000974] -A---------- \--* ASG byref [000972] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 16 [000009] ------------ * STMT void (IL ???... ???) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 [000984] -A---------- | /--* ASG int [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 [000985] -A---+------ \--* COMMA void [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 [000981] -A---------- \--* ASG byref [000979] D------N---- \--* LCL_VAR byref V61 tmp52 ***** BB04, stmt 17 [000355] ------------ * STMT void (IL 0x00C... ???) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 [000991] -A---------- | /--* ASG int [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 [000992] -A---+------ \--* COMMA void [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 [000988] -A---------- \--* ASG byref [000986] D------N---- \--* LCL_VAR byref V72 tmp63 ***** BB04, stmt 18 [000359] ------------ * STMT void (IL 0x00C... ???) [001004] x----------- | /--* IND int [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001003] ------------ | | \--* ADD byref [001001] ------------ | | \--* LCL_VAR byref V00 arg0 [001005] -A---------- | /--* ASG int [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 [001006] -A---+------ \--* COMMA void [000998] x----------- | /--* IND byref [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000997] ------------ | | \--* ADD byref [000995] ------------ | | \--* LCL_VAR byref V00 arg0 [000999] -A---------- \--* ASG byref [000994] D------N---- \--* LCL_VAR byref V74 tmp65 ***** BB04, stmt 19 [000363] ------------ * STMT void (IL 0x00C... ???) [000360] -----+------ | /--* CNS_INT int 0 [000362] -A---+------ \--* ASG bool [000361] D----+-N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 20 [000367] ------------ * STMT void (IL 0x00C... ???) [000364] -----+------ | /--* CNS_INT int 0 [000366] -A---+------ \--* ASG bool [000365] D----+-N---- \--* LCL_VAR int V21 tmp12 ***** BB04, stmt 21 [000371] ------------ * STMT void (IL 0x00C... ???) [000368] -----+------ | /--* CNS_INT int 0 [000370] -A---+------ \--* ASG bool [000369] D----+-N---- \--* LCL_VAR int V20 tmp11 ***** BB04, stmt 22 [000384] ------------ * STMT void (IL 0x00C... ???) [000381] -----+------ | /--* CNS_INT int 0 [000383] -A---+------ \--* ASG int [000382] D----+-N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 23 [000379] ------------ * STMT void (IL 0x00C... ???) [000376] -----+------ | /--* LCL_VAR int V73 tmp64 [000378] -A---+------ \--* ASG int [000377] D----+-N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 24 [000294] ------------ * STMT void (IL 0x00C... ???) [000380] -----+------ | /--* LCL_VAR int V73 tmp64 [000293] -A---+------ \--* ASG int [000292] D----+-N---- \--* LCL_VAR int V18 tmp9 ***** BB04, stmt 25 [000397] ------------ * STMT void (IL 0x00C... ???) [000394] -----+------ | /--* CNS_INT int 0 [000396] -A---+------ \--* ASG int [000395] D----+-N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 26 [000392] ------------ * STMT void (IL 0x00C... ???) [000389] -----+------ | /--* LCL_VAR int V75 tmp66 [000391] -A---+------ \--* ASG int [000390] D----+-N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 27 [000302] ------------ * STMT void (IL 0x00C... ???) [000393] -----+------ | /--* LCL_VAR int V75 tmp66 [000297] -----+------ | /--* NE int [000295] -----+------ | | \--* LCL_VAR int V73 tmp64 [000301] -A---+------ \--* ASG bool [000300] D----+-N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 28 [000307] ------------ * STMT void (IL 0x00C... ???) [000306] -----+------ \--* JTRUE void [000304] -----+------ | /--* CNS_INT int 0 [000305] J----+-N---- \--* EQ int [000303] -----+------ \--* LCL_VAR int V19 tmp10 ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 29 [000351] ------------ * STMT void (IL 0x00C... ???) [000348] -----+------ | /--* CNS_INT int 0 [000350] -A---+------ \--* ASG bool [000349] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 30 [000410] ------------ * STMT void (IL 0x00C... ???) [000407] -----+------ | /--* CNS_INT int 0 [000409] -A---+------ \--* ASG int [000408] D----+-N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 31 [000405] ------------ * STMT void (IL 0x00C... ???) [000402] -----+------ | /--* LCL_VAR int V75 tmp66 [000404] -A---+------ \--* ASG int [000403] D----+-N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 32 [000318] ------------ * STMT void (IL 0x00C... ???) [000314] -----+------ | /--* CNS_INT int 0 [000315] -----+------ | /--* EQ int [000406] -----+------ | | \--* LCL_VAR int V75 tmp66 [000317] -A---+------ \--* ASG bool [000316] D----+-N---- \--* LCL_VAR int V20 tmp11 ***** BB06, stmt 33 [000323] ------------ * STMT void (IL 0x00C... ???) [000322] -----+------ \--* JTRUE void [000320] -----+------ | /--* CNS_INT int 0 [000321] J----+-N---- \--* EQ int [000319] -----+------ \--* LCL_VAR int V20 tmp11 ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 34 [000346] ------------ * STMT void (IL 0x00C... ???) [000343] -----+------ | /--* CNS_INT int 1 [000345] -A---+------ \--* ASG bool [000344] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 35 [000338] ------------ * STMT void (IL 0x00C... ???) [000334] -----+------ | /--* CNS_INT int 0 [000335] -ACXG+------ | /--* EQ int [000327] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001029] *------N---- | | | | \--* IND int [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001028] ------------ | | | | \--* ADD byref [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 [001032] -A---+----L- arg0 SETUP | | +--* COMMA void [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001022] *------N---- | | | | | \--* IND byref [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001021] ------------ | | | | | \--* ADD byref [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 [001025] -A---------- | | | \--* COMMA void [001015] L----------- | | | | /--* ADDR byref [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001018] -A---------- | | | \--* ASG byref [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001050] *------N---- | | | | \--* IND int [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001049] ------------ | | | | \--* ADD byref [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 [001053] -A---+----L- arg1 SETUP | | +--* COMMA void [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001043] *------N---- | | | | | \--* IND byref [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001042] ------------ | | | | | \--* ADD byref [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 [001046] -A---------- | | | \--* COMMA void [001036] L----------- | | | | /--* ADDR byref [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001039] -A---------- | | | \--* ASG byref [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 [001055] L----------- arg0 in rcx | | +--* ADDR byref [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001058] L----------- arg1 in rdx | | \--* ADDR byref [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000337] -ACXG+------ \--* ASG bool [000336] D----+-N---- \--* LCL_VAR int V21 tmp12 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 36 [000024] ------------ * STMT void (IL ???... ???) [000340] -----+------ | /--* LCL_VAR int V21 tmp12 [000023] -A---+------ \--* ASG int [000022] D----+-N---- \--* LCL_VAR int V04 loc2 ***** BB09, stmt 37 [000029] ------------ * STMT void (IL 0x014...0x015) [000028] -----+------ \--* JTRUE void [000026] -----+------ | /--* CNS_INT int 0 [000027] J----+-N---- \--* EQ int [000025] -----+------ \--* LCL_VAR int V21 tmp12 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 38 [000160] ------------ * STMT void (IL 0x018...0x01A) [000157] -----+------ | /--* CNS_INT int 1 [000159] -A-XG+------ \--* ASG byte [000158] *--X-+-N---- \--* IND byte [000156] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB10, stmt 39 [000164] ------------ * STMT void (IL 0x01B...0x01C) [000161] -----+------ | /--* CNS_INT int 1 [000163] -A---+------ \--* ASG int [000162] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 40 [000471] ------------ * STMT void (IL 0x01F... ???) [000468] -----+------ | /--* CNS_INT int 0 [000470] -A---+------ \--* ASG bool [000469] D----+-N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 41 [000418] ------------ * STMT void (IL 0x01F... ???) [000414] -----+------ | /--* CNS_INT ref null [000415] -----+------ | /--* EQ int [001063] -----+------ | | \--* NOP ref [001062] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000417] -A---+------ \--* ASG bool [000416] D----+-N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 42 [000423] ------------ * STMT void (IL 0x01F... ???) [000422] -----+------ \--* JTRUE void [000420] -----+------ | /--* CNS_INT int 0 [000421] J----+-N---- \--* EQ int [000419] -----+------ \--* LCL_VAR int V25 tmp16 ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 43 [000462] ------------ * STMT void (IL 0x01F... ???) [001068] ------------ | /--* CNS_INT int 0 [001069] -A---------- | /--* ASG int [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 [001070] -A---+------ \--* COMMA void [001065] ------------ | /--* CNS_INT byref 0 [001066] -A---------- \--* ASG byref [001064] D------N---- \--* LCL_VAR byref V80 tmp71 ***** BB12, stmt 44 [000467] ------------ * STMT void (IL 0x01F... ???) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 [001076] -A---------- | /--* ASG int [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 [001077] -A---+------ \--* COMMA void [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 [001073] -A---------- \--* ASG byref [001071] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 45 [000434] ------------ * STMT void (IL 0x01F... ???) [001086] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [001087] -----+------ | /--* ADD byref [001085] -----+------ | | \--* LCL_VAR ref V96 tmp87 [001088] -A-XG+-N---- | /--* COMMA byref [001083] ---X-+-N---- | | | /--* NULLCHECK byte [001082] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [001091] -A-X-------- | | \--* COMMA void [001090] -----+------ | | | /--* NOP ref [001089] -----+------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [001081] -A---+------ | | \--* ASG ref [001080] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000433] -A-XG+------ \--* ASG byref [000432] D----+-N---- \--* LCL_VAR byref V26 tmp17 ***** BB13, stmt 46 [000494] ------------ * STMT void (IL 0x01F... ???) [000491] -----+------ | /--* CNS_INT int 0 [000493] -A---+------ \--* ASG int [000492] D----+-N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 47 [000486] ------------ * STMT void (IL 0x01F... ???) [000483] x---G+------ | /--* IND int [001095] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [001096] -----+------ | | \--* ADD byref [001098] -----+------ | | \--* NOP ref [001097] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000485] -A--G+------ \--* ASG int [000484] D----+-N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 48 [000440] ------------ * STMT void (IL 0x01F... ???) [001103] ------------ | /--* CNS_INT int 0 [001104] -A---------- | /--* ASG int [001102] D------N---- | | \--* LCL_VAR int V77 tmp68 [001105] -A---+------ \--* COMMA void [001100] ------------ | /--* CNS_INT byref 0 [001101] -A---------- \--* ASG byref [001099] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 49 [000503] ------------ * STMT void (IL 0x01F... ???) [000501] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000497] -----+------ | /--* CNS_INT int 0 [000498] -----+------ arg0 in rcx \--* GE int [000487] -----+------ \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 50 [000509] ------------ * STMT void (IL 0x01F... ???) [001109] ------------ | /--* CNS_INT byref 0 [001110] -A---+------ \--* ASG byref [001108] D------N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 51 [000515] ------------ * STMT void (IL 0x01F... ???) [000435] -----+------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---+------ \--* ASG byref [000512] D----+-N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 52 [000520] ------------ * STMT void (IL 0x01F... ???) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 [001113] -A---+------ \--* ASG byref [001111] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 53 [000526] ------------ * STMT void (IL 0x01F... ???) [000523] -----+------ | /--* LCL_VAR int V30 tmp21 [000525] -A---+------ \--* ASG int [000524] D----+-N---- \--* LCL_VAR int V77 tmp68 ***** BB13, stmt 54 [000451] ------------ * STMT void (IL 0x01F... ???) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 [001119] -A---------- | /--* ASG int [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 [001120] -A---+------ \--* COMMA void [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 [001116] -A---------- \--* ASG byref [001114] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 55 [000039] ------------ * STMT void (IL ???... ???) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 [001126] -A---------- | /--* ASG int [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 [001127] -A---+------ \--* COMMA void [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 [001123] -A---------- \--* ASG byref [001121] D------N---- \--* LCL_VAR byref V63 tmp54 ***** BB14, stmt 56 [000602] ------------ * STMT void (IL 0x02A... ???) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 [001133] -A---------- | /--* ASG int [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 [001134] -A---+------ \--* COMMA void [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 [001130] -A---------- \--* ASG byref [001128] D------N---- \--* LCL_VAR byref V83 tmp74 ***** BB14, stmt 57 [000606] ------------ * STMT void (IL 0x02A... ???) [001146] x----------- | /--* IND int [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001145] ------------ | | \--* ADD byref [001143] ------------ | | \--* LCL_VAR byref V00 arg0 [001147] -A---------- | /--* ASG int [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 [001148] -A---+------ \--* COMMA void [001140] x----------- | /--* IND byref [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001139] ------------ | | \--* ADD byref [001137] ------------ | | \--* LCL_VAR byref V00 arg0 [001141] -A---------- \--* ASG byref [001136] D------N---- \--* LCL_VAR byref V85 tmp76 ***** BB14, stmt 58 [000610] ------------ * STMT void (IL 0x02A... ???) [000607] -----+------ | /--* CNS_INT int 0 [000609] -A---+------ \--* ASG bool [000608] D----+-N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 59 [000614] ------------ * STMT void (IL 0x02A... ???) [000611] -----+------ | /--* CNS_INT int 0 [000613] -A---+------ \--* ASG bool [000612] D----+-N---- \--* LCL_VAR int V37 tmp28 ***** BB14, stmt 60 [000618] ------------ * STMT void (IL 0x02A... ???) [000615] -----+------ | /--* CNS_INT int 0 [000617] -A---+------ \--* ASG bool [000616] D----+-N---- \--* LCL_VAR int V36 tmp27 ***** BB14, stmt 61 [000631] ------------ * STMT void (IL 0x02A... ???) [000628] -----+------ | /--* CNS_INT int 0 [000630] -A---+------ \--* ASG int [000629] D----+-N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 62 [000626] ------------ * STMT void (IL 0x02A... ???) [000623] -----+------ | /--* LCL_VAR int V84 tmp75 [000625] -A---+------ \--* ASG int [000624] D----+-N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 63 [000541] ------------ * STMT void (IL 0x02A... ???) [000627] -----+------ | /--* LCL_VAR int V84 tmp75 [000540] -A---+------ \--* ASG int [000539] D----+-N---- \--* LCL_VAR int V34 tmp25 ***** BB14, stmt 64 [000644] ------------ * STMT void (IL 0x02A... ???) [000641] -----+------ | /--* CNS_INT int 0 [000643] -A---+------ \--* ASG int [000642] D----+-N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 65 [000639] ------------ * STMT void (IL 0x02A... ???) [000636] -----+------ | /--* LCL_VAR int V86 tmp77 [000638] -A---+------ \--* ASG int [000637] D----+-N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 66 [000549] ------------ * STMT void (IL 0x02A... ???) [000640] -----+------ | /--* LCL_VAR int V86 tmp77 [000544] -----+------ | /--* NE int [000542] -----+------ | | \--* LCL_VAR int V84 tmp75 [000548] -A---+------ \--* ASG bool [000547] D----+-N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 67 [000554] ------------ * STMT void (IL 0x02A... ???) [000553] -----+------ \--* JTRUE void [000551] -----+------ | /--* CNS_INT int 0 [000552] J----+-N---- \--* EQ int [000550] -----+------ \--* LCL_VAR int V35 tmp26 ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 68 [000598] ------------ * STMT void (IL 0x02A... ???) [000595] -----+------ | /--* CNS_INT int 0 [000597] -A---+------ \--* ASG bool [000596] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 69 [000657] ------------ * STMT void (IL 0x02A... ???) [000654] -----+------ | /--* CNS_INT int 0 [000656] -A---+------ \--* ASG int [000655] D----+-N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 70 [000652] ------------ * STMT void (IL 0x02A... ???) [000649] -----+------ | /--* LCL_VAR int V86 tmp77 [000651] -A---+------ \--* ASG int [000650] D----+-N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 71 [000565] ------------ * STMT void (IL 0x02A... ???) [000561] -----+------ | /--* CNS_INT int 0 [000562] -----+------ | /--* EQ int [000653] -----+------ | | \--* LCL_VAR int V86 tmp77 [000564] -A---+------ \--* ASG bool [000563] D----+-N---- \--* LCL_VAR int V36 tmp27 ***** BB16, stmt 72 [000570] ------------ * STMT void (IL 0x02A... ???) [000569] -----+------ \--* JTRUE void [000567] -----+------ | /--* CNS_INT int 0 [000568] J----+-N---- \--* EQ int [000566] -----+------ \--* LCL_VAR int V36 tmp27 ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 73 [000593] ------------ * STMT void (IL 0x02A... ???) [000590] -----+------ | /--* CNS_INT int 1 [000592] -A---+------ \--* ASG bool [000591] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 74 [000585] ------------ * STMT void (IL 0x02A... ???) [000581] -----+------ | /--* CNS_INT int 0 [000582] -ACXG+------ | /--* EQ int [000574] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001171] *------N---- | | | | \--* IND int [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001170] ------------ | | | | \--* ADD byref [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 [001174] -A---+----L- arg0 SETUP | | +--* COMMA void [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001164] *------N---- | | | | | \--* IND byref [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001163] ------------ | | | | | \--* ADD byref [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 [001167] -A---------- | | | \--* COMMA void [001157] L----------- | | | | /--* ADDR byref [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001160] -A---------- | | | \--* ASG byref [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001192] *------N---- | | | | \--* IND int [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001191] ------------ | | | | \--* ADD byref [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 [001195] -A---+----L- arg1 SETUP | | +--* COMMA void [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001185] *------N---- | | | | | \--* IND byref [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001184] ------------ | | | | | \--* ADD byref [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 [001188] -A---------- | | | \--* COMMA void [001178] L----------- | | | | /--* ADDR byref [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001181] -A---------- | | | \--* ASG byref [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 [001197] L----------- arg0 in rcx | | +--* ADDR byref [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001200] L----------- arg1 in rdx | | \--* ADDR byref [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000584] -ACXG+------ \--* ASG bool [000583] D----+-N---- \--* LCL_VAR int V37 tmp28 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 75 [000054] ------------ * STMT void (IL ???... ???) [000587] -----+------ | /--* LCL_VAR int V37 tmp28 [000053] -A---+------ \--* ASG int [000052] D----+-N---- \--* LCL_VAR int V06 loc4 ***** BB19, stmt 76 [000059] ------------ * STMT void (IL 0x033...0x035) [000058] -----+------ \--* JTRUE void [000056] -----+------ | /--* CNS_INT int 0 [000057] J----+-N---- \--* EQ int [000055] -----+------ \--* LCL_VAR int V37 tmp28 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 77 [000150] ------------ * STMT void (IL 0x038...0x03A) [000147] -----+------ | /--* CNS_INT int 0 [000149] -A-XG+------ \--* ASG byte [000148] *--X-+-N---- \--* IND byte [000146] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB20, stmt 78 [000154] ------------ * STMT void (IL 0x03B...0x03C) [000151] -----+------ | /--* CNS_INT int 1 [000153] -A---+------ \--* ASG int [000152] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 79 [000069] ------------ * STMT void (IL 0x03F...0x045) [000062] SACXG+------ \--* CALL void System.Boolean.TrimWhiteSpaceAndNull [000066] -----+------ | /--* LCL_VAR byref V00 arg0 [001206] -A--------L- arg0 SETUP +--* ASG byref [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 [000064] x----+-N---- | /--* IND struct [000061] -----+------ | | \--* LCL_VAR byref V00 arg0 [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 [001210] L----------- arg1 in rdx \--* ADDR byref [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 ***** BB21, stmt 80 [000732] ------------ * STMT void (IL 0x047... ???) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 [001217] -A---------- | /--* ASG int [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 [001218] -A---+------ \--* COMMA void [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 [001214] -A---------- \--* ASG byref [001212] D------N---- \--* LCL_VAR byref V87 tmp78 ***** BB21, stmt 81 [000736] ------------ * STMT void (IL 0x047... ???) [001230] x----------- | /--* IND int [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001229] ------------ | | \--* ADD byref [001227] ------------ | | \--* LCL_VAR byref V00 arg0 [001231] -A---------- | /--* ASG int [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 [001232] -A---+------ \--* COMMA void [001224] x----------- | /--* IND byref [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001223] ------------ | | \--* ADD byref [001221] ------------ | | \--* LCL_VAR byref V00 arg0 [001225] -A---------- \--* ASG byref [001220] D------N---- \--* LCL_VAR byref V89 tmp80 ***** BB21, stmt 82 [000740] ------------ * STMT void (IL 0x047... ???) [000737] -----+------ | /--* CNS_INT int 0 [000739] -A---+------ \--* ASG bool [000738] D----+-N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 83 [000744] ------------ * STMT void (IL 0x047... ???) [000741] -----+------ | /--* CNS_INT int 0 [000743] -A---+------ \--* ASG bool [000742] D----+-N---- \--* LCL_VAR int V46 tmp37 ***** BB21, stmt 84 [000748] ------------ * STMT void (IL 0x047... ???) [000745] -----+------ | /--* CNS_INT int 0 [000747] -A---+------ \--* ASG bool [000746] D----+-N---- \--* LCL_VAR int V45 tmp36 ***** BB21, stmt 85 [000761] ------------ * STMT void (IL 0x047... ???) [000758] -----+------ | /--* CNS_INT int 0 [000760] -A---+------ \--* ASG int [000759] D----+-N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 86 [000756] ------------ * STMT void (IL 0x047... ???) [000753] -----+------ | /--* LCL_VAR int V88 tmp79 [000755] -A---+------ \--* ASG int [000754] D----+-N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 87 [000671] ------------ * STMT void (IL 0x047... ???) [000757] -----+------ | /--* LCL_VAR int V88 tmp79 [000670] -A---+------ \--* ASG int [000669] D----+-N---- \--* LCL_VAR int V43 tmp34 ***** BB21, stmt 88 [000774] ------------ * STMT void (IL 0x047... ???) [000771] -----+------ | /--* CNS_INT int 0 [000773] -A---+------ \--* ASG int [000772] D----+-N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 89 [000769] ------------ * STMT void (IL 0x047... ???) [000766] -----+------ | /--* LCL_VAR int V90 tmp81 [000768] -A---+------ \--* ASG int [000767] D----+-N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 90 [000679] ------------ * STMT void (IL 0x047... ???) [000770] -----+------ | /--* LCL_VAR int V90 tmp81 [000674] -----+------ | /--* NE int [000672] -----+------ | | \--* LCL_VAR int V88 tmp79 [000678] -A---+------ \--* ASG bool [000677] D----+-N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 91 [000684] ------------ * STMT void (IL 0x047... ???) [000683] -----+------ \--* JTRUE void [000681] -----+------ | /--* CNS_INT int 0 [000682] J----+-N---- \--* EQ int [000680] -----+------ \--* LCL_VAR int V44 tmp35 ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 92 [000728] ------------ * STMT void (IL 0x047... ???) [000725] -----+------ | /--* CNS_INT int 0 [000727] -A---+------ \--* ASG bool [000726] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 93 [000787] ------------ * STMT void (IL 0x047... ???) [000784] -----+------ | /--* CNS_INT int 0 [000786] -A---+------ \--* ASG int [000785] D----+-N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 94 [000782] ------------ * STMT void (IL 0x047... ???) [000779] -----+------ | /--* LCL_VAR int V90 tmp81 [000781] -A---+------ \--* ASG int [000780] D----+-N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 95 [000695] ------------ * STMT void (IL 0x047... ???) [000691] -----+------ | /--* CNS_INT int 0 [000692] -----+------ | /--* EQ int [000783] -----+------ | | \--* LCL_VAR int V90 tmp81 [000694] -A---+------ \--* ASG bool [000693] D----+-N---- \--* LCL_VAR int V45 tmp36 ***** BB23, stmt 96 [000700] ------------ * STMT void (IL 0x047... ???) [000699] -----+------ \--* JTRUE void [000697] -----+------ | /--* CNS_INT int 0 [000698] J----+-N---- \--* EQ int [000696] -----+------ \--* LCL_VAR int V45 tmp36 ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 97 [000723] ------------ * STMT void (IL 0x047... ???) [000720] -----+------ | /--* CNS_INT int 1 [000722] -A---+------ \--* ASG bool [000721] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 98 [000715] ------------ * STMT void (IL 0x047... ???) [000711] -----+------ | /--* CNS_INT int 0 [000712] -ACXG+------ | /--* EQ int [000704] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001255] *------N---- | | | | \--* IND int [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001254] ------------ | | | | \--* ADD byref [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 [001258] -A---+----L- arg0 SETUP | | +--* COMMA void [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001248] *------N---- | | | | | \--* IND byref [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001247] ------------ | | | | | \--* ADD byref [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 [001251] -A---------- | | | \--* COMMA void [001241] L----------- | | | | /--* ADDR byref [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001244] -A---------- | | | \--* ASG byref [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001276] *------N---- | | | | \--* IND int [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001275] ------------ | | | | \--* ADD byref [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 [001279] -A---+----L- arg1 SETUP | | +--* COMMA void [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001269] *------N---- | | | | | \--* IND byref [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001268] ------------ | | | | | \--* ADD byref [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 [001272] -A---------- | | | \--* COMMA void [001262] L----------- | | | | /--* ADDR byref [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001265] -A---------- | | | \--* ASG byref [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 [001281] L----------- arg0 in rcx | | +--* ADDR byref [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001284] L----------- arg1 in rdx | | \--* ADDR byref [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000714] -ACXG+------ \--* ASG bool [000713] D----+-N---- \--* LCL_VAR int V46 tmp37 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 99 [000084] ------------ * STMT void (IL ???... ???) [000717] -----+------ | /--* LCL_VAR int V46 tmp37 [000083] -A---+------ \--* ASG int [000082] D----+-N---- \--* LCL_VAR int V07 loc5 ***** BB26, stmt 100 [000089] ------------ * STMT void (IL 0x050...0x052) [000088] -----+------ \--* JTRUE void [000086] -----+------ | /--* CNS_INT int 0 [000087] J----+-N---- \--* EQ int [000085] -----+------ \--* LCL_VAR int V46 tmp37 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 101 [000140] ------------ * STMT void (IL 0x055...0x057) [000137] -----+------ | /--* CNS_INT int 1 [000139] -A-XG+------ \--* ASG byte [000138] *--X-+-N---- \--* IND byte [000136] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB27, stmt 102 [000144] ------------ * STMT void (IL 0x058...0x059) [000141] -----+------ | /--* CNS_INT int 1 [000143] -A---+------ \--* ASG int [000142] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 103 [000862] ------------ * STMT void (IL 0x05C... ???) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 [001292] -A---------- | /--* ASG int [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 [001293] -A---+------ \--* COMMA void [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 [001289] -A---------- \--* ASG byref [001287] D------N---- \--* LCL_VAR byref V91 tmp82 ***** BB28, stmt 104 [000866] ------------ * STMT void (IL 0x05C... ???) [001305] x----------- | /--* IND int [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001304] ------------ | | \--* ADD byref [001302] ------------ | | \--* LCL_VAR byref V00 arg0 [001306] -A---------- | /--* ASG int [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 [001307] -A---+------ \--* COMMA void [001299] x----------- | /--* IND byref [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001298] ------------ | | \--* ADD byref [001296] ------------ | | \--* LCL_VAR byref V00 arg0 [001300] -A---------- \--* ASG byref [001295] D------N---- \--* LCL_VAR byref V93 tmp84 ***** BB28, stmt 105 [000870] ------------ * STMT void (IL 0x05C... ???) [000867] -----+------ | /--* CNS_INT int 0 [000869] -A---+------ \--* ASG bool [000868] D----+-N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 106 [000874] ------------ * STMT void (IL 0x05C... ???) [000871] -----+------ | /--* CNS_INT int 0 [000873] -A---+------ \--* ASG bool [000872] D----+-N---- \--* LCL_VAR int V55 tmp46 ***** BB28, stmt 107 [000878] ------------ * STMT void (IL 0x05C... ???) [000875] -----+------ | /--* CNS_INT int 0 [000877] -A---+------ \--* ASG bool [000876] D----+-N---- \--* LCL_VAR int V54 tmp45 ***** BB28, stmt 108 [000891] ------------ * STMT void (IL 0x05C... ???) [000888] -----+------ | /--* CNS_INT int 0 [000890] -A---+------ \--* ASG int [000889] D----+-N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 109 [000886] ------------ * STMT void (IL 0x05C... ???) [000883] -----+------ | /--* LCL_VAR int V92 tmp83 [000885] -A---+------ \--* ASG int [000884] D----+-N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 110 [000801] ------------ * STMT void (IL 0x05C... ???) [000887] -----+------ | /--* LCL_VAR int V92 tmp83 [000800] -A---+------ \--* ASG int [000799] D----+-N---- \--* LCL_VAR int V52 tmp43 ***** BB28, stmt 111 [000904] ------------ * STMT void (IL 0x05C... ???) [000901] -----+------ | /--* CNS_INT int 0 [000903] -A---+------ \--* ASG int [000902] D----+-N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 112 [000899] ------------ * STMT void (IL 0x05C... ???) [000896] -----+------ | /--* LCL_VAR int V94 tmp85 [000898] -A---+------ \--* ASG int [000897] D----+-N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 113 [000809] ------------ * STMT void (IL 0x05C... ???) [000900] -----+------ | /--* LCL_VAR int V94 tmp85 [000804] -----+------ | /--* NE int [000802] -----+------ | | \--* LCL_VAR int V92 tmp83 [000808] -A---+------ \--* ASG bool [000807] D----+-N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 114 [000814] ------------ * STMT void (IL 0x05C... ???) [000813] -----+------ \--* JTRUE void [000811] -----+------ | /--* CNS_INT int 0 [000812] J----+-N---- \--* EQ int [000810] -----+------ \--* LCL_VAR int V53 tmp44 ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 115 [000858] ------------ * STMT void (IL 0x05C... ???) [000855] -----+------ | /--* CNS_INT int 0 [000857] -A---+------ \--* ASG bool [000856] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 116 [000917] ------------ * STMT void (IL 0x05C... ???) [000914] -----+------ | /--* CNS_INT int 0 [000916] -A---+------ \--* ASG int [000915] D----+-N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 117 [000912] ------------ * STMT void (IL 0x05C... ???) [000909] -----+------ | /--* LCL_VAR int V94 tmp85 [000911] -A---+------ \--* ASG int [000910] D----+-N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 118 [000825] ------------ * STMT void (IL 0x05C... ???) [000821] -----+------ | /--* CNS_INT int 0 [000822] -----+------ | /--* EQ int [000913] -----+------ | | \--* LCL_VAR int V94 tmp85 [000824] -A---+------ \--* ASG bool [000823] D----+-N---- \--* LCL_VAR int V54 tmp45 ***** BB30, stmt 119 [000830] ------------ * STMT void (IL 0x05C... ???) [000829] -----+------ \--* JTRUE void [000827] -----+------ | /--* CNS_INT int 0 [000828] J----+-N---- \--* EQ int [000826] -----+------ \--* LCL_VAR int V54 tmp45 ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 120 [000853] ------------ * STMT void (IL 0x05C... ???) [000850] -----+------ | /--* CNS_INT int 1 [000852] -A---+------ \--* ASG bool [000851] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 121 [000845] ------------ * STMT void (IL 0x05C... ???) [000841] -----+------ | /--* CNS_INT int 0 [000842] -ACXG+------ | /--* EQ int [000834] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001330] *------N---- | | | | \--* IND int [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001329] ------------ | | | | \--* ADD byref [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 [001333] -A---+----L- arg0 SETUP | | +--* COMMA void [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001323] *------N---- | | | | | \--* IND byref [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001322] ------------ | | | | | \--* ADD byref [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 [001326] -A---------- | | | \--* COMMA void [001316] L----------- | | | | /--* ADDR byref [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001319] -A---------- | | | \--* ASG byref [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001351] *------N---- | | | | \--* IND int [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001350] ------------ | | | | \--* ADD byref [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 [001354] -A---+----L- arg1 SETUP | | +--* COMMA void [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001344] *------N---- | | | | | \--* IND byref [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001343] ------------ | | | | | \--* ADD byref [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 [001347] -A---------- | | | \--* COMMA void [001337] L----------- | | | | /--* ADDR byref [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001340] -A---------- | | | \--* ASG byref [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 [001356] L----------- arg0 in rcx | | +--* ADDR byref [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001359] L----------- arg1 in rdx | | \--* ADDR byref [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000844] -ACXG+------ \--* ASG bool [000843] D----+-N---- \--* LCL_VAR int V55 tmp46 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 122 [000105] ------------ * STMT void (IL ???... ???) [000847] -----+------ | /--* LCL_VAR int V55 tmp46 [000104] -A---+------ \--* ASG int [000103] D----+-N---- \--* LCL_VAR int V08 loc6 ***** BB33, stmt 123 [000110] ------------ * STMT void (IL 0x065...0x067) [000109] -----+------ \--* JTRUE void [000107] -----+------ | /--* CNS_INT int 0 [000108] J----+-N---- \--* EQ int [000106] -----+------ \--* LCL_VAR int V55 tmp46 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 124 [000130] ------------ * STMT void (IL 0x06A...0x06C) [000127] -----+------ | /--* CNS_INT int 0 [000129] -A-XG+------ \--* ASG byte [000128] *--X-+-N---- \--* IND byte [000126] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB34, stmt 125 [000134] ------------ * STMT void (IL 0x06D...0x06E) [000131] -----+------ | /--* CNS_INT int 1 [000133] -A---+------ \--* ASG int [000132] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 126 [000116] ------------ * STMT void (IL 0x071...0x073) [000113] -----+------ | /--* CNS_INT int 0 [000115] -A-XG+------ \--* ASG byte [000114] *--X-+-N---- \--* IND byte [000112] -----+------ \--* LCL_VAR byref V01 arg1 ***** BB35, stmt 127 [000120] ------------ * STMT void (IL 0x074...0x075) [000117] -----+------ | /--* CNS_INT int 0 [000119] -A---+------ \--* ASG int [000118] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 128 [000124] ------------ * STMT void (IL 0x078...0x079) [000123] -----+------ \--* RETURN int [000122] -----+------ \--* LCL_VAR int V05 loc3 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optOptimizeLoops() After optSetBlockWeights: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optCloneLoops() *************** In lvaMarkLocalVars() lvaGrabTemp returning 108 (V108 tmp99) (a long lifetime temp) called for OutgoingArgSpace. *** marking local variables in block BB01 (weight=1 ) [000224] ------------ * STMT void (IL 0x001... ???) [000221] -----+------ | /--* CNS_INT int 0 [000223] -A---+------ \--* ASG bool [000222] D----+-N---- \--* LCL_VAR int V09 tmp0 New refCnts for V09: refCnt = 1, refCntWtd = 1 [000171] ------------ * STMT void (IL 0x001... ???) [000167] -----+------ | /--* CNS_INT ref null [000168] -----+------ | /--* EQ int [000921] -----+------ | | \--* NOP ref [000920] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000170] -A---+------ \--* ASG bool [000169] D----+-N---- \--* LCL_VAR int V09 tmp0 New refCnts for V09: refCnt = 2, refCntWtd = 2 [000176] ------------ * STMT void (IL 0x001... ???) [000175] -----+------ \--* JTRUE void [000173] -----+------ | /--* CNS_INT int 0 [000174] J----+-N---- \--* EQ int [000172] -----+------ \--* LCL_VAR int V09 tmp0 New refCnts for V09: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB02 (weight=0.25) [000215] ------------ * STMT void (IL 0x001... ???) [000926] ------------ | /--* CNS_INT int 0 [000927] -A---------- | /--* ASG int [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 [000928] -A---+------ \--* COMMA void [000923] ------------ | /--* CNS_INT byref 0 [000924] -A---------- \--* ASG byref [000922] D------N---- \--* LCL_VAR byref V69 tmp60 New refCnts for V69: refCnt = 1, refCntWtd = 0.25 New refCnts for V70: refCnt = 1, refCntWtd = 0.25 [000220] ------------ * STMT void (IL 0x001... ???) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 [000934] -A---------- | /--* ASG int [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 [000935] -A---+------ \--* COMMA void [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 [000931] -A---------- \--* ASG byref [000929] D------N---- \--* LCL_VAR byref V67 tmp58 New refCnts for V67: refCnt = 1, refCntWtd = 0.25 New refCnts for V69: refCnt = 2, refCntWtd = 0.50 New refCnts for V68: refCnt = 1, refCntWtd = 0.25 New refCnts for V70: refCnt = 2, refCntWtd = 0.50 *** marking local variables in block BB03 (weight=0.25) [000187] ------------ * STMT void (IL 0x001... ???) [000944] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [000945] -----+------ | /--* ADD byref [000943] -----+------ | | \--* LCL_VAR ref V96 tmp87 [000946] -A-XG+-N---- | /--* COMMA byref [000941] ---X-+-N---- | | | /--* NULLCHECK byte [000940] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [000949] -A-X-------- | | \--* COMMA void [000948] -----+------ | | | /--* NOP ref [000947] -----+------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000939] -A---+------ | | \--* ASG ref [000938] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000186] -A-XG+------ \--* ASG byref [000185] D----+-N---- \--* LCL_VAR byref V10 tmp1 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V96: refCnt = 1, refCntWtd = 0.25 New refCnts for V96: refCnt = 2, refCntWtd = 0.50 New refCnts for V96: refCnt = 3, refCntWtd = 0.75 [000247] ------------ * STMT void (IL 0x001... ???) [000244] -----+------ | /--* CNS_INT int 0 [000246] -A---+------ \--* ASG int [000245] D----+-N---- \--* LCL_VAR int V14 tmp5 New refCnts for V14: refCnt = 1, refCntWtd = 0.25 [000239] ------------ * STMT void (IL 0x001... ???) [000236] x---G+------ | /--* IND int [000953] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [000954] -----+------ | | \--* ADD byref [000956] -----+------ | | \--* NOP ref [000955] -----+------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] [000238] -A--G+------ \--* ASG int [000237] D----+-N---- \--* LCL_VAR int V14 tmp5 New refCnts for V14: refCnt = 2, refCntWtd = 0.50 [000193] ------------ * STMT void (IL 0x001... ???) [000961] ------------ | /--* CNS_INT int 0 [000962] -A---------- | /--* ASG int [000960] D------N---- | | \--* LCL_VAR int V66 tmp57 [000963] -A---+------ \--* COMMA void [000958] ------------ | /--* CNS_INT byref 0 [000959] -A---------- \--* ASG byref [000957] D------N---- \--* LCL_VAR byref V65 tmp56 New refCnts for V65: refCnt = 1, refCntWtd = 0.25 New refCnts for V66: refCnt = 1, refCntWtd = 0.25 [000256] ------------ * STMT void (IL 0x001... ???) [000254] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000250] -----+------ | /--* CNS_INT int 0 [000251] -----+------ arg0 in rcx \--* GE int [000240] -----+------ \--* LCL_VAR int V14 tmp5 New refCnts for V14: refCnt = 3, refCntWtd = 0.75 [000262] ------------ * STMT void (IL 0x001... ???) [000967] ------------ | /--* CNS_INT byref 0 [000968] -A---+------ \--* ASG byref [000966] D------N---- \--* LCL_VAR byref V71 tmp62 New refCnts for V71: refCnt = 1, refCntWtd = 0.25 [000268] ------------ * STMT void (IL 0x001... ???) [000188] -----+------ | /--* LCL_VAR byref V10 tmp1 [000266] -A---+------ \--* ASG byref [000265] D----+-N---- \--* LCL_VAR byref V71 tmp62 New refCnts for V71: refCnt = 2, refCntWtd = 0.50 New refCnts for V10: refCnt = 2, refCntWtd = 1 [000273] ------------ * STMT void (IL 0x001... ???) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 [000971] -A---+------ \--* ASG byref [000969] D------N---- \--* LCL_VAR byref V65 tmp56 New refCnts for V65: refCnt = 2, refCntWtd = 0.50 New refCnts for V71: refCnt = 3, refCntWtd = 0.75 [000279] ------------ * STMT void (IL 0x001... ???) [000276] -----+------ | /--* LCL_VAR int V14 tmp5 [000278] -A---+------ \--* ASG int [000277] D----+-N---- \--* LCL_VAR int V66 tmp57 New refCnts for V66: refCnt = 2, refCntWtd = 0.50 New refCnts for V14: refCnt = 4, refCntWtd = 1 [000204] ------------ * STMT void (IL 0x001... ???) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 [000977] -A---------- | /--* ASG int [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 [000978] -A---+------ \--* COMMA void [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 [000974] -A---------- \--* ASG byref [000972] D------N---- \--* LCL_VAR byref V67 tmp58 New refCnts for V67: refCnt = 2, refCntWtd = 0.50 New refCnts for V65: refCnt = 3, refCntWtd = 0.75 New refCnts for V68: refCnt = 2, refCntWtd = 0.50 New refCnts for V66: refCnt = 3, refCntWtd = 0.75 *** marking local variables in block BB04 (weight=1 ) [000009] ------------ * STMT void (IL ???... ???) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 [000984] -A---------- | /--* ASG int [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 [000985] -A---+------ \--* COMMA void [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 [000981] -A---------- \--* ASG byref [000979] D------N---- \--* LCL_VAR byref V61 tmp52 New refCnts for V61: refCnt = 1, refCntWtd = 1 New refCnts for V67: refCnt = 3, refCntWtd = 1.50 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V68: refCnt = 3, refCntWtd = 1.50 [000355] ------------ * STMT void (IL 0x00C... ???) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 [000991] -A---------- | /--* ASG int [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 [000992] -A---+------ \--* COMMA void [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 [000988] -A---------- \--* ASG byref [000986] D------N---- \--* LCL_VAR byref V72 tmp63 New refCnts for V72: refCnt = 1, refCntWtd = 1 New refCnts for V61: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V62: refCnt = 2, refCntWtd = 2 [000359] ------------ * STMT void (IL 0x00C... ???) [001004] x----------- | /--* IND int [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001003] ------------ | | \--* ADD byref [001001] ------------ | | \--* LCL_VAR byref V00 arg0 [001005] -A---------- | /--* ASG int [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 [001006] -A---+------ \--* COMMA void [000998] x----------- | /--* IND byref [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000997] ------------ | | \--* ADD byref [000995] ------------ | | \--* LCL_VAR byref V00 arg0 [000999] -A---------- \--* ASG byref [000994] D------N---- \--* LCL_VAR byref V74 tmp65 New refCnts for V74: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 2 New refCnts for V75: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 4 [000363] ------------ * STMT void (IL 0x00C... ???) [000360] -----+------ | /--* CNS_INT int 0 [000362] -A---+------ \--* ASG bool [000361] D----+-N---- \--* LCL_VAR int V19 tmp10 New refCnts for V19: refCnt = 1, refCntWtd = 1 [000367] ------------ * STMT void (IL 0x00C... ???) [000364] -----+------ | /--* CNS_INT int 0 [000366] -A---+------ \--* ASG bool [000365] D----+-N---- \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 1, refCntWtd = 1 [000371] ------------ * STMT void (IL 0x00C... ???) [000368] -----+------ | /--* CNS_INT int 0 [000370] -A---+------ \--* ASG bool [000369] D----+-N---- \--* LCL_VAR int V20 tmp11 New refCnts for V20: refCnt = 1, refCntWtd = 1 [000384] ------------ * STMT void (IL 0x00C... ???) [000381] -----+------ | /--* CNS_INT int 0 [000383] -A---+------ \--* ASG int [000382] D----+-N---- \--* LCL_VAR int V22 tmp13 New refCnts for V22: refCnt = 1, refCntWtd = 1 [000379] ------------ * STMT void (IL 0x00C... ???) [000376] -----+------ | /--* LCL_VAR int V73 tmp64 [000378] -A---+------ \--* ASG int [000377] D----+-N---- \--* LCL_VAR int V22 tmp13 New refCnts for V22: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 2, refCntWtd = 2 [000294] ------------ * STMT void (IL 0x00C... ???) [000380] -----+------ | /--* LCL_VAR int V73 tmp64 [000293] -A---+------ \--* ASG int [000292] D----+-N---- \--* LCL_VAR int V18 tmp9 New refCnts for V18: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 3, refCntWtd = 3 [000397] ------------ * STMT void (IL 0x00C... ???) [000394] -----+------ | /--* CNS_INT int 0 [000396] -A---+------ \--* ASG int [000395] D----+-N---- \--* LCL_VAR int V23 tmp14 New refCnts for V23: refCnt = 1, refCntWtd = 1 [000392] ------------ * STMT void (IL 0x00C... ???) [000389] -----+------ | /--* LCL_VAR int V75 tmp66 [000391] -A---+------ \--* ASG int [000390] D----+-N---- \--* LCL_VAR int V23 tmp14 New refCnts for V23: refCnt = 2, refCntWtd = 2 New refCnts for V75: refCnt = 2, refCntWtd = 2 [000302] ------------ * STMT void (IL 0x00C... ???) [000393] -----+------ | /--* LCL_VAR int V75 tmp66 [000297] -----+------ | /--* NE int [000295] -----+------ | | \--* LCL_VAR int V73 tmp64 [000301] -A---+------ \--* ASG bool [000300] D----+-N---- \--* LCL_VAR int V19 tmp10 New refCnts for V19: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V75: refCnt = 3, refCntWtd = 3 [000307] ------------ * STMT void (IL 0x00C... ???) [000306] -----+------ \--* JTRUE void [000304] -----+------ | /--* CNS_INT int 0 [000305] J----+-N---- \--* EQ int [000303] -----+------ \--* LCL_VAR int V19 tmp10 New refCnts for V19: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB05 (weight=0.25) [000351] ------------ * STMT void (IL 0x00C... ???) [000348] -----+------ | /--* CNS_INT int 0 [000350] -A---+------ \--* ASG bool [000349] D----+-N---- \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 2, refCntWtd = 1.25 *** marking local variables in block BB06 (weight=0.25) [000410] ------------ * STMT void (IL 0x00C... ???) [000407] -----+------ | /--* CNS_INT int 0 [000409] -A---+------ \--* ASG int [000408] D----+-N---- \--* LCL_VAR int V24 tmp15 New refCnts for V24: refCnt = 1, refCntWtd = 0.25 [000405] ------------ * STMT void (IL 0x00C... ???) [000402] -----+------ | /--* LCL_VAR int V75 tmp66 [000404] -A---+------ \--* ASG int [000403] D----+-N---- \--* LCL_VAR int V24 tmp15 New refCnts for V24: refCnt = 2, refCntWtd = 0.50 New refCnts for V75: refCnt = 4, refCntWtd = 3.25 [000318] ------------ * STMT void (IL 0x00C... ???) [000314] -----+------ | /--* CNS_INT int 0 [000315] -----+------ | /--* EQ int [000406] -----+------ | | \--* LCL_VAR int V75 tmp66 [000317] -A---+------ \--* ASG bool [000316] D----+-N---- \--* LCL_VAR int V20 tmp11 New refCnts for V20: refCnt = 2, refCntWtd = 1.25 New refCnts for V75: refCnt = 5, refCntWtd = 3.50 [000323] ------------ * STMT void (IL 0x00C... ???) [000322] -----+------ \--* JTRUE void [000320] -----+------ | /--* CNS_INT int 0 [000321] J----+-N---- \--* EQ int [000319] -----+------ \--* LCL_VAR int V20 tmp11 New refCnts for V20: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB07 (weight=0.25) [000346] ------------ * STMT void (IL 0x00C... ???) [000343] -----+------ | /--* CNS_INT int 1 [000345] -A---+------ \--* ASG bool [000344] D----+-N---- \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB08 (weight=0.25) [000338] ------------ * STMT void (IL 0x00C... ???) [000334] -----+------ | /--* CNS_INT int 0 [000335] -ACXG+------ | /--* EQ int [000327] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001029] *------N---- | | | | \--* IND int [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001028] ------------ | | | | \--* ADD byref [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 [001032] -A---+----L- arg0 SETUP | | +--* COMMA void [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001022] *------N---- | | | | | \--* IND byref [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001021] ------------ | | | | | \--* ADD byref [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 [001025] -A---------- | | | \--* COMMA void [001015] L----------- | | | | /--* ADDR byref [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001018] -A---------- | | | \--* ASG byref [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001050] *------N---- | | | | \--* IND int [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001049] ------------ | | | | \--* ADD byref [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 [001053] -A---+----L- arg1 SETUP | | +--* COMMA void [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001043] *------N---- | | | | | \--* IND byref [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001042] ------------ | | | | | \--* ADD byref [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 [001046] -A---------- | | | \--* COMMA void [001036] L----------- | | | | /--* ADDR byref [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001039] -A---------- | | | \--* ASG byref [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 [001055] L----------- arg0 in rcx | | +--* ADDR byref [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001058] L----------- arg1 in rdx | | \--* ADDR byref [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000337] -ACXG+------ \--* ASG bool [000336] D----+-N---- \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 4, refCntWtd = 1.75 New refCnts for V98: refCnt = 1, refCntWtd = 0.50 New refCnts for V97: refCnt = 6, refCntWtd = 6.50 New refCnts for V98: refCnt = 2, refCntWtd = 1 New refCnts for V72: refCnt = 2, refCntWtd = 1.25 New refCnts for V98: refCnt = 3, refCntWtd = 1.50 New refCnts for V73: refCnt = 5, refCntWtd = 4.25 New refCnts for V100: refCnt = 1, refCntWtd = 0.50 New refCnts for V99: refCnt = 5, refCntWtd = 4.50 New refCnts for V100: refCnt = 2, refCntWtd = 1 New refCnts for V74: refCnt = 2, refCntWtd = 1.25 New refCnts for V100: refCnt = 3, refCntWtd = 1.50 New refCnts for V75: refCnt = 6, refCntWtd = 3.75 New refCnts for V97: refCnt = 7, refCntWtd = 7 New refCnts for V99: refCnt = 6, refCntWtd = 5 *** marking local variables in block BB09 (weight=1 ) [000024] ------------ * STMT void (IL ???... ???) [000340] -----+------ | /--* LCL_VAR int V21 tmp12 [000023] -A---+------ \--* ASG int [000022] D----+-N---- \--* LCL_VAR int V04 loc2 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 5, refCntWtd = 2.75 [000029] ------------ * STMT void (IL 0x014...0x015) [000028] -----+------ \--* JTRUE void [000026] -----+------ | /--* CNS_INT int 0 [000027] J----+-N---- \--* EQ int [000025] -----+------ \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 6, refCntWtd = 3.75 *** marking local variables in block BB10 (weight=0.50) [000160] ------------ * STMT void (IL 0x018...0x01A) [000157] -----+------ | /--* CNS_INT int 1 [000159] -A-XG+------ \--* ASG byte [000158] *--X-+-N---- \--* IND byte [000156] -----+------ \--* LCL_VAR byref V01 arg1 New refCnts for V01: refCnt = 1, refCntWtd = 0.50 [000164] ------------ * STMT void (IL 0x01B...0x01C) [000161] -----+------ | /--* CNS_INT int 1 [000163] -A---+------ \--* ASG int [000162] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 1, refCntWtd = 0.50 *** marking local variables in block BB11 (weight=0.50) [000471] ------------ * STMT void (IL 0x01F... ???) [000468] -----+------ | /--* CNS_INT int 0 [000470] -A---+------ \--* ASG bool [000469] D----+-N---- \--* LCL_VAR int V25 tmp16 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 [000418] ------------ * STMT void (IL 0x01F... ???) [000414] -----+------ | /--* CNS_INT ref null [000415] -----+------ | /--* EQ int [001063] -----+------ | | \--* NOP ref [001062] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000417] -A---+------ \--* ASG bool [000416] D----+-N---- \--* LCL_VAR int V25 tmp16 New refCnts for V25: refCnt = 2, refCntWtd = 1 [000423] ------------ * STMT void (IL 0x01F... ???) [000422] -----+------ \--* JTRUE void [000420] -----+------ | /--* CNS_INT int 0 [000421] J----+-N---- \--* EQ int [000419] -----+------ \--* LCL_VAR int V25 tmp16 New refCnts for V25: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB12 (weight=0.25) [000462] ------------ * STMT void (IL 0x01F... ???) [001068] ------------ | /--* CNS_INT int 0 [001069] -A---------- | /--* ASG int [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 [001070] -A---+------ \--* COMMA void [001065] ------------ | /--* CNS_INT byref 0 [001066] -A---------- \--* ASG byref [001064] D------N---- \--* LCL_VAR byref V80 tmp71 New refCnts for V80: refCnt = 1, refCntWtd = 0.25 New refCnts for V81: refCnt = 1, refCntWtd = 0.25 [000467] ------------ * STMT void (IL 0x01F... ???) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 [001076] -A---------- | /--* ASG int [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 [001077] -A---+------ \--* COMMA void [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 [001073] -A---------- \--* ASG byref [001071] D------N---- \--* LCL_VAR byref V78 tmp69 New refCnts for V78: refCnt = 1, refCntWtd = 0.25 New refCnts for V80: refCnt = 2, refCntWtd = 0.50 New refCnts for V79: refCnt = 1, refCntWtd = 0.25 New refCnts for V81: refCnt = 2, refCntWtd = 0.50 *** marking local variables in block BB13 (weight=0.25) [000434] ------------ * STMT void (IL 0x01F... ???) [001086] -----+------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] [001087] -----+------ | /--* ADD byref [001085] -----+------ | | \--* LCL_VAR ref V96 tmp87 [001088] -A-XG+-N---- | /--* COMMA byref [001083] ---X-+-N---- | | | /--* NULLCHECK byte [001082] -----+------ | | | | \--* LCL_VAR ref V96 tmp87 [001091] -A-X-------- | | \--* COMMA void [001090] -----+------ | | | /--* NOP ref [001089] -----+------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [001081] -A---+------ | | \--* ASG ref [001080] D----+-N---- | | \--* LCL_VAR ref V96 tmp87 [000433] -A-XG+------ \--* ASG byref [000432] D----+-N---- \--* LCL_VAR byref V26 tmp17 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V96: refCnt = 4, refCntWtd = 1 New refCnts for V96: refCnt = 5, refCntWtd = 1.25 New refCnts for V96: refCnt = 6, refCntWtd = 1.50 [000494] ------------ * STMT void (IL 0x01F... ???) [000491] -----+------ | /--* CNS_INT int 0 [000493] -A---+------ \--* ASG int [000492] D----+-N---- \--* LCL_VAR int V30 tmp21 New refCnts for V30: refCnt = 1, refCntWtd = 0.25 [000486] ------------ * STMT void (IL 0x01F... ???) [000483] x---G+------ | /--* IND int [001095] -----+------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] [001096] -----+------ | | \--* ADD byref [001098] -----+------ | | \--* NOP ref [001097] -----+------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] [000485] -A--G+------ \--* ASG int [000484] D----+-N---- \--* LCL_VAR int V30 tmp21 New refCnts for V30: refCnt = 2, refCntWtd = 0.50 [000440] ------------ * STMT void (IL 0x01F... ???) [001103] ------------ | /--* CNS_INT int 0 [001104] -A---------- | /--* ASG int [001102] D------N---- | | \--* LCL_VAR int V77 tmp68 [001105] -A---+------ \--* COMMA void [001100] ------------ | /--* CNS_INT byref 0 [001101] -A---------- \--* ASG byref [001099] D------N---- \--* LCL_VAR byref V76 tmp67 New refCnts for V76: refCnt = 1, refCntWtd = 0.25 New refCnts for V77: refCnt = 1, refCntWtd = 0.25 [000503] ------------ * STMT void (IL 0x01F... ???) [000501] --CXG+------ \--* CALL void System.Diagnostics.Debug.Assert [000497] -----+------ | /--* CNS_INT int 0 [000498] -----+------ arg0 in rcx \--* GE int [000487] -----+------ \--* LCL_VAR int V30 tmp21 New refCnts for V30: refCnt = 3, refCntWtd = 0.75 [000509] ------------ * STMT void (IL 0x01F... ???) [001109] ------------ | /--* CNS_INT byref 0 [001110] -A---+------ \--* ASG byref [001108] D------N---- \--* LCL_VAR byref V82 tmp73 New refCnts for V82: refCnt = 1, refCntWtd = 0.25 [000515] ------------ * STMT void (IL 0x01F... ???) [000435] -----+------ | /--* LCL_VAR byref V26 tmp17 [000513] -A---+------ \--* ASG byref [000512] D----+-N---- \--* LCL_VAR byref V82 tmp73 New refCnts for V82: refCnt = 2, refCntWtd = 0.50 New refCnts for V26: refCnt = 2, refCntWtd = 1 [000520] ------------ * STMT void (IL 0x01F... ???) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 [001113] -A---+------ \--* ASG byref [001111] D------N---- \--* LCL_VAR byref V76 tmp67 New refCnts for V76: refCnt = 2, refCntWtd = 0.50 New refCnts for V82: refCnt = 3, refCntWtd = 0.75 [000526] ------------ * STMT void (IL 0x01F... ???) [000523] -----+------ | /--* LCL_VAR int V30 tmp21 [000525] -A---+------ \--* ASG int [000524] D----+-N---- \--* LCL_VAR int V77 tmp68 New refCnts for V77: refCnt = 2, refCntWtd = 0.50 New refCnts for V30: refCnt = 4, refCntWtd = 1 [000451] ------------ * STMT void (IL 0x01F... ???) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 [001119] -A---------- | /--* ASG int [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 [001120] -A---+------ \--* COMMA void [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 [001116] -A---------- \--* ASG byref [001114] D------N---- \--* LCL_VAR byref V78 tmp69 New refCnts for V78: refCnt = 2, refCntWtd = 0.50 New refCnts for V76: refCnt = 3, refCntWtd = 0.75 New refCnts for V79: refCnt = 2, refCntWtd = 0.50 New refCnts for V77: refCnt = 3, refCntWtd = 0.75 *** marking local variables in block BB14 (weight=0.50) [000039] ------------ * STMT void (IL ???... ???) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 [001126] -A---------- | /--* ASG int [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 [001127] -A---+------ \--* COMMA void [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 [001123] -A---------- \--* ASG byref [001121] D------N---- \--* LCL_VAR byref V63 tmp54 New refCnts for V63: refCnt = 1, refCntWtd = 0.50 New refCnts for V78: refCnt = 3, refCntWtd = 1 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V79: refCnt = 3, refCntWtd = 1 [000602] ------------ * STMT void (IL 0x02A... ???) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 [001133] -A---------- | /--* ASG int [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 [001134] -A---+------ \--* COMMA void [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 [001130] -A---------- \--* ASG byref [001128] D------N---- \--* LCL_VAR byref V83 tmp74 New refCnts for V83: refCnt = 1, refCntWtd = 0.50 New refCnts for V63: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 1, refCntWtd = 0.50 New refCnts for V64: refCnt = 2, refCntWtd = 1 [000606] ------------ * STMT void (IL 0x02A... ???) [001146] x----------- | /--* IND int [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001145] ------------ | | \--* ADD byref [001143] ------------ | | \--* LCL_VAR byref V00 arg0 [001147] -A---------- | /--* ASG int [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 [001148] -A---+------ \--* COMMA void [001140] x----------- | /--* IND byref [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001139] ------------ | | \--* ADD byref [001137] ------------ | | \--* LCL_VAR byref V00 arg0 [001141] -A---------- \--* ASG byref [001136] D------N---- \--* LCL_VAR byref V85 tmp76 New refCnts for V85: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 3, refCntWtd = 5 New refCnts for V86: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 4, refCntWtd = 6 [000610] ------------ * STMT void (IL 0x02A... ???) [000607] -----+------ | /--* CNS_INT int 0 [000609] -A---+------ \--* ASG bool [000608] D----+-N---- \--* LCL_VAR int V35 tmp26 New refCnts for V35: refCnt = 1, refCntWtd = 0.50 [000614] ------------ * STMT void (IL 0x02A... ???) [000611] -----+------ | /--* CNS_INT int 0 [000613] -A---+------ \--* ASG bool [000612] D----+-N---- \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 1, refCntWtd = 0.50 [000618] ------------ * STMT void (IL 0x02A... ???) [000615] -----+------ | /--* CNS_INT int 0 [000617] -A---+------ \--* ASG bool [000616] D----+-N---- \--* LCL_VAR int V36 tmp27 New refCnts for V36: refCnt = 1, refCntWtd = 0.50 [000631] ------------ * STMT void (IL 0x02A... ???) [000628] -----+------ | /--* CNS_INT int 0 [000630] -A---+------ \--* ASG int [000629] D----+-N---- \--* LCL_VAR int V38 tmp29 New refCnts for V38: refCnt = 1, refCntWtd = 0.50 [000626] ------------ * STMT void (IL 0x02A... ???) [000623] -----+------ | /--* LCL_VAR int V84 tmp75 [000625] -A---+------ \--* ASG int [000624] D----+-N---- \--* LCL_VAR int V38 tmp29 New refCnts for V38: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 2, refCntWtd = 1 [000541] ------------ * STMT void (IL 0x02A... ???) [000627] -----+------ | /--* LCL_VAR int V84 tmp75 [000540] -A---+------ \--* ASG int [000539] D----+-N---- \--* LCL_VAR int V34 tmp25 New refCnts for V34: refCnt = 1, refCntWtd = 1 New refCnts for V84: refCnt = 3, refCntWtd = 1.50 [000644] ------------ * STMT void (IL 0x02A... ???) [000641] -----+------ | /--* CNS_INT int 0 [000643] -A---+------ \--* ASG int [000642] D----+-N---- \--* LCL_VAR int V39 tmp30 New refCnts for V39: refCnt = 1, refCntWtd = 0.50 [000639] ------------ * STMT void (IL 0x02A... ???) [000636] -----+------ | /--* LCL_VAR int V86 tmp77 [000638] -A---+------ \--* ASG int [000637] D----+-N---- \--* LCL_VAR int V39 tmp30 New refCnts for V39: refCnt = 2, refCntWtd = 1 New refCnts for V86: refCnt = 2, refCntWtd = 1 [000549] ------------ * STMT void (IL 0x02A... ???) [000640] -----+------ | /--* LCL_VAR int V86 tmp77 [000544] -----+------ | /--* NE int [000542] -----+------ | | \--* LCL_VAR int V84 tmp75 [000548] -A---+------ \--* ASG bool [000547] D----+-N---- \--* LCL_VAR int V35 tmp26 New refCnts for V35: refCnt = 2, refCntWtd = 1 New refCnts for V84: refCnt = 4, refCntWtd = 2 New refCnts for V86: refCnt = 3, refCntWtd = 1.50 [000554] ------------ * STMT void (IL 0x02A... ???) [000553] -----+------ \--* JTRUE void [000551] -----+------ | /--* CNS_INT int 0 [000552] J----+-N---- \--* EQ int [000550] -----+------ \--* LCL_VAR int V35 tmp26 New refCnts for V35: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB15 (weight=0.25) [000598] ------------ * STMT void (IL 0x02A... ???) [000595] -----+------ | /--* CNS_INT int 0 [000597] -A---+------ \--* ASG bool [000596] D----+-N---- \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 2, refCntWtd = 0.75 *** marking local variables in block BB16 (weight=0.25) [000657] ------------ * STMT void (IL 0x02A... ???) [000654] -----+------ | /--* CNS_INT int 0 [000656] -A---+------ \--* ASG int [000655] D----+-N---- \--* LCL_VAR int V40 tmp31 New refCnts for V40: refCnt = 1, refCntWtd = 0.25 [000652] ------------ * STMT void (IL 0x02A... ???) [000649] -----+------ | /--* LCL_VAR int V86 tmp77 [000651] -A---+------ \--* ASG int [000650] D----+-N---- \--* LCL_VAR int V40 tmp31 New refCnts for V40: refCnt = 2, refCntWtd = 0.50 New refCnts for V86: refCnt = 4, refCntWtd = 1.75 [000565] ------------ * STMT void (IL 0x02A... ???) [000561] -----+------ | /--* CNS_INT int 0 [000562] -----+------ | /--* EQ int [000653] -----+------ | | \--* LCL_VAR int V86 tmp77 [000564] -A---+------ \--* ASG bool [000563] D----+-N---- \--* LCL_VAR int V36 tmp27 New refCnts for V36: refCnt = 2, refCntWtd = 0.75 New refCnts for V86: refCnt = 5, refCntWtd = 2 [000570] ------------ * STMT void (IL 0x02A... ???) [000569] -----+------ \--* JTRUE void [000567] -----+------ | /--* CNS_INT int 0 [000568] J----+-N---- \--* EQ int [000566] -----+------ \--* LCL_VAR int V36 tmp27 New refCnts for V36: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB17 (weight=0.25) [000593] ------------ * STMT void (IL 0x02A... ???) [000590] -----+------ | /--* CNS_INT int 1 [000592] -A---+------ \--* ASG bool [000591] D----+-N---- \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB18 (weight=0.25) [000585] ------------ * STMT void (IL 0x02A... ???) [000581] -----+------ | /--* CNS_INT int 0 [000582] -ACXG+------ | /--* EQ int [000574] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001171] *------N---- | | | | \--* IND int [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001170] ------------ | | | | \--* ADD byref [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 [001174] -A---+----L- arg0 SETUP | | +--* COMMA void [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001164] *------N---- | | | | | \--* IND byref [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001163] ------------ | | | | | \--* ADD byref [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 [001167] -A---------- | | | \--* COMMA void [001157] L----------- | | | | /--* ADDR byref [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001160] -A---------- | | | \--* ASG byref [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001192] *------N---- | | | | \--* IND int [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001191] ------------ | | | | \--* ADD byref [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 [001195] -A---+----L- arg1 SETUP | | +--* COMMA void [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001185] *------N---- | | | | | \--* IND byref [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001184] ------------ | | | | | \--* ADD byref [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 [001188] -A---------- | | | \--* COMMA void [001178] L----------- | | | | /--* ADDR byref [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001181] -A---------- | | | \--* ASG byref [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 [001197] L----------- arg0 in rcx | | +--* ADDR byref [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001200] L----------- arg1 in rdx | | \--* ADDR byref [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000584] -ACXG+------ \--* ASG bool [000583] D----+-N---- \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 4, refCntWtd = 1.25 New refCnts for V101: refCnt = 1, refCntWtd = 0.50 New refCnts for V97: refCnt = 8, refCntWtd = 7.50 New refCnts for V101: refCnt = 2, refCntWtd = 1 New refCnts for V83: refCnt = 2, refCntWtd = 0.75 New refCnts for V101: refCnt = 3, refCntWtd = 1.50 New refCnts for V84: refCnt = 5, refCntWtd = 2.25 New refCnts for V102: refCnt = 1, refCntWtd = 0.50 New refCnts for V99: refCnt = 7, refCntWtd = 5.50 New refCnts for V102: refCnt = 2, refCntWtd = 1 New refCnts for V85: refCnt = 2, refCntWtd = 0.75 New refCnts for V102: refCnt = 3, refCntWtd = 1.50 New refCnts for V86: refCnt = 6, refCntWtd = 2.25 New refCnts for V97: refCnt = 9, refCntWtd = 8 New refCnts for V99: refCnt = 8, refCntWtd = 6 *** marking local variables in block BB19 (weight=0.50) [000054] ------------ * STMT void (IL ???... ???) [000587] -----+------ | /--* LCL_VAR int V37 tmp28 [000053] -A---+------ \--* ASG int [000052] D----+-N---- \--* LCL_VAR int V06 loc4 New refCnts for V06: refCnt = 1, refCntWtd = 0.50 New refCnts for V37: refCnt = 5, refCntWtd = 1.75 [000059] ------------ * STMT void (IL 0x033...0x035) [000058] -----+------ \--* JTRUE void [000056] -----+------ | /--* CNS_INT int 0 [000057] J----+-N---- \--* EQ int [000055] -----+------ \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 6, refCntWtd = 2.25 *** marking local variables in block BB20 (weight=0.50) [000150] ------------ * STMT void (IL 0x038...0x03A) [000147] -----+------ | /--* CNS_INT int 0 [000149] -A-XG+------ \--* ASG byte [000148] *--X-+-N---- \--* IND byte [000146] -----+------ \--* LCL_VAR byref V01 arg1 New refCnts for V01: refCnt = 2, refCntWtd = 1 [000154] ------------ * STMT void (IL 0x03B...0x03C) [000151] -----+------ | /--* CNS_INT int 1 [000153] -A---+------ \--* ASG int [000152] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB21 (weight=0.50) [000069] ------------ * STMT void (IL 0x03F...0x045) [000062] SACXG+------ \--* CALL void System.Boolean.TrimWhiteSpaceAndNull [000066] -----+------ | /--* LCL_VAR byref V00 arg0 [001206] -A--------L- arg0 SETUP +--* ASG byref [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 [000064] x----+-N---- | /--* IND struct [000061] -----+------ | | \--* LCL_VAR byref V00 arg0 [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 [001210] L----------- arg1 in rdx \--* ADDR byref [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 New refCnts for V103: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 5, refCntWtd = 7 New refCnts for V97: refCnt = 10, refCntWtd = 9 New refCnts for V00: refCnt = 6, refCntWtd = 8 New refCnts for V103: refCnt = 2, refCntWtd = 2 New refCnts for V97: refCnt = 11, refCntWtd = 10 [000732] ------------ * STMT void (IL 0x047... ???) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 [001217] -A---------- | /--* ASG int [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 [001218] -A---+------ \--* COMMA void [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 [001214] -A---------- \--* ASG byref [001212] D------N---- \--* LCL_VAR byref V87 tmp78 New refCnts for V87: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 3, refCntWtd = 2.50 New refCnts for V88: refCnt = 1, refCntWtd = 0.50 New refCnts for V62: refCnt = 3, refCntWtd = 2.50 [000736] ------------ * STMT void (IL 0x047... ???) [001230] x----------- | /--* IND int [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001229] ------------ | | \--* ADD byref [001227] ------------ | | \--* LCL_VAR byref V00 arg0 [001231] -A---------- | /--* ASG int [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 [001232] -A---+------ \--* COMMA void [001224] x----------- | /--* IND byref [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001223] ------------ | | \--* ADD byref [001221] ------------ | | \--* LCL_VAR byref V00 arg0 [001225] -A---------- \--* ASG byref [001220] D------N---- \--* LCL_VAR byref V89 tmp80 New refCnts for V89: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 7, refCntWtd = 9 New refCnts for V90: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 8, refCntWtd = 10 [000740] ------------ * STMT void (IL 0x047... ???) [000737] -----+------ | /--* CNS_INT int 0 [000739] -A---+------ \--* ASG bool [000738] D----+-N---- \--* LCL_VAR int V44 tmp35 New refCnts for V44: refCnt = 1, refCntWtd = 0.50 [000744] ------------ * STMT void (IL 0x047... ???) [000741] -----+------ | /--* CNS_INT int 0 [000743] -A---+------ \--* ASG bool [000742] D----+-N---- \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 [000748] ------------ * STMT void (IL 0x047... ???) [000745] -----+------ | /--* CNS_INT int 0 [000747] -A---+------ \--* ASG bool [000746] D----+-N---- \--* LCL_VAR int V45 tmp36 New refCnts for V45: refCnt = 1, refCntWtd = 0.50 [000761] ------------ * STMT void (IL 0x047... ???) [000758] -----+------ | /--* CNS_INT int 0 [000760] -A---+------ \--* ASG int [000759] D----+-N---- \--* LCL_VAR int V47 tmp38 New refCnts for V47: refCnt = 1, refCntWtd = 0.50 [000756] ------------ * STMT void (IL 0x047... ???) [000753] -----+------ | /--* LCL_VAR int V88 tmp79 [000755] -A---+------ \--* ASG int [000754] D----+-N---- \--* LCL_VAR int V47 tmp38 New refCnts for V47: refCnt = 2, refCntWtd = 1 New refCnts for V88: refCnt = 2, refCntWtd = 1 [000671] ------------ * STMT void (IL 0x047... ???) [000757] -----+------ | /--* LCL_VAR int V88 tmp79 [000670] -A---+------ \--* ASG int [000669] D----+-N---- \--* LCL_VAR int V43 tmp34 New refCnts for V43: refCnt = 1, refCntWtd = 1 New refCnts for V88: refCnt = 3, refCntWtd = 1.50 [000774] ------------ * STMT void (IL 0x047... ???) [000771] -----+------ | /--* CNS_INT int 0 [000773] -A---+------ \--* ASG int [000772] D----+-N---- \--* LCL_VAR int V48 tmp39 New refCnts for V48: refCnt = 1, refCntWtd = 0.50 [000769] ------------ * STMT void (IL 0x047... ???) [000766] -----+------ | /--* LCL_VAR int V90 tmp81 [000768] -A---+------ \--* ASG int [000767] D----+-N---- \--* LCL_VAR int V48 tmp39 New refCnts for V48: refCnt = 2, refCntWtd = 1 New refCnts for V90: refCnt = 2, refCntWtd = 1 [000679] ------------ * STMT void (IL 0x047... ???) [000770] -----+------ | /--* LCL_VAR int V90 tmp81 [000674] -----+------ | /--* NE int [000672] -----+------ | | \--* LCL_VAR int V88 tmp79 [000678] -A---+------ \--* ASG bool [000677] D----+-N---- \--* LCL_VAR int V44 tmp35 New refCnts for V44: refCnt = 2, refCntWtd = 1 New refCnts for V88: refCnt = 4, refCntWtd = 2 New refCnts for V90: refCnt = 3, refCntWtd = 1.50 [000684] ------------ * STMT void (IL 0x047... ???) [000683] -----+------ \--* JTRUE void [000681] -----+------ | /--* CNS_INT int 0 [000682] J----+-N---- \--* EQ int [000680] -----+------ \--* LCL_VAR int V44 tmp35 New refCnts for V44: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB22 (weight=0.25) [000728] ------------ * STMT void (IL 0x047... ???) [000725] -----+------ | /--* CNS_INT int 0 [000727] -A---+------ \--* ASG bool [000726] D----+-N---- \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 2, refCntWtd = 0.75 *** marking local variables in block BB23 (weight=0.25) [000787] ------------ * STMT void (IL 0x047... ???) [000784] -----+------ | /--* CNS_INT int 0 [000786] -A---+------ \--* ASG int [000785] D----+-N---- \--* LCL_VAR int V49 tmp40 New refCnts for V49: refCnt = 1, refCntWtd = 0.25 [000782] ------------ * STMT void (IL 0x047... ???) [000779] -----+------ | /--* LCL_VAR int V90 tmp81 [000781] -A---+------ \--* ASG int [000780] D----+-N---- \--* LCL_VAR int V49 tmp40 New refCnts for V49: refCnt = 2, refCntWtd = 0.50 New refCnts for V90: refCnt = 4, refCntWtd = 1.75 [000695] ------------ * STMT void (IL 0x047... ???) [000691] -----+------ | /--* CNS_INT int 0 [000692] -----+------ | /--* EQ int [000783] -----+------ | | \--* LCL_VAR int V90 tmp81 [000694] -A---+------ \--* ASG bool [000693] D----+-N---- \--* LCL_VAR int V45 tmp36 New refCnts for V45: refCnt = 2, refCntWtd = 0.75 New refCnts for V90: refCnt = 5, refCntWtd = 2 [000700] ------------ * STMT void (IL 0x047... ???) [000699] -----+------ \--* JTRUE void [000697] -----+------ | /--* CNS_INT int 0 [000698] J----+-N---- \--* EQ int [000696] -----+------ \--* LCL_VAR int V45 tmp36 New refCnts for V45: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB24 (weight=0.25) [000723] ------------ * STMT void (IL 0x047... ???) [000720] -----+------ | /--* CNS_INT int 1 [000722] -A---+------ \--* ASG bool [000721] D----+-N---- \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB25 (weight=0.25) [000715] ------------ * STMT void (IL 0x047... ???) [000711] -----+------ | /--* CNS_INT int 0 [000712] -ACXG+------ | /--* EQ int [000704] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001255] *------N---- | | | | \--* IND int [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001254] ------------ | | | | \--* ADD byref [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 [001258] -A---+----L- arg0 SETUP | | +--* COMMA void [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001248] *------N---- | | | | | \--* IND byref [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001247] ------------ | | | | | \--* ADD byref [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 [001251] -A---------- | | | \--* COMMA void [001241] L----------- | | | | /--* ADDR byref [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001244] -A---------- | | | \--* ASG byref [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001276] *------N---- | | | | \--* IND int [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001275] ------------ | | | | \--* ADD byref [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 [001279] -A---+----L- arg1 SETUP | | +--* COMMA void [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001269] *------N---- | | | | | \--* IND byref [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001268] ------------ | | | | | \--* ADD byref [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 [001272] -A---------- | | | \--* COMMA void [001262] L----------- | | | | /--* ADDR byref [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001265] -A---------- | | | \--* ASG byref [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 [001281] L----------- arg0 in rcx | | +--* ADDR byref [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001284] L----------- arg1 in rdx | | \--* ADDR byref [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000714] -ACXG+------ \--* ASG bool [000713] D----+-N---- \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 4, refCntWtd = 1.25 New refCnts for V104: refCnt = 1, refCntWtd = 0.50 New refCnts for V97: refCnt = 12, refCntWtd = 10.50 New refCnts for V104: refCnt = 2, refCntWtd = 1 New refCnts for V87: refCnt = 2, refCntWtd = 0.75 New refCnts for V104: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 5, refCntWtd = 2.25 New refCnts for V105: refCnt = 1, refCntWtd = 0.50 New refCnts for V99: refCnt = 9, refCntWtd = 6.50 New refCnts for V105: refCnt = 2, refCntWtd = 1 New refCnts for V89: refCnt = 2, refCntWtd = 0.75 New refCnts for V105: refCnt = 3, refCntWtd = 1.50 New refCnts for V90: refCnt = 6, refCntWtd = 2.25 New refCnts for V97: refCnt = 13, refCntWtd = 11 New refCnts for V99: refCnt = 10, refCntWtd = 7 *** marking local variables in block BB26 (weight=0.50) [000084] ------------ * STMT void (IL ???... ???) [000717] -----+------ | /--* LCL_VAR int V46 tmp37 [000083] -A---+------ \--* ASG int [000082] D----+-N---- \--* LCL_VAR int V07 loc5 New refCnts for V07: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 5, refCntWtd = 1.75 [000089] ------------ * STMT void (IL 0x050...0x052) [000088] -----+------ \--* JTRUE void [000086] -----+------ | /--* CNS_INT int 0 [000087] J----+-N---- \--* EQ int [000085] -----+------ \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 6, refCntWtd = 2.25 *** marking local variables in block BB27 (weight=0.50) [000140] ------------ * STMT void (IL 0x055...0x057) [000137] -----+------ | /--* CNS_INT int 1 [000139] -A-XG+------ \--* ASG byte [000138] *--X-+-N---- \--* IND byte [000136] -----+------ \--* LCL_VAR byref V01 arg1 New refCnts for V01: refCnt = 3, refCntWtd = 1.50 [000144] ------------ * STMT void (IL 0x058...0x059) [000141] -----+------ | /--* CNS_INT int 1 [000143] -A---+------ \--* ASG int [000142] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB28 (weight=0.50) [000862] ------------ * STMT void (IL 0x05C... ???) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 [001292] -A---------- | /--* ASG int [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 [001293] -A---+------ \--* COMMA void [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 [001289] -A---------- \--* ASG byref [001287] D------N---- \--* LCL_VAR byref V91 tmp82 New refCnts for V91: refCnt = 1, refCntWtd = 0.50 New refCnts for V63: refCnt = 3, refCntWtd = 1.50 New refCnts for V92: refCnt = 1, refCntWtd = 0.50 New refCnts for V64: refCnt = 3, refCntWtd = 1.50 [000866] ------------ * STMT void (IL 0x05C... ???) [001305] x----------- | /--* IND int [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [001304] ------------ | | \--* ADD byref [001302] ------------ | | \--* LCL_VAR byref V00 arg0 [001306] -A---------- | /--* ASG int [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 [001307] -A---+------ \--* COMMA void [001299] x----------- | /--* IND byref [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [001298] ------------ | | \--* ADD byref [001296] ------------ | | \--* LCL_VAR byref V00 arg0 [001300] -A---------- \--* ASG byref [001295] D------N---- \--* LCL_VAR byref V93 tmp84 New refCnts for V93: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 9, refCntWtd = 11 New refCnts for V94: refCnt = 1, refCntWtd = 0.50 New refCnts for V00: refCnt = 10, refCntWtd = 12 [000870] ------------ * STMT void (IL 0x05C... ???) [000867] -----+------ | /--* CNS_INT int 0 [000869] -A---+------ \--* ASG bool [000868] D----+-N---- \--* LCL_VAR int V53 tmp44 New refCnts for V53: refCnt = 1, refCntWtd = 0.50 [000874] ------------ * STMT void (IL 0x05C... ???) [000871] -----+------ | /--* CNS_INT int 0 [000873] -A---+------ \--* ASG bool [000872] D----+-N---- \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 [000878] ------------ * STMT void (IL 0x05C... ???) [000875] -----+------ | /--* CNS_INT int 0 [000877] -A---+------ \--* ASG bool [000876] D----+-N---- \--* LCL_VAR int V54 tmp45 New refCnts for V54: refCnt = 1, refCntWtd = 0.50 [000891] ------------ * STMT void (IL 0x05C... ???) [000888] -----+------ | /--* CNS_INT int 0 [000890] -A---+------ \--* ASG int [000889] D----+-N---- \--* LCL_VAR int V56 tmp47 New refCnts for V56: refCnt = 1, refCntWtd = 0.50 [000886] ------------ * STMT void (IL 0x05C... ???) [000883] -----+------ | /--* LCL_VAR int V92 tmp83 [000885] -A---+------ \--* ASG int [000884] D----+-N---- \--* LCL_VAR int V56 tmp47 New refCnts for V56: refCnt = 2, refCntWtd = 1 New refCnts for V92: refCnt = 2, refCntWtd = 1 [000801] ------------ * STMT void (IL 0x05C... ???) [000887] -----+------ | /--* LCL_VAR int V92 tmp83 [000800] -A---+------ \--* ASG int [000799] D----+-N---- \--* LCL_VAR int V52 tmp43 New refCnts for V52: refCnt = 1, refCntWtd = 1 New refCnts for V92: refCnt = 3, refCntWtd = 1.50 [000904] ------------ * STMT void (IL 0x05C... ???) [000901] -----+------ | /--* CNS_INT int 0 [000903] -A---+------ \--* ASG int [000902] D----+-N---- \--* LCL_VAR int V57 tmp48 New refCnts for V57: refCnt = 1, refCntWtd = 0.50 [000899] ------------ * STMT void (IL 0x05C... ???) [000896] -----+------ | /--* LCL_VAR int V94 tmp85 [000898] -A---+------ \--* ASG int [000897] D----+-N---- \--* LCL_VAR int V57 tmp48 New refCnts for V57: refCnt = 2, refCntWtd = 1 New refCnts for V94: refCnt = 2, refCntWtd = 1 [000809] ------------ * STMT void (IL 0x05C... ???) [000900] -----+------ | /--* LCL_VAR int V94 tmp85 [000804] -----+------ | /--* NE int [000802] -----+------ | | \--* LCL_VAR int V92 tmp83 [000808] -A---+------ \--* ASG bool [000807] D----+-N---- \--* LCL_VAR int V53 tmp44 New refCnts for V53: refCnt = 2, refCntWtd = 1 New refCnts for V92: refCnt = 4, refCntWtd = 2 New refCnts for V94: refCnt = 3, refCntWtd = 1.50 [000814] ------------ * STMT void (IL 0x05C... ???) [000813] -----+------ \--* JTRUE void [000811] -----+------ | /--* CNS_INT int 0 [000812] J----+-N---- \--* EQ int [000810] -----+------ \--* LCL_VAR int V53 tmp44 New refCnts for V53: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB29 (weight=0.25) [000858] ------------ * STMT void (IL 0x05C... ???) [000855] -----+------ | /--* CNS_INT int 0 [000857] -A---+------ \--* ASG bool [000856] D----+-N---- \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 2, refCntWtd = 0.75 *** marking local variables in block BB30 (weight=0.25) [000917] ------------ * STMT void (IL 0x05C... ???) [000914] -----+------ | /--* CNS_INT int 0 [000916] -A---+------ \--* ASG int [000915] D----+-N---- \--* LCL_VAR int V58 tmp49 New refCnts for V58: refCnt = 1, refCntWtd = 0.25 [000912] ------------ * STMT void (IL 0x05C... ???) [000909] -----+------ | /--* LCL_VAR int V94 tmp85 [000911] -A---+------ \--* ASG int [000910] D----+-N---- \--* LCL_VAR int V58 tmp49 New refCnts for V58: refCnt = 2, refCntWtd = 0.50 New refCnts for V94: refCnt = 4, refCntWtd = 1.75 [000825] ------------ * STMT void (IL 0x05C... ???) [000821] -----+------ | /--* CNS_INT int 0 [000822] -----+------ | /--* EQ int [000913] -----+------ | | \--* LCL_VAR int V94 tmp85 [000824] -A---+------ \--* ASG bool [000823] D----+-N---- \--* LCL_VAR int V54 tmp45 New refCnts for V54: refCnt = 2, refCntWtd = 0.75 New refCnts for V94: refCnt = 5, refCntWtd = 2 [000830] ------------ * STMT void (IL 0x05C... ???) [000829] -----+------ \--* JTRUE void [000827] -----+------ | /--* CNS_INT int 0 [000828] J----+-N---- \--* EQ int [000826] -----+------ \--* LCL_VAR int V54 tmp45 New refCnts for V54: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB31 (weight=0.25) [000853] ------------ * STMT void (IL 0x05C... ???) [000850] -----+------ | /--* CNS_INT int 1 [000852] -A---+------ \--* ASG bool [000851] D----+-N---- \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 3, refCntWtd = 1 *** marking local variables in block BB32 (weight=0.25) [000845] ------------ * STMT void (IL 0x05C... ???) [000841] -----+------ | /--* CNS_INT int 0 [000842] -ACXG+------ | /--* EQ int [000834] -ACXG+------ | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 [001330] *------N---- | | | | \--* IND int [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001329] ------------ | | | | \--* ADD byref [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 [001333] -A---+----L- arg0 SETUP | | +--* COMMA void [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 [001323] *------N---- | | | | | \--* IND byref [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001322] ------------ | | | | | \--* ADD byref [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 [001326] -A---------- | | | \--* COMMA void [001316] L----------- | | | | /--* ADDR byref [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 [001319] -A---------- | | | \--* ASG byref [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 [001351] *------N---- | | | | \--* IND int [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] [001350] ------------ | | | | \--* ADD byref [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 [001354] -A---+----L- arg1 SETUP | | +--* COMMA void [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 [001344] *------N---- | | | | | \--* IND byref [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] [001343] ------------ | | | | | \--* ADD byref [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 [001347] -A---------- | | | \--* COMMA void [001337] L----------- | | | | /--* ADDR byref [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 [001340] -A---------- | | | \--* ASG byref [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 [001356] L----------- arg0 in rcx | | +--* ADDR byref [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 [001359] L----------- arg1 in rdx | | \--* ADDR byref [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 [000844] -ACXG+------ \--* ASG bool [000843] D----+-N---- \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 4, refCntWtd = 1.25 New refCnts for V106: refCnt = 1, refCntWtd = 0.50 New refCnts for V97: refCnt = 14, refCntWtd = 11.50 New refCnts for V106: refCnt = 2, refCntWtd = 1 New refCnts for V91: refCnt = 2, refCntWtd = 0.75 New refCnts for V106: refCnt = 3, refCntWtd = 1.50 New refCnts for V92: refCnt = 5, refCntWtd = 2.25 New refCnts for V107: refCnt = 1, refCntWtd = 0.50 New refCnts for V99: refCnt = 11, refCntWtd = 7.50 New refCnts for V107: refCnt = 2, refCntWtd = 1 New refCnts for V93: refCnt = 2, refCntWtd = 0.75 New refCnts for V107: refCnt = 3, refCntWtd = 1.50 New refCnts for V94: refCnt = 6, refCntWtd = 2.25 New refCnts for V97: refCnt = 15, refCntWtd = 12 New refCnts for V99: refCnt = 12, refCntWtd = 8 *** marking local variables in block BB33 (weight=0.50) [000105] ------------ * STMT void (IL ???... ???) [000847] -----+------ | /--* LCL_VAR int V55 tmp46 [000104] -A---+------ \--* ASG int [000103] D----+-N---- \--* LCL_VAR int V08 loc6 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V55: refCnt = 5, refCntWtd = 1.75 [000110] ------------ * STMT void (IL 0x065...0x067) [000109] -----+------ \--* JTRUE void [000107] -----+------ | /--* CNS_INT int 0 [000108] J----+-N---- \--* EQ int [000106] -----+------ \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 6, refCntWtd = 2.25 *** marking local variables in block BB34 (weight=0.50) [000130] ------------ * STMT void (IL 0x06A...0x06C) [000127] -----+------ | /--* CNS_INT int 0 [000129] -A-XG+------ \--* ASG byte [000128] *--X-+-N---- \--* IND byte [000126] -----+------ \--* LCL_VAR byref V01 arg1 New refCnts for V01: refCnt = 4, refCntWtd = 2 [000134] ------------ * STMT void (IL 0x06D...0x06E) [000131] -----+------ | /--* CNS_INT int 1 [000133] -A---+------ \--* ASG int [000132] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB35 (weight=0.50) [000116] ------------ * STMT void (IL 0x071...0x073) [000113] -----+------ | /--* CNS_INT int 0 [000115] -A-XG+------ \--* ASG byte [000114] *--X-+-N---- \--* IND byte [000112] -----+------ \--* LCL_VAR byref V01 arg1 New refCnts for V01: refCnt = 5, refCntWtd = 2.50 [000120] ------------ * STMT void (IL 0x074...0x075) [000117] -----+------ | /--* CNS_INT int 0 [000119] -A---+------ \--* ASG int [000118] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 5, refCntWtd = 2.50 *** marking local variables in block BB36 (weight=1 ) [000124] ------------ * STMT void (IL 0x078...0x079) [000123] -----+------ \--* RETURN int [000122] -----+------ \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 6, refCntWtd = 3.50 New refCnts for V00: refCnt = 11, refCntWtd = 14 New refCnts for V00: refCnt = 12, refCntWtd = 16 New refCnts for V01: refCnt = 6, refCntWtd = 3.50 New refCnts for V01: refCnt = 7, refCntWtd = 4.50 *************** In optAddCopies() Local V59 should not be enregistered because: field of a dependently promoted struct Local V60 should not be enregistered because: field of a dependently promoted struct refCnt table for 'TryParse': V00 arg0 [ byref]: refCnt = 12, refCntWtd = 16 pref [rcx] V01 arg1 [ byref]: refCnt = 7, refCntWtd = 4.50 pref [rdx] V73 tmp64 [ int]: refCnt = 5, refCntWtd = 4.25 V21 tmp12 [ bool]: refCnt = 6, refCntWtd = 3.75 V75 tmp66 [ int]: refCnt = 6, refCntWtd = 3.75 V05 loc3 [ bool]: refCnt = 6, refCntWtd = 3.50 V09 tmp0 [ bool]: refCnt = 3, refCntWtd = 3 V19 tmp10 [ bool]: refCnt = 3, refCntWtd = 3 V61 tmp52 [ byref]: refCnt = 3, refCntWtd = 2.50 V62 tmp53 [ int]: refCnt = 3, refCntWtd = 2.50 V37 tmp28 [ bool]: refCnt = 6, refCntWtd = 2.25 V46 tmp37 [ bool]: refCnt = 6, refCntWtd = 2.25 V55 tmp46 [ bool]: refCnt = 6, refCntWtd = 2.25 V86 tmp77 [ int]: refCnt = 6, refCntWtd = 2.25 V90 tmp81 [ int]: refCnt = 6, refCntWtd = 2.25 V94 tmp85 [ int]: refCnt = 6, refCntWtd = 2.25 V84 tmp75 [ int]: refCnt = 5, refCntWtd = 2.25 V88 tmp79 [ int]: refCnt = 5, refCntWtd = 2.25 V92 tmp83 [ int]: refCnt = 5, refCntWtd = 2.25 V103 tmp94 [ byref]: refCnt = 2, refCntWtd = 2 V22 tmp13 [ int]: refCnt = 2, refCntWtd = 2 V23 tmp14 [ int]: refCnt = 2, refCntWtd = 2 V18 tmp9 [ int]: refCnt = 1, refCntWtd = 2 V96 tmp87 [ ref]: refCnt = 6, refCntWtd = 1.50 V63 tmp54 [ byref]: refCnt = 3, refCntWtd = 1.50 V67 tmp58 [ byref]: refCnt = 3, refCntWtd = 1.50 V98 tmp89 [ byref]: refCnt = 3, refCntWtd = 1.50 V100 tmp91 [ byref]: refCnt = 3, refCntWtd = 1.50 V101 tmp92 [ byref]: refCnt = 3, refCntWtd = 1.50 V102 tmp93 [ byref]: refCnt = 3, refCntWtd = 1.50 V104 tmp95 [ byref]: refCnt = 3, refCntWtd = 1.50 V105 tmp96 [ byref]: refCnt = 3, refCntWtd = 1.50 V106 tmp97 [ byref]: refCnt = 3, refCntWtd = 1.50 V107 tmp98 [ byref]: refCnt = 3, refCntWtd = 1.50 V20 tmp11 [ bool]: refCnt = 3, refCntWtd = 1.50 V25 tmp16 [ bool]: refCnt = 3, refCntWtd = 1.50 V35 tmp26 [ bool]: refCnt = 3, refCntWtd = 1.50 V44 tmp35 [ bool]: refCnt = 3, refCntWtd = 1.50 V53 tmp44 [ bool]: refCnt = 3, refCntWtd = 1.50 V64 tmp55 [ int]: refCnt = 3, refCntWtd = 1.50 V68 tmp59 [ int]: refCnt = 3, refCntWtd = 1.50 V72 tmp63 [ byref]: refCnt = 2, refCntWtd = 1.25 V74 tmp65 [ byref]: refCnt = 2, refCntWtd = 1.25 V14 tmp5 [ int]: refCnt = 4, refCntWtd = 1 V30 tmp21 [ int]: refCnt = 4, refCntWtd = 1 V78 tmp69 [ byref]: refCnt = 3, refCntWtd = 1 V36 tmp27 [ bool]: refCnt = 3, refCntWtd = 1 V45 tmp36 [ bool]: refCnt = 3, refCntWtd = 1 V54 tmp45 [ bool]: refCnt = 3, refCntWtd = 1 V79 tmp70 [ int]: refCnt = 3, refCntWtd = 1 V10 tmp1 [ byref]: refCnt = 2, refCntWtd = 1 V26 tmp17 [ byref]: refCnt = 2, refCntWtd = 1 V38 tmp29 [ int]: refCnt = 2, refCntWtd = 1 V39 tmp30 [ int]: refCnt = 2, refCntWtd = 1 V47 tmp38 [ int]: refCnt = 2, refCntWtd = 1 V48 tmp39 [ int]: refCnt = 2, refCntWtd = 1 V56 tmp47 [ int]: refCnt = 2, refCntWtd = 1 V57 tmp48 [ int]: refCnt = 2, refCntWtd = 1 V04 loc2 [ bool]: refCnt = 1, refCntWtd = 1 V34 tmp25 [ int]: refCnt = 1, refCntWtd = 1 V43 tmp34 [ int]: refCnt = 1, refCntWtd = 1 V52 tmp43 [ int]: refCnt = 1, refCntWtd = 1 V65 tmp56 [ byref]: refCnt = 3, refCntWtd = 0.75 V71 tmp62 [ byref]: refCnt = 3, refCntWtd = 0.75 V76 tmp67 [ byref]: refCnt = 3, refCntWtd = 0.75 V82 tmp73 [ byref]: refCnt = 3, refCntWtd = 0.75 V66 tmp57 [ int]: refCnt = 3, refCntWtd = 0.75 V77 tmp68 [ int]: refCnt = 3, refCntWtd = 0.75 V83 tmp74 [ byref]: refCnt = 2, refCntWtd = 0.75 V85 tmp76 [ byref]: refCnt = 2, refCntWtd = 0.75 V87 tmp78 [ byref]: refCnt = 2, refCntWtd = 0.75 V89 tmp80 [ byref]: refCnt = 2, refCntWtd = 0.75 V91 tmp82 [ byref]: refCnt = 2, refCntWtd = 0.75 V93 tmp84 [ byref]: refCnt = 2, refCntWtd = 0.75 V69 tmp60 [ byref]: refCnt = 2, refCntWtd = 0.50 V80 tmp71 [ byref]: refCnt = 2, refCntWtd = 0.50 V24 tmp15 [ int]: refCnt = 2, refCntWtd = 0.50 V40 tmp31 [ int]: refCnt = 2, refCntWtd = 0.50 V49 tmp40 [ int]: refCnt = 2, refCntWtd = 0.50 V58 tmp49 [ int]: refCnt = 2, refCntWtd = 0.50 V70 tmp61 [ int]: refCnt = 2, refCntWtd = 0.50 V81 tmp72 [ int]: refCnt = 2, refCntWtd = 0.50 V06 loc4 [ bool]: refCnt = 1, refCntWtd = 0.50 V07 loc5 [ bool]: refCnt = 1, refCntWtd = 0.50 V08 loc6 [ bool]: refCnt = 1, refCntWtd = 0.50 V97 tmp88 [struct]: refCnt = 15, refCntWtd = 12 V99 tmp90 [struct]: refCnt = 12, refCntWtd = 8 V108 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** In fgFindOperOrder() *************** In fgSetBlockOrder() The biggest BB has 49 tree nodes -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 ( 1, 3) [000224] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000221] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000223] -A------R--- \--* ASG bool N002 ( 1, 1) [000222] D------N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 2 ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N003 ( 1, 1) [000167] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000168] ------------ | /--* EQ int N002 ( 3, 10) [000921] ------------ | | \--* NOP ref N001 ( 3, 10) [000920] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N006 ( 8, 12) [000170] -A------R--- \--* ASG bool N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 ***** BB01, stmt 3 ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000174] J------N---- \--* EQ int N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 4 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 N007 ( 10, 8) [000928] -A---------- \--* COMMA void N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000924] -A------R--- \--* ASG byref N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 ***** BB02, stmt 5 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 N006 ( 7, 5) [000934] -A------R--- | /--* ASG int N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 N007 ( 14, 10) [000935] -A---------- \--* COMMA void N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 N003 ( 7, 5) [000931] -A------R--- \--* ASG byref N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 6 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [000945] ------------ | /--* ADD byref N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 ***** BB03, stmt 7 ( 5, 4) [000247] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000244] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000246] -A------R--- \--* ASG int N002 ( 3, 2) [000245] D------N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 8 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref N002 ( 3, 10) [000956] ------------ | | \--* NOP ref N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 9 ( 10, 8) [000193] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000961] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [000962] -A------R--- | /--* ASG int N005 ( 3, 2) [000960] D------N---- | | \--* LCL_VAR int V66 tmp57 N007 ( 10, 8) [000963] -A---------- \--* COMMA void N001 ( 1, 1) [000958] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000959] -A------R--- \--* ASG byref N002 ( 3, 2) [000957] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 10 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 ***** BB03, stmt 11 ( 5, 4) [000262] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000967] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000968] -A------R--- \--* ASG byref N002 ( 3, 2) [000966] D------N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 12 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 N003 ( 7, 5) [000266] -A------R--- \--* ASG byref N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 ***** BB03, stmt 13 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 N003 ( 7, 5) [000971] -A------R--- \--* ASG byref N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 ***** BB03, stmt 14 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 ***** BB03, stmt 15 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 N003 ( 7, 5) [000974] -A------R--- \--* ASG byref N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 16 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 N006 ( 7, 5) [000984] -A------R--- | /--* ASG int N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 N007 ( 14, 10) [000985] -A---------- \--* COMMA void N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 N003 ( 7, 5) [000981] -A------R--- \--* ASG byref N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 ***** BB04, stmt 17 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 N007 ( 10, 8) [000992] -A---------- \--* COMMA void N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 N003 ( 7, 5) [000988] -A------R--- \--* ASG byref N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 ***** BB04, stmt 18 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 ***** BB04, stmt 19 ( 1, 3) [000363] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000360] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000362] -A------R--- \--* ASG bool N002 ( 1, 1) [000361] D------N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 20 ( 1, 3) [000367] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000364] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000366] -A------R--- \--* ASG bool N002 ( 1, 1) [000365] D------N---- \--* LCL_VAR int V21 tmp12 ***** BB04, stmt 21 ( 5, 4) [000371] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000368] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000370] -A------R--- \--* ASG bool N002 ( 3, 2) [000369] D------N---- \--* LCL_VAR int V20 tmp11 ***** BB04, stmt 22 ( 5, 4) [000384] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000381] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000383] -A------R--- \--* ASG int N002 ( 3, 2) [000382] D------N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 23 ( 5, 4) [000379] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000376] ------------ | /--* LCL_VAR int V73 tmp64 N003 ( 5, 4) [000378] -A------R--- \--* ASG int N002 ( 3, 2) [000377] D------N---- \--* LCL_VAR int V22 tmp13 ***** BB04, stmt 24 ( 5, 4) [000294] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000380] ------------ | /--* LCL_VAR int V73 tmp64 N003 ( 5, 4) [000293] -A------R--- \--* ASG int N002 ( 3, 2) [000292] D------N---- \--* LCL_VAR int V18 tmp9 ***** BB04, stmt 25 ( 5, 4) [000397] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000394] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000396] -A------R--- \--* ASG int N002 ( 3, 2) [000395] D------N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 26 ( 5, 4) [000392] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000389] ------------ | /--* LCL_VAR int V75 tmp66 N003 ( 5, 4) [000391] -A------R--- \--* ASG int N002 ( 3, 2) [000390] D------N---- \--* LCL_VAR int V23 tmp14 ***** BB04, stmt 27 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V73 tmp64 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 ***** BB04, stmt 28 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 29 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 30 ( 5, 4) [000410] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000407] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000409] -A------R--- \--* ASG int N002 ( 3, 2) [000408] D------N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 31 ( 5, 4) [000405] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000402] ------------ | /--* LCL_VAR int V75 tmp66 N003 ( 5, 4) [000404] -A------R--- \--* ASG int N002 ( 3, 2) [000403] D------N---- \--* LCL_VAR int V24 tmp15 ***** BB06, stmt 32 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 ***** BB06, stmt 33 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 34 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 35 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 36 ( 5, 4) [000024] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000340] ------------ | /--* LCL_VAR int V21 tmp12 N003 ( 5, 4) [000023] -A------R--- \--* ASG int N002 ( 3, 2) [000022] D------N---- \--* LCL_VAR int V04 loc2 ***** BB09, stmt 37 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000027] J------N---- \--* EQ int N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 38 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte N002 ( 4, 3) [000158] *--X---N---- \--* IND byte N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 ***** BB10, stmt 39 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000163] -A------R--- \--* ASG int N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 40 ( 5, 4) [000471] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000468] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000470] -A------R--- \--* ASG bool N002 ( 3, 2) [000469] D------N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 41 ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N003 ( 1, 1) [000414] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000415] ------------ | /--* EQ int N002 ( 3, 10) [001063] ------------ | | \--* NOP ref N001 ( 3, 10) [001062] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N006 ( 12, 15) [000417] -A------R--- \--* ASG bool N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 ***** BB11, stmt 42 ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000421] J------N---- \--* EQ int N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 43 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 N007 ( 10, 8) [001070] -A---------- \--* COMMA void N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001066] -A------R--- \--* ASG byref N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 ***** BB12, stmt 44 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 N006 ( 7, 5) [001076] -A------R--- | /--* ASG int N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 N007 ( 14, 10) [001077] -A---------- \--* COMMA void N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 N003 ( 7, 5) [001073] -A------R--- \--* ASG byref N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 45 ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [001087] ------------ | /--* ADD byref N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 ***** BB13, stmt 46 ( 5, 4) [000494] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000491] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000493] -A------R--- \--* ASG int N002 ( 3, 2) [000492] D------N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 47 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref N002 ( 3, 10) [001098] ------------ | | \--* NOP ref N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 48 ( 10, 8) [000440] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001103] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [001104] -A------R--- | /--* ASG int N005 ( 3, 2) [001102] D------N---- | | \--* LCL_VAR int V77 tmp68 N007 ( 10, 8) [001105] -A---------- \--* COMMA void N001 ( 1, 1) [001100] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001101] -A------R--- \--* ASG byref N002 ( 3, 2) [001099] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 49 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 ***** BB13, stmt 50 ( 5, 4) [000509] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [001109] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001110] -A------R--- \--* ASG byref N002 ( 3, 2) [001108] D------N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 51 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V26 tmp17 N003 ( 7, 5) [000513] -A------R--- \--* ASG byref N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 ***** BB13, stmt 52 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 N003 ( 7, 5) [001113] -A------R--- \--* ASG byref N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 ***** BB13, stmt 53 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 ***** BB13, stmt 54 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 N003 ( 7, 5) [001116] -A------R--- \--* ASG byref N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 55 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 N006 ( 7, 5) [001126] -A------R--- | /--* ASG int N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 N007 ( 14, 10) [001127] -A---------- \--* COMMA void N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 N003 ( 7, 5) [001123] -A------R--- \--* ASG byref N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 ***** BB14, stmt 56 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 N007 ( 14, 10) [001134] -A---------- \--* COMMA void N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 N003 ( 7, 5) [001130] -A------R--- \--* ASG byref N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 ***** BB14, stmt 57 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 ***** BB14, stmt 58 ( 5, 4) [000610] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000607] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000609] -A------R--- \--* ASG bool N002 ( 3, 2) [000608] D------N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 59 ( 5, 4) [000614] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000611] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000613] -A------R--- \--* ASG bool N002 ( 3, 2) [000612] D------N---- \--* LCL_VAR int V37 tmp28 ***** BB14, stmt 60 ( 5, 4) [000618] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000615] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000617] -A------R--- \--* ASG bool N002 ( 3, 2) [000616] D------N---- \--* LCL_VAR int V36 tmp27 ***** BB14, stmt 61 ( 5, 4) [000631] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000628] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000630] -A------R--- \--* ASG int N002 ( 3, 2) [000629] D------N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 62 ( 7, 5) [000626] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000623] ------------ | /--* LCL_VAR int V84 tmp75 N003 ( 7, 5) [000625] -A------R--- \--* ASG int N002 ( 3, 2) [000624] D------N---- \--* LCL_VAR int V38 tmp29 ***** BB14, stmt 63 ( 7, 5) [000541] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000627] ------------ | /--* LCL_VAR int V84 tmp75 N003 ( 7, 5) [000540] -A------R--- \--* ASG int N002 ( 3, 2) [000539] D------N---- \--* LCL_VAR int V34 tmp25 ***** BB14, stmt 64 ( 5, 4) [000644] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000641] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000643] -A------R--- \--* ASG int N002 ( 3, 2) [000642] D------N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 65 ( 7, 5) [000639] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000636] ------------ | /--* LCL_VAR int V86 tmp77 N003 ( 7, 5) [000638] -A------R--- \--* ASG int N002 ( 3, 2) [000637] D------N---- \--* LCL_VAR int V39 tmp30 ***** BB14, stmt 66 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V84 tmp75 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 ***** BB14, stmt 67 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 68 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 69 ( 5, 4) [000657] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000654] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000656] -A------R--- \--* ASG int N002 ( 3, 2) [000655] D------N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 70 ( 7, 5) [000652] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000649] ------------ | /--* LCL_VAR int V86 tmp77 N003 ( 7, 5) [000651] -A------R--- \--* ASG int N002 ( 3, 2) [000650] D------N---- \--* LCL_VAR int V40 tmp31 ***** BB16, stmt 71 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 ***** BB16, stmt 72 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 73 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 74 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 75 ( 7, 5) [000054] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000587] ------------ | /--* LCL_VAR int V37 tmp28 N003 ( 7, 5) [000053] -A------R--- \--* ASG int N002 ( 3, 2) [000052] D------N---- \--* LCL_VAR int V06 loc4 ***** BB19, stmt 76 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000057] J------N---- \--* EQ int N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 77 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte N002 ( 4, 3) [000148] *--X---N---- \--* IND byte N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 ***** BB20, stmt 78 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000153] -A------R--- \--* ASG int N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 79 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 ***** BB21, stmt 80 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 N006 ( 7, 5) [001217] -A------R--- | /--* ASG int N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 N007 ( 14, 10) [001218] -A---------- \--* COMMA void N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 N003 ( 7, 5) [001214] -A------R--- \--* ASG byref N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 ***** BB21, stmt 81 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 ***** BB21, stmt 82 ( 5, 4) [000740] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000737] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000739] -A------R--- \--* ASG bool N002 ( 3, 2) [000738] D------N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 83 ( 5, 4) [000744] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000741] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000743] -A------R--- \--* ASG bool N002 ( 3, 2) [000742] D------N---- \--* LCL_VAR int V46 tmp37 ***** BB21, stmt 84 ( 5, 4) [000748] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000745] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000747] -A------R--- \--* ASG bool N002 ( 3, 2) [000746] D------N---- \--* LCL_VAR int V45 tmp36 ***** BB21, stmt 85 ( 5, 4) [000761] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000758] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000760] -A------R--- \--* ASG int N002 ( 3, 2) [000759] D------N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 86 ( 7, 5) [000756] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000753] ------------ | /--* LCL_VAR int V88 tmp79 N003 ( 7, 5) [000755] -A------R--- \--* ASG int N002 ( 3, 2) [000754] D------N---- \--* LCL_VAR int V47 tmp38 ***** BB21, stmt 87 ( 7, 5) [000671] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000757] ------------ | /--* LCL_VAR int V88 tmp79 N003 ( 7, 5) [000670] -A------R--- \--* ASG int N002 ( 3, 2) [000669] D------N---- \--* LCL_VAR int V43 tmp34 ***** BB21, stmt 88 ( 5, 4) [000774] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000771] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000773] -A------R--- \--* ASG int N002 ( 3, 2) [000772] D------N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 89 ( 7, 5) [000769] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000766] ------------ | /--* LCL_VAR int V90 tmp81 N003 ( 7, 5) [000768] -A------R--- \--* ASG int N002 ( 3, 2) [000767] D------N---- \--* LCL_VAR int V48 tmp39 ***** BB21, stmt 90 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 ***** BB21, stmt 91 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 92 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 93 ( 5, 4) [000787] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000784] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000786] -A------R--- \--* ASG int N002 ( 3, 2) [000785] D------N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 94 ( 7, 5) [000782] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000779] ------------ | /--* LCL_VAR int V90 tmp81 N003 ( 7, 5) [000781] -A------R--- \--* ASG int N002 ( 3, 2) [000780] D------N---- \--* LCL_VAR int V49 tmp40 ***** BB23, stmt 95 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 ***** BB23, stmt 96 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 97 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 98 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 99 ( 7, 5) [000084] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000717] ------------ | /--* LCL_VAR int V46 tmp37 N003 ( 7, 5) [000083] -A------R--- \--* ASG int N002 ( 3, 2) [000082] D------N---- \--* LCL_VAR int V07 loc5 ***** BB26, stmt 100 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000087] J------N---- \--* EQ int N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 101 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte N002 ( 4, 3) [000138] *--X---N---- \--* IND byte N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 ***** BB27, stmt 102 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000143] -A------R--- \--* ASG int N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 103 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 N006 ( 7, 5) [001292] -A------R--- | /--* ASG int N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 N007 ( 14, 10) [001293] -A---------- \--* COMMA void N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 N003 ( 7, 5) [001289] -A------R--- \--* ASG byref N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 ***** BB28, stmt 104 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 ***** BB28, stmt 105 ( 5, 4) [000870] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000867] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000869] -A------R--- \--* ASG bool N002 ( 3, 2) [000868] D------N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 106 ( 5, 4) [000874] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000871] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000873] -A------R--- \--* ASG bool N002 ( 3, 2) [000872] D------N---- \--* LCL_VAR int V55 tmp46 ***** BB28, stmt 107 ( 5, 4) [000878] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000875] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000877] -A------R--- \--* ASG bool N002 ( 3, 2) [000876] D------N---- \--* LCL_VAR int V54 tmp45 ***** BB28, stmt 108 ( 5, 4) [000891] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000888] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000890] -A------R--- \--* ASG int N002 ( 3, 2) [000889] D------N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 109 ( 7, 5) [000886] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000883] ------------ | /--* LCL_VAR int V92 tmp83 N003 ( 7, 5) [000885] -A------R--- \--* ASG int N002 ( 3, 2) [000884] D------N---- \--* LCL_VAR int V56 tmp47 ***** BB28, stmt 110 ( 7, 5) [000801] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000887] ------------ | /--* LCL_VAR int V92 tmp83 N003 ( 7, 5) [000800] -A------R--- \--* ASG int N002 ( 3, 2) [000799] D------N---- \--* LCL_VAR int V52 tmp43 ***** BB28, stmt 111 ( 5, 4) [000904] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000901] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000903] -A------R--- \--* ASG int N002 ( 3, 2) [000902] D------N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 112 ( 7, 5) [000899] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000896] ------------ | /--* LCL_VAR int V94 tmp85 N003 ( 7, 5) [000898] -A------R--- \--* ASG int N002 ( 3, 2) [000897] D------N---- \--* LCL_VAR int V57 tmp48 ***** BB28, stmt 113 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 ***** BB28, stmt 114 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 115 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 116 ( 5, 4) [000917] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000914] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000916] -A------R--- \--* ASG int N002 ( 3, 2) [000915] D------N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 117 ( 7, 5) [000912] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000909] ------------ | /--* LCL_VAR int V94 tmp85 N003 ( 7, 5) [000911] -A------R--- \--* ASG int N002 ( 3, 2) [000910] D------N---- \--* LCL_VAR int V58 tmp49 ***** BB30, stmt 118 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 ***** BB30, stmt 119 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 120 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 121 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 122 ( 7, 5) [000105] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000847] ------------ | /--* LCL_VAR int V55 tmp46 N003 ( 7, 5) [000104] -A------R--- \--* ASG int N002 ( 3, 2) [000103] D------N---- \--* LCL_VAR int V08 loc6 ***** BB33, stmt 123 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000108] J------N---- \--* EQ int N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 124 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte N002 ( 4, 3) [000128] *--X---N---- \--* IND byte N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 ***** BB34, stmt 125 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000133] -A------R--- \--* ASG int N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 126 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte N002 ( 4, 3) [000114] *--X---N---- \--* IND byte N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 ***** BB35, stmt 127 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000119] -A------R--- \--* ASG int N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 128 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 ------------------------------------------------------------------------------------------------------------------- *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 37. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] *************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...) *************** In SsaBuilder::InsertPhiFunctions() *************** In fgLocalVarLiveness() *************** In fgPerBlockLocalVarLiveness() BB01 USE(0)={ } DEF(1)={V09} BB02 USE(0)={ } DEF(4)={V67 V68 V69 V70} BB03 USE(0)={ } + ByrefExposed + GcHeap DEF(8)={V96 V67 V68 V14 V10 V65 V71 V66} + ByrefExposed* + GcHeap* BB04 USE(3)={V00 V67 V68 } + ByrefExposed + GcHeap DEF(12)={ V73 V21 V75 V19 V61 V62 V22 V23 V18 V20 V72 V74} BB05 USE(0)={ } DEF(1)={V21} BB06 USE(1)={V75 } DEF(2)={ V20 V24} BB07 USE(0)={ } DEF(1)={V21} BB08 USE(4)={V73 V75 V72 V74} + ByrefExposed + GcHeap DEF(3)={ V21 V98 V100 } + ByrefExposed* + GcHeap* BB09 USE(1)={V21 } DEF(1)={ V04} BB10 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V05} + ByrefExposed + GcHeap BB11 USE(0)={ } DEF(1)={V25} BB12 USE(0)={ } DEF(4)={V78 V79 V80 V81} BB13 USE(0)={ } + ByrefExposed + GcHeap DEF(8)={V96 V30 V78 V79 V26 V76 V82 V77} + ByrefExposed* + GcHeap* BB14 USE(3)={V00 V78 V79 } + ByrefExposed + GcHeap DEF(12)={ V37 V86 V84 V63 V35 V64 V36 V38 V39 V34 V83 V85} BB15 USE(0)={ } DEF(1)={V37} BB16 USE(1)={V86 } DEF(2)={ V36 V40} BB17 USE(0)={ } DEF(1)={V37} BB18 USE(4)={ V86 V84 V83 V85} + ByrefExposed + GcHeap DEF(3)={V37 V101 V102 } + ByrefExposed* + GcHeap* BB19 USE(1)={V37 } DEF(1)={ V06} BB20 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V05} + ByrefExposed + GcHeap BB21 USE(3)={V00 V61 V62 } + ByrefExposed + GcHeap DEF(11)={ V46 V90 V88 V103 V44 V45 V47 V48 V43 V87 V89} + ByrefExposed* + GcHeap* BB22 USE(0)={ } DEF(1)={V46} BB23 USE(1)={V90 } DEF(2)={ V45 V49} BB24 USE(0)={ } DEF(1)={V46} BB25 USE(4)={ V90 V88 V87 V89} + ByrefExposed + GcHeap DEF(3)={V46 V104 V105 } + ByrefExposed* + GcHeap* BB26 USE(1)={V46 } DEF(1)={ V07} BB27 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V05} + ByrefExposed + GcHeap BB28 USE(3)={V00 V63 V64 } + ByrefExposed + GcHeap DEF(10)={ V55 V94 V92 V53 V54 V56 V57 V52 V91 V93} BB29 USE(0)={ } DEF(1)={V55} BB30 USE(1)={V94 } DEF(2)={ V54 V58} BB31 USE(0)={ } DEF(1)={V55} BB32 USE(4)={ V94 V92 V91 V93} + ByrefExposed + GcHeap DEF(3)={V55 V106 V107 } + ByrefExposed* + GcHeap* BB33 USE(1)={V55 } DEF(1)={ V08} BB34 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V05} + ByrefExposed + GcHeap BB35 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V05} + ByrefExposed + GcHeap BB36 USE(1)={V05} DEF(0)={ } ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V00 V01} + ByrefExposed + GcHeap OUT(2)={V00 V01} + ByrefExposed + GcHeap BB02 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(4)={V00 V01 V67 V68} + ByrefExposed + GcHeap BB03 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(4)={V00 V01 V67 V68} + ByrefExposed + GcHeap BB04 IN (4)={V00 V01 V67 V68 } + ByrefExposed + GcHeap OUT(8)={V00 V01 V73 V75 V61 V62 V72 V74} + ByrefExposed + GcHeap BB05 IN (4)={V00 V01 V61 V62} + ByrefExposed + GcHeap OUT(5)={V00 V01 V21 V61 V62} + ByrefExposed + GcHeap BB06 IN (8)={V00 V01 V73 V75 V61 V62 V72 V74} + ByrefExposed + GcHeap OUT(8)={V00 V01 V73 V75 V61 V62 V72 V74} + ByrefExposed + GcHeap BB07 IN (4)={V00 V01 V61 V62} + ByrefExposed + GcHeap OUT(5)={V00 V01 V21 V61 V62} + ByrefExposed + GcHeap BB08 IN (8)={V00 V01 V73 V75 V61 V62 V72 V74} + ByrefExposed + GcHeap OUT(5)={V00 V01 V21 V61 V62 } + ByrefExposed + GcHeap BB09 IN (5)={V00 V01 V21 V61 V62} + ByrefExposed + GcHeap OUT(4)={V00 V01 V61 V62} + ByrefExposed + GcHeap BB10 IN (1)={V01 } + ByrefExposed + GcHeap OUT(1)={ V05} BB11 IN (4)={V00 V01 V61 V62} + ByrefExposed + GcHeap OUT(4)={V00 V01 V61 V62} + ByrefExposed + GcHeap BB12 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V78 V79} + ByrefExposed + GcHeap BB13 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V78 V79} + ByrefExposed + GcHeap BB14 IN (6)={V00 V01 V61 V62 V78 V79 } + ByrefExposed + GcHeap OUT(10)={V00 V01 V61 V62 V86 V84 V63 V64 V83 V85} + ByrefExposed + GcHeap BB15 IN (6)={V00 V01 V61 V62 V63 V64} + ByrefExposed + GcHeap OUT(7)={V00 V01 V61 V62 V37 V63 V64} + ByrefExposed + GcHeap BB16 IN (10)={V00 V01 V61 V62 V86 V84 V63 V64 V83 V85} + ByrefExposed + GcHeap OUT(10)={V00 V01 V61 V62 V86 V84 V63 V64 V83 V85} + ByrefExposed + GcHeap BB17 IN (6)={V00 V01 V61 V62 V63 V64} + ByrefExposed + GcHeap OUT(7)={V00 V01 V61 V62 V37 V63 V64} + ByrefExposed + GcHeap BB18 IN (10)={V00 V01 V61 V62 V86 V84 V63 V64 V83 V85} + ByrefExposed + GcHeap OUT(7)={V00 V01 V61 V62 V37 V63 V64 } + ByrefExposed + GcHeap BB19 IN (7)={V00 V01 V61 V62 V37 V63 V64} + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V63 V64} + ByrefExposed + GcHeap BB20 IN (1)={V01 } + ByrefExposed + GcHeap OUT(1)={ V05} BB21 IN (6)={V00 V01 V61 V62 V63 V64 } + ByrefExposed + GcHeap OUT(8)={V00 V01 V90 V88 V63 V64 V87 V89} + ByrefExposed + GcHeap BB22 IN (4)={V00 V01 V63 V64} + ByrefExposed + GcHeap OUT(5)={V00 V01 V46 V63 V64} + ByrefExposed + GcHeap BB23 IN (8)={V00 V01 V90 V88 V63 V64 V87 V89} + ByrefExposed + GcHeap OUT(8)={V00 V01 V90 V88 V63 V64 V87 V89} + ByrefExposed + GcHeap BB24 IN (4)={V00 V01 V63 V64} + ByrefExposed + GcHeap OUT(5)={V00 V01 V46 V63 V64} + ByrefExposed + GcHeap BB25 IN (8)={V00 V01 V90 V88 V63 V64 V87 V89} + ByrefExposed + GcHeap OUT(5)={V00 V01 V46 V63 V64 } + ByrefExposed + GcHeap BB26 IN (5)={V00 V01 V46 V63 V64} + ByrefExposed + GcHeap OUT(4)={V00 V01 V63 V64} + ByrefExposed + GcHeap BB27 IN (1)={V01 } + ByrefExposed + GcHeap OUT(1)={ V05} BB28 IN (4)={V00 V01 V63 V64 } + ByrefExposed + GcHeap OUT(5)={ V01 V94 V92 V91 V93} + ByrefExposed + GcHeap BB29 IN (1)={V01 } + ByrefExposed + GcHeap OUT(2)={V01 V55} + ByrefExposed + GcHeap BB30 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap BB31 IN (1)={V01 } + ByrefExposed + GcHeap OUT(2)={V01 V55} + ByrefExposed + GcHeap BB32 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(2)={V01 V55 } + ByrefExposed + GcHeap BB33 IN (2)={V01 V55} + ByrefExposed + GcHeap OUT(1)={V01 } + ByrefExposed + GcHeap BB34 IN (1)={V01 } + ByrefExposed + GcHeap OUT(1)={ V05} BB35 IN (1)={V01 } + ByrefExposed + GcHeap OUT(1)={ V05} BB36 IN (1)={V05} OUT(0)={ } top level assign removing stmt with no side effects Removing statement [000224] in BB01 as useless: ( 1, 3) [000224] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000221] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000223] -A------R--- \--* ASG bool N002 ( 1, 1) [000222] D------N---- \--* LCL_VAR int V09 tmp0 New refCnts for V09: refCnt = 2, refCntWtd = 2 top level assign removing stmt with no side effects Removing statement [000262] in BB03 as useless: ( 5, 4) [000262] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000967] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000968] -A------R--- \--* ASG byref N002 ( 3, 2) [000966] D------N---- \--* LCL_VAR byref V71 tmp62 New refCnts for V71: refCnt = 2, refCntWtd = 0.50 Removing tree [000962] in BB03 as useless N004 ( 1, 1) [000961] ------------ /--* CNS_INT int 0 N006 ( 5, 4) [000962] -A------R--- * ASG int N005 ( 3, 2) [000960] D------N---- \--* LCL_VAR int V66 tmp57 New refCnts for V66: refCnt = 2, refCntWtd = 0.50 Removing tree [000959] in BB03 as useless N001 ( 1, 1) [000958] ------------ /--* CNS_INT byref 0 N003 ( 5, 4) [000959] -A------R--- * ASG byref N002 ( 3, 2) [000957] D------N---- \--* LCL_VAR byref V65 tmp56 New refCnts for V65: refCnt = 2, refCntWtd = 0.50 fgComputeLife modified tree: N002 ( 0, 0) [000962] ------------ /--* NOP void N003 ( 0, 0) [000963] ------------ * COMMA void N001 ( 0, 0) [000959] ------------ \--* NOP void top level assign removing stmt with no side effects Removing statement [000247] in BB03 as useless: ( 5, 4) [000247] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000244] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000246] -A------R--- \--* ASG int N002 ( 3, 2) [000245] D------N---- \--* LCL_VAR int V14 tmp5 New refCnts for V14: refCnt = 3, refCntWtd = 0.75 top level assign removing stmt with no side effects Removing statement [000392] in BB04 as useless: ( 5, 4) [000392] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000389] ------------ | /--* LCL_VAR int V75 tmp66 N003 ( 5, 4) [000391] -A------R--- \--* ASG int N002 ( 3, 2) [000390] D------N---- \--* LCL_VAR int V23 tmp14 New refCnts for V23: refCnt = 1, refCntWtd = 1 New refCnts for V75: refCnt = 5, refCntWtd = 2.75 top level assign removing stmt with no side effects Removing statement [000397] in BB04 as useless: ( 5, 4) [000397] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000394] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000396] -A------R--- \--* ASG int N002 ( 3, 2) [000395] D------N---- \--* LCL_VAR int V23 tmp14 New refCnts for V23: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000294] in BB04 as useless: ( 5, 4) [000294] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000380] ------------ | /--* LCL_VAR int V73 tmp64 N003 ( 5, 4) [000293] -A------R--- \--* ASG int N002 ( 3, 2) [000292] D------N---- \--* LCL_VAR int V18 tmp9 New refCnts for V18: refCnt = 0, refCntWtd = 0 New refCnts for V73: refCnt = 4, refCntWtd = 3.25 top level assign removing stmt with no side effects Removing statement [000379] in BB04 as useless: ( 5, 4) [000379] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000376] ------------ | /--* LCL_VAR int V73 tmp64 N003 ( 5, 4) [000378] -A------R--- \--* ASG int N002 ( 3, 2) [000377] D------N---- \--* LCL_VAR int V22 tmp13 New refCnts for V22: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 3, refCntWtd = 2.25 top level assign removing stmt with no side effects Removing statement [000384] in BB04 as useless: ( 5, 4) [000384] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000381] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000383] -A------R--- \--* ASG int N002 ( 3, 2) [000382] D------N---- \--* LCL_VAR int V22 tmp13 New refCnts for V22: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000371] in BB04 as useless: ( 5, 4) [000371] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000368] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000370] -A------R--- \--* ASG bool N002 ( 3, 2) [000369] D------N---- \--* LCL_VAR int V20 tmp11 New refCnts for V20: refCnt = 2, refCntWtd = 0.50 top level assign removing stmt with no side effects Removing statement [000367] in BB04 as useless: ( 1, 3) [000367] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000364] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000366] -A------R--- \--* ASG bool N002 ( 1, 1) [000365] D------N---- \--* LCL_VAR int V21 tmp12 New refCnts for V21: refCnt = 5, refCntWtd = 2.75 top level assign removing stmt with no side effects Removing statement [000363] in BB04 as useless: ( 1, 3) [000363] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000360] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000362] -A------R--- \--* ASG bool N002 ( 1, 1) [000361] D------N---- \--* LCL_VAR int V19 tmp10 New refCnts for V19: refCnt = 2, refCntWtd = 2 top level assign removing stmt with no side effects Removing statement [000405] in BB06 as useless: ( 5, 4) [000405] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000402] ------------ | /--* LCL_VAR int V75 tmp66 N003 ( 5, 4) [000404] -A------R--- \--* ASG int N002 ( 3, 2) [000403] D------N---- \--* LCL_VAR int V24 tmp15 New refCnts for V24: refCnt = 1, refCntWtd = 0.25 New refCnts for V75: refCnt = 4, refCntWtd = 2.50 top level assign removing stmt with no side effects Removing statement [000410] in BB06 as useless: ( 5, 4) [000410] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000407] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000409] -A------R--- \--* ASG int N002 ( 3, 2) [000408] D------N---- \--* LCL_VAR int V24 tmp15 New refCnts for V24: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000024] in BB09 as useless: ( 5, 4) [000024] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000340] ------------ | /--* LCL_VAR int V21 tmp12 N003 ( 5, 4) [000023] -A------R--- \--* ASG int N002 ( 3, 2) [000022] D------N---- \--* LCL_VAR int V04 loc2 New refCnts for V04: refCnt = 0, refCntWtd = 0 New refCnts for V21: refCnt = 4, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000471] in BB11 as useless: ( 5, 4) [000471] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000468] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000470] -A------R--- \--* ASG bool N002 ( 3, 2) [000469] D------N---- \--* LCL_VAR int V25 tmp16 New refCnts for V25: refCnt = 2, refCntWtd = 1 top level assign removing stmt with no side effects Removing statement [000509] in BB13 as useless: ( 5, 4) [000509] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [001109] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001110] -A------R--- \--* ASG byref N002 ( 3, 2) [001108] D------N---- \--* LCL_VAR byref V82 tmp73 New refCnts for V82: refCnt = 2, refCntWtd = 0.50 Removing tree [001104] in BB13 as useless N004 ( 1, 1) [001103] ------------ /--* CNS_INT int 0 N006 ( 5, 4) [001104] -A------R--- * ASG int N005 ( 3, 2) [001102] D------N---- \--* LCL_VAR int V77 tmp68 New refCnts for V77: refCnt = 2, refCntWtd = 0.50 Removing tree [001101] in BB13 as useless N001 ( 1, 1) [001100] ------------ /--* CNS_INT byref 0 N003 ( 5, 4) [001101] -A------R--- * ASG byref N002 ( 3, 2) [001099] D------N---- \--* LCL_VAR byref V76 tmp67 New refCnts for V76: refCnt = 2, refCntWtd = 0.50 fgComputeLife modified tree: N002 ( 0, 0) [001104] ------------ /--* NOP void N003 ( 0, 0) [001105] ------------ * COMMA void N001 ( 0, 0) [001101] ------------ \--* NOP void top level assign removing stmt with no side effects Removing statement [000494] in BB13 as useless: ( 5, 4) [000494] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000491] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000493] -A------R--- \--* ASG int N002 ( 3, 2) [000492] D------N---- \--* LCL_VAR int V30 tmp21 New refCnts for V30: refCnt = 3, refCntWtd = 0.75 top level assign removing stmt with no side effects Removing statement [000639] in BB14 as useless: ( 7, 5) [000639] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000636] ------------ | /--* LCL_VAR int V86 tmp77 N003 ( 7, 5) [000638] -A------R--- \--* ASG int N002 ( 3, 2) [000637] D------N---- \--* LCL_VAR int V39 tmp30 New refCnts for V39: refCnt = 1, refCntWtd = 0.50 New refCnts for V86: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000644] in BB14 as useless: ( 5, 4) [000644] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000641] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000643] -A------R--- \--* ASG int N002 ( 3, 2) [000642] D------N---- \--* LCL_VAR int V39 tmp30 New refCnts for V39: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000541] in BB14 as useless: ( 7, 5) [000541] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000627] ------------ | /--* LCL_VAR int V84 tmp75 N003 ( 7, 5) [000540] -A------R--- \--* ASG int N002 ( 3, 2) [000539] D------N---- \--* LCL_VAR int V34 tmp25 New refCnts for V34: refCnt = 0, refCntWtd = 0 New refCnts for V84: refCnt = 4, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000626] in BB14 as useless: ( 7, 5) [000626] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000623] ------------ | /--* LCL_VAR int V84 tmp75 N003 ( 7, 5) [000625] -A------R--- \--* ASG int N002 ( 3, 2) [000624] D------N---- \--* LCL_VAR int V38 tmp29 New refCnts for V38: refCnt = 1, refCntWtd = 0.50 New refCnts for V84: refCnt = 3, refCntWtd = 1.25 top level assign removing stmt with no side effects Removing statement [000631] in BB14 as useless: ( 5, 4) [000631] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000628] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000630] -A------R--- \--* ASG int N002 ( 3, 2) [000629] D------N---- \--* LCL_VAR int V38 tmp29 New refCnts for V38: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000618] in BB14 as useless: ( 5, 4) [000618] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000615] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000617] -A------R--- \--* ASG bool N002 ( 3, 2) [000616] D------N---- \--* LCL_VAR int V36 tmp27 New refCnts for V36: refCnt = 2, refCntWtd = 0.50 top level assign removing stmt with no side effects Removing statement [000614] in BB14 as useless: ( 5, 4) [000614] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000611] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000613] -A------R--- \--* ASG bool N002 ( 3, 2) [000612] D------N---- \--* LCL_VAR int V37 tmp28 New refCnts for V37: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000610] in BB14 as useless: ( 5, 4) [000610] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000607] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000609] -A------R--- \--* ASG bool N002 ( 3, 2) [000608] D------N---- \--* LCL_VAR int V35 tmp26 New refCnts for V35: refCnt = 2, refCntWtd = 1 top level assign removing stmt with no side effects Removing statement [000652] in BB16 as useless: ( 7, 5) [000652] ------------ * STMT void (IL 0x02A... ???) N001 ( 3, 2) [000649] ------------ | /--* LCL_VAR int V86 tmp77 N003 ( 7, 5) [000651] -A------R--- \--* ASG int N002 ( 3, 2) [000650] D------N---- \--* LCL_VAR int V40 tmp31 New refCnts for V40: refCnt = 1, refCntWtd = 0.25 New refCnts for V86: refCnt = 4, refCntWtd = 1.50 top level assign removing stmt with no side effects Removing statement [000657] in BB16 as useless: ( 5, 4) [000657] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000654] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000656] -A------R--- \--* ASG int N002 ( 3, 2) [000655] D------N---- \--* LCL_VAR int V40 tmp31 New refCnts for V40: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000054] in BB19 as useless: ( 7, 5) [000054] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000587] ------------ | /--* LCL_VAR int V37 tmp28 N003 ( 7, 5) [000053] -A------R--- \--* ASG int N002 ( 3, 2) [000052] D------N---- \--* LCL_VAR int V06 loc4 New refCnts for V06: refCnt = 0, refCntWtd = 0 New refCnts for V37: refCnt = 4, refCntWtd = 1.25 top level assign removing stmt with no side effects Removing statement [000769] in BB21 as useless: ( 7, 5) [000769] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000766] ------------ | /--* LCL_VAR int V90 tmp81 N003 ( 7, 5) [000768] -A------R--- \--* ASG int N002 ( 3, 2) [000767] D------N---- \--* LCL_VAR int V48 tmp39 New refCnts for V48: refCnt = 1, refCntWtd = 0.50 New refCnts for V90: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000774] in BB21 as useless: ( 5, 4) [000774] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000771] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000773] -A------R--- \--* ASG int N002 ( 3, 2) [000772] D------N---- \--* LCL_VAR int V48 tmp39 New refCnts for V48: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000671] in BB21 as useless: ( 7, 5) [000671] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000757] ------------ | /--* LCL_VAR int V88 tmp79 N003 ( 7, 5) [000670] -A------R--- \--* ASG int N002 ( 3, 2) [000669] D------N---- \--* LCL_VAR int V43 tmp34 New refCnts for V43: refCnt = 0, refCntWtd = 0 New refCnts for V88: refCnt = 4, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000756] in BB21 as useless: ( 7, 5) [000756] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000753] ------------ | /--* LCL_VAR int V88 tmp79 N003 ( 7, 5) [000755] -A------R--- \--* ASG int N002 ( 3, 2) [000754] D------N---- \--* LCL_VAR int V47 tmp38 New refCnts for V47: refCnt = 1, refCntWtd = 0.50 New refCnts for V88: refCnt = 3, refCntWtd = 1.25 top level assign removing stmt with no side effects Removing statement [000761] in BB21 as useless: ( 5, 4) [000761] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000758] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000760] -A------R--- \--* ASG int N002 ( 3, 2) [000759] D------N---- \--* LCL_VAR int V47 tmp38 New refCnts for V47: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000748] in BB21 as useless: ( 5, 4) [000748] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000745] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000747] -A------R--- \--* ASG bool N002 ( 3, 2) [000746] D------N---- \--* LCL_VAR int V45 tmp36 New refCnts for V45: refCnt = 2, refCntWtd = 0.50 top level assign removing stmt with no side effects Removing statement [000744] in BB21 as useless: ( 5, 4) [000744] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000741] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000743] -A------R--- \--* ASG bool N002 ( 3, 2) [000742] D------N---- \--* LCL_VAR int V46 tmp37 New refCnts for V46: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000740] in BB21 as useless: ( 5, 4) [000740] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000737] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000739] -A------R--- \--* ASG bool N002 ( 3, 2) [000738] D------N---- \--* LCL_VAR int V44 tmp35 New refCnts for V44: refCnt = 2, refCntWtd = 1 top level assign removing stmt with no side effects Removing statement [000782] in BB23 as useless: ( 7, 5) [000782] ------------ * STMT void (IL 0x047... ???) N001 ( 3, 2) [000779] ------------ | /--* LCL_VAR int V90 tmp81 N003 ( 7, 5) [000781] -A------R--- \--* ASG int N002 ( 3, 2) [000780] D------N---- \--* LCL_VAR int V49 tmp40 New refCnts for V49: refCnt = 1, refCntWtd = 0.25 New refCnts for V90: refCnt = 4, refCntWtd = 1.50 top level assign removing stmt with no side effects Removing statement [000787] in BB23 as useless: ( 5, 4) [000787] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000784] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000786] -A------R--- \--* ASG int N002 ( 3, 2) [000785] D------N---- \--* LCL_VAR int V49 tmp40 New refCnts for V49: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000084] in BB26 as useless: ( 7, 5) [000084] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000717] ------------ | /--* LCL_VAR int V46 tmp37 N003 ( 7, 5) [000083] -A------R--- \--* ASG int N002 ( 3, 2) [000082] D------N---- \--* LCL_VAR int V07 loc5 New refCnts for V07: refCnt = 0, refCntWtd = 0 New refCnts for V46: refCnt = 4, refCntWtd = 1.25 top level assign removing stmt with no side effects Removing statement [000899] in BB28 as useless: ( 7, 5) [000899] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000896] ------------ | /--* LCL_VAR int V94 tmp85 N003 ( 7, 5) [000898] -A------R--- \--* ASG int N002 ( 3, 2) [000897] D------N---- \--* LCL_VAR int V57 tmp48 New refCnts for V57: refCnt = 1, refCntWtd = 0.50 New refCnts for V94: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000904] in BB28 as useless: ( 5, 4) [000904] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000901] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000903] -A------R--- \--* ASG int N002 ( 3, 2) [000902] D------N---- \--* LCL_VAR int V57 tmp48 New refCnts for V57: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000801] in BB28 as useless: ( 7, 5) [000801] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000887] ------------ | /--* LCL_VAR int V92 tmp83 N003 ( 7, 5) [000800] -A------R--- \--* ASG int N002 ( 3, 2) [000799] D------N---- \--* LCL_VAR int V52 tmp43 New refCnts for V52: refCnt = 0, refCntWtd = 0 New refCnts for V92: refCnt = 4, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000886] in BB28 as useless: ( 7, 5) [000886] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000883] ------------ | /--* LCL_VAR int V92 tmp83 N003 ( 7, 5) [000885] -A------R--- \--* ASG int N002 ( 3, 2) [000884] D------N---- \--* LCL_VAR int V56 tmp47 New refCnts for V56: refCnt = 1, refCntWtd = 0.50 New refCnts for V92: refCnt = 3, refCntWtd = 1.25 top level assign removing stmt with no side effects Removing statement [000891] in BB28 as useless: ( 5, 4) [000891] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000888] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000890] -A------R--- \--* ASG int N002 ( 3, 2) [000889] D------N---- \--* LCL_VAR int V56 tmp47 New refCnts for V56: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000878] in BB28 as useless: ( 5, 4) [000878] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000875] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000877] -A------R--- \--* ASG bool N002 ( 3, 2) [000876] D------N---- \--* LCL_VAR int V54 tmp45 New refCnts for V54: refCnt = 2, refCntWtd = 0.50 top level assign removing stmt with no side effects Removing statement [000874] in BB28 as useless: ( 5, 4) [000874] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000871] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000873] -A------R--- \--* ASG bool N002 ( 3, 2) [000872] D------N---- \--* LCL_VAR int V55 tmp46 New refCnts for V55: refCnt = 5, refCntWtd = 1.75 top level assign removing stmt with no side effects Removing statement [000870] in BB28 as useless: ( 5, 4) [000870] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000867] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000869] -A------R--- \--* ASG bool N002 ( 3, 2) [000868] D------N---- \--* LCL_VAR int V53 tmp44 New refCnts for V53: refCnt = 2, refCntWtd = 1 top level assign removing stmt with no side effects Removing statement [000912] in BB30 as useless: ( 7, 5) [000912] ------------ * STMT void (IL 0x05C... ???) N001 ( 3, 2) [000909] ------------ | /--* LCL_VAR int V94 tmp85 N003 ( 7, 5) [000911] -A------R--- \--* ASG int N002 ( 3, 2) [000910] D------N---- \--* LCL_VAR int V58 tmp49 New refCnts for V58: refCnt = 1, refCntWtd = 0.25 New refCnts for V94: refCnt = 4, refCntWtd = 1.50 top level assign removing stmt with no side effects Removing statement [000917] in BB30 as useless: ( 5, 4) [000917] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000914] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000916] -A------R--- \--* ASG int N002 ( 3, 2) [000915] D------N---- \--* LCL_VAR int V58 tmp49 New refCnts for V58: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000105] in BB33 as useless: ( 7, 5) [000105] ------------ * STMT void (IL ???... ???) N001 ( 3, 2) [000847] ------------ | /--* LCL_VAR int V55 tmp46 N003 ( 7, 5) [000104] -A------R--- \--* ASG int N002 ( 3, 2) [000103] D------N---- \--* LCL_VAR int V08 loc6 New refCnts for V08: refCnt = 0, refCntWtd = 0 New refCnts for V55: refCnt = 4, refCntWtd = 1.25 In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal) Inserting phi functions: Inserting phi definition for V05 at start of BB36. Inserting phi definition for V55 at start of BB33. Inserting phi definition for ByrefExposed at start of BB33. Inserting phi definition for GcHeap at start of BB33. Inserting phi definition for V46 at start of BB26. Inserting phi definition for ByrefExposed at start of BB26. Inserting phi definition for GcHeap at start of BB26. Inserting phi definition for V37 at start of BB19. Inserting phi definition for ByrefExposed at start of BB19. Inserting phi definition for GcHeap at start of BB19. Inserting phi definition for V78 at start of BB14. Inserting phi definition for V79 at start of BB14. Inserting phi definition for ByrefExposed at start of BB14. Inserting phi definition for GcHeap at start of BB14. Inserting phi definition for V21 at start of BB09. Inserting phi definition for ByrefExposed at start of BB09. Inserting phi definition for GcHeap at start of BB09. Inserting phi definition for V67 at start of BB04. Inserting phi definition for V68 at start of BB04. Inserting phi definition for ByrefExposed at start of BB04. Inserting phi definition for GcHeap at start of BB04. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N003 ( 1, 1) [000167] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000168] ------------ | /--* EQ int N002 ( 3, 10) [000921] ------------ | | \--* NOP ref N001 ( 3, 10) [000920] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N006 ( 8, 12) [000170] -A------R--- \--* ASG bool N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 ***** BB01, stmt 2 ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000174] J------N---- \--* EQ int N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 3 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 N007 ( 10, 8) [000928] -A---------- \--* COMMA void N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000924] -A------R--- \--* ASG byref N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 ***** BB02, stmt 4 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) N006 ( 7, 5) [000934] -A------R--- | /--* ASG int N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 N007 ( 14, 10) [000935] -A---------- \--* COMMA void N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) N003 ( 7, 5) [000931] -A------R--- \--* ASG byref N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 5 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [000945] ------------ | /--* ADD byref N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 ***** BB03, stmt 6 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref N002 ( 3, 10) [000956] ------------ | | \--* NOP ref N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB03, stmt 7 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void N003 ( 0, 0) [000963] ------------ \--* COMMA void N001 ( 0, 0) [000959] ------------ \--* NOP void ***** BB03, stmt 8 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB03, stmt 9 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) N003 ( 7, 5) [000266] -A------R--- \--* ASG byref N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 ***** BB03, stmt 10 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) N003 ( 7, 5) [000971] -A------R--- \--* ASG byref N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 ***** BB03, stmt 11 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB03, stmt 12 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) N003 ( 7, 5) [000974] -A------R--- \--* ASG byref N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 13 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB04, stmt 14 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB04, stmt 15 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) N006 ( 7, 5) [000984] -A------R--- | /--* ASG int N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 N007 ( 14, 10) [000985] -A---------- \--* COMMA void N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) N003 ( 7, 5) [000981] -A------R--- \--* ASG byref N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 ***** BB04, stmt 16 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 N007 ( 10, 8) [000992] -A---------- \--* COMMA void N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 N003 ( 7, 5) [000988] -A------R--- \--* ASG byref N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 ***** BB04, stmt 17 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB04, stmt 18 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V73 tmp64 u:3 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB04, stmt 19 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 20 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 21 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 22 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 23 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 24 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 u:3 (last use) N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 u:3 (last use) N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 25 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 26 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000027] J------N---- \--* EQ int N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 27 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte N002 ( 4, 3) [000158] *--X---N---- \--* IND byte N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB10, stmt 28 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000163] -A------R--- \--* ASG int N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 29 ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N003 ( 1, 1) [000414] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000415] ------------ | /--* EQ int N002 ( 3, 10) [001063] ------------ | | \--* NOP ref N001 ( 3, 10) [001062] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N006 ( 12, 15) [000417] -A------R--- \--* ASG bool N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 ***** BB11, stmt 30 ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000421] J------N---- \--* EQ int N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 31 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 N007 ( 10, 8) [001070] -A---------- \--* COMMA void N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001066] -A------R--- \--* ASG byref N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 ***** BB12, stmt 32 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) N006 ( 7, 5) [001076] -A------R--- | /--* ASG int N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 N007 ( 14, 10) [001077] -A---------- \--* COMMA void N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 u:3 (last use) N003 ( 7, 5) [001073] -A------R--- \--* ASG byref N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 33 ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [001087] ------------ | /--* ADD byref N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 ***** BB13, stmt 34 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref N002 ( 3, 10) [001098] ------------ | | \--* NOP ref N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB13, stmt 35 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void N003 ( 0, 0) [001105] ------------ \--* COMMA void N001 ( 0, 0) [001101] ------------ \--* NOP void ***** BB13, stmt 36 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB13, stmt 37 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V26 tmp17 u:3 (last use) N003 ( 7, 5) [000513] -A------R--- \--* ASG byref N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 ***** BB13, stmt 38 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 u:3 (last use) N003 ( 7, 5) [001113] -A------R--- \--* ASG byref N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 ***** BB13, stmt 39 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB13, stmt 40 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 u:3 (last use) N003 ( 7, 5) [001116] -A------R--- \--* ASG byref N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 41 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB14, stmt 42 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB14, stmt 43 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) N006 ( 7, 5) [001126] -A------R--- | /--* ASG int N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 N007 ( 14, 10) [001127] -A---------- \--* COMMA void N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 u:3 (last use) N003 ( 7, 5) [001123] -A------R--- \--* ASG byref N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 ***** BB14, stmt 44 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 N007 ( 14, 10) [001134] -A---------- \--* COMMA void N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 N003 ( 7, 5) [001130] -A------R--- \--* ASG byref N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 ***** BB14, stmt 45 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB14, stmt 46 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V84 tmp75 u:3 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB14, stmt 47 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 48 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 49 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 50 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 51 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 52 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 u:3 (last use) N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 u:3 (last use) N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 53 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 54 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000057] J------N---- \--* EQ int N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 55 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte N002 ( 4, 3) [000148] *--X---N---- \--* IND byte N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB20, stmt 56 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000153] -A------R--- \--* ASG int N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 57 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 u:3 (last use) N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 ***** BB21, stmt 58 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) N006 ( 7, 5) [001217] -A------R--- | /--* ASG int N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 N007 ( 14, 10) [001218] -A---------- \--* COMMA void N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) N003 ( 7, 5) [001214] -A------R--- \--* ASG byref N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 ***** BB21, stmt 59 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 60 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 61 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 62 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 63 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 64 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 65 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 66 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 u:3 (last use) N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 67 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 68 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000087] J------N---- \--* EQ int N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 69 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte N002 ( 4, 3) [000138] *--X---N---- \--* IND byte N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB27, stmt 70 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000143] -A------R--- \--* ASG int N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 71 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) N006 ( 7, 5) [001292] -A------R--- | /--* ASG int N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 N007 ( 14, 10) [001293] -A---------- \--* COMMA void N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) N003 ( 7, 5) [001289] -A------R--- \--* ASG byref N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 ***** BB28, stmt 72 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 73 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 74 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 75 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 76 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 77 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 78 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 79 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 80 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 81 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000108] J------N---- \--* EQ int N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 82 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte N002 ( 4, 3) [000128] *--X---N---- \--* IND byte N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB34, stmt 83 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000133] -A------R--- \--* ASG int N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 84 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte N002 ( 4, 3) [000114] *--X---N---- \--* IND byte N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB35, stmt 85 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000119] -A------R--- \--* ASG int N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 86 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 87 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) ------------------------------------------------------------------------------------------------------------------- *************** In optEarlyProp() After optEarlyProp: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N003 ( 1, 1) [000167] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000168] ------------ | /--* EQ int N002 ( 3, 10) [000921] ------------ | | \--* NOP ref N001 ( 3, 10) [000920] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N006 ( 8, 12) [000170] -A------R--- \--* ASG bool N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 ***** BB01, stmt 2 ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000174] J------N---- \--* EQ int N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 3 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 N007 ( 10, 8) [000928] -A---------- \--* COMMA void N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000924] -A------R--- \--* ASG byref N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 ***** BB02, stmt 4 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) N006 ( 7, 5) [000934] -A------R--- | /--* ASG int N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 N007 ( 14, 10) [000935] -A---------- \--* COMMA void N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) N003 ( 7, 5) [000931] -A------R--- \--* ASG byref N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 5 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [000945] ------------ | /--* ADD byref N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 ***** BB03, stmt 6 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref N002 ( 3, 10) [000956] ------------ | | \--* NOP ref N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB03, stmt 7 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void N003 ( 0, 0) [000963] ------------ \--* COMMA void N001 ( 0, 0) [000959] ------------ \--* NOP void ***** BB03, stmt 8 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB03, stmt 9 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) N003 ( 7, 5) [000266] -A------R--- \--* ASG byref N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 ***** BB03, stmt 10 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) N003 ( 7, 5) [000971] -A------R--- \--* ASG byref N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 ***** BB03, stmt 11 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB03, stmt 12 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) N003 ( 7, 5) [000974] -A------R--- \--* ASG byref N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 13 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB04, stmt 14 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB04, stmt 15 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) N006 ( 7, 5) [000984] -A------R--- | /--* ASG int N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 N007 ( 14, 10) [000985] -A---------- \--* COMMA void N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) N003 ( 7, 5) [000981] -A------R--- \--* ASG byref N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 ***** BB04, stmt 16 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 N007 ( 10, 8) [000992] -A---------- \--* COMMA void N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 N003 ( 7, 5) [000988] -A------R--- \--* ASG byref N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 ***** BB04, stmt 17 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB04, stmt 18 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V73 tmp64 u:3 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB04, stmt 19 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 20 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 21 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 22 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 23 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 24 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V73 tmp64 u:3 (last use) N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V72 tmp63 u:3 (last use) N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 25 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 26 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000027] J------N---- \--* EQ int N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 27 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte N002 ( 4, 3) [000158] *--X---N---- \--* IND byte N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB10, stmt 28 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000163] -A------R--- \--* ASG int N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 29 ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N003 ( 1, 1) [000414] ------------ | /--* CNS_INT ref null N004 ( 8, 12) [000415] ------------ | /--* EQ int N002 ( 3, 10) [001063] ------------ | | \--* NOP ref N001 ( 3, 10) [001062] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N006 ( 12, 15) [000417] -A------R--- \--* ASG bool N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 ***** BB11, stmt 30 ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000421] J------N---- \--* EQ int N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 31 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 N007 ( 10, 8) [001070] -A---------- \--* COMMA void N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001066] -A------R--- \--* ASG byref N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 ***** BB12, stmt 32 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) N006 ( 7, 5) [001076] -A------R--- | /--* ASG int N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 N007 ( 14, 10) [001077] -A---------- \--* COMMA void N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 u:3 (last use) N003 ( 7, 5) [001073] -A------R--- \--* ASG byref N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 33 ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [001087] ------------ | /--* ADD byref N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 ***** BB13, stmt 34 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref N002 ( 3, 10) [001098] ------------ | | \--* NOP ref N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB13, stmt 35 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void N003 ( 0, 0) [001105] ------------ \--* COMMA void N001 ( 0, 0) [001101] ------------ \--* NOP void ***** BB13, stmt 36 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB13, stmt 37 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V26 tmp17 u:3 (last use) N003 ( 7, 5) [000513] -A------R--- \--* ASG byref N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 ***** BB13, stmt 38 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V82 tmp73 u:3 (last use) N003 ( 7, 5) [001113] -A------R--- \--* ASG byref N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 ***** BB13, stmt 39 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB13, stmt 40 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 u:3 (last use) N003 ( 7, 5) [001116] -A------R--- \--* ASG byref N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 41 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB14, stmt 42 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB14, stmt 43 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) N006 ( 7, 5) [001126] -A------R--- | /--* ASG int N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 N007 ( 14, 10) [001127] -A---------- \--* COMMA void N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 u:3 (last use) N003 ( 7, 5) [001123] -A------R--- \--* ASG byref N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 ***** BB14, stmt 44 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 N007 ( 14, 10) [001134] -A---------- \--* COMMA void N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 N003 ( 7, 5) [001130] -A------R--- \--* ASG byref N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 ***** BB14, stmt 45 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB14, stmt 46 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V84 tmp75 u:3 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB14, stmt 47 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 48 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 49 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 50 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 51 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 52 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V84 tmp75 u:3 (last use) N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V83 tmp74 u:3 (last use) N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 53 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 54 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000057] J------N---- \--* EQ int N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 55 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte N002 ( 4, 3) [000148] *--X---N---- \--* IND byte N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB20, stmt 56 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000153] -A------R--- \--* ASG int N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 57 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 u:3 (last use) N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 ***** BB21, stmt 58 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) N006 ( 7, 5) [001217] -A------R--- | /--* ASG int N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 N007 ( 14, 10) [001218] -A---------- \--* COMMA void N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) N003 ( 7, 5) [001214] -A------R--- \--* ASG byref N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 ***** BB21, stmt 59 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 60 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 61 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 62 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 63 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 64 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 65 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 66 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V87 tmp78 u:3 (last use) N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 67 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 68 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000087] J------N---- \--* EQ int N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 69 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte N002 ( 4, 3) [000138] *--X---N---- \--* IND byte N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB27, stmt 70 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000143] -A------R--- \--* ASG int N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 71 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) N006 ( 7, 5) [001292] -A------R--- | /--* ASG int N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 N007 ( 14, 10) [001293] -A---------- \--* COMMA void N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) N003 ( 7, 5) [001289] -A------R--- \--* ASG byref N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 ***** BB28, stmt 72 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 73 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 74 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 75 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 76 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 77 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 78 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 79 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 80 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 81 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000108] J------N---- \--* EQ int N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 82 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte N002 ( 4, 3) [000128] *--X---N---- \--* IND byte N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB34, stmt 83 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 N003 ( 1, 3) [000133] -A------R--- \--* ASG int N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 84 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte N002 ( 4, 3) [000114] *--X---N---- \--* IND byte N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) ***** BB35, stmt 85 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 N003 ( 1, 3) [000119] -A------R--- \--* ASG int N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 86 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 87 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) ------------------------------------------------------------------------------------------------------------------- *************** In fgValueNumber() Memory Initial Value in BB01 is: $140 The SSA definition for ByrefExposed (#2) at start of BB01 is $140 {InitVal($42)} The SSA definition for GcHeap (#2) at start of BB01 is $140 {InitVal($42)} ***** BB01, stmt 1 (before) N003 ( 1, 1) [000167] ------------ /--* CNS_INT ref null N004 ( 8, 12) [000168] ------------ /--* EQ int N002 ( 3, 10) [000921] ------------ | \--* NOP ref N001 ( 3, 10) [000920] ------------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N006 ( 8, 12) [000170] -A------R--- * ASG bool N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 N001 [000920] CNS_INT(h) 0x421150 [ICON_STR_HDL] => $180 {Hnd const: 0x0000000000421150} N002 [000921] NOP => $180 {Hnd const: 0x0000000000421150} N003 [000167] CNS_INT null => $VN.Null N004 [000168] EQ => $40 {IntCns 0} N005 [000169] LCL_VAR V09 tmp0 d:3 => $40 {IntCns 0} N006 [000170] ASG => $40 {IntCns 0} ***** BB01, stmt 1 (after) N003 ( 1, 1) [000167] ------------ /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000168] ------------ /--* EQ int $40 N002 ( 3, 10) [000921] ------------ | \--* NOP ref $180 N001 ( 3, 10) [000920] ------------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N006 ( 8, 12) [000170] -A------R--- * ASG bool $40 N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 --------- ***** BB01, stmt 2 (before) N004 ( 5, 5) [000175] ------------ * JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000174] J------N---- \--* EQ int N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) N001 [000172] LCL_VAR V09 tmp0 u:3 (last use) => $40 {IntCns 0} N002 [000173] CNS_INT 0 => $40 {IntCns 0} N003 [000174] EQ => $41 {IntCns 1} ***** BB01, stmt 2 (after) N004 ( 5, 5) [000175] ------------ * JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000174] J------N---- \--* EQ int $41 N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) $40 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB03). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB03 is $140 {InitVal($42)} The SSA definition for GcHeap (#2) at start of BB03 is $140 {InitVal($42)} ***** BB03, stmt 5 (before) N009 ( 1, 1) [000944] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [000945] ------------ /--* ADD byref N008 ( 3, 2) [000943] ------------ | \--* LCL_VAR ref V96 tmp87 u:4 (last use) N011 ( 16, 20) [000946] -A-XG--N---- /--* COMMA byref N006 ( 4, 3) [000941] ---X---N---- | | /--* NULLCHECK byte N005 ( 3, 2) [000940] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:4 N007 ( 11, 16) [000949] -A-X-------- | \--* COMMA void N002 ( 3, 10) [000948] ------------ | | /--* NOP ref N001 ( 3, 10) [000947] ------------ | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N004 ( 7, 13) [000939] -A------R--- | \--* ASG ref N003 ( 3, 2) [000938] D------N---- | \--* LCL_VAR ref V96 tmp87 d:4 N013 ( 20, 23) [000186] -A-XG---R--- * ASG byref N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 N001 [000947] CNS_INT(h) 0x421150 [ICON_STR_HDL] => $180 {Hnd const: 0x0000000000421150} N002 [000948] NOP => $180 {Hnd const: 0x0000000000421150} N003 [000938] LCL_VAR V96 tmp87 d:4 => $180 {Hnd const: 0x0000000000421150} N004 [000939] ASG => $180 {Hnd const: 0x0000000000421150} N005 [000940] LCL_VAR V96 tmp87 u:4 => $180 {Hnd const: 0x0000000000421150} $240 = singleton exc set {NullPtrExc($180)} $240 = singleton exc set {NullPtrExc($180)} N006 [000941] NULLCHECK => $241 {ValWithExc($3, $240)} N007 [000949] COMMA => $241 {ValWithExc($3, $240)} N008 [000943] LCL_VAR V96 tmp87 u:4 (last use) => $180 {Hnd const: 0x0000000000421150} N009 [000944] CNS_INT 12 field offset Fseq[_firstChar] => $280 {LngCns: 12} N010 [000945] ADD => $VN.Null N011 [000946] COMMA => $242 {ValWithExc($0, $240)} N012 [000185] LCL_VAR V10 tmp1 d:3 => $VN.Null N013 [000186] ASG => $242 {ValWithExc($0, $240)} ***** BB03, stmt 5 (after) N009 ( 1, 1) [000944] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [000949] -A-X-------- | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- * ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null --------- ***** BB03, stmt 6 (before) N005 ( 6, 13) [000236] x---G------- /--* IND int N003 ( 1, 1) [000953] ------------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [000954] -------N---- | \--* ADD byref N002 ( 3, 10) [000956] ------------ | \--* NOP ref N001 ( 3, 10) [000955] ------------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] N007 ( 10, 16) [000238] -A--G---R--- * ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 N001 [000955] CNS_INT(h) 0x421150 [ICON_STR_HDL] => $180 {Hnd const: 0x0000000000421150} N002 [000956] NOP => $180 {Hnd const: 0x0000000000421150} N003 [000953] CNS_INT 8 field offset Fseq[_stringLength] => $281 {LngCns: 8} N004 [000954] ADD => $VN.Null VNApplySelectors: VNForHandle(Fseq[_stringLength]) is $181, fieldType is int VNForMapSelect($140, $181):int returns $300 {$140[$181]} VNForMapSelect($300, $180):int returns $301 {$300[$180]} N005 [000236] IND => N006 [000237] LCL_VAR V14 tmp5 d:3 => N007 [000238] ASG => ***** BB03, stmt 6 (after) N005 ( 6, 13) [000236] x---G------- /--* IND int N003 ( 1, 1) [000953] ------------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [000954] -------N---- | \--* ADD byref $VN.Null N002 ( 3, 10) [000956] ------------ | \--* NOP ref $180 N001 ( 3, 10) [000955] ------------ | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N007 ( 10, 16) [000238] -A--G---R--- * ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 --------- ***** BB03, stmt 7 (before) N002 ( 0, 0) [000962] ------------ /--* NOP void N003 ( 0, 0) [000963] ------------ * COMMA void N001 ( 0, 0) [000959] ------------ \--* NOP void N001 [000959] NOP => $340 {340} N002 [000962] NOP => $341 {341} N003 [000963] COMMA => $341 {341} ***** BB03, stmt 7 (after) N002 ( 0, 0) [000962] ------------ /--* NOP void $341 N003 ( 0, 0) [000963] ------------ * COMMA void $341 N001 ( 0, 0) [000959] ------------ \--* NOP void $340 --------- ***** BB03, stmt 8 (before) N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 N001 [000964] ARGPLACE => $1c3 {1c3} N002 [000255] LIST => $380 {LIST($1c3, $0)} N003 [000240] LCL_VAR V14 tmp5 u:3 => N004 [000250] CNS_INT 0 => $40 {IntCns 0} N005 [000251] GE => N006 [000965] LIST => VN of ARGPLACE tree [000964] updated to N002 [000255] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000254] to VN: $201. N007 [000254] CALL => $VN.Void ***** BB03, stmt 8 (after) N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 --------- ***** BB03, stmt 9 (before) N001 ( 3, 2) [000188] ------------ /--* LCL_VAR byref V10 tmp1 u:3 (last use) N003 ( 7, 5) [000266] -A------R--- * ASG byref N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 N001 [000188] LCL_VAR V10 tmp1 u:3 (last use) => $VN.Null N002 [000265] LCL_VAR V71 tmp62 d:3 => $VN.Null N003 [000266] ASG => $VN.Null ***** BB03, stmt 9 (after) N001 ( 3, 2) [000188] ------------ /--* LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null N003 ( 7, 5) [000266] -A------R--- * ASG byref $VN.Null N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 $VN.Null --------- ***** BB03, stmt 10 (before) N001 ( 3, 2) [000970] -------N---- /--* LCL_VAR byref V71 tmp62 u:3 (last use) N003 ( 7, 5) [000971] -A------R--- * ASG byref N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 N001 [000970] LCL_VAR V71 tmp62 u:3 (last use) => $VN.Null N002 [000969] LCL_VAR V65 tmp56 d:3 => $VN.Null N003 [000971] ASG => $VN.Null ***** BB03, stmt 10 (after) N001 ( 3, 2) [000970] -------N---- /--* LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null N003 ( 7, 5) [000971] -A------R--- * ASG byref $VN.Null N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 $VN.Null --------- ***** BB03, stmt 11 (before) N001 ( 3, 2) [000276] ------------ /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- * ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 N001 [000276] LCL_VAR V14 tmp5 u:3 (last use) => N002 [000277] LCL_VAR V66 tmp57 d:3 => N003 [000278] ASG => ***** BB03, stmt 11 (after) N001 ( 3, 2) [000276] ------------ /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- * ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 --------- ***** BB03, stmt 12 (before) N004 ( 3, 2) [000976] -------N---- /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- /--* ASG int N005 ( 3, 2) [000975] D------N---- | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- * COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) N003 ( 7, 5) [000974] -A------R--- \--* ASG byref N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 N001 [000973] LCL_VAR V65 tmp56 u:3 (last use) => $VN.Null N002 [000972] LCL_VAR V67 tmp58 d:4 => $VN.Null N003 [000974] ASG => $VN.Null N004 [000976] LCL_VAR V66 tmp57 u:3 (last use) => N005 [000975] LCL_VAR V68 tmp59 d:4 => N006 [000977] ASG => N007 [000978] COMMA => ***** BB03, stmt 12 (after) N004 ( 3, 2) [000976] -------N---- /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- /--* ASG int N005 ( 3, 2) [000975] D------N---- | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- * COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null N003 ( 7, 5) [000974] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 $VN.Null finish(BB03). Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB02 is $140 {InitVal($42)} The SSA definition for GcHeap (#2) at start of BB02 is $140 {InitVal($42)} ***** BB02, stmt 3 (before) N004 ( 1, 1) [000926] ------------ /--* CNS_INT int 0 N006 ( 5, 4) [000927] -A------R--- /--* ASG int N005 ( 3, 2) [000925] D------N---- | \--* LCL_VAR int V70 tmp61 d:3 N007 ( 10, 8) [000928] -A---------- * COMMA void N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [000924] -A------R--- \--* ASG byref N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 N001 [000923] CNS_INT 0 => $VN.Null N002 [000922] LCL_VAR V69 tmp60 d:3 => $VN.Null N003 [000924] ASG => $VN.Null N004 [000926] CNS_INT 0 => $40 {IntCns 0} N005 [000925] LCL_VAR V70 tmp61 d:3 => $40 {IntCns 0} N006 [000927] ASG => $40 {IntCns 0} N007 [000928] COMMA => $40 {IntCns 0} ***** BB02, stmt 3 (after) N004 ( 1, 1) [000926] ------------ /--* CNS_INT int 0 $40 N006 ( 5, 4) [000927] -A------R--- /--* ASG int $40 N005 ( 3, 2) [000925] D------N---- | \--* LCL_VAR int V70 tmp61 d:3 $40 N007 ( 10, 8) [000928] -A---------- * COMMA void $40 N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [000924] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 $VN.Null --------- ***** BB02, stmt 4 (before) N004 ( 3, 2) [000933] -------N---- /--* LCL_VAR int V70 tmp61 u:3 (last use) N006 ( 7, 5) [000934] -A------R--- /--* ASG int N005 ( 3, 2) [000932] D------N---- | \--* LCL_VAR int V68 tmp59 d:5 N007 ( 14, 10) [000935] -A---------- * COMMA void N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) N003 ( 7, 5) [000931] -A------R--- \--* ASG byref N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 N001 [000930] LCL_VAR V69 tmp60 u:3 (last use) => $VN.Null N002 [000929] LCL_VAR V67 tmp58 d:5 => $VN.Null N003 [000931] ASG => $VN.Null N004 [000933] LCL_VAR V70 tmp61 u:3 (last use) => $40 {IntCns 0} N005 [000932] LCL_VAR V68 tmp59 d:5 => $40 {IntCns 0} N006 [000934] ASG => $40 {IntCns 0} N007 [000935] COMMA => $40 {IntCns 0} ***** BB02, stmt 4 (after) N004 ( 3, 2) [000933] -------N---- /--* LCL_VAR int V70 tmp61 u:3 (last use) $40 N006 ( 7, 5) [000934] -A------R--- /--* ASG int $40 N005 ( 3, 2) [000932] D------N---- | \--* LCL_VAR int V68 tmp59 d:5 $40 N007 ( 14, 10) [000935] -A---------- * COMMA void $40 N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) $VN.Null N003 ( 7, 5) [000931] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 $VN.Null finish(BB02). Succ(BB04). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 68/3 to $3c0 {PhiDef($44, $3, $304)}. In SSA definition, incoming phi args all same, set VN of local 67/3 to $VN.Null. Building phi application: $45 = SSA# 2. Building phi application: $46 = SSA# 37. Building phi application: $243 = phi($46, $45). The SSA definition for ByrefExposed (#3) at start of BB04 is $244 {PhiMemoryDef($182, $243)} Building phi application: $45 = SSA# 2. Building phi application: $47 = SSA# 38. Building phi application: $245 = phi($47, $45). The SSA definition for GcHeap (#4) at start of BB04 is $246 {PhiMemoryDef($182, $245)} ***** BB04, stmt 13 (before) N004 ( 3, 2) [000983] -------N---- /--* LCL_VAR int V68 tmp59 u:3 (last use) N006 ( 7, 5) [000984] -A------R--- /--* ASG int N005 ( 3, 2) [000982] D------N---- | \--* LCL_VAR int V62 tmp53 d:3 N007 ( 14, 10) [000985] -A---------- * COMMA void N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) N003 ( 7, 5) [000981] -A------R--- \--* ASG byref N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 N001 [000980] LCL_VAR V67 tmp58 u:3 (last use) => $VN.Null N002 [000979] LCL_VAR V61 tmp52 d:3 => $VN.Null N003 [000981] ASG => $VN.Null N004 [000983] LCL_VAR V68 tmp59 u:3 (last use) => $3c0 {PhiDef($44, $3, $304)} N005 [000982] LCL_VAR V62 tmp53 d:3 => $3c0 {PhiDef($44, $3, $304)} N006 [000984] ASG => $3c0 {PhiDef($44, $3, $304)} N007 [000985] COMMA => $3c0 {PhiDef($44, $3, $304)} ***** BB04, stmt 13 (after) N004 ( 3, 2) [000983] -------N---- /--* LCL_VAR int V68 tmp59 u:3 (last use) $3c0 N006 ( 7, 5) [000984] -A------R--- /--* ASG int $3c0 N005 ( 3, 2) [000982] D------N---- | \--* LCL_VAR int V62 tmp53 d:3 $3c0 N007 ( 14, 10) [000985] -A---------- * COMMA void $3c0 N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null N003 ( 7, 5) [000981] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 $VN.Null --------- ***** BB04, stmt 14 (before) N004 ( 3, 2) [000990] -------N---- /--* LCL_VAR int V62 tmp53 u:3 N006 ( 3, 3) [000991] -A------R--- /--* ASG int N005 ( 1, 1) [000989] D------N---- | \--* LCL_VAR int V73 tmp64 d:3 N007 ( 10, 8) [000992] -A---------- * COMMA void N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 N003 ( 7, 5) [000988] -A------R--- \--* ASG byref N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 N001 [000987] LCL_VAR V61 tmp52 u:3 => $VN.Null N002 [000986] LCL_VAR V72 tmp63 d:3 => $VN.Null N003 [000988] ASG => $VN.Null N004 [000990] LCL_VAR V62 tmp53 u:3 => $3c0 {PhiDef($44, $3, $304)} N005 [000989] LCL_VAR V73 tmp64 d:3 => $3c0 {PhiDef($44, $3, $304)} N006 [000991] ASG => $3c0 {PhiDef($44, $3, $304)} N007 [000992] COMMA => $3c0 {PhiDef($44, $3, $304)} ***** BB04, stmt 14 (after) N004 ( 3, 2) [000990] -------N---- /--* LCL_VAR int V62 tmp53 u:3 $3c0 N006 ( 3, 3) [000991] -A------R--- /--* ASG int $3c0 N005 ( 1, 1) [000989] D------N---- | \--* LCL_VAR int V73 tmp64 d:3 $3c0 N007 ( 10, 8) [000992] -A---------- * COMMA void $3c0 N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [000988] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 $VN.Null --------- ***** BB04, stmt 15 (before) N010 ( 4, 4) [001004] x----------- /--* IND int N008 ( 1, 1) [001002] ------------ | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001003] -------N---- | \--* ADD byref N007 ( 1, 1) [001001] ------------ | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 4, 4) [001005] -A------R--- /--* ASG int N011 ( 1, 1) [001000] D------N---- | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- * COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 N001 [000995] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [000996] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N003 [000997] ADD => $400 {ADD($80, $282)} N004 [000998] IND => N005 [000994] LCL_VAR V74 tmp65 d:3 => N006 [000999] ASG => N007 [001001] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N008 [001002] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N009 [001003] ADD => $401 {ADD($80, $281)} N010 [001004] IND => N011 [001000] LCL_VAR V75 tmp66 d:3 => N012 [001005] ASG => N013 [001006] COMMA => ***** BB04, stmt 15 (after) N010 ( 4, 4) [001004] x----------- /--* IND int N008 ( 1, 1) [001002] ------------ | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001003] -------N---- | \--* ADD byref $401 N007 ( 1, 1) [001001] ------------ | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [001005] -A------R--- /--* ASG int N011 ( 1, 1) [001000] D------N---- | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- * COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 --------- ***** BB04, stmt 16 (before) N002 ( 1, 1) [000393] ------------ /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ /--* NE int N001 ( 1, 1) [000295] ------------ | \--* LCL_VAR int V73 tmp64 u:3 N005 ( 6, 3) [000301] -A------R--- * ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 N001 [000295] LCL_VAR V73 tmp64 u:3 => $3c0 {PhiDef($44, $3, $304)} N002 [000393] LCL_VAR V75 tmp66 u:3 => N003 [000297] NE => N004 [000300] LCL_VAR V19 tmp10 d:3 => N005 [000301] ASG => ***** BB04, stmt 16 (after) N002 ( 1, 1) [000393] ------------ /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ /--* NE int N001 ( 1, 1) [000295] ------------ | \--* LCL_VAR int V73 tmp64 u:3 $3c0 N005 ( 6, 3) [000301] -A------R--- * ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 --------- ***** BB04, stmt 17 (before) N004 ( 5, 5) [000306] ------------ * JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) N001 [000303] LCL_VAR V19 tmp10 u:3 (last use) => N002 [000304] CNS_INT 0 => $40 {IntCns 0} N003 [000305] EQ => ***** BB04, stmt 17 (after) N004 ( 5, 5) [000306] ------------ * JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) finish(BB04). Succ(BB05). Not yet completed. All preds complete, adding to allDone. Succ(BB06). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#3) at start of BB06 is $244 {PhiMemoryDef($182, $243)} The SSA definition for GcHeap (#4) at start of BB06 is $246 {PhiMemoryDef($182, $245)} ***** BB06, stmt 21 (before) N002 ( 1, 1) [000314] ------------ /--* CNS_INT int 0 N003 ( 6, 3) [000315] ------------ /--* EQ int N001 ( 1, 1) [000406] ------------ | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- * ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 N001 [000406] LCL_VAR V75 tmp66 u:3 => N002 [000314] CNS_INT 0 => $40 {IntCns 0} N003 [000315] EQ => N004 [000316] LCL_VAR V20 tmp11 d:3 => N005 [000317] ASG => ***** BB06, stmt 21 (after) N002 ( 1, 1) [000314] ------------ /--* CNS_INT int 0 $40 N003 ( 6, 3) [000315] ------------ /--* EQ int N001 ( 1, 1) [000406] ------------ | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- * ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 --------- ***** BB06, stmt 22 (before) N004 ( 7, 6) [000322] ------------ * JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) N001 [000319] LCL_VAR V20 tmp11 u:3 (last use) => N002 [000320] CNS_INT 0 => $40 {IntCns 0} N003 [000321] EQ => ***** BB06, stmt 22 (after) N004 ( 7, 6) [000322] ------------ * JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) finish(BB06). Succ(BB07). Not yet completed. All preds complete, adding to allDone. Succ(BB08). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#3) at start of BB08 is $244 {PhiMemoryDef($182, $243)} The SSA definition for GcHeap (#4) at start of BB08 is $246 {PhiMemoryDef($182, $245)} ***** BB08, stmt 24 (before) N046 ( 1, 1) [000334] ------------ /--* CNS_INT int 0 N047 ( 81, 55) [000335] -ACXG------- /--* EQ int N045 ( 76, 53) [000327] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 1, 1) [001030] -------N---- | | /--* LCL_VAR int V73 tmp64 u:3 (last use) N017 ( 8, 7) [001031] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001029] *------N---- | | | \--* IND int N013 ( 1, 1) [001027] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001028] -------N---- | | | \--* ADD byref N012 ( 3, 2) [001026] ------------ | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | +--* COMMA void N009 ( 3, 2) [001023] -------N---- | | | /--* LCL_VAR byref V72 tmp63 u:3 (last use) N010 ( 10, 7) [001024] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001022] *------N---- | | | | \--* IND byref N006 ( 1, 1) [001020] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001021] -------N---- | | | | \--* ADD byref N005 ( 3, 2) [001019] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 N011 ( 17, 13) [001025] -A---------- | | \--* COMMA void N002 ( 3, 3) [001015] L----------- | | | /--* ADDR byref N001 ( 3, 2) [001016] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001018] -A------R--- | | \--* ASG byref N003 ( 3, 2) [001017] D------N---- | | \--* LCL_VAR byref V98 tmp89 d:3 N034 ( 1, 1) [001051] -------N---- | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001050] *------N---- | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001049] -------N---- | | | \--* ADD byref N030 ( 3, 2) [001047] ------------ | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | +--* COMMA void N027 ( 3, 2) [001044] -------N---- | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001043] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001042] -------N---- | | | | \--* ADD byref N023 ( 3, 2) [001040] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 N029 ( 17, 13) [001046] -A---------- | | \--* COMMA void N020 ( 3, 3) [001036] L----------- | | | /--* ADDR byref N019 ( 3, 2) [001037] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001039] -A------R--- | | \--* ASG byref N021 ( 3, 2) [001038] D------N---- | | \--* LCL_VAR byref V100 tmp91 d:3 N040 ( 3, 3) [001055] L----------- arg0 in rcx | +--* ADDR byref N039 ( 3, 2) [001054] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001058] L----------- arg1 in rdx | \--* ADDR byref N041 ( 3, 2) [001057] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 81, 55) [000337] -ACXG---R--- * ASG bool N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 N001 [001016] LCL_VAR V97 tmp88 => $480 {ByrefExposedLoad($4b, $402, $244)} N002 [001015] ADDR => $2ca {2ca} N003 [001017] LCL_VAR V98 tmp89 d:3 => $2ca {2ca} N004 [001018] ASG => $2ca {2ca} N005 [001019] LCL_VAR V98 tmp89 u:3 => $2ca {2ca} N006 [001020] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N007 [001021] ADD => $403 {ADD($282, $2ca)} N009 [001023] LCL_VAR V72 tmp63 u:3 (last use) => $VN.Null fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001024] to VN: $202. N010 [001024] ASG => $VN.Void N011 [001025] COMMA => $VN.Void N012 [001026] LCL_VAR V98 tmp89 u:3 (last use) => $2ca {2ca} N013 [001027] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N014 [001028] ADD => $404 {ADD($281, $2ca)} N016 [001030] LCL_VAR V73 tmp64 u:3 (last use) => $3c0 {PhiDef($44, $3, $304)} fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001031] to VN: $203. N017 [001031] ASG => $VN.Void N018 [001032] COMMA => $VN.Void N019 [001037] LCL_VAR V99 tmp90 => $481 {ByrefExposedLoad($4b, $405, $103)} N020 [001036] ADDR => $2cc {2cc} N021 [001038] LCL_VAR V100 tmp91 d:3 => $2cc {2cc} N022 [001039] ASG => $2cc {2cc} N023 [001040] LCL_VAR V100 tmp91 u:3 => $2cc {2cc} N024 [001041] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N025 [001042] ADD => $406 {ADD($282, $2cc)} N027 [001044] LCL_VAR V74 tmp65 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001045] to VN: $204. N028 [001045] ASG => $VN.Void N029 [001046] COMMA => $VN.Void N030 [001047] LCL_VAR V100 tmp91 u:3 (last use) => $2cc {2cc} N031 [001048] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N032 [001049] ADD => $407 {ADD($281, $2cc)} N034 [001051] LCL_VAR V75 tmp66 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001052] to VN: $205. N035 [001052] ASG => $VN.Void N036 [001053] COMMA => $VN.Void N037 [000330] LIST => $383 {LIST($3, $0)} N038 [000333] LIST => $384 {LIST($3, $383)} N039 [001054] LCL_VAR V97 tmp88 => $482 {ByrefExposedLoad($4b, $402, $105)} N040 [001055] ADDR => $2ce {2ce} N041 [001057] LCL_VAR V99 tmp90 => $483 {ByrefExposedLoad($4b, $405, $105)} N042 [001058] ADDR => $2cf {2cf} N043 [001059] LIST => $385 {LIST($2cf, $0)} N044 [001056] LIST => $386 {LIST($2ce, $385)} fgCurMemoryVN[GcHeap] assigned by CALL at [000327] to VN: $206. N045 [000327] CALL => $1ce {1ce} N046 [000334] CNS_INT 0 => $40 {IntCns 0} N047 [000335] EQ => $30d {EQ($1ce, $40)} N048 [000336] LCL_VAR V21 tmp12 d:3 => $30d {EQ($1ce, $40)} N049 [000337] ASG => $30d {EQ($1ce, $40)} ***** BB08, stmt 24 (after) N046 ( 1, 1) [000334] ------------ /--* CNS_INT int 0 $40 N047 ( 81, 55) [000335] -ACXG------- /--* EQ int $30d N045 ( 76, 53) [000327] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N016 ( 1, 1) [001030] -------N---- | | /--* LCL_VAR int V73 tmp64 u:3 (last use) $3c0 N017 ( 8, 7) [001031] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001029] *------N---- | | | \--* IND int $3c0 N013 ( 1, 1) [001027] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001028] -------N---- | | | \--* ADD byref $404 N012 ( 3, 2) [001026] ------------ | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | +--* COMMA void $VN.Void N009 ( 3, 2) [001023] -------N---- | | | /--* LCL_VAR byref V72 tmp63 u:3 (last use) $VN.Null N010 ( 10, 7) [001024] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001022] *------N---- | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001020] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001021] -------N---- | | | | \--* ADD byref $403 N005 ( 3, 2) [001019] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 $2ca N011 ( 17, 13) [001025] -A---------- | | \--* COMMA void $VN.Void N002 ( 3, 3) [001015] L----------- | | | /--* ADDR byref $2ca N001 ( 3, 2) [001016] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 $480 N004 ( 7, 6) [001018] -A------R--- | | \--* ASG byref $2ca N003 ( 3, 2) [001017] D------N---- | | \--* LCL_VAR byref V98 tmp89 d:3 $2ca N034 ( 1, 1) [001051] -------N---- | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001050] *------N---- | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001049] -------N---- | | | \--* ADD byref $407 N030 ( 3, 2) [001047] ------------ | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N027 ( 3, 2) [001044] -------N---- | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001043] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001042] -------N---- | | | | \--* ADD byref $406 N023 ( 3, 2) [001040] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 $2cc N029 ( 17, 13) [001046] -A---------- | | \--* COMMA void $VN.Void N020 ( 3, 3) [001036] L----------- | | | /--* ADDR byref $2cc N019 ( 3, 2) [001037] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 $481 N022 ( 7, 6) [001039] -A------R--- | | \--* ASG byref $2cc N021 ( 3, 2) [001038] D------N---- | | \--* LCL_VAR byref V100 tmp91 d:3 $2cc N040 ( 3, 3) [001055] L----------- arg0 in rcx | +--* ADDR byref $2ce N039 ( 3, 2) [001054] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 $482 N042 ( 3, 3) [001058] L----------- arg1 in rdx | \--* ADDR byref $2cf N041 ( 3, 2) [001057] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 $483 N049 ( 81, 55) [000337] -ACXG---R--- * ASG bool $30d N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 $30d finish(BB08). Succ(BB09). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#3) at start of BB07 is $244 {PhiMemoryDef($182, $243)} The SSA definition for GcHeap (#4) at start of BB07 is $246 {PhiMemoryDef($182, $245)} ***** BB07, stmt 23 (before) N001 ( 1, 1) [000343] ------------ /--* CNS_INT int 1 N003 ( 1, 3) [000345] -A------R--- * ASG bool N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 N001 [000343] CNS_INT 1 => $41 {IntCns 1} N002 [000344] LCL_VAR V21 tmp12 d:4 => $41 {IntCns 1} N003 [000345] ASG => $41 {IntCns 1} ***** BB07, stmt 23 (after) N001 ( 1, 1) [000343] ------------ /--* CNS_INT int 1 $41 N003 ( 1, 3) [000345] -A------R--- * ASG bool $41 N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 $41 finish(BB07). Succ(BB09). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#3) at start of BB05 is $244 {PhiMemoryDef($182, $243)} The SSA definition for GcHeap (#4) at start of BB05 is $246 {PhiMemoryDef($182, $245)} ***** BB05, stmt 20 (before) N001 ( 1, 1) [000348] ------------ /--* CNS_INT int 0 N003 ( 1, 3) [000350] -A------R--- * ASG bool N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 N001 [000348] CNS_INT 0 => $40 {IntCns 0} N002 [000349] LCL_VAR V21 tmp12 d:5 => $40 {IntCns 0} N003 [000350] ASG => $40 {IntCns 0} ***** BB05, stmt 20 (after) N001 ( 1, 1) [000348] ------------ /--* CNS_INT int 0 $40 N003 ( 1, 3) [000350] -A------R--- * ASG bool $40 N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 $40 finish(BB05). Succ(BB09). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 21/6 to $500 {PhiDef($15, $6, $4c0)}. Building phi application: $4d = SSA# 3. Building phi application: $43 = SSA# 5. Building phi application: $247 = phi($43, $4d). The SSA definition for ByrefExposed (#7) at start of BB09 is $248 {PhiMemoryDef($183, $247)} Building phi application: $44 = SSA# 4. Building phi application: $4e = SSA# 6. Building phi application: $249 = phi($4e, $44). The SSA definition for GcHeap (#8) at start of BB09 is $24a {PhiMemoryDef($183, $249)} ***** BB09, stmt 25 (before) N004 ( 5, 5) [000028] ------------ * JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 N003 ( 3, 3) [000027] J------N---- \--* EQ int N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) N001 [000025] LCL_VAR V21 tmp12 u:6 (last use) => $500 {PhiDef($15, $6, $4c0)} N002 [000026] CNS_INT 0 => $40 {IntCns 0} N003 [000027] EQ => $30e {EQ($500, $40)} ***** BB09, stmt 25 (after) N004 ( 5, 5) [000028] ------------ * JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000027] J------N---- \--* EQ int $30e N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) $500 finish(BB09). Succ(BB10). Not yet completed. All preds complete, adding to allDone. Succ(BB11). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#7) at start of BB11 is $248 {PhiMemoryDef($183, $247)} The SSA definition for GcHeap (#8) at start of BB11 is $24a {PhiMemoryDef($183, $249)} ***** BB11, stmt 29 (before) N003 ( 1, 1) [000414] ------------ /--* CNS_INT ref null N004 ( 8, 12) [000415] ------------ /--* EQ int N002 ( 3, 10) [001063] ------------ | \--* NOP ref N001 ( 3, 10) [001062] ------------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N006 ( 12, 15) [000417] -A------R--- * ASG bool N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 N001 [001062] CNS_INT(h) 0x421158 [ICON_STR_HDL] => $184 {Hnd const: 0x0000000000421158} N002 [001063] NOP => $184 {Hnd const: 0x0000000000421158} N003 [000414] CNS_INT null => $VN.Null N004 [000415] EQ => $40 {IntCns 0} N005 [000416] LCL_VAR V25 tmp16 d:3 => $40 {IntCns 0} N006 [000417] ASG => $40 {IntCns 0} ***** BB11, stmt 29 (after) N003 ( 1, 1) [000414] ------------ /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000415] ------------ /--* EQ int $40 N002 ( 3, 10) [001063] ------------ | \--* NOP ref $184 N001 ( 3, 10) [001062] ------------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N006 ( 12, 15) [000417] -A------R--- * ASG bool $40 N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 --------- ***** BB11, stmt 30 (before) N004 ( 7, 6) [000422] ------------ * JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000421] J------N---- \--* EQ int N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) N001 [000419] LCL_VAR V25 tmp16 u:3 (last use) => $40 {IntCns 0} N002 [000420] CNS_INT 0 => $40 {IntCns 0} N003 [000421] EQ => $41 {IntCns 1} ***** BB11, stmt 30 (after) N004 ( 7, 6) [000422] ------------ * JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000421] J------N---- \--* EQ int $41 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) $40 finish(BB11). Succ(BB12). Not yet completed. All preds complete, adding to allDone. Succ(BB13). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#7) at start of BB13 is $248 {PhiMemoryDef($183, $247)} The SSA definition for GcHeap (#8) at start of BB13 is $24a {PhiMemoryDef($183, $249)} ***** BB13, stmt 33 (before) N009 ( 1, 1) [001086] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] N010 ( 5, 4) [001087] ------------ /--* ADD byref N008 ( 3, 2) [001085] ------------ | \--* LCL_VAR ref V96 tmp87 u:3 (last use) N011 ( 16, 20) [001088] -A-XG--N---- /--* COMMA byref N006 ( 4, 3) [001083] ---X---N---- | | /--* NULLCHECK byte N005 ( 3, 2) [001082] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:3 N007 ( 11, 16) [001091] -A-X-------- | \--* COMMA void N002 ( 3, 10) [001090] ------------ | | /--* NOP ref N001 ( 3, 10) [001089] ------------ | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N004 ( 7, 13) [001081] -A------R--- | \--* ASG ref N003 ( 3, 2) [001080] D------N---- | \--* LCL_VAR ref V96 tmp87 d:3 N013 ( 20, 23) [000433] -A-XG---R--- * ASG byref N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 N001 [001089] CNS_INT(h) 0x421158 [ICON_STR_HDL] => $184 {Hnd const: 0x0000000000421158} N002 [001090] NOP => $184 {Hnd const: 0x0000000000421158} N003 [001080] LCL_VAR V96 tmp87 d:3 => $184 {Hnd const: 0x0000000000421158} N004 [001081] ASG => $184 {Hnd const: 0x0000000000421158} N005 [001082] LCL_VAR V96 tmp87 u:3 => $184 {Hnd const: 0x0000000000421158} $24b = singleton exc set {NullPtrExc($184)} $24b = singleton exc set {NullPtrExc($184)} N006 [001083] NULLCHECK => $24c {ValWithExc($3, $24b)} N007 [001091] COMMA => $24c {ValWithExc($3, $24b)} N008 [001085] LCL_VAR V96 tmp87 u:3 (last use) => $184 {Hnd const: 0x0000000000421158} N009 [001086] CNS_INT 12 field offset Fseq[_firstChar] => $280 {LngCns: 12} N010 [001087] ADD => $VN.Null N011 [001088] COMMA => $24d {ValWithExc($0, $24b)} N012 [000432] LCL_VAR V26 tmp17 d:3 => $VN.Null N013 [000433] ASG => $24d {ValWithExc($0, $24b)} ***** BB13, stmt 33 (after) N009 ( 1, 1) [001086] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [001087] ------------ /--* ADD byref $VN.Null N008 ( 3, 2) [001085] ------------ | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 16, 20) [001088] -A-XG--N---- /--* COMMA byref $24d N006 ( 4, 3) [001083] ---X---N---- | | /--* NULLCHECK byte $24c N005 ( 3, 2) [001082] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 11, 16) [001091] -A-X-------- | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 7, 13) [001081] -A------R--- | \--* ASG ref $184 N003 ( 3, 2) [001080] D------N---- | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 20, 23) [000433] -A-XG---R--- * ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null --------- ***** BB13, stmt 34 (before) N005 ( 6, 13) [000483] x---G------- /--* IND int N003 ( 1, 1) [001095] ------------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] N004 ( 4, 11) [001096] -------N---- | \--* ADD byref N002 ( 3, 10) [001098] ------------ | \--* NOP ref N001 ( 3, 10) [001097] ------------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] N007 ( 10, 16) [000485] -A--G---R--- * ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 N001 [001097] CNS_INT(h) 0x421158 [ICON_STR_HDL] => $184 {Hnd const: 0x0000000000421158} N002 [001098] NOP => $184 {Hnd const: 0x0000000000421158} N003 [001095] CNS_INT 8 field offset Fseq[_stringLength] => $281 {LngCns: 8} N004 [001096] ADD => $VN.Null VNApplySelectors: VNForHandle(Fseq[_stringLength]) is $181, fieldType is int VNForMapSelect($24a, $181):int returns $312 {$24a[$181]} VNForMapSelect($312, $184):int returns $313 {$312[$184]} N005 [000483] IND => N006 [000484] LCL_VAR V30 tmp21 d:3 => N007 [000485] ASG => ***** BB13, stmt 34 (after) N005 ( 6, 13) [000483] x---G------- /--* IND int N003 ( 1, 1) [001095] ------------ | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [001096] -------N---- | \--* ADD byref $VN.Null N002 ( 3, 10) [001098] ------------ | \--* NOP ref $184 N001 ( 3, 10) [001097] ------------ | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N007 ( 10, 16) [000485] -A--G---R--- * ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 --------- ***** BB13, stmt 35 (before) N002 ( 0, 0) [001104] ------------ /--* NOP void N003 ( 0, 0) [001105] ------------ * COMMA void N001 ( 0, 0) [001101] ------------ \--* NOP void N001 [001101] NOP => $342 {342} N002 [001104] NOP => $343 {343} N003 [001105] COMMA => $343 {343} ***** BB13, stmt 35 (after) N002 ( 0, 0) [001104] ------------ /--* NOP void $343 N003 ( 0, 0) [001105] ------------ * COMMA void $343 N001 ( 0, 0) [001101] ------------ \--* NOP void $342 --------- ***** BB13, stmt 36 (before) N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 N001 [001106] ARGPLACE => $1d5 {1d5} N002 [000502] LIST => $387 {LIST($1d5, $0)} N003 [000487] LCL_VAR V30 tmp21 u:3 => N004 [000497] CNS_INT 0 => $40 {IntCns 0} N005 [000498] GE => N006 [001107] LIST => VN of ARGPLACE tree [001106] updated to N002 [000502] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000501] to VN: $208. N007 [000501] CALL => $VN.Void ***** BB13, stmt 36 (after) N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 --------- ***** BB13, stmt 37 (before) N001 ( 3, 2) [000435] ------------ /--* LCL_VAR byref V26 tmp17 u:3 (last use) N003 ( 7, 5) [000513] -A------R--- * ASG byref N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 N001 [000435] LCL_VAR V26 tmp17 u:3 (last use) => $VN.Null N002 [000512] LCL_VAR V82 tmp73 d:3 => $VN.Null N003 [000513] ASG => $VN.Null ***** BB13, stmt 37 (after) N001 ( 3, 2) [000435] ------------ /--* LCL_VAR byref V26 tmp17 u:3 (last use) $VN.Null N003 ( 7, 5) [000513] -A------R--- * ASG byref $VN.Null N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 $VN.Null --------- ***** BB13, stmt 38 (before) N001 ( 3, 2) [001112] -------N---- /--* LCL_VAR byref V82 tmp73 u:3 (last use) N003 ( 7, 5) [001113] -A------R--- * ASG byref N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 N001 [001112] LCL_VAR V82 tmp73 u:3 (last use) => $VN.Null N002 [001111] LCL_VAR V76 tmp67 d:3 => $VN.Null N003 [001113] ASG => $VN.Null ***** BB13, stmt 38 (after) N001 ( 3, 2) [001112] -------N---- /--* LCL_VAR byref V82 tmp73 u:3 (last use) $VN.Null N003 ( 7, 5) [001113] -A------R--- * ASG byref $VN.Null N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 $VN.Null --------- ***** BB13, stmt 39 (before) N001 ( 3, 2) [000523] ------------ /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- * ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 N001 [000523] LCL_VAR V30 tmp21 u:3 (last use) => N002 [000524] LCL_VAR V77 tmp68 d:3 => N003 [000525] ASG => ***** BB13, stmt 39 (after) N001 ( 3, 2) [000523] ------------ /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- * ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 --------- ***** BB13, stmt 40 (before) N004 ( 3, 2) [001118] -------N---- /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- /--* ASG int N005 ( 3, 2) [001117] D------N---- | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- * COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 u:3 (last use) N003 ( 7, 5) [001116] -A------R--- \--* ASG byref N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 N001 [001115] LCL_VAR V76 tmp67 u:3 (last use) => $VN.Null N002 [001114] LCL_VAR V78 tmp69 d:4 => $VN.Null N003 [001116] ASG => $VN.Null N004 [001118] LCL_VAR V77 tmp68 u:3 (last use) => N005 [001117] LCL_VAR V79 tmp70 d:4 => N006 [001119] ASG => N007 [001120] COMMA => ***** BB13, stmt 40 (after) N004 ( 3, 2) [001118] -------N---- /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- /--* ASG int N005 ( 3, 2) [001117] D------N---- | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- * COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V76 tmp67 u:3 (last use) $VN.Null N003 ( 7, 5) [001116] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 $VN.Null finish(BB13). Succ(BB14). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#7) at start of BB12 is $248 {PhiMemoryDef($183, $247)} The SSA definition for GcHeap (#8) at start of BB12 is $24a {PhiMemoryDef($183, $249)} ***** BB12, stmt 31 (before) N004 ( 1, 1) [001068] ------------ /--* CNS_INT int 0 N006 ( 5, 4) [001069] -A------R--- /--* ASG int N005 ( 3, 2) [001067] D------N---- | \--* LCL_VAR int V81 tmp72 d:3 N007 ( 10, 8) [001070] -A---------- * COMMA void N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 N003 ( 5, 4) [001066] -A------R--- \--* ASG byref N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 N001 [001065] CNS_INT 0 => $VN.Null N002 [001064] LCL_VAR V80 tmp71 d:3 => $VN.Null N003 [001066] ASG => $VN.Null N004 [001068] CNS_INT 0 => $40 {IntCns 0} N005 [001067] LCL_VAR V81 tmp72 d:3 => $40 {IntCns 0} N006 [001069] ASG => $40 {IntCns 0} N007 [001070] COMMA => $40 {IntCns 0} ***** BB12, stmt 31 (after) N004 ( 1, 1) [001068] ------------ /--* CNS_INT int 0 $40 N006 ( 5, 4) [001069] -A------R--- /--* ASG int $40 N005 ( 3, 2) [001067] D------N---- | \--* LCL_VAR int V81 tmp72 d:3 $40 N007 ( 10, 8) [001070] -A---------- * COMMA void $40 N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [001066] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 $VN.Null --------- ***** BB12, stmt 32 (before) N004 ( 3, 2) [001075] -------N---- /--* LCL_VAR int V81 tmp72 u:3 (last use) N006 ( 7, 5) [001076] -A------R--- /--* ASG int N005 ( 3, 2) [001074] D------N---- | \--* LCL_VAR int V79 tmp70 d:5 N007 ( 14, 10) [001077] -A---------- * COMMA void N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 u:3 (last use) N003 ( 7, 5) [001073] -A------R--- \--* ASG byref N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 N001 [001072] LCL_VAR V80 tmp71 u:3 (last use) => $VN.Null N002 [001071] LCL_VAR V78 tmp69 d:5 => $VN.Null N003 [001073] ASG => $VN.Null N004 [001075] LCL_VAR V81 tmp72 u:3 (last use) => $40 {IntCns 0} N005 [001074] LCL_VAR V79 tmp70 d:5 => $40 {IntCns 0} N006 [001076] ASG => $40 {IntCns 0} N007 [001077] COMMA => $40 {IntCns 0} ***** BB12, stmt 32 (after) N004 ( 3, 2) [001075] -------N---- /--* LCL_VAR int V81 tmp72 u:3 (last use) $40 N006 ( 7, 5) [001076] -A------R--- /--* ASG int $40 N005 ( 3, 2) [001074] D------N---- | \--* LCL_VAR int V79 tmp70 d:5 $40 N007 ( 14, 10) [001077] -A---------- * COMMA void $40 N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V80 tmp71 u:3 (last use) $VN.Null N003 ( 7, 5) [001073] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 $VN.Null finish(BB12). Succ(BB14). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 79/3 to $3c2 {PhiDef($4f, $3, $304)}. In SSA definition, incoming phi args all same, set VN of local 78/3 to $VN.Null. Building phi application: $49 = SSA# 7. Building phi application: $4f = SSA# 33. Building phi application: $24e = phi($4f, $49). The SSA definition for ByrefExposed (#9) at start of BB14 is $24f {PhiMemoryDef($185, $24e)} Building phi application: $50 = SSA# 8. Building phi application: $51 = SSA# 34. Building phi application: $250 = phi($51, $50). The SSA definition for GcHeap (#10) at start of BB14 is $251 {PhiMemoryDef($185, $250)} ***** BB14, stmt 41 (before) N004 ( 3, 2) [001125] -------N---- /--* LCL_VAR int V79 tmp70 u:3 (last use) N006 ( 7, 5) [001126] -A------R--- /--* ASG int N005 ( 3, 2) [001124] D------N---- | \--* LCL_VAR int V64 tmp55 d:3 N007 ( 14, 10) [001127] -A---------- * COMMA void N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 u:3 (last use) N003 ( 7, 5) [001123] -A------R--- \--* ASG byref N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 N001 [001122] LCL_VAR V78 tmp69 u:3 (last use) => $VN.Null N002 [001121] LCL_VAR V63 tmp54 d:3 => $VN.Null N003 [001123] ASG => $VN.Null N004 [001125] LCL_VAR V79 tmp70 u:3 (last use) => $3c2 {PhiDef($4f, $3, $304)} N005 [001124] LCL_VAR V64 tmp55 d:3 => $3c2 {PhiDef($4f, $3, $304)} N006 [001126] ASG => $3c2 {PhiDef($4f, $3, $304)} N007 [001127] COMMA => $3c2 {PhiDef($4f, $3, $304)} ***** BB14, stmt 41 (after) N004 ( 3, 2) [001125] -------N---- /--* LCL_VAR int V79 tmp70 u:3 (last use) $3c2 N006 ( 7, 5) [001126] -A------R--- /--* ASG int $3c2 N005 ( 3, 2) [001124] D------N---- | \--* LCL_VAR int V64 tmp55 d:3 $3c2 N007 ( 14, 10) [001127] -A---------- * COMMA void $3c2 N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V78 tmp69 u:3 (last use) $VN.Null N003 ( 7, 5) [001123] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 $VN.Null --------- ***** BB14, stmt 42 (before) N004 ( 3, 2) [001132] -------N---- /--* LCL_VAR int V64 tmp55 u:3 N006 ( 7, 5) [001133] -A------R--- /--* ASG int N005 ( 3, 2) [001131] D------N---- | \--* LCL_VAR int V84 tmp75 d:3 N007 ( 14, 10) [001134] -A---------- * COMMA void N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 N003 ( 7, 5) [001130] -A------R--- \--* ASG byref N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 N001 [001129] LCL_VAR V63 tmp54 u:3 => $VN.Null N002 [001128] LCL_VAR V83 tmp74 d:3 => $VN.Null N003 [001130] ASG => $VN.Null N004 [001132] LCL_VAR V64 tmp55 u:3 => $3c2 {PhiDef($4f, $3, $304)} N005 [001131] LCL_VAR V84 tmp75 d:3 => $3c2 {PhiDef($4f, $3, $304)} N006 [001133] ASG => $3c2 {PhiDef($4f, $3, $304)} N007 [001134] COMMA => $3c2 {PhiDef($4f, $3, $304)} ***** BB14, stmt 42 (after) N004 ( 3, 2) [001132] -------N---- /--* LCL_VAR int V64 tmp55 u:3 $3c2 N006 ( 7, 5) [001133] -A------R--- /--* ASG int $3c2 N005 ( 3, 2) [001131] D------N---- | \--* LCL_VAR int V84 tmp75 d:3 $3c2 N007 ( 14, 10) [001134] -A---------- * COMMA void $3c2 N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 $VN.Null N003 ( 7, 5) [001130] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 $VN.Null --------- ***** BB14, stmt 43 (before) N010 ( 4, 4) [001146] x----------- /--* IND int N008 ( 1, 1) [001144] ------------ | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001145] -------N---- | \--* ADD byref N007 ( 1, 1) [001143] ------------ | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001147] -A------R--- /--* ASG int N011 ( 3, 2) [001142] D------N---- | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- * COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 N001 [001137] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [001138] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N003 [001139] ADD => $400 {ADD($80, $282)} N004 [001140] IND => N005 [001136] LCL_VAR V85 tmp76 d:3 => N006 [001141] ASG => N007 [001143] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N008 [001144] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N009 [001145] ADD => $401 {ADD($80, $281)} N010 [001146] IND => N011 [001142] LCL_VAR V86 tmp77 d:3 => N012 [001147] ASG => N013 [001148] COMMA => ***** BB14, stmt 43 (after) N010 ( 4, 4) [001146] x----------- /--* IND int N008 ( 1, 1) [001144] ------------ | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001145] -------N---- | \--* ADD byref $401 N007 ( 1, 1) [001143] ------------ | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001147] -A------R--- /--* ASG int N011 ( 3, 2) [001142] D------N---- | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- * COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 --------- ***** BB14, stmt 44 (before) N002 ( 3, 2) [000640] ------------ /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ /--* NE int N001 ( 3, 2) [000542] ------------ | \--* LCL_VAR int V84 tmp75 u:3 N005 ( 14, 8) [000548] -A------R--- * ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 N001 [000542] LCL_VAR V84 tmp75 u:3 => $3c2 {PhiDef($4f, $3, $304)} N002 [000640] LCL_VAR V86 tmp77 u:3 => N003 [000544] NE => N004 [000547] LCL_VAR V35 tmp26 d:3 => N005 [000548] ASG => ***** BB14, stmt 44 (after) N002 ( 3, 2) [000640] ------------ /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ /--* NE int N001 ( 3, 2) [000542] ------------ | \--* LCL_VAR int V84 tmp75 u:3 $3c2 N005 ( 14, 8) [000548] -A------R--- * ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 --------- ***** BB14, stmt 45 (before) N004 ( 7, 6) [000553] ------------ * JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) N001 [000550] LCL_VAR V35 tmp26 u:3 (last use) => N002 [000551] CNS_INT 0 => $40 {IntCns 0} N003 [000552] EQ => ***** BB14, stmt 45 (after) N004 ( 7, 6) [000553] ------------ * JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) finish(BB14). Succ(BB15). Not yet completed. All preds complete, adding to allDone. Succ(BB16). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#9) at start of BB16 is $24f {PhiMemoryDef($185, $24e)} The SSA definition for GcHeap (#10) at start of BB16 is $251 {PhiMemoryDef($185, $250)} ***** BB16, stmt 49 (before) N002 ( 1, 1) [000561] ------------ /--* CNS_INT int 0 N003 ( 8, 4) [000562] ------------ /--* EQ int N001 ( 3, 2) [000653] ------------ | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- * ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 N001 [000653] LCL_VAR V86 tmp77 u:3 => N002 [000561] CNS_INT 0 => $40 {IntCns 0} N003 [000562] EQ => N004 [000563] LCL_VAR V36 tmp27 d:3 => N005 [000564] ASG => ***** BB16, stmt 49 (after) N002 ( 1, 1) [000561] ------------ /--* CNS_INT int 0 $40 N003 ( 8, 4) [000562] ------------ /--* EQ int N001 ( 3, 2) [000653] ------------ | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- * ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 --------- ***** BB16, stmt 50 (before) N004 ( 7, 6) [000569] ------------ * JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) N001 [000566] LCL_VAR V36 tmp27 u:3 (last use) => N002 [000567] CNS_INT 0 => $40 {IntCns 0} N003 [000568] EQ => ***** BB16, stmt 50 (after) N004 ( 7, 6) [000569] ------------ * JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) finish(BB16). Succ(BB17). Not yet completed. All preds complete, adding to allDone. Succ(BB18). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#9) at start of BB18 is $24f {PhiMemoryDef($185, $24e)} The SSA definition for GcHeap (#10) at start of BB18 is $251 {PhiMemoryDef($185, $250)} ***** BB18, stmt 52 (before) N046 ( 1, 1) [000581] ------------ /--* CNS_INT int 0 N047 ( 85, 57) [000582] -ACXG------- /--* EQ int N045 ( 80, 55) [000574] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001172] -------N---- | | /--* LCL_VAR int V84 tmp75 u:3 (last use) N017 ( 10, 8) [001173] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001171] *------N---- | | | \--* IND int N013 ( 1, 1) [001169] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001170] -------N---- | | | \--* ADD byref N012 ( 3, 2) [001168] ------------ | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | +--* COMMA void N009 ( 3, 2) [001165] -------N---- | | | /--* LCL_VAR byref V83 tmp74 u:3 (last use) N010 ( 10, 7) [001166] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001164] *------N---- | | | | \--* IND byref N006 ( 1, 1) [001162] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001163] -------N---- | | | | \--* ADD byref N005 ( 3, 2) [001161] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 N011 ( 17, 13) [001167] -A---------- | | \--* COMMA void N002 ( 3, 3) [001157] L----------- | | | /--* ADDR byref N001 ( 3, 2) [001158] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001160] -A------R--- | | \--* ASG byref N003 ( 3, 2) [001159] D------N---- | | \--* LCL_VAR byref V101 tmp92 d:3 N034 ( 3, 2) [001193] -------N---- | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001192] *------N---- | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001191] -------N---- | | | \--* ADD byref N030 ( 3, 2) [001189] ------------ | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | +--* COMMA void N027 ( 3, 2) [001186] -------N---- | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001185] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001184] -------N---- | | | | \--* ADD byref N023 ( 3, 2) [001182] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 N029 ( 17, 13) [001188] -A---------- | | \--* COMMA void N020 ( 3, 3) [001178] L----------- | | | /--* ADDR byref N019 ( 3, 2) [001179] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001181] -A------R--- | | \--* ASG byref N021 ( 3, 2) [001180] D------N---- | | \--* LCL_VAR byref V102 tmp93 d:3 N040 ( 3, 3) [001197] L----------- arg0 in rcx | +--* ADDR byref N039 ( 3, 2) [001196] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001200] L----------- arg1 in rdx | \--* ADDR byref N041 ( 3, 2) [001199] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000584] -ACXG---R--- * ASG bool N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 N001 [001158] LCL_VAR V97 tmp88 => $484 {ByrefExposedLoad($4b, $402, $24f)} N002 [001157] ADDR => $2da {2da} N003 [001159] LCL_VAR V101 tmp92 d:3 => $2da {2da} N004 [001160] ASG => $2da {2da} N005 [001161] LCL_VAR V101 tmp92 u:3 => $2da {2da} N006 [001162] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N007 [001163] ADD => $408 {ADD($282, $2da)} N009 [001165] LCL_VAR V83 tmp74 u:3 (last use) => $VN.Null fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001166] to VN: $209. N010 [001166] ASG => $VN.Void N011 [001167] COMMA => $VN.Void N012 [001168] LCL_VAR V101 tmp92 u:3 (last use) => $2da {2da} N013 [001169] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N014 [001170] ADD => $409 {ADD($281, $2da)} N016 [001172] LCL_VAR V84 tmp75 u:3 (last use) => $3c2 {PhiDef($4f, $3, $304)} fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001173] to VN: $20a. N017 [001173] ASG => $VN.Void N018 [001174] COMMA => $VN.Void N019 [001179] LCL_VAR V99 tmp90 => $485 {ByrefExposedLoad($4b, $405, $109)} N020 [001178] ADDR => $2dc {2dc} N021 [001180] LCL_VAR V102 tmp93 d:3 => $2dc {2dc} N022 [001181] ASG => $2dc {2dc} N023 [001182] LCL_VAR V102 tmp93 u:3 => $2dc {2dc} N024 [001183] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N025 [001184] ADD => $40a {ADD($282, $2dc)} N027 [001186] LCL_VAR V85 tmp76 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001187] to VN: $20b. N028 [001187] ASG => $VN.Void N029 [001188] COMMA => $VN.Void N030 [001189] LCL_VAR V102 tmp93 u:3 (last use) => $2dc {2dc} N031 [001190] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N032 [001191] ADD => $40b {ADD($281, $2dc)} N034 [001193] LCL_VAR V86 tmp77 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001194] to VN: $20c. N035 [001194] ASG => $VN.Void N036 [001195] COMMA => $VN.Void N037 [000577] LIST => $383 {LIST($3, $0)} N038 [000580] LIST => $384 {LIST($3, $383)} N039 [001196] LCL_VAR V97 tmp88 => $486 {ByrefExposedLoad($4b, $402, $10b)} N040 [001197] ADDR => $2de {2de} N041 [001199] LCL_VAR V99 tmp90 => $487 {ByrefExposedLoad($4b, $405, $10b)} N042 [001200] ADDR => $2df {2df} N043 [001201] LIST => $38a {LIST($2df, $0)} N044 [001198] LIST => $38b {LIST($2de, $38a)} fgCurMemoryVN[GcHeap] assigned by CALL at [000574] to VN: $20d. N045 [000574] CALL => $1e0 {1e0} N046 [000581] CNS_INT 0 => $40 {IntCns 0} N047 [000582] EQ => $31e {EQ($1e0, $40)} N048 [000583] LCL_VAR V37 tmp28 d:4 => $31e {EQ($1e0, $40)} N049 [000584] ASG => $31e {EQ($1e0, $40)} ***** BB18, stmt 52 (after) N046 ( 1, 1) [000581] ------------ /--* CNS_INT int 0 $40 N047 ( 85, 57) [000582] -ACXG------- /--* EQ int $31e N045 ( 80, 55) [000574] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N016 ( 3, 2) [001172] -------N---- | | /--* LCL_VAR int V84 tmp75 u:3 (last use) $3c2 N017 ( 10, 8) [001173] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001171] *------N---- | | | \--* IND int $3c2 N013 ( 1, 1) [001169] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001170] -------N---- | | | \--* ADD byref $409 N012 ( 3, 2) [001168] ------------ | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) $2da N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | +--* COMMA void $VN.Void N009 ( 3, 2) [001165] -------N---- | | | /--* LCL_VAR byref V83 tmp74 u:3 (last use) $VN.Null N010 ( 10, 7) [001166] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001164] *------N---- | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001162] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001163] -------N---- | | | | \--* ADD byref $408 N005 ( 3, 2) [001161] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 $2da N011 ( 17, 13) [001167] -A---------- | | \--* COMMA void $VN.Void N002 ( 3, 3) [001157] L----------- | | | /--* ADDR byref $2da N001 ( 3, 2) [001158] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 $484 N004 ( 7, 6) [001160] -A------R--- | | \--* ASG byref $2da N003 ( 3, 2) [001159] D------N---- | | \--* LCL_VAR byref V101 tmp92 d:3 $2da N034 ( 3, 2) [001193] -------N---- | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001192] *------N---- | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001191] -------N---- | | | \--* ADD byref $40b N030 ( 3, 2) [001189] ------------ | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N027 ( 3, 2) [001186] -------N---- | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001185] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001184] -------N---- | | | | \--* ADD byref $40a N023 ( 3, 2) [001182] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 $2dc N029 ( 17, 13) [001188] -A---------- | | \--* COMMA void $VN.Void N020 ( 3, 3) [001178] L----------- | | | /--* ADDR byref $2dc N019 ( 3, 2) [001179] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 $485 N022 ( 7, 6) [001181] -A------R--- | | \--* ASG byref $2dc N021 ( 3, 2) [001180] D------N---- | | \--* LCL_VAR byref V102 tmp93 d:3 $2dc N040 ( 3, 3) [001197] L----------- arg0 in rcx | +--* ADDR byref $2de N039 ( 3, 2) [001196] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 $486 N042 ( 3, 3) [001200] L----------- arg1 in rdx | \--* ADDR byref $2df N041 ( 3, 2) [001199] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 $487 N049 ( 89, 60) [000584] -ACXG---R--- * ASG bool $31e N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 $31e finish(BB18). Succ(BB19). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#9) at start of BB17 is $24f {PhiMemoryDef($185, $24e)} The SSA definition for GcHeap (#10) at start of BB17 is $251 {PhiMemoryDef($185, $250)} ***** BB17, stmt 51 (before) N001 ( 1, 1) [000590] ------------ /--* CNS_INT int 1 N003 ( 5, 4) [000592] -A------R--- * ASG bool N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 N001 [000590] CNS_INT 1 => $41 {IntCns 1} N002 [000591] LCL_VAR V37 tmp28 d:3 => $41 {IntCns 1} N003 [000592] ASG => $41 {IntCns 1} ***** BB17, stmt 51 (after) N001 ( 1, 1) [000590] ------------ /--* CNS_INT int 1 $41 N003 ( 5, 4) [000592] -A------R--- * ASG bool $41 N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 $41 finish(BB17). Succ(BB19). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#9) at start of BB15 is $24f {PhiMemoryDef($185, $24e)} The SSA definition for GcHeap (#10) at start of BB15 is $251 {PhiMemoryDef($185, $250)} ***** BB15, stmt 48 (before) N001 ( 1, 1) [000595] ------------ /--* CNS_INT int 0 N003 ( 5, 4) [000597] -A------R--- * ASG bool N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 N001 [000595] CNS_INT 0 => $40 {IntCns 0} N002 [000596] LCL_VAR V37 tmp28 d:5 => $40 {IntCns 0} N003 [000597] ASG => $40 {IntCns 0} ***** BB15, stmt 48 (after) N001 ( 1, 1) [000595] ------------ /--* CNS_INT int 0 $40 N003 ( 5, 4) [000597] -A------R--- * ASG bool $40 N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 $40 finish(BB15). Succ(BB19). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 37/6 to $501 {PhiDef($25, $6, $4c0)}. Building phi application: $52 = SSA# 11. Building phi application: $53 = SSA# 9. Building phi application: $252 = phi($53, $52). The SSA definition for ByrefExposed (#13) at start of BB19 is $253 {PhiMemoryDef($186, $252)} Building phi application: $54 = SSA# 12. Building phi application: $55 = SSA# 10. Building phi application: $254 = phi($55, $54). The SSA definition for GcHeap (#14) at start of BB19 is $255 {PhiMemoryDef($186, $254)} ***** BB19, stmt 53 (before) N004 ( 7, 6) [000058] ------------ * JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000057] J------N---- \--* EQ int N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) N001 [000055] LCL_VAR V37 tmp28 u:6 (last use) => $501 {PhiDef($25, $6, $4c0)} N002 [000056] CNS_INT 0 => $40 {IntCns 0} N003 [000057] EQ => $31f {EQ($501, $40)} ***** BB19, stmt 53 (after) N004 ( 7, 6) [000058] ------------ * JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000057] J------N---- \--* EQ int $31f N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) $501 finish(BB19). Succ(BB20). Not yet completed. All preds complete, adding to allDone. Succ(BB21). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#13) at start of BB21 is $253 {PhiMemoryDef($186, $252)} The SSA definition for GcHeap (#14) at start of BB21 is $255 {PhiMemoryDef($186, $254)} ***** BB21, stmt 57 (before) N015 ( 38, 21) [000062] SACXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 u:3 (last use) N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 N001 [000066] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [001205] LCL_VAR V103 tmp94 d:3 => $80 {InitVal($40)} N003 [001206] ASG => $80 {InitVal($40)} N004 [000061] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N005 [000064] IND => fgCurMemoryVN[ByrefExposed] assigned by COPYBLK - address-exposed local at [001204] to VN: $10d. N007 [001204] ASG => $VN.Void N008 [000065] LIST => $383 {LIST($3, $0)} N009 [000068] LIST => $38c {LIST($80, $383)} N010 [001207] LCL_VAR V103 tmp94 u:3 (last use) => $80 {InitVal($40)} N011 [001209] LCL_VAR V97 tmp88 => $489 {ByrefExposedLoad($4b, $402, $10d)} N012 [001210] ADDR => $2e1 {2e1} N013 [001211] LIST => $38d {LIST($2e1, $0)} N014 [001208] LIST => $38e {LIST($80, $38d)} fgCurMemoryVN[GcHeap] assigned by CALL at [000062] to VN: $20e. N015 [000062] CALL => $VN.Void ***** BB21, stmt 57 (after) N015 ( 38, 21) [000062] SACXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 $80 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref $80 N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 $80 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) $VN.Void N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V103 tmp94 u:3 (last use) $80 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref $2e1 N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 $489 --------- ***** BB21, stmt 58 (before) N004 ( 3, 2) [001216] -------N---- /--* LCL_VAR int V62 tmp53 u:3 (last use) N006 ( 7, 5) [001217] -A------R--- /--* ASG int N005 ( 3, 2) [001215] D------N---- | \--* LCL_VAR int V88 tmp79 d:3 N007 ( 14, 10) [001218] -A---------- * COMMA void N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) N003 ( 7, 5) [001214] -A------R--- \--* ASG byref N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 N001 [001213] LCL_VAR V61 tmp52 u:3 (last use) => $VN.Null N002 [001212] LCL_VAR V87 tmp78 d:3 => $VN.Null N003 [001214] ASG => $VN.Null N004 [001216] LCL_VAR V62 tmp53 u:3 (last use) => $3c0 {PhiDef($44, $3, $304)} N005 [001215] LCL_VAR V88 tmp79 d:3 => $3c0 {PhiDef($44, $3, $304)} N006 [001217] ASG => $3c0 {PhiDef($44, $3, $304)} N007 [001218] COMMA => $3c0 {PhiDef($44, $3, $304)} ***** BB21, stmt 58 (after) N004 ( 3, 2) [001216] -------N---- /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N006 ( 7, 5) [001217] -A------R--- /--* ASG int $3c0 N005 ( 3, 2) [001215] D------N---- | \--* LCL_VAR int V88 tmp79 d:3 $3c0 N007 ( 14, 10) [001218] -A---------- * COMMA void $3c0 N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001214] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 $VN.Null --------- ***** BB21, stmt 59 (before) N010 ( 4, 4) [001230] x----------- /--* IND int N008 ( 1, 1) [001228] ------------ | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001229] -------N---- | \--* ADD byref N007 ( 1, 1) [001227] ------------ | \--* LCL_VAR byref V00 arg0 u:2 N012 ( 8, 7) [001231] -A------R--- /--* ASG int N011 ( 3, 2) [001226] D------N---- | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- * COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 N001 [001221] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [001222] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N003 [001223] ADD => $400 {ADD($80, $282)} N004 [001224] IND => N005 [001220] LCL_VAR V89 tmp80 d:3 => N006 [001225] ASG => N007 [001227] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N008 [001228] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N009 [001229] ADD => $401 {ADD($80, $281)} N010 [001230] IND => N011 [001226] LCL_VAR V90 tmp81 d:3 => N012 [001231] ASG => N013 [001232] COMMA => ***** BB21, stmt 59 (after) N010 ( 4, 4) [001230] x----------- /--* IND int N008 ( 1, 1) [001228] ------------ | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001229] -------N---- | \--* ADD byref $401 N007 ( 1, 1) [001227] ------------ | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001231] -A------R--- /--* ASG int N011 ( 3, 2) [001226] D------N---- | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- * COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 --------- ***** BB21, stmt 60 (before) N002 ( 3, 2) [000770] ------------ /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ /--* NE int N001 ( 3, 2) [000672] ------------ | \--* LCL_VAR int V88 tmp79 u:3 N005 ( 14, 8) [000678] -A------R--- * ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 N001 [000672] LCL_VAR V88 tmp79 u:3 => $3c0 {PhiDef($44, $3, $304)} N002 [000770] LCL_VAR V90 tmp81 u:3 => N003 [000674] NE => N004 [000677] LCL_VAR V44 tmp35 d:3 => N005 [000678] ASG => ***** BB21, stmt 60 (after) N002 ( 3, 2) [000770] ------------ /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ /--* NE int N001 ( 3, 2) [000672] ------------ | \--* LCL_VAR int V88 tmp79 u:3 $3c0 N005 ( 14, 8) [000678] -A------R--- * ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 --------- ***** BB21, stmt 61 (before) N004 ( 7, 6) [000683] ------------ * JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) N001 [000680] LCL_VAR V44 tmp35 u:3 (last use) => N002 [000681] CNS_INT 0 => $40 {IntCns 0} N003 [000682] EQ => ***** BB21, stmt 61 (after) N004 ( 7, 6) [000683] ------------ * JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) finish(BB21). Succ(BB22). Not yet completed. All preds complete, adding to allDone. Succ(BB23). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#15) at start of BB23 is $10e {10e} The SSA definition for GcHeap (#16) at start of BB23 is $20e {20e} ***** BB23, stmt 63 (before) N002 ( 1, 1) [000691] ------------ /--* CNS_INT int 0 N003 ( 8, 4) [000692] ------------ /--* EQ int N001 ( 3, 2) [000783] ------------ | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- * ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 N001 [000783] LCL_VAR V90 tmp81 u:3 => N002 [000691] CNS_INT 0 => $40 {IntCns 0} N003 [000692] EQ => N004 [000693] LCL_VAR V45 tmp36 d:3 => N005 [000694] ASG => ***** BB23, stmt 63 (after) N002 ( 1, 1) [000691] ------------ /--* CNS_INT int 0 $40 N003 ( 8, 4) [000692] ------------ /--* EQ int N001 ( 3, 2) [000783] ------------ | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- * ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 --------- ***** BB23, stmt 64 (before) N004 ( 7, 6) [000699] ------------ * JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) N001 [000696] LCL_VAR V45 tmp36 u:3 (last use) => N002 [000697] CNS_INT 0 => $40 {IntCns 0} N003 [000698] EQ => ***** BB23, stmt 64 (after) N004 ( 7, 6) [000699] ------------ * JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) finish(BB23). Succ(BB24). Not yet completed. All preds complete, adding to allDone. Succ(BB25). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#15) at start of BB25 is $10e {10e} The SSA definition for GcHeap (#16) at start of BB25 is $20e {20e} ***** BB25, stmt 66 (before) N046 ( 1, 1) [000711] ------------ /--* CNS_INT int 0 N047 ( 85, 57) [000712] -ACXG------- /--* EQ int N045 ( 80, 55) [000704] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001256] -------N---- | | /--* LCL_VAR int V88 tmp79 u:3 (last use) N017 ( 10, 8) [001257] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001255] *------N---- | | | \--* IND int N013 ( 1, 1) [001253] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001254] -------N---- | | | \--* ADD byref N012 ( 3, 2) [001252] ------------ | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | +--* COMMA void N009 ( 3, 2) [001249] -------N---- | | | /--* LCL_VAR byref V87 tmp78 u:3 (last use) N010 ( 10, 7) [001250] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001248] *------N---- | | | | \--* IND byref N006 ( 1, 1) [001246] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001247] -------N---- | | | | \--* ADD byref N005 ( 3, 2) [001245] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 N011 ( 17, 13) [001251] -A---------- | | \--* COMMA void N002 ( 3, 3) [001241] L----------- | | | /--* ADDR byref N001 ( 3, 2) [001242] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001244] -A------R--- | | \--* ASG byref N003 ( 3, 2) [001243] D------N---- | | \--* LCL_VAR byref V104 tmp95 d:3 N034 ( 3, 2) [001277] -------N---- | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001276] *------N---- | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001275] -------N---- | | | \--* ADD byref N030 ( 3, 2) [001273] ------------ | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | +--* COMMA void N027 ( 3, 2) [001270] -------N---- | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001269] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001268] -------N---- | | | | \--* ADD byref N023 ( 3, 2) [001266] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 N029 ( 17, 13) [001272] -A---------- | | \--* COMMA void N020 ( 3, 3) [001262] L----------- | | | /--* ADDR byref N019 ( 3, 2) [001263] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001265] -A------R--- | | \--* ASG byref N021 ( 3, 2) [001264] D------N---- | | \--* LCL_VAR byref V105 tmp96 d:3 N040 ( 3, 3) [001281] L----------- arg0 in rcx | +--* ADDR byref N039 ( 3, 2) [001280] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001284] L----------- arg1 in rdx | \--* ADDR byref N041 ( 3, 2) [001283] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000714] -ACXG---R--- * ASG bool N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 N001 [001242] LCL_VAR V97 tmp88 => $48a {ByrefExposedLoad($4b, $402, $10e)} N002 [001241] ADDR => $2e5 {2e5} N003 [001243] LCL_VAR V104 tmp95 d:3 => $2e5 {2e5} N004 [001244] ASG => $2e5 {2e5} N005 [001245] LCL_VAR V104 tmp95 u:3 => $2e5 {2e5} N006 [001246] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N007 [001247] ADD => $40c {ADD($282, $2e5)} N009 [001249] LCL_VAR V87 tmp78 u:3 (last use) => $VN.Null fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001250] to VN: $20f. N010 [001250] ASG => $VN.Void N011 [001251] COMMA => $VN.Void N012 [001252] LCL_VAR V104 tmp95 u:3 (last use) => $2e5 {2e5} N013 [001253] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N014 [001254] ADD => $40d {ADD($281, $2e5)} N016 [001256] LCL_VAR V88 tmp79 u:3 (last use) => $3c0 {PhiDef($44, $3, $304)} fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001257] to VN: $210. N017 [001257] ASG => $VN.Void N018 [001258] COMMA => $VN.Void N019 [001263] LCL_VAR V99 tmp90 => $48b {ByrefExposedLoad($4b, $405, $110)} N020 [001262] ADDR => $2e7 {2e7} N021 [001264] LCL_VAR V105 tmp96 d:3 => $2e7 {2e7} N022 [001265] ASG => $2e7 {2e7} N023 [001266] LCL_VAR V105 tmp96 u:3 => $2e7 {2e7} N024 [001267] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N025 [001268] ADD => $40e {ADD($282, $2e7)} N027 [001270] LCL_VAR V89 tmp80 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001271] to VN: $211. N028 [001271] ASG => $VN.Void N029 [001272] COMMA => $VN.Void N030 [001273] LCL_VAR V105 tmp96 u:3 (last use) => $2e7 {2e7} N031 [001274] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N032 [001275] ADD => $40f {ADD($281, $2e7)} N034 [001277] LCL_VAR V90 tmp81 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001278] to VN: $212. N035 [001278] ASG => $VN.Void N036 [001279] COMMA => $VN.Void N037 [000707] LIST => $383 {LIST($3, $0)} N038 [000710] LIST => $384 {LIST($3, $383)} N039 [001280] LCL_VAR V97 tmp88 => $48c {ByrefExposedLoad($4b, $402, $112)} N040 [001281] ADDR => $2e9 {2e9} N041 [001283] LCL_VAR V99 tmp90 => $48d {ByrefExposedLoad($4b, $405, $112)} N042 [001284] ADDR => $2ea {2ea} N043 [001285] LIST => $38f {LIST($2ea, $0)} N044 [001282] LIST => $390 {LIST($2e9, $38f)} fgCurMemoryVN[GcHeap] assigned by CALL at [000704] to VN: $213. N045 [000704] CALL => $1e9 {1e9} N046 [000711] CNS_INT 0 => $40 {IntCns 0} N047 [000712] EQ => $328 {EQ($1e9, $40)} N048 [000713] LCL_VAR V46 tmp37 d:4 => $328 {EQ($1e9, $40)} N049 [000714] ASG => $328 {EQ($1e9, $40)} ***** BB25, stmt 66 (after) N046 ( 1, 1) [000711] ------------ /--* CNS_INT int 0 $40 N047 ( 85, 57) [000712] -ACXG------- /--* EQ int $328 N045 ( 80, 55) [000704] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N016 ( 3, 2) [001256] -------N---- | | /--* LCL_VAR int V88 tmp79 u:3 (last use) $3c0 N017 ( 10, 8) [001257] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001255] *------N---- | | | \--* IND int $3c0 N013 ( 1, 1) [001253] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001254] -------N---- | | | \--* ADD byref $40d N012 ( 3, 2) [001252] ------------ | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | +--* COMMA void $VN.Void N009 ( 3, 2) [001249] -------N---- | | | /--* LCL_VAR byref V87 tmp78 u:3 (last use) $VN.Null N010 ( 10, 7) [001250] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001248] *------N---- | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001246] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001247] -------N---- | | | | \--* ADD byref $40c N005 ( 3, 2) [001245] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 $2e5 N011 ( 17, 13) [001251] -A---------- | | \--* COMMA void $VN.Void N002 ( 3, 3) [001241] L----------- | | | /--* ADDR byref $2e5 N001 ( 3, 2) [001242] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48a N004 ( 7, 6) [001244] -A------R--- | | \--* ASG byref $2e5 N003 ( 3, 2) [001243] D------N---- | | \--* LCL_VAR byref V104 tmp95 d:3 $2e5 N034 ( 3, 2) [001277] -------N---- | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001276] *------N---- | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001275] -------N---- | | | \--* ADD byref $40f N030 ( 3, 2) [001273] ------------ | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N027 ( 3, 2) [001270] -------N---- | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001269] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001268] -------N---- | | | | \--* ADD byref $40e N023 ( 3, 2) [001266] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 $2e7 N029 ( 17, 13) [001272] -A---------- | | \--* COMMA void $VN.Void N020 ( 3, 3) [001262] L----------- | | | /--* ADDR byref $2e7 N019 ( 3, 2) [001263] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48b N022 ( 7, 6) [001265] -A------R--- | | \--* ASG byref $2e7 N021 ( 3, 2) [001264] D------N---- | | \--* LCL_VAR byref V105 tmp96 d:3 $2e7 N040 ( 3, 3) [001281] L----------- arg0 in rcx | +--* ADDR byref $2e9 N039 ( 3, 2) [001280] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 $48c N042 ( 3, 3) [001284] L----------- arg1 in rdx | \--* ADDR byref $2ea N041 ( 3, 2) [001283] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 $48d N049 ( 89, 60) [000714] -ACXG---R--- * ASG bool $328 N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 $328 finish(BB25). Succ(BB26). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#15) at start of BB24 is $10e {10e} The SSA definition for GcHeap (#16) at start of BB24 is $20e {20e} ***** BB24, stmt 65 (before) N001 ( 1, 1) [000720] ------------ /--* CNS_INT int 1 N003 ( 5, 4) [000722] -A------R--- * ASG bool N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 N001 [000720] CNS_INT 1 => $41 {IntCns 1} N002 [000721] LCL_VAR V46 tmp37 d:5 => $41 {IntCns 1} N003 [000722] ASG => $41 {IntCns 1} ***** BB24, stmt 65 (after) N001 ( 1, 1) [000720] ------------ /--* CNS_INT int 1 $41 N003 ( 5, 4) [000722] -A------R--- * ASG bool $41 N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 $41 finish(BB24). Succ(BB26). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#15) at start of BB22 is $10e {10e} The SSA definition for GcHeap (#16) at start of BB22 is $20e {20e} ***** BB22, stmt 62 (before) N001 ( 1, 1) [000725] ------------ /--* CNS_INT int 0 N003 ( 5, 4) [000727] -A------R--- * ASG bool N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 N001 [000725] CNS_INT 0 => $40 {IntCns 0} N002 [000726] LCL_VAR V46 tmp37 d:6 => $40 {IntCns 0} N003 [000727] ASG => $40 {IntCns 0} ***** BB22, stmt 62 (after) N001 ( 1, 1) [000725] ------------ /--* CNS_INT int 0 $40 N003 ( 5, 4) [000727] -A------R--- * ASG bool $40 N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 $40 finish(BB22). Succ(BB26). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 46/3 to $502 {PhiDef($2e, $3, $4c2)}. Building phi application: $4b = SSA# 15. Building phi application: $56 = SSA# 29. Building phi application: $256 = phi($56, $4b). The SSA definition for ByrefExposed (#17) at start of BB26 is $257 {PhiMemoryDef($187, $256)} Building phi application: $57 = SSA# 16. Building phi application: $58 = SSA# 30. Building phi application: $258 = phi($58, $57). The SSA definition for GcHeap (#18) at start of BB26 is $259 {PhiMemoryDef($187, $258)} ***** BB26, stmt 67 (before) N004 ( 7, 6) [000088] ------------ * JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000087] J------N---- \--* EQ int N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) N001 [000085] LCL_VAR V46 tmp37 u:3 (last use) => $502 {PhiDef($2e, $3, $4c2)} N002 [000086] CNS_INT 0 => $40 {IntCns 0} N003 [000087] EQ => $329 {EQ($502, $40)} ***** BB26, stmt 67 (after) N004 ( 7, 6) [000088] ------------ * JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000087] J------N---- \--* EQ int $329 N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) $502 finish(BB26). Succ(BB27). Not yet completed. All preds complete, adding to allDone. Succ(BB28). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#17) at start of BB28 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB28 is $259 {PhiMemoryDef($187, $258)} ***** BB28, stmt 71 (before) N004 ( 3, 2) [001291] -------N---- /--* LCL_VAR int V64 tmp55 u:3 (last use) N006 ( 7, 5) [001292] -A------R--- /--* ASG int N005 ( 3, 2) [001290] D------N---- | \--* LCL_VAR int V92 tmp83 d:3 N007 ( 14, 10) [001293] -A---------- * COMMA void N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) N003 ( 7, 5) [001289] -A------R--- \--* ASG byref N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 N001 [001288] LCL_VAR V63 tmp54 u:3 (last use) => $VN.Null N002 [001287] LCL_VAR V91 tmp82 d:3 => $VN.Null N003 [001289] ASG => $VN.Null N004 [001291] LCL_VAR V64 tmp55 u:3 (last use) => $3c2 {PhiDef($4f, $3, $304)} N005 [001290] LCL_VAR V92 tmp83 d:3 => $3c2 {PhiDef($4f, $3, $304)} N006 [001292] ASG => $3c2 {PhiDef($4f, $3, $304)} N007 [001293] COMMA => $3c2 {PhiDef($4f, $3, $304)} ***** BB28, stmt 71 (after) N004 ( 3, 2) [001291] -------N---- /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N006 ( 7, 5) [001292] -A------R--- /--* ASG int $3c2 N005 ( 3, 2) [001290] D------N---- | \--* LCL_VAR int V92 tmp83 d:3 $3c2 N007 ( 14, 10) [001293] -A---------- * COMMA void $3c2 N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001289] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 $VN.Null --------- ***** BB28, stmt 72 (before) N010 ( 4, 4) [001305] x----------- /--* IND int N008 ( 1, 1) [001303] ------------ | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [001304] -------N---- | \--* ADD byref N007 ( 1, 1) [001302] ------------ | \--* LCL_VAR byref V00 arg0 u:2 (last use) N012 ( 8, 7) [001306] -A------R--- /--* ASG int N011 ( 3, 2) [001301] D------N---- | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- * COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 N001 [001296] LCL_VAR V00 arg0 u:2 => $80 {InitVal($40)} N002 [001297] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N003 [001298] ADD => $400 {ADD($80, $282)} N004 [001299] IND => N005 [001295] LCL_VAR V93 tmp84 d:3 => N006 [001300] ASG => N007 [001302] LCL_VAR V00 arg0 u:2 (last use) => $80 {InitVal($40)} N008 [001303] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N009 [001304] ADD => $401 {ADD($80, $281)} N010 [001305] IND => N011 [001301] LCL_VAR V94 tmp85 d:3 => N012 [001306] ASG => N013 [001307] COMMA => ***** BB28, stmt 72 (after) N010 ( 4, 4) [001305] x----------- /--* IND int N008 ( 1, 1) [001303] ------------ | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001304] -------N---- | \--* ADD byref $401 N007 ( 1, 1) [001302] ------------ | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 8, 7) [001306] -A------R--- /--* ASG int N011 ( 3, 2) [001301] D------N---- | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- * COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 --------- ***** BB28, stmt 73 (before) N002 ( 3, 2) [000900] ------------ /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ /--* NE int N001 ( 3, 2) [000802] ------------ | \--* LCL_VAR int V92 tmp83 u:3 N005 ( 14, 8) [000808] -A------R--- * ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 N001 [000802] LCL_VAR V92 tmp83 u:3 => $3c2 {PhiDef($4f, $3, $304)} N002 [000900] LCL_VAR V94 tmp85 u:3 => N003 [000804] NE => N004 [000807] LCL_VAR V53 tmp44 d:3 => N005 [000808] ASG => ***** BB28, stmt 73 (after) N002 ( 3, 2) [000900] ------------ /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ /--* NE int N001 ( 3, 2) [000802] ------------ | \--* LCL_VAR int V92 tmp83 u:3 $3c2 N005 ( 14, 8) [000808] -A------R--- * ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 --------- ***** BB28, stmt 74 (before) N004 ( 7, 6) [000813] ------------ * JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) N001 [000810] LCL_VAR V53 tmp44 u:3 (last use) => N002 [000811] CNS_INT 0 => $40 {IntCns 0} N003 [000812] EQ => ***** BB28, stmt 74 (after) N004 ( 7, 6) [000813] ------------ * JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) finish(BB28). Succ(BB29). Not yet completed. All preds complete, adding to allDone. Succ(BB30). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#17) at start of BB30 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB30 is $259 {PhiMemoryDef($187, $258)} ***** BB30, stmt 76 (before) N002 ( 1, 1) [000821] ------------ /--* CNS_INT int 0 N003 ( 8, 4) [000822] ------------ /--* EQ int N001 ( 3, 2) [000913] ------------ | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- * ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 N001 [000913] LCL_VAR V94 tmp85 u:3 => N002 [000821] CNS_INT 0 => $40 {IntCns 0} N003 [000822] EQ => N004 [000823] LCL_VAR V54 tmp45 d:3 => N005 [000824] ASG => ***** BB30, stmt 76 (after) N002 ( 1, 1) [000821] ------------ /--* CNS_INT int 0 $40 N003 ( 8, 4) [000822] ------------ /--* EQ int N001 ( 3, 2) [000913] ------------ | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- * ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 --------- ***** BB30, stmt 77 (before) N004 ( 7, 6) [000829] ------------ * JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) N001 [000826] LCL_VAR V54 tmp45 u:3 (last use) => N002 [000827] CNS_INT 0 => $40 {IntCns 0} N003 [000828] EQ => ***** BB30, stmt 77 (after) N004 ( 7, 6) [000829] ------------ * JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) finish(BB30). Succ(BB31). Not yet completed. All preds complete, adding to allDone. Succ(BB32). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#17) at start of BB32 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB32 is $259 {PhiMemoryDef($187, $258)} ***** BB32, stmt 79 (before) N046 ( 1, 1) [000841] ------------ /--* CNS_INT int 0 N047 ( 85, 57) [000842] -ACXG------- /--* EQ int N045 ( 80, 55) [000834] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase N016 ( 3, 2) [001331] -------N---- | | /--* LCL_VAR int V92 tmp83 u:3 (last use) N017 ( 10, 8) [001332] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 N015 ( 6, 5) [001330] *------N---- | | | \--* IND int N013 ( 1, 1) [001328] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N014 ( 4, 3) [001329] -------N---- | | | \--* ADD byref N012 ( 3, 2) [001327] ------------ | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | +--* COMMA void N009 ( 3, 2) [001324] -------N---- | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) N010 ( 10, 7) [001325] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 N008 ( 6, 4) [001323] *------N---- | | | | \--* IND byref N006 ( 1, 1) [001321] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N007 ( 5, 4) [001322] -------N---- | | | | \--* ADD byref N005 ( 3, 2) [001320] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 N011 ( 17, 13) [001326] -A---------- | | \--* COMMA void N002 ( 3, 3) [001316] L----------- | | | /--* ADDR byref N001 ( 3, 2) [001317] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 N004 ( 7, 6) [001319] -A------R--- | | \--* ASG byref N003 ( 3, 2) [001318] D------N---- | | \--* LCL_VAR byref V106 tmp97 d:3 N034 ( 3, 2) [001352] -------N---- | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 N033 ( 6, 5) [001351] *------N---- | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] N032 ( 4, 3) [001350] -------N---- | | | \--* ADD byref N030 ( 3, 2) [001348] ------------ | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | +--* COMMA void N027 ( 3, 2) [001345] -------N---- | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 N026 ( 6, 4) [001344] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] N025 ( 5, 4) [001343] -------N---- | | | | \--* ADD byref N023 ( 3, 2) [001341] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 N029 ( 17, 13) [001347] -A---------- | | \--* COMMA void N020 ( 3, 3) [001337] L----------- | | | /--* ADDR byref N019 ( 3, 2) [001338] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 N022 ( 7, 6) [001340] -A------R--- | | \--* ASG byref N021 ( 3, 2) [001339] D------N---- | | \--* LCL_VAR byref V107 tmp98 d:3 N040 ( 3, 3) [001356] L----------- arg0 in rcx | +--* ADDR byref N039 ( 3, 2) [001355] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 N042 ( 3, 3) [001359] L----------- arg1 in rdx | \--* ADDR byref N041 ( 3, 2) [001358] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 N049 ( 89, 60) [000844] -ACXG---R--- * ASG bool N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 N001 [001317] LCL_VAR V97 tmp88 => $48e {ByrefExposedLoad($4b, $402, $257)} N002 [001316] ADDR => $2ee {2ee} N003 [001318] LCL_VAR V106 tmp97 d:3 => $2ee {2ee} N004 [001319] ASG => $2ee {2ee} N005 [001320] LCL_VAR V106 tmp97 u:3 => $2ee {2ee} N006 [001321] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N007 [001322] ADD => $410 {ADD($282, $2ee)} N009 [001324] LCL_VAR V91 tmp82 u:3 (last use) => $VN.Null fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001325] to VN: $214. N010 [001325] ASG => $VN.Void N011 [001326] COMMA => $VN.Void N012 [001327] LCL_VAR V106 tmp97 u:3 (last use) => $2ee {2ee} N013 [001328] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N014 [001329] ADD => $411 {ADD($281, $2ee)} N016 [001331] LCL_VAR V92 tmp83 u:3 (last use) => $3c2 {PhiDef($4f, $3, $304)} fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001332] to VN: $215. N017 [001332] ASG => $VN.Void N018 [001333] COMMA => $VN.Void N019 [001338] LCL_VAR V99 tmp90 => $48f {ByrefExposedLoad($4b, $405, $115)} N020 [001337] ADDR => $2f0 {2f0} N021 [001339] LCL_VAR V107 tmp98 d:3 => $2f0 {2f0} N022 [001340] ASG => $2f0 {2f0} N023 [001341] LCL_VAR V107 tmp98 u:3 => $2f0 {2f0} N024 [001342] CNS_INT 0 Fseq[_pointer] => $282 {LngCns: 0} N025 [001343] ADD => $412 {ADD($282, $2f0)} N027 [001345] LCL_VAR V93 tmp84 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001346] to VN: $216. N028 [001346] ASG => $VN.Void N029 [001347] COMMA => $VN.Void N030 [001348] LCL_VAR V107 tmp98 u:3 (last use) => $2f0 {2f0} N031 [001349] CNS_INT 8 Fseq[_length] => $281 {LngCns: 8} N032 [001350] ADD => $413 {ADD($281, $2f0)} N034 [001352] LCL_VAR V94 tmp85 u:3 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [001353] to VN: $217. N035 [001353] ASG => $VN.Void N036 [001354] COMMA => $VN.Void N037 [000837] LIST => $383 {LIST($3, $0)} N038 [000840] LIST => $384 {LIST($3, $383)} N039 [001355] LCL_VAR V97 tmp88 => $490 {ByrefExposedLoad($4b, $402, $117)} N040 [001356] ADDR => $2f2 {2f2} N041 [001358] LCL_VAR V99 tmp90 => $491 {ByrefExposedLoad($4b, $405, $117)} N042 [001359] ADDR => $2f3 {2f3} N043 [001360] LIST => $391 {LIST($2f3, $0)} N044 [001357] LIST => $392 {LIST($2f2, $391)} fgCurMemoryVN[GcHeap] assigned by CALL at [000834] to VN: $218. N045 [000834] CALL => $1f2 {1f2} N046 [000841] CNS_INT 0 => $40 {IntCns 0} N047 [000842] EQ => $332 {EQ($1f2, $40)} N048 [000843] LCL_VAR V55 tmp46 d:4 => $332 {EQ($1f2, $40)} N049 [000844] ASG => $332 {EQ($1f2, $40)} ***** BB32, stmt 79 (after) N046 ( 1, 1) [000841] ------------ /--* CNS_INT int 0 $40 N047 ( 85, 57) [000842] -ACXG------- /--* EQ int $332 N045 ( 80, 55) [000834] -ACXG------- | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N016 ( 3, 2) [001331] -------N---- | | /--* LCL_VAR int V92 tmp83 u:3 (last use) $3c2 N017 ( 10, 8) [001332] -A---------- | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001330] *------N---- | | | \--* IND int $3c2 N013 ( 1, 1) [001328] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001329] -------N---- | | | \--* ADD byref $411 N012 ( 3, 2) [001327] ------------ | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | +--* COMMA void $VN.Void N009 ( 3, 2) [001324] -------N---- | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null N010 ( 10, 7) [001325] -A---------- | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001323] *------N---- | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001321] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001322] -------N---- | | | | \--* ADD byref $410 N005 ( 3, 2) [001320] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 $2ee N011 ( 17, 13) [001326] -A---------- | | \--* COMMA void $VN.Void N002 ( 3, 3) [001316] L----------- | | | /--* ADDR byref $2ee N001 ( 3, 2) [001317] -------N---- | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48e N004 ( 7, 6) [001319] -A------R--- | | \--* ASG byref $2ee N003 ( 3, 2) [001318] D------N---- | | \--* LCL_VAR byref V106 tmp97 d:3 $2ee N034 ( 3, 2) [001352] -------N---- | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001351] *------N---- | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001350] -------N---- | | | \--* ADD byref $413 N030 ( 3, 2) [001348] ------------ | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | +--* COMMA void $VN.Void N027 ( 3, 2) [001345] -------N---- | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001344] *------N---- | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001343] -------N---- | | | | \--* ADD byref $412 N023 ( 3, 2) [001341] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 $2f0 N029 ( 17, 13) [001347] -A---------- | | \--* COMMA void $VN.Void N020 ( 3, 3) [001337] L----------- | | | /--* ADDR byref $2f0 N019 ( 3, 2) [001338] -------N---- | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48f N022 ( 7, 6) [001340] -A------R--- | | \--* ASG byref $2f0 N021 ( 3, 2) [001339] D------N---- | | \--* LCL_VAR byref V107 tmp98 d:3 $2f0 N040 ( 3, 3) [001356] L----------- arg0 in rcx | +--* ADDR byref $2f2 N039 ( 3, 2) [001355] -------N---- | | \--* LCL_VAR struct(AX) V97 tmp88 $490 N042 ( 3, 3) [001359] L----------- arg1 in rdx | \--* ADDR byref $2f3 N041 ( 3, 2) [001358] -------N---- | \--* LCL_VAR struct(AX) V99 tmp90 $491 N049 ( 89, 60) [000844] -ACXG---R--- * ASG bool $332 N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 $332 finish(BB32). Succ(BB33). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#17) at start of BB31 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB31 is $259 {PhiMemoryDef($187, $258)} ***** BB31, stmt 78 (before) N001 ( 1, 1) [000850] ------------ /--* CNS_INT int 1 N003 ( 5, 4) [000852] -A------R--- * ASG bool N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 N001 [000850] CNS_INT 1 => $41 {IntCns 1} N002 [000851] LCL_VAR V55 tmp46 d:5 => $41 {IntCns 1} N003 [000852] ASG => $41 {IntCns 1} ***** BB31, stmt 78 (after) N001 ( 1, 1) [000850] ------------ /--* CNS_INT int 1 $41 N003 ( 5, 4) [000852] -A------R--- * ASG bool $41 N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 $41 finish(BB31). Succ(BB33). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#17) at start of BB29 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB29 is $259 {PhiMemoryDef($187, $258)} ***** BB29, stmt 75 (before) N001 ( 1, 1) [000855] ------------ /--* CNS_INT int 0 N003 ( 5, 4) [000857] -A------R--- * ASG bool N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 N001 [000855] CNS_INT 0 => $40 {IntCns 0} N002 [000856] LCL_VAR V55 tmp46 d:6 => $40 {IntCns 0} N003 [000857] ASG => $40 {IntCns 0} ***** BB29, stmt 75 (after) N001 ( 1, 1) [000855] ------------ /--* CNS_INT int 0 $40 N003 ( 5, 4) [000857] -A------R--- * ASG bool $40 N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 $40 finish(BB29). Succ(BB33). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 55/3 to $503 {PhiDef($37, $3, $4c2)}. Building phi application: $59 = SSA# 17. Building phi application: $5a = SSA# 25. Building phi application: $25a = phi($5a, $59). The SSA definition for ByrefExposed (#19) at start of BB33 is $25b {PhiMemoryDef($188, $25a)} Building phi application: $5b = SSA# 18. Building phi application: $5c = SSA# 26. Building phi application: $25c = phi($5c, $5b). The SSA definition for GcHeap (#20) at start of BB33 is $25d {PhiMemoryDef($188, $25c)} ***** BB33, stmt 80 (before) N004 ( 7, 6) [000109] ------------ * JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000108] J------N---- \--* EQ int N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) N001 [000106] LCL_VAR V55 tmp46 u:3 (last use) => $503 {PhiDef($37, $3, $4c2)} N002 [000107] CNS_INT 0 => $40 {IntCns 0} N003 [000108] EQ => $333 {EQ($503, $40)} ***** BB33, stmt 80 (after) N004 ( 7, 6) [000109] ------------ * JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000108] J------N---- \--* EQ int $333 N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) $503 finish(BB33). Succ(BB34). Not yet completed. All preds complete, adding to allDone. Succ(BB35). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#19) at start of BB35 is $25b {PhiMemoryDef($188, $25a)} The SSA definition for GcHeap (#20) at start of BB35 is $25d {PhiMemoryDef($188, $25c)} ***** BB35, stmt 84 (before) N003 ( 1, 1) [000113] ------------ /--* CNS_INT int 0 N004 ( 6, 5) [000115] -A-XG------- * ASG byte N002 ( 4, 3) [000114] *--X---N---- \--* IND byte N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) N001 [000112] LCL_VAR V01 arg1 u:2 (last use) => $81 {InitVal($41)} N003 [000113] CNS_INT 0 => $40 {IntCns 0} VNForCastOper(byte) is $4e fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000115] to VN: $219. N004 [000115] ASG => $VN.Void ***** BB35, stmt 84 (after) N003 ( 1, 1) [000113] ------------ /--* CNS_INT int 0 $40 N004 ( 6, 5) [000115] -A-XG------- * ASG byte $VN.Void N002 ( 4, 3) [000114] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 --------- ***** BB35, stmt 85 (before) N001 ( 1, 1) [000117] ------------ /--* CNS_INT int 0 N003 ( 1, 3) [000119] -A------R--- * ASG int N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 N001 [000117] CNS_INT 0 => $40 {IntCns 0} N002 [000118] LCL_VAR V05 loc3 d:3 => $40 {IntCns 0} N003 [000119] ASG => $40 {IntCns 0} ***** BB35, stmt 85 (after) N001 ( 1, 1) [000117] ------------ /--* CNS_INT int 0 $40 N003 ( 1, 3) [000119] -A------R--- * ASG int $40 N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 $40 finish(BB35). Succ(BB36). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#19) at start of BB34 is $25b {PhiMemoryDef($188, $25a)} The SSA definition for GcHeap (#20) at start of BB34 is $25d {PhiMemoryDef($188, $25c)} ***** BB34, stmt 82 (before) N003 ( 1, 1) [000127] ------------ /--* CNS_INT int 0 N004 ( 6, 5) [000129] -A-XG------- * ASG byte N002 ( 4, 3) [000128] *--X---N---- \--* IND byte N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) N001 [000126] LCL_VAR V01 arg1 u:2 (last use) => $81 {InitVal($41)} N003 [000127] CNS_INT 0 => $40 {IntCns 0} VNForCastOper(byte) is $4e fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000129] to VN: $21a. N004 [000129] ASG => $VN.Void ***** BB34, stmt 82 (after) N003 ( 1, 1) [000127] ------------ /--* CNS_INT int 0 $40 N004 ( 6, 5) [000129] -A-XG------- * ASG byte $VN.Void N002 ( 4, 3) [000128] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 --------- ***** BB34, stmt 83 (before) N001 ( 1, 1) [000131] ------------ /--* CNS_INT int 1 N003 ( 1, 3) [000133] -A------R--- * ASG int N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 N001 [000131] CNS_INT 1 => $41 {IntCns 1} N002 [000132] LCL_VAR V05 loc3 d:4 => $41 {IntCns 1} N003 [000133] ASG => $41 {IntCns 1} ***** BB34, stmt 83 (after) N001 ( 1, 1) [000131] ------------ /--* CNS_INT int 1 $41 N003 ( 1, 3) [000133] -A------R--- * ASG int $41 N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 $41 finish(BB34). Succ(BB36). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#17) at start of BB27 is $257 {PhiMemoryDef($187, $256)} The SSA definition for GcHeap (#18) at start of BB27 is $259 {PhiMemoryDef($187, $258)} ***** BB27, stmt 69 (before) N003 ( 1, 1) [000137] ------------ /--* CNS_INT int 1 N004 ( 6, 5) [000139] -A-XG------- * ASG byte N002 ( 4, 3) [000138] *--X---N---- \--* IND byte N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) N001 [000136] LCL_VAR V01 arg1 u:2 (last use) => $81 {InitVal($41)} N003 [000137] CNS_INT 1 => $41 {IntCns 1} VNForCastOper(byte) is $4e fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000139] to VN: $21b. N004 [000139] ASG => $VN.Void ***** BB27, stmt 69 (after) N003 ( 1, 1) [000137] ------------ /--* CNS_INT int 1 $41 N004 ( 6, 5) [000139] -A-XG------- * ASG byte $VN.Void N002 ( 4, 3) [000138] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 --------- ***** BB27, stmt 70 (before) N001 ( 1, 1) [000141] ------------ /--* CNS_INT int 1 N003 ( 1, 3) [000143] -A------R--- * ASG int N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 N001 [000141] CNS_INT 1 => $41 {IntCns 1} N002 [000142] LCL_VAR V05 loc3 d:5 => $41 {IntCns 1} N003 [000143] ASG => $41 {IntCns 1} ***** BB27, stmt 70 (after) N001 ( 1, 1) [000141] ------------ /--* CNS_INT int 1 $41 N003 ( 1, 3) [000143] -A------R--- * ASG int $41 N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 $41 finish(BB27). Succ(BB36). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB20 is $253 {PhiMemoryDef($186, $252)} The SSA definition for GcHeap (#14) at start of BB20 is $255 {PhiMemoryDef($186, $254)} ***** BB20, stmt 55 (before) N003 ( 1, 1) [000147] ------------ /--* CNS_INT int 0 N004 ( 6, 5) [000149] -A-XG------- * ASG byte N002 ( 4, 3) [000148] *--X---N---- \--* IND byte N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) N001 [000146] LCL_VAR V01 arg1 u:2 (last use) => $81 {InitVal($41)} N003 [000147] CNS_INT 0 => $40 {IntCns 0} VNForCastOper(byte) is $4e fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000149] to VN: $21c. N004 [000149] ASG => $VN.Void ***** BB20, stmt 55 (after) N003 ( 1, 1) [000147] ------------ /--* CNS_INT int 0 $40 N004 ( 6, 5) [000149] -A-XG------- * ASG byte $VN.Void N002 ( 4, 3) [000148] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 --------- ***** BB20, stmt 56 (before) N001 ( 1, 1) [000151] ------------ /--* CNS_INT int 1 N003 ( 1, 3) [000153] -A------R--- * ASG int N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 N001 [000151] CNS_INT 1 => $41 {IntCns 1} N002 [000152] LCL_VAR V05 loc3 d:6 => $41 {IntCns 1} N003 [000153] ASG => $41 {IntCns 1} ***** BB20, stmt 56 (after) N001 ( 1, 1) [000151] ------------ /--* CNS_INT int 1 $41 N003 ( 1, 3) [000153] -A------R--- * ASG int $41 N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 $41 finish(BB20). Succ(BB36). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#7) at start of BB10 is $248 {PhiMemoryDef($183, $247)} The SSA definition for GcHeap (#8) at start of BB10 is $24a {PhiMemoryDef($183, $249)} ***** BB10, stmt 27 (before) N003 ( 1, 1) [000157] ------------ /--* CNS_INT int 1 N004 ( 6, 5) [000159] -A-XG------- * ASG byte N002 ( 4, 3) [000158] *--X---N---- \--* IND byte N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) N001 [000156] LCL_VAR V01 arg1 u:2 (last use) => $81 {InitVal($41)} N003 [000157] CNS_INT 1 => $41 {IntCns 1} VNForCastOper(byte) is $4e fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000159] to VN: $21d. N004 [000159] ASG => $VN.Void ***** BB10, stmt 27 (after) N003 ( 1, 1) [000157] ------------ /--* CNS_INT int 1 $41 N004 ( 6, 5) [000159] -A-XG------- * ASG byte $VN.Void N002 ( 4, 3) [000158] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 --------- ***** BB10, stmt 28 (before) N001 ( 1, 1) [000161] ------------ /--* CNS_INT int 1 N003 ( 1, 3) [000163] -A------R--- * ASG int N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 N001 [000161] CNS_INT 1 => $41 {IntCns 1} N002 [000162] LCL_VAR V05 loc3 d:7 => $41 {IntCns 1} N003 [000163] ASG => $41 {IntCns 1} ***** BB10, stmt 28 (after) N001 ( 1, 1) [000161] ------------ /--* CNS_INT int 1 $41 N003 ( 1, 3) [000163] -A------R--- * ASG int $41 N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 $41 finish(BB10). Succ(BB36). Not yet completed. All preds complete, adding to allDone. SSA definition: set VN of local 5/8 to $504 {PhiDef($5, $8, $4c6)}. The SSA definition for ByrefExposed (#7) at start of BB36 is $248 {PhiMemoryDef($183, $247)} The SSA definition for GcHeap (#8) at start of BB36 is $24a {PhiMemoryDef($183, $249)} ***** BB36, stmt 86 (before) N002 ( 2, 2) [000123] ------------ * RETURN int N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) N001 [000122] LCL_VAR V05 loc3 u:8 (last use) => $504 {PhiDef($5, $8, $4c6)} N002 [000123] RETURN => $1fb {1fb} ***** BB36, stmt 86 (after) N002 ( 2, 2) [000123] ------------ * RETURN int $1fb N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) $504 finish(BB36). *************** In optVnCopyProp() *************** In SsaBuilder::ComputeDominators(Compiler*, ...) Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01} => {V00 V01 V09} Live vars: {V00 V01 V09} => {V00 V01} Copy Assertion for BB04 curSsaName stack: { 9-[000169]:V09 } Live vars: {V00 V01 V67 V68} => {V00 V01 V68} Live vars: {V00 V01 V68} => {V00 V01 V61 V68} Live vars: {V00 V01 V61 V68} => {V00 V01 V61} Live vars: {V00 V01 V61} => {V00 V01 V61 V62} Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V72} Live vars: {V00 V01 V61 V62 V72} => {V00 V01 V61 V62 V72 V73} Live vars: {V00 V01 V61 V62 V72 V73} => {V00 V01 V61 V62 V72 V73 V74} Live vars: {V00 V01 V61 V62 V72 V73 V74} => {V00 V01 V61 V62 V72 V73 V74 V75} VN based copy assertion for [000295] V73 @000003C0 by [000982] V62 @000003C0. N001 ( 1, 1) [000295] ------------ * LCL_VAR int V73 tmp64 u:3 $3c0 New refCnts for V73: refCnt = 2, refCntWtd = 1.25 New refCnts for V62: refCnt = 4, refCntWtd = 3.50 copy propagated to: N001 ( 1, 1) [000295] ------------ * LCL_VAR int V62 tmp53 u:3 $3c0 Live vars: {V00 V01 V61 V62 V72 V73 V74 V75} => {V00 V01 V19 V61 V62 V72 V73 V74 V75} Live vars: {V00 V01 V19 V61 V62 V72 V73 V74 V75} => {V00 V01 V61 V62 V72 V73 V74 V75} Copy Assertion for BB06 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62 V72 V73 V74 V75} => {V00 V01 V20 V61 V62 V72 V73 V74 V75} Live vars: {V00 V01 V20 V61 V62 V72 V73 V74 V75} => {V00 V01 V61 V62 V72 V73 V74 V75} Copy Assertion for BB08 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 20-[000316]:V20 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62 V72 V73 V74 V75} => {V00 V01 V61 V62 V72 V73 V74 V75 V98} Live vars: {V00 V01 V61 V62 V72 V73 V74 V75 V98} => {V00 V01 V61 V62 V73 V74 V75 V98} VN based copy assertion for [001023] V72 @00000000 by [000979] V61 @00000000. N009 ( 3, 2) [001023] -------N---- * LCL_VAR byref V72 tmp63 u:3 (last use) $VN.Null New refCnts for V72: refCnt = 1, refCntWtd = 1 New refCnts for V61: refCnt = 4, refCntWtd = 2.75 copy propagated to: N009 ( 3, 2) [001023] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V61 V62 V73 V74 V75 V98} => {V00 V01 V61 V62 V73 V74 V75} Live vars: {V00 V01 V61 V62 V73 V74 V75} => {V00 V01 V61 V62 V74 V75} VN based copy assertion for [001030] V73 @000003C0 by [000982] V62 @000003C0. N016 ( 1, 1) [001030] -------N---- * LCL_VAR int V73 tmp64 u:3 (last use) $3c0 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V62: refCnt = 5, refCntWtd = 3.75 copy propagated to: N016 ( 1, 1) [001030] -------N---- * LCL_VAR int V62 tmp53 u:3 (last use) $3c0 Live vars: {V00 V01 V61 V62 V74 V75} => {V00 V01 V61 V62 V74 V75 V100} Live vars: {V00 V01 V61 V62 V74 V75 V100} => {V00 V01 V61 V62 V75 V100} Live vars: {V00 V01 V61 V62 V75 V100} => {V00 V01 V61 V62 V75} Live vars: {V00 V01 V61 V62 V75} => {V00 V01 V61 V62} Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Copy Assertion for BB07 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 20-[000316]:V20 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Copy Assertion for BB05 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Copy Assertion for BB09 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V21 V61 V62} => {V00 V01 V61 V62} Copy Assertion for BB11 curSsaName stack: { 0-[000995]:V00 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 21-[001388]:V21 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62} => {V00 V01 V25 V61 V62} Live vars: {V00 V01 V25 V61 V62} => {V00 V01 V61 V62} Copy Assertion for BB14 curSsaName stack: { 0-[000995]:V00 25-[000416]:V25 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 9-[000169]:V09 61-[000979]:V61 62-[000982]:V62 19-[000300]:V19 21-[001388]:V21 67-[001392]:V67 68-[001396]:V68 } Live vars: {V00 V01 V61 V62 V78 V79} => {V00 V01 V61 V62 V79} VN based copy assertion for [001122] V78 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [001122] -------N---- * LCL_VAR byref V78 tmp69 u:3 (last use) $VN.Null New refCnts for V78: refCnt = 2, refCntWtd = 0.50 New refCnts for V61: refCnt = 5, refCntWtd = 3.25 copy propagated to: N001 ( 3, 2) [001122] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V61 V62 V79} => {V00 V01 V61 V62 V63 V79} Live vars: {V00 V01 V61 V62 V63 V79} => {V00 V01 V61 V62 V63} Live vars: {V00 V01 V61 V62 V63} => {V00 V01 V61 V62 V63 V64} VN based copy assertion for [001129] V63 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [001129] -------N---- * LCL_VAR byref V63 tmp54 u:3 $VN.Null New refCnts for V63: refCnt = 2, refCntWtd = 1 New refCnts for V61: refCnt = 6, refCntWtd = 3.75 copy propagated to: N001 ( 3, 2) [001129] -------N---- * LCL_VAR byref V61 tmp52 u:3 $VN.Null Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V61 V62 V63 V64 V83} Live vars: {V00 V01 V61 V62 V63 V64 V83} => {V00 V01 V61 V62 V63 V64 V83 V84} Live vars: {V00 V01 V61 V62 V63 V64 V83 V84} => {V00 V01 V61 V62 V63 V64 V83 V84 V85} Live vars: {V00 V01 V61 V62 V63 V64 V83 V84 V85} => {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} VN based copy assertion for [000542] V84 @000003C2 by [001124] V64 @000003C2. N001 ( 3, 2) [000542] ------------ * LCL_VAR int V84 tmp75 u:3 $3c2 New refCnts for V84: refCnt = 2, refCntWtd = 0.75 New refCnts for V64: refCnt = 4, refCntWtd = 2 copy propagated to: N001 ( 3, 2) [000542] ------------ * LCL_VAR int V64 tmp55 u:3 $3c2 Live vars: {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} => {V00 V01 V35 V61 V62 V63 V64 V83 V84 V85 V86} Live vars: {V00 V01 V35 V61 V62 V63 V64 V83 V84 V85 V86} => {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} Copy Assertion for BB16 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 } Live vars: {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} => {V00 V01 V36 V61 V62 V63 V64 V83 V84 V85 V86} Live vars: {V00 V01 V36 V61 V62 V63 V64 V83 V84 V85 V86} => {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} Copy Assertion for BB17 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 36-[000563]:V36 } Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V37 V61 V62 V63 V64} Copy Assertion for BB18 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 36-[000563]:V36 } Live vars: {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86} => {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86 V101} Live vars: {V00 V01 V61 V62 V63 V64 V83 V84 V85 V86 V101} => {V00 V01 V61 V62 V63 V64 V84 V85 V86 V101} VN based copy assertion for [001165] V83 @00000000 by [000979] V61 @00000000. N009 ( 3, 2) [001165] -------N---- * LCL_VAR byref V83 tmp74 u:3 (last use) $VN.Null New refCnts for V83: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 7, refCntWtd = 4 copy propagated to: N009 ( 3, 2) [001165] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V61 V62 V63 V64 V84 V85 V86 V101} => {V00 V01 V61 V62 V63 V64 V84 V85 V86} Live vars: {V00 V01 V61 V62 V63 V64 V84 V85 V86} => {V00 V01 V61 V62 V63 V64 V85 V86} VN based copy assertion for [001172] V84 @000003C2 by [001124] V64 @000003C2. N016 ( 3, 2) [001172] -------N---- * LCL_VAR int V84 tmp75 u:3 (last use) $3c2 New refCnts for V84: refCnt = 1, refCntWtd = 0.50 New refCnts for V64: refCnt = 5, refCntWtd = 2.25 copy propagated to: N016 ( 3, 2) [001172] -------N---- * LCL_VAR int V64 tmp55 u:3 (last use) $3c2 Live vars: {V00 V01 V61 V62 V63 V64 V85 V86} => {V00 V01 V61 V62 V63 V64 V85 V86 V102} Live vars: {V00 V01 V61 V62 V63 V64 V85 V86 V102} => {V00 V01 V61 V62 V63 V64 V86 V102} Live vars: {V00 V01 V61 V62 V63 V64 V86 V102} => {V00 V01 V61 V62 V63 V64 V86} Live vars: {V00 V01 V61 V62 V63 V64 V86} => {V00 V01 V61 V62 V63 V64} Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V37 V61 V62 V63 V64} Copy Assertion for BB15 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 } Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V37 V61 V62 V63 V64} Copy Assertion for BB19 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 } Live vars: {V00 V01 V37 V61 V62 V63 V64} => {V00 V01 V61 V62 V63 V64} Copy Assertion for BB21 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 37-[001376]:V37 } Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V61 V62 V63 V64 V103} Live vars: {V00 V01 V61 V62 V63 V64 V103} => {V00 V01 V61 V62 V63 V64} VN based copy assertion for [001207] V103 @00000080 by [000995] V00 @00000080. N010 ( 3, 2) [001207] ------------ * LCL_VAR byref V103 tmp94 u:3 (last use) $80 New refCnts for V103: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 13, refCntWtd = 17 copy propagated to: N010 ( 3, 2) [001207] ------------ * LCL_VAR byref V00 arg0 u:2 (last use) $80 Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V62 V63 V64} VN based copy assertion for [001213] V61 @00000000 by [001121] V63 @00000000. N001 ( 3, 2) [001213] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null New refCnts for V61: refCnt = 6, refCntWtd = 3.50 New refCnts for V63: refCnt = 3, refCntWtd = 1.50 copy propagated to: N001 ( 3, 2) [001213] -------N---- * LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null Live vars: {V00 V01 V62 V63 V64} => {V00 V01 V62 V63 V64 V87} Live vars: {V00 V01 V62 V63 V64 V87} => {V00 V01 V63 V64 V87} Live vars: {V00 V01 V63 V64 V87} => {V00 V01 V63 V64 V87 V88} Live vars: {V00 V01 V63 V64 V87 V88} => {V00 V01 V63 V64 V87 V88 V89} Live vars: {V00 V01 V63 V64 V87 V88 V89} => {V00 V01 V63 V64 V87 V88 V89 V90} Live vars: {V00 V01 V63 V64 V87 V88 V89 V90} => {V00 V01 V44 V63 V64 V87 V88 V89 V90} Live vars: {V00 V01 V44 V63 V64 V87 V88 V89 V90} => {V00 V01 V63 V64 V87 V88 V89 V90} Copy Assertion for BB26 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 } Live vars: {V00 V01 V46 V63 V64} => {V00 V01 V63 V64} Copy Assertion for BB28 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 } Live vars: {V00 V01 V63 V64} => {V00 V01 V64} Live vars: {V00 V01 V64} => {V00 V01 V64 V91} Live vars: {V00 V01 V64 V91} => {V00 V01 V91} Live vars: {V00 V01 V91} => {V00 V01 V91 V92} Live vars: {V00 V01 V91 V92} => {V00 V01 V91 V92 V93} Live vars: {V00 V01 V91 V92 V93} => {V01 V91 V92 V93} Live vars: {V01 V91 V92 V93} => {V01 V91 V92 V93 V94} Live vars: {V01 V91 V92 V93 V94} => {V01 V53 V91 V92 V93 V94} Live vars: {V01 V53 V91 V92 V93 V94} => {V01 V91 V92 V93 V94} Copy Assertion for BB33 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 } Live vars: {V01 V55} => {V01} Copy Assertion for BB35 curSsaName stack: { 0-[000995]:V00 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 55-[001368]:V55 } Live vars: {V01} => {} Live vars: {} => {V05} Copy Assertion for BB34 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 55-[001368]:V55 } Live vars: {V01} => {} Live vars: {} => {V05} Copy Assertion for BB30 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 } Live vars: {V01 V91 V92 V93 V94} => {V01 V54 V91 V92 V93 V94} Live vars: {V01 V54 V91 V92 V93 V94} => {V01 V91 V92 V93 V94} Copy Assertion for BB32 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 54-[000823]:V54 } Live vars: {V01 V91 V92 V93 V94} => {V01 V91 V92 V93 V94 V106} Live vars: {V01 V91 V92 V93 V94 V106} => {V01 V92 V93 V94 V106} Live vars: {V01 V92 V93 V94 V106} => {V01 V92 V93 V94} Live vars: {V01 V92 V93 V94} => {V01 V93 V94} Live vars: {V01 V93 V94} => {V01 V93 V94 V107} Live vars: {V01 V93 V94 V107} => {V01 V94 V107} Live vars: {V01 V94 V107} => {V01 V94} Live vars: {V01 V94} => {V01} Live vars: {V01} => {V01 V55} Copy Assertion for BB31 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 54-[000823]:V54 } Live vars: {V01} => {V01 V55} Copy Assertion for BB29 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 91-[001287]:V91 92-[001290]:V92 93-[001295]:V93 94-[001301]:V94 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 53-[000807]:V53 } Live vars: {V01} => {V01 V55} Copy Assertion for BB27 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 46-[001372]:V46 } Live vars: {V01} => {} Live vars: {} => {V05} Copy Assertion for BB23 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 } Live vars: {V00 V01 V63 V64 V87 V88 V89 V90} => {V00 V01 V45 V63 V64 V87 V88 V89 V90} Live vars: {V00 V01 V45 V63 V64 V87 V88 V89 V90} => {V00 V01 V63 V64 V87 V88 V89 V90} Copy Assertion for BB25 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 45-[000693]:V45 } Live vars: {V00 V01 V63 V64 V87 V88 V89 V90} => {V00 V01 V63 V64 V87 V88 V89 V90 V104} Live vars: {V00 V01 V63 V64 V87 V88 V89 V90 V104} => {V00 V01 V63 V64 V88 V89 V90 V104} VN based copy assertion for [001249] V87 @00000000 by [001121] V63 @00000000. N009 ( 3, 2) [001249] -------N---- * LCL_VAR byref V87 tmp78 u:3 (last use) $VN.Null New refCnts for V87: refCnt = 1, refCntWtd = 0.50 New refCnts for V63: refCnt = 4, refCntWtd = 1.75 copy propagated to: N009 ( 3, 2) [001249] -------N---- * LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null Live vars: {V00 V01 V63 V64 V88 V89 V90 V104} => {V00 V01 V63 V64 V88 V89 V90} Live vars: {V00 V01 V63 V64 V88 V89 V90} => {V00 V01 V63 V64 V89 V90} Live vars: {V00 V01 V63 V64 V89 V90} => {V00 V01 V63 V64 V89 V90 V105} Live vars: {V00 V01 V63 V64 V89 V90 V105} => {V00 V01 V63 V64 V90 V105} Live vars: {V00 V01 V63 V64 V90 V105} => {V00 V01 V63 V64 V90} Live vars: {V00 V01 V63 V64 V90} => {V00 V01 V63 V64} Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Copy Assertion for BB24 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 45-[000693]:V45 } Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Copy Assertion for BB22 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 87-[001212]:V87 88-[001215]:V88 89-[001220]:V89 90-[001226]:V90 35-[000547]:V35 37-[001376]:V37 44-[000677]:V44 103-[001205]:V103 } Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Copy Assertion for BB20 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 63-[001121]:V63 64-[001124]:V64 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 78-[001380]:V78 79-[001384]:V79 21-[001388]:V21 83-[001128]:V83 84-[001131]:V84 25-[000416]:V25 85-[001136]:V85 86-[001142]:V86 35-[000547]:V35 37-[001376]:V37 } Live vars: {V01} => {} Live vars: {} => {V05} Copy Assertion for BB13 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 21-[001388]:V21 25-[000416]:V25 } Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V96} Live vars: {V00 V01 V61 V62 V96} => {V00 V01 V61 V62} Live vars: {V00 V01 V61 V62} => {V00 V01 V26 V61 V62} Live vars: {V00 V01 V26 V61 V62} => {V00 V01 V26 V30 V61 V62} Live vars: {V00 V01 V26 V30 V61 V62} => {V00 V01 V30 V61 V62} VN based copy assertion for [000435] V26 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [000435] ------------ * LCL_VAR byref V26 tmp17 u:3 (last use) $VN.Null New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V61: refCnt = 7, refCntWtd = 3.75 copy propagated to: N001 ( 3, 2) [000435] ------------ * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V30 V61 V62} => {V00 V01 V30 V61 V62 V82} Live vars: {V00 V01 V30 V61 V62 V82} => {V00 V01 V30 V61 V62} VN based copy assertion for [001112] V82 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [001112] -------N---- * LCL_VAR byref V82 tmp73 u:3 (last use) $VN.Null New refCnts for V82: refCnt = 1, refCntWtd = 0.25 New refCnts for V61: refCnt = 8, refCntWtd = 4 copy propagated to: N001 ( 3, 2) [001112] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V30 V61 V62} => {V00 V01 V30 V61 V62 V76} Live vars: {V00 V01 V30 V61 V62 V76} => {V00 V01 V61 V62 V76} Live vars: {V00 V01 V61 V62 V76} => {V00 V01 V61 V62 V76 V77} Live vars: {V00 V01 V61 V62 V76 V77} => {V00 V01 V61 V62 V77} VN based copy assertion for [001115] V76 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [001115] -------N---- * LCL_VAR byref V76 tmp67 u:3 (last use) $VN.Null New refCnts for V76: refCnt = 1, refCntWtd = 0.25 New refCnts for V61: refCnt = 9, refCntWtd = 4.25 copy propagated to: N001 ( 3, 2) [001115] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V61 V62 V77} => {V00 V01 V61 V62 V77 V78} Live vars: {V00 V01 V61 V62 V77 V78} => {V00 V01 V61 V62 V78} Live vars: {V00 V01 V61 V62 V78} => {V00 V01 V61 V62 V78 V79} Copy Assertion for BB12 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 21-[001388]:V21 25-[000416]:V25 } Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V80} Live vars: {V00 V01 V61 V62 V80} => {V00 V01 V61 V62 V80 V81} Live vars: {V00 V01 V61 V62 V80 V81} => {V00 V01 V61 V62 V81} VN based copy assertion for [001072] V80 @00000000 by [000979] V61 @00000000. N001 ( 3, 2) [001072] -------N---- * LCL_VAR byref V80 tmp71 u:3 (last use) $VN.Null New refCnts for V80: refCnt = 1, refCntWtd = 0.25 New refCnts for V61: refCnt = 10, refCntWtd = 4.50 copy propagated to: N001 ( 3, 2) [001072] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null Live vars: {V00 V01 V61 V62 V81} => {V00 V01 V61 V62 V78 V81} Live vars: {V00 V01 V61 V62 V78 V81} => {V00 V01 V61 V62 V78} Live vars: {V00 V01 V61 V62 V78} => {V00 V01 V61 V62 V78 V79} Copy Assertion for BB10 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 21-[001388]:V21 } Live vars: {V01} => {} Live vars: {} => {V05} Copy Assertion for BB36 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 61-[000979]:V61 62-[000982]:V62 67-[001392]:V67 68-[001396]:V68 9-[000169]:V09 72-[000986]:V72 73-[000989]:V73 74-[000994]:V74 75-[001000]:V75 19-[000300]:V19 21-[001388]:V21 } Live vars: {V05} => {} Copy Assertion for BB03 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 9-[000169]:V09 } Live vars: {V00 V01} => {V00 V01 V96} Live vars: {V00 V01 V96} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V10} Live vars: {V00 V01 V10} => {V00 V01 V10 V14} Live vars: {V00 V01 V10 V14} => {V00 V01 V14} Live vars: {V00 V01 V14} => {V00 V01 V14 V71} Live vars: {V00 V01 V14 V71} => {V00 V01 V14} Live vars: {V00 V01 V14} => {V00 V01 V14 V65} Live vars: {V00 V01 V14 V65} => {V00 V01 V65} Live vars: {V00 V01 V65} => {V00 V01 V65 V66} Live vars: {V00 V01 V65 V66} => {V00 V01 V66} Live vars: {V00 V01 V66} => {V00 V01 V66 V67} Live vars: {V00 V01 V66 V67} => {V00 V01 V67} Live vars: {V00 V01 V67} => {V00 V01 V67 V68} Copy Assertion for BB02 curSsaName stack: { 0-[000995]:V00 1-[000112]:V01 9-[000169]:V09 } Live vars: {V00 V01} => {V00 V01 V69} Live vars: {V00 V01 V69} => {V00 V01 V69 V70} Live vars: {V00 V01 V69 V70} => {V00 V01 V70} Live vars: {V00 V01 V70} => {V00 V01 V67 V70} Live vars: {V00 V01 V67 V70} => {V00 V01 V67} Live vars: {V00 V01 V67} => {V00 V01 V67 V68} *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N003 ( 1, 1) [000167] ------------ | /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000168] ------------ | /--* EQ int $40 N002 ( 3, 10) [000921] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000920] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N006 ( 8, 12) [000170] -A------R--- \--* ASG bool $40 N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 ***** BB01, stmt 2 ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000174] J------N---- \--* EQ int $41 N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) $40 ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 3 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 $40 N007 ( 10, 8) [000928] -A---------- \--* COMMA void $40 N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [000924] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 $VN.Null ***** BB02, stmt 4 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) $40 N006 ( 7, 5) [000934] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 $40 N007 ( 14, 10) [000935] -A---------- \--* COMMA void $40 N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) $VN.Null N003 ( 7, 5) [000931] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 $VN.Null ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 5 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null ***** BB03, stmt 6 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [000956] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB03, stmt 7 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void $341 N003 ( 0, 0) [000963] ------------ \--* COMMA void $341 N001 ( 0, 0) [000959] ------------ \--* NOP void $340 ***** BB03, stmt 8 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB03, stmt 9 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null N003 ( 7, 5) [000266] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 $VN.Null ***** BB03, stmt 10 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null N003 ( 7, 5) [000971] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 $VN.Null ***** BB03, stmt 11 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB03, stmt 12 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null N003 ( 7, 5) [000974] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 $VN.Null ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 13 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB04, stmt 14 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 $VN.Null N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB04, stmt 15 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) $3c0 N006 ( 7, 5) [000984] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 $3c0 N007 ( 14, 10) [000985] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null N003 ( 7, 5) [000981] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 $VN.Null ***** BB04, stmt 16 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 $3c0 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int $3c0 N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 $3c0 N007 ( 10, 8) [000992] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [000988] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 $VN.Null ***** BB04, stmt 17 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB04, stmt 18 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V62 tmp53 u:3 $3c0 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB04, stmt 19 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 20 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 $40 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 21 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 $40 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 22 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 23 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool $41 N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 $41 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 24 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 $40 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int $30d N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref $404 N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref $403 N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 $2ca N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref $2ca N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $480 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref $2ca N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 $2ca N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref $407 N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref $406 N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 $2cc N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref $2cc N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $481 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref $2cc N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 $2cc N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref $2ce N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $482 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref $2cf N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $483 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool $30d N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 $30d ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 25 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 $30d N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 26 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000027] J------N---- \--* EQ int $30e N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) $500 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 27 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000158] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB10, stmt 28 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000163] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 $41 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 29 ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N003 ( 1, 1) [000414] ------------ | /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000415] ------------ | /--* EQ int $40 N002 ( 3, 10) [001063] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001062] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N006 ( 12, 15) [000417] -A------R--- \--* ASG bool $40 N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 ***** BB11, stmt 30 ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000421] J------N---- \--* EQ int $41 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) $40 ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 31 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 $40 N007 ( 10, 8) [001070] -A---------- \--* COMMA void $40 N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [001066] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 $VN.Null ***** BB12, stmt 32 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) $40 N006 ( 7, 5) [001076] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 $40 N007 ( 14, 10) [001077] -A---------- \--* COMMA void $40 N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001073] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 $VN.Null ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 33 ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null ***** BB13, stmt 34 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [001098] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB13, stmt 35 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void $343 N003 ( 0, 0) [001105] ------------ \--* COMMA void $343 N001 ( 0, 0) [001101] ------------ \--* NOP void $342 ***** BB13, stmt 36 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB13, stmt 37 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [000513] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 $VN.Null ***** BB13, stmt 38 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001113] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 $VN.Null ***** BB13, stmt 39 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB13, stmt 40 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001116] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 $VN.Null ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 41 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB14, stmt 42 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 $VN.Null N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB14, stmt 43 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) $3c2 N006 ( 7, 5) [001126] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 $3c2 N007 ( 14, 10) [001127] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001123] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 $VN.Null ***** BB14, stmt 44 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 $3c2 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 $3c2 N007 ( 14, 10) [001134] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [001130] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 $VN.Null ***** BB14, stmt 45 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB14, stmt 46 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V64 tmp55 u:3 $3c2 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB14, stmt 47 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 48 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 $40 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 49 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 50 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 51 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 $41 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 52 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int $31e N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref $409 N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) $2da N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref $408 N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 $2da N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref $2da N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $484 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref $2da N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 $2da N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref $40b N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref $40a N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 $2dc N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref $2dc N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $485 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref $2dc N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 $2dc N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref $2de N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $486 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref $2df N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $487 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool $31e N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 $31e ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 53 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 $41 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 54 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000057] J------N---- \--* EQ int $31f N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) $501 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 55 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000148] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB20, stmt 56 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000153] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 $41 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 57 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 $80 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref $80 N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 $80 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) $VN.Void N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref $2e1 N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 $489 ***** BB21, stmt 58 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N006 ( 7, 5) [001217] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 $3c0 N007 ( 14, 10) [001218] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001214] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 $VN.Null ***** BB21, stmt 59 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 60 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 $3c0 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 61 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 62 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 $40 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 63 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 64 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 65 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 $41 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 66 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int $328 N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) $3c0 N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref $40d N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref $40c N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 $2e5 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref $2e5 N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48a N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref $2e5 N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 $2e5 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref $40f N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref $40e N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 $2e7 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref $2e7 N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48b N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref $2e7 N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 $2e7 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref $2e9 N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $48c N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref $2ea N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $48d N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool $328 N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 $328 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 67 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 $328 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 68 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000087] J------N---- \--* EQ int $329 N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) $502 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 69 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000138] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB27, stmt 70 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000143] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 $41 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 71 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N006 ( 7, 5) [001292] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 $3c2 N007 ( 14, 10) [001293] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001289] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 $VN.Null ***** BB28, stmt 72 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 73 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 $3c2 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 74 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 75 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 $40 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 76 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 77 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 78 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 $41 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 79 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int $332 N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) $3c2 N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref $411 N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref $410 N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 $2ee N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref $2ee N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48e N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref $2ee N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 $2ee N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref $413 N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref $412 N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 $2f0 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref $2f0 N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48f N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref $2f0 N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 $2f0 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref $2f2 N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $490 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref $2f3 N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $491 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool $332 N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 $332 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 80 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 $332 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 81 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000108] J------N---- \--* EQ int $333 N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) $503 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 82 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000128] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB34, stmt 83 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000133] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 $41 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 84 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000114] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB35, stmt 85 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000119] -A------R--- \--* ASG int $40 N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 $40 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 86 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 $40 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 87 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int $1fb N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) $504 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() *************** In optAssertionPropMain() Blocks/Trees at start of phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 ( cond ) i label target BB02 [0011] 1 BB01 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 ( cond ) i label target BB12 [0029] 1 BB11 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01, stmt 1 ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N003 ( 1, 1) [000167] ------------ | /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000168] ------------ | /--* EQ int $40 N002 ( 3, 10) [000921] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000920] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N006 ( 8, 12) [000170] -A------R--- \--* ASG bool $40 N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 ***** BB01, stmt 2 ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N002 ( 1, 1) [000173] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000174] J------N---- \--* EQ int $41 N001 ( 1, 1) [000172] ------------ \--* LCL_VAR int V09 tmp0 u:3 (last use) $40 ------------ BB02 [001..002) -> BB04 (always), preds={BB01} succs={BB04} ***** BB02, stmt 3 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 $40 N007 ( 10, 8) [000928] -A---------- \--* COMMA void $40 N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [000924] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 $VN.Null ***** BB02, stmt 4 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) $40 N006 ( 7, 5) [000934] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 $40 N007 ( 14, 10) [000935] -A---------- \--* COMMA void $40 N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) $VN.Null N003 ( 7, 5) [000931] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 $VN.Null ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 5 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null ***** BB03, stmt 6 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [000956] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB03, stmt 7 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void $341 N003 ( 0, 0) [000963] ------------ \--* COMMA void $341 N001 ( 0, 0) [000959] ------------ \--* NOP void $340 ***** BB03, stmt 8 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB03, stmt 9 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null N003 ( 7, 5) [000266] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 $VN.Null ***** BB03, stmt 10 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null N003 ( 7, 5) [000971] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 $VN.Null ***** BB03, stmt 11 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB03, stmt 12 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null N003 ( 7, 5) [000974] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 $VN.Null ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 13 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB04, stmt 14 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 $VN.Null N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB04, stmt 15 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) $3c0 N006 ( 7, 5) [000984] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 $3c0 N007 ( 14, 10) [000985] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null N003 ( 7, 5) [000981] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 $VN.Null ***** BB04, stmt 16 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 $3c0 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int $3c0 N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 $3c0 N007 ( 10, 8) [000992] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [000988] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 $VN.Null ***** BB04, stmt 17 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB04, stmt 18 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V62 tmp53 u:3 $3c0 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB04, stmt 19 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 20 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 $40 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 21 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 $40 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 22 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 23 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool $41 N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 $41 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 24 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 $40 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int $30d N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref $404 N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref $403 N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 $2ca N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref $2ca N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $480 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref $2ca N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 $2ca N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref $407 N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref $406 N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 $2cc N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref $2cc N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $481 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref $2cc N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 $2cc N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref $2ce N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $482 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref $2cf N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $483 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool $30d N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 $30d ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 25 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 $30d N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 26 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000027] J------N---- \--* EQ int $30e N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) $500 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 27 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000158] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB10, stmt 28 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000163] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 $41 ------------ BB11 [01F..037) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB11, stmt 29 ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N003 ( 1, 1) [000414] ------------ | /--* CNS_INT ref null $VN.Null N004 ( 8, 12) [000415] ------------ | /--* EQ int $40 N002 ( 3, 10) [001063] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001062] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N006 ( 12, 15) [000417] -A------R--- \--* ASG bool $40 N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 ***** BB11, stmt 30 ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N002 ( 1, 1) [000420] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000421] J------N---- \--* EQ int $41 N001 ( 3, 2) [000419] ------------ \--* LCL_VAR int V25 tmp16 u:3 (last use) $40 ------------ BB12 [01F..020) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12, stmt 31 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 $40 N007 ( 10, 8) [001070] -A---------- \--* COMMA void $40 N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [001066] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 $VN.Null ***** BB12, stmt 32 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) $40 N006 ( 7, 5) [001076] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 $40 N007 ( 14, 10) [001077] -A---------- \--* COMMA void $40 N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001073] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 $VN.Null ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 33 ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null ***** BB13, stmt 34 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [001098] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB13, stmt 35 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void $343 N003 ( 0, 0) [001105] ------------ \--* COMMA void $343 N001 ( 0, 0) [001101] ------------ \--* NOP void $342 ***** BB13, stmt 36 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB13, stmt 37 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [000513] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 $VN.Null ***** BB13, stmt 38 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001113] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 $VN.Null ***** BB13, stmt 39 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB13, stmt 40 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001116] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 $VN.Null ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 41 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB14, stmt 42 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 $VN.Null N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB14, stmt 43 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) $3c2 N006 ( 7, 5) [001126] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 $3c2 N007 ( 14, 10) [001127] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001123] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 $VN.Null ***** BB14, stmt 44 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 $3c2 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 $3c2 N007 ( 14, 10) [001134] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [001130] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 $VN.Null ***** BB14, stmt 45 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB14, stmt 46 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V64 tmp55 u:3 $3c2 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB14, stmt 47 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 48 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 $40 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 49 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 50 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 51 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 $41 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 52 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int $31e N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref $409 N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) $2da N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref $408 N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 $2da N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref $2da N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $484 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref $2da N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 $2da N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref $40b N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref $40a N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 $2dc N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref $2dc N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $485 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref $2dc N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 $2dc N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref $2de N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $486 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref $2df N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $487 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool $31e N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 $31e ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 53 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 $41 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 54 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000057] J------N---- \--* EQ int $31f N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) $501 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 55 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000148] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB20, stmt 56 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000153] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 $41 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 57 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 $80 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref $80 N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 $80 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) $VN.Void N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref $2e1 N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 $489 ***** BB21, stmt 58 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N006 ( 7, 5) [001217] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 $3c0 N007 ( 14, 10) [001218] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001214] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 $VN.Null ***** BB21, stmt 59 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 60 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 $3c0 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 61 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 62 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 $40 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 63 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 64 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 65 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 $41 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 66 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int $328 N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) $3c0 N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref $40d N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref $40c N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 $2e5 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref $2e5 N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48a N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref $2e5 N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 $2e5 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref $40f N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref $40e N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 $2e7 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref $2e7 N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48b N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref $2e7 N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 $2e7 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref $2e9 N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $48c N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref $2ea N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $48d N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool $328 N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 $328 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 67 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 $328 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 68 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000087] J------N---- \--* EQ int $329 N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) $502 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 69 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000138] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB27, stmt 70 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000143] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 $41 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 71 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N006 ( 7, 5) [001292] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 $3c2 N007 ( 14, 10) [001293] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001289] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 $VN.Null ***** BB28, stmt 72 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 73 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 $3c2 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 74 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 75 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 $40 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 76 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 77 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 78 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 $41 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 79 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int $332 N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) $3c2 N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref $411 N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref $410 N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 $2ee N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref $2ee N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48e N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref $2ee N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 $2ee N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref $413 N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref $412 N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 $2f0 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref $2f0 N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48f N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref $2f0 N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 $2f0 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref $2f2 N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $490 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref $2f3 N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $491 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool $332 N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 $332 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 80 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 $332 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 81 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000108] J------N---- \--* EQ int $333 N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) $503 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 82 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000128] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB34, stmt 83 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000133] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 $41 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 84 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000114] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB35, stmt 85 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000119] -A------R--- \--* ASG int $40 N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 $40 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 86 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 $40 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 87 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int $1fb N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) $504 ------------------------------------------------------------------------------------------------------------------- After constant propagation on [000168]: ( 8, 12) [000171] ------------ * STMT void (IL 0x001... ???) N004 ( 8, 12) [000168] ------------ | /--* CNS_INT int 0 $40 N006 ( 8, 12) [000170] -A------R--- \--* ASG bool $40 N005 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 New refCnts for V09: refCnt = 3, refCntWtd = 3 optVNAssertionPropCurStmt morphed tree: N001 ( 1, 1) [000168] ------------ /--* CNS_INT int 0 $40 N003 ( 1, 3) [000170] -A------R--- * ASG bool $40 N002 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 New refCnts for V09: refCnt = 2, refCntWtd = 2 After constant propagation on [000175]: ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void [001451] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000174] J------N---- \--* EQ int $41 [001450] ------------ \--* CNS_INT int 0 $40 Folding operator with constant nodes into a constant: [001451] ------------ /--* CNS_INT int 0 $40 N003 ( 3, 3) [000174] J------N---- * EQ int $41 [001450] ------------ \--* CNS_INT int 0 $40 Bashed to int constant: N003 ( 3, 3) [000174] ------------ * CNS_INT int 1 $41 Removing statement [000176] in BB01 as useless: ( 5, 5) [000176] ------------ * STMT void (IL 0x001... ???) N004 ( 5, 5) [000175] ------------ \--* JTRUE void N003 ( 3, 3) [000174] ------------ \--* CNS_INT int 1 $41 Conditional folded at BB01 BB01 becomes a BBJ_ALWAYS to BB03 optVNAssertionPropCurStmt removed tree: N004 ( 5, 5) [000175] ------------ * JTRUE void N003 ( 3, 3) [000174] ------------ \--* CNS_INT int 1 $41 After constant propagation on [000940]: ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null After constant propagation on [000943]: ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [000949] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V96: refCnt = 7, refCntWtd = 1.75 New refCnts for V96: refCnt = 8, refCntWtd = 2 New refCnts for V96: refCnt = 9, refCntWtd = 2.25 optVNAssertionPropCurStmt morphed tree: N009 ( 1, 1) [000944] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [001452] -A-X-------- | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- * ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null GenTreeNode creates assertion: N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 In BB03 New Global Constant Assertion: (384, 0) ($180,$0) V96.04 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: N004 ( 5, 5) [000306] ------------ * JTRUE void In BB04 New Global Constant Assertion: (773, 64) ($305,$40) V19.03 == 0 index=#02, mask=0000000000000002 GenTreeNode creates assertion: N004 ( 5, 5) [000306] ------------ * JTRUE void In BB04 New Global Constant Assertion: (773, 64) ($305,$40) V19.03 != 0 index=#03, mask=0000000000000004 GenTreeNode creates assertion: N004 ( 7, 6) [000322] ------------ * JTRUE void In BB06 New Global Constant Assertion: (777, 64) ($309,$40) V20.03 == 0 index=#04, mask=0000000000000008 GenTreeNode creates assertion: N004 ( 7, 6) [000322] ------------ * JTRUE void In BB06 New Global Constant Assertion: (777, 64) ($309,$40) V20.03 != 0 index=#05, mask=0000000000000010 GenTreeNode creates assertion: N004 ( 5, 5) [000028] ------------ * JTRUE void In BB09 New Global Constant Assertion: (1280, 64) ($500,$40) V21.06 == 0 index=#06, mask=0000000000000020 GenTreeNode creates assertion: N004 ( 5, 5) [000028] ------------ * JTRUE void In BB09 New Global Constant Assertion: (1280, 64) ($500,$40) V21.06 != 0 index=#07, mask=0000000000000040 After constant propagation on [000415]: ( 12, 15) [000418] ------------ * STMT void (IL 0x01F... ???) N004 ( 8, 12) [000415] ------------ | /--* CNS_INT int 0 $40 N006 ( 12, 15) [000417] -A------R--- \--* ASG bool $40 N005 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 New refCnts for V25: refCnt = 3, refCntWtd = 1.50 optVNAssertionPropCurStmt morphed tree: N001 ( 1, 1) [000415] ------------ /--* CNS_INT int 0 $40 N003 ( 5, 4) [000417] -A------R--- * ASG bool $40 N002 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 New refCnts for V25: refCnt = 2, refCntWtd = 1 After constant propagation on [000422]: ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void [001454] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000421] J------N---- \--* EQ int $41 [001453] ------------ \--* CNS_INT int 0 $40 Folding operator with constant nodes into a constant: [001454] ------------ /--* CNS_INT int 0 $40 N003 ( 5, 4) [000421] J------N---- * EQ int $41 [001453] ------------ \--* CNS_INT int 0 $40 Bashed to int constant: N003 ( 5, 4) [000421] ------------ * CNS_INT int 1 $41 Removing statement [000423] in BB11 as useless: ( 7, 6) [000423] ------------ * STMT void (IL 0x01F... ???) N004 ( 7, 6) [000422] ------------ \--* JTRUE void N003 ( 5, 4) [000421] ------------ \--* CNS_INT int 1 $41 Conditional folded at BB11 BB11 becomes a BBJ_ALWAYS to BB13 optVNAssertionPropCurStmt removed tree: N004 ( 7, 6) [000422] ------------ * JTRUE void N003 ( 5, 4) [000421] ------------ \--* CNS_INT int 1 $41 After constant propagation on [001082]: ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null After constant propagation on [001085]: ( 20, 23) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 16, 20) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 4, 3) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 3, 2) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 11, 16) [001091] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 7, 13) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 3, 2) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 20, 23) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V96: refCnt = 10, refCntWtd = 2.50 New refCnts for V96: refCnt = 11, refCntWtd = 2.75 New refCnts for V96: refCnt = 12, refCntWtd = 3 optVNAssertionPropCurStmt morphed tree: N009 ( 1, 1) [001086] ------------ /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 3, 3) [001087] ------------ /--* ADD byref $VN.Null N008 ( 1, 1) [001085] ------------ | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 8, 15) [001088] -A-XG--N---- /--* COMMA byref $24d N006 ( 2, 2) [001083] ---X---N---- | | /--* NULLCHECK byte $24c N005 ( 1, 1) [001082] ------------ | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 5, 12) [001455] -A-X-------- | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 3, 10) [001081] -A------R--- | \--* ASG ref $184 N003 ( 1, 1) [001080] D------N---- | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 12, 18) [000433] -A-XG---R--- * ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null GenTreeNode creates assertion: N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c In BB13 New Global Constant Assertion: (388, 0) ($184,$0) V96.03 != null index=#08, mask=0000000000000080 GenTreeNode creates assertion: N004 ( 7, 6) [000553] ------------ * JTRUE void In BB14 New Global Constant Assertion: (790, 64) ($316,$40) V35.03 == 0 index=#09, mask=0000000000000100 GenTreeNode creates assertion: N004 ( 7, 6) [000553] ------------ * JTRUE void In BB14 New Global Constant Assertion: (790, 64) ($316,$40) V35.03 != 0 index=#10, mask=0000000000000200 GenTreeNode creates assertion: N004 ( 7, 6) [000569] ------------ * JTRUE void In BB16 New Global Constant Assertion: (794, 64) ($31a,$40) V36.03 == 0 index=#11, mask=0000000000000400 GenTreeNode creates assertion: N004 ( 7, 6) [000569] ------------ * JTRUE void In BB16 New Global Constant Assertion: (794, 64) ($31a,$40) V36.03 != 0 index=#12, mask=0000000000000800 GenTreeNode creates assertion: N004 ( 7, 6) [000058] ------------ * JTRUE void In BB19 New Global Constant Assertion: (1281, 64) ($501,$40) V37.06 == 0 index=#13, mask=0000000000001000 GenTreeNode creates assertion: N004 ( 7, 6) [000058] ------------ * JTRUE void In BB19 New Global Constant Assertion: (1281, 64) ($501,$40) V37.06 != 0 index=#14, mask=0000000000002000 GenTreeNode creates assertion: N004 ( 7, 6) [000683] ------------ * JTRUE void In BB21 New Global Constant Assertion: (800, 64) ($320,$40) V44.03 == 0 index=#15, mask=0000000000004000 GenTreeNode creates assertion: N004 ( 7, 6) [000683] ------------ * JTRUE void In BB21 New Global Constant Assertion: (800, 64) ($320,$40) V44.03 != 0 index=#16, mask=0000000000008000 GenTreeNode creates assertion: N004 ( 7, 6) [000699] ------------ * JTRUE void In BB23 New Global Constant Assertion: (804, 64) ($324,$40) V45.03 == 0 index=#17, mask=0000000000010000 GenTreeNode creates assertion: N004 ( 7, 6) [000699] ------------ * JTRUE void In BB23 New Global Constant Assertion: (804, 64) ($324,$40) V45.03 != 0 index=#18, mask=0000000000020000 GenTreeNode creates assertion: N004 ( 7, 6) [000088] ------------ * JTRUE void In BB26 New Global Constant Assertion: (1282, 64) ($502,$40) V46.03 == 0 index=#19, mask=0000000000040000 GenTreeNode creates assertion: N004 ( 7, 6) [000088] ------------ * JTRUE void In BB26 New Global Constant Assertion: (1282, 64) ($502,$40) V46.03 != 0 index=#20, mask=0000000000080000 GenTreeNode creates assertion: N004 ( 7, 6) [000813] ------------ * JTRUE void In BB28 New Global Constant Assertion: (810, 64) ($32a,$40) V53.03 == 0 index=#21, mask=0000000000100000 GenTreeNode creates assertion: N004 ( 7, 6) [000813] ------------ * JTRUE void In BB28 New Global Constant Assertion: (810, 64) ($32a,$40) V53.03 != 0 index=#22, mask=0000000000200000 GenTreeNode creates assertion: N004 ( 7, 6) [000829] ------------ * JTRUE void In BB30 New Global Constant Assertion: (814, 64) ($32e,$40) V54.03 == 0 index=#23, mask=0000000000400000 GenTreeNode creates assertion: N004 ( 7, 6) [000829] ------------ * JTRUE void In BB30 New Global Constant Assertion: (814, 64) ($32e,$40) V54.03 != 0 index=#24, mask=0000000000800000 GenTreeNode creates assertion: N004 ( 7, 6) [000109] ------------ * JTRUE void In BB33 New Global Constant Assertion: (1283, 64) ($503,$40) V55.03 == 0 index=#25, mask=0000000001000000 GenTreeNode creates assertion: N004 ( 7, 6) [000109] ------------ * JTRUE void In BB33 New Global Constant Assertion: (1283, 64) ($503,$40) V55.03 != 0 index=#26, mask=0000000002000000 BB01 valueGen = 0000000000000000 BB02 valueGen = 0000000000000000 BB03 valueGen = 0000000000000001 BB04 valueGen = 0000000000000004 => BB06 valueGen = 0000000000000002, BB05 valueGen = 0000000000000000 BB06 valueGen = 0000000000000010 => BB08 valueGen = 0000000000000008, BB07 valueGen = 0000000000000000 BB08 valueGen = 0000000000000000 BB09 valueGen = 0000000000000040 => BB11 valueGen = 0000000000000020, BB10 valueGen = 0000000000000000 BB11 valueGen = 0000000000000000 BB12 valueGen = 0000000000000000 BB13 valueGen = 0000000000000080 BB14 valueGen = 0000000000000200 => BB16 valueGen = 0000000000000100, BB15 valueGen = 0000000000000000 BB16 valueGen = 0000000000000800 => BB18 valueGen = 0000000000000400, BB17 valueGen = 0000000000000000 BB18 valueGen = 0000000000000000 BB19 valueGen = 0000000000002000 => BB21 valueGen = 0000000000001000, BB20 valueGen = 0000000000000000 BB21 valueGen = 0000000000008000 => BB23 valueGen = 0000000000004000, BB22 valueGen = 0000000000000000 BB23 valueGen = 0000000000020000 => BB25 valueGen = 0000000000010000, BB24 valueGen = 0000000000000000 BB25 valueGen = 0000000000000000 BB26 valueGen = 0000000000080000 => BB28 valueGen = 0000000000040000, BB27 valueGen = 0000000000000000 BB28 valueGen = 0000000000200000 => BB30 valueGen = 0000000000100000, BB29 valueGen = 0000000000000000 BB30 valueGen = 0000000000800000 => BB32 valueGen = 0000000000400000, BB31 valueGen = 0000000000000000 BB32 valueGen = 0000000000000000 BB33 valueGen = 0000000002000000 => BB35 valueGen = 0000000001000000, BB34 valueGen = 0000000000000000 BB35 valueGen = 0000000000000000 BB36 valueGen = 0000000000000000AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 0000000003FFFFFF; after out -> 0000000000000000; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB03 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB03 in -> 0000000003FFFFFF, predBlock BB01 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000 AssertionPropCallback::Changed : BB03 before out -> 0000000003FFFFFF; after out -> 0000000000000001; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB04 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB04 in -> 0000000003FFFFFF, predBlock BB02 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB04 in -> 0000000003FFFFFF, predBlock BB03 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000001 AssertionPropCallback::Changed : BB04 before out -> 0000000003FFFFFF; after out -> 0000000000000005; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB05 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB05 in -> 0000000003FFFFFF, predBlock BB04 out -> 0000000000000005 AssertionPropCallback::EndMerge : BB05 in -> 0000000000000005 AssertionPropCallback::Changed : BB05 before out -> 0000000003FFFFFF; after out -> 0000000000000005; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000005; AssertionPropCallback::StartMerge: BB06 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB06 in -> 0000000003FFFFFF, predBlock BB04 out -> 0000000000000005 AssertionPropCallback::EndMerge : BB06 in -> 0000000000000003 AssertionPropCallback::Changed : BB06 before out -> 0000000003FFFFFF; after out -> 0000000000000013; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 000000000000000B; AssertionPropCallback::StartMerge: BB09 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB09 in -> 0000000003FFFFFF, predBlock BB05 out -> 0000000000000005 AssertionPropCallback::Merge : BB09 in -> 0000000000000005, predBlock BB07 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB09 in -> 0000000000000005, predBlock BB08 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB09 in -> 0000000000000005 AssertionPropCallback::Changed : BB09 before out -> 0000000003FFFFFF; after out -> 0000000000000045; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000025; AssertionPropCallback::StartMerge: BB07 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB07 in -> 0000000003FFFFFF, predBlock BB06 out -> 0000000000000013 AssertionPropCallback::EndMerge : BB07 in -> 0000000000000013 AssertionPropCallback::Changed : BB07 before out -> 0000000003FFFFFF; after out -> 0000000000000013; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000013; AssertionPropCallback::StartMerge: BB08 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB08 in -> 0000000003FFFFFF, predBlock BB06 out -> 0000000000000013 AssertionPropCallback::EndMerge : BB08 in -> 000000000000000B AssertionPropCallback::Changed : BB08 before out -> 0000000003FFFFFF; after out -> 000000000000000B; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 000000000000000B; AssertionPropCallback::StartMerge: BB10 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB10 in -> 0000000003FFFFFF, predBlock BB09 out -> 0000000000000045 AssertionPropCallback::EndMerge : BB10 in -> 0000000000000045 AssertionPropCallback::Changed : BB10 before out -> 0000000003FFFFFF; after out -> 0000000000000045; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000045; AssertionPropCallback::StartMerge: BB11 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB11 in -> 0000000003FFFFFF, predBlock BB09 out -> 0000000000000045 AssertionPropCallback::EndMerge : BB11 in -> 0000000000000025 AssertionPropCallback::Changed : BB11 before out -> 0000000003FFFFFF; after out -> 0000000000000025; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000025; AssertionPropCallback::StartMerge: BB09 in -> 0000000000000005 AssertionPropCallback::Merge : BB09 in -> 0000000000000005, predBlock BB05 out -> 0000000000000005 AssertionPropCallback::Merge : BB09 in -> 0000000000000005, predBlock BB07 out -> 0000000000000013 AssertionPropCallback::Merge : BB09 in -> 0000000000000001, predBlock BB08 out -> 000000000000000B AssertionPropCallback::EndMerge : BB09 in -> 0000000000000001 AssertionPropCallback::Changed : BB09 before out -> 0000000000000045; after out -> 0000000000000041; jumpDest before out -> 0000000000000025; jumpDest after out -> 0000000000000021; AssertionPropCallback::StartMerge: BB09 in -> 0000000000000001 AssertionPropCallback::Merge : BB09 in -> 0000000000000001, predBlock BB05 out -> 0000000000000005 AssertionPropCallback::Merge : BB09 in -> 0000000000000001, predBlock BB07 out -> 0000000000000013 AssertionPropCallback::Merge : BB09 in -> 0000000000000001, predBlock BB08 out -> 000000000000000B AssertionPropCallback::EndMerge : BB09 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB09 out -> 0000000000000041; jumpDest out -> 0000000000000021 AssertionPropCallback::StartMerge: BB36 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000003FFFFFF, predBlock BB10 out -> 0000000000000045 AssertionPropCallback::Merge : BB36 in -> 0000000000000045, predBlock BB20 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000045, predBlock BB27 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000045, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000045, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000045 AssertionPropCallback::Changed : BB36 before out -> 0000000003FFFFFF; after out -> 0000000000000045; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000045; AssertionPropCallback::StartMerge: BB13 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB13 in -> 0000000003FFFFFF, predBlock BB11 out -> 0000000000000025 AssertionPropCallback::EndMerge : BB13 in -> 0000000000000025 AssertionPropCallback::Changed : BB13 before out -> 0000000003FFFFFF; after out -> 00000000000000A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 0000000000000025; AssertionPropCallback::StartMerge: BB10 in -> 0000000000000045 AssertionPropCallback::Merge : BB10 in -> 0000000000000045, predBlock BB09 out -> 0000000000000041 AssertionPropCallback::EndMerge : BB10 in -> 0000000000000041 AssertionPropCallback::Changed : BB10 before out -> 0000000000000045; after out -> 0000000000000041; jumpDest before out -> 0000000000000045; jumpDest after out -> 0000000000000041; AssertionPropCallback::StartMerge: BB11 in -> 0000000000000025 AssertionPropCallback::Merge : BB11 in -> 0000000000000025, predBlock BB09 out -> 0000000000000041 AssertionPropCallback::EndMerge : BB11 in -> 0000000000000021 AssertionPropCallback::Changed : BB11 before out -> 0000000000000025; after out -> 0000000000000021; jumpDest before out -> 0000000000000025; jumpDest after out -> 0000000000000021; AssertionPropCallback::StartMerge: BB14 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB14 in -> 0000000003FFFFFF, predBlock BB12 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB14 in -> 0000000003FFFFFF, predBlock BB13 out -> 00000000000000A5 AssertionPropCallback::EndMerge : BB14 in -> 00000000000000A5 AssertionPropCallback::Changed : BB14 before out -> 0000000003FFFFFF; after out -> 00000000000002A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000001A5; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000045 AssertionPropCallback::Merge : BB36 in -> 0000000000000045, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB20 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB27 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000041 AssertionPropCallback::Changed : BB36 before out -> 0000000000000045; after out -> 0000000000000041; jumpDest before out -> 0000000000000045; jumpDest after out -> 0000000000000041; AssertionPropCallback::StartMerge: BB13 in -> 0000000000000025 AssertionPropCallback::Merge : BB13 in -> 0000000000000025, predBlock BB11 out -> 0000000000000021 AssertionPropCallback::EndMerge : BB13 in -> 0000000000000021 AssertionPropCallback::Changed : BB13 before out -> 00000000000000A5; after out -> 00000000000000A1; jumpDest before out -> 0000000000000025; jumpDest after out -> 0000000000000021; AssertionPropCallback::StartMerge: BB15 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB15 in -> 0000000003FFFFFF, predBlock BB14 out -> 00000000000002A5 AssertionPropCallback::EndMerge : BB15 in -> 00000000000002A5 AssertionPropCallback::Changed : BB15 before out -> 0000000003FFFFFF; after out -> 00000000000002A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000002A5; AssertionPropCallback::StartMerge: BB16 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB16 in -> 0000000003FFFFFF, predBlock BB14 out -> 00000000000002A5 AssertionPropCallback::EndMerge : BB16 in -> 00000000000001A5 AssertionPropCallback::Changed : BB16 before out -> 0000000003FFFFFF; after out -> 00000000000009A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000005A5; AssertionPropCallback::StartMerge: BB14 in -> 00000000000000A5 AssertionPropCallback::Merge : BB14 in -> 00000000000000A5, predBlock BB12 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB14 in -> 00000000000000A5, predBlock BB13 out -> 00000000000000A1 AssertionPropCallback::EndMerge : BB14 in -> 00000000000000A1 AssertionPropCallback::Changed : BB14 before out -> 00000000000002A5; after out -> 00000000000002A1; jumpDest before out -> 00000000000001A5; jumpDest after out -> 00000000000001A1; AssertionPropCallback::StartMerge: BB19 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB19 in -> 0000000003FFFFFF, predBlock BB15 out -> 00000000000002A5 AssertionPropCallback::Merge : BB19 in -> 00000000000002A5, predBlock BB17 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB19 in -> 00000000000002A5, predBlock BB18 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB19 in -> 00000000000002A5 AssertionPropCallback::Changed : BB19 before out -> 0000000003FFFFFF; after out -> 00000000000022A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000012A5; AssertionPropCallback::StartMerge: BB17 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB17 in -> 0000000003FFFFFF, predBlock BB16 out -> 00000000000009A5 AssertionPropCallback::EndMerge : BB17 in -> 00000000000009A5 AssertionPropCallback::Changed : BB17 before out -> 0000000003FFFFFF; after out -> 00000000000009A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000009A5; AssertionPropCallback::StartMerge: BB18 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB18 in -> 0000000003FFFFFF, predBlock BB16 out -> 00000000000009A5 AssertionPropCallback::EndMerge : BB18 in -> 00000000000005A5 AssertionPropCallback::Changed : BB18 before out -> 0000000003FFFFFF; after out -> 00000000000005A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000005A5; AssertionPropCallback::StartMerge: BB15 in -> 00000000000002A5 AssertionPropCallback::Merge : BB15 in -> 00000000000002A5, predBlock BB14 out -> 00000000000002A1 AssertionPropCallback::EndMerge : BB15 in -> 00000000000002A1 AssertionPropCallback::Changed : BB15 before out -> 00000000000002A5; after out -> 00000000000002A1; jumpDest before out -> 00000000000002A5; jumpDest after out -> 00000000000002A1; AssertionPropCallback::StartMerge: BB16 in -> 00000000000001A5 AssertionPropCallback::Merge : BB16 in -> 00000000000001A5, predBlock BB14 out -> 00000000000002A1 AssertionPropCallback::EndMerge : BB16 in -> 00000000000001A1 AssertionPropCallback::Changed : BB16 before out -> 00000000000009A5; after out -> 00000000000009A1; jumpDest before out -> 00000000000005A5; jumpDest after out -> 00000000000005A1; AssertionPropCallback::StartMerge: BB20 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB20 in -> 0000000003FFFFFF, predBlock BB19 out -> 00000000000022A5 AssertionPropCallback::EndMerge : BB20 in -> 00000000000022A5 AssertionPropCallback::Changed : BB20 before out -> 0000000003FFFFFF; after out -> 00000000000022A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000022A5; AssertionPropCallback::StartMerge: BB21 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB21 in -> 0000000003FFFFFF, predBlock BB19 out -> 00000000000022A5 AssertionPropCallback::EndMerge : BB21 in -> 00000000000012A5 AssertionPropCallback::Changed : BB21 before out -> 0000000003FFFFFF; after out -> 00000000000092A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000052A5; AssertionPropCallback::StartMerge: BB19 in -> 00000000000002A5 AssertionPropCallback::Merge : BB19 in -> 00000000000002A5, predBlock BB15 out -> 00000000000002A1 AssertionPropCallback::Merge : BB19 in -> 00000000000002A1, predBlock BB17 out -> 00000000000009A5 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB18 out -> 00000000000005A5 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000A1 AssertionPropCallback::Changed : BB19 before out -> 00000000000022A5; after out -> 00000000000020A1; jumpDest before out -> 00000000000012A5; jumpDest after out -> 00000000000010A1; AssertionPropCallback::StartMerge: BB19 in -> 00000000000000A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB15 out -> 00000000000002A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB17 out -> 00000000000009A5 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB18 out -> 00000000000005A5 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000A1 AssertionPropCallback::Unchanged : BB19 out -> 00000000000020A1; jumpDest out -> 00000000000010A1 AssertionPropCallback::StartMerge: BB19 in -> 00000000000000A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB15 out -> 00000000000002A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB17 out -> 00000000000009A5 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB18 out -> 00000000000005A5 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000A1 AssertionPropCallback::Unchanged : BB19 out -> 00000000000020A1; jumpDest out -> 00000000000010A1 AssertionPropCallback::StartMerge: BB17 in -> 00000000000009A5 AssertionPropCallback::Merge : BB17 in -> 00000000000009A5, predBlock BB16 out -> 00000000000009A1 AssertionPropCallback::EndMerge : BB17 in -> 00000000000009A1 AssertionPropCallback::Changed : BB17 before out -> 00000000000009A5; after out -> 00000000000009A1; jumpDest before out -> 00000000000009A5; jumpDest after out -> 00000000000009A1; AssertionPropCallback::StartMerge: BB18 in -> 00000000000005A5 AssertionPropCallback::Merge : BB18 in -> 00000000000005A5, predBlock BB16 out -> 00000000000009A1 AssertionPropCallback::EndMerge : BB18 in -> 00000000000005A1 AssertionPropCallback::Changed : BB18 before out -> 00000000000005A5; after out -> 00000000000005A1; jumpDest before out -> 00000000000005A5; jumpDest after out -> 00000000000005A1; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000041, predBlock BB20 out -> 00000000000022A5 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Changed : BB36 before out -> 0000000000000041; after out -> 0000000000000001; jumpDest before out -> 0000000000000041; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB22 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB22 in -> 0000000003FFFFFF, predBlock BB21 out -> 00000000000092A5 AssertionPropCallback::EndMerge : BB22 in -> 00000000000092A5 AssertionPropCallback::Changed : BB22 before out -> 0000000003FFFFFF; after out -> 00000000000092A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000092A5; AssertionPropCallback::StartMerge: BB23 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB23 in -> 0000000003FFFFFF, predBlock BB21 out -> 00000000000092A5 AssertionPropCallback::EndMerge : BB23 in -> 00000000000052A5 AssertionPropCallback::Changed : BB23 before out -> 0000000003FFFFFF; after out -> 00000000000252A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000152A5; AssertionPropCallback::StartMerge: BB20 in -> 00000000000022A5 AssertionPropCallback::Merge : BB20 in -> 00000000000022A5, predBlock BB19 out -> 00000000000020A1 AssertionPropCallback::EndMerge : BB20 in -> 00000000000020A1 AssertionPropCallback::Changed : BB20 before out -> 00000000000022A5; after out -> 00000000000020A1; jumpDest before out -> 00000000000022A5; jumpDest after out -> 00000000000020A1; AssertionPropCallback::StartMerge: BB21 in -> 00000000000012A5 AssertionPropCallback::Merge : BB21 in -> 00000000000012A5, predBlock BB19 out -> 00000000000020A1 AssertionPropCallback::EndMerge : BB21 in -> 00000000000010A1 AssertionPropCallback::Changed : BB21 before out -> 00000000000092A5; after out -> 00000000000090A1; jumpDest before out -> 00000000000052A5; jumpDest after out -> 00000000000050A1; AssertionPropCallback::StartMerge: BB19 in -> 00000000000000A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB15 out -> 00000000000002A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB17 out -> 00000000000009A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB18 out -> 00000000000005A1 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000A1 AssertionPropCallback::Unchanged : BB19 out -> 00000000000020A1; jumpDest out -> 00000000000010A1 AssertionPropCallback::StartMerge: BB19 in -> 00000000000000A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB15 out -> 00000000000002A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB17 out -> 00000000000009A1 AssertionPropCallback::Merge : BB19 in -> 00000000000000A1, predBlock BB18 out -> 00000000000005A1 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000A1 AssertionPropCallback::Unchanged : BB19 out -> 00000000000020A1; jumpDest out -> 00000000000010A1 AssertionPropCallback::StartMerge: BB26 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB26 in -> 0000000003FFFFFF, predBlock BB22 out -> 00000000000092A5 AssertionPropCallback::Merge : BB26 in -> 00000000000092A5, predBlock BB24 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB26 in -> 00000000000092A5, predBlock BB25 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB26 in -> 00000000000092A5 AssertionPropCallback::Changed : BB26 before out -> 0000000003FFFFFF; after out -> 00000000000892A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000492A5; AssertionPropCallback::StartMerge: BB24 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB24 in -> 0000000003FFFFFF, predBlock BB23 out -> 00000000000252A5 AssertionPropCallback::EndMerge : BB24 in -> 00000000000252A5 AssertionPropCallback::Changed : BB24 before out -> 0000000003FFFFFF; after out -> 00000000000252A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000252A5; AssertionPropCallback::StartMerge: BB25 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB25 in -> 0000000003FFFFFF, predBlock BB23 out -> 00000000000252A5 AssertionPropCallback::EndMerge : BB25 in -> 00000000000152A5 AssertionPropCallback::Changed : BB25 before out -> 0000000003FFFFFF; after out -> 00000000000152A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000152A5; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB22 in -> 00000000000092A5 AssertionPropCallback::Merge : BB22 in -> 00000000000092A5, predBlock BB21 out -> 00000000000090A1 AssertionPropCallback::EndMerge : BB22 in -> 00000000000090A1 AssertionPropCallback::Changed : BB22 before out -> 00000000000092A5; after out -> 00000000000090A1; jumpDest before out -> 00000000000092A5; jumpDest after out -> 00000000000090A1; AssertionPropCallback::StartMerge: BB23 in -> 00000000000052A5 AssertionPropCallback::Merge : BB23 in -> 00000000000052A5, predBlock BB21 out -> 00000000000090A1 AssertionPropCallback::EndMerge : BB23 in -> 00000000000050A1 AssertionPropCallback::Changed : BB23 before out -> 00000000000252A5; after out -> 00000000000250A1; jumpDest before out -> 00000000000152A5; jumpDest after out -> 00000000000150A1; AssertionPropCallback::StartMerge: BB27 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB27 in -> 0000000003FFFFFF, predBlock BB26 out -> 00000000000892A5 AssertionPropCallback::EndMerge : BB27 in -> 00000000000892A5 AssertionPropCallback::Changed : BB27 before out -> 0000000003FFFFFF; after out -> 00000000000892A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000000892A5; AssertionPropCallback::StartMerge: BB28 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB28 in -> 0000000003FFFFFF, predBlock BB26 out -> 00000000000892A5 AssertionPropCallback::EndMerge : BB28 in -> 00000000000492A5 AssertionPropCallback::Changed : BB28 before out -> 0000000003FFFFFF; after out -> 00000000002492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000001492A5; AssertionPropCallback::StartMerge: BB26 in -> 00000000000092A5 AssertionPropCallback::Merge : BB26 in -> 00000000000092A5, predBlock BB22 out -> 00000000000090A1 AssertionPropCallback::Merge : BB26 in -> 00000000000090A1, predBlock BB24 out -> 00000000000252A5 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB25 out -> 00000000000152A5 AssertionPropCallback::EndMerge : BB26 in -> 00000000000010A1 AssertionPropCallback::Changed : BB26 before out -> 00000000000892A5; after out -> 00000000000810A1; jumpDest before out -> 00000000000492A5; jumpDest after out -> 00000000000410A1; AssertionPropCallback::StartMerge: BB26 in -> 00000000000010A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB22 out -> 00000000000090A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB24 out -> 00000000000252A5 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB25 out -> 00000000000152A5 AssertionPropCallback::EndMerge : BB26 in -> 00000000000010A1 AssertionPropCallback::Unchanged : BB26 out -> 00000000000810A1; jumpDest out -> 00000000000410A1 AssertionPropCallback::StartMerge: BB26 in -> 00000000000010A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB22 out -> 00000000000090A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB24 out -> 00000000000252A5 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB25 out -> 00000000000152A5 AssertionPropCallback::EndMerge : BB26 in -> 00000000000010A1 AssertionPropCallback::Unchanged : BB26 out -> 00000000000810A1; jumpDest out -> 00000000000410A1 AssertionPropCallback::StartMerge: BB24 in -> 00000000000252A5 AssertionPropCallback::Merge : BB24 in -> 00000000000252A5, predBlock BB23 out -> 00000000000250A1 AssertionPropCallback::EndMerge : BB24 in -> 00000000000250A1 AssertionPropCallback::Changed : BB24 before out -> 00000000000252A5; after out -> 00000000000250A1; jumpDest before out -> 00000000000252A5; jumpDest after out -> 00000000000250A1; AssertionPropCallback::StartMerge: BB25 in -> 00000000000152A5 AssertionPropCallback::Merge : BB25 in -> 00000000000152A5, predBlock BB23 out -> 00000000000250A1 AssertionPropCallback::EndMerge : BB25 in -> 00000000000150A1 AssertionPropCallback::Changed : BB25 before out -> 00000000000152A5; after out -> 00000000000150A1; jumpDest before out -> 00000000000152A5; jumpDest after out -> 00000000000150A1; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000892A5 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB29 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB29 in -> 0000000003FFFFFF, predBlock BB28 out -> 00000000002492A5 AssertionPropCallback::EndMerge : BB29 in -> 00000000002492A5 AssertionPropCallback::Changed : BB29 before out -> 0000000003FFFFFF; after out -> 00000000002492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000002492A5; AssertionPropCallback::StartMerge: BB30 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB30 in -> 0000000003FFFFFF, predBlock BB28 out -> 00000000002492A5 AssertionPropCallback::EndMerge : BB30 in -> 00000000001492A5 AssertionPropCallback::Changed : BB30 before out -> 0000000003FFFFFF; after out -> 00000000009492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000005492A5; AssertionPropCallback::StartMerge: BB27 in -> 00000000000892A5 AssertionPropCallback::Merge : BB27 in -> 00000000000892A5, predBlock BB26 out -> 00000000000810A1 AssertionPropCallback::EndMerge : BB27 in -> 00000000000810A1 AssertionPropCallback::Changed : BB27 before out -> 00000000000892A5; after out -> 00000000000810A1; jumpDest before out -> 00000000000892A5; jumpDest after out -> 00000000000810A1; AssertionPropCallback::StartMerge: BB28 in -> 00000000000492A5 AssertionPropCallback::Merge : BB28 in -> 00000000000492A5, predBlock BB26 out -> 00000000000810A1 AssertionPropCallback::EndMerge : BB28 in -> 00000000000410A1 AssertionPropCallback::Changed : BB28 before out -> 00000000002492A5; after out -> 00000000002410A1; jumpDest before out -> 00000000001492A5; jumpDest after out -> 00000000001410A1; AssertionPropCallback::StartMerge: BB26 in -> 00000000000010A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB22 out -> 00000000000090A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB24 out -> 00000000000250A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB25 out -> 00000000000150A1 AssertionPropCallback::EndMerge : BB26 in -> 00000000000010A1 AssertionPropCallback::Unchanged : BB26 out -> 00000000000810A1; jumpDest out -> 00000000000410A1 AssertionPropCallback::StartMerge: BB26 in -> 00000000000010A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB22 out -> 00000000000090A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB24 out -> 00000000000250A1 AssertionPropCallback::Merge : BB26 in -> 00000000000010A1, predBlock BB25 out -> 00000000000150A1 AssertionPropCallback::EndMerge : BB26 in -> 00000000000010A1 AssertionPropCallback::Unchanged : BB26 out -> 00000000000810A1; jumpDest out -> 00000000000410A1 AssertionPropCallback::StartMerge: BB33 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB33 in -> 0000000003FFFFFF, predBlock BB29 out -> 00000000002492A5 AssertionPropCallback::Merge : BB33 in -> 00000000002492A5, predBlock BB31 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB33 in -> 00000000002492A5, predBlock BB32 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB33 in -> 00000000002492A5 AssertionPropCallback::Changed : BB33 before out -> 0000000003FFFFFF; after out -> 00000000022492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000012492A5; AssertionPropCallback::StartMerge: BB31 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB31 in -> 0000000003FFFFFF, predBlock BB30 out -> 00000000009492A5 AssertionPropCallback::EndMerge : BB31 in -> 00000000009492A5 AssertionPropCallback::Changed : BB31 before out -> 0000000003FFFFFF; after out -> 00000000009492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000009492A5; AssertionPropCallback::StartMerge: BB32 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB32 in -> 0000000003FFFFFF, predBlock BB30 out -> 00000000009492A5 AssertionPropCallback::EndMerge : BB32 in -> 00000000005492A5 AssertionPropCallback::Changed : BB32 before out -> 0000000003FFFFFF; after out -> 00000000005492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000005492A5; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000810A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 0000000003FFFFFF AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 0000000003FFFFFF AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB29 in -> 00000000002492A5 AssertionPropCallback::Merge : BB29 in -> 00000000002492A5, predBlock BB28 out -> 00000000002410A1 AssertionPropCallback::EndMerge : BB29 in -> 00000000002410A1 AssertionPropCallback::Changed : BB29 before out -> 00000000002492A5; after out -> 00000000002410A1; jumpDest before out -> 00000000002492A5; jumpDest after out -> 00000000002410A1; AssertionPropCallback::StartMerge: BB30 in -> 00000000001492A5 AssertionPropCallback::Merge : BB30 in -> 00000000001492A5, predBlock BB28 out -> 00000000002410A1 AssertionPropCallback::EndMerge : BB30 in -> 00000000001410A1 AssertionPropCallback::Changed : BB30 before out -> 00000000009492A5; after out -> 00000000009410A1; jumpDest before out -> 00000000005492A5; jumpDest after out -> 00000000005410A1; AssertionPropCallback::StartMerge: BB34 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB34 in -> 0000000003FFFFFF, predBlock BB33 out -> 00000000022492A5 AssertionPropCallback::EndMerge : BB34 in -> 00000000022492A5 AssertionPropCallback::Changed : BB34 before out -> 0000000003FFFFFF; after out -> 00000000022492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000022492A5; AssertionPropCallback::StartMerge: BB35 in -> 0000000003FFFFFF AssertionPropCallback::Merge : BB35 in -> 0000000003FFFFFF, predBlock BB33 out -> 00000000022492A5 AssertionPropCallback::EndMerge : BB35 in -> 00000000012492A5 AssertionPropCallback::Changed : BB35 before out -> 0000000003FFFFFF; after out -> 00000000012492A5; jumpDest before out -> 0000000003FFFFFF; jumpDest after out -> 00000000012492A5; AssertionPropCallback::StartMerge: BB33 in -> 00000000002492A5 AssertionPropCallback::Merge : BB33 in -> 00000000002492A5, predBlock BB29 out -> 00000000002410A1 AssertionPropCallback::Merge : BB33 in -> 00000000002410A1, predBlock BB31 out -> 00000000009492A5 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB32 out -> 00000000005492A5 AssertionPropCallback::EndMerge : BB33 in -> 00000000000410A1 AssertionPropCallback::Changed : BB33 before out -> 00000000022492A5; after out -> 00000000020410A1; jumpDest before out -> 00000000012492A5; jumpDest after out -> 00000000010410A1; AssertionPropCallback::StartMerge: BB33 in -> 00000000000410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB29 out -> 00000000002410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB31 out -> 00000000009492A5 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB32 out -> 00000000005492A5 AssertionPropCallback::EndMerge : BB33 in -> 00000000000410A1 AssertionPropCallback::Unchanged : BB33 out -> 00000000020410A1; jumpDest out -> 00000000010410A1 AssertionPropCallback::StartMerge: BB33 in -> 00000000000410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB29 out -> 00000000002410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB31 out -> 00000000009492A5 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB32 out -> 00000000005492A5 AssertionPropCallback::EndMerge : BB33 in -> 00000000000410A1 AssertionPropCallback::Unchanged : BB33 out -> 00000000020410A1; jumpDest out -> 00000000010410A1 AssertionPropCallback::StartMerge: BB31 in -> 00000000009492A5 AssertionPropCallback::Merge : BB31 in -> 00000000009492A5, predBlock BB30 out -> 00000000009410A1 AssertionPropCallback::EndMerge : BB31 in -> 00000000009410A1 AssertionPropCallback::Changed : BB31 before out -> 00000000009492A5; after out -> 00000000009410A1; jumpDest before out -> 00000000009492A5; jumpDest after out -> 00000000009410A1; AssertionPropCallback::StartMerge: BB32 in -> 00000000005492A5 AssertionPropCallback::Merge : BB32 in -> 00000000005492A5, predBlock BB30 out -> 00000000009410A1 AssertionPropCallback::EndMerge : BB32 in -> 00000000005410A1 AssertionPropCallback::Changed : BB32 before out -> 00000000005492A5; after out -> 00000000005410A1; jumpDest before out -> 00000000005492A5; jumpDest after out -> 00000000005410A1; AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000810A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 00000000022492A5 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 00000000012492A5 AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000810A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 00000000022492A5 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 00000000012492A5 AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB34 in -> 00000000022492A5 AssertionPropCallback::Merge : BB34 in -> 00000000022492A5, predBlock BB33 out -> 00000000020410A1 AssertionPropCallback::EndMerge : BB34 in -> 00000000020410A1 AssertionPropCallback::Changed : BB34 before out -> 00000000022492A5; after out -> 00000000020410A1; jumpDest before out -> 00000000022492A5; jumpDest after out -> 00000000020410A1; AssertionPropCallback::StartMerge: BB35 in -> 00000000012492A5 AssertionPropCallback::Merge : BB35 in -> 00000000012492A5, predBlock BB33 out -> 00000000020410A1 AssertionPropCallback::EndMerge : BB35 in -> 00000000010410A1 AssertionPropCallback::Changed : BB35 before out -> 00000000012492A5; after out -> 00000000010410A1; jumpDest before out -> 00000000012492A5; jumpDest after out -> 00000000010410A1; AssertionPropCallback::StartMerge: BB33 in -> 00000000000410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB29 out -> 00000000002410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB31 out -> 00000000009410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB32 out -> 00000000005410A1 AssertionPropCallback::EndMerge : BB33 in -> 00000000000410A1 AssertionPropCallback::Unchanged : BB33 out -> 00000000020410A1; jumpDest out -> 00000000010410A1 AssertionPropCallback::StartMerge: BB33 in -> 00000000000410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB29 out -> 00000000002410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB31 out -> 00000000009410A1 AssertionPropCallback::Merge : BB33 in -> 00000000000410A1, predBlock BB32 out -> 00000000005410A1 AssertionPropCallback::EndMerge : BB33 in -> 00000000000410A1 AssertionPropCallback::Unchanged : BB33 out -> 00000000020410A1; jumpDest out -> 00000000010410A1 AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000810A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 00000000020410A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 00000000010410A1 AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB36 in -> 0000000000000001 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB10 out -> 0000000000000041 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB20 out -> 00000000000020A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB27 out -> 00000000000810A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB34 out -> 00000000020410A1 AssertionPropCallback::Merge : BB36 in -> 0000000000000001, predBlock BB35 out -> 00000000010410A1 AssertionPropCallback::EndMerge : BB36 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB36 out -> 0000000000000001; jumpDest out -> 0000000000000001 BB01 valueIn = 0000000000000000 valueOut = 0000000000000000 BB02 valueIn = 0000000003FFFFFF valueOut = 0000000003FFFFFF BB03 valueIn = 0000000000000000 valueOut = 0000000000000001 BB04 valueIn = 0000000000000001 valueOut = 0000000000000005 => BB06 valueOut= 0000000000000003 BB05 valueIn = 0000000000000005 valueOut = 0000000000000005 BB06 valueIn = 0000000000000003 valueOut = 0000000000000013 => BB08 valueOut= 000000000000000B BB07 valueIn = 0000000000000013 valueOut = 0000000000000013 BB08 valueIn = 000000000000000B valueOut = 000000000000000B BB09 valueIn = 0000000000000001 valueOut = 0000000000000041 => BB11 valueOut= 0000000000000021 BB10 valueIn = 0000000000000041 valueOut = 0000000000000041 BB11 valueIn = 0000000000000021 valueOut = 0000000000000021 BB12 valueIn = 0000000003FFFFFF valueOut = 0000000003FFFFFF BB13 valueIn = 0000000000000021 valueOut = 00000000000000A1 BB14 valueIn = 00000000000000A1 valueOut = 00000000000002A1 => BB16 valueOut= 00000000000001A1 BB15 valueIn = 00000000000002A1 valueOut = 00000000000002A1 BB16 valueIn = 00000000000001A1 valueOut = 00000000000009A1 => BB18 valueOut= 00000000000005A1 BB17 valueIn = 00000000000009A1 valueOut = 00000000000009A1 BB18 valueIn = 00000000000005A1 valueOut = 00000000000005A1 BB19 valueIn = 00000000000000A1 valueOut = 00000000000020A1 => BB21 valueOut= 00000000000010A1 BB20 valueIn = 00000000000020A1 valueOut = 00000000000020A1 BB21 valueIn = 00000000000010A1 valueOut = 00000000000090A1 => BB23 valueOut= 00000000000050A1 BB22 valueIn = 00000000000090A1 valueOut = 00000000000090A1 BB23 valueIn = 00000000000050A1 valueOut = 00000000000250A1 => BB25 valueOut= 00000000000150A1 BB24 valueIn = 00000000000250A1 valueOut = 00000000000250A1 BB25 valueIn = 00000000000150A1 valueOut = 00000000000150A1 BB26 valueIn = 00000000000010A1 valueOut = 00000000000810A1 => BB28 valueOut= 00000000000410A1 BB27 valueIn = 00000000000810A1 valueOut = 00000000000810A1 BB28 valueIn = 00000000000410A1 valueOut = 00000000002410A1 => BB30 valueOut= 00000000001410A1 BB29 valueIn = 00000000002410A1 valueOut = 00000000002410A1 BB30 valueIn = 00000000001410A1 valueOut = 00000000009410A1 => BB32 valueOut= 00000000005410A1 BB31 valueIn = 00000000009410A1 valueOut = 00000000009410A1 BB32 valueIn = 00000000005410A1 valueOut = 00000000005410A1 BB33 valueIn = 00000000000410A1 valueOut = 00000000020410A1 => BB35 valueOut= 00000000010410A1 BB34 valueIn = 00000000020410A1 valueOut = 00000000020410A1 BB35 valueIn = 00000000010410A1 valueOut = 00000000010410A1 BB36 valueIn = 0000000000000001 valueOut = 0000000000000001 Propagating 0000000000000000 assertions for BB01, stmt [000171], tree [000168], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000171], tree [000169], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000171], tree [000170], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000923], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000922], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000924], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000926], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000925], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000927], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000215], tree [000928], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000930], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000929], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000931], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000933], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000932], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000934], tree -> 0 Propagating 0000000003FFFFFF assertions for BB02, stmt [000220], tree [000935], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000947], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000948], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000938], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000939], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000940], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt [000187], tree [000941], tree -> 1 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [001452], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000943], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000944], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000945], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000946], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000185], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000187], tree [000186], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000955], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000956], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000953], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000954], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000236], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000237], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000239], tree [000238], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000193], tree [000959], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000193], tree [000962], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000193], tree [000963], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000964], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000255], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000240], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000250], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000251], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000965], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000256], tree [000254], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000268], tree [000188], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000268], tree [000265], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000268], tree [000266], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000273], tree [000970], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000273], tree [000969], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000273], tree [000971], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000279], tree [000276], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000279], tree [000277], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000279], tree [000278], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000973], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000972], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000974], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000976], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000975], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000977], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000204], tree [000978], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000980], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000979], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000981], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000983], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000982], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000984], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000009], tree [000985], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000987], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000986], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000988], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000990], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000989], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000991], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000355], tree [000992], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000995], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000996], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000997], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000998], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000994], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [000999], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001001], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001002], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001003], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001004], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001000], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001005], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000359], tree [001006], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000302], tree [000295], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000302], tree [000393], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000302], tree [000297], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000302], tree [000300], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000302], tree [000301], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000307], tree [000303], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000307], tree [000304], tree -> 0 Propagating 0000000000000001 assertions for BB04, stmt [000307], tree [000305], tree -> 0 Propagating 0000000000000005 assertions for BB05, stmt [000351], tree [000348], tree -> 0 Propagating 0000000000000005 assertions for BB05, stmt [000351], tree [000349], tree -> 0 Propagating 0000000000000005 assertions for BB05, stmt [000351], tree [000350], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000318], tree [000406], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000318], tree [000314], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000318], tree [000315], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000318], tree [000316], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000318], tree [000317], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000323], tree [000319], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000323], tree [000320], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt [000323], tree [000321], tree -> 0 Propagating 0000000000000013 assertions for BB07, stmt [000346], tree [000343], tree -> 0 Propagating 0000000000000013 assertions for BB07, stmt [000346], tree [000344], tree -> 0 Propagating 0000000000000013 assertions for BB07, stmt [000346], tree [000345], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001016], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001015], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001017], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001018], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001019], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001020], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001021], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001022], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001023], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001024], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001025], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001026], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001027], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001028], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001029], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001030], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001031], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001032], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001037], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001036], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001038], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001039], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001040], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001041], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001042], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001043], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001044], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001045], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001046], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001047], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001048], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001049], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001050], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001051], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001052], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001053], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000330], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000333], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001054], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001055], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001057], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001058], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001059], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [001056], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000327], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000334], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000335], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000336], tree -> 0 Propagating 000000000000000B assertions for BB08, stmt [000338], tree [000337], tree -> 0 Propagating 0000000000000001 assertions for BB09, stmt [000029], tree [000025], tree -> 0 Propagating 0000000000000001 assertions for BB09, stmt [000029], tree [000026], tree -> 0 Propagating 0000000000000001 assertions for BB09, stmt [000029], tree [000027], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000160], tree [000156], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000160], tree [000158], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000160], tree [000157], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000160], tree [000159], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000164], tree [000161], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000164], tree [000162], tree -> 0 Propagating 0000000000000041 assertions for BB10, stmt [000164], tree [000163], tree -> 0 Propagating 0000000000000021 assertions for BB11, stmt [000418], tree [000415], tree -> 0 Propagating 0000000000000021 assertions for BB11, stmt [000418], tree [000416], tree -> 0 Propagating 0000000000000021 assertions for BB11, stmt [000418], tree [000417], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001065], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001064], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001066], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001068], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001067], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001069], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000462], tree [001070], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001072], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001071], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001073], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001075], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001074], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001076], tree -> 0 Propagating 0000000003FFFFFF assertions for BB12, stmt [000467], tree [001077], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001089], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001090], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001080], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001081], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001082], tree -> 0 Propagating 0000000000000021 assertions for BB13, stmt [000434], tree [001083], tree -> 8 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [001455], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [001085], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [001086], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [001087], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [001088], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [000432], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000434], tree [000433], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [001097], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [001098], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [001095], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [001096], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [000483], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [000484], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000486], tree [000485], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000440], tree [001101], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000440], tree [001104], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000440], tree [001105], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [001106], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [000502], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [000487], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [000497], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [000498], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [001107], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000503], tree [000501], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000515], tree [000435], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000515], tree [000512], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000515], tree [000513], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000520], tree [001112], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000520], tree [001111], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000520], tree [001113], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000526], tree [000523], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000526], tree [000524], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000526], tree [000525], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001115], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001114], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001116], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001118], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001117], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001119], tree -> 0 Propagating 00000000000000A1 assertions for BB13, stmt [000451], tree [001120], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001122], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001121], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001123], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001125], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001124], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001126], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000039], tree [001127], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001129], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001128], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001130], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001132], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001131], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001133], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000602], tree [001134], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000606], tree [001137], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000606], tree [001138], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000606], tree [001139], tree -> 0 Propagating 00000000000000A1 assertions for BB14, stmt [000606], tree [001140], tree -> 0 Propagating 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00000000000010A1 assertions for BB26, stmt [000089], tree [000087], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000140], tree [000136], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000140], tree [000138], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000140], tree [000137], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000140], tree [000139], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000144], tree [000141], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000144], tree [000142], tree -> 0 Propagating 00000000000810A1 assertions for BB27, stmt [000144], tree [000143], tree -> 0 Propagating 00000000000410A1 assertions for BB28, stmt [000862], tree [001288], tree -> 0 Propagating 00000000000410A1 assertions for BB28, stmt [000862], tree [001287], tree -> 0 Propagating 00000000000410A1 assertions for BB28, stmt [000862], tree [001289], tree -> 0 Propagating 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00000000001410A1 assertions for BB30, stmt [000830], tree [000826], tree -> 0 Propagating 00000000001410A1 assertions for BB30, stmt [000830], tree [000827], tree -> 0 Propagating 00000000001410A1 assertions for BB30, stmt [000830], tree [000828], tree -> 0 Propagating 00000000009410A1 assertions for BB31, stmt [000853], tree [000850], tree -> 0 Propagating 00000000009410A1 assertions for BB31, stmt [000853], tree [000851], tree -> 0 Propagating 00000000009410A1 assertions for BB31, stmt [000853], tree [000852], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001317], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001316], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001318], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001319], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001320], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001321], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001322], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001323], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001324], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001325], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001326], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001327], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001328], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001329], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001330], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001331], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001332], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001333], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001338], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001337], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001339], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001340], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001341], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001342], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001343], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001344], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001345], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001346], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001347], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001348], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001349], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001350], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001351], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001352], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001353], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001354], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000837], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000840], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001355], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001356], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001358], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001359], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001360], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [001357], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000834], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000841], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000842], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000843], tree -> 0 Propagating 00000000005410A1 assertions for BB32, stmt [000845], tree [000844], tree -> 0 Propagating 00000000000410A1 assertions for BB33, stmt [000110], tree [000106], tree -> 0 Propagating 00000000000410A1 assertions for BB33, stmt [000110], tree [000107], tree -> 0 Propagating 00000000000410A1 assertions for BB33, stmt [000110], tree [000108], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000130], tree [000126], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000130], tree [000128], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000130], tree [000127], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000130], tree [000129], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000134], tree [000131], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000134], tree [000132], tree -> 0 Propagating 00000000020410A1 assertions for BB34, stmt [000134], tree [000133], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000116], tree [000112], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000116], tree [000114], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000116], tree [000113], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000116], tree [000115], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000120], tree [000117], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000120], tree [000118], tree -> 0 Propagating 00000000010410A1 assertions for BB35, stmt [000120], tree [000119], tree -> 0 Propagating 0000000000000001 assertions for BB36, stmt [000124], tree [000122], tree -> 0 Propagating 0000000000000001 assertions for BB36, stmt [000124], tree [000123], tree -> 0 *************** In fgDebugCheckBBlist *************** In OptimizeRangeChecks() Blocks/trees before phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 (always) i label target BB02 [0011] 0 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 (always) i label target BB12 [0029] 0 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB03 (always), preds={} succs={BB03} ***** BB01, stmt 1 ( 1, 3) [000171] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000168] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000170] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 ------------ BB02 [001..002) -> BB04 (always), preds={} succs={BB04} ***** BB02, stmt 2 ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 $40 N007 ( 10, 8) [000928] -A---------- \--* COMMA void $40 N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [000924] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 $VN.Null ***** BB02, stmt 3 ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) $40 N006 ( 7, 5) [000934] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 $40 N007 ( 14, 10) [000935] -A---------- \--* COMMA void $40 N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) $VN.Null N003 ( 7, 5) [000931] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 $VN.Null ------------ BB03 [001..002), preds={BB01} succs={BB04} ***** BB03, stmt 4 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [001452] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null ***** BB03, stmt 5 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [000956] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB03, stmt 6 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void $341 N003 ( 0, 0) [000963] ------------ \--* COMMA void $341 N001 ( 0, 0) [000959] ------------ \--* NOP void $340 ***** BB03, stmt 7 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB03, stmt 8 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null N003 ( 7, 5) [000266] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 $VN.Null ***** BB03, stmt 9 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null N003 ( 7, 5) [000971] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 $VN.Null ***** BB03, stmt 10 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB03, stmt 11 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null N003 ( 7, 5) [000974] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 $VN.Null ------------ BB04 [001..00D) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04, stmt 12 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB04, stmt 13 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 $VN.Null N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB04, stmt 14 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) $3c0 N006 ( 7, 5) [000984] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 $3c0 N007 ( 14, 10) [000985] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null N003 ( 7, 5) [000981] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 $VN.Null ***** BB04, stmt 15 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 $3c0 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int $3c0 N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 $3c0 N007 ( 10, 8) [000992] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [000988] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 $VN.Null ***** BB04, stmt 16 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB04, stmt 17 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V62 tmp53 u:3 $3c0 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB04, stmt 18 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB04} succs={BB09} ***** BB05, stmt 19 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 $40 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB04} succs={BB07,BB08} ***** BB06, stmt 20 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 $40 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 21 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 22 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool $41 N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 $41 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 23 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 $40 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int $30d N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref $404 N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref $403 N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 $2ca N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref $2ca N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $480 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref $2ca N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 $2ca N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref $407 N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref $406 N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 $2cc N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref $2cc N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $481 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref $2cc N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 $2cc N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref $2ce N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $482 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref $2cf N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $483 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool $30d N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 $30d ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 24 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 $30d N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 25 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000027] J------N---- \--* EQ int $30e N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) $500 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 26 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000158] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB10, stmt 27 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000163] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 $41 ------------ BB11 [01F..037) -> BB13 (always), preds={BB09} succs={BB13} ***** BB11, stmt 28 ( 5, 4) [000418] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000415] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000417] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 ------------ BB12 [01F..020) -> BB14 (always), preds={} succs={BB14} ***** BB12, stmt 29 ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 $40 N007 ( 10, 8) [001070] -A---------- \--* COMMA void $40 N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [001066] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 $VN.Null ***** BB12, stmt 30 ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) $40 N006 ( 7, 5) [001076] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 $40 N007 ( 14, 10) [001077] -A---------- \--* COMMA void $40 N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001073] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 $VN.Null ------------ BB13 [01F..020), preds={BB11} succs={BB14} ***** BB13, stmt 31 ( 12, 18) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 3, 3) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 1, 1) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 8, 15) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 2, 2) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 1, 1) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 5, 12) [001455] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 3, 10) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 1, 1) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 12, 18) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null ***** BB13, stmt 32 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [001098] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB13, stmt 33 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void $343 N003 ( 0, 0) [001105] ------------ \--* COMMA void $343 N001 ( 0, 0) [001101] ------------ \--* NOP void $342 ***** BB13, stmt 34 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB13, stmt 35 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [000513] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 $VN.Null ***** BB13, stmt 36 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001113] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 $VN.Null ***** BB13, stmt 37 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB13, stmt 38 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001116] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 $VN.Null ------------ BB14 [01F..02B) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14, stmt 39 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB14, stmt 40 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 $VN.Null N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB14, stmt 41 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) $3c2 N006 ( 7, 5) [001126] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 $3c2 N007 ( 14, 10) [001127] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001123] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 $VN.Null ***** BB14, stmt 42 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 $3c2 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 $3c2 N007 ( 14, 10) [001134] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [001130] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 $VN.Null ***** BB14, stmt 43 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB14, stmt 44 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V64 tmp55 u:3 $3c2 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB14, stmt 45 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB14} succs={BB19} ***** BB15, stmt 46 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 $40 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB14} succs={BB17,BB18} ***** BB16, stmt 47 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 48 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 49 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 $41 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 50 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int $31e N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref $409 N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) $2da N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref $408 N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 $2da N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref $2da N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $484 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref $2da N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 $2da N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref $40b N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref $40a N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 $2dc N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref $2dc N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $485 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref $2dc N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 $2dc N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref $2de N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $486 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref $2df N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $487 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool $31e N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 $31e ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 51 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 $41 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 52 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000057] J------N---- \--* EQ int $31f N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) $501 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 53 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000148] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB20, stmt 54 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000153] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 $41 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 55 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 $80 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref $80 N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 $80 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) $VN.Void N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref $2e1 N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 $489 ***** BB21, stmt 56 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N006 ( 7, 5) [001217] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 $3c0 N007 ( 14, 10) [001218] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001214] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 $VN.Null ***** BB21, stmt 57 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 58 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 $3c0 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 59 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 60 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 $40 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 61 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 62 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 63 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 $41 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 64 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int $328 N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) $3c0 N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref $40d N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref $40c N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 $2e5 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref $2e5 N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48a N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref $2e5 N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 $2e5 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref $40f N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref $40e N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 $2e7 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref $2e7 N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48b N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref $2e7 N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 $2e7 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref $2e9 N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $48c N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref $2ea N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $48d N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool $328 N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 $328 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 65 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 $328 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 66 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000087] J------N---- \--* EQ int $329 N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) $502 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 67 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000138] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB27, stmt 68 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000143] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 $41 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 69 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N006 ( 7, 5) [001292] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 $3c2 N007 ( 14, 10) [001293] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001289] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 $VN.Null ***** BB28, stmt 70 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 71 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 $3c2 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 72 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 73 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 $40 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 74 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 75 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 76 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 $41 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 77 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int $332 N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) $3c2 N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref $411 N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref $410 N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 $2ee N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref $2ee N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48e N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref $2ee N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 $2ee N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref $413 N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref $412 N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 $2f0 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref $2f0 N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48f N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref $2f0 N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 $2f0 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref $2f2 N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $490 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref $2f3 N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $491 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool $332 N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 $332 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 78 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 $332 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 79 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000108] J------N---- \--* EQ int $333 N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) $503 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 80 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000128] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB34, stmt 81 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000133] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 $41 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 82 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000114] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB35, stmt 83 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000119] -A------R--- \--* ASG int $40 N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 $40 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 84 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 $40 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 85 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int $1fb N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) $504 ------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB03 (always) i label target BB02 [0011] 0 0.25 [001..002)-> BB04 (always) i BB03 [0012] 1 BB01 0.25 [001..002) i label target gcsafe BB04 [0013] 2 BB02,BB03 1 [001..00D)-> BB06 ( cond ) i label target BB05 [0019] 1 BB04 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB04 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB13 (always) i label target BB12 [0029] 0 0.25 [01F..020)-> BB14 (always) i BB13 [0030] 1 BB11 0.25 [01F..020) i label target gcsafe BB14 [0031] 2 BB12,BB13 0.50 [01F..02B)-> BB16 ( cond ) i label target BB15 [0037] 1 BB14 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB14 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- fgRemoveBlock BB02 Removing unreachable BB02 Removing statement [000215] in BB02 as useless: ( 10, 8) [000215] ------------ * STMT void (IL 0x001... ???) N004 ( 1, 1) [000926] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [000927] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000925] D------N---- | | \--* LCL_VAR int V70 tmp61 d:3 $40 N007 ( 10, 8) [000928] -A---------- \--* COMMA void $40 N001 ( 1, 1) [000923] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [000924] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000922] D------N---- \--* LCL_VAR byref V69 tmp60 d:3 $VN.Null New refCnts for V69: refCnt = 1, refCntWtd = 0.25 New refCnts for V70: refCnt = 1, refCntWtd = 0.25 Removing statement [000220] in BB02 as useless: ( 14, 10) [000220] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000933] -------N---- | /--* LCL_VAR int V70 tmp61 u:3 (last use) $40 N006 ( 7, 5) [000934] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [000932] D------N---- | | \--* LCL_VAR int V68 tmp59 d:5 $40 N007 ( 14, 10) [000935] -A---------- \--* COMMA void $40 N001 ( 3, 2) [000930] -------N---- | /--* LCL_VAR byref V69 tmp60 u:3 (last use) $VN.Null N003 ( 7, 5) [000931] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000929] D------N---- \--* LCL_VAR byref V67 tmp58 d:5 $VN.Null New refCnts for V67: refCnt = 2, refCntWtd = 1.25 New refCnts for V69: refCnt = 0, refCntWtd = 0 New refCnts for V68: refCnt = 2, refCntWtd = 1.25 New refCnts for V70: refCnt = 0, refCntWtd = 0 BB02 becomes empty Compacting blocks BB03 and BB04: *************** In fgDebugCheckBBlist fgRemoveBlock BB12 Removing unreachable BB12 Removing statement [000462] in BB12 as useless: ( 10, 8) [000462] ------------ * STMT void (IL 0x01F... ???) N004 ( 1, 1) [001068] ------------ | /--* CNS_INT int 0 $40 N006 ( 5, 4) [001069] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001067] D------N---- | | \--* LCL_VAR int V81 tmp72 d:3 $40 N007 ( 10, 8) [001070] -A---------- \--* COMMA void $40 N001 ( 1, 1) [001065] ------------ | /--* CNS_INT byref 0 $VN.Null N003 ( 5, 4) [001066] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001064] D------N---- \--* LCL_VAR byref V80 tmp71 d:3 $VN.Null New refCnts for V80: refCnt = 0, refCntWtd = 0 New refCnts for V81: refCnt = 1, refCntWtd = 0.25 Removing statement [000467] in BB12 as useless: ( 14, 10) [000467] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001075] -------N---- | /--* LCL_VAR int V81 tmp72 u:3 (last use) $40 N006 ( 7, 5) [001076] -A------R--- | /--* ASG int $40 N005 ( 3, 2) [001074] D------N---- | | \--* LCL_VAR int V79 tmp70 d:5 $40 N007 ( 14, 10) [001077] -A---------- \--* COMMA void $40 N001 ( 3, 2) [001072] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001073] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001071] D------N---- \--* LCL_VAR byref V78 tmp69 d:5 $VN.Null New refCnts for V78: refCnt = 1, refCntWtd = 0.25 New refCnts for V61: refCnt = 9, refCntWtd = 4.25 New refCnts for V79: refCnt = 2, refCntWtd = 0.75 New refCnts for V81: refCnt = 0, refCntWtd = 0 BB12 becomes empty Compacting blocks BB13 and BB14: *************** In fgDebugCheckBBlist Compacting blocks BB01 and BB03: *************** In fgDebugCheckBBlist Compacting blocks BB11 and BB13: *************** In fgDebugCheckBBlist After updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgComputeEdgeWeights() fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** In IR Rationalize Trees before IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB01, stmt 1 ( 6, 5) [001399] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001397] ------------ | * PHI int N001 ( 0, 0) [001446] ------------ | /--* PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ | \--* PHI_ARG int V68 tmp59 u:4 N007 ( 6, 5) [001398] -A------R--- \--* ASG int N006 ( 3, 2) [001396] D------N---- \--* LCL_VAR int V68 tmp59 d:3 ***** BB01, stmt 2 ( 6, 5) [001395] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001393] ------------ | * PHI byref N001 ( 0, 0) [001448] ------------ | /--* PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ | \--* PHI_ARG byref V67 tmp58 u:4 $VN.Null N007 ( 6, 5) [001394] -A------R--- \--* ASG byref N006 ( 3, 2) [001392] D------N---- \--* LCL_VAR byref V67 tmp58 d:3 ***** BB01, stmt 3 ( 1, 3) [000171] ------------ * STMT void (IL 0x001... ???) N001 ( 1, 1) [000168] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000170] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000169] D------N---- \--* LCL_VAR int V09 tmp0 d:3 $40 ***** BB01, stmt 4 ( 20, 23) [000187] ------------ * STMT void (IL 0x001... ???) N009 ( 1, 1) [000944] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 5, 4) [000945] ------------ | /--* ADD byref $VN.Null N008 ( 3, 2) [000943] ------------ | | \--* LCL_VAR ref V96 tmp87 u:4 (last use) $180 N011 ( 16, 20) [000946] -A-XG--N---- | /--* COMMA byref $242 N006 ( 4, 3) [000941] ---X---N---- | | | /--* NULLCHECK byte $241 N005 ( 3, 2) [000940] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:4 $180 N007 ( 11, 16) [001452] -A-X-------- | | \--* COMMA void $241 N002 ( 3, 10) [000948] ------------ | | | /--* NOP ref $180 N001 ( 3, 10) [000947] ------------ | | | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N004 ( 7, 13) [000939] -A------R--- | | \--* ASG ref $180 N003 ( 3, 2) [000938] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:4 $180 N013 ( 20, 23) [000186] -A-XG---R--- \--* ASG byref $242 N012 ( 3, 2) [000185] D------N---- \--* LCL_VAR byref V10 tmp1 d:3 $VN.Null ***** BB01, stmt 5 ( 10, 16) [000239] ------------ * STMT void (IL 0x001... ???) N005 ( 6, 13) [000236] x---G------- | /--* IND int N003 ( 1, 1) [000953] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [000954] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [000956] ------------ | | \--* NOP ref $180 N001 ( 3, 10) [000955] ------------ | | \--* CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N007 ( 10, 16) [000238] -A--G---R--- \--* ASG int N006 ( 3, 2) [000237] D------N---- \--* LCL_VAR int V14 tmp5 d:3 ***** BB01, stmt 6 ( 0, 0) [000193] ------------ * STMT void (IL 0x001... ???) N002 ( 0, 0) [000962] ------------ | /--* NOP void $341 N003 ( 0, 0) [000963] ------------ \--* COMMA void $341 N001 ( 0, 0) [000959] ------------ \--* NOP void $340 ***** BB01, stmt 7 ( 22, 10) [000256] ------------ * STMT void (IL 0x001... ???) N007 ( 22, 10) [000254] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000250] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000251] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000240] ------------ \--* LCL_VAR int V14 tmp5 u:3 ***** BB01, stmt 8 ( 7, 5) [000268] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000188] ------------ | /--* LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null N003 ( 7, 5) [000266] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000265] D------N---- \--* LCL_VAR byref V71 tmp62 d:3 $VN.Null ***** BB01, stmt 9 ( 7, 5) [000273] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000970] -------N---- | /--* LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null N003 ( 7, 5) [000971] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000969] D------N---- \--* LCL_VAR byref V65 tmp56 d:3 $VN.Null ***** BB01, stmt 10 ( 7, 5) [000279] ------------ * STMT void (IL 0x001... ???) N001 ( 3, 2) [000276] ------------ | /--* LCL_VAR int V14 tmp5 u:3 (last use) N003 ( 7, 5) [000278] -A------R--- \--* ASG int N002 ( 3, 2) [000277] D------N---- \--* LCL_VAR int V66 tmp57 d:3 ***** BB01, stmt 11 ( 14, 10) [000204] ------------ * STMT void (IL 0x001... ???) N004 ( 3, 2) [000976] -------N---- | /--* LCL_VAR int V66 tmp57 u:3 (last use) N006 ( 7, 5) [000977] -A------R--- | /--* ASG int N005 ( 3, 2) [000975] D------N---- | | \--* LCL_VAR int V68 tmp59 d:4 N007 ( 14, 10) [000978] -A---------- \--* COMMA void N001 ( 3, 2) [000973] -------N---- | /--* LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null N003 ( 7, 5) [000974] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000972] D------N---- \--* LCL_VAR byref V67 tmp58 d:4 $VN.Null ***** BB01, stmt 12 ( 14, 10) [000009] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [000983] -------N---- | /--* LCL_VAR int V68 tmp59 u:3 (last use) $3c0 N006 ( 7, 5) [000984] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [000982] D------N---- | | \--* LCL_VAR int V62 tmp53 d:3 $3c0 N007 ( 14, 10) [000985] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000980] -------N---- | /--* LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null N003 ( 7, 5) [000981] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000979] D------N---- \--* LCL_VAR byref V61 tmp52 d:3 $VN.Null ***** BB01, stmt 13 ( 10, 8) [000355] ------------ * STMT void (IL 0x00C... ???) N004 ( 3, 2) [000990] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 $3c0 N006 ( 3, 3) [000991] -A------R--- | /--* ASG int $3c0 N005 ( 1, 1) [000989] D------N---- | | \--* LCL_VAR int V73 tmp64 d:3 $3c0 N007 ( 10, 8) [000992] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [000987] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [000988] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000986] D------N---- \--* LCL_VAR byref V72 tmp63 d:3 $VN.Null ***** BB01, stmt 14 ( 12, 10) [000359] ------------ * STMT void (IL 0x00C... ???) N010 ( 4, 4) [001004] x----------- | /--* IND int N008 ( 1, 1) [001002] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001003] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001001] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 4, 4) [001005] -A------R--- | /--* ASG int N011 ( 1, 1) [001000] D------N---- | | \--* LCL_VAR int V75 tmp66 d:3 N013 ( 12, 10) [001006] -A---------- \--* COMMA void N004 ( 4, 3) [000998] x----------- | /--* IND byref N002 ( 1, 1) [000996] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [000997] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [000995] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [000999] -A------R--- \--* ASG byref N005 ( 3, 2) [000994] D------N---- \--* LCL_VAR byref V74 tmp65 d:3 ***** BB01, stmt 15 ( 6, 3) [000302] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000393] ------------ | /--* LCL_VAR int V75 tmp66 u:3 N003 ( 6, 3) [000297] ------------ | /--* NE int N001 ( 1, 1) [000295] ------------ | | \--* LCL_VAR int V62 tmp53 u:3 $3c0 N005 ( 6, 3) [000301] -A------R--- \--* ASG bool N004 ( 1, 1) [000300] D------N---- \--* LCL_VAR int V19 tmp10 d:3 ***** BB01, stmt 16 ( 5, 5) [000307] ------------ * STMT void (IL 0x00C... ???) N004 ( 5, 5) [000306] ------------ \--* JTRUE void N002 ( 1, 1) [000304] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000305] J------N---- \--* EQ int N001 ( 1, 1) [000303] ------------ \--* LCL_VAR int V19 tmp10 u:3 (last use) ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ***** BB05, stmt 17 ( 1, 3) [000351] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000348] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000350] -A------R--- \--* ASG bool $40 N002 ( 1, 1) [000349] D------N---- \--* LCL_VAR int V21 tmp12 d:5 $40 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ***** BB06, stmt 18 ( 10, 6) [000318] ------------ * STMT void (IL 0x00C... ???) N002 ( 1, 1) [000314] ------------ | /--* CNS_INT int 0 $40 N003 ( 6, 3) [000315] ------------ | /--* EQ int N001 ( 1, 1) [000406] ------------ | | \--* LCL_VAR int V75 tmp66 u:3 N005 ( 10, 6) [000317] -A------R--- \--* ASG bool N004 ( 3, 2) [000316] D------N---- \--* LCL_VAR int V20 tmp11 d:3 ***** BB06, stmt 19 ( 7, 6) [000323] ------------ * STMT void (IL 0x00C... ???) N004 ( 7, 6) [000322] ------------ \--* JTRUE void N002 ( 1, 1) [000320] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000321] J------N---- \--* EQ int N001 ( 3, 2) [000319] ------------ \--* LCL_VAR int V20 tmp11 u:3 (last use) ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ***** BB07, stmt 20 ( 1, 3) [000346] ------------ * STMT void (IL 0x00C... ???) N001 ( 1, 1) [000343] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000345] -A------R--- \--* ASG bool $41 N002 ( 1, 1) [000344] D------N---- \--* LCL_VAR int V21 tmp12 d:4 $41 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ***** BB08, stmt 21 ( 81, 55) [000338] ------------ * STMT void (IL 0x00C... ???) N046 ( 1, 1) [000334] ------------ | /--* CNS_INT int 0 $40 N047 ( 81, 55) [000335] -ACXG------- | /--* EQ int $30d N045 ( 76, 53) [000327] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N016 ( 1, 1) [001030] -------N---- | | | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N017 ( 8, 7) [001031] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001029] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001027] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001028] -------N---- | | | | \--* ADD byref $404 N012 ( 3, 2) [001026] ------------ | | | | \--* LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N018 ( 25, 20) [001032] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001023] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001024] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001022] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001020] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001021] -------N---- | | | | | \--* ADD byref $403 N005 ( 3, 2) [001019] ------------ | | | | | \--* LCL_VAR byref V98 tmp89 u:3 $2ca N011 ( 17, 13) [001025] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001015] L----------- | | | | /--* ADDR byref $2ca N001 ( 3, 2) [001016] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $480 N004 ( 7, 6) [001018] -A------R--- | | | \--* ASG byref $2ca N003 ( 3, 2) [001017] D------N---- | | | \--* LCL_VAR byref V98 tmp89 d:3 $2ca N034 ( 1, 1) [001051] -------N---- | | | /--* LCL_VAR int V75 tmp66 u:3 (last use) N035 ( 8, 7) [001052] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001050] *------N---- | | | | \--* IND int N031 ( 1, 1) [001048] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001049] -------N---- | | | | \--* ADD byref $407 N030 ( 3, 2) [001047] ------------ | | | | \--* LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N036 ( 25, 20) [001053] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001044] -------N---- | | | | /--* LCL_VAR byref V74 tmp65 u:3 (last use) N028 ( 10, 7) [001045] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001043] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001041] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001042] -------N---- | | | | | \--* ADD byref $406 N023 ( 3, 2) [001040] ------------ | | | | | \--* LCL_VAR byref V100 tmp91 u:3 $2cc N029 ( 17, 13) [001046] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001036] L----------- | | | | /--* ADDR byref $2cc N019 ( 3, 2) [001037] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $481 N022 ( 7, 6) [001039] -A------R--- | | | \--* ASG byref $2cc N021 ( 3, 2) [001038] D------N---- | | | \--* LCL_VAR byref V100 tmp91 d:3 $2cc N040 ( 3, 3) [001055] L----------- arg0 in rcx | | +--* ADDR byref $2ce N039 ( 3, 2) [001054] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $482 N042 ( 3, 3) [001058] L----------- arg1 in rdx | | \--* ADDR byref $2cf N041 ( 3, 2) [001057] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $483 N049 ( 81, 55) [000337] -ACXG---R--- \--* ASG bool $30d N048 ( 1, 1) [000336] D------N---- \--* LCL_VAR int V21 tmp12 d:3 $30d ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ***** BB09, stmt 22 ( 8, 7) [001391] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001389] ------------ | * PHI bool N001 ( 0, 0) [001404] ------------ | /--* PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ | +--* PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ | \--* PHI_ARG bool V21 tmp12 u:3 $30d N009 ( 8, 7) [001390] -A------R--- \--* ASG bool N008 ( 4, 3) [001388] D------N---- \--* LCL_VAR bool V21 tmp12 d:6 ***** BB09, stmt 23 ( 5, 5) [000029] ------------ * STMT void (IL 0x014...0x015) N004 ( 5, 5) [000028] ------------ \--* JTRUE void N002 ( 1, 1) [000026] ------------ | /--* CNS_INT int 0 $40 N003 ( 3, 3) [000027] J------N---- \--* EQ int $30e N001 ( 1, 1) [000025] ------------ \--* LCL_VAR int V21 tmp12 u:6 (last use) $500 ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ***** BB10, stmt 24 ( 6, 5) [000160] ------------ * STMT void (IL 0x018...0x01A) N003 ( 1, 1) [000157] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000159] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000158] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000156] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB10, stmt 25 ( 1, 3) [000164] ------------ * STMT void (IL 0x01B...0x01C) N001 ( 1, 1) [000161] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000163] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000162] D------N---- \--* LCL_VAR int V05 loc3 d:7 $41 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} ***** BB11, stmt 26 ( 6, 5) [001387] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001385] ------------ | * PHI int N001 ( 0, 0) [001436] ------------ | /--* PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ | \--* PHI_ARG int V79 tmp70 u:4 N007 ( 6, 5) [001386] -A------R--- \--* ASG int N006 ( 3, 2) [001384] D------N---- \--* LCL_VAR int V79 tmp70 d:3 ***** BB11, stmt 27 ( 6, 5) [001383] ------------ * STMT void (IL ???... ???) N005 ( 2, 2) [001381] ------------ | * PHI byref N001 ( 0, 0) [001438] ------------ | /--* PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ | \--* PHI_ARG byref V78 tmp69 u:4 $VN.Null N007 ( 6, 5) [001382] -A------R--- \--* ASG byref N006 ( 3, 2) [001380] D------N---- \--* LCL_VAR byref V78 tmp69 d:3 ***** BB11, stmt 28 ( 5, 4) [000418] ------------ * STMT void (IL 0x01F... ???) N001 ( 1, 1) [000415] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000417] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000416] D------N---- \--* LCL_VAR int V25 tmp16 d:3 $40 ***** BB11, stmt 29 ( 12, 18) [000434] ------------ * STMT void (IL 0x01F... ???) N009 ( 1, 1) [001086] ------------ | /--* CNS_INT long 12 field offset Fseq[_firstChar] $280 N010 ( 3, 3) [001087] ------------ | /--* ADD byref $VN.Null N008 ( 1, 1) [001085] ------------ | | \--* LCL_VAR ref V96 tmp87 u:3 (last use) $184 N011 ( 8, 15) [001088] -A-XG--N---- | /--* COMMA byref $24d N006 ( 2, 2) [001083] ---X---N---- | | | /--* NULLCHECK byte $24c N005 ( 1, 1) [001082] ------------ | | | | \--* LCL_VAR ref V96 tmp87 u:3 $184 N007 ( 5, 12) [001455] -A-X-------- | | \--* COMMA void $24c N002 ( 3, 10) [001090] ------------ | | | /--* NOP ref $184 N001 ( 3, 10) [001089] ------------ | | | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N004 ( 3, 10) [001081] -A------R--- | | \--* ASG ref $184 N003 ( 1, 1) [001080] D------N---- | | \--* LCL_VAR ref V96 tmp87 d:3 $184 N013 ( 12, 18) [000433] -A-XG---R--- \--* ASG byref $24d N012 ( 3, 2) [000432] D------N---- \--* LCL_VAR byref V26 tmp17 d:3 $VN.Null ***** BB11, stmt 30 ( 10, 16) [000486] ------------ * STMT void (IL 0x01F... ???) N005 ( 6, 13) [000483] x---G------- | /--* IND int N003 ( 1, 1) [001095] ------------ | | | /--* CNS_INT long 8 field offset Fseq[_stringLength] $281 N004 ( 4, 11) [001096] -------N---- | | \--* ADD byref $VN.Null N002 ( 3, 10) [001098] ------------ | | \--* NOP ref $184 N001 ( 3, 10) [001097] ------------ | | \--* CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N007 ( 10, 16) [000485] -A--G---R--- \--* ASG int N006 ( 3, 2) [000484] D------N---- \--* LCL_VAR int V30 tmp21 d:3 ***** BB11, stmt 31 ( 0, 0) [000440] ------------ * STMT void (IL 0x01F... ???) N002 ( 0, 0) [001104] ------------ | /--* NOP void $343 N003 ( 0, 0) [001105] ------------ \--* COMMA void $343 N001 ( 0, 0) [001101] ------------ \--* NOP void $342 ***** BB11, stmt 32 ( 22, 10) [000503] ------------ * STMT void (IL 0x01F... ???) N007 ( 22, 10) [000501] --CXG------- \--* CALL void System.Diagnostics.Debug.Assert $VN.Void N004 ( 1, 1) [000497] ------------ | /--* CNS_INT int 0 $40 N005 ( 8, 4) [000498] ------------ arg0 in rcx \--* GE int N003 ( 3, 2) [000487] ------------ \--* LCL_VAR int V30 tmp21 u:3 ***** BB11, stmt 33 ( 7, 5) [000515] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000435] ------------ | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [000513] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [000512] D------N---- \--* LCL_VAR byref V82 tmp73 d:3 $VN.Null ***** BB11, stmt 34 ( 7, 5) [000520] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [001112] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001113] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001111] D------N---- \--* LCL_VAR byref V76 tmp67 d:3 $VN.Null ***** BB11, stmt 35 ( 7, 5) [000526] ------------ * STMT void (IL 0x01F... ???) N001 ( 3, 2) [000523] ------------ | /--* LCL_VAR int V30 tmp21 u:3 (last use) N003 ( 7, 5) [000525] -A------R--- \--* ASG int N002 ( 3, 2) [000524] D------N---- \--* LCL_VAR int V77 tmp68 d:3 ***** BB11, stmt 36 ( 14, 10) [000451] ------------ * STMT void (IL 0x01F... ???) N004 ( 3, 2) [001118] -------N---- | /--* LCL_VAR int V77 tmp68 u:3 (last use) N006 ( 7, 5) [001119] -A------R--- | /--* ASG int N005 ( 3, 2) [001117] D------N---- | | \--* LCL_VAR int V79 tmp70 d:4 N007 ( 14, 10) [001120] -A---------- \--* COMMA void N001 ( 3, 2) [001115] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001116] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001114] D------N---- \--* LCL_VAR byref V78 tmp69 d:4 $VN.Null ***** BB11, stmt 37 ( 14, 10) [000039] ------------ * STMT void (IL ???... ???) N004 ( 3, 2) [001125] -------N---- | /--* LCL_VAR int V79 tmp70 u:3 (last use) $3c2 N006 ( 7, 5) [001126] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001124] D------N---- | | \--* LCL_VAR int V64 tmp55 d:3 $3c2 N007 ( 14, 10) [001127] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001122] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N003 ( 7, 5) [001123] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001121] D------N---- \--* LCL_VAR byref V63 tmp54 d:3 $VN.Null ***** BB11, stmt 38 ( 14, 10) [000602] ------------ * STMT void (IL 0x02A... ???) N004 ( 3, 2) [001132] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 $3c2 N006 ( 7, 5) [001133] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001131] D------N---- | | \--* LCL_VAR int V84 tmp75 d:3 $3c2 N007 ( 14, 10) [001134] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001129] -------N---- | /--* LCL_VAR byref V61 tmp52 u:3 $VN.Null N003 ( 7, 5) [001130] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001128] D------N---- \--* LCL_VAR byref V83 tmp74 d:3 $VN.Null ***** BB11, stmt 39 ( 16, 13) [000606] ------------ * STMT void (IL 0x02A... ???) N010 ( 4, 4) [001146] x----------- | /--* IND int N008 ( 1, 1) [001144] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001145] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001143] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001147] -A------R--- | /--* ASG int N011 ( 3, 2) [001142] D------N---- | | \--* LCL_VAR int V86 tmp77 d:3 N013 ( 16, 13) [001148] -A---------- \--* COMMA void N004 ( 4, 3) [001140] x----------- | /--* IND byref N002 ( 1, 1) [001138] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001139] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001137] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001141] -A------R--- \--* ASG byref N005 ( 3, 2) [001136] D------N---- \--* LCL_VAR byref V85 tmp76 d:3 ***** BB11, stmt 40 ( 14, 8) [000549] ------------ * STMT void (IL 0x02A... ???) N002 ( 3, 2) [000640] ------------ | /--* LCL_VAR int V86 tmp77 u:3 N003 ( 10, 5) [000544] ------------ | /--* NE int N001 ( 3, 2) [000542] ------------ | | \--* LCL_VAR int V64 tmp55 u:3 $3c2 N005 ( 14, 8) [000548] -A------R--- \--* ASG bool N004 ( 3, 2) [000547] D------N---- \--* LCL_VAR int V35 tmp26 d:3 ***** BB11, stmt 41 ( 7, 6) [000554] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000553] ------------ \--* JTRUE void N002 ( 1, 1) [000551] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000552] J------N---- \--* EQ int N001 ( 3, 2) [000550] ------------ \--* LCL_VAR int V35 tmp26 u:3 (last use) ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ***** BB15, stmt 42 ( 5, 4) [000598] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000595] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000597] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000596] D------N---- \--* LCL_VAR int V37 tmp28 d:5 $40 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ***** BB16, stmt 43 ( 12, 7) [000565] ------------ * STMT void (IL 0x02A... ???) N002 ( 1, 1) [000561] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000562] ------------ | /--* EQ int N001 ( 3, 2) [000653] ------------ | | \--* LCL_VAR int V86 tmp77 u:3 N005 ( 12, 7) [000564] -A------R--- \--* ASG bool N004 ( 3, 2) [000563] D------N---- \--* LCL_VAR int V36 tmp27 d:3 ***** BB16, stmt 44 ( 7, 6) [000570] ------------ * STMT void (IL 0x02A... ???) N004 ( 7, 6) [000569] ------------ \--* JTRUE void N002 ( 1, 1) [000567] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000568] J------N---- \--* EQ int N001 ( 3, 2) [000566] ------------ \--* LCL_VAR int V36 tmp27 u:3 (last use) ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ***** BB17, stmt 45 ( 5, 4) [000593] ------------ * STMT void (IL 0x02A... ???) N001 ( 1, 1) [000590] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000592] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000591] D------N---- \--* LCL_VAR int V37 tmp28 d:3 $41 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ***** BB18, stmt 46 ( 89, 60) [000585] ------------ * STMT void (IL 0x02A... ???) N046 ( 1, 1) [000581] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000582] -ACXG------- | /--* EQ int $31e N045 ( 80, 55) [000574] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N016 ( 3, 2) [001172] -------N---- | | | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N017 ( 10, 8) [001173] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001171] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001169] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001170] -------N---- | | | | \--* ADD byref $409 N012 ( 3, 2) [001168] ------------ | | | | \--* LCL_VAR byref V101 tmp92 u:3 (last use) $2da N018 ( 27, 21) [001174] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001165] -------N---- | | | | /--* LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null N010 ( 10, 7) [001166] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001164] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001162] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001163] -------N---- | | | | | \--* ADD byref $408 N005 ( 3, 2) [001161] ------------ | | | | | \--* LCL_VAR byref V101 tmp92 u:3 $2da N011 ( 17, 13) [001167] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001157] L----------- | | | | /--* ADDR byref $2da N001 ( 3, 2) [001158] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $484 N004 ( 7, 6) [001160] -A------R--- | | | \--* ASG byref $2da N003 ( 3, 2) [001159] D------N---- | | | \--* LCL_VAR byref V101 tmp92 d:3 $2da N034 ( 3, 2) [001193] -------N---- | | | /--* LCL_VAR int V86 tmp77 u:3 (last use) N035 ( 10, 8) [001194] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001192] *------N---- | | | | \--* IND int N031 ( 1, 1) [001190] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001191] -------N---- | | | | \--* ADD byref $40b N030 ( 3, 2) [001189] ------------ | | | | \--* LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N036 ( 27, 21) [001195] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001186] -------N---- | | | | /--* LCL_VAR byref V85 tmp76 u:3 (last use) N028 ( 10, 7) [001187] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001185] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001183] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001184] -------N---- | | | | | \--* ADD byref $40a N023 ( 3, 2) [001182] ------------ | | | | | \--* LCL_VAR byref V102 tmp93 u:3 $2dc N029 ( 17, 13) [001188] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001178] L----------- | | | | /--* ADDR byref $2dc N019 ( 3, 2) [001179] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $485 N022 ( 7, 6) [001181] -A------R--- | | | \--* ASG byref $2dc N021 ( 3, 2) [001180] D------N---- | | | \--* LCL_VAR byref V102 tmp93 d:3 $2dc N040 ( 3, 3) [001197] L----------- arg0 in rcx | | +--* ADDR byref $2de N039 ( 3, 2) [001196] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $486 N042 ( 3, 3) [001200] L----------- arg1 in rdx | | \--* ADDR byref $2df N041 ( 3, 2) [001199] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $487 N049 ( 89, 60) [000584] -ACXG---R--- \--* ASG bool $31e N048 ( 3, 2) [000583] D------N---- \--* LCL_VAR int V37 tmp28 d:4 $31e ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ***** BB19, stmt 47 ( 8, 7) [001379] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001377] ------------ | * PHI bool N001 ( 0, 0) [001410] ------------ | /--* PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ | +--* PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ | \--* PHI_ARG bool V37 tmp28 u:3 $41 N009 ( 8, 7) [001378] -A------R--- \--* ASG bool N008 ( 4, 3) [001376] D------N---- \--* LCL_VAR bool V37 tmp28 d:6 ***** BB19, stmt 48 ( 7, 6) [000059] ------------ * STMT void (IL 0x033...0x035) N004 ( 7, 6) [000058] ------------ \--* JTRUE void N002 ( 1, 1) [000056] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000057] J------N---- \--* EQ int $31f N001 ( 3, 2) [000055] ------------ \--* LCL_VAR int V37 tmp28 u:6 (last use) $501 ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ***** BB20, stmt 49 ( 6, 5) [000150] ------------ * STMT void (IL 0x038...0x03A) N003 ( 1, 1) [000147] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000149] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000148] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000146] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB20, stmt 50 ( 1, 3) [000154] ------------ * STMT void (IL 0x03B...0x03C) N001 ( 1, 1) [000151] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000153] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000152] D------N---- \--* LCL_VAR int V05 loc3 d:6 $41 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ***** BB21, stmt 51 ( 38, 21) [000069] ------------ * STMT void (IL 0x03F...0x045) N015 ( 38, 21) [000062] SACXG------- \--* CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N001 ( 1, 1) [000066] ------------ | /--* LCL_VAR byref V00 arg0 u:2 $80 N003 ( 5, 4) [001206] -A------R-L- arg0 SETUP +--* ASG byref $80 N002 ( 3, 2) [001205] D------N---- | \--* LCL_VAR byref V103 tmp94 d:3 $80 N005 ( 3, 2) [000064] x------N---- | /--* IND struct N004 ( 1, 1) [000061] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N007 ( 7, 5) [001204] -A------R-L- arg1 SETUP +--* ASG struct (copy) $VN.Void N006 ( 3, 2) [001203] D------N---- | \--* LCL_VAR struct(AX) V97 tmp88 N010 ( 3, 2) [001207] ------------ arg0 in rcx +--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 3, 3) [001210] L----------- arg1 in rdx \--* ADDR byref $2e1 N011 ( 3, 2) [001209] -------N---- \--* LCL_VAR struct(AX) V97 tmp88 $489 ***** BB21, stmt 52 ( 14, 10) [000732] ------------ * STMT void (IL 0x047... ???) N004 ( 3, 2) [001216] -------N---- | /--* LCL_VAR int V62 tmp53 u:3 (last use) $3c0 N006 ( 7, 5) [001217] -A------R--- | /--* ASG int $3c0 N005 ( 3, 2) [001215] D------N---- | | \--* LCL_VAR int V88 tmp79 d:3 $3c0 N007 ( 14, 10) [001218] -A---------- \--* COMMA void $3c0 N001 ( 3, 2) [001213] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001214] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001212] D------N---- \--* LCL_VAR byref V87 tmp78 d:3 $VN.Null ***** BB21, stmt 53 ( 16, 13) [000736] ------------ * STMT void (IL 0x047... ???) N010 ( 4, 4) [001230] x----------- | /--* IND int N008 ( 1, 1) [001228] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001229] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001227] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N012 ( 8, 7) [001231] -A------R--- | /--* ASG int N011 ( 3, 2) [001226] D------N---- | | \--* LCL_VAR int V90 tmp81 d:3 N013 ( 16, 13) [001232] -A---------- \--* COMMA void N004 ( 4, 3) [001224] x----------- | /--* IND byref N002 ( 1, 1) [001222] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001223] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001221] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001225] -A------R--- \--* ASG byref N005 ( 3, 2) [001220] D------N---- \--* LCL_VAR byref V89 tmp80 d:3 ***** BB21, stmt 54 ( 14, 8) [000679] ------------ * STMT void (IL 0x047... ???) N002 ( 3, 2) [000770] ------------ | /--* LCL_VAR int V90 tmp81 u:3 N003 ( 10, 5) [000674] ------------ | /--* NE int N001 ( 3, 2) [000672] ------------ | | \--* LCL_VAR int V88 tmp79 u:3 $3c0 N005 ( 14, 8) [000678] -A------R--- \--* ASG bool N004 ( 3, 2) [000677] D------N---- \--* LCL_VAR int V44 tmp35 d:3 ***** BB21, stmt 55 ( 7, 6) [000684] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000683] ------------ \--* JTRUE void N002 ( 1, 1) [000681] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000682] J------N---- \--* EQ int N001 ( 3, 2) [000680] ------------ \--* LCL_VAR int V44 tmp35 u:3 (last use) ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ***** BB22, stmt 56 ( 5, 4) [000728] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000725] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000727] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000726] D------N---- \--* LCL_VAR int V46 tmp37 d:6 $40 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23, stmt 57 ( 12, 7) [000695] ------------ * STMT void (IL 0x047... ???) N002 ( 1, 1) [000691] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000692] ------------ | /--* EQ int N001 ( 3, 2) [000783] ------------ | | \--* LCL_VAR int V90 tmp81 u:3 N005 ( 12, 7) [000694] -A------R--- \--* ASG bool N004 ( 3, 2) [000693] D------N---- \--* LCL_VAR int V45 tmp36 d:3 ***** BB23, stmt 58 ( 7, 6) [000700] ------------ * STMT void (IL 0x047... ???) N004 ( 7, 6) [000699] ------------ \--* JTRUE void N002 ( 1, 1) [000697] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000698] J------N---- \--* EQ int N001 ( 3, 2) [000696] ------------ \--* LCL_VAR int V45 tmp36 u:3 (last use) ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ***** BB24, stmt 59 ( 5, 4) [000723] ------------ * STMT void (IL 0x047... ???) N001 ( 1, 1) [000720] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000722] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000721] D------N---- \--* LCL_VAR int V46 tmp37 d:5 $41 ------------ BB25 [047..048), preds={BB23} succs={BB26} ***** BB25, stmt 60 ( 89, 60) [000715] ------------ * STMT void (IL 0x047... ???) N046 ( 1, 1) [000711] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000712] -ACXG------- | /--* EQ int $328 N045 ( 80, 55) [000704] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N016 ( 3, 2) [001256] -------N---- | | | /--* LCL_VAR int V88 tmp79 u:3 (last use) $3c0 N017 ( 10, 8) [001257] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001255] *------N---- | | | | \--* IND int $3c0 N013 ( 1, 1) [001253] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001254] -------N---- | | | | \--* ADD byref $40d N012 ( 3, 2) [001252] ------------ | | | | \--* LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N018 ( 27, 21) [001258] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001249] -------N---- | | | | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N010 ( 10, 7) [001250] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001248] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001246] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001247] -------N---- | | | | | \--* ADD byref $40c N005 ( 3, 2) [001245] ------------ | | | | | \--* LCL_VAR byref V104 tmp95 u:3 $2e5 N011 ( 17, 13) [001251] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001241] L----------- | | | | /--* ADDR byref $2e5 N001 ( 3, 2) [001242] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48a N004 ( 7, 6) [001244] -A------R--- | | | \--* ASG byref $2e5 N003 ( 3, 2) [001243] D------N---- | | | \--* LCL_VAR byref V104 tmp95 d:3 $2e5 N034 ( 3, 2) [001277] -------N---- | | | /--* LCL_VAR int V90 tmp81 u:3 (last use) N035 ( 10, 8) [001278] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001276] *------N---- | | | | \--* IND int N031 ( 1, 1) [001274] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001275] -------N---- | | | | \--* ADD byref $40f N030 ( 3, 2) [001273] ------------ | | | | \--* LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N036 ( 27, 21) [001279] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001270] -------N---- | | | | /--* LCL_VAR byref V89 tmp80 u:3 (last use) N028 ( 10, 7) [001271] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001269] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001267] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001268] -------N---- | | | | | \--* ADD byref $40e N023 ( 3, 2) [001266] ------------ | | | | | \--* LCL_VAR byref V105 tmp96 u:3 $2e7 N029 ( 17, 13) [001272] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001262] L----------- | | | | /--* ADDR byref $2e7 N019 ( 3, 2) [001263] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48b N022 ( 7, 6) [001265] -A------R--- | | | \--* ASG byref $2e7 N021 ( 3, 2) [001264] D------N---- | | | \--* LCL_VAR byref V105 tmp96 d:3 $2e7 N040 ( 3, 3) [001281] L----------- arg0 in rcx | | +--* ADDR byref $2e9 N039 ( 3, 2) [001280] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $48c N042 ( 3, 3) [001284] L----------- arg1 in rdx | | \--* ADDR byref $2ea N041 ( 3, 2) [001283] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $48d N049 ( 89, 60) [000714] -ACXG---R--- \--* ASG bool $328 N048 ( 3, 2) [000713] D------N---- \--* LCL_VAR int V46 tmp37 d:4 $328 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ***** BB26, stmt 61 ( 8, 7) [001375] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001373] ------------ | * PHI bool N001 ( 0, 0) [001428] ------------ | /--* PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ | +--* PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ | \--* PHI_ARG bool V46 tmp37 u:4 $328 N009 ( 8, 7) [001374] -A------R--- \--* ASG bool N008 ( 4, 3) [001372] D------N---- \--* LCL_VAR bool V46 tmp37 d:3 ***** BB26, stmt 62 ( 7, 6) [000089] ------------ * STMT void (IL 0x050...0x052) N004 ( 7, 6) [000088] ------------ \--* JTRUE void N002 ( 1, 1) [000086] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000087] J------N---- \--* EQ int $329 N001 ( 3, 2) [000085] ------------ \--* LCL_VAR int V46 tmp37 u:3 (last use) $502 ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ***** BB27, stmt 63 ( 6, 5) [000140] ------------ * STMT void (IL 0x055...0x057) N003 ( 1, 1) [000137] ------------ | /--* CNS_INT int 1 $41 N004 ( 6, 5) [000139] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000138] *--X---N---- \--* IND byte $41 N001 ( 1, 1) [000136] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB27, stmt 64 ( 1, 3) [000144] ------------ * STMT void (IL 0x058...0x059) N001 ( 1, 1) [000141] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000143] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000142] D------N---- \--* LCL_VAR int V05 loc3 d:5 $41 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ***** BB28, stmt 65 ( 14, 10) [000862] ------------ * STMT void (IL 0x05C... ???) N004 ( 3, 2) [001291] -------N---- | /--* LCL_VAR int V64 tmp55 u:3 (last use) $3c2 N006 ( 7, 5) [001292] -A------R--- | /--* ASG int $3c2 N005 ( 3, 2) [001290] D------N---- | | \--* LCL_VAR int V92 tmp83 d:3 $3c2 N007 ( 14, 10) [001293] -A---------- \--* COMMA void $3c2 N001 ( 3, 2) [001288] -------N---- | /--* LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null N003 ( 7, 5) [001289] -A------R--- \--* ASG byref $VN.Null N002 ( 3, 2) [001287] D------N---- \--* LCL_VAR byref V91 tmp82 d:3 $VN.Null ***** BB28, stmt 66 ( 16, 13) [000866] ------------ * STMT void (IL 0x05C... ???) N010 ( 4, 4) [001305] x----------- | /--* IND int N008 ( 1, 1) [001303] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $281 N009 ( 2, 2) [001304] -------N---- | | \--* ADD byref $401 N007 ( 1, 1) [001302] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 (last use) $80 N012 ( 8, 7) [001306] -A------R--- | /--* ASG int N011 ( 3, 2) [001301] D------N---- | | \--* LCL_VAR int V94 tmp85 d:3 N013 ( 16, 13) [001307] -A---------- \--* COMMA void N004 ( 4, 3) [001299] x----------- | /--* IND byref N002 ( 1, 1) [001297] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N003 ( 3, 3) [001298] -------N---- | | \--* ADD byref $400 N001 ( 1, 1) [001296] ------------ | | \--* LCL_VAR byref V00 arg0 u:2 $80 N006 ( 8, 6) [001300] -A------R--- \--* ASG byref N005 ( 3, 2) [001295] D------N---- \--* LCL_VAR byref V93 tmp84 d:3 ***** BB28, stmt 67 ( 14, 8) [000809] ------------ * STMT void (IL 0x05C... ???) N002 ( 3, 2) [000900] ------------ | /--* LCL_VAR int V94 tmp85 u:3 N003 ( 10, 5) [000804] ------------ | /--* NE int N001 ( 3, 2) [000802] ------------ | | \--* LCL_VAR int V92 tmp83 u:3 $3c2 N005 ( 14, 8) [000808] -A------R--- \--* ASG bool N004 ( 3, 2) [000807] D------N---- \--* LCL_VAR int V53 tmp44 d:3 ***** BB28, stmt 68 ( 7, 6) [000814] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000813] ------------ \--* JTRUE void N002 ( 1, 1) [000811] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000812] J------N---- \--* EQ int N001 ( 3, 2) [000810] ------------ \--* LCL_VAR int V53 tmp44 u:3 (last use) ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ***** BB29, stmt 69 ( 5, 4) [000858] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000855] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000857] -A------R--- \--* ASG bool $40 N002 ( 3, 2) [000856] D------N---- \--* LCL_VAR int V55 tmp46 d:6 $40 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ***** BB30, stmt 70 ( 12, 7) [000825] ------------ * STMT void (IL 0x05C... ???) N002 ( 1, 1) [000821] ------------ | /--* CNS_INT int 0 $40 N003 ( 8, 4) [000822] ------------ | /--* EQ int N001 ( 3, 2) [000913] ------------ | | \--* LCL_VAR int V94 tmp85 u:3 N005 ( 12, 7) [000824] -A------R--- \--* ASG bool N004 ( 3, 2) [000823] D------N---- \--* LCL_VAR int V54 tmp45 d:3 ***** BB30, stmt 71 ( 7, 6) [000830] ------------ * STMT void (IL 0x05C... ???) N004 ( 7, 6) [000829] ------------ \--* JTRUE void N002 ( 1, 1) [000827] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000828] J------N---- \--* EQ int N001 ( 3, 2) [000826] ------------ \--* LCL_VAR int V54 tmp45 u:3 (last use) ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ***** BB31, stmt 72 ( 5, 4) [000853] ------------ * STMT void (IL 0x05C... ???) N001 ( 1, 1) [000850] ------------ | /--* CNS_INT int 1 $41 N003 ( 5, 4) [000852] -A------R--- \--* ASG bool $41 N002 ( 3, 2) [000851] D------N---- \--* LCL_VAR int V55 tmp46 d:5 $41 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ***** BB32, stmt 73 ( 89, 60) [000845] ------------ * STMT void (IL 0x05C... ???) N046 ( 1, 1) [000841] ------------ | /--* CNS_INT int 0 $40 N047 ( 85, 57) [000842] -ACXG------- | /--* EQ int $332 N045 ( 80, 55) [000834] -ACXG------- | | \--* CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N016 ( 3, 2) [001331] -------N---- | | | /--* LCL_VAR int V92 tmp83 u:3 (last use) $3c2 N017 ( 10, 8) [001332] -A---------- | | | /--* ASG int indir assign of V97:ud:0->0 $VN.Void N015 ( 6, 5) [001330] *------N---- | | | | \--* IND int $3c2 N013 ( 1, 1) [001328] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N014 ( 4, 3) [001329] -------N---- | | | | \--* ADD byref $411 N012 ( 3, 2) [001327] ------------ | | | | \--* LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N018 ( 27, 21) [001333] -A--------L- arg0 SETUP | | +--* COMMA void $VN.Void N009 ( 3, 2) [001324] -------N---- | | | | /--* LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null N010 ( 10, 7) [001325] -A---------- | | | | /--* ASG byref indir assign of V97:ud:0->0 $VN.Void N008 ( 6, 4) [001323] *------N---- | | | | | \--* IND byref $VN.Null N006 ( 1, 1) [001321] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N007 ( 5, 4) [001322] -------N---- | | | | | \--* ADD byref $410 N005 ( 3, 2) [001320] ------------ | | | | | \--* LCL_VAR byref V106 tmp97 u:3 $2ee N011 ( 17, 13) [001326] -A---------- | | | \--* COMMA void $VN.Void N002 ( 3, 3) [001316] L----------- | | | | /--* ADDR byref $2ee N001 ( 3, 2) [001317] -------N---- | | | | | \--* LCL_VAR struct(AX) V97 tmp88 $48e N004 ( 7, 6) [001319] -A------R--- | | | \--* ASG byref $2ee N003 ( 3, 2) [001318] D------N---- | | | \--* LCL_VAR byref V106 tmp97 d:3 $2ee N034 ( 3, 2) [001352] -------N---- | | | /--* LCL_VAR int V94 tmp85 u:3 (last use) N035 ( 10, 8) [001353] -A---------- | | | /--* ASG int indir assign of V99:ud:0->0 $VN.Void N033 ( 6, 5) [001351] *------N---- | | | | \--* IND int N031 ( 1, 1) [001349] ------------ | | | | | /--* CNS_INT long 8 Fseq[_length] $281 N032 ( 4, 3) [001350] -------N---- | | | | \--* ADD byref $413 N030 ( 3, 2) [001348] ------------ | | | | \--* LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N036 ( 27, 21) [001354] -A--------L- arg1 SETUP | | +--* COMMA void $VN.Void N027 ( 3, 2) [001345] -------N---- | | | | /--* LCL_VAR byref V93 tmp84 u:3 (last use) N028 ( 10, 7) [001346] -A---------- | | | | /--* ASG byref indir assign of V99:ud:0->0 $VN.Void N026 ( 6, 4) [001344] *------N---- | | | | | \--* IND byref N024 ( 1, 1) [001342] ------------ | | | | | | /--* CNS_INT long 0 Fseq[_pointer] $282 N025 ( 5, 4) [001343] -------N---- | | | | | \--* ADD byref $412 N023 ( 3, 2) [001341] ------------ | | | | | \--* LCL_VAR byref V107 tmp98 u:3 $2f0 N029 ( 17, 13) [001347] -A---------- | | | \--* COMMA void $VN.Void N020 ( 3, 3) [001337] L----------- | | | | /--* ADDR byref $2f0 N019 ( 3, 2) [001338] -------N---- | | | | | \--* LCL_VAR struct(AX) V99 tmp90 $48f N022 ( 7, 6) [001340] -A------R--- | | | \--* ASG byref $2f0 N021 ( 3, 2) [001339] D------N---- | | | \--* LCL_VAR byref V107 tmp98 d:3 $2f0 N040 ( 3, 3) [001356] L----------- arg0 in rcx | | +--* ADDR byref $2f2 N039 ( 3, 2) [001355] -------N---- | | | \--* LCL_VAR struct(AX) V97 tmp88 $490 N042 ( 3, 3) [001359] L----------- arg1 in rdx | | \--* ADDR byref $2f3 N041 ( 3, 2) [001358] -------N---- | | \--* LCL_VAR struct(AX) V99 tmp90 $491 N049 ( 89, 60) [000844] -ACXG---R--- \--* ASG bool $332 N048 ( 3, 2) [000843] D------N---- \--* LCL_VAR int V55 tmp46 d:4 $332 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ***** BB33, stmt 74 ( 8, 7) [001371] ------------ * STMT void (IL ???... ???) N007 ( 3, 3) [001369] ------------ | * PHI bool N001 ( 0, 0) [001420] ------------ | /--* PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ | +--* PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ | \--* PHI_ARG bool V55 tmp46 u:4 $332 N009 ( 8, 7) [001370] -A------R--- \--* ASG bool N008 ( 4, 3) [001368] D------N---- \--* LCL_VAR bool V55 tmp46 d:3 ***** BB33, stmt 75 ( 7, 6) [000110] ------------ * STMT void (IL 0x065...0x067) N004 ( 7, 6) [000109] ------------ \--* JTRUE void N002 ( 1, 1) [000107] ------------ | /--* CNS_INT int 0 $40 N003 ( 5, 4) [000108] J------N---- \--* EQ int $333 N001 ( 3, 2) [000106] ------------ \--* LCL_VAR int V55 tmp46 u:3 (last use) $503 ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34, stmt 76 ( 6, 5) [000130] ------------ * STMT void (IL 0x06A...0x06C) N003 ( 1, 1) [000127] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000129] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000128] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000126] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB34, stmt 77 ( 1, 3) [000134] ------------ * STMT void (IL 0x06D...0x06E) N001 ( 1, 1) [000131] ------------ | /--* CNS_INT int 1 $41 N003 ( 1, 3) [000133] -A------R--- \--* ASG int $41 N002 ( 1, 1) [000132] D------N---- \--* LCL_VAR int V05 loc3 d:4 $41 ------------ BB35 [071..078), preds={BB33} succs={BB36} ***** BB35, stmt 78 ( 6, 5) [000116] ------------ * STMT void (IL 0x071...0x073) N003 ( 1, 1) [000113] ------------ | /--* CNS_INT int 0 $40 N004 ( 6, 5) [000115] -A-XG------- \--* ASG byte $VN.Void N002 ( 4, 3) [000114] *--X---N---- \--* IND byte $40 N001 ( 1, 1) [000112] ------------ \--* LCL_VAR byref V01 arg1 u:2 (last use) $81 ***** BB35, stmt 79 ( 1, 3) [000120] ------------ * STMT void (IL 0x074...0x075) N001 ( 1, 1) [000117] ------------ | /--* CNS_INT int 0 $40 N003 ( 1, 3) [000119] -A------R--- \--* ASG int $40 N002 ( 1, 1) [000118] D------N---- \--* LCL_VAR int V05 loc3 d:3 $40 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ***** BB36, stmt 80 ( 5, 5) [001367] ------------ * STMT void (IL ???... ???) N011 ( 5, 5) [001365] ------------ | * PHI bool N001 ( 0, 0) [001440] ------------ | /--* PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ | +--* PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ | +--* PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ | +--* PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ | \--* PHI_ARG bool V05 loc3 u:3 $40 N013 ( 5, 5) [001366] -A------R--- \--* ASG bool N012 ( 1, 1) [001364] D------N---- \--* LCL_VAR bool V05 loc3 d:8 ***** BB36, stmt 81 ( 2, 2) [000124] ------------ * STMT void (IL 0x078...0x079) N002 ( 2, 2) [000123] ------------ \--* RETURN int $1fb N001 ( 1, 1) [000122] ------------ \--* LCL_VAR int V05 loc3 u:8 (last use) $504 ------------------------------------------------------------------------------------------------------------------- rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000170] DA---------- * STORE_LCL_VAR int V09 tmp0 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000988] DA---------- * STORE_LCL_VAR byref V72 tmp63 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 3, 3) [000991] DA---------- * STORE_LCL_VAR int V73 tmp64 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N049 ( 81, 55) [000337] DACXG------- * STORE_LCL_VAR int V21 tmp12 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V25 tmp16 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 12, 18) [000433] DA-XG------- * STORE_LCL_VAR byref V26 tmp17 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000513] DA---------- * STORE_LCL_VAR byref V82 tmp73 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001113] DA---------- * STORE_LCL_VAR byref V76 tmp67 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001116] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001130] DA---------- * STORE_LCL_VAR byref V83 tmp74 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [001133] DA---------- * STORE_LCL_VAR int V84 tmp75 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N049 ( 89, 60) [000584] DACXG------- * STORE_LCL_VAR int V37 tmp28 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 After transforming local struct assignment into a block op: N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] x------N---- t64 = * IND struct N006 ( 3, 2) [001203] D------N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001214] DA---------- * STORE_LCL_VAR byref V87 tmp78 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N049 ( 89, 60) [000714] DACXG------- * STORE_LCL_VAR int V46 tmp37 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N049 ( 89, 60) [000844] DACXG------- * STORE_LCL_VAR int V55 tmp46 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 *************** Exiting IR Rationalize Trees after IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 1, 1) [000168] ------------ t168 = CNS_INT int 0 $40 /--* t168 int N003 ( 1, 3) [000170] DA---------- * STORE_LCL_VAR int V09 tmp0 d:3 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] ------------ t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N003 ( 1, 1) [000953] ------------ t953 = CNS_INT long 8 field offset Fseq[_stringLength] $281 /--* t955 ref +--* t953 long N004 ( 4, 11) [000954] -------N---- t954 = * ADD byref $VN.Null /--* t954 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] ------------ t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000987] -------N---- t987 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t987 byref N003 ( 7, 5) [000988] DA---------- * STORE_LCL_VAR byref V72 tmp63 d:3 N004 ( 3, 2) [000990] -------N---- t990 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t990 int N006 ( 3, 3) [000991] DA---------- * STORE_LCL_VAR int V73 tmp64 d:3 ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [000996] ------------ t996 = CNS_INT long 0 Fseq[_pointer] $282 /--* t995 byref +--* t996 long N003 ( 3, 3) [000997] -------N---- t997 = * ADD byref $400 /--* t997 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001002] ------------ t1002 = CNS_INT long 8 Fseq[_length] $281 /--* t1001 byref +--* t1002 long N009 ( 2, 2) [001003] -------N---- t1003 = * ADD byref $401 /--* t1003 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] ------------ t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- t305 = * EQ int /--* t305 int N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] ------------ t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] ------------ t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- t321 = * EQ int /--* t321 int N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] ------------ t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca N006 ( 1, 1) [001020] ------------ t1020 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1019 byref +--* t1020 long N007 ( 5, 4) [001021] -------N---- t1021 = * ADD byref $403 N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1021 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N013 ( 1, 1) [001027] ------------ t1027 = CNS_INT long 8 Fseq[_length] $281 /--* t1026 byref +--* t1027 long N014 ( 4, 3) [001028] -------N---- t1028 = * ADD byref $404 N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1028 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc N024 ( 1, 1) [001041] ------------ t1041 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1040 byref +--* t1041 long N025 ( 5, 4) [001042] -------N---- t1042 = * ADD byref $406 N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1042 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N031 ( 1, 1) [001048] ------------ t1048 = CNS_INT long 8 Fseq[_length] $281 /--* t1047 byref +--* t1048 long N032 ( 4, 3) [001049] -------N---- t1049 = * ADD byref $407 N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1049 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1054 byref arg0 in rcx +--* t1057 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] ------------ t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] ------------ t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- t27 = * EQ int $30e /--* t27 int N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] ------------ t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] ------------ t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V25 tmp16 d:3 ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c N008 ( 1, 1) [001085] ------------ t1085 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 N009 ( 1, 1) [001086] ------------ t1086 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t1085 ref +--* t1086 long N010 ( 3, 3) [001087] ------------ t1087 = * ADD byref $VN.Null /--* t1087 byref N013 ( 12, 18) [000433] DA-XG------- * STORE_LCL_VAR byref V26 tmp17 d:3 ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N003 ( 1, 1) [001095] ------------ t1095 = CNS_INT long 8 field offset Fseq[_stringLength] $281 /--* t1097 ref +--* t1095 long N004 ( 4, 11) [001096] -------N---- t1096 = * ADD byref $VN.Null /--* t1096 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] ------------ t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000435] ------------ t435 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t435 byref N003 ( 7, 5) [000513] DA---------- * STORE_LCL_VAR byref V82 tmp73 d:3 ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001112] -------N---- t1112 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1112 byref N003 ( 7, 5) [001113] DA---------- * STORE_LCL_VAR byref V76 tmp67 d:3 ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001115] -------N---- t1115 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1115 byref N003 ( 7, 5) [001116] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:4 N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001129] -------N---- t1129 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1129 byref N003 ( 7, 5) [001130] DA---------- * STORE_LCL_VAR byref V83 tmp74 d:3 N004 ( 3, 2) [001132] -------N---- t1132 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1132 int N006 ( 7, 5) [001133] DA---------- * STORE_LCL_VAR int V84 tmp75 d:3 ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001138] ------------ t1138 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1137 byref +--* t1138 long N003 ( 3, 3) [001139] -------N---- t1139 = * ADD byref $400 /--* t1139 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001144] ------------ t1144 = CNS_INT long 8 Fseq[_length] $281 /--* t1143 byref +--* t1144 long N009 ( 2, 2) [001145] -------N---- t1145 = * ADD byref $401 /--* t1145 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] ------------ t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- t552 = * EQ int /--* t552 int N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] ------------ t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] ------------ t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- t568 = * EQ int /--* t568 int N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] ------------ t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da N006 ( 1, 1) [001162] ------------ t1162 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1161 byref +--* t1162 long N007 ( 5, 4) [001163] -------N---- t1163 = * ADD byref $408 N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1163 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da N013 ( 1, 1) [001169] ------------ t1169 = CNS_INT long 8 Fseq[_length] $281 /--* t1168 byref +--* t1169 long N014 ( 4, 3) [001170] -------N---- t1170 = * ADD byref $409 N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1170 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc N024 ( 1, 1) [001183] ------------ t1183 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1182 byref +--* t1183 long N025 ( 5, 4) [001184] -------N---- t1184 = * ADD byref $40a N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1184 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N031 ( 1, 1) [001190] ------------ t1190 = CNS_INT long 8 Fseq[_length] $281 /--* t1189 byref +--* t1190 long N032 ( 4, 3) [001191] -------N---- t1191 = * ADD byref $40b N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1191 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1196 byref arg0 in rcx +--* t1199 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] ------------ t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] ------------ t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- t57 = * EQ int $31f /--* t57 int N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] ------------ t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] ------------ t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR byref V00 arg0 u:2 $80 /--* t66 byref N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] x------N---- t64 = * IND struct N006 ( 3, 2) [001203] D------N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1207 byref arg0 in rcx +--* t1209 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001213] -------N---- t1213 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1213 byref N003 ( 7, 5) [001214] DA---------- * STORE_LCL_VAR byref V87 tmp78 d:3 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001222] ------------ t1222 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1221 byref +--* t1222 long N003 ( 3, 3) [001223] -------N---- t1223 = * ADD byref $400 /--* t1223 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001228] ------------ t1228 = CNS_INT long 8 Fseq[_length] $281 /--* t1227 byref +--* t1228 long N009 ( 2, 2) [001229] -------N---- t1229 = * ADD byref $401 /--* t1229 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] ------------ t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- t682 = * EQ int /--* t682 int N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] ------------ t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] ------------ t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- t698 = * EQ int /--* t698 int N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] ------------ t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 N006 ( 1, 1) [001246] ------------ t1246 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1245 byref +--* t1246 long N007 ( 5, 4) [001247] -------N---- t1247 = * ADD byref $40c N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1247 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N013 ( 1, 1) [001253] ------------ t1253 = CNS_INT long 8 Fseq[_length] $281 /--* t1252 byref +--* t1253 long N014 ( 4, 3) [001254] -------N---- t1254 = * ADD byref $40d N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1254 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 N024 ( 1, 1) [001267] ------------ t1267 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1266 byref +--* t1267 long N025 ( 5, 4) [001268] -------N---- t1268 = * ADD byref $40e N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1268 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N031 ( 1, 1) [001274] ------------ t1274 = CNS_INT long 8 Fseq[_length] $281 /--* t1273 byref +--* t1274 long N032 ( 4, 3) [001275] -------N---- t1275 = * ADD byref $40f N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1275 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1280 byref arg0 in rcx +--* t1283 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] ------------ t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] ------------ t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- t87 = * EQ int $329 /--* t87 int N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] ------------ t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] ------------ t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001297] ------------ t1297 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1296 byref +--* t1297 long N003 ( 3, 3) [001298] -------N---- t1298 = * ADD byref $400 /--* t1298 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N008 ( 1, 1) [001303] ------------ t1303 = CNS_INT long 8 Fseq[_length] $281 /--* t1302 byref +--* t1303 long N009 ( 2, 2) [001304] -------N---- t1304 = * ADD byref $401 /--* t1304 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] ------------ t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- t812 = * EQ int /--* t812 int N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] ------------ t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] ------------ t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- t828 = * EQ int /--* t828 int N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] ------------ t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee N006 ( 1, 1) [001321] ------------ t1321 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1320 byref +--* t1321 long N007 ( 5, 4) [001322] -------N---- t1322 = * ADD byref $410 N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1322 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N013 ( 1, 1) [001328] ------------ t1328 = CNS_INT long 8 Fseq[_length] $281 /--* t1327 byref +--* t1328 long N014 ( 4, 3) [001329] -------N---- t1329 = * ADD byref $411 N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1329 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 N024 ( 1, 1) [001342] ------------ t1342 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1341 byref +--* t1342 long N025 ( 5, 4) [001343] -------N---- t1343 = * ADD byref $412 N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1343 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N031 ( 1, 1) [001349] ------------ t1349 = CNS_INT long 8 Fseq[_length] $281 /--* t1348 byref +--* t1349 long N032 ( 4, 3) [001350] -------N---- t1350 = * ADD byref $413 N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1350 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1355 byref arg0 in rcx +--* t1358 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] ------------ t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] ------------ t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- t108 = * EQ int $333 /--* t108 int N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] ------------ t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] ------------ t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] ------------ t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Bumping outgoingArgSpaceSize to 32 for call [000254] outgoingArgSpaceSize 32 sufficient for call [000327], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000501], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000574], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000062], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000704], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000834], which needs 32 *************** In fgDebugCheckBBlist *************** In Lowering Trees before Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 1, 1) [000168] ------------ t168 = CNS_INT int 0 $40 /--* t168 int N003 ( 1, 3) [000170] DA---------- * STORE_LCL_VAR int V09 tmp0 d:3 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] ------------ t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 N003 ( 1, 1) [000953] ------------ t953 = CNS_INT long 8 field offset Fseq[_stringLength] $281 /--* t955 ref +--* t953 long N004 ( 4, 11) [000954] -------N---- t954 = * ADD byref $VN.Null /--* t954 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] ------------ t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000987] -------N---- t987 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t987 byref N003 ( 7, 5) [000988] DA---------- * STORE_LCL_VAR byref V72 tmp63 d:3 N004 ( 3, 2) [000990] -------N---- t990 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t990 int N006 ( 3, 3) [000991] DA---------- * STORE_LCL_VAR int V73 tmp64 d:3 ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [000996] ------------ t996 = CNS_INT long 0 Fseq[_pointer] $282 /--* t995 byref +--* t996 long N003 ( 3, 3) [000997] -------N---- t997 = * ADD byref $400 /--* t997 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001002] ------------ t1002 = CNS_INT long 8 Fseq[_length] $281 /--* t1001 byref +--* t1002 long N009 ( 2, 2) [001003] -------N---- t1003 = * ADD byref $401 /--* t1003 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] ------------ t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- t305 = * EQ int /--* t305 int N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] ------------ t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] ------------ t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- t321 = * EQ int /--* t321 int N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] ------------ t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca N006 ( 1, 1) [001020] ------------ t1020 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1019 byref +--* t1020 long N007 ( 5, 4) [001021] -------N---- t1021 = * ADD byref $403 N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1021 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca N013 ( 1, 1) [001027] ------------ t1027 = CNS_INT long 8 Fseq[_length] $281 /--* t1026 byref +--* t1027 long N014 ( 4, 3) [001028] -------N---- t1028 = * ADD byref $404 N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1028 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc N024 ( 1, 1) [001041] ------------ t1041 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1040 byref +--* t1041 long N025 ( 5, 4) [001042] -------N---- t1042 = * ADD byref $406 N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1042 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc N031 ( 1, 1) [001048] ------------ t1048 = CNS_INT long 8 Fseq[_length] $281 /--* t1047 byref +--* t1048 long N032 ( 4, 3) [001049] -------N---- t1049 = * ADD byref $407 N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1049 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1054 byref arg0 in rcx +--* t1057 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] ------------ t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] ------------ t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- t27 = * EQ int $30e /--* t27 int N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] ------------ t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] ------------ t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V25 tmp16 d:3 ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c N008 ( 1, 1) [001085] ------------ t1085 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 N009 ( 1, 1) [001086] ------------ t1086 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t1085 ref +--* t1086 long N010 ( 3, 3) [001087] ------------ t1087 = * ADD byref $VN.Null /--* t1087 byref N013 ( 12, 18) [000433] DA-XG------- * STORE_LCL_VAR byref V26 tmp17 d:3 ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 N003 ( 1, 1) [001095] ------------ t1095 = CNS_INT long 8 field offset Fseq[_stringLength] $281 /--* t1097 ref +--* t1095 long N004 ( 4, 11) [001096] -------N---- t1096 = * ADD byref $VN.Null /--* t1096 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] ------------ t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000435] ------------ t435 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t435 byref N003 ( 7, 5) [000513] DA---------- * STORE_LCL_VAR byref V82 tmp73 d:3 ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001112] -------N---- t1112 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1112 byref N003 ( 7, 5) [001113] DA---------- * STORE_LCL_VAR byref V76 tmp67 d:3 ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001115] -------N---- t1115 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1115 byref N003 ( 7, 5) [001116] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:4 N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001129] -------N---- t1129 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1129 byref N003 ( 7, 5) [001130] DA---------- * STORE_LCL_VAR byref V83 tmp74 d:3 N004 ( 3, 2) [001132] -------N---- t1132 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1132 int N006 ( 7, 5) [001133] DA---------- * STORE_LCL_VAR int V84 tmp75 d:3 ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001138] ------------ t1138 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1137 byref +--* t1138 long N003 ( 3, 3) [001139] -------N---- t1139 = * ADD byref $400 /--* t1139 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001144] ------------ t1144 = CNS_INT long 8 Fseq[_length] $281 /--* t1143 byref +--* t1144 long N009 ( 2, 2) [001145] -------N---- t1145 = * ADD byref $401 /--* t1145 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] ------------ t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- t552 = * EQ int /--* t552 int N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] ------------ t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] ------------ t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- t568 = * EQ int /--* t568 int N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] ------------ t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da N006 ( 1, 1) [001162] ------------ t1162 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1161 byref +--* t1162 long N007 ( 5, 4) [001163] -------N---- t1163 = * ADD byref $408 N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1163 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da N013 ( 1, 1) [001169] ------------ t1169 = CNS_INT long 8 Fseq[_length] $281 /--* t1168 byref +--* t1169 long N014 ( 4, 3) [001170] -------N---- t1170 = * ADD byref $409 N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1170 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc N024 ( 1, 1) [001183] ------------ t1183 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1182 byref +--* t1183 long N025 ( 5, 4) [001184] -------N---- t1184 = * ADD byref $40a N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1184 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc N031 ( 1, 1) [001190] ------------ t1190 = CNS_INT long 8 Fseq[_length] $281 /--* t1189 byref +--* t1190 long N032 ( 4, 3) [001191] -------N---- t1191 = * ADD byref $40b N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1191 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1196 byref arg0 in rcx +--* t1199 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] ------------ t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] ------------ t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- t57 = * EQ int $31f /--* t57 int N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] ------------ t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] ------------ t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR byref V00 arg0 u:2 $80 /--* t66 byref N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] x------N---- t64 = * IND struct N006 ( 3, 2) [001203] D------N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1207 byref arg0 in rcx +--* t1209 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001213] -------N---- t1213 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1213 byref N003 ( 7, 5) [001214] DA---------- * STORE_LCL_VAR byref V87 tmp78 d:3 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001222] ------------ t1222 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1221 byref +--* t1222 long N003 ( 3, 3) [001223] -------N---- t1223 = * ADD byref $400 /--* t1223 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 N008 ( 1, 1) [001228] ------------ t1228 = CNS_INT long 8 Fseq[_length] $281 /--* t1227 byref +--* t1228 long N009 ( 2, 2) [001229] -------N---- t1229 = * ADD byref $401 /--* t1229 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] ------------ t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- t682 = * EQ int /--* t682 int N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] ------------ t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] ------------ t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- t698 = * EQ int /--* t698 int N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] ------------ t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 N006 ( 1, 1) [001246] ------------ t1246 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1245 byref +--* t1246 long N007 ( 5, 4) [001247] -------N---- t1247 = * ADD byref $40c N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1247 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 N013 ( 1, 1) [001253] ------------ t1253 = CNS_INT long 8 Fseq[_length] $281 /--* t1252 byref +--* t1253 long N014 ( 4, 3) [001254] -------N---- t1254 = * ADD byref $40d N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1254 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 N024 ( 1, 1) [001267] ------------ t1267 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1266 byref +--* t1267 long N025 ( 5, 4) [001268] -------N---- t1268 = * ADD byref $40e N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1268 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 N031 ( 1, 1) [001274] ------------ t1274 = CNS_INT long 8 Fseq[_length] $281 /--* t1273 byref +--* t1274 long N032 ( 4, 3) [001275] -------N---- t1275 = * ADD byref $40f N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1275 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1280 byref arg0 in rcx +--* t1283 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] ------------ t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] ------------ t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- t87 = * EQ int $329 /--* t87 int N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] ------------ t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] ------------ t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 N002 ( 1, 1) [001297] ------------ t1297 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1296 byref +--* t1297 long N003 ( 3, 3) [001298] -------N---- t1298 = * ADD byref $400 /--* t1298 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N008 ( 1, 1) [001303] ------------ t1303 = CNS_INT long 8 Fseq[_length] $281 /--* t1302 byref +--* t1303 long N009 ( 2, 2) [001304] -------N---- t1304 = * ADD byref $401 /--* t1304 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] ------------ t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- t812 = * EQ int /--* t812 int N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] ------------ t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] ------------ t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- t828 = * EQ int /--* t828 int N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] ------------ t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee N006 ( 1, 1) [001321] ------------ t1321 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1320 byref +--* t1321 long N007 ( 5, 4) [001322] -------N---- t1322 = * ADD byref $410 N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1322 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee N013 ( 1, 1) [001328] ------------ t1328 = CNS_INT long 8 Fseq[_length] $281 /--* t1327 byref +--* t1328 long N014 ( 4, 3) [001329] -------N---- t1329 = * ADD byref $411 N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1329 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 N024 ( 1, 1) [001342] ------------ t1342 = CNS_INT long 0 Fseq[_pointer] $282 /--* t1341 byref +--* t1342 long N025 ( 5, 4) [001343] -------N---- t1343 = * ADD byref $412 N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1343 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 N031 ( 1, 1) [001349] ------------ t1349 = CNS_INT long 8 Fseq[_length] $281 /--* t1348 byref +--* t1349 long N032 ( 4, 3) [001350] -------N---- t1350 = * ADD byref $413 N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1350 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1355 byref arg0 in rcx +--* t1358 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] ------------ t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] ------------ t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- t108 = * EQ int $333 /--* t108 int N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] ------------ t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] ------------ t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] ------------ t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- Addressing mode: Base N001 ( 3, 10) [000955] ------------ * CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 + 8 New addressing mode node: [001478] ------------ * LEA(b+8) byref lowering call (before): N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000964] ----------L- * ARGPLACE int late: ====== lowering arg : N005 ( 8, 4) [000251] ------------ * GE int new node is : [001479] ------------ * PUTARG_REG int REG rcx lowering call (after): N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void Addressing mode: Base N001 ( 1, 1) [000995] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 0 New addressing mode node: [001480] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [001001] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 8 New addressing mode node: [001481] ------------ * LEA(b+8) byref Addressing mode: Base N005 ( 3, 2) [001019] ------------ * LCL_VAR byref V98 tmp89 u:3 $2ca + 0 New addressing mode node: [001482] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] ------------ t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref Addressing mode: Base N012 ( 3, 2) [001026] ------------ * LCL_VAR byref V98 tmp89 u:3 (last use) $2ca + 8 New addressing mode node: [001483] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] ------------ t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int Addressing mode: Base N023 ( 3, 2) [001040] ------------ * LCL_VAR byref V100 tmp91 u:3 $2cc + 0 New addressing mode node: [001484] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] ------------ t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref Addressing mode: Base N030 ( 3, 2) [001047] ------------ * LCL_VAR byref V100 tmp91 u:3 (last use) $2cc + 8 New addressing mode node: [001485] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] ------------ t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int lowering call (before): N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1054 byref arg0 in rcx +--* t1057 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce objp: ====== args: ====== lowering arg : [001457] -A--------L- * STOREIND int lowering arg : [001459] -A--------L- * STOREIND int late: ====== lowering arg : N039 ( 3, 2) [001054] -------N---- * LCL_VAR_ADDR byref V97 tmp88 new node is : [001486] ------------ * PUTARG_REG byref REG rcx lowering arg : N041 ( 3, 2) [001057] -------N---- * LCL_VAR_ADDR byref V99 tmp90 new node is : [001487] ------------ * PUTARG_REG byref REG rdx lowering call (after): N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce No addressing mode: N001 ( 1, 1) [000156] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $81 Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] ------------ t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte Addressing mode: Base N001 ( 3, 10) [001097] ------------ * CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 + 8 New addressing mode node: [001488] ------------ * LEA(b+8) byref lowering call (before): N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001106] ----------L- * ARGPLACE int late: ====== lowering arg : N005 ( 8, 4) [000498] ------------ * GE int new node is : [001489] ------------ * PUTARG_REG int REG rcx lowering call (after): N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void Addressing mode: Base N001 ( 1, 1) [001137] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 0 New addressing mode node: [001490] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [001143] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 8 New addressing mode node: [001491] ------------ * LEA(b+8) byref Addressing mode: Base N005 ( 3, 2) [001161] ------------ * LCL_VAR byref V101 tmp92 u:3 $2da + 0 New addressing mode node: [001492] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] ------------ t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref Addressing mode: Base N012 ( 3, 2) [001168] ------------ * LCL_VAR byref V101 tmp92 u:3 (last use) $2da + 8 New addressing mode node: [001493] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] ------------ t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int Addressing mode: Base N023 ( 3, 2) [001182] ------------ * LCL_VAR byref V102 tmp93 u:3 $2dc + 0 New addressing mode node: [001494] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] ------------ t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref Addressing mode: Base N030 ( 3, 2) [001189] ------------ * LCL_VAR byref V102 tmp93 u:3 (last use) $2dc + 8 New addressing mode node: [001495] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] ------------ t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int lowering call (before): N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1196 byref arg0 in rcx +--* t1199 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 objp: ====== args: ====== lowering arg : [001462] -A--------L- * STOREIND int lowering arg : [001464] -A--------L- * STOREIND int late: ====== lowering arg : N039 ( 3, 2) [001196] -------N---- * LCL_VAR_ADDR byref V97 tmp88 new node is : [001496] ------------ * PUTARG_REG byref REG rcx lowering arg : N041 ( 3, 2) [001199] -------N---- * LCL_VAR_ADDR byref V99 tmp90 new node is : [001497] ------------ * PUTARG_REG byref REG rdx lowering call (after): N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 No addressing mode: N001 ( 1, 1) [000146] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $81 Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] ------------ t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte lowering call (before): N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR byref V00 arg0 u:2 $80 /--* t66 byref N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 (last use) $80 N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1207 byref arg0 in rcx +--* t1209 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void objp: ====== args: ====== lowering arg : N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 lowering arg : [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) late: ====== lowering arg : N010 ( 3, 2) [001207] ------------ * LCL_VAR byref V00 arg0 u:2 (last use) $80 new node is : [001498] ------------ * PUTARG_REG byref REG rcx lowering arg : N011 ( 3, 2) [001209] -------N---- * LCL_VAR_ADDR byref V97 tmp88 new node is : [001499] ------------ * PUTARG_REG byref REG rdx lowering call (after): N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR byref V00 arg0 u:2 $80 /--* t66 byref N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void Addressing mode: Base N001 ( 1, 1) [001221] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 0 New addressing mode node: [001500] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [001227] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 8 New addressing mode node: [001501] ------------ * LEA(b+8) byref Addressing mode: Base N005 ( 3, 2) [001245] ------------ * LCL_VAR byref V104 tmp95 u:3 $2e5 + 0 New addressing mode node: [001502] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] ------------ t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref Addressing mode: Base N012 ( 3, 2) [001252] ------------ * LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 + 8 New addressing mode node: [001503] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] ------------ t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int Addressing mode: Base N023 ( 3, 2) [001266] ------------ * LCL_VAR byref V105 tmp96 u:3 $2e7 + 0 New addressing mode node: [001504] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] ------------ t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref Addressing mode: Base N030 ( 3, 2) [001273] ------------ * LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 + 8 New addressing mode node: [001505] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] ------------ t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int lowering call (before): N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1280 byref arg0 in rcx +--* t1283 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 objp: ====== args: ====== lowering arg : [001468] -A--------L- * STOREIND int lowering arg : [001470] -A--------L- * STOREIND int late: ====== lowering arg : N039 ( 3, 2) [001280] -------N---- * LCL_VAR_ADDR byref V97 tmp88 new node is : [001506] ------------ * PUTARG_REG byref REG rcx lowering arg : N041 ( 3, 2) [001283] -------N---- * LCL_VAR_ADDR byref V99 tmp90 new node is : [001507] ------------ * PUTARG_REG byref REG rdx lowering call (after): N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 No addressing mode: N001 ( 1, 1) [000136] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $81 Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] ------------ t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte Addressing mode: Base N001 ( 1, 1) [001296] ------------ * LCL_VAR byref V00 arg0 u:2 $80 + 0 New addressing mode node: [001508] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [001302] ------------ * LCL_VAR byref V00 arg0 u:2 (last use) $80 + 8 New addressing mode node: [001509] ------------ * LEA(b+8) byref Addressing mode: Base N005 ( 3, 2) [001320] ------------ * LCL_VAR byref V106 tmp97 u:3 $2ee + 0 New addressing mode node: [001510] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] ------------ t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref Addressing mode: Base N012 ( 3, 2) [001327] ------------ * LCL_VAR byref V106 tmp97 u:3 (last use) $2ee + 8 New addressing mode node: [001511] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] ------------ t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int Addressing mode: Base N023 ( 3, 2) [001341] ------------ * LCL_VAR byref V107 tmp98 u:3 $2f0 + 0 New addressing mode node: [001512] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] ------------ t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref Addressing mode: Base N030 ( 3, 2) [001348] ------------ * LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 + 8 New addressing mode node: [001513] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] ------------ t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int lowering call (before): N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1355 byref arg0 in rcx +--* t1358 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 objp: ====== args: ====== lowering arg : [001473] -A--------L- * STOREIND int lowering arg : [001475] -A--------L- * STOREIND int late: ====== lowering arg : N039 ( 3, 2) [001355] -------N---- * LCL_VAR_ADDR byref V97 tmp88 new node is : [001514] ------------ * PUTARG_REG byref REG rcx lowering arg : N041 ( 3, 2) [001358] -------N---- * LCL_VAR_ADDR byref V99 tmp90 new node is : [001515] ------------ * PUTARG_REG byref REG rdx lowering call (after): N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 No addressing mode: N001 ( 1, 1) [000126] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $81 Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] ------------ t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte No addressing mode: N001 ( 1, 1) [000112] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $81 Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] ------------ t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte lowering GT_RETURN N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ============Lower has completed modifying nodes. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 1, 1) [000168] ------------ t168 = CNS_INT int 0 $40 /--* t168 int N003 ( 1, 3) [000170] DA---------- * STORE_LCL_VAR int V09 tmp0 d:3 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t955 ref [001478] -c---------- t1478 = * LEA(b+8) byref /--* t1478 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000987] -------N---- t987 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t987 byref N003 ( 7, 5) [000988] DA---------- * STORE_LCL_VAR byref V72 tmp63 d:3 N004 ( 3, 2) [000990] -------N---- t990 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t990 int N006 ( 3, 3) [000991] DA---------- * STORE_LCL_VAR int V73 tmp64 d:3 ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 /--* t995 byref [001480] -c---------- t1480 = * LEA(b+0) byref /--* t1480 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1001 byref [001481] -c---------- t1481 = * LEA(b+8) byref /--* t1481 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- * EQ void N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- * EQ void N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] -c---------- t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- * EQ void $30e N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 1, 1) [000415] ------------ t415 = CNS_INT int 0 $40 /--* t415 int N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V25 tmp16 d:3 ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c N008 ( 1, 1) [001085] ------------ t1085 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 N009 ( 1, 1) [001086] -c---------- t1086 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t1085 ref +--* t1086 long N010 ( 3, 3) [001087] ------------ t1087 = * ADD byref $VN.Null /--* t1087 byref N013 ( 12, 18) [000433] DA-XG------- * STORE_LCL_VAR byref V26 tmp17 d:3 ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1097 ref [001488] -c---------- t1488 = * LEA(b+8) byref /--* t1488 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000435] ------------ t435 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t435 byref N003 ( 7, 5) [000513] DA---------- * STORE_LCL_VAR byref V82 tmp73 d:3 ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001112] -------N---- t1112 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1112 byref N003 ( 7, 5) [001113] DA---------- * STORE_LCL_VAR byref V76 tmp67 d:3 ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [001115] -------N---- t1115 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1115 byref N003 ( 7, 5) [001116] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:4 N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001129] -------N---- t1129 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1129 byref N003 ( 7, 5) [001130] DA---------- * STORE_LCL_VAR byref V83 tmp74 d:3 N004 ( 3, 2) [001132] -------N---- t1132 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1132 int N006 ( 7, 5) [001133] DA---------- * STORE_LCL_VAR int V84 tmp75 d:3 ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1137 byref [001490] -c---------- t1490 = * LEA(b+0) byref /--* t1490 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1143 byref [001491] -c---------- t1491 = * LEA(b+8) byref /--* t1491 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- * EQ void N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- * EQ void N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] -c---------- t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- * EQ void $31f N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR byref V00 arg0 u:2 $80 /--* t66 byref N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001213] -------N---- t1213 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1213 byref N003 ( 7, 5) [001214] DA---------- * STORE_LCL_VAR byref V87 tmp78 d:3 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1221 byref [001500] -c---------- t1500 = * LEA(b+0) byref /--* t1500 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1227 byref [001501] -c---------- t1501 = * LEA(b+8) byref /--* t1501 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- * EQ void N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- * EQ void N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] -c---------- t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- * EQ void $329 N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1296 byref [001508] -c---------- t1508 = * LEA(b+0) byref /--* t1508 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1302 byref [001509] -c---------- t1509 = * LEA(b+8) byref /--* t1509 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- * EQ void N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- * EQ void N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] -c---------- t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- * EQ void $333 N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 byref ; V01 arg1 byref ; V02 loc0 struct (16) ; V03 loc1 struct (16) ; V04 loc2 bool ; V05 loc3 bool ; V06 loc4 bool ; V07 loc5 bool ; V08 loc6 bool ; V09 tmp0 bool ; V10 tmp1 byref ; V11 tmp2 struct (16) ; V12 tmp3 struct (16) ; V13 tmp4 struct (16) ld-addr-op ; V14 tmp5 int ; V15 tmp6 struct ( 8) ; V16 tmp7 struct (16) ld-addr-op ; V17 tmp8 struct (16) ld-addr-op ; V18 tmp9 int ; V19 tmp10 bool ; V20 tmp11 bool ; V21 tmp12 bool ; V22 tmp13 int ; V23 tmp14 int ; V24 tmp15 int ; V25 tmp16 bool ; V26 tmp17 byref ; V27 tmp18 struct (16) ; V28 tmp19 struct (16) ; V29 tmp20 struct (16) ld-addr-op ; V30 tmp21 int ; V31 tmp22 struct ( 8) ; V32 tmp23 struct (16) ld-addr-op ; V33 tmp24 struct (16) ld-addr-op ; V34 tmp25 int ; V35 tmp26 bool ; V36 tmp27 bool ; V37 tmp28 bool ; V38 tmp29 int ; V39 tmp30 int ; V40 tmp31 int ; V41 tmp32 struct (16) ld-addr-op ; V42 tmp33 struct (16) ld-addr-op ; V43 tmp34 int ; V44 tmp35 bool ; V45 tmp36 bool ; V46 tmp37 bool ; V47 tmp38 int ; V48 tmp39 int ; V49 tmp40 int ; V50 tmp41 struct (16) ld-addr-op ; V51 tmp42 struct (16) ld-addr-op ; V52 tmp43 int ; V53 tmp44 bool ; V54 tmp45 bool ; V55 tmp46 bool ; V56 tmp47 int ; V57 tmp48 int ; V58 tmp49 int ; V59 tmp50 byref do-not-enreg[] V95._pointer(offs=0x00) P-DEP ; V60 tmp51 int do-not-enreg[] V95._length(offs=0x08) P-DEP ; V61 tmp52 byref V02._pointer(offs=0x00) P-INDEP ; V62 tmp53 int V02._length(offs=0x08) P-INDEP ; V63 tmp54 byref V03._pointer(offs=0x00) P-INDEP ; V64 tmp55 int V03._length(offs=0x08) P-INDEP ; V65 tmp56 byref V11._pointer(offs=0x00) P-INDEP ; V66 tmp57 int V11._length(offs=0x08) P-INDEP ; V67 tmp58 byref V12._pointer(offs=0x00) P-INDEP ; V68 tmp59 int V12._length(offs=0x08) P-INDEP ; V69 tmp60 byref V13._pointer(offs=0x00) P-INDEP ; V70 tmp61 int V13._length(offs=0x08) P-INDEP ; V71 tmp62 byref V15._value(offs=0x00) P-INDEP ; V72 tmp63 byref V16._pointer(offs=0x00) P-INDEP ; V73 tmp64 int V16._length(offs=0x08) P-INDEP ; V74 tmp65 byref V17._pointer(offs=0x00) P-INDEP ; V75 tmp66 int V17._length(offs=0x08) P-INDEP ; V76 tmp67 byref V27._pointer(offs=0x00) P-INDEP ; V77 tmp68 int V27._length(offs=0x08) P-INDEP ; V78 tmp69 byref V28._pointer(offs=0x00) P-INDEP ; V79 tmp70 int V28._length(offs=0x08) P-INDEP ; V80 tmp71 byref V29._pointer(offs=0x00) P-INDEP ; V81 tmp72 int V29._length(offs=0x08) P-INDEP ; V82 tmp73 byref V31._value(offs=0x00) P-INDEP ; V83 tmp74 byref V32._pointer(offs=0x00) P-INDEP ; V84 tmp75 int V32._length(offs=0x08) P-INDEP ; V85 tmp76 byref V33._pointer(offs=0x00) P-INDEP ; V86 tmp77 int V33._length(offs=0x08) P-INDEP ; V87 tmp78 byref V41._pointer(offs=0x00) P-INDEP ; V88 tmp79 int V41._length(offs=0x08) P-INDEP ; V89 tmp80 byref V42._pointer(offs=0x00) P-INDEP ; V90 tmp81 int V42._length(offs=0x08) P-INDEP ; V91 tmp82 byref V50._pointer(offs=0x00) P-INDEP ; V92 tmp83 int V50._length(offs=0x08) P-INDEP ; V93 tmp84 byref V51._pointer(offs=0x00) P-INDEP ; V94 tmp85 int V51._length(offs=0x08) P-INDEP ; V95 tmp86 struct (16) do-not-enreg[S] ; V96 tmp87 ref ; V97 tmp88 struct (16) do-not-enreg[XSB] addr-exposed ; V98 tmp89 byref stack-byref ; V99 tmp90 struct (16) do-not-enreg[XSB] addr-exposed ; V100 tmp91 byref stack-byref ; V101 tmp92 byref stack-byref ; V102 tmp93 byref stack-byref ; V103 tmp94 byref ; V104 tmp95 byref stack-byref ; V105 tmp96 byref stack-byref ; V106 tmp97 byref stack-byref ; V107 tmp98 byref stack-byref ; V108 OutArgs lclBlk (32) In fgLocalVarLivenessInit, sorting locals Local V59 should not be enregistered because: field of a dependently promoted struct Local V60 should not be enregistered because: field of a dependently promoted struct refCnt table for 'TryParse': V00 arg0 [ byref]: refCnt = 13, refCntWtd = 17 pref [rcx] V01 arg1 [ byref]: refCnt = 7, refCntWtd = 4.50 pref [rdx] V61 tmp52 [ byref]: refCnt = 9, refCntWtd = 4.25 V62 tmp53 [ int]: refCnt = 5, refCntWtd = 3.75 V05 loc3 [ bool]: refCnt = 6, refCntWtd = 3.50 V96 tmp87 [ ref]: refCnt = 12, refCntWtd = 3 V75 tmp66 [ int]: refCnt = 4, refCntWtd = 2.50 V64 tmp55 [ int]: refCnt = 5, refCntWtd = 2.25 V09 tmp0 [ bool]: refCnt = 2, refCntWtd = 2 V19 tmp10 [ bool]: refCnt = 2, refCntWtd = 2 V63 tmp54 [ byref]: refCnt = 4, refCntWtd = 1.75 V21 tmp12 [ bool]: refCnt = 4, refCntWtd = 1.75 V86 tmp77 [ int]: refCnt = 4, refCntWtd = 1.50 V90 tmp81 [ int]: refCnt = 4, refCntWtd = 1.50 V94 tmp85 [ int]: refCnt = 4, refCntWtd = 1.50 V10 tmp1 [ byref]: refCnt = 3, refCntWtd = 1.50 V98 tmp89 [ byref]: refCnt = 3, refCntWtd = 1.50 V100 tmp91 [ byref]: refCnt = 3, refCntWtd = 1.50 V101 tmp92 [ byref]: refCnt = 3, refCntWtd = 1.50 V102 tmp93 [ byref]: refCnt = 3, refCntWtd = 1.50 V104 tmp95 [ byref]: refCnt = 3, refCntWtd = 1.50 V105 tmp96 [ byref]: refCnt = 3, refCntWtd = 1.50 V106 tmp97 [ byref]: refCnt = 3, refCntWtd = 1.50 V107 tmp98 [ byref]: refCnt = 3, refCntWtd = 1.50 V37 tmp28 [ bool]: refCnt = 4, refCntWtd = 1.25 V46 tmp37 [ bool]: refCnt = 4, refCntWtd = 1.25 V55 tmp46 [ bool]: refCnt = 4, refCntWtd = 1.25 V88 tmp79 [ int]: refCnt = 3, refCntWtd = 1.25 V92 tmp83 [ int]: refCnt = 3, refCntWtd = 1.25 V67 tmp58 [ byref]: refCnt = 2, refCntWtd = 1.25 V74 tmp65 [ byref]: refCnt = 2, refCntWtd = 1.25 V68 tmp59 [ int]: refCnt = 2, refCntWtd = 1.25 V26 tmp17 [ byref]: refCnt = 2, refCntWtd = 1 V25 tmp16 [ bool]: refCnt = 2, refCntWtd = 1 V35 tmp26 [ bool]: refCnt = 2, refCntWtd = 1 V44 tmp35 [ bool]: refCnt = 2, refCntWtd = 1 V53 tmp44 [ bool]: refCnt = 2, refCntWtd = 1 V72 tmp63 [ byref]: refCnt = 1, refCntWtd = 1 V103 tmp94 [ byref]: refCnt = 1, refCntWtd = 1 V73 tmp64 [ int]: refCnt = 1, refCntWtd = 1 V14 tmp5 [ int]: refCnt = 3, refCntWtd = 0.75 V30 tmp21 [ int]: refCnt = 3, refCntWtd = 0.75 V85 tmp76 [ byref]: refCnt = 2, refCntWtd = 0.75 V89 tmp80 [ byref]: refCnt = 2, refCntWtd = 0.75 V91 tmp82 [ byref]: refCnt = 2, refCntWtd = 0.75 V93 tmp84 [ byref]: refCnt = 2, refCntWtd = 0.75 V79 tmp70 [ int]: refCnt = 2, refCntWtd = 0.75 V65 tmp56 [ byref]: refCnt = 2, refCntWtd = 0.50 V71 tmp62 [ byref]: refCnt = 2, refCntWtd = 0.50 V20 tmp11 [ bool]: refCnt = 2, refCntWtd = 0.50 V36 tmp27 [ bool]: refCnt = 2, refCntWtd = 0.50 V45 tmp36 [ bool]: refCnt = 2, refCntWtd = 0.50 V54 tmp45 [ bool]: refCnt = 2, refCntWtd = 0.50 V66 tmp57 [ int]: refCnt = 2, refCntWtd = 0.50 V77 tmp68 [ int]: refCnt = 2, refCntWtd = 0.50 V83 tmp74 [ byref]: refCnt = 1, refCntWtd = 0.50 V87 tmp78 [ byref]: refCnt = 1, refCntWtd = 0.50 V84 tmp75 [ int]: refCnt = 1, refCntWtd = 0.50 V76 tmp67 [ byref]: refCnt = 1, refCntWtd = 0.25 V78 tmp69 [ byref]: refCnt = 1, refCntWtd = 0.25 V82 tmp73 [ byref]: refCnt = 1, refCntWtd = 0.25 V97 tmp88 [struct]: refCnt = 15, refCntWtd = 12 V99 tmp90 [struct]: refCnt = 12, refCntWtd = 8 V108 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(16)={ V61 V62 V96 V75 V09 V19 V10 V67 V74 V68 V72 V73 V14 V65 V71 V66} + ByrefExposed* + GcHeap* BB05 USE(0)={ } DEF(1)={V21} BB06 USE(1)={V75 } DEF(1)={ V20} BB07 USE(0)={ } DEF(1)={V21} BB08 USE(4)={V61 V62 V75 V74} + ByrefExposed + GcHeap DEF(3)={ V21 V98 V100 } + ByrefExposed* + GcHeap* BB09 USE(1)={V21} DEF(0)={ } BB10 USE(1)={V01 } DEF(1)={ V05} BB11 USE(2)={V00 V61 } + ByrefExposed + GcHeap DEF(16)={ V96 V64 V63 V86 V26 V25 V35 V30 V85 V79 V77 V83 V84 V76 V78 V82} + ByrefExposed* + GcHeap* BB15 USE(0)={ } DEF(1)={V37} BB16 USE(1)={V86 } DEF(1)={ V36} BB17 USE(0)={ } DEF(1)={V37} BB18 USE(4)={V61 V64 V86 V85} + ByrefExposed + GcHeap DEF(3)={ V101 V102 V37 } + ByrefExposed* + GcHeap* BB19 USE(1)={V37} DEF(0)={ } BB20 USE(1)={V01 } DEF(1)={ V05} BB21 USE(3)={V00 V62 V63 } + ByrefExposed + GcHeap DEF(6)={ V90 V88 V44 V103 V89 V87} + ByrefExposed* + GcHeap* BB22 USE(0)={ } DEF(1)={V46} BB23 USE(1)={V90 } DEF(1)={ V45} BB24 USE(0)={ } DEF(1)={V46} BB25 USE(4)={V63 V90 V88 V89} + ByrefExposed + GcHeap DEF(3)={ V104 V105 V46 } + ByrefExposed* + GcHeap* BB26 USE(1)={V46} DEF(0)={ } BB27 USE(1)={V01 } DEF(1)={ V05} BB28 USE(3)={V00 V64 V63 } + ByrefExposed + GcHeap DEF(5)={ V94 V92 V53 V91 V93} BB29 USE(0)={ } DEF(1)={V55} BB30 USE(1)={V94 } DEF(1)={ V54} BB31 USE(0)={ } DEF(1)={V55} BB32 USE(4)={V94 V92 V91 V93} + ByrefExposed + GcHeap DEF(3)={ V106 V107 V55 } + ByrefExposed* + GcHeap* BB33 USE(1)={V55} DEF(0)={ } BB34 USE(1)={V01 } DEF(1)={ V05} BB35 USE(1)={V01 } DEF(1)={ V05} BB36 USE(1)={V05} DEF(0)={ } ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap BB05 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap BB06 IN (6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap BB07 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap BB08 IN (6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21 } + ByrefExposed + GcHeap BB09 IN (5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap OUT(4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap BB10 IN (1)={V01 } OUT(1)={ V05} BB11 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap BB15 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap BB16 IN (8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap OUT(8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap BB17 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap BB18 IN (8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37 } + ByrefExposed + GcHeap BB19 IN (6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap OUT(5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap BB20 IN (1)={V01 } OUT(1)={ V05} BB21 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap BB22 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap BB23 IN (7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap OUT(7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap BB24 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap BB25 IN (7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46 } + ByrefExposed + GcHeap BB26 IN (5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap OUT(4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap BB27 IN (1)={V01 } OUT(1)={ V05} BB28 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={ V01 V94 V92 V91 V93} + ByrefExposed + GcHeap BB29 IN (1)={V01 } OUT(2)={V01 V55} BB30 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap BB31 IN (1)={V01 } OUT(2)={V01 V55} BB32 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(2)={V01 V55 } BB33 IN (2)={V01 V55} OUT(1)={V01 } BB34 IN (1)={V01 } OUT(1)={ V05} BB35 IN (1)={V01 } OUT(1)={ V05} BB36 IN (1)={V05} OUT(0)={ } Removing dead store: N006 ( 3, 3) [000991] DA---------- * STORE_LCL_VAR int V73 tmp64 d:3 (last use) New refCnts for V73: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N004 ( 3, 2) [000990] -------N---- * LCL_VAR int V62 tmp53 u:3 $3c0 New refCnts for V62: refCnt = 4, refCntWtd = 2.75 Removing dead store: N003 ( 7, 5) [000988] DA---------- * STORE_LCL_VAR byref V72 tmp63 d:3 (last use) New refCnts for V72: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [000987] -------N---- * LCL_VAR byref V61 tmp52 u:3 $VN.Null New refCnts for V61: refCnt = 8, refCntWtd = 3.25 Removing dead store: N003 ( 1, 3) [000170] DA---------- * STORE_LCL_VAR int V09 tmp0 d:3 (last use) New refCnts for V09: refCnt = 1, refCntWtd = 1 Removing dead node: N001 ( 1, 1) [000168] ------------ * CNS_INT int 0 $40 Removing dead store: N006 ( 7, 5) [001133] DA---------- * STORE_LCL_VAR int V84 tmp75 d:3 (last use) New refCnts for V84: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N004 ( 3, 2) [001132] -------N---- * LCL_VAR int V64 tmp55 u:3 $3c2 New refCnts for V64: refCnt = 4, refCntWtd = 1.75 Removing dead store: N003 ( 7, 5) [001130] DA---------- * STORE_LCL_VAR byref V83 tmp74 d:3 (last use) New refCnts for V83: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [001129] -------N---- * LCL_VAR byref V61 tmp52 u:3 $VN.Null New refCnts for V61: refCnt = 7, refCntWtd = 2.75 Removing dead store: N003 ( 7, 5) [001116] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:4 (last use) New refCnts for V78: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [001115] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null New refCnts for V61: refCnt = 6, refCntWtd = 2.25 Removing dead store: N003 ( 7, 5) [001113] DA---------- * STORE_LCL_VAR byref V76 tmp67 d:3 (last use) New refCnts for V76: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [001112] -------N---- * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null New refCnts for V61: refCnt = 5, refCntWtd = 1.75 Removing dead store: N003 ( 7, 5) [000513] DA---------- * STORE_LCL_VAR byref V82 tmp73 d:3 (last use) New refCnts for V82: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [000435] ------------ * LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null New refCnts for V61: refCnt = 4, refCntWtd = 1.25 Removing dead store: N013 ( 12, 18) [000433] DA-XG------- * STORE_LCL_VAR byref V26 tmp17 d:3 (last use) New refCnts for V26: refCnt = 1, refCntWtd = 0 Removing dead node: N010 ( 3, 3) [001087] ------------ * ADD byref $VN.Null Removing dead node: N009 ( 1, 1) [001086] ------------ * CNS_INT long 12 field offset Fseq[_firstChar] $280 Removing dead LclVar use: N008 ( 1, 1) [001085] ------------ * LCL_VAR ref V96 tmp87 u:3 (last use) $184 New refCnts for V96: refCnt = 11, refCntWtd = 2.50 Removing dead store: N003 ( 5, 4) [000417] DA---------- * STORE_LCL_VAR int V25 tmp16 d:3 (last use) New refCnts for V25: refCnt = 1, refCntWtd = 0.50 Removing dead node: N001 ( 1, 1) [000415] ------------ * CNS_INT int 0 $40 Removing dead store: N003 ( 7, 5) [001214] DA---------- * STORE_LCL_VAR byref V87 tmp78 d:3 (last use) New refCnts for V87: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 3, 2) [001213] -------N---- * LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null New refCnts for V63: refCnt = 3, refCntWtd = 1.25 Removing dead store: N003 ( 5, 4) [001206] DA--------L- * STORE_LCL_VAR byref V103 tmp94 d:3 (last use) New refCnts for V103: refCnt = 0, refCntWtd = 0 node is a late arg; replacing with NOP Removing dead LclVar use: N001 ( 1, 1) [000066] ------------ * LCL_VAR byref V00 arg0 u:2 $80 New refCnts for V00: refCnt = 12, refCntWtd = 16 In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal) *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Liveness pass finished after lowering, IR: lvasortagain = 0 -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t955 ref [001478] -c---------- t1478 = * LEA(b+8) byref /--* t1478 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 /--* t995 byref [001480] -c---------- t1480 = * LEA(b+0) byref /--* t1480 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1001 byref [001481] -c---------- t1481 = * LEA(b+8) byref /--* t1481 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- * EQ void N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- * EQ void N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] -c---------- t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- * EQ void $30e N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1097 ref [001488] -c---------- t1488 = * LEA(b+8) byref /--* t1488 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1137 byref [001490] -c---------- t1490 = * LEA(b+0) byref /--* t1490 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1143 byref [001491] -c---------- t1491 = * LEA(b+8) byref /--* t1491 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- * EQ void N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- * EQ void N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] -c---------- t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- * EQ void $31f N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N003 ( 5, 4) [001206] -----O----L- NOP void N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1221 byref [001500] -c---------- t1500 = * LEA(b+0) byref /--* t1500 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1227 byref [001501] -c---------- t1501 = * LEA(b+8) byref /--* t1501 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- * EQ void N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- * EQ void N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] -c---------- t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- * EQ void $329 N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1296 byref [001508] -c---------- t1508 = * LEA(b+0) byref /--* t1508 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1302 byref [001509] -c---------- t1509 = * LEA(b+8) byref /--* t1509 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- * EQ void N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- * EQ void N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] -c---------- t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- * EQ void $333 N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** Exiting Lowering Trees after Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t955 ref [001478] -c---------- t1478 = * LEA(b+8) byref /--* t1478 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 /--* t995 byref [001480] -c---------- t1480 = * LEA(b+0) byref /--* t1480 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1001 byref [001481] -c---------- t1481 = * LEA(b+8) byref /--* t1481 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- * EQ void N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- * EQ void N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] -c---------- t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- * EQ void $30e N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1097 ref [001488] -c---------- t1488 = * LEA(b+8) byref /--* t1488 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1137 byref [001490] -c---------- t1490 = * LEA(b+0) byref /--* t1490 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1143 byref [001491] -c---------- t1491 = * LEA(b+8) byref /--* t1491 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- * EQ void N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- * EQ void N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] -c---------- t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- * EQ void $31f N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N003 ( 5, 4) [001206] -----O----L- NOP void N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1221 byref [001500] -c---------- t1500 = * LEA(b+0) byref /--* t1500 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1227 byref [001501] -c---------- t1501 = * LEA(b+8) byref /--* t1501 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- * EQ void N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- * EQ void N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] -c---------- t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- * EQ void $329 N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1296 byref [001508] -c---------- t1508 = * LEA(b+0) byref /--* t1508 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1302 byref [001509] -c---------- t1509 = * LEA(b+8) byref /--* t1509 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- * EQ void N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- * EQ void N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] -c---------- t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- * EQ void $333 N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In StackLevelSetter Trees before StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t955 ref [001478] -c---------- t1478 = * LEA(b+8) byref /--* t1478 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 /--* t995 byref [001480] -c---------- t1480 = * LEA(b+0) byref /--* t1480 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1001 byref [001481] -c---------- t1481 = * LEA(b+8) byref /--* t1481 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- * EQ void N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- * EQ void N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] -c---------- t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- * EQ void $30e N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1097 ref [001488] -c---------- t1488 = * LEA(b+8) byref /--* t1488 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1137 byref [001490] -c---------- t1490 = * LEA(b+0) byref /--* t1490 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1143 byref [001491] -c---------- t1491 = * LEA(b+8) byref /--* t1491 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- * EQ void N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- * EQ void N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] -c---------- t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- * EQ void $31f N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N003 ( 5, 4) [001206] -----O----L- NOP void N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1221 byref [001500] -c---------- t1500 = * LEA(b+0) byref /--* t1500 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1227 byref [001501] -c---------- t1501 = * LEA(b+8) byref /--* t1501 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- * EQ void N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- * EQ void N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] -c---------- t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- * EQ void $329 N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1296 byref [001508] -c---------- t1508 = * LEA(b+0) byref /--* t1508 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1302 byref [001509] -c---------- t1509 = * LEA(b+8) byref /--* t1509 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- * EQ void N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- * EQ void N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] -c---------- t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- * EQ void $333 N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** Exiting StackLevelSetter Trees after StackLevelSetter -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t947 ref N004 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 N005 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 $180 /--* t940 ref N006 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte $241 N008 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 (last use) $180 N009 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] $280 /--* t943 ref +--* t944 long N010 ( 5, 4) [000945] ------------ t945 = * ADD byref $VN.Null /--* t945 byref N013 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] $180 /--* t955 ref [001478] -c---------- t1478 = * LEA(b+8) byref /--* t1478 byref N005 ( 6, 13) [000236] x---G------- t236 = * IND int /--* t236 int N007 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 N003 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 N004 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 $40 /--* t240 int +--* t250 int N005 ( 8, 4) [000251] ------------ t251 = * GE int /--* t251 int [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N007 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 (last use) $VN.Null /--* t188 byref N003 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 (last use) $VN.Null /--* t970 byref N003 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 (last use) /--* t276 int N003 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 N001 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 (last use) $VN.Null /--* t973 byref N003 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 N004 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 (last use) /--* t976 int N006 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 N001 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 (last use) $VN.Null /--* t980 byref N003 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 N004 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 (last use) $3c0 /--* t983 int N006 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 $80 /--* t995 byref [001480] -c---------- t1480 = * LEA(b+0) byref /--* t1480 byref N004 ( 4, 3) [000998] x----------- t998 = * IND byref /--* t998 byref N006 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 N007 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1001 byref [001481] -c---------- t1481 = * LEA(b+8) byref /--* t1481 byref N010 ( 4, 4) [001004] x----------- t1004 = * IND int /--* t1004 int N012 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 $3c0 N002 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 /--* t295 int +--* t393 int N003 ( 6, 3) [000297] ------------ t297 = * NE int /--* t297 int N005 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 (last use) N002 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 $40 /--* t303 int +--* t304 int N003 ( 3, 3) [000305] J------N---- * EQ void N004 ( 5, 5) [000306] ------------ * JTRUE void ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 $40 /--* t348 int N003 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 N002 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 $40 /--* t406 int +--* t314 int N003 ( 6, 3) [000315] ------------ t315 = * EQ int /--* t315 int N005 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 (last use) N002 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 $40 /--* t319 int +--* t320 int N003 ( 5, 4) [000321] J------N---- * EQ void N004 ( 7, 6) [000322] ------------ * JTRUE void ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 $41 /--* t343 int N003 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc N001 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 /--* t1016 byref N004 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 N005 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 $2ca /--* t1019 byref [001482] -c---------- t1482 = * LEA(b+0) byref N009 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1482 byref +--* t1023 byref [001456] -A---------- * STOREIND byref N012 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 (last use) $2ca /--* t1026 byref [001483] -c---------- t1483 = * LEA(b+8) byref N016 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 $3c0 /--* t1483 byref +--* t1030 int [001457] -A--------L- * STOREIND int N019 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 /--* t1037 byref N022 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 N023 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 $2cc /--* t1040 byref [001484] -c---------- t1484 = * LEA(b+0) byref N027 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 (last use) /--* t1484 byref +--* t1044 byref [001458] -A---------- * STOREIND byref N030 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 (last use) $2cc /--* t1047 byref [001485] -c---------- t1485 = * LEA(b+8) byref N034 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 (last use) /--* t1485 byref +--* t1051 int [001459] -A--------L- * STOREIND int N039 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 /--* t1054 byref [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 /--* t1057 byref [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N045 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N046 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 $40 /--* t327 int +--* t334 int N047 ( 81, 55) [000335] ---XG------- t335 = * EQ int $30d /--* t335 int N049 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 (last use) $500 N002 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N003 ( 3, 3) [000027] J------N---- * EQ void $30e N004 ( 5, 5) [000028] ------------ * JTRUE void ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 N001 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 $41 /--* t156 byref +--* t157 int [001460] -A-XG------- * STOREIND byte ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b N001 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 $41 /--* t161 int N003 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1089 ref N004 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 N005 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 (last use) $184 /--* t1082 ref N006 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte $24c ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] $184 /--* t1097 ref [001488] -c---------- t1488 = * LEA(b+8) byref /--* t1488 byref N005 ( 6, 13) [000483] x---G------- t483 = * IND int /--* t483 int N007 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f N003 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 N004 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 $40 /--* t487 int +--* t497 int N005 ( 8, 4) [000498] ------------ t498 = * GE int /--* t498 int [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N007 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f N001 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 (last use) /--* t523 int N003 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f N004 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 (last use) /--* t1118 int N006 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 N001 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 $VN.Null /--* t1122 byref N003 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 N004 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 (last use) $3c2 /--* t1125 int N006 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1137 byref [001490] -c---------- t1490 = * LEA(b+0) byref /--* t1490 byref N004 ( 4, 3) [001140] x----------- t1140 = * IND byref /--* t1140 byref N006 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 N007 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1143 byref [001491] -c---------- t1491 = * LEA(b+8) byref /--* t1491 byref N010 ( 4, 4) [001146] x----------- t1146 = * IND int /--* t1146 int N012 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 $3c2 N002 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 /--* t542 int +--* t640 int N003 ( 10, 5) [000544] ------------ t544 = * NE int /--* t544 int N005 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 (last use) N002 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 $40 /--* t550 int +--* t551 int N003 ( 5, 4) [000552] J------N---- * EQ void N004 ( 7, 6) [000553] ------------ * JTRUE void ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 $40 /--* t595 int N003 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 N002 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 $40 /--* t653 int +--* t561 int N003 ( 8, 4) [000562] ------------ t562 = * EQ int /--* t562 int N005 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 (last use) N002 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 $40 /--* t566 int +--* t567 int N003 ( 5, 4) [000568] J------N---- * EQ void N004 ( 7, 6) [000569] ------------ * JTRUE void ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 $41 /--* t590 int N003 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a N001 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 /--* t1158 byref N004 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 N005 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 $2da /--* t1161 byref [001492] -c---------- t1492 = * LEA(b+0) byref N009 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 (last use) $VN.Null /--* t1492 byref +--* t1165 byref [001461] -A---------- * STOREIND byref N012 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 (last use) $2da /--* t1168 byref [001493] -c---------- t1493 = * LEA(b+8) byref N016 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 $3c2 /--* t1493 byref +--* t1172 int [001462] -A--------L- * STOREIND int N019 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 /--* t1179 byref N022 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 N023 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 $2dc /--* t1182 byref [001494] -c---------- t1494 = * LEA(b+0) byref N027 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 (last use) /--* t1494 byref +--* t1186 byref [001463] -A---------- * STOREIND byref N030 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 (last use) $2dc /--* t1189 byref [001495] -c---------- t1495 = * LEA(b+8) byref N034 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 (last use) /--* t1495 byref +--* t1193 int [001464] -A--------L- * STOREIND int N039 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 /--* t1196 byref [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 /--* t1199 byref [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N045 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N046 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 $40 /--* t574 int +--* t581 int N047 ( 85, 57) [000582] ---XG------- t582 = * EQ int $31e /--* t582 int N049 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 (last use) $501 N002 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 $40 /--* t55 int +--* t56 int N003 ( 5, 4) [000057] J------N---- * EQ void $31f N004 ( 7, 6) [000058] ------------ * JTRUE void ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 N001 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 $40 /--* t146 byref +--* t147 int [001465] -A-XG------- * STOREIND byte ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b N001 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 $41 /--* t151 int N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f N003 ( 5, 4) [001206] -----O----L- NOP void N004 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 $80 /--* t61 byref N005 ( 3, 2) [000064] xc-----N---- t64 = * IND struct N006 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 /--* t1203 byref +--* t64 struct [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) N010 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1207 byref [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N011 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 /--* t1209 byref [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N015 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 N004 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 (last use) $3c0 /--* t1216 int N006 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1221 byref [001500] -c---------- t1500 = * LEA(b+0) byref /--* t1500 byref N004 ( 4, 3) [001224] x----------- t1224 = * IND byref /--* t1224 byref N006 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 N007 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1227 byref [001501] -c---------- t1501 = * LEA(b+8) byref /--* t1501 byref N010 ( 4, 4) [001230] x----------- t1230 = * IND int /--* t1230 int N012 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 $3c0 N002 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 /--* t672 int +--* t770 int N003 ( 10, 5) [000674] ------------ t674 = * NE int /--* t674 int N005 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 (last use) N002 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 $40 /--* t680 int +--* t681 int N003 ( 5, 4) [000682] J------N---- * EQ void N004 ( 7, 6) [000683] ------------ * JTRUE void ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 $40 /--* t725 int N003 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $40 /--* t783 int +--* t691 int N003 ( 8, 4) [000692] ------------ t692 = * EQ int /--* t692 int N005 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 (last use) N002 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 $40 /--* t696 int +--* t697 int N003 ( 5, 4) [000698] J------N---- * EQ void N004 ( 7, 6) [000699] ------------ * JTRUE void ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 $41 /--* t720 int N003 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 ------------ BB25 [047..048), preds={BB23} succs={BB26} ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 /--* t1242 byref N004 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 N005 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 $2e5 /--* t1245 byref [001502] -c---------- t1502 = * LEA(b+0) byref N009 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 $VN.Null /--* t1502 byref +--* t1249 byref [001467] -A---------- * STOREIND byref N012 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 (last use) $2e5 /--* t1252 byref [001503] -c---------- t1503 = * LEA(b+8) byref N016 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 (last use) $3c0 /--* t1503 byref +--* t1256 int [001468] -A--------L- * STOREIND int N019 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 /--* t1263 byref N022 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 N023 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 $2e7 /--* t1266 byref [001504] -c---------- t1504 = * LEA(b+0) byref N027 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 (last use) /--* t1504 byref +--* t1270 byref [001469] -A---------- * STOREIND byref N030 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 (last use) $2e7 /--* t1273 byref [001505] -c---------- t1505 = * LEA(b+8) byref N034 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 (last use) /--* t1505 byref +--* t1277 int [001470] -A--------L- * STOREIND int N039 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 /--* t1280 byref [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 /--* t1283 byref [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N045 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N046 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 $40 /--* t704 int +--* t711 int N047 ( 85, 57) [000712] ---XG------- t712 = * EQ int $328 /--* t712 int N049 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 (last use) $502 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 $40 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] J------N---- * EQ void $329 N004 ( 7, 6) [000088] ------------ * JTRUE void ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 N001 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 $41 /--* t136 byref +--* t137 int [001471] -A-XG------- * STOREIND byte ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 N001 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 $41 /--* t141 int N003 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 (last use) $VN.Null /--* t1288 byref N003 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 N004 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 (last use) $3c2 /--* t1291 int N006 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 $80 /--* t1296 byref [001508] -c---------- t1508 = * LEA(b+0) byref /--* t1508 byref N004 ( 4, 3) [001299] x----------- t1299 = * IND byref /--* t1299 byref N006 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 N007 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 (last use) $80 /--* t1302 byref [001509] -c---------- t1509 = * LEA(b+8) byref /--* t1509 byref N010 ( 4, 4) [001305] x----------- t1305 = * IND int /--* t1305 int N012 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 $3c2 N002 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 /--* t802 int +--* t900 int N003 ( 10, 5) [000804] ------------ t804 = * NE int /--* t804 int N005 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 (last use) N002 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 $40 /--* t810 int +--* t811 int N003 ( 5, 4) [000812] J------N---- * EQ void N004 ( 7, 6) [000813] ------------ * JTRUE void ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 $40 /--* t855 int N003 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 N002 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 $40 /--* t913 int +--* t821 int N003 ( 8, 4) [000822] ------------ t822 = * EQ int /--* t822 int N005 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 (last use) N002 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 $40 /--* t826 int +--* t827 int N003 ( 5, 4) [000828] J------N---- * EQ void N004 ( 7, 6) [000829] ------------ * JTRUE void ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 $41 /--* t850 int N003 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 ------------ BB32 [05C..05D), preds={BB30} succs={BB33} ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c N001 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 /--* t1317 byref N004 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 N005 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 $2ee /--* t1320 byref [001510] -c---------- t1510 = * LEA(b+0) byref N009 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 (last use) $VN.Null /--* t1510 byref +--* t1324 byref [001472] -A---------- * STOREIND byref N012 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 (last use) $2ee /--* t1327 byref [001511] -c---------- t1511 = * LEA(b+8) byref N016 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 (last use) $3c2 /--* t1511 byref +--* t1331 int [001473] -A--------L- * STOREIND int N019 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 /--* t1338 byref N022 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 N023 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 $2f0 /--* t1341 byref [001512] -c---------- t1512 = * LEA(b+0) byref N027 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 (last use) /--* t1512 byref +--* t1345 byref [001474] -A---------- * STOREIND byref N030 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 (last use) $2f0 /--* t1348 byref [001513] -c---------- t1513 = * LEA(b+8) byref N034 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 (last use) /--* t1513 byref +--* t1352 int [001475] -A--------L- * STOREIND int N039 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 /--* t1355 byref [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N041 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 /--* t1358 byref [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N045 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N046 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 $40 /--* t834 int +--* t841 int N047 ( 85, 57) [000842] ---XG------- t842 = * EQ int $332 /--* t842 int N049 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 N001 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 (last use) $503 N002 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 $40 /--* t106 int +--* t107 int N003 ( 5, 4) [000108] J------N---- * EQ void $333 N004 ( 7, 6) [000109] ------------ * JTRUE void ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 $40 /--* t126 byref +--* t127 int [001476] -A-XG------- * STOREIND byte ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 $41 /--* t131 int N003 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 ------------ BB35 [071..078), preds={BB33} succs={BB36} ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 N001 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 (last use) $81 N003 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 $40 /--* t112 byref +--* t113 int [001477] -A-XG------- * STOREIND byte ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 $40 /--* t117 int N003 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 N001 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 (last use) $504 /--* t122 int N002 ( 2, 2) [000123] ------------ * RETURN int $1fb ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V00} {V09 V10 V14 V19 V61 V62 V65 V66 V67 V68 V71 V72 V73 V74 V75 V96} {V00 V01} {V00 V01 V61 V62 V74 V75} BB05 use def in out {} {V21} {V00 V01 V61 V62} {V00 V01 V21 V61 V62} BB06 use def in out {V75} {V20} {V00 V01 V61 V62 V74 V75} {V00 V01 V61 V62 V74 V75} BB07 use def in out {} {V21} {V00 V01 V61 V62} {V00 V01 V21 V61 V62} BB08 use def in out {V61 V62 V74 V75} {V21 V98 V100} {V00 V01 V61 V62 V74 V75} {V00 V01 V21 V61 V62} BB09 use def in out {V21} {} {V00 V01 V21 V61 V62} {V00 V01 V61 V62} BB10 use def in out {V01} {V05} {V01} {V05} BB11 use def in out {V00 V61} {V25 V26 V30 V35 V63 V64 V76 V77 V78 V79 V82 V83 V84 V85 V86 V96} {V00 V01 V61 V62} {V00 V01 V61 V62 V63 V64 V85 V86} BB15 use def in out {} {V37} {V00 V01 V62 V63 V64} {V00 V01 V37 V62 V63 V64} BB16 use def in out {V86} {V36} {V00 V01 V61 V62 V63 V64 V85 V86} {V00 V01 V61 V62 V63 V64 V85 V86} BB17 use def in out {} {V37} {V00 V01 V62 V63 V64} {V00 V01 V37 V62 V63 V64} BB18 use def in out {V61 V64 V85 V86} {V37 V101 V102} {V00 V01 V61 V62 V63 V64 V85 V86} {V00 V01 V37 V62 V63 V64} BB19 use def in out {V37} {} {V00 V01 V37 V62 V63 V64} {V00 V01 V62 V63 V64} BB20 use def in out {V01} {V05} {V01} {V05} BB21 use def in out {V00 V62 V63} {V44 V87 V88 V89 V90 V103} {V00 V01 V62 V63 V64} {V00 V01 V63 V64 V88 V89 V90} BB22 use def in out {} {V46} {V00 V01 V63 V64} {V00 V01 V46 V63 V64} BB23 use def in out {V90} {V45} {V00 V01 V63 V64 V88 V89 V90} {V00 V01 V63 V64 V88 V89 V90} BB24 use def in out {} {V46} {V00 V01 V63 V64} {V00 V01 V46 V63 V64} BB25 use def in out {V63 V88 V89 V90} {V46 V104 V105} {V00 V01 V63 V64 V88 V89 V90} {V00 V01 V46 V63 V64} BB26 use def in out {V46} {} {V00 V01 V46 V63 V64} {V00 V01 V63 V64} BB27 use def in out {V01} {V05} {V01} {V05} BB28 use def in out {V00 V63 V64} {V53 V91 V92 V93 V94} {V00 V01 V63 V64} {V01 V91 V92 V93 V94} BB29 use def in out {} {V55} {V01} {V01 V55} BB30 use def in out {V94} {V54} {V01 V91 V92 V93 V94} {V01 V91 V92 V93 V94} BB31 use def in out {} {V55} {V01} {V01 V55} BB32 use def in out {V91 V92 V93 V94} {V55 V106 V107} {V01 V91 V92 V93 V94} {V01 V55} BB33 use def in out {V55} {} {V01 V55} {V01} BB34 use def in out {V01} {V05} {V01} {V05} BB35 use def in out {V01} {V05} {V01} {V05} BB36 use def in out {V05} {} {V05} {} Interval 0: RefPositions {} physReg:NA Preferences=[allInt] Interval 1: RefPositions {} physReg:NA Preferences=[allInt] Interval 2: RefPositions {} physReg:NA Preferences=[allInt] Interval 3: RefPositions {} physReg:NA Preferences=[allInt] Interval 4: RefPositions {} physReg:NA Preferences=[allInt] Interval 5: RefPositions {} physReg:NA Preferences=[allInt] Interval 6: RefPositions {} physReg:NA Preferences=[allInt] Interval 7: RefPositions {} physReg:NA Preferences=[allInt] Interval 8: RefPositions {} physReg:NA Preferences=[allInt] Interval 9: RefPositions {} physReg:NA Preferences=[allInt] Interval 10: RefPositions {} physReg:NA Preferences=[allInt] Interval 11: RefPositions {} physReg:NA Preferences=[allInt] Interval 12: RefPositions {} physReg:NA Preferences=[allInt] Interval 13: RefPositions {} physReg:NA Preferences=[allInt] Interval 14: RefPositions {} physReg:NA Preferences=[allInt] Interval 15: RefPositions {} physReg:NA Preferences=[allInt] Interval 16: RefPositions {} physReg:NA Preferences=[allInt] Interval 17: RefPositions {} physReg:NA Preferences=[allInt] Interval 18: RefPositions {} physReg:NA Preferences=[allInt] Interval 19: RefPositions {} physReg:NA Preferences=[allInt] Interval 20: RefPositions {} physReg:NA Preferences=[allInt] Interval 21: RefPositions {} physReg:NA Preferences=[allInt] Interval 22: RefPositions {} physReg:NA Preferences=[allInt] Interval 23: RefPositions {} physReg:NA Preferences=[allInt] Interval 24: RefPositions {} physReg:NA Preferences=[allInt] Interval 25: RefPositions {} physReg:NA Preferences=[allInt] Interval 26: RefPositions {} physReg:NA Preferences=[allInt] Interval 27: RefPositions {} physReg:NA Preferences=[allInt] Interval 28: RefPositions {} physReg:NA Preferences=[allInt] Interval 29: RefPositions {} physReg:NA Preferences=[allInt] Interval 30: RefPositions {} physReg:NA Preferences=[allInt] Interval 31: RefPositions {} physReg:NA Preferences=[allInt] Interval 32: RefPositions {} physReg:NA Preferences=[allInt] Interval 33: RefPositions {} physReg:NA Preferences=[allInt] Interval 34: RefPositions {} physReg:NA Preferences=[allInt] Interval 35: RefPositions {} physReg:NA Preferences=[allInt] Interval 36: RefPositions {} physReg:NA Preferences=[allInt] Interval 37: RefPositions {} physReg:NA Preferences=[allInt] Interval 38: RefPositions {} physReg:NA Preferences=[allInt] Interval 39: RefPositions {} physReg:NA Preferences=[allInt] Interval 40: RefPositions {} physReg:NA Preferences=[allInt] Interval 41: RefPositions {} physReg:NA Preferences=[allInt] Interval 42: RefPositions {} physReg:NA Preferences=[allInt] Interval 43: RefPositions {} physReg:NA Preferences=[allInt] Interval 44: RefPositions {} physReg:NA Preferences=[allInt] Interval 45: RefPositions {} physReg:NA Preferences=[allInt] Interval 46: RefPositions {} physReg:NA Preferences=[allInt] Interval 47: RefPositions {} physReg:NA Preferences=[allInt] Interval 48: RefPositions {} physReg:NA Preferences=[allInt] Interval 49: RefPositions {} physReg:NA Preferences=[allInt] Interval 50: RefPositions {} physReg:NA Preferences=[allInt] Interval 51: RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB05( 0.25) BB06( 0.25) BB07( 0.25) BB08( 0.25) BB09( 1 ) BB10( 0.50) BB11( 0.50) BB15( 0.25) BB16( 0.25) BB17( 0.25) BB18( 0.25) BB19( 0.50) BB20( 0.50) BB21( 0.50) BB22( 0.25) BB23( 0.25) BB24( 0.25) BB25( 0.25) BB26( 0.50) BB27( 0.50) BB28( 0.50) BB29( 0.25) BB30( 0.25) BB31( 0.25) BB32( 0.25) BB33( 0.50) BB34( 0.50) BB35( 0.50) BB36( 1 ) BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} ===== N000. IL_OFFSET IL offset: 0x1 N000. IL_OFFSET IL offset: 0x1 N001. t947 = CNS_INT(h) 0x421150 [ICON_STR_HDL] N004. V96(t939); t947 N005. V96(t940) N006. NULLCHECK; t940 N008. V96(t943*) N009. CNS_INT 12 field offset Fseq[_firstChar] N010. t945 = ADD ; t943* N013. V10(t186); t945 N000. IL_OFFSET IL offset: 0x1 N001. t955 = CNS_INT(h) 0x421150 [ICON_STR_HDL] N000. t1478 = LEA(b+8) ; t955 N005. t236 = IND ; t1478 N007. V14(t238); t236 N000. IL_OFFSET IL offset: 0x1 N000. IL_OFFSET IL offset: 0x1 N003. V14(t240) N004. CNS_INT 0 N005. t251 = GE ; t240 N000. t1479 = PUTARG_REG; t251 N007. CALL ; t1479 N000. IL_OFFSET IL offset: 0x1 N001. V10(t188*) N003. V71(t266); t188* N000. IL_OFFSET IL offset: 0x1 N001. V71(t970*) N003. V65(t971); t970* N000. IL_OFFSET IL offset: 0x1 N001. V14(t276*) N003. V66(t278); t276* N000. IL_OFFSET IL offset: 0x1 N001. V65(t973*) N003. V67(t974); t973* N004. V66(t976*) N006. V68(t977); t976* N001. V67(t980*) N003. V61(t981); t980* N004. V68(t983*) N006. V62(t984); t983* N000. IL_OFFSET IL offset: 0xc N000. IL_OFFSET IL offset: 0xc N001. V00(t995) N000. t1480 = LEA(b+0) ; t995 N004. t998 = IND ; t1480 N006. V74(t999); t998 N007. V00(t1001) N000. t1481 = LEA(b+8) ; t1001 N010. t1004 = IND ; t1481 N012. V75(t1005); t1004 N000. IL_OFFSET IL offset: 0xc N001. V62(t295) N002. V75(t393) N003. t297 = NE ; t295,t393 N005. V19(t301); t297 N000. IL_OFFSET IL offset: 0xc N001. V19(t303*) N002. CNS_INT 0 N003. EQ ; t303* N004. JTRUE BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ===== N000. IL_OFFSET IL offset: 0xc N001. t348 = CNS_INT 0 N003. V21(t350); t348 BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ===== N000. IL_OFFSET IL offset: 0xc N001. V75(t406) N002. CNS_INT 0 N003. t315 = EQ ; t406 N005. V20(t317); t315 N000. IL_OFFSET IL offset: 0xc N001. V20(t319*) N002. CNS_INT 0 N003. EQ ; t319* N004. JTRUE BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ===== N000. IL_OFFSET IL offset: 0xc N001. CNS_INT 1 N003. V21(t345) BB08 [00C..00D), preds={BB06} succs={BB09} ===== N000. IL_OFFSET IL offset: 0xc N001. t1016 = LCL_VAR_ADDR V97 tmp88 N004. V98(t1018); t1016 N005. V98(t1019) N000. t1482 = LEA(b+0) ; t1019 N009. V61(t1023) N000. STOREIND ; t1482,t1023 N012. V98(t1026*) N000. t1483 = LEA(b+8) ; t1026* N016. V62(t1030) N000. STOREIND ; t1483,t1030 N019. t1037 = LCL_VAR_ADDR V99 tmp90 N022. V100(t1039); t1037 N023. V100(t1040) N000. t1484 = LEA(b+0) ; t1040 N027. V74(t1044*) N000. STOREIND ; t1484,t1044* N030. V100(t1047*) N000. t1485 = LEA(b+8) ; t1047* N034. V75(t1051*) N000. STOREIND ; t1485,t1051* N039. t1054 = LCL_VAR_ADDR V97 tmp88 N000. t1486 = PUTARG_REG; t1054 N041. t1057 = LCL_VAR_ADDR V99 tmp90 N000. t1487 = PUTARG_REG; t1057 N045. t327 = CALL ; t1486,t1487 N046. CNS_INT 0 N047. t335 = EQ ; t327 N049. V21(t337); t335 BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ===== N000. IL_OFFSET IL offset: 0x14 N001. V21(t25*) N002. CNS_INT 0 N003. EQ ; t25* N004. JTRUE BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ===== N000. IL_OFFSET IL offset: 0x18 N001. V01(t156*) N003. CNS_INT 1 N000. STOREIND ; t156* N000. IL_OFFSET IL offset: 0x1b N001. CNS_INT 1 N003. V05(t163) BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} ===== N000. IL_OFFSET IL offset: 0x1f N000. IL_OFFSET IL offset: 0x1f N001. t1089 = CNS_INT(h) 0x421158 [ICON_STR_HDL] N004. V96(t1081); t1089 N005. V96(t1082*) N006. NULLCHECK; t1082* N000. IL_OFFSET IL offset: 0x1f N001. t1097 = CNS_INT(h) 0x421158 [ICON_STR_HDL] N000. t1488 = LEA(b+8) ; t1097 N005. t483 = IND ; t1488 N007. V30(t485); t483 N000. IL_OFFSET IL offset: 0x1f N000. IL_OFFSET IL offset: 0x1f N003. V30(t487) N004. CNS_INT 0 N005. t498 = GE ; t487 N000. t1489 = PUTARG_REG; t498 N007. CALL ; t1489 N000. IL_OFFSET IL offset: 0x1f N000. IL_OFFSET IL offset: 0x1f N000. IL_OFFSET IL offset: 0x1f N001. V30(t523*) N003. V77(t525); t523* N000. IL_OFFSET IL offset: 0x1f N004. V77(t1118*) N006. V79(t1119); t1118* N001. V61(t1122) N003. V63(t1123); t1122 N004. V79(t1125*) N006. V64(t1126); t1125* N000. IL_OFFSET IL offset: 0x2a N000. IL_OFFSET IL offset: 0x2a N001. V00(t1137) N000. t1490 = LEA(b+0) ; t1137 N004. t1140 = IND ; t1490 N006. V85(t1141); t1140 N007. V00(t1143) N000. t1491 = LEA(b+8) ; t1143 N010. t1146 = IND ; t1491 N012. V86(t1147); t1146 N000. IL_OFFSET IL offset: 0x2a N001. V64(t542) N002. V86(t640) N003. t544 = NE ; t542,t640 N005. V35(t548); t544 N000. IL_OFFSET IL offset: 0x2a N001. V35(t550*) N002. CNS_INT 0 N003. EQ ; t550* N004. JTRUE BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ===== N000. IL_OFFSET IL offset: 0x2a N001. t595 = CNS_INT 0 N003. V37(t597); t595 BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ===== N000. IL_OFFSET IL offset: 0x2a N001. V86(t653) N002. CNS_INT 0 N003. t562 = EQ ; t653 N005. V36(t564); t562 N000. IL_OFFSET IL offset: 0x2a N001. V36(t566*) N002. CNS_INT 0 N003. EQ ; t566* N004. JTRUE BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ===== N000. IL_OFFSET IL offset: 0x2a N001. CNS_INT 1 N003. V37(t592) BB18 [02A..02B), preds={BB16} succs={BB19} ===== N000. IL_OFFSET IL offset: 0x2a N001. t1158 = LCL_VAR_ADDR V97 tmp88 N004. V101(t1160); t1158 N005. V101(t1161) N000. t1492 = LEA(b+0) ; t1161 N009. V61(t1165*) N000. STOREIND ; t1492,t1165* N012. V101(t1168*) N000. t1493 = LEA(b+8) ; t1168* N016. V64(t1172) N000. STOREIND ; t1493,t1172 N019. t1179 = LCL_VAR_ADDR V99 tmp90 N022. V102(t1181); t1179 N023. V102(t1182) N000. t1494 = LEA(b+0) ; t1182 N027. V85(t1186*) N000. STOREIND ; t1494,t1186* N030. V102(t1189*) N000. t1495 = LEA(b+8) ; t1189* N034. V86(t1193*) N000. STOREIND ; t1495,t1193* N039. t1196 = LCL_VAR_ADDR V97 tmp88 N000. t1496 = PUTARG_REG; t1196 N041. t1199 = LCL_VAR_ADDR V99 tmp90 N000. t1497 = PUTARG_REG; t1199 N045. t574 = CALL ; t1496,t1497 N046. CNS_INT 0 N047. t582 = EQ ; t574 N049. V37(t584); t582 BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ===== N000. IL_OFFSET IL offset: 0x33 N001. V37(t55*) N002. CNS_INT 0 N003. EQ ; t55* N004. JTRUE BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ===== N000. IL_OFFSET IL offset: 0x38 N001. V01(t146*) N003. CNS_INT 0 N000. STOREIND ; t146* N000. IL_OFFSET IL offset: 0x3b N001. CNS_INT 1 N003. V05(t153) BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ===== N000. IL_OFFSET IL offset: 0x3f N003. NOP N004. V00(t61) N005. t64 = IND ; t61 N006. LCL_VAR_ADDR V97 tmp88 N000. STORE_BLK(16); t64 N010. V00(t1207) N000. t1498 = PUTARG_REG; t1207 N011. t1209 = LCL_VAR_ADDR V97 tmp88 N000. t1499 = PUTARG_REG; t1209 N015. CALL ; t1498,t1499 N000. IL_OFFSET IL offset: 0x47 N004. V62(t1216*) N006. V88(t1217); t1216* N000. IL_OFFSET IL offset: 0x47 N001. V00(t1221) N000. t1500 = LEA(b+0) ; t1221 N004. t1224 = IND ; t1500 N006. V89(t1225); t1224 N007. V00(t1227) N000. t1501 = LEA(b+8) ; t1227 N010. t1230 = IND ; t1501 N012. V90(t1231); t1230 N000. IL_OFFSET IL offset: 0x47 N001. V88(t672) N002. V90(t770) N003. t674 = NE ; t672,t770 N005. V44(t678); t674 N000. IL_OFFSET IL offset: 0x47 N001. V44(t680*) N002. CNS_INT 0 N003. EQ ; t680* N004. JTRUE BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ===== N000. IL_OFFSET IL offset: 0x47 N001. t725 = CNS_INT 0 N003. V46(t727); t725 BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ===== N000. IL_OFFSET IL offset: 0x47 N001. V90(t783) N002. CNS_INT 0 N003. t692 = EQ ; t783 N005. V45(t694); t692 N000. IL_OFFSET IL offset: 0x47 N001. V45(t696*) N002. CNS_INT 0 N003. EQ ; t696* N004. JTRUE BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ===== N000. IL_OFFSET IL offset: 0x47 N001. CNS_INT 1 N003. V46(t722) BB25 [047..048), preds={BB23} succs={BB26} ===== N000. IL_OFFSET IL offset: 0x47 N001. t1242 = LCL_VAR_ADDR V97 tmp88 N004. V104(t1244); t1242 N005. V104(t1245) N000. t1502 = LEA(b+0) ; t1245 N009. V63(t1249) N000. STOREIND ; t1502,t1249 N012. V104(t1252*) N000. t1503 = LEA(b+8) ; t1252* N016. V88(t1256*) N000. STOREIND ; t1503,t1256* N019. t1263 = LCL_VAR_ADDR V99 tmp90 N022. V105(t1265); t1263 N023. V105(t1266) N000. t1504 = LEA(b+0) ; t1266 N027. V89(t1270*) N000. STOREIND ; t1504,t1270* N030. V105(t1273*) N000. t1505 = LEA(b+8) ; t1273* N034. V90(t1277*) N000. STOREIND ; t1505,t1277* N039. t1280 = LCL_VAR_ADDR V97 tmp88 N000. t1506 = PUTARG_REG; t1280 N041. t1283 = LCL_VAR_ADDR V99 tmp90 N000. t1507 = PUTARG_REG; t1283 N045. t704 = CALL ; t1506,t1507 N046. CNS_INT 0 N047. t712 = EQ ; t704 N049. V46(t714); t712 BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ===== N000. IL_OFFSET IL offset: 0x50 N001. V46(t85*) N002. CNS_INT 0 N003. EQ ; t85* N004. JTRUE BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ===== N000. IL_OFFSET IL offset: 0x55 N001. V01(t136*) N003. CNS_INT 1 N000. STOREIND ; t136* N000. IL_OFFSET IL offset: 0x58 N001. CNS_INT 1 N003. V05(t143) BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ===== N000. IL_OFFSET IL offset: 0x5c N001. V63(t1288*) N003. V91(t1289); t1288* N004. V64(t1291*) N006. V92(t1292); t1291* N000. IL_OFFSET IL offset: 0x5c N001. V00(t1296) N000. t1508 = LEA(b+0) ; t1296 N004. t1299 = IND ; t1508 N006. V93(t1300); t1299 N007. V00(t1302*) N000. t1509 = LEA(b+8) ; t1302* N010. t1305 = IND ; t1509 N012. V94(t1306); t1305 N000. IL_OFFSET IL offset: 0x5c N001. V92(t802) N002. V94(t900) N003. t804 = NE ; t802,t900 N005. V53(t808); t804 N000. IL_OFFSET IL offset: 0x5c N001. V53(t810*) N002. CNS_INT 0 N003. EQ ; t810* N004. JTRUE BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ===== N000. IL_OFFSET IL offset: 0x5c N001. t855 = CNS_INT 0 N003. V55(t857); t855 BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ===== N000. IL_OFFSET IL offset: 0x5c N001. V94(t913) N002. CNS_INT 0 N003. t822 = EQ ; t913 N005. V54(t824); t822 N000. IL_OFFSET IL offset: 0x5c N001. V54(t826*) N002. CNS_INT 0 N003. EQ ; t826* N004. JTRUE BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ===== N000. IL_OFFSET IL offset: 0x5c N001. CNS_INT 1 N003. V55(t852) BB32 [05C..05D), preds={BB30} succs={BB33} ===== N000. IL_OFFSET IL offset: 0x5c N001. t1317 = LCL_VAR_ADDR V97 tmp88 N004. V106(t1319); t1317 N005. V106(t1320) N000. t1510 = LEA(b+0) ; t1320 N009. V91(t1324*) N000. STOREIND ; t1510,t1324* N012. V106(t1327*) N000. t1511 = LEA(b+8) ; t1327* N016. V92(t1331*) N000. STOREIND ; t1511,t1331* N019. t1338 = LCL_VAR_ADDR V99 tmp90 N022. V107(t1340); t1338 N023. V107(t1341) N000. t1512 = LEA(b+0) ; t1341 N027. V93(t1345*) N000. STOREIND ; t1512,t1345* N030. V107(t1348*) N000. t1513 = LEA(b+8) ; t1348* N034. V94(t1352*) N000. STOREIND ; t1513,t1352* N039. t1355 = LCL_VAR_ADDR V97 tmp88 N000. t1514 = PUTARG_REG; t1355 N041. t1358 = LCL_VAR_ADDR V99 tmp90 N000. t1515 = PUTARG_REG; t1358 N045. t834 = CALL ; t1514,t1515 N046. CNS_INT 0 N047. t842 = EQ ; t834 N049. V55(t844); t842 BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ===== N000. IL_OFFSET IL offset: 0x65 N001. V55(t106*) N002. CNS_INT 0 N003. EQ ; t106* N004. JTRUE BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ===== N000. IL_OFFSET IL offset: 0x6a N001. V01(t126*) N003. CNS_INT 0 N000. STOREIND ; t126* N000. IL_OFFSET IL offset: 0x6d N001. CNS_INT 1 N003. V05(t133) BB35 [071..078), preds={BB33} succs={BB36} ===== N000. IL_OFFSET IL offset: 0x71 N001. V01(t112*) N003. CNS_INT 0 N000. STOREIND ; t112* N000. IL_OFFSET IL offset: 0x74 N001. t117 = CNS_INT 0 N003. V05(t119); t117 BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ===== N000. IL_OFFSET IL offset: 0x78 N001. V05(t122*) N002. RETURN ; t122* buildIntervals second part ======== Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> Int arg V01 in reg rdx BB00 regmask=[rdx] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 3) [000171] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N005 ( 20, 23) [000187] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N007 ( 3, 10) [000947] ------------ * CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG NA $180 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 52: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N007.t947. CNS_INT } N009 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N011 ( 3, 2) [000940] ------------ * LCL_VAR ref V96 tmp87 u:4 NA REG NA $180 +[--] consume=0 produce=1 DefList: { N011.t940. LCL_VAR } N013 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte REG NA $241 +[--] consume=1 produce=0 LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N015 ( 3, 2) [000943] ------------ * LCL_VAR ref V96 tmp87 u:4 NA (last use) REG NA $180 +[--] consume=0 produce=1 DefList: { N015.t943. LCL_VAR } N017 ( 1, 1) [000944] -c---------- * CNS_INT long 12 field offset Fseq[_firstChar] REG NA $280 Contained DefList: { N015.t943. LCL_VAR } N019 ( 5, 4) [000945] ------------ * ADD byref REG NA $VN.Null +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 53: RefPositions {} physReg:NA Preferences=[allInt] Assigning related to ADD BB01 regmask=[allInt] minReg=1> DefList: { N019.t945. ADD } N021 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N023 ( 10, 16) [000239] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N025 ( 3, 10) [000955] ------------ * CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG NA $180 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 54: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N025.t955. CNS_INT } N027 (???,???) [001478] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N025.t955. CNS_INT } N029 ( 6, 13) [000236] x---G------- * IND int REG NA +[--] consume=1 produce=1 BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 55: RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N029.t236. IND } N031 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N033 ( 0, 0) [000193] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N035 ( 22, 10) [000256] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N037 ( 3, 2) [000240] ------------ * LCL_VAR int V14 tmp5 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N037.t240. LCL_VAR } N039 ( 1, 1) [000250] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N037.t240. LCL_VAR } N041 ( 8, 4) [000251] ------------ * GE int REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 56: RefPositions {} physReg:NA Preferences=[allInt] GE BB01 regmask=[allInt] minReg=1> DefList: { N041.t251. GE } N043 (???,???) [001479] ------------ * PUTARG_REG int REG rcx +[--] consume=1 produce=1 BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 57: RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rcx] minReg=1> PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed> DefList: { N043.t1479. PUTARG_REG } N045 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void +[--] consume=1 produce=0 BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> DefList: { } N047 ( 7, 5) [000268] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N049 ( 3, 2) [000188] ------------ * LCL_VAR byref V10 tmp1 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N049.t188. LCL_VAR } N051 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N053 ( 7, 5) [000273] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N055 ( 3, 2) [000970] -------N---- * LCL_VAR byref V71 tmp62 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N055.t970. LCL_VAR } N057 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N059 ( 7, 5) [000279] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N061 ( 3, 2) [000276] ------------ * LCL_VAR int V14 tmp5 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N061.t276. LCL_VAR } N063 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N065 ( 14, 10) [000204] ------------ * IL_OFFSET void IL offset: 0x1 REG NA +[--] consume=0 produce=0 DefList: { } N067 ( 3, 2) [000973] -------N---- * LCL_VAR byref V65 tmp56 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N067.t973. LCL_VAR } N069 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N071 ( 3, 2) [000976] -------N---- * LCL_VAR int V66 tmp57 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N071.t976. LCL_VAR } N073 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N075 ( 3, 2) [000980] -------N---- * LCL_VAR byref V67 tmp58 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N075.t980. LCL_VAR } N077 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N079 ( 3, 2) [000983] -------N---- * LCL_VAR int V68 tmp59 u:3 NA (last use) REG NA $3c0 +[--] consume=0 produce=1 DefList: { N079.t983. LCL_VAR } N081 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N083 ( 10, 8) [000355] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N085 ( 12, 10) [000359] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N087 ( 1, 1) [000995] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N087.t995. LCL_VAR } N089 (???,???) [001480] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N087.t995. LCL_VAR } N091 ( 4, 3) [000998] x----------- * IND byref REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 58: RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N091.t998. IND } N093 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N095 ( 1, 1) [001001] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N095.t1001. LCL_VAR } N097 (???,???) [001481] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N095.t1001. LCL_VAR } N099 ( 4, 4) [001004] x----------- * IND int REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 59: RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N099.t1004. IND } N101 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N103 ( 6, 3) [000302] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N105 ( 1, 1) [000295] ------------ * LCL_VAR int V62 tmp53 u:3 NA REG NA $3c0 +[--] consume=0 produce=1 DefList: { N105.t295. LCL_VAR } N107 ( 1, 1) [000393] ------------ * LCL_VAR int V75 tmp66 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N105.t295. LCL_VAR; N107.t393. LCL_VAR } N109 ( 6, 3) [000297] ------------ * NE int REG NA +[--] consume=2 produce=1 LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 60: RefPositions {} physReg:NA Preferences=[allInt] NE BB01 regmask=[allInt] minReg=1> DefList: { N109.t297. NE } N111 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N113 ( 5, 5) [000307] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N115 ( 1, 1) [000303] ------------ * LCL_VAR int V19 tmp10 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N115.t303. LCL_VAR } N117 ( 1, 1) [000304] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N115.t303. LCL_VAR } N119 ( 3, 3) [000305] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N121 ( 5, 5) [000306] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 1, liveout={V00 V01 V61 V62 V74 V75} ============================== use: {V00} def: {V09 V10 V14 V19 V61 V62 V65 V66 V67 V68 V71 V72 V73 V74 V75 V96} NEW BLOCK BB05 Setting BB05 as the predecessor for determining incoming variable registers of BB01 DefList: { } N125 ( 1, 3) [000351] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N127 ( 1, 1) [000348] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 61: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB05 regmask=[allInt] minReg=1> DefList: { N127.t348. CNS_INT } N129 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 NA REG NA +[--] consume=1 produce=0 Assigning related to BB05 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 5, liveout={V00 V01 V21 V61 V62} ============================== use: {} def: {V21} NEW BLOCK BB06 Setting BB06 as the predecessor for determining incoming variable registers of BB01 DefList: { } N133 ( 10, 6) [000318] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N135 ( 1, 1) [000406] ------------ * LCL_VAR int V75 tmp66 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N135.t406. LCL_VAR } N137 ( 1, 1) [000314] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N135.t406. LCL_VAR } N139 ( 6, 3) [000315] ------------ * EQ int REG NA +[--] consume=1 produce=1 LCL_VAR BB06 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 62: RefPositions {} physReg:NA Preferences=[allInt] EQ BB06 regmask=[allInt] minReg=1> DefList: { N139.t315. EQ } N141 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB06 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N143 ( 7, 6) [000323] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N145 ( 3, 2) [000319] ------------ * LCL_VAR int V20 tmp11 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N145.t319. LCL_VAR } N147 ( 1, 1) [000320] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N145.t319. LCL_VAR } N149 ( 5, 4) [000321] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N151 ( 7, 6) [000322] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 6, liveout={V00 V01 V61 V62 V74 V75} ============================== use: {V75} def: {V20} NEW BLOCK BB07 Setting BB07 as the predecessor for determining incoming variable registers of BB06 DefList: { } N155 ( 1, 3) [000346] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N157 ( 1, 1) [000343] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N159 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 7, liveout={V00 V01 V21 V61 V62} ============================== use: {} def: {V21} NEW BLOCK BB08 Setting BB08 as the predecessor for determining incoming variable registers of BB06 DefList: { } N163 ( 81, 55) [000338] ------------ * IL_OFFSET void IL offset: 0xc REG NA +[--] consume=0 produce=0 DefList: { } N165 ( 3, 2) [001016] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 63: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> DefList: { N165.t1016. LCL_VAR_ADDR } N167 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB08 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N169 ( 3, 2) [001019] ------------ * LCL_VAR byref V98 tmp89 u:3 NA REG NA $2ca +[--] consume=0 produce=1 DefList: { N169.t1019. LCL_VAR } N171 (???,???) [001482] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N169.t1019. LCL_VAR } N173 ( 3, 2) [001023] -------N---- * LCL_VAR byref V61 tmp52 u:3 NA REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N169.t1019. LCL_VAR; N173.t1023. LCL_VAR } N175 (???,???) [001456] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N177 ( 3, 2) [001026] ------------ * LCL_VAR byref V98 tmp89 u:3 NA (last use) REG NA $2ca +[--] consume=0 produce=1 DefList: { N177.t1026. LCL_VAR } N179 (???,???) [001483] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N177.t1026. LCL_VAR } N181 ( 1, 1) [001030] -------N---- * LCL_VAR int V62 tmp53 u:3 NA REG NA $3c0 +[--] consume=0 produce=1 DefList: { N177.t1026. LCL_VAR; N181.t1030. LCL_VAR } N183 (???,???) [001457] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N185 ( 3, 2) [001037] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 64: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> DefList: { N185.t1037. LCL_VAR_ADDR } N187 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB08 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N189 ( 3, 2) [001040] ------------ * LCL_VAR byref V100 tmp91 u:3 NA REG NA $2cc +[--] consume=0 produce=1 DefList: { N189.t1040. LCL_VAR } N191 (???,???) [001484] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N189.t1040. LCL_VAR } N193 ( 3, 2) [001044] -------N---- * LCL_VAR byref V74 tmp65 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N189.t1040. LCL_VAR; N193.t1044. LCL_VAR } N195 (???,???) [001458] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N197 ( 3, 2) [001047] ------------ * LCL_VAR byref V100 tmp91 u:3 NA (last use) REG NA $2cc +[--] consume=0 produce=1 DefList: { N197.t1047. LCL_VAR } N199 (???,???) [001485] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N197.t1047. LCL_VAR } N201 ( 1, 1) [001051] -------N---- * LCL_VAR int V75 tmp66 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N197.t1047. LCL_VAR; N201.t1051. LCL_VAR } N203 (???,???) [001459] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N205 ( 3, 2) [001054] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 65: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> DefList: { N205.t1054. LCL_VAR_ADDR } N207 (???,???) [001486] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 66: RefPositions {} physReg:NA Preferences=[allInt] BB08 regmask=[rcx] minReg=1> PUTARG_REG BB08 regmask=[rcx] minReg=1 fixed> DefList: { N207.t1486. PUTARG_REG } N209 ( 3, 2) [001057] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 67: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> DefList: { N207.t1486. PUTARG_REG; N209.t1057. LCL_VAR_ADDR } N211 (???,???) [001487] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 68: RefPositions {} physReg:NA Preferences=[allInt] BB08 regmask=[rdx] minReg=1> PUTARG_REG BB08 regmask=[rdx] minReg=1 fixed> DefList: { N207.t1486. PUTARG_REG; N211.t1487. PUTARG_REG } N213 ( 76, 53) [000327] --CXG------- * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce +[-O] consume=2 produce=1 BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allInt] BB08 regmask=[rax] minReg=1> BB08 regmask=[rcx] minReg=1> BB08 regmask=[rdx] minReg=1> BB08 regmask=[r8] minReg=1> BB08 regmask=[r9] minReg=1> BB08 regmask=[r10] minReg=1> BB08 regmask=[r11] minReg=1> Interval 69: RefPositions {} physReg:NA Preferences=[allInt] BB08 regmask=[rax] minReg=1> CALL BB08 regmask=[rax] minReg=1 fixed> DefList: { N213.t327. CALL } N215 ( 1, 1) [000334] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N213.t327. CALL } N217 ( 81, 55) [000335] ---XG------- * EQ int REG NA $30d +[--] consume=1 produce=1 BB08 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 70: RefPositions {} physReg:NA Preferences=[allInt] EQ BB08 regmask=[allInt] minReg=1> DefList: { N217.t335. EQ } N219 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB08 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB08 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 8, liveout={V00 V01 V21 V61 V62} ============================== use: {V61 V62 V74 V75} def: {V21 V98 V100} NEW BLOCK BB09 Setting BB09 as the predecessor for determining incoming variable registers of BB05 DefList: { } N223 ( 5, 5) [000029] ------------ * IL_OFFSET void IL offset: 0x14 REG NA +[--] consume=0 produce=0 DefList: { } N225 ( 1, 1) [000025] ------------ * LCL_VAR int V21 tmp12 u:6 NA (last use) REG NA $500 +[-O] consume=0 produce=1 DefList: { N225.t25. LCL_VAR } N227 ( 1, 1) [000026] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N225.t25. LCL_VAR } N229 ( 3, 3) [000027] J------N---- * EQ void REG NA $30e +[--] consume=1 produce=0 LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N231 ( 5, 5) [000028] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 9, liveout={V00 V01 V61 V62} ============================== use: {V21} def: {} NEW BLOCK BB10 Setting BB10 as the predecessor for determining incoming variable registers of BB09 DefList: { } N235 ( 6, 5) [000160] ------------ * IL_OFFSET void IL offset: 0x18 REG NA +[--] consume=0 produce=0 DefList: { } N237 ( 1, 1) [000156] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $81 +[--] consume=0 produce=1 DefList: { N237.t156. LCL_VAR } N239 ( 1, 1) [000157] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { N237.t156. LCL_VAR } N241 (???,???) [001460] -A-XG------- * STOREIND byte REG NA +[--] consume=1 produce=0 LCL_VAR BB10 regmask=[allInt] minReg=1 last> DefList: { } N243 ( 1, 3) [000164] ------------ * IL_OFFSET void IL offset: 0x1b REG NA +[--] consume=0 produce=0 DefList: { } N245 ( 1, 1) [000161] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N247 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 10, liveout={V05} ============================== use: {V01} def: {V05} NEW BLOCK BB11 Setting BB11 as the predecessor for determining incoming variable registers of BB09 DefList: { } N251 ( 5, 4) [000418] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N253 ( 12, 18) [000434] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N255 ( 3, 10) [001089] ------------ * CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG NA $184 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 71: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB11 regmask=[allInt] minReg=1> DefList: { N255.t1089. CNS_INT } N257 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N259 ( 1, 1) [001082] ------------ * LCL_VAR ref V96 tmp87 u:3 NA (last use) REG NA $184 +[--] consume=0 produce=1 DefList: { N259.t1082. LCL_VAR } N261 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte REG NA $24c +[--] consume=1 produce=0 LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N263 ( 10, 16) [000486] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N265 ( 3, 10) [001097] ------------ * CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG NA $184 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 72: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB11 regmask=[allInt] minReg=1> DefList: { N265.t1097. CNS_INT } N267 (???,???) [001488] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N265.t1097. CNS_INT } N269 ( 6, 13) [000483] x---G------- * IND int REG NA +[--] consume=1 produce=1 BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 73: RefPositions {} physReg:NA Preferences=[allInt] IND BB11 regmask=[allInt] minReg=1> DefList: { N269.t483. IND } N271 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N273 ( 0, 0) [000440] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N275 ( 22, 10) [000503] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N277 ( 3, 2) [000487] ------------ * LCL_VAR int V30 tmp21 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N277.t487. LCL_VAR } N279 ( 1, 1) [000497] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N277.t487. LCL_VAR } N281 ( 8, 4) [000498] ------------ * GE int REG NA +[--] consume=1 produce=1 LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 74: RefPositions {} physReg:NA Preferences=[allInt] GE BB11 regmask=[allInt] minReg=1> DefList: { N281.t498. GE } N283 (???,???) [001489] ------------ * PUTARG_REG int REG rcx +[--] consume=1 produce=1 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 75: RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> DefList: { N283.t1489. PUTARG_REG } N285 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void +[--] consume=1 produce=0 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[r8] minReg=1> BB11 regmask=[r9] minReg=1> BB11 regmask=[r10] minReg=1> BB11 regmask=[r11] minReg=1> DefList: { } N287 ( 7, 5) [000515] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N289 ( 7, 5) [000520] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N291 ( 7, 5) [000526] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N293 ( 3, 2) [000523] ------------ * LCL_VAR int V30 tmp21 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N293.t523. LCL_VAR } N295 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N297 ( 14, 10) [000451] ------------ * IL_OFFSET void IL offset: 0x1f REG NA +[--] consume=0 produce=0 DefList: { } N299 ( 3, 2) [001118] -------N---- * LCL_VAR int V77 tmp68 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N299.t1118. LCL_VAR } N301 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N303 ( 3, 2) [001122] -------N---- * LCL_VAR byref V61 tmp52 u:3 NA REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N303.t1122. LCL_VAR } N305 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 NA REG NA +[--] consume=1 produce=0 LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N307 ( 3, 2) [001125] -------N---- * LCL_VAR int V79 tmp70 u:3 NA (last use) REG NA $3c2 +[--] consume=0 produce=1 DefList: { N307.t1125. LCL_VAR } N309 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N311 ( 14, 10) [000602] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N313 ( 16, 13) [000606] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N315 ( 1, 1) [001137] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N315.t1137. LCL_VAR } N317 (???,???) [001490] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N315.t1137. LCL_VAR } N319 ( 4, 3) [001140] x----------- * IND byref REG NA +[--] consume=1 produce=1 LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 76: RefPositions {} physReg:NA Preferences=[allInt] IND BB11 regmask=[allInt] minReg=1> DefList: { N319.t1140. IND } N321 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N323 ( 1, 1) [001143] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N323.t1143. LCL_VAR } N325 (???,???) [001491] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N323.t1143. LCL_VAR } N327 ( 4, 4) [001146] x----------- * IND int REG NA +[--] consume=1 produce=1 LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 77: RefPositions {} physReg:NA Preferences=[allInt] IND BB11 regmask=[allInt] minReg=1> DefList: { N327.t1146. IND } N329 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N331 ( 14, 8) [000549] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N333 ( 3, 2) [000542] ------------ * LCL_VAR int V64 tmp55 u:3 NA REG NA $3c2 +[--] consume=0 produce=1 DefList: { N333.t542. LCL_VAR } N335 ( 3, 2) [000640] ------------ * LCL_VAR int V86 tmp77 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N333.t542. LCL_VAR; N335.t640. LCL_VAR } N337 ( 10, 5) [000544] ------------ * NE int REG NA +[--] consume=2 produce=1 LCL_VAR BB11 regmask=[allInt] minReg=1 last> LCL_VAR BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 78: RefPositions {} physReg:NA Preferences=[allInt] NE BB11 regmask=[allInt] minReg=1> DefList: { N337.t544. NE } N339 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB11 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N341 ( 7, 6) [000554] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N343 ( 3, 2) [000550] ------------ * LCL_VAR int V35 tmp26 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N343.t550. LCL_VAR } N345 ( 1, 1) [000551] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N343.t550. LCL_VAR } N347 ( 5, 4) [000552] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB11 regmask=[allInt] minReg=1 last> DefList: { } N349 ( 7, 6) [000553] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 11, liveout={V00 V01 V61 V62 V63 V64 V85 V86} ============================== use: {V00 V61} def: {V25 V26 V30 V35 V63 V64 V76 V77 V78 V79 V82 V83 V84 V85 V86 V96} NEW BLOCK BB15 Setting BB15 as the predecessor for determining incoming variable registers of BB11 DefList: { } N353 ( 5, 4) [000598] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N355 ( 1, 1) [000595] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 79: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB15 regmask=[allInt] minReg=1> DefList: { N355.t595. CNS_INT } N357 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 NA REG NA +[--] consume=1 produce=0 Assigning related to BB15 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB15 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 15, liveout={V00 V01 V37 V62 V63 V64} ============================== use: {} def: {V37} NEW BLOCK BB16 Setting BB16 as the predecessor for determining incoming variable registers of BB11 DefList: { } N361 ( 12, 7) [000565] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N363 ( 3, 2) [000653] ------------ * LCL_VAR int V86 tmp77 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N363.t653. LCL_VAR } N365 ( 1, 1) [000561] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N363.t653. LCL_VAR } N367 ( 8, 4) [000562] ------------ * EQ int REG NA +[--] consume=1 produce=1 LCL_VAR BB16 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 80: RefPositions {} physReg:NA Preferences=[allInt] EQ BB16 regmask=[allInt] minReg=1> DefList: { N367.t562. EQ } N369 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB16 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N371 ( 7, 6) [000570] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N373 ( 3, 2) [000566] ------------ * LCL_VAR int V36 tmp27 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N373.t566. LCL_VAR } N375 ( 1, 1) [000567] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N373.t566. LCL_VAR } N377 ( 5, 4) [000568] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N379 ( 7, 6) [000569] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 16, liveout={V00 V01 V61 V62 V63 V64 V85 V86} ============================== use: {V86} def: {V36} NEW BLOCK BB17 Setting BB17 as the predecessor for determining incoming variable registers of BB16 DefList: { } N383 ( 5, 4) [000593] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N385 ( 1, 1) [000590] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N387 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB17 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 17, liveout={V00 V01 V37 V62 V63 V64} ============================== use: {} def: {V37} NEW BLOCK BB18 Setting BB18 as the predecessor for determining incoming variable registers of BB16 DefList: { } N391 ( 89, 60) [000585] ------------ * IL_OFFSET void IL offset: 0x2a REG NA +[--] consume=0 produce=0 DefList: { } N393 ( 3, 2) [001158] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 81: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> DefList: { N393.t1158. LCL_VAR_ADDR } N395 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB18 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N397 ( 3, 2) [001161] ------------ * LCL_VAR byref V101 tmp92 u:3 NA REG NA $2da +[--] consume=0 produce=1 DefList: { N397.t1161. LCL_VAR } N399 (???,???) [001492] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N397.t1161. LCL_VAR } N401 ( 3, 2) [001165] -------N---- * LCL_VAR byref V61 tmp52 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N397.t1161. LCL_VAR; N401.t1165. LCL_VAR } N403 (???,???) [001461] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N405 ( 3, 2) [001168] ------------ * LCL_VAR byref V101 tmp92 u:3 NA (last use) REG NA $2da +[--] consume=0 produce=1 DefList: { N405.t1168. LCL_VAR } N407 (???,???) [001493] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N405.t1168. LCL_VAR } N409 ( 3, 2) [001172] -------N---- * LCL_VAR int V64 tmp55 u:3 NA REG NA $3c2 +[--] consume=0 produce=1 DefList: { N405.t1168. LCL_VAR; N409.t1172. LCL_VAR } N411 (???,???) [001462] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N413 ( 3, 2) [001179] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 82: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> DefList: { N413.t1179. LCL_VAR_ADDR } N415 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB18 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N417 ( 3, 2) [001182] ------------ * LCL_VAR byref V102 tmp93 u:3 NA REG NA $2dc +[--] consume=0 produce=1 DefList: { N417.t1182. LCL_VAR } N419 (???,???) [001494] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N417.t1182. LCL_VAR } N421 ( 3, 2) [001186] -------N---- * LCL_VAR byref V85 tmp76 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N417.t1182. LCL_VAR; N421.t1186. LCL_VAR } N423 (???,???) [001463] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N425 ( 3, 2) [001189] ------------ * LCL_VAR byref V102 tmp93 u:3 NA (last use) REG NA $2dc +[--] consume=0 produce=1 DefList: { N425.t1189. LCL_VAR } N427 (???,???) [001495] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N425.t1189. LCL_VAR } N429 ( 3, 2) [001193] -------N---- * LCL_VAR int V86 tmp77 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N425.t1189. LCL_VAR; N429.t1193. LCL_VAR } N431 (???,???) [001464] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N433 ( 3, 2) [001196] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 83: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> DefList: { N433.t1196. LCL_VAR_ADDR } N435 (???,???) [001496] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 84: RefPositions {} physReg:NA Preferences=[allInt] BB18 regmask=[rcx] minReg=1> PUTARG_REG BB18 regmask=[rcx] minReg=1 fixed> DefList: { N435.t1496. PUTARG_REG } N437 ( 3, 2) [001199] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 85: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> DefList: { N435.t1496. PUTARG_REG; N437.t1199. LCL_VAR_ADDR } N439 (???,???) [001497] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 86: RefPositions {} physReg:NA Preferences=[allInt] BB18 regmask=[rdx] minReg=1> PUTARG_REG BB18 regmask=[rdx] minReg=1 fixed> DefList: { N435.t1496. PUTARG_REG; N439.t1497. PUTARG_REG } N441 ( 80, 55) [000574] --CXG------- * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 +[-O] consume=2 produce=1 BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allInt] BB18 regmask=[rax] minReg=1> BB18 regmask=[rcx] minReg=1> BB18 regmask=[rdx] minReg=1> BB18 regmask=[r8] minReg=1> BB18 regmask=[r9] minReg=1> BB18 regmask=[r10] minReg=1> BB18 regmask=[r11] minReg=1> Interval 87: RefPositions {} physReg:NA Preferences=[allInt] BB18 regmask=[rax] minReg=1> CALL BB18 regmask=[rax] minReg=1 fixed> DefList: { N441.t574. CALL } N443 ( 1, 1) [000581] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N441.t574. CALL } N445 ( 85, 57) [000582] ---XG------- * EQ int REG NA $31e +[--] consume=1 produce=1 BB18 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 88: RefPositions {} physReg:NA Preferences=[allInt] EQ BB18 regmask=[allInt] minReg=1> DefList: { N445.t582. EQ } N447 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to BB18 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 18, liveout={V00 V01 V37 V62 V63 V64} ============================== use: {V61 V64 V85 V86} def: {V37 V101 V102} NEW BLOCK BB19 Setting BB19 as the predecessor for determining incoming variable registers of BB15 DefList: { } N451 ( 7, 6) [000059] ------------ * IL_OFFSET void IL offset: 0x33 REG NA +[--] consume=0 produce=0 DefList: { } N453 ( 3, 2) [000055] ------------ * LCL_VAR int V37 tmp28 u:6 NA (last use) REG NA $501 +[-O] consume=0 produce=1 DefList: { N453.t55. LCL_VAR } N455 ( 1, 1) [000056] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N453.t55. LCL_VAR } N457 ( 5, 4) [000057] J------N---- * EQ void REG NA $31f +[--] consume=1 produce=0 LCL_VAR BB19 regmask=[allInt] minReg=1 last> DefList: { } N459 ( 7, 6) [000058] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 19, liveout={V00 V01 V62 V63 V64} ============================== use: {V37} def: {} NEW BLOCK BB20 Setting BB20 as the predecessor for determining incoming variable registers of BB19 DefList: { } N463 ( 6, 5) [000150] ------------ * IL_OFFSET void IL offset: 0x38 REG NA +[--] consume=0 produce=0 DefList: { } N465 ( 1, 1) [000146] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $81 +[--] consume=0 produce=1 DefList: { N465.t146. LCL_VAR } N467 ( 1, 1) [000147] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N465.t146. LCL_VAR } N469 (???,???) [001465] -A-XG------- * STOREIND byte REG NA +[--] consume=1 produce=0 LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N471 ( 1, 3) [000154] ------------ * IL_OFFSET void IL offset: 0x3b REG NA +[--] consume=0 produce=0 DefList: { } N473 ( 1, 1) [000151] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N475 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 20, liveout={V05} ============================== use: {V01} def: {V05} NEW BLOCK BB21 Setting BB21 as the predecessor for determining incoming variable registers of BB19 DefList: { } N479 ( 38, 21) [000069] ------------ * IL_OFFSET void IL offset: 0x3f REG NA +[--] consume=0 produce=0 DefList: { } N481 ( 5, 4) [001206] -----O----L- * NOP void REG NA +[--] consume=0 produce=0 DefList: { } N483 ( 1, 1) [000061] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N483.t61. LCL_VAR } N485 ( 3, 2) [000064] xc-----N---- * IND struct REG NA Contained DefList: { N483.t61. LCL_VAR } N487 ( 3, 2) [001203] Dc-----N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA Contained DefList: { N483.t61. LCL_VAR } N489 (???,???) [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) REG NA +[--] consume=1 produce=0 Interval 89: RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB21 regmask=[mm0-mm5] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last> STORE_BLK BB21 regmask=[mm0-mm5] minReg=1 last> DefList: { } N491 ( 3, 2) [001207] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N491.t1207. LCL_VAR } N493 (???,???) [001498] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 90: RefPositions {} physReg:NA Preferences=[allInt] Assigning related to BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> DefList: { N493.t1498. PUTARG_REG } N495 ( 3, 2) [001209] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 91: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB21 regmask=[allInt] minReg=1> DefList: { N493.t1498. PUTARG_REG; N495.t1209. LCL_VAR_ADDR } N497 (???,???) [001499] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 92: RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rdx] minReg=1> PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> DefList: { N493.t1498. PUTARG_REG; N497.t1499. PUTARG_REG } N499 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void +[--] consume=2 produce=0 BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[r8] minReg=1> BB21 regmask=[r9] minReg=1> BB21 regmask=[r10] minReg=1> BB21 regmask=[r11] minReg=1> DefList: { } N501 ( 14, 10) [000732] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N503 ( 3, 2) [001216] -------N---- * LCL_VAR int V62 tmp53 u:3 NA (last use) REG NA $3c0 +[--] consume=0 produce=1 DefList: { N503.t1216. LCL_VAR } N505 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N507 ( 16, 13) [000736] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N509 ( 1, 1) [001221] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N509.t1221. LCL_VAR } N511 (???,???) [001500] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N509.t1221. LCL_VAR } N513 ( 4, 3) [001224] x----------- * IND byref REG NA +[--] consume=1 produce=1 LCL_VAR BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 93: RefPositions {} physReg:NA Preferences=[allInt] IND BB21 regmask=[allInt] minReg=1> DefList: { N513.t1224. IND } N515 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N517 ( 1, 1) [001227] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N517.t1227. LCL_VAR } N519 (???,???) [001501] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N517.t1227. LCL_VAR } N521 ( 4, 4) [001230] x----------- * IND int REG NA +[--] consume=1 produce=1 LCL_VAR BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 94: RefPositions {} physReg:NA Preferences=[allInt] IND BB21 regmask=[allInt] minReg=1> DefList: { N521.t1230. IND } N523 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N525 ( 14, 8) [000679] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N527 ( 3, 2) [000672] ------------ * LCL_VAR int V88 tmp79 u:3 NA REG NA $3c0 +[-O] consume=0 produce=1 DefList: { N527.t672. LCL_VAR } N529 ( 3, 2) [000770] ------------ * LCL_VAR int V90 tmp81 u:3 NA REG NA +[--] consume=0 produce=1 DefList: { N527.t672. LCL_VAR; N529.t770. LCL_VAR } N531 ( 10, 5) [000674] ------------ * NE int REG NA +[--] consume=2 produce=1 LCL_VAR BB21 regmask=[allInt] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 95: RefPositions {} physReg:NA Preferences=[allInt] NE BB21 regmask=[allInt] minReg=1> DefList: { N531.t674. NE } N533 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB21 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N535 ( 7, 6) [000684] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N537 ( 3, 2) [000680] ------------ * LCL_VAR int V44 tmp35 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N537.t680. LCL_VAR } N539 ( 1, 1) [000681] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N537.t680. LCL_VAR } N541 ( 5, 4) [000682] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB21 regmask=[allInt] minReg=1 last> DefList: { } N543 ( 7, 6) [000683] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 21, liveout={V00 V01 V63 V64 V88 V89 V90} ============================== use: {V00 V62 V63} def: {V44 V87 V88 V89 V90 V103} NEW BLOCK BB22 Setting BB22 as the predecessor for determining incoming variable registers of BB21 DefList: { } N547 ( 5, 4) [000728] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N549 ( 1, 1) [000725] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 96: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB22 regmask=[allInt] minReg=1> DefList: { N549.t725. CNS_INT } N551 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 NA REG NA +[--] consume=1 produce=0 Assigning related to BB22 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB22 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 22, liveout={V00 V01 V46 V63 V64} ============================== use: {} def: {V46} NEW BLOCK BB23 Setting BB23 as the predecessor for determining incoming variable registers of BB21 DefList: { } N555 ( 12, 7) [000695] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N557 ( 3, 2) [000783] ------------ * LCL_VAR int V90 tmp81 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N557.t783. LCL_VAR } N559 ( 1, 1) [000691] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N557.t783. LCL_VAR } N561 ( 8, 4) [000692] ------------ * EQ int REG NA +[--] consume=1 produce=1 LCL_VAR BB23 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 97: RefPositions {} physReg:NA Preferences=[allInt] EQ BB23 regmask=[allInt] minReg=1> DefList: { N561.t692. EQ } N563 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB23 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N565 ( 7, 6) [000700] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N567 ( 3, 2) [000696] ------------ * LCL_VAR int V45 tmp36 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N567.t696. LCL_VAR } N569 ( 1, 1) [000697] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N567.t696. LCL_VAR } N571 ( 5, 4) [000698] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N573 ( 7, 6) [000699] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 23, liveout={V00 V01 V63 V64 V88 V89 V90} ============================== use: {V90} def: {V45} NEW BLOCK BB24 Setting BB24 as the predecessor for determining incoming variable registers of BB23 DefList: { } N577 ( 5, 4) [000723] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N579 ( 1, 1) [000720] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N581 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB24 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 24, liveout={V00 V01 V46 V63 V64} ============================== use: {} def: {V46} NEW BLOCK BB25 Setting BB25 as the predecessor for determining incoming variable registers of BB23 DefList: { } N585 ( 89, 60) [000715] ------------ * IL_OFFSET void IL offset: 0x47 REG NA +[--] consume=0 produce=0 DefList: { } N587 ( 3, 2) [001242] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 98: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> DefList: { N587.t1242. LCL_VAR_ADDR } N589 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB25 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N591 ( 3, 2) [001245] ------------ * LCL_VAR byref V104 tmp95 u:3 NA REG NA $2e5 +[--] consume=0 produce=1 DefList: { N591.t1245. LCL_VAR } N593 (???,???) [001502] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N591.t1245. LCL_VAR } N595 ( 3, 2) [001249] -------N---- * LCL_VAR byref V63 tmp54 u:3 NA REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N591.t1245. LCL_VAR; N595.t1249. LCL_VAR } N597 (???,???) [001467] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N599 ( 3, 2) [001252] ------------ * LCL_VAR byref V104 tmp95 u:3 NA (last use) REG NA $2e5 +[--] consume=0 produce=1 DefList: { N599.t1252. LCL_VAR } N601 (???,???) [001503] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N599.t1252. LCL_VAR } N603 ( 3, 2) [001256] -------N---- * LCL_VAR int V88 tmp79 u:3 NA (last use) REG NA $3c0 +[--] consume=0 produce=1 DefList: { N599.t1252. LCL_VAR; N603.t1256. LCL_VAR } N605 (???,???) [001468] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N607 ( 3, 2) [001263] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 99: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> DefList: { N607.t1263. LCL_VAR_ADDR } N609 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB25 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N611 ( 3, 2) [001266] ------------ * LCL_VAR byref V105 tmp96 u:3 NA REG NA $2e7 +[--] consume=0 produce=1 DefList: { N611.t1266. LCL_VAR } N613 (???,???) [001504] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N611.t1266. LCL_VAR } N615 ( 3, 2) [001270] -------N---- * LCL_VAR byref V89 tmp80 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N611.t1266. LCL_VAR; N615.t1270. LCL_VAR } N617 (???,???) [001469] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N619 ( 3, 2) [001273] ------------ * LCL_VAR byref V105 tmp96 u:3 NA (last use) REG NA $2e7 +[--] consume=0 produce=1 DefList: { N619.t1273. LCL_VAR } N621 (???,???) [001505] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N619.t1273. LCL_VAR } N623 ( 3, 2) [001277] -------N---- * LCL_VAR int V90 tmp81 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N619.t1273. LCL_VAR; N623.t1277. LCL_VAR } N625 (???,???) [001470] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N627 ( 3, 2) [001280] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 100: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> DefList: { N627.t1280. LCL_VAR_ADDR } N629 (???,???) [001506] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 101: RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rcx] minReg=1> PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> DefList: { N629.t1506. PUTARG_REG } N631 ( 3, 2) [001283] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 102: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> DefList: { N629.t1506. PUTARG_REG; N631.t1283. LCL_VAR_ADDR } N633 (???,???) [001507] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 103: RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rdx] minReg=1> PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> DefList: { N629.t1506. PUTARG_REG; N633.t1507. PUTARG_REG } N635 ( 80, 55) [000704] --CXG------- * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 +[-O] consume=2 produce=1 BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allInt] BB25 regmask=[rax] minReg=1> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[r8] minReg=1> BB25 regmask=[r9] minReg=1> BB25 regmask=[r10] minReg=1> BB25 regmask=[r11] minReg=1> Interval 104: RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rax] minReg=1> CALL BB25 regmask=[rax] minReg=1 fixed> DefList: { N635.t704. CALL } N637 ( 1, 1) [000711] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N635.t704. CALL } N639 ( 85, 57) [000712] ---XG------- * EQ int REG NA $328 +[--] consume=1 produce=1 BB25 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 105: RefPositions {} physReg:NA Preferences=[allInt] EQ BB25 regmask=[allInt] minReg=1> DefList: { N639.t712. EQ } N641 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to BB25 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB25 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 25, liveout={V00 V01 V46 V63 V64} ============================== use: {V63 V88 V89 V90} def: {V46 V104 V105} NEW BLOCK BB26 Setting BB26 as the predecessor for determining incoming variable registers of BB22 DefList: { } N645 ( 7, 6) [000089] ------------ * IL_OFFSET void IL offset: 0x50 REG NA +[--] consume=0 produce=0 DefList: { } N647 ( 3, 2) [000085] ------------ * LCL_VAR int V46 tmp37 u:3 NA (last use) REG NA $502 +[-O] consume=0 produce=1 DefList: { N647.t85. LCL_VAR } N649 ( 1, 1) [000086] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N647.t85. LCL_VAR } N651 ( 5, 4) [000087] J------N---- * EQ void REG NA $329 +[--] consume=1 produce=0 LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N653 ( 7, 6) [000088] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 26, liveout={V00 V01 V63 V64} ============================== use: {V46} def: {} NEW BLOCK BB27 Setting BB27 as the predecessor for determining incoming variable registers of BB26 DefList: { } N657 ( 6, 5) [000140] ------------ * IL_OFFSET void IL offset: 0x55 REG NA +[--] consume=0 produce=0 DefList: { } N659 ( 1, 1) [000136] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $81 +[--] consume=0 produce=1 DefList: { N659.t136. LCL_VAR } N661 ( 1, 1) [000137] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { N659.t136. LCL_VAR } N663 (???,???) [001471] -A-XG------- * STOREIND byte REG NA +[--] consume=1 produce=0 LCL_VAR BB27 regmask=[allInt] minReg=1 last> DefList: { } N665 ( 1, 3) [000144] ------------ * IL_OFFSET void IL offset: 0x58 REG NA +[--] consume=0 produce=0 DefList: { } N667 ( 1, 1) [000141] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N669 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB27 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 27, liveout={V05} ============================== use: {V01} def: {V05} NEW BLOCK BB28 Setting BB28 as the predecessor for determining incoming variable registers of BB26 DefList: { } N673 ( 14, 10) [000862] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N675 ( 3, 2) [001288] -------N---- * LCL_VAR byref V63 tmp54 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N675.t1288. LCL_VAR } N677 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N679 ( 3, 2) [001291] -------N---- * LCL_VAR int V64 tmp55 u:3 NA (last use) REG NA $3c2 +[--] consume=0 produce=1 DefList: { N679.t1291. LCL_VAR } N681 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N683 ( 16, 13) [000866] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N685 ( 1, 1) [001296] ------------ * LCL_VAR byref V00 arg0 u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N685.t1296. LCL_VAR } N687 (???,???) [001508] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N685.t1296. LCL_VAR } N689 ( 4, 3) [001299] x----------- * IND byref REG NA +[--] consume=1 produce=1 LCL_VAR BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 106: RefPositions {} physReg:NA Preferences=[allInt] IND BB28 regmask=[allInt] minReg=1> DefList: { N689.t1299. IND } N691 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N693 ( 1, 1) [001302] ------------ * LCL_VAR byref V00 arg0 u:2 NA (last use) REG NA $80 +[--] consume=0 produce=1 DefList: { N693.t1302. LCL_VAR } N695 (???,???) [001509] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N693.t1302. LCL_VAR } N697 ( 4, 4) [001305] x----------- * IND int REG NA +[--] consume=1 produce=1 LCL_VAR BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 107: RefPositions {} physReg:NA Preferences=[allInt] IND BB28 regmask=[allInt] minReg=1> DefList: { N697.t1305. IND } N699 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N701 ( 14, 8) [000809] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N703 ( 3, 2) [000802] ------------ * LCL_VAR int V92 tmp83 u:3 NA REG NA $3c2 +[-O] consume=0 produce=1 DefList: { N703.t802. LCL_VAR } N705 ( 3, 2) [000900] ------------ * LCL_VAR int V94 tmp85 u:3 NA REG NA +[--] consume=0 produce=1 DefList: { N703.t802. LCL_VAR; N705.t900. LCL_VAR } N707 ( 10, 5) [000804] ------------ * NE int REG NA +[--] consume=2 produce=1 LCL_VAR BB28 regmask=[allInt] minReg=1 last> LCL_VAR BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 108: RefPositions {} physReg:NA Preferences=[allInt] NE BB28 regmask=[allInt] minReg=1> DefList: { N707.t804. NE } N709 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB28 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N711 ( 7, 6) [000814] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N713 ( 3, 2) [000810] ------------ * LCL_VAR int V53 tmp44 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N713.t810. LCL_VAR } N715 ( 1, 1) [000811] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N713.t810. LCL_VAR } N717 ( 5, 4) [000812] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N719 ( 7, 6) [000813] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 28, liveout={V01 V91 V92 V93 V94} ============================== use: {V00 V63 V64} def: {V53 V91 V92 V93 V94} NEW BLOCK BB29 Setting BB29 as the predecessor for determining incoming variable registers of BB28 DefList: { } N723 ( 5, 4) [000858] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N725 ( 1, 1) [000855] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 109: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB29 regmask=[allInt] minReg=1> DefList: { N725.t855. CNS_INT } N727 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 NA REG NA +[--] consume=1 produce=0 Assigning related to BB29 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB29 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 29, liveout={V01 V55} ============================== use: {} def: {V55} NEW BLOCK BB30 Setting BB30 as the predecessor for determining incoming variable registers of BB28 DefList: { } N731 ( 12, 7) [000825] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N733 ( 3, 2) [000913] ------------ * LCL_VAR int V94 tmp85 u:3 NA REG NA +[-O] consume=0 produce=1 DefList: { N733.t913. LCL_VAR } N735 ( 1, 1) [000821] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N733.t913. LCL_VAR } N737 ( 8, 4) [000822] ------------ * EQ int REG NA +[--] consume=1 produce=1 LCL_VAR BB30 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 110: RefPositions {} physReg:NA Preferences=[allInt] EQ BB30 regmask=[allInt] minReg=1> DefList: { N737.t822. EQ } N739 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB30 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB30 regmask=[allInt] minReg=1 last> DefList: { } N741 ( 7, 6) [000830] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N743 ( 3, 2) [000826] ------------ * LCL_VAR int V54 tmp45 u:3 NA (last use) REG NA +[-O] consume=0 produce=1 DefList: { N743.t826. LCL_VAR } N745 ( 1, 1) [000827] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N743.t826. LCL_VAR } N747 ( 5, 4) [000828] J------N---- * EQ void REG NA +[--] consume=1 produce=0 LCL_VAR BB30 regmask=[allInt] minReg=1 last> DefList: { } N749 ( 7, 6) [000829] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 30, liveout={V01 V91 V92 V93 V94} ============================== use: {V94} def: {V54} NEW BLOCK BB31 Setting BB31 as the predecessor for determining incoming variable registers of BB30 DefList: { } N753 ( 5, 4) [000853] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N755 ( 1, 1) [000850] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N757 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB31 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 31, liveout={V01 V55} ============================== use: {} def: {V55} NEW BLOCK BB32 Setting BB32 as the predecessor for determining incoming variable registers of BB30 DefList: { } N761 ( 89, 60) [000845] ------------ * IL_OFFSET void IL offset: 0x5c REG NA +[--] consume=0 produce=0 DefList: { } N763 ( 3, 2) [001317] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 111: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N763.t1317. LCL_VAR_ADDR } N765 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB32 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N767 ( 3, 2) [001320] ------------ * LCL_VAR byref V106 tmp97 u:3 NA REG NA $2ee +[--] consume=0 produce=1 DefList: { N767.t1320. LCL_VAR } N769 (???,???) [001510] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N767.t1320. LCL_VAR } N771 ( 3, 2) [001324] -------N---- * LCL_VAR byref V91 tmp82 u:3 NA (last use) REG NA $VN.Null +[--] consume=0 produce=1 DefList: { N767.t1320. LCL_VAR; N771.t1324. LCL_VAR } N773 (???,???) [001472] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N775 ( 3, 2) [001327] ------------ * LCL_VAR byref V106 tmp97 u:3 NA (last use) REG NA $2ee +[--] consume=0 produce=1 DefList: { N775.t1327. LCL_VAR } N777 (???,???) [001511] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N775.t1327. LCL_VAR } N779 ( 3, 2) [001331] -------N---- * LCL_VAR int V92 tmp83 u:3 NA (last use) REG NA $3c2 +[--] consume=0 produce=1 DefList: { N775.t1327. LCL_VAR; N779.t1331. LCL_VAR } N781 (???,???) [001473] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N783 ( 3, 2) [001338] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 112: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N783.t1338. LCL_VAR_ADDR } N785 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB32 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N787 ( 3, 2) [001341] ------------ * LCL_VAR byref V107 tmp98 u:3 NA REG NA $2f0 +[--] consume=0 produce=1 DefList: { N787.t1341. LCL_VAR } N789 (???,???) [001512] -c---------- * LEA(b+0) byref REG NA Contained DefList: { N787.t1341. LCL_VAR } N791 ( 3, 2) [001345] -------N---- * LCL_VAR byref V93 tmp84 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N787.t1341. LCL_VAR; N791.t1345. LCL_VAR } N793 (???,???) [001474] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N795 ( 3, 2) [001348] ------------ * LCL_VAR byref V107 tmp98 u:3 NA (last use) REG NA $2f0 +[--] consume=0 produce=1 DefList: { N795.t1348. LCL_VAR } N797 (???,???) [001513] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N795.t1348. LCL_VAR } N799 ( 3, 2) [001352] -------N---- * LCL_VAR int V94 tmp85 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N795.t1348. LCL_VAR; N799.t1352. LCL_VAR } N801 (???,???) [001475] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N803 ( 3, 2) [001355] -------N---- * LCL_VAR_ADDR byref V97 tmp88 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 113: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N803.t1355. LCL_VAR_ADDR } N805 (???,???) [001514] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 114: RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rcx] minReg=1> PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> DefList: { N805.t1514. PUTARG_REG } N807 ( 3, 2) [001358] -------N---- * LCL_VAR_ADDR byref V99 tmp90 NA REG NA +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 115: RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> DefList: { N805.t1514. PUTARG_REG; N807.t1358. LCL_VAR_ADDR } N809 (???,???) [001515] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 116: RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rdx] minReg=1> PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> DefList: { N805.t1514. PUTARG_REG; N809.t1515. PUTARG_REG } N811 ( 80, 55) [000834] --CXG------- * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 +[-O] consume=2 produce=1 BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allInt] BB32 regmask=[rax] minReg=1> BB32 regmask=[rcx] minReg=1> BB32 regmask=[rdx] minReg=1> BB32 regmask=[r8] minReg=1> BB32 regmask=[r9] minReg=1> BB32 regmask=[r10] minReg=1> BB32 regmask=[r11] minReg=1> Interval 117: RefPositions {} physReg:NA Preferences=[allInt] BB32 regmask=[rax] minReg=1> CALL BB32 regmask=[rax] minReg=1 fixed> DefList: { N811.t834. CALL } N813 ( 1, 1) [000841] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N811.t834. CALL } N815 ( 85, 57) [000842] ---XG------- * EQ int REG NA $332 +[--] consume=1 produce=1 BB32 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] Interval 118: RefPositions {} physReg:NA Preferences=[allInt] EQ BB32 regmask=[allInt] minReg=1> DefList: { N815.t842. EQ } N817 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 NA REG NA +[--] consume=1 produce=0 Assigning related to BB32 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 32, liveout={V01 V55} ============================== use: {V91 V92 V93 V94} def: {V55 V106 V107} NEW BLOCK BB33 Setting BB33 as the predecessor for determining incoming variable registers of BB29 DefList: { } N821 ( 7, 6) [000110] ------------ * IL_OFFSET void IL offset: 0x65 REG NA +[--] consume=0 produce=0 DefList: { } N823 ( 3, 2) [000106] ------------ * LCL_VAR int V55 tmp46 u:3 NA (last use) REG NA $503 +[-O] consume=0 produce=1 DefList: { N823.t106. LCL_VAR } N825 ( 1, 1) [000107] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N823.t106. LCL_VAR } N827 ( 5, 4) [000108] J------N---- * EQ void REG NA $333 +[--] consume=1 produce=0 LCL_VAR BB33 regmask=[allInt] minReg=1 last> DefList: { } N829 ( 7, 6) [000109] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 33, liveout={V01} ============================== use: {V55} def: {} NEW BLOCK BB34 Setting BB34 as the predecessor for determining incoming variable registers of BB33 DefList: { } N833 ( 6, 5) [000130] ------------ * IL_OFFSET void IL offset: 0x6a REG NA +[--] consume=0 produce=0 DefList: { } N835 ( 1, 1) [000126] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $81 +[--] consume=0 produce=1 DefList: { N835.t126. LCL_VAR } N837 ( 1, 1) [000127] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N835.t126. LCL_VAR } N839 (???,???) [001476] -A-XG------- * STOREIND byte REG NA +[--] consume=1 produce=0 LCL_VAR BB34 regmask=[allInt] minReg=1 last> DefList: { } N841 ( 1, 3) [000134] ------------ * IL_OFFSET void IL offset: 0x6d REG NA +[--] consume=0 produce=0 DefList: { } N843 ( 1, 1) [000131] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N845 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 NA REG NA +[--] consume=0 produce=0 Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB34 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 34, liveout={V05} ============================== use: {V01} def: {V05} NEW BLOCK BB35 Setting BB35 as the predecessor for determining incoming variable registers of BB33 DefList: { } N849 ( 6, 5) [000116] ------------ * IL_OFFSET void IL offset: 0x71 REG NA +[--] consume=0 produce=0 DefList: { } N851 ( 1, 1) [000112] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $81 +[--] consume=0 produce=1 DefList: { N851.t112. LCL_VAR } N853 ( 1, 1) [000113] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N851.t112. LCL_VAR } N855 (???,???) [001477] -A-XG------- * STOREIND byte REG NA +[--] consume=1 produce=0 LCL_VAR BB35 regmask=[allInt] minReg=1 last> DefList: { } N857 ( 1, 3) [000120] ------------ * IL_OFFSET void IL offset: 0x74 REG NA +[--] consume=0 produce=0 DefList: { } N859 ( 1, 1) [000117] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allInt], Use candidates [allInt] Interval 119: RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB35 regmask=[allInt] minReg=1> DefList: { N859.t117. CNS_INT } N861 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB35 regmask=[allInt] minReg=1 last> Def candidates [allInt], Use candidates [allInt] STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> CHECKING LAST USES for block 35, liveout={V05} ============================== use: {V01} def: {V05} NEW BLOCK BB36 Setting BB36 as the predecessor for determining incoming variable registers of BB10 DefList: { } N865 ( 2, 2) [000124] ------------ * IL_OFFSET void IL offset: 0x78 REG NA +[--] consume=0 produce=0 DefList: { } N867 ( 1, 1) [000122] ------------ * LCL_VAR int V05 loc3 u:8 NA (last use) REG NA $504 +[--] consume=0 produce=1 DefList: { N867.t122. LCL_VAR } N869 ( 2, 2) [000123] ------------ * RETURN int REG NA $1fb +[--] consume=1 produce=0 BB36 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for block 36, liveout={} ============================== use: {V05} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) RefPositions {#0@0 #45@91 #49@99 #151@319 #155@327 #226@489 #229@493 #250@513 #254@521 #328@689 #332@697} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) RefPositions {#1@0 #116@241 #222@469 #321@663 #399@839 #402@855} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V05) RefPositions {#117@248 #223@476 #322@670 #400@846 #405@862 #408@869} physReg:NA Preferences=[rax] Interval 3: (V09) RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V10) RefPositions {#10@22 #31@51} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A4A0] Interval 5: (V14) RefPositions {#15@32 #16@41 #35@63} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A398] Interval 6: (V19) RefPositions {#57@112 #58@119} physReg:NA Preferences=[allInt] Interval 7: (V20) RefPositions {#67@142 #68@149} physReg:NA Preferences=[allInt] Interval 8: (V21) RefPositions {#62@130 #70@160 #112@220 #114@229} physReg:NA Preferences=[allInt] Interval 9: (V25) RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V26) RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V30) RefPositions {#127@272 #128@281 #143@295} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A5A8] Interval 12: (V35) RefPositions {#163@340 #164@347} physReg:NA Preferences=[allInt] Interval 13: (V36) RefPositions {#173@370 #174@377} physReg:NA Preferences=[allInt] Interval 14: (V37) RefPositions {#168@358 #176@388 #218@448 #220@457} physReg:NA Preferences=[allInt] Interval 15: (V44) RefPositions {#262@534 #263@541} physReg:NA Preferences=[allInt] Interval 16: (V45) RefPositions {#272@564 #273@571} physReg:NA Preferences=[allInt] Interval 17: (V46) RefPositions {#267@552 #275@582 #317@642 #319@651} physReg:NA Preferences=[allInt] Interval 18: (V53) RefPositions {#340@710 #341@717} physReg:NA Preferences=[allInt] Interval 19: (V54) RefPositions {#350@740 #351@747} physReg:NA Preferences=[allInt] Interval 20: (V55) RefPositions {#345@728 #353@758 #395@818 #397@827} physReg:NA Preferences=[allInt] Interval 21: (V61) (struct) RefPositions {#42@78 #76@175 #147@305 #182@403} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 22: (V62) (struct) RefPositions {#44@82 #53@109 #78@183 #248@505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A708] Interval 23: (V63) (struct) RefPositions {#148@306 #281@597 #324@677} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A810] Interval 24: (V64) (struct) RefPositions {#150@310 #159@337 #184@411 #326@681} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A868] Interval 25: (V65) (struct) RefPositions {#34@58 #37@69} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A3F0] Interval 26: (V66) (struct) RefPositions {#36@64 #39@73} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A448] Interval 27: (V67) (struct) RefPositions {#38@70 #41@77} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A1E0] Interval 28: (V68) (struct) RefPositions {#40@74 #43@81} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A238] Interval 29: (V71) (struct) RefPositions {#32@52 #33@57} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A340] Interval 30: (V74) (struct) RefPositions {#48@94 #83@195} physReg:NA Preferences=[allInt] Interval 31: (V75) (struct) RefPositions {#52@102 #54@109 #64@139 #85@203} physReg:NA Preferences=[allInt] Interval 32: (V77) (struct) RefPositions {#144@296 #145@301} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A600] Interval 33: (V79) (struct) RefPositions {#146@302 #149@309} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A2E8] Interval 34: (V85) (struct) RefPositions {#154@322 #189@423} physReg:NA Preferences=[allInt] Interval 35: (V86) (struct) RefPositions {#158@330 #160@337 #170@367 #191@431} physReg:NA Preferences=[allInt] Interval 36: (V88) (struct) RefPositions {#249@506 #258@531 #283@605} physReg:NA Preferences=[allInt] Interval 37: (V89) (struct) RefPositions {#253@516 #288@617} physReg:NA Preferences=[allInt] Interval 38: (V90) (struct) RefPositions {#257@524 #259@531 #269@561 #290@625} physReg:NA Preferences=[allInt] Interval 39: (V91) (struct) RefPositions {#325@678 #359@773} physReg:NA Preferences=[allInt] Interval 40: (V92) (struct) RefPositions {#327@682 #336@707 #361@781} physReg:NA Preferences=[allInt] Interval 41: (V93) (struct) RefPositions {#331@692 #366@793} physReg:NA Preferences=[allInt] Interval 42: (V94) (struct) RefPositions {#335@700 #337@707 #347@737 #368@801} physReg:NA Preferences=[allInt] Interval 43: (V96) RefPositions {#5@10 #6@13 #7@19 #121@258 #122@261} physReg:NA Preferences=[allInt] Interval 44: (V98) RefPositions {#74@168 #75@175 #77@183} physReg:NA Preferences=[allInt] Interval 45: (V100) RefPositions {#81@188 #82@195 #84@203} physReg:NA Preferences=[allInt] Interval 46: (V101) RefPositions {#180@396 #181@403 #183@411} physReg:NA Preferences=[allInt] Interval 47: (V102) RefPositions {#187@416 #188@423 #190@431} physReg:NA Preferences=[allInt] Interval 48: (V104) RefPositions {#279@590 #280@597 #282@605} physReg:NA Preferences=[allInt] Interval 49: (V105) RefPositions {#286@610 #287@617 #289@625} physReg:NA Preferences=[allInt] Interval 50: (V106) RefPositions {#357@766 #358@773 #360@781} physReg:NA Preferences=[allInt] Interval 51: (V107) RefPositions {#364@786 #365@793 #367@801} physReg:NA Preferences=[allInt] Interval 52: (constant) RefPositions {#3@8 #4@9} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 53: RefPositions {#8@20 #9@21} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C08] Interval 54: (constant) RefPositions {#11@26 #12@29} physReg:NA Preferences=[allInt] Interval 55: RefPositions {#13@30 #14@31} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C60] Interval 56: RefPositions {#17@42 #19@43} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#21@44 #23@45} physReg:NA Preferences=[rcx] Interval 58: RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A4F8] Interval 59: RefPositions {#50@100 #51@101} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A550] Interval 60: RefPositions {#55@110 #56@111} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19CB8] Interval 61: (constant) RefPositions {#60@128 #61@129} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 62: RefPositions {#65@140 #66@141} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D10] Interval 63: RefPositions {#72@166 #73@167} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A9C8] Interval 64: RefPositions {#79@186 #80@187} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA20] Interval 65: RefPositions {#86@206 #88@207} physReg:NA Preferences=[rcx] Interval 66: RefPositions {#90@208 #97@213} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#91@210 #93@211} physReg:NA Preferences=[rdx] Interval 68: RefPositions {#95@212 #99@213} physReg:NA Preferences=[rdx] Interval 69: RefPositions {#108@214 #109@217} physReg:NA Preferences=[rax] Interval 70: RefPositions {#110@218 #111@219} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 71: (constant) RefPositions {#119@256 #120@257} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 72: (constant) RefPositions {#123@266 #124@269} physReg:NA Preferences=[allInt] Interval 73: RefPositions {#125@270 #126@271} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19E70] Interval 74: RefPositions {#129@282 #131@283} physReg:NA Preferences=[rcx] Interval 75: RefPositions {#133@284 #135@285} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#152@320 #153@321} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A658] Interval 77: RefPositions {#156@328 #157@329} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A6B0] Interval 78: RefPositions {#161@338 #162@339} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19EC8] Interval 79: (constant) RefPositions {#166@356 #167@357} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 80: RefPositions {#171@368 #172@369} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F20] Interval 81: RefPositions {#178@394 #179@395} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA78] Interval 82: RefPositions {#185@414 #186@415} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AAD0] Interval 83: RefPositions {#192@434 #194@435} physReg:NA Preferences=[rcx] Interval 84: RefPositions {#196@436 #203@441} physReg:NA Preferences=[rcx] Interval 85: RefPositions {#197@438 #199@439} physReg:NA Preferences=[rdx] Interval 86: RefPositions {#201@440 #205@441} physReg:NA Preferences=[rdx] Interval 87: RefPositions {#214@442 #215@445} physReg:NA Preferences=[rax] Interval 88: RefPositions {#216@446 #217@447} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 89: (INTERNAL) RefPositions {#225@489 #227@489} physReg:NA Preferences=[mm0-mm5] Interval 90: (specialPutArg) RefPositions {#231@494 #238@499} physReg:NA Preferences=[rcx] RelatedInterval [000001C31DA19AA8] Interval 91: RefPositions {#232@496 #234@497} physReg:NA Preferences=[rdx] Interval 92: RefPositions {#236@498 #240@499} physReg:NA Preferences=[rdx] Interval 93: RefPositions {#251@514 #252@515} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A760] Interval 94: RefPositions {#255@522 #256@523} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A7B8] Interval 95: RefPositions {#260@532 #261@533} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19FD0] Interval 96: (constant) RefPositions {#265@550 #266@551} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 97: RefPositions {#270@562 #271@563} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A028] Interval 98: RefPositions {#277@588 #278@589} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB28] Interval 99: RefPositions {#284@608 #285@609} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB80] Interval 100: RefPositions {#291@628 #293@629} physReg:NA Preferences=[rcx] Interval 101: RefPositions {#295@630 #302@635} physReg:NA Preferences=[rcx] Interval 102: RefPositions {#296@632 #298@633} physReg:NA Preferences=[rdx] Interval 103: RefPositions {#300@634 #304@635} physReg:NA Preferences=[rdx] Interval 104: RefPositions {#313@636 #314@639} physReg:NA Preferences=[rax] Interval 105: RefPositions {#315@640 #316@641} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 106: RefPositions {#329@690 #330@691} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A8C0] Interval 107: RefPositions {#333@698 #334@699} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A918] Interval 108: RefPositions {#338@708 #339@709} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A0D8] Interval 109: (constant) RefPositions {#343@726 #344@727} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 110: RefPositions {#348@738 #349@739} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A130] Interval 111: RefPositions {#355@764 #356@765} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1ABD8] Interval 112: RefPositions {#362@784 #363@785} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AC30] Interval 113: RefPositions {#369@804 #371@805} physReg:NA Preferences=[rcx] Interval 114: RefPositions {#373@806 #380@811} physReg:NA Preferences=[rcx] Interval 115: RefPositions {#374@808 #376@809} physReg:NA Preferences=[rdx] Interval 116: RefPositions {#378@810 #382@811} physReg:NA Preferences=[rdx] Interval 117: RefPositions {#391@812 #392@815} physReg:NA Preferences=[rax] Interval 118: RefPositions {#393@816 #394@817} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 119: (constant) RefPositions {#403@860 #404@861} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19B58] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ #45 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #116 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #4 RefTypeDef CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 last> #9 RefTypeDef ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #12 RefTypeDef CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #14 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #19 RefTypeDef GE BB01 regmask=[rcx] minReg=1> #20 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed> #25 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #100 RefTypeKill BB01 regmask=[rax] minReg=1 last> #87 RefTypeKill BB01 regmask=[rcx] minReg=1 last> #92 RefTypeKill BB01 regmask=[rdx] minReg=1 last> #103 RefTypeKill BB01 regmask=[r8] minReg=1 last> #104 RefTypeKill BB01 regmask=[r9] minReg=1 last> #105 RefTypeKill BB01 regmask=[r10] minReg=1 last> #106 RefTypeKill BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #49 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #47 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #51 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #56 RefTypeDef NE BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional> #61 RefTypeDef CNS_INT BB05 regmask=[allInt] minReg=1> BB05 regmask=[allInt] minReg=1 last> #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> #85 RefTypeUse LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> #66 RefTypeDef EQ BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> #73 RefTypeDef LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> #248 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #80 RefTypeDef LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> #88 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rcx] minReg=1> #89 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #96 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> #97 RefTypeDef PUTARG_REG BB08 regmask=[rcx] minReg=1 fixed> #93 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rdx] minReg=1> #94 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #98 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> #99 RefTypeDef PUTARG_REG BB08 regmask=[rdx] minReg=1 fixed> #101 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #102 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #107 RefTypeKill BB08 regmask=[rax] minReg=1 last> #130 RefTypeKill BB08 regmask=[rcx] minReg=1 last> #138 RefTypeKill BB08 regmask=[rdx] minReg=1 last> #139 RefTypeKill BB08 regmask=[r8] minReg=1 last> #140 RefTypeKill BB08 regmask=[r9] minReg=1 last> #141 RefTypeKill BB08 regmask=[r10] minReg=1 last> #142 RefTypeKill BB08 regmask=[r11] minReg=1 last> #136 RefTypeFixedReg BB08 regmask=[rax] minReg=1> #109 RefTypeDef CALL BB08 regmask=[rax] minReg=1 fixed> BB08 regmask=[allInt] minReg=1 last regOptional> #111 RefTypeDef EQ BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 last regOptional> #222 RefTypeUse LCL_VAR BB10 regmask=[allInt] minReg=1 last> #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> #120 RefTypeDef CNS_INT BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #124 RefTypeDef CNS_INT BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #126 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #131 RefTypeDef GE BB11 regmask=[rcx] minReg=1> #132 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #134 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #135 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #137 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #206 RefTypeKill BB11 regmask=[rax] minReg=1 last> #193 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #198 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #209 RefTypeKill BB11 regmask=[r8] minReg=1 last> #210 RefTypeKill BB11 regmask=[r9] minReg=1 last> #211 RefTypeKill BB11 regmask=[r10] minReg=1 last> #212 RefTypeKill BB11 regmask=[r11] minReg=1 last> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #153 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #157 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #162 RefTypeDef NE BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last regOptional> #167 RefTypeDef CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[allInt] minReg=1 last> #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[allInt] minReg=1> #191 RefTypeUse LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> #172 RefTypeDef EQ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[allInt] minReg=1> #179 RefTypeDef LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> #326 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> #186 RefTypeDef LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> #194 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rcx] minReg=1> #195 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB18 regmask=[rcx] minReg=1 fixed> #199 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rdx] minReg=1> #200 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB18 regmask=[rdx] minReg=1 fixed> #207 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #208 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #213 RefTypeKill BB18 regmask=[rax] minReg=1 last> #228 RefTypeKill BB18 regmask=[rcx] minReg=1 last> #233 RefTypeKill BB18 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB18 regmask=[r8] minReg=1 last> #245 RefTypeKill BB18 regmask=[r9] minReg=1 last> #246 RefTypeKill BB18 regmask=[r10] minReg=1 last> #247 RefTypeKill BB18 regmask=[r11] minReg=1 last> #241 RefTypeFixedReg BB18 regmask=[rax] minReg=1> #215 RefTypeDef CALL BB18 regmask=[rax] minReg=1 fixed> BB18 regmask=[allInt] minReg=1 last regOptional> #217 RefTypeDef EQ BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last regOptional> #321 RefTypeUse LCL_VAR BB20 regmask=[allInt] minReg=1 last> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> #227 RefTypeDef STORE_BLK BB21 regmask=[mm0-mm5] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> STORE_BLK BB21 regmask=[mm0-mm5] minReg=1 last> #230 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> #237 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #238 RefTypeDef PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> #234 RefTypeDef LCL_VAR_ADDR BB21 regmask=[rdx] minReg=1> #235 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #239 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> #240 RefTypeDef PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> #242 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> #243 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB21 regmask=[rax] minReg=1 last> #292 RefTypeKill BB21 regmask=[rcx] minReg=1 last> #297 RefTypeKill BB21 regmask=[rdx] minReg=1 last> #308 RefTypeKill BB21 regmask=[r8] minReg=1 last> #309 RefTypeKill BB21 regmask=[r9] minReg=1 last> #310 RefTypeKill BB21 regmask=[r10] minReg=1 last> #311 RefTypeKill BB21 regmask=[r11] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last> #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #254 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #252 RefTypeDef IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #256 RefTypeDef IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1 regOptional> #269 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #261 RefTypeDef NE BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> #266 RefTypeDef CNS_INT BB22 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 last> #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> #271 RefTypeDef EQ BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last regOptional> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> #278 RefTypeDef LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> #285 RefTypeDef LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> #293 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rcx] minReg=1> #294 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #301 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> #302 RefTypeDef PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> #298 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rdx] minReg=1> #299 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #303 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> #304 RefTypeDef PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> #306 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #307 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #312 RefTypeKill BB25 regmask=[rax] minReg=1 last> #370 RefTypeKill BB25 regmask=[rcx] minReg=1 last> #375 RefTypeKill BB25 regmask=[rdx] minReg=1 last> #386 RefTypeKill BB25 regmask=[r8] minReg=1 last> #387 RefTypeKill BB25 regmask=[r9] minReg=1 last> #388 RefTypeKill BB25 regmask=[r10] minReg=1 last> #389 RefTypeKill BB25 regmask=[r11] minReg=1 last> #383 RefTypeFixedReg BB25 regmask=[rax] minReg=1> #314 RefTypeDef CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[allInt] minReg=1 last regOptional> #316 RefTypeDef EQ BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> #399 RefTypeUse LCL_VAR BB27 regmask=[allInt] minReg=1 last> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #330 RefTypeDef IND BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #334 RefTypeDef IND BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> #347 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #339 RefTypeDef NE BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last regOptional> #344 RefTypeDef CNS_INT BB29 regmask=[allInt] minReg=1> BB29 regmask=[allInt] minReg=1 last> #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[allInt] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[allInt] minReg=1 regOptional> #349 RefTypeDef EQ BB30 regmask=[allInt] minReg=1> BB30 regmask=[allInt] minReg=1 last> #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> #356 RefTypeDef LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> #363 RefTypeDef LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> #371 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rcx] minReg=1> #372 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #379 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> #380 RefTypeDef PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> #376 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> #377 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #381 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> #382 RefTypeDef PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> #384 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #385 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #390 RefTypeKill BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> #407 RefTypeFixedReg BB32 regmask=[rax] minReg=1> #392 RefTypeDef CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[allInt] minReg=1 last regOptional> #394 RefTypeDef EQ BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last regOptional> #402 RefTypeUse LCL_VAR BB34 regmask=[allInt] minReg=1 last> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> #404 RefTypeDef CNS_INT BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB36 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> ----------------- #45 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #49 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> #254 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> ----------------- #116 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #222 RefTypeUse LCL_VAR BB10 regmask=[allInt] minReg=1 last> #321 RefTypeUse LCL_VAR BB20 regmask=[allInt] minReg=1 last> TryParse: LocalVar V01: undefined use at 469 #399 RefTypeUse LCL_VAR BB27 regmask=[allInt] minReg=1 last> TryParse: LocalVar V01: undefined use at 663 #402 RefTypeUse LCL_VAR BB34 regmask=[allInt] minReg=1 last> TryParse: LocalVar V01: undefined use at 839 LCL_VAR BB35 regmask=[allInt] minReg=1 last> TryParse: LocalVar V01: undefined use at 855 ----------------- #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #248 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last> ----------------- #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> ----------------- #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> ----------------- #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #85 RefTypeUse LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> ----------------- #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #326 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> ----------------- ----------------- #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional> ----------------- #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> ----------------- #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 last regOptional> ----------------- #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #191 RefTypeUse LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #269 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #347 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> ----------------- #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> ----------------- #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[allInt] minReg=1> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[allInt] minReg=1> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last regOptional> ----------------- #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> ----------------- #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[allInt] minReg=1> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last regOptional> ----------------- #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> ----------------- #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- ----------------- ----------------- #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last regOptional> ----------------- #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> ----------------- #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last regOptional> ----------------- #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB11 regmask=[allInt] minReg=1 last> ----------------- #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> ----------------- #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> ----------------- #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> ----------------- #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> ----------------- #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last regOptional> ----------------- #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> ----------------- #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 V01 BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} ===== N003. IL_OFFSET IL offset: 0x1 REG NA N005. IL_OFFSET IL offset: 0x1 REG NA N007. CNS_INT(h) 0x421150 [ICON_STR_HDL] REG NA Def:(#3) Pref: N009. V96(L43) Use:(#4) * Def:(#5) N011. V96(L43) N013. NULLCHECK Use:(#6) N015. V96(L43) N017. CNS_INT 12 field offset Fseq[_firstChar] REG NA N019. ADD Use:(#7) * Def:(#8) Pref: N021. V10(L4) Use:(#9) * Def:(#10) Pref: N023. IL_OFFSET IL offset: 0x1 REG NA N025. CNS_INT(h) 0x421150 [ICON_STR_HDL] REG NA Def:(#11) N027. LEA(b+8) N029. IND Use:(#12) * Def:(#13) Pref: N031. V14(L5) Use:(#14) * Def:(#15) Pref: N033. IL_OFFSET IL offset: 0x1 REG NA N035. IL_OFFSET IL offset: 0x1 REG NA N037. V14(L5) N039. CNS_INT 0 REG NA N041. GE Use:(#16) Def:(#17) N043. PUTARG_REG Use:(#19) Fixed:rcx(#18) * Def:(#21) rcx N045. CALL Use:(#23) Fixed:rcx(#22) * Kill: rax rcx rdx r8 r9 r10 r11 N047. IL_OFFSET IL offset: 0x1 REG NA N049. V10(L4) N051. V71(L29) Use:(#31) * Def:(#32) Pref: N053. IL_OFFSET IL offset: 0x1 REG NA N055. V71(L29) N057. V65(L25) Use:(#33) * Def:(#34) Pref: N059. IL_OFFSET IL offset: 0x1 REG NA N061. V14(L5) N063. V66(L26) Use:(#35) * Def:(#36) Pref: N065. IL_OFFSET IL offset: 0x1 REG NA N067. V65(L25) N069. V67(L27) Use:(#37) * Def:(#38) Pref: N071. V66(L26) N073. V68(L28) Use:(#39) * Def:(#40) Pref: N075. V67(L27) N077. V61(L21) Use:(#41) * Def:(#42) N079. V68(L28) N081. V62(L22) Use:(#43) * Def:(#44) Pref: N083. IL_OFFSET IL offset: 0xc REG NA N085. IL_OFFSET IL offset: 0xc REG NA N087. V00(L0) N089. LEA(b+0) N091. IND Use:(#45) Def:(#46) Pref: N093. V74(L30) Use:(#47) * Def:(#48) N095. V00(L0) N097. LEA(b+8) N099. IND Use:(#49) Def:(#50) Pref: N101. V75(L31) Use:(#51) * Def:(#52) N103. IL_OFFSET IL offset: 0xc REG NA N105. V62(L22) N107. V75(L31) N109. NE Use:(#53) Use:(#54) Def:(#55) Pref: N111. V19(L6) Use:(#56) * Def:(#57) N113. IL_OFFSET IL offset: 0xc REG NA N115. V19(L6) N117. CNS_INT 0 REG NA N119. EQ Use:(#58) * N121. JTRUE BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ===== N125. IL_OFFSET IL offset: 0xc REG NA N127. CNS_INT 0 REG NA Def:(#60) Pref: N129. V21(L8) Use:(#61) * Def:(#62) BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ===== N133. IL_OFFSET IL offset: 0xc REG NA N135. V75(L31) N137. CNS_INT 0 REG NA N139. EQ Use:(#64) Def:(#65) Pref: N141. V20(L7) Use:(#66) * Def:(#67) N143. IL_OFFSET IL offset: 0xc REG NA N145. V20(L7) N147. CNS_INT 0 REG NA N149. EQ Use:(#68) * N151. JTRUE BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ===== N155. IL_OFFSET IL offset: 0xc REG NA N157. CNS_INT 1 REG NA N159. V21(L8) Def:(#70) BB08 [00C..00D), preds={BB06} succs={BB09} ===== N163. IL_OFFSET IL offset: 0xc REG NA N165. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#72) Pref: N167. V98(L44) Use:(#73) * Def:(#74) N169. V98(L44) N171. LEA(b+0) N173. V61(L21) N175. STOREIND Use:(#75) Use:(#76) N177. V98(L44) N179. LEA(b+8) N181. V62(L22) N183. STOREIND Use:(#77) * Use:(#78) N185. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#79) Pref: N187. V100(L45) Use:(#80) * Def:(#81) N189. V100(L45) N191. LEA(b+0) N193. V74(L30) N195. STOREIND Use:(#82) Use:(#83) * N197. V100(L45) N199. LEA(b+8) N201. V75(L31) N203. STOREIND Use:(#84) * Use:(#85) * N205. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#86) N207. PUTARG_REG Use:(#88) Fixed:rcx(#87) * Def:(#90) rcx N209. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#91) N211. PUTARG_REG Use:(#93) Fixed:rdx(#92) * Def:(#95) rdx N213. CALL Use:(#97) Fixed:rcx(#96) * Use:(#99) Fixed:rdx(#98) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#108) rax N215. CNS_INT 0 REG NA N217. EQ Use:(#109) * Def:(#110) Pref: N219. V21(L8) Use:(#111) * Def:(#112) BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ===== N223. IL_OFFSET IL offset: 0x14 REG NA N225. V21(L8) N227. CNS_INT 0 REG NA N229. EQ Use:(#114) * N231. JTRUE BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ===== N235. IL_OFFSET IL offset: 0x18 REG NA N237. V01(L1) N239. CNS_INT 1 REG NA N241. STOREIND Use:(#116) * N243. IL_OFFSET IL offset: 0x1b REG NA N245. CNS_INT 1 REG NA N247. V05(L2) Def:(#117) BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} ===== N251. IL_OFFSET IL offset: 0x1f REG NA N253. IL_OFFSET IL offset: 0x1f REG NA N255. CNS_INT(h) 0x421158 [ICON_STR_HDL] REG NA Def:(#119) Pref: N257. V96(L43) Use:(#120) * Def:(#121) N259. V96(L43) N261. NULLCHECK Use:(#122) * N263. IL_OFFSET IL offset: 0x1f REG NA N265. CNS_INT(h) 0x421158 [ICON_STR_HDL] REG NA Def:(#123) N267. LEA(b+8) N269. IND Use:(#124) * Def:(#125) Pref: N271. V30(L11) Use:(#126) * Def:(#127) Pref: N273. IL_OFFSET IL offset: 0x1f REG NA N275. IL_OFFSET IL offset: 0x1f REG NA N277. V30(L11) N279. CNS_INT 0 REG NA N281. GE Use:(#128) Def:(#129) N283. PUTARG_REG Use:(#131) Fixed:rcx(#130) * Def:(#133) rcx N285. CALL Use:(#135) Fixed:rcx(#134) * Kill: rax rcx rdx r8 r9 r10 r11 N287. IL_OFFSET IL offset: 0x1f REG NA N289. IL_OFFSET IL offset: 0x1f REG NA N291. IL_OFFSET IL offset: 0x1f REG NA N293. V30(L11) N295. V77(L32) Use:(#143) * Def:(#144) Pref: N297. IL_OFFSET IL offset: 0x1f REG NA N299. V77(L32) N301. V79(L33) Use:(#145) * Def:(#146) Pref: N303. V61(L21) N305. V63(L23) Use:(#147) Def:(#148) Pref: N307. V79(L33) N309. V64(L24) Use:(#149) * Def:(#150) Pref: N311. IL_OFFSET IL offset: 0x2a REG NA N313. IL_OFFSET IL offset: 0x2a REG NA N315. V00(L0) N317. LEA(b+0) N319. IND Use:(#151) Def:(#152) Pref: N321. V85(L34) Use:(#153) * Def:(#154) N323. V00(L0) N325. LEA(b+8) N327. IND Use:(#155) Def:(#156) Pref: N329. V86(L35) Use:(#157) * Def:(#158) N331. IL_OFFSET IL offset: 0x2a REG NA N333. V64(L24) N335. V86(L35) N337. NE Use:(#159) Use:(#160) Def:(#161) Pref: N339. V35(L12) Use:(#162) * Def:(#163) N341. IL_OFFSET IL offset: 0x2a REG NA N343. V35(L12) N345. CNS_INT 0 REG NA N347. EQ Use:(#164) * N349. JTRUE BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ===== N353. IL_OFFSET IL offset: 0x2a REG NA N355. CNS_INT 0 REG NA Def:(#166) Pref: N357. V37(L14) Use:(#167) * Def:(#168) BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ===== N361. IL_OFFSET IL offset: 0x2a REG NA N363. V86(L35) N365. CNS_INT 0 REG NA N367. EQ Use:(#170) Def:(#171) Pref: N369. V36(L13) Use:(#172) * Def:(#173) N371. IL_OFFSET IL offset: 0x2a REG NA N373. V36(L13) N375. CNS_INT 0 REG NA N377. EQ Use:(#174) * N379. JTRUE BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ===== N383. IL_OFFSET IL offset: 0x2a REG NA N385. CNS_INT 1 REG NA N387. V37(L14) Def:(#176) BB18 [02A..02B), preds={BB16} succs={BB19} ===== N391. IL_OFFSET IL offset: 0x2a REG NA N393. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#178) Pref: N395. V101(L46) Use:(#179) * Def:(#180) N397. V101(L46) N399. LEA(b+0) N401. V61(L21) N403. STOREIND Use:(#181) Use:(#182) * N405. V101(L46) N407. LEA(b+8) N409. V64(L24) N411. STOREIND Use:(#183) * Use:(#184) N413. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#185) Pref: N415. V102(L47) Use:(#186) * Def:(#187) N417. V102(L47) N419. LEA(b+0) N421. V85(L34) N423. STOREIND Use:(#188) Use:(#189) * N425. V102(L47) N427. LEA(b+8) N429. V86(L35) N431. STOREIND Use:(#190) * Use:(#191) * N433. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#192) N435. PUTARG_REG Use:(#194) Fixed:rcx(#193) * Def:(#196) rcx N437. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#197) N439. PUTARG_REG Use:(#199) Fixed:rdx(#198) * Def:(#201) rdx N441. CALL Use:(#203) Fixed:rcx(#202) * Use:(#205) Fixed:rdx(#204) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#214) rax N443. CNS_INT 0 REG NA N445. EQ Use:(#215) * Def:(#216) Pref: N447. V37(L14) Use:(#217) * Def:(#218) BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ===== N451. IL_OFFSET IL offset: 0x33 REG NA N453. V37(L14) N455. CNS_INT 0 REG NA N457. EQ Use:(#220) * N459. JTRUE BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ===== N463. IL_OFFSET IL offset: 0x38 REG NA N465. V01(L1) N467. CNS_INT 0 REG NA N469. STOREIND Use:(#222) * N471. IL_OFFSET IL offset: 0x3b REG NA N473. CNS_INT 1 REG NA N475. V05(L2) Def:(#223) BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ===== N479. IL_OFFSET IL offset: 0x3f REG NA N481. NOP N483. V00(L0) N485. IND N487. LCL_VAR_ADDR V97 tmp88 NA REG NA N489. STORE_BLK(16) Def:(#225) Use:(#226) Use:(#227) * N491. V00(L0) N493. PUTARG_REG Use:(#229) Fixed:rcx(#228) Def:(#231) rcx Pref: N495. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#232) N497. PUTARG_REG Use:(#234) Fixed:rdx(#233) * Def:(#236) rdx N499. CALL Use:(#238) Fixed:rcx(#237) * Use:(#240) Fixed:rdx(#239) * Kill: rax rcx rdx r8 r9 r10 r11 N501. IL_OFFSET IL offset: 0x47 REG NA N503. V62(L22) N505. V88(L36) Use:(#248) * Def:(#249) N507. IL_OFFSET IL offset: 0x47 REG NA N509. V00(L0) N511. LEA(b+0) N513. IND Use:(#250) Def:(#251) Pref: N515. V89(L37) Use:(#252) * Def:(#253) N517. V00(L0) N519. LEA(b+8) N521. IND Use:(#254) Def:(#255) Pref: N523. V90(L38) Use:(#256) * Def:(#257) N525. IL_OFFSET IL offset: 0x47 REG NA N527. V88(L36) N529. V90(L38) N531. NE Use:(#258) Use:(#259) Def:(#260) Pref: N533. V44(L15) Use:(#261) * Def:(#262) N535. IL_OFFSET IL offset: 0x47 REG NA N537. V44(L15) N539. CNS_INT 0 REG NA N541. EQ Use:(#263) * N543. JTRUE BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ===== N547. IL_OFFSET IL offset: 0x47 REG NA N549. CNS_INT 0 REG NA Def:(#265) Pref: N551. V46(L17) Use:(#266) * Def:(#267) BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ===== N555. IL_OFFSET IL offset: 0x47 REG NA N557. V90(L38) N559. CNS_INT 0 REG NA N561. EQ Use:(#269) Def:(#270) Pref: N563. V45(L16) Use:(#271) * Def:(#272) N565. IL_OFFSET IL offset: 0x47 REG NA N567. V45(L16) N569. CNS_INT 0 REG NA N571. EQ Use:(#273) * N573. JTRUE BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ===== N577. IL_OFFSET IL offset: 0x47 REG NA N579. CNS_INT 1 REG NA N581. V46(L17) Def:(#275) BB25 [047..048), preds={BB23} succs={BB26} ===== N585. IL_OFFSET IL offset: 0x47 REG NA N587. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#277) Pref: N589. V104(L48) Use:(#278) * Def:(#279) N591. V104(L48) N593. LEA(b+0) N595. V63(L23) N597. STOREIND Use:(#280) Use:(#281) N599. V104(L48) N601. LEA(b+8) N603. V88(L36) N605. STOREIND Use:(#282) * Use:(#283) * N607. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#284) Pref: N609. V105(L49) Use:(#285) * Def:(#286) N611. V105(L49) N613. LEA(b+0) N615. V89(L37) N617. STOREIND Use:(#287) Use:(#288) * N619. V105(L49) N621. LEA(b+8) N623. V90(L38) N625. STOREIND Use:(#289) * Use:(#290) * N627. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#291) N629. PUTARG_REG Use:(#293) Fixed:rcx(#292) * Def:(#295) rcx N631. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#296) N633. PUTARG_REG Use:(#298) Fixed:rdx(#297) * Def:(#300) rdx N635. CALL Use:(#302) Fixed:rcx(#301) * Use:(#304) Fixed:rdx(#303) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#313) rax N637. CNS_INT 0 REG NA N639. EQ Use:(#314) * Def:(#315) Pref: N641. V46(L17) Use:(#316) * Def:(#317) BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ===== N645. IL_OFFSET IL offset: 0x50 REG NA N647. V46(L17) N649. CNS_INT 0 REG NA N651. EQ Use:(#319) * N653. JTRUE BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ===== N657. IL_OFFSET IL offset: 0x55 REG NA N659. V01(L1) N661. CNS_INT 1 REG NA N663. STOREIND Use:(#321) * N665. IL_OFFSET IL offset: 0x58 REG NA N667. CNS_INT 1 REG NA N669. V05(L2) Def:(#322) BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ===== N673. IL_OFFSET IL offset: 0x5c REG NA N675. V63(L23) N677. V91(L39) Use:(#324) * Def:(#325) N679. V64(L24) N681. V92(L40) Use:(#326) * Def:(#327) N683. IL_OFFSET IL offset: 0x5c REG NA N685. V00(L0) N687. LEA(b+0) N689. IND Use:(#328) Def:(#329) Pref: N691. V93(L41) Use:(#330) * Def:(#331) N693. V00(L0) N695. LEA(b+8) N697. IND Use:(#332) * Def:(#333) Pref: N699. V94(L42) Use:(#334) * Def:(#335) N701. IL_OFFSET IL offset: 0x5c REG NA N703. V92(L40) N705. V94(L42) N707. NE Use:(#336) Use:(#337) Def:(#338) Pref: N709. V53(L18) Use:(#339) * Def:(#340) N711. IL_OFFSET IL offset: 0x5c REG NA N713. V53(L18) N715. CNS_INT 0 REG NA N717. EQ Use:(#341) * N719. JTRUE BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ===== N723. IL_OFFSET IL offset: 0x5c REG NA N725. CNS_INT 0 REG NA Def:(#343) Pref: N727. V55(L20) Use:(#344) * Def:(#345) BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ===== N731. IL_OFFSET IL offset: 0x5c REG NA N733. V94(L42) N735. CNS_INT 0 REG NA N737. EQ Use:(#347) Def:(#348) Pref: N739. V54(L19) Use:(#349) * Def:(#350) N741. IL_OFFSET IL offset: 0x5c REG NA N743. V54(L19) N745. CNS_INT 0 REG NA N747. EQ Use:(#351) * N749. JTRUE BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ===== N753. IL_OFFSET IL offset: 0x5c REG NA N755. CNS_INT 1 REG NA N757. V55(L20) Def:(#353) BB32 [05C..05D), preds={BB30} succs={BB33} ===== N761. IL_OFFSET IL offset: 0x5c REG NA N763. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#355) Pref: N765. V106(L50) Use:(#356) * Def:(#357) N767. V106(L50) N769. LEA(b+0) N771. V91(L39) N773. STOREIND Use:(#358) Use:(#359) * N775. V106(L50) N777. LEA(b+8) N779. V92(L40) N781. STOREIND Use:(#360) * Use:(#361) * N783. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#362) Pref: N785. V107(L51) Use:(#363) * Def:(#364) N787. V107(L51) N789. LEA(b+0) N791. V93(L41) N793. STOREIND Use:(#365) Use:(#366) * N795. V107(L51) N797. LEA(b+8) N799. V94(L42) N801. STOREIND Use:(#367) * Use:(#368) * N803. LCL_VAR_ADDR V97 tmp88 NA REG NA Def:(#369) N805. PUTARG_REG Use:(#371) Fixed:rcx(#370) * Def:(#373) rcx N807. LCL_VAR_ADDR V99 tmp90 NA REG NA Def:(#374) N809. PUTARG_REG Use:(#376) Fixed:rdx(#375) * Def:(#378) rdx N811. CALL Use:(#380) Fixed:rcx(#379) * Use:(#382) Fixed:rdx(#381) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#391) rax N813. CNS_INT 0 REG NA N815. EQ Use:(#392) * Def:(#393) Pref: N817. V55(L20) Use:(#394) * Def:(#395) BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ===== N821. IL_OFFSET IL offset: 0x65 REG NA N823. V55(L20) N825. CNS_INT 0 REG NA N827. EQ Use:(#397) * N829. JTRUE BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ===== N833. IL_OFFSET IL offset: 0x6a REG NA N835. V01(L1) N837. CNS_INT 0 REG NA N839. STOREIND Use:(#399) * N841. IL_OFFSET IL offset: 0x6d REG NA N843. CNS_INT 1 REG NA N845. V05(L2) Def:(#400) BB35 [071..078), preds={BB33} succs={BB36} ===== N849. IL_OFFSET IL offset: 0x71 REG NA N851. V01(L1) N853. CNS_INT 0 REG NA N855. STOREIND Use:(#402) * N857. IL_OFFSET IL offset: 0x74 REG NA N859. CNS_INT 0 REG NA Def:(#403) Pref: N861. V05(L2) Use:(#404) * Def:(#405) BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ===== N865. IL_OFFSET IL offset: 0x78 REG NA N867. V05(L2) N869. RETURN Use:(#408) Fixed:rax(#407) * Linear scan intervals after buildIntervals: Interval 0: (V00) RefPositions {#0@0 #45@91 #49@99 #151@319 #155@327 #226@489 #229@493 #250@513 #254@521 #328@689 #332@697} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) RefPositions {#1@0 #116@241 #222@469 #321@663 #399@839 #402@855} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V05) RefPositions {#117@248 #223@476 #322@670 #400@846 #405@862 #408@869} physReg:NA Preferences=[rax] Interval 3: (V09) RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V10) RefPositions {#10@22 #31@51} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A4A0] Interval 5: (V14) RefPositions {#15@32 #16@41 #35@63} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A398] Interval 6: (V19) RefPositions {#57@112 #58@119} physReg:NA Preferences=[allInt] Interval 7: (V20) RefPositions {#67@142 #68@149} physReg:NA Preferences=[allInt] Interval 8: (V21) RefPositions {#62@130 #70@160 #112@220 #114@229} physReg:NA Preferences=[allInt] Interval 9: (V25) RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V26) RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V30) RefPositions {#127@272 #128@281 #143@295} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A5A8] Interval 12: (V35) RefPositions {#163@340 #164@347} physReg:NA Preferences=[allInt] Interval 13: (V36) RefPositions {#173@370 #174@377} physReg:NA Preferences=[allInt] Interval 14: (V37) RefPositions {#168@358 #176@388 #218@448 #220@457} physReg:NA Preferences=[allInt] Interval 15: (V44) RefPositions {#262@534 #263@541} physReg:NA Preferences=[allInt] Interval 16: (V45) RefPositions {#272@564 #273@571} physReg:NA Preferences=[allInt] Interval 17: (V46) RefPositions {#267@552 #275@582 #317@642 #319@651} physReg:NA Preferences=[allInt] Interval 18: (V53) RefPositions {#340@710 #341@717} physReg:NA Preferences=[allInt] Interval 19: (V54) RefPositions {#350@740 #351@747} physReg:NA Preferences=[allInt] Interval 20: (V55) RefPositions {#345@728 #353@758 #395@818 #397@827} physReg:NA Preferences=[allInt] Interval 21: (V61) (struct) RefPositions {#42@78 #76@175 #147@305 #182@403} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 22: (V62) (struct) RefPositions {#44@82 #53@109 #78@183 #248@505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A708] Interval 23: (V63) (struct) RefPositions {#148@306 #281@597 #324@677} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A810] Interval 24: (V64) (struct) RefPositions {#150@310 #159@337 #184@411 #326@681} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A868] Interval 25: (V65) (struct) RefPositions {#34@58 #37@69} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A3F0] Interval 26: (V66) (struct) RefPositions {#36@64 #39@73} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A448] Interval 27: (V67) (struct) RefPositions {#38@70 #41@77} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A1E0] Interval 28: (V68) (struct) RefPositions {#40@74 #43@81} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A238] Interval 29: (V71) (struct) RefPositions {#32@52 #33@57} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A340] Interval 30: (V74) (struct) RefPositions {#48@94 #83@195} physReg:NA Preferences=[allInt] Interval 31: (V75) (struct) RefPositions {#52@102 #54@109 #64@139 #85@203} physReg:NA Preferences=[allInt] Interval 32: (V77) (struct) RefPositions {#144@296 #145@301} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A600] Interval 33: (V79) (struct) RefPositions {#146@302 #149@309} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A2E8] Interval 34: (V85) (struct) RefPositions {#154@322 #189@423} physReg:NA Preferences=[allInt] Interval 35: (V86) (struct) RefPositions {#158@330 #160@337 #170@367 #191@431} physReg:NA Preferences=[allInt] Interval 36: (V88) (struct) RefPositions {#249@506 #258@531 #283@605} physReg:NA Preferences=[allInt] Interval 37: (V89) (struct) RefPositions {#253@516 #288@617} physReg:NA Preferences=[allInt] Interval 38: (V90) (struct) RefPositions {#257@524 #259@531 #269@561 #290@625} physReg:NA Preferences=[allInt] Interval 39: (V91) (struct) RefPositions {#325@678 #359@773} physReg:NA Preferences=[allInt] Interval 40: (V92) (struct) RefPositions {#327@682 #336@707 #361@781} physReg:NA Preferences=[allInt] Interval 41: (V93) (struct) RefPositions {#331@692 #366@793} physReg:NA Preferences=[allInt] Interval 42: (V94) (struct) RefPositions {#335@700 #337@707 #347@737 #368@801} physReg:NA Preferences=[allInt] Interval 43: (V96) RefPositions {#5@10 #6@13 #7@19 #121@258 #122@261} physReg:NA Preferences=[allInt] Interval 44: (V98) RefPositions {#74@168 #75@175 #77@183} physReg:NA Preferences=[allInt] Interval 45: (V100) RefPositions {#81@188 #82@195 #84@203} physReg:NA Preferences=[allInt] Interval 46: (V101) RefPositions {#180@396 #181@403 #183@411} physReg:NA Preferences=[allInt] Interval 47: (V102) RefPositions {#187@416 #188@423 #190@431} physReg:NA Preferences=[allInt] Interval 48: (V104) RefPositions {#279@590 #280@597 #282@605} physReg:NA Preferences=[allInt] Interval 49: (V105) RefPositions {#286@610 #287@617 #289@625} physReg:NA Preferences=[allInt] Interval 50: (V106) RefPositions {#357@766 #358@773 #360@781} physReg:NA Preferences=[allInt] Interval 51: (V107) RefPositions {#364@786 #365@793 #367@801} physReg:NA Preferences=[allInt] Interval 52: (constant) RefPositions {#3@8 #4@9} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 53: RefPositions {#8@20 #9@21} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C08] Interval 54: (constant) RefPositions {#11@26 #12@29} physReg:NA Preferences=[allInt] Interval 55: RefPositions {#13@30 #14@31} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C60] Interval 56: RefPositions {#17@42 #19@43} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#21@44 #23@45} physReg:NA Preferences=[rcx] Interval 58: RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A4F8] Interval 59: RefPositions {#50@100 #51@101} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A550] Interval 60: RefPositions {#55@110 #56@111} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19CB8] Interval 61: (constant) RefPositions {#60@128 #61@129} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 62: RefPositions {#65@140 #66@141} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D10] Interval 63: RefPositions {#72@166 #73@167} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A9C8] Interval 64: RefPositions {#79@186 #80@187} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA20] Interval 65: RefPositions {#86@206 #88@207} physReg:NA Preferences=[rcx] Interval 66: RefPositions {#90@208 #97@213} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#91@210 #93@211} physReg:NA Preferences=[rdx] Interval 68: RefPositions {#95@212 #99@213} physReg:NA Preferences=[rdx] Interval 69: RefPositions {#108@214 #109@217} physReg:NA Preferences=[rax] Interval 70: RefPositions {#110@218 #111@219} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 71: (constant) RefPositions {#119@256 #120@257} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 72: (constant) RefPositions {#123@266 #124@269} physReg:NA Preferences=[allInt] Interval 73: RefPositions {#125@270 #126@271} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19E70] Interval 74: RefPositions {#129@282 #131@283} physReg:NA Preferences=[rcx] Interval 75: RefPositions {#133@284 #135@285} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#152@320 #153@321} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A658] Interval 77: RefPositions {#156@328 #157@329} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A6B0] Interval 78: RefPositions {#161@338 #162@339} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19EC8] Interval 79: (constant) RefPositions {#166@356 #167@357} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 80: RefPositions {#171@368 #172@369} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F20] Interval 81: RefPositions {#178@394 #179@395} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA78] Interval 82: RefPositions {#185@414 #186@415} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AAD0] Interval 83: RefPositions {#192@434 #194@435} physReg:NA Preferences=[rcx] Interval 84: RefPositions {#196@436 #203@441} physReg:NA Preferences=[rcx] Interval 85: RefPositions {#197@438 #199@439} physReg:NA Preferences=[rdx] Interval 86: RefPositions {#201@440 #205@441} physReg:NA Preferences=[rdx] Interval 87: RefPositions {#214@442 #215@445} physReg:NA Preferences=[rax] Interval 88: RefPositions {#216@446 #217@447} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 89: (INTERNAL) RefPositions {#225@489 #227@489} physReg:NA Preferences=[mm0-mm5] Interval 90: (specialPutArg) RefPositions {#231@494 #238@499} physReg:NA Preferences=[rcx] RelatedInterval [000001C31DA19AA8] Interval 91: RefPositions {#232@496 #234@497} physReg:NA Preferences=[rdx] Interval 92: RefPositions {#236@498 #240@499} physReg:NA Preferences=[rdx] Interval 93: RefPositions {#251@514 #252@515} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A760] Interval 94: RefPositions {#255@522 #256@523} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A7B8] Interval 95: RefPositions {#260@532 #261@533} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19FD0] Interval 96: (constant) RefPositions {#265@550 #266@551} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 97: RefPositions {#270@562 #271@563} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A028] Interval 98: RefPositions {#277@588 #278@589} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB28] Interval 99: RefPositions {#284@608 #285@609} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB80] Interval 100: RefPositions {#291@628 #293@629} physReg:NA Preferences=[rcx] Interval 101: RefPositions {#295@630 #302@635} physReg:NA Preferences=[rcx] Interval 102: RefPositions {#296@632 #298@633} physReg:NA Preferences=[rdx] Interval 103: RefPositions {#300@634 #304@635} physReg:NA Preferences=[rdx] Interval 104: RefPositions {#313@636 #314@639} physReg:NA Preferences=[rax] Interval 105: RefPositions {#315@640 #316@641} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 106: RefPositions {#329@690 #330@691} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A8C0] Interval 107: RefPositions {#333@698 #334@699} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A918] Interval 108: RefPositions {#338@708 #339@709} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A0D8] Interval 109: (constant) RefPositions {#343@726 #344@727} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 110: RefPositions {#348@738 #349@739} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A130] Interval 111: RefPositions {#355@764 #356@765} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1ABD8] Interval 112: RefPositions {#362@784 #363@785} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AC30] Interval 113: RefPositions {#369@804 #371@805} physReg:NA Preferences=[rcx] Interval 114: RefPositions {#373@806 #380@811} physReg:NA Preferences=[rcx] Interval 115: RefPositions {#374@808 #376@809} physReg:NA Preferences=[rdx] Interval 116: RefPositions {#378@810 #382@811} physReg:NA Preferences=[rdx] Interval 117: RefPositions {#391@812 #392@815} physReg:NA Preferences=[rax] Interval 118: RefPositions {#393@816 #394@817} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 119: (constant) RefPositions {#403@860 #404@861} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19B58] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) RefPositions {#0@0 #45@91 #49@99 #151@319 #155@327 #226@489 #229@493 #250@513 #254@521 #328@689 #332@697} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) RefPositions {#1@0 #116@241 #222@469 #321@663 #399@839 #402@855} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V05) RefPositions {#117@248 #223@476 #322@670 #400@846 #405@862 #408@869} physReg:NA Preferences=[rax] Interval 3: (V09) RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V10) RefPositions {#10@22 #31@51} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A4A0] Interval 5: (V14) RefPositions {#15@32 #16@41 #35@63} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A398] Interval 6: (V19) RefPositions {#57@112 #58@119} physReg:NA Preferences=[allInt] Interval 7: (V20) RefPositions {#67@142 #68@149} physReg:NA Preferences=[allInt] Interval 8: (V21) RefPositions {#62@130 #70@160 #112@220 #114@229} physReg:NA Preferences=[allInt] Interval 9: (V25) RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V26) RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V30) RefPositions {#127@272 #128@281 #143@295} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A5A8] Interval 12: (V35) RefPositions {#163@340 #164@347} physReg:NA Preferences=[allInt] Interval 13: (V36) RefPositions {#173@370 #174@377} physReg:NA Preferences=[allInt] Interval 14: (V37) RefPositions {#168@358 #176@388 #218@448 #220@457} physReg:NA Preferences=[allInt] Interval 15: (V44) RefPositions {#262@534 #263@541} physReg:NA Preferences=[allInt] Interval 16: (V45) RefPositions {#272@564 #273@571} physReg:NA Preferences=[allInt] Interval 17: (V46) RefPositions {#267@552 #275@582 #317@642 #319@651} physReg:NA Preferences=[allInt] Interval 18: (V53) RefPositions {#340@710 #341@717} physReg:NA Preferences=[allInt] Interval 19: (V54) RefPositions {#350@740 #351@747} physReg:NA Preferences=[allInt] Interval 20: (V55) RefPositions {#345@728 #353@758 #395@818 #397@827} physReg:NA Preferences=[allInt] Interval 21: (V61) (struct) RefPositions {#42@78 #76@175 #147@305 #182@403} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 22: (V62) (struct) RefPositions {#44@82 #53@109 #78@183 #248@505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A708] Interval 23: (V63) (struct) RefPositions {#148@306 #281@597 #324@677} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A810] Interval 24: (V64) (struct) RefPositions {#150@310 #159@337 #184@411 #326@681} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval [000001C31DA1A868] Interval 25: (V65) (struct) RefPositions {#34@58 #37@69} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A3F0] Interval 26: (V66) (struct) RefPositions {#36@64 #39@73} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A448] Interval 27: (V67) (struct) RefPositions {#38@70 #41@77} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A1E0] Interval 28: (V68) (struct) RefPositions {#40@74 #43@81} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A238] Interval 29: (V71) (struct) RefPositions {#32@52 #33@57} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A340] Interval 30: (V74) (struct) RefPositions {#48@94 #83@195} physReg:NA Preferences=[allInt] Interval 31: (V75) (struct) RefPositions {#52@102 #54@109 #64@139 #85@203} physReg:NA Preferences=[allInt] Interval 32: (V77) (struct) RefPositions {#144@296 #145@301} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A600] Interval 33: (V79) (struct) RefPositions {#146@302 #149@309} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A2E8] Interval 34: (V85) (struct) RefPositions {#154@322 #189@423} physReg:NA Preferences=[allInt] Interval 35: (V86) (struct) RefPositions {#158@330 #160@337 #170@367 #191@431} physReg:NA Preferences=[allInt] Interval 36: (V88) (struct) RefPositions {#249@506 #258@531 #283@605} physReg:NA Preferences=[allInt] Interval 37: (V89) (struct) RefPositions {#253@516 #288@617} physReg:NA Preferences=[allInt] Interval 38: (V90) (struct) RefPositions {#257@524 #259@531 #269@561 #290@625} physReg:NA Preferences=[allInt] Interval 39: (V91) (struct) RefPositions {#325@678 #359@773} physReg:NA Preferences=[allInt] Interval 40: (V92) (struct) RefPositions {#327@682 #336@707 #361@781} physReg:NA Preferences=[allInt] Interval 41: (V93) (struct) RefPositions {#331@692 #366@793} physReg:NA Preferences=[allInt] Interval 42: (V94) (struct) RefPositions {#335@700 #337@707 #347@737 #368@801} physReg:NA Preferences=[allInt] Interval 43: (V96) RefPositions {#5@10 #6@13 #7@19 #121@258 #122@261} physReg:NA Preferences=[allInt] Interval 44: (V98) RefPositions {#74@168 #75@175 #77@183} physReg:NA Preferences=[allInt] Interval 45: (V100) RefPositions {#81@188 #82@195 #84@203} physReg:NA Preferences=[allInt] Interval 46: (V101) RefPositions {#180@396 #181@403 #183@411} physReg:NA Preferences=[allInt] Interval 47: (V102) RefPositions {#187@416 #188@423 #190@431} physReg:NA Preferences=[allInt] Interval 48: (V104) RefPositions {#279@590 #280@597 #282@605} physReg:NA Preferences=[allInt] Interval 49: (V105) RefPositions {#286@610 #287@617 #289@625} physReg:NA Preferences=[allInt] Interval 50: (V106) RefPositions {#357@766 #358@773 #360@781} physReg:NA Preferences=[allInt] Interval 51: (V107) RefPositions {#364@786 #365@793 #367@801} physReg:NA Preferences=[allInt] Interval 52: (constant) RefPositions {#3@8 #4@9} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 53: RefPositions {#8@20 #9@21} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C08] Interval 54: (constant) RefPositions {#11@26 #12@29} physReg:NA Preferences=[allInt] Interval 55: RefPositions {#13@30 #14@31} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19C60] Interval 56: RefPositions {#17@42 #19@43} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#21@44 #23@45} physReg:NA Preferences=[rcx] Interval 58: RefPositions {#46@92 #47@93} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A4F8] Interval 59: RefPositions {#50@100 #51@101} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A550] Interval 60: RefPositions {#55@110 #56@111} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19CB8] Interval 61: (constant) RefPositions {#60@128 #61@129} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 62: RefPositions {#65@140 #66@141} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D10] Interval 63: RefPositions {#72@166 #73@167} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A9C8] Interval 64: RefPositions {#79@186 #80@187} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA20] Interval 65: RefPositions {#86@206 #88@207} physReg:NA Preferences=[rcx] Interval 66: RefPositions {#90@208 #97@213} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#91@210 #93@211} physReg:NA Preferences=[rdx] Interval 68: RefPositions {#95@212 #99@213} physReg:NA Preferences=[rdx] Interval 69: RefPositions {#108@214 #109@217} physReg:NA Preferences=[rax] Interval 70: RefPositions {#110@218 #111@219} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19D68] Interval 71: (constant) RefPositions {#119@256 #120@257} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A970] Interval 72: (constant) RefPositions {#123@266 #124@269} physReg:NA Preferences=[allInt] Interval 73: RefPositions {#125@270 #126@271} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19E70] Interval 74: RefPositions {#129@282 #131@283} physReg:NA Preferences=[rcx] Interval 75: RefPositions {#133@284 #135@285} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#152@320 #153@321} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A658] Interval 77: RefPositions {#156@328 #157@329} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A6B0] Interval 78: RefPositions {#161@338 #162@339} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19EC8] Interval 79: (constant) RefPositions {#166@356 #167@357} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 80: RefPositions {#171@368 #172@369} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F20] Interval 81: RefPositions {#178@394 #179@395} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AA78] Interval 82: RefPositions {#185@414 #186@415} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AAD0] Interval 83: RefPositions {#192@434 #194@435} physReg:NA Preferences=[rcx] Interval 84: RefPositions {#196@436 #203@441} physReg:NA Preferences=[rcx] Interval 85: RefPositions {#197@438 #199@439} physReg:NA Preferences=[rdx] Interval 86: RefPositions {#201@440 #205@441} physReg:NA Preferences=[rdx] Interval 87: RefPositions {#214@442 #215@445} physReg:NA Preferences=[rax] Interval 88: RefPositions {#216@446 #217@447} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19F78] Interval 89: (INTERNAL) RefPositions {#225@489 #227@489} physReg:NA Preferences=[mm0-mm5] Interval 90: (specialPutArg) RefPositions {#231@494 #238@499} physReg:NA Preferences=[rcx] RelatedInterval [000001C31DA19AA8] Interval 91: RefPositions {#232@496 #234@497} physReg:NA Preferences=[rdx] Interval 92: RefPositions {#236@498 #240@499} physReg:NA Preferences=[rdx] Interval 93: RefPositions {#251@514 #252@515} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A760] Interval 94: RefPositions {#255@522 #256@523} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A7B8] Interval 95: RefPositions {#260@532 #261@533} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19FD0] Interval 96: (constant) RefPositions {#265@550 #266@551} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 97: RefPositions {#270@562 #271@563} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A028] Interval 98: RefPositions {#277@588 #278@589} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB28] Interval 99: RefPositions {#284@608 #285@609} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AB80] Interval 100: RefPositions {#291@628 #293@629} physReg:NA Preferences=[rcx] Interval 101: RefPositions {#295@630 #302@635} physReg:NA Preferences=[rcx] Interval 102: RefPositions {#296@632 #298@633} physReg:NA Preferences=[rdx] Interval 103: RefPositions {#300@634 #304@635} physReg:NA Preferences=[rdx] Interval 104: RefPositions {#313@636 #314@639} physReg:NA Preferences=[rax] Interval 105: RefPositions {#315@640 #316@641} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A080] Interval 106: RefPositions {#329@690 #330@691} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A8C0] Interval 107: RefPositions {#333@698 #334@699} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A918] Interval 108: RefPositions {#338@708 #339@709} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A0D8] Interval 109: (constant) RefPositions {#343@726 #344@727} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 110: RefPositions {#348@738 #349@739} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A130] Interval 111: RefPositions {#355@764 #356@765} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1ABD8] Interval 112: RefPositions {#362@784 #363@785} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1AC30] Interval 113: RefPositions {#369@804 #371@805} physReg:NA Preferences=[rcx] Interval 114: RefPositions {#373@806 #380@811} physReg:NA Preferences=[rcx] Interval 115: RefPositions {#374@808 #376@809} physReg:NA Preferences=[rdx] Interval 116: RefPositions {#378@810 #382@811} physReg:NA Preferences=[rdx] Interval 117: RefPositions {#391@812 #392@815} physReg:NA Preferences=[rax] Interval 118: RefPositions {#393@816 #394@817} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA1A188] Interval 119: (constant) RefPositions {#403@860 #404@861} physReg:NA Preferences=[allInt] RelatedInterval [000001C31DA19B58] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ #45 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #116 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #4 RefTypeDef CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 last> #9 RefTypeDef ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #12 RefTypeDef CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #14 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #19 RefTypeDef GE BB01 regmask=[rcx] minReg=1> #20 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed> #25 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #100 RefTypeKill BB01 regmask=[rax] minReg=1 last> #87 RefTypeKill BB01 regmask=[rcx] minReg=1 last> #92 RefTypeKill BB01 regmask=[rdx] minReg=1 last> #103 RefTypeKill BB01 regmask=[r8] minReg=1 last> #104 RefTypeKill BB01 regmask=[r9] minReg=1 last> #105 RefTypeKill BB01 regmask=[r10] minReg=1 last> #106 RefTypeKill BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #49 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #47 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #51 RefTypeDef IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #56 RefTypeDef NE BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional> #61 RefTypeDef CNS_INT BB05 regmask=[allInt] minReg=1> BB05 regmask=[allInt] minReg=1 last> #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> #85 RefTypeUse LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> #66 RefTypeDef EQ BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> #73 RefTypeDef LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> #248 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #80 RefTypeDef LCL_VAR_ADDR BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1 last> #88 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rcx] minReg=1> #89 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #96 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> #97 RefTypeDef PUTARG_REG BB08 regmask=[rcx] minReg=1 fixed> #93 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rdx] minReg=1> #94 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #98 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> #99 RefTypeDef PUTARG_REG BB08 regmask=[rdx] minReg=1 fixed> #101 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #102 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #107 RefTypeKill BB08 regmask=[rax] minReg=1 last> #130 RefTypeKill BB08 regmask=[rcx] minReg=1 last> #138 RefTypeKill BB08 regmask=[rdx] minReg=1 last> #139 RefTypeKill BB08 regmask=[r8] minReg=1 last> #140 RefTypeKill BB08 regmask=[r9] minReg=1 last> #141 RefTypeKill BB08 regmask=[r10] minReg=1 last> #142 RefTypeKill BB08 regmask=[r11] minReg=1 last> #136 RefTypeFixedReg BB08 regmask=[rax] minReg=1> #109 RefTypeDef CALL BB08 regmask=[rax] minReg=1 fixed> BB08 regmask=[allInt] minReg=1 last regOptional> #111 RefTypeDef EQ BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 last regOptional> #222 RefTypeUse LCL_VAR BB10 regmask=[allInt] minReg=1 last> #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> #120 RefTypeDef CNS_INT BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #124 RefTypeDef CNS_INT BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #126 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #131 RefTypeDef GE BB11 regmask=[rcx] minReg=1> #132 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #134 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #135 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #137 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #206 RefTypeKill BB11 regmask=[rax] minReg=1 last> #193 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #198 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #209 RefTypeKill BB11 regmask=[r8] minReg=1 last> #210 RefTypeKill BB11 regmask=[r9] minReg=1 last> #211 RefTypeKill BB11 regmask=[r10] minReg=1 last> #212 RefTypeKill BB11 regmask=[r11] minReg=1 last> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #153 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #157 RefTypeDef IND BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #162 RefTypeDef NE BB11 regmask=[allInt] minReg=1> BB11 regmask=[allInt] minReg=1 last> #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last regOptional> #167 RefTypeDef CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[allInt] minReg=1 last> #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[allInt] minReg=1> #191 RefTypeUse LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> #172 RefTypeDef EQ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[allInt] minReg=1> #179 RefTypeDef LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> #326 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> #186 RefTypeDef LCL_VAR_ADDR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> #194 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rcx] minReg=1> #195 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB18 regmask=[rcx] minReg=1 fixed> #199 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rdx] minReg=1> #200 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB18 regmask=[rdx] minReg=1 fixed> #207 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #208 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #213 RefTypeKill BB18 regmask=[rax] minReg=1 last> #228 RefTypeKill BB18 regmask=[rcx] minReg=1 last> #233 RefTypeKill BB18 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB18 regmask=[r8] minReg=1 last> #245 RefTypeKill BB18 regmask=[r9] minReg=1 last> #246 RefTypeKill BB18 regmask=[r10] minReg=1 last> #247 RefTypeKill BB18 regmask=[r11] minReg=1 last> #241 RefTypeFixedReg BB18 regmask=[rax] minReg=1> #215 RefTypeDef CALL BB18 regmask=[rax] minReg=1 fixed> BB18 regmask=[allInt] minReg=1 last regOptional> #217 RefTypeDef EQ BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last regOptional> #321 RefTypeUse LCL_VAR BB20 regmask=[allInt] minReg=1 last> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> #227 RefTypeDef STORE_BLK BB21 regmask=[mm0-mm5] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> STORE_BLK BB21 regmask=[mm0-mm5] minReg=1 last> #230 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> #237 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #238 RefTypeDef PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> #234 RefTypeDef LCL_VAR_ADDR BB21 regmask=[rdx] minReg=1> #235 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #239 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> #240 RefTypeDef PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> #242 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> #243 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB21 regmask=[rax] minReg=1 last> #292 RefTypeKill BB21 regmask=[rcx] minReg=1 last> #297 RefTypeKill BB21 regmask=[rdx] minReg=1 last> #308 RefTypeKill BB21 regmask=[r8] minReg=1 last> #309 RefTypeKill BB21 regmask=[r9] minReg=1 last> #310 RefTypeKill BB21 regmask=[r10] minReg=1 last> #311 RefTypeKill BB21 regmask=[r11] minReg=1 last> LCL_VAR BB21 regmask=[allInt] minReg=1 last> #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #254 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #252 RefTypeDef IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #256 RefTypeDef IND BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1 regOptional> #269 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #261 RefTypeDef NE BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> #266 RefTypeDef CNS_INT BB22 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 last> #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> #271 RefTypeDef EQ BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last regOptional> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> #278 RefTypeDef LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> #285 RefTypeDef LCL_VAR_ADDR BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> #293 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rcx] minReg=1> #294 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #301 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> #302 RefTypeDef PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> #298 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rdx] minReg=1> #299 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #303 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> #304 RefTypeDef PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> #306 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #307 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #312 RefTypeKill BB25 regmask=[rax] minReg=1 last> #370 RefTypeKill BB25 regmask=[rcx] minReg=1 last> #375 RefTypeKill BB25 regmask=[rdx] minReg=1 last> #386 RefTypeKill BB25 regmask=[r8] minReg=1 last> #387 RefTypeKill BB25 regmask=[r9] minReg=1 last> #388 RefTypeKill BB25 regmask=[r10] minReg=1 last> #389 RefTypeKill BB25 regmask=[r11] minReg=1 last> #383 RefTypeFixedReg BB25 regmask=[rax] minReg=1> #314 RefTypeDef CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[allInt] minReg=1 last regOptional> #316 RefTypeDef EQ BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> #399 RefTypeUse LCL_VAR BB27 regmask=[allInt] minReg=1 last> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #330 RefTypeDef IND BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> #334 RefTypeDef IND BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> #347 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #339 RefTypeDef NE BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last regOptional> #344 RefTypeDef CNS_INT BB29 regmask=[allInt] minReg=1> BB29 regmask=[allInt] minReg=1 last> #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[allInt] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[allInt] minReg=1 regOptional> #349 RefTypeDef EQ BB30 regmask=[allInt] minReg=1> BB30 regmask=[allInt] minReg=1 last> #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> #356 RefTypeDef LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> #363 RefTypeDef LCL_VAR_ADDR BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> #371 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rcx] minReg=1> #372 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #379 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> #380 RefTypeDef PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> #376 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> #377 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #381 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> #382 RefTypeDef PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> #384 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #385 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #390 RefTypeKill BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> #407 RefTypeFixedReg BB32 regmask=[rax] minReg=1> #392 RefTypeDef CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[allInt] minReg=1 last regOptional> #394 RefTypeDef EQ BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last regOptional> #402 RefTypeUse LCL_VAR BB34 regmask=[allInt] minReg=1 last> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB35 regmask=[allInt] minReg=1 last> #404 RefTypeDef CNS_INT BB35 regmask=[allInt] minReg=1> BB35 regmask=[allInt] minReg=1 last> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB36 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 #45 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #49 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 fixed> #254 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> --- V01 #116 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #222 RefTypeUse LCL_VAR BB10 regmask=[allInt] minReg=1 last> #321 RefTypeUse LCL_VAR BB20 regmask=[allInt] minReg=1 last> #399 RefTypeUse LCL_VAR BB27 regmask=[allInt] minReg=1 last> #402 RefTypeUse LCL_VAR BB34 regmask=[allInt] minReg=1 last> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V02 --- V03 --- V04 --- V05 #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> --- V06 --- V07 --- V08 --- V09 --- V10 #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V11 --- V12 --- V13 --- V14 #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V15 --- V16 --- V17 --- V18 --- V19 #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last regOptional> --- V20 #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> --- V21 #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[allInt] minReg=1> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 last regOptional> --- V22 --- V23 --- V24 --- V25 --- V26 --- V27 --- V28 --- V29 --- V30 #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB11 regmask=[allInt] minReg=1 last> --- V31 --- V32 --- V33 --- V34 --- V35 #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last regOptional> --- V36 #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> --- V37 #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[allInt] minReg=1> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[allInt] minReg=1> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 last regOptional> --- V38 --- V39 --- V40 --- V41 --- V42 --- V43 --- V44 #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last regOptional> --- V45 #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 last regOptional> --- V46 #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> --- V47 --- V48 --- V49 --- V50 --- V51 --- V52 --- V53 #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last regOptional> --- V54 #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[allInt] minReg=1> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> --- V55 #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[allInt] minReg=1> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[allInt] minReg=1> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last regOptional> --- V56 --- V57 --- V58 --- V59 --- V60 --- V61 #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V62 #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #248 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[allInt] minReg=1 last> --- V63 #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> --- V64 #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1> #326 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB28 regmask=[allInt] minReg=1 last> --- V65 #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V66 #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V67 #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V68 #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V69 --- V70 --- V71 #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V72 --- V73 --- V74 #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> --- V75 #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> #85 RefTypeUse LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB08 regmask=[allInt] minReg=1 last> --- V76 --- V77 #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> --- V78 --- V79 #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> --- V80 --- V81 --- V82 --- V83 --- V84 --- V85 #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V86 #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[allInt] minReg=1 regOptional> #191 RefTypeUse LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V87 --- V88 #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V89 #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V90 #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> #269 RefTypeUse LCL_VAR BB21 regmask=[allInt] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V91 #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V92 #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V93 #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V94 #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> #347 RefTypeUse LCL_VAR BB28 regmask=[allInt] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V95 --- V96 #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[allInt] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[allInt] minReg=1 last> --- V97 --- V98 #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> --- V99 --- V100 #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 last> --- V101 #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V102 #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V103 --- V104 #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V105 #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[allInt] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V106 #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V107 #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 last> --- V108 Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ---------------------------------+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi | ---------------------------------+-----+-----+-----+-----+-----+-----+ | |V0 a| | | | | 0.#0 V0 Parm Alloc rsi | | | | |V0 a| | 0.#1 V1 Parm Alloc rdi | | | | |V0 a|V1 a| 1.#2 BB1 PredBB0 | | | | |V0 a|V1 a| 8.#3 C52 Def Alloc rbx | | |C52 a| |V0 a|V1 a| 9.#4 C52 Use * Keep rbx | | |C52 a| |V0 a|V1 a| 10.#5 V96 Def Alloc rbx | | |V96 a| |V0 a|V1 a| 13.#6 V96 Use Keep rbx | | |V96 a| |V0 a|V1 a| 19.#7 V96 Use * Keep rbx | | |V96 i| |V0 a|V1 a| 20.#8 I53 Def Alloc rbx | | |I53 a| |V0 a|V1 a| 21.#9 I53 Use * Keep rbx | | |I53 a| |V0 a|V1 a| Restr rbx | | |V96 i| |V0 a|V1 a| 22.#10 V10 Def Alloc rbx | | |V10 a| |V0 a|V1 a| 26.#11 C54 Def Alloc rcx | |C54 a|V10 a| |V0 a|V1 a| 29.#12 C54 Use * Keep rcx | |C54 a|V10 a| |V0 a|V1 a| 30.#13 I55 Def Alloc rbp | |C54 i|V10 a|I55 a|V0 a|V1 a| 31.#14 I55 Use * Keep rbp | |C54 i|V10 a|I55 a|V0 a|V1 a| 32.#15 V14 Def Alloc rbp | |C54 i|V10 a|V14 a|V0 a|V1 a| 41.#16 V14 Use Keep rbp | |C54 i|V10 a|V14 a|V0 a|V1 a| 42.#17 I56 Def Alloc rcx | |I56 a|V10 a|V14 a|V0 a|V1 a| 43.#18 rcx Fixd Keep rcx | |I56 a|V10 a|V14 a|V0 a|V1 a| 43.#19 I56 Use * Keep rcx | |I56 a|V10 a|V14 a|V0 a|V1 a| 44.#20 rcx Fixd Keep rcx | | |V10 a|V14 a|V0 a|V1 a| 44.#21 I57 Def Alloc rcx | |I57 a|V10 a|V14 a|V0 a|V1 a| 45.#22 rcx Fixd Keep rcx | |I57 a|V10 a|V14 a|V0 a|V1 a| 45.#23 I57 Use * Keep rcx | |I57 a|V10 a|V14 a|V0 a|V1 a| 46.#24 rax Kill Keep rax | | |V10 a|V14 a|V0 a|V1 a| 46.#25 rcx Kill Keep rcx | | |V10 a|V14 a|V0 a|V1 a| 46.#26 rdx Kill Keep rdx | | |V10 a|V14 a|V0 a|V1 a| 46.#27 r8 Kill Keep r8 | | |V10 a|V14 a|V0 a|V1 a| 46.#28 r9 Kill Keep r9 | | |V10 a|V14 a|V0 a|V1 a| 46.#29 r10 Kill Keep r10 | | |V10 a|V14 a|V0 a|V1 a| 46.#30 r11 Kill Keep r11 | | |V10 a|V14 a|V0 a|V1 a| 51.#31 V10 Use * Keep rbx | | |V10 a|V14 a|V0 a|V1 a| Restr rbx | | |V96 i|V14 a|V0 a|V1 a| 52.#32 V71 Def Alloc rbx | | |V71 a|V14 a|V0 a|V1 a| 57.#33 V71 Use * Keep rbx | | |V71 a|V14 a|V0 a|V1 a| Restr rbx | | |V96 i|V14 a|V0 a|V1 a| 58.#34 V65 Def Alloc rbx | | |V65 a|V14 a|V0 a|V1 a| 63.#35 V14 Use * Keep rbp | | |V65 a|V14 a|V0 a|V1 a| 64.#36 V66 Def Alloc rbp | | |V65 a|V66 a|V0 a|V1 a| 69.#37 V65 Use * Keep rbx | | |V65 a|V66 a|V0 a|V1 a| 70.#38 V67 Def Alloc rbx | | |V67 a|V66 a|V0 a|V1 a| 73.#39 V66 Use * Keep rbp | | |V67 a|V66 a|V0 a|V1 a| 74.#40 V68 Def Alloc rbp | | |V67 a|V68 a|V0 a|V1 a| 77.#41 V67 Use * Keep rbx | | |V67 a|V68 a|V0 a|V1 a| 78.#42 V61 Def Alloc rbx | | |V61 a|V68 a|V0 a|V1 a| 81.#43 V68 Use * Keep rbp | | |V61 a|V68 a|V0 a|V1 a| 82.#44 V62 Def Alloc rbp | | |V61 a|V62 a|V0 a|V1 a| 91.#45 V0 Use Keep rsi | | |V61 a|V62 a|V0 a|V1 a| 92.#46 I58 Def Alloc rcx | |I58 a|V61 a|V62 a|V0 a|V1 a| ---------------------------------+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi | ---------------------------------+-----+-----+-----+-----+-----+-----+ 93.#47 I58 Use * Keep rcx | |I58 a|V61 a|V62 a|V0 a|V1 a| 94.#48 V74 Def Alloc rcx | |V74 a|V61 a|V62 a|V0 a|V1 a| 99.#49 V0 Use Keep rsi | |V74 a|V61 a|V62 a|V0 a|V1 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+ 100.#50 I59 Def Alloc rdx | |V74 a|I59 a|V61 a|V62 a|V0 a|V1 a| 101.#51 I59 Use * Keep rdx | |V74 a|I59 a|V61 a|V62 a|V0 a|V1 a| 102.#52 V75 Def Alloc rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 109.#53 V62 Use Keep rbp | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 109.#54 V75 Use Keep rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 110.#55 I60 Def Alloc rax |I60 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 111.#56 I60 Use * Keep rax |I60 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 112.#57 V19 Def Alloc rax |V19 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| 119.#58 V19 Use * Keep rax |V19 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+ 123.#59 BB5 PredBB1 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 128.#60 C61 Def Alloc r14 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a|C61 a| 129.#61 C61 Use * Keep r14 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a|C61 a| 130.#62 V21 Def Alloc r14 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a|V21 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 131.#63 BB6 PredBB1 | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 139.#64 V75 Use Keep rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 140.#65 I62 Def Alloc rax |I62 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 141.#66 I62 Use * Keep rax |I62 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 142.#67 V20 Def Alloc rax |V20 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 149.#68 V20 Use * Keep rax |V20 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 153.#69 BB7 PredBB6 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a|V21 i| 160.#70 V21 Def Keep r14 | |V74 i|V75 i|V61 a|V62 a|V0 a|V1 a|V21 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 161.#71 BB8 PredBB6 | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 166.#72 I63 Def Alloc rax |I63 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 167.#73 I63 Use * Keep rax |I63 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 168.#74 V98 Def Alloc rax |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 175.#75 V98 Use Keep rax |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 175.#76 V61 Use Keep rbx |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 183.#77 V98 Use * Keep rax |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 183.#78 V62 Use Keep rbp |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 186.#79 I64 Def Alloc rax |I64 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 187.#80 I64 Use * Keep rax |I64 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 188.#81 V100 Def Alloc rax |V100a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 195.#82 V100 Use Keep rax |V100a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 195.#83 V74 Use * Keep rcx |V100a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 203.#84 V100 Use * Keep rax |V100a| |V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 203.#85 V75 Use * Keep rdx |V100a| |V75 a|V61 a|V62 a|V0 a|V1 a|V21 i| 206.#86 I65 Def Alloc rcx | |I65 a| |V61 a|V62 a|V0 a|V1 a|V21 i| 207.#87 rcx Fixd Keep rcx | |I65 a| |V61 a|V62 a|V0 a|V1 a|V21 i| 207.#88 I65 Use * Keep rcx | |I65 a| |V61 a|V62 a|V0 a|V1 a|V21 i| 208.#89 rcx Fixd Keep rcx | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 208.#90 I66 Def Alloc rcx | |I66 a| |V61 a|V62 a|V0 a|V1 a|V21 i| 210.#91 I67 Def Alloc rdx | |I66 a|I67 a|V61 a|V62 a|V0 a|V1 a|V21 i| 211.#92 rdx Fixd Keep rdx | |I66 a|I67 a|V61 a|V62 a|V0 a|V1 a|V21 i| 211.#93 I67 Use * Keep rdx | |I66 a|I67 a|V61 a|V62 a|V0 a|V1 a|V21 i| 212.#94 rdx Fixd Keep rdx | |I66 a| |V61 a|V62 a|V0 a|V1 a|V21 i| 212.#95 I68 Def Alloc rdx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a|V21 i| 213.#96 rcx Fixd Keep rcx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a|V21 i| 213.#97 I66 Use * Keep rcx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a|V21 i| 213.#98 rdx Fixd Keep rdx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a|V21 i| 213.#99 I68 Use * Keep rdx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a|V21 i| 214.#100 rax Kill Keep rax | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#101 rcx Kill Keep rcx | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#102 rdx Kill Keep rdx | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#103 r8 Kill Keep r8 | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#104 r9 Kill Keep r9 | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#105 r10 Kill Keep r10 | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#106 r11 Kill Keep r11 | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#107 rax Fixd Keep rax | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 214.#108 I69 Def Alloc rax |I69 a| | |V61 a|V62 a|V0 a|V1 a|V21 i| 217.#109 I69 Use * Keep rax |I69 a| | |V61 a|V62 a|V0 a|V1 a|V21 i| 218.#110 I70 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a|I70 a| 219.#111 I70 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a|I70 a| Restr r14 | | | |V61 a|V62 a|V0 a|V1 a|V21 i| 220.#112 V21 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a|V21 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 221.#113 BB9 PredBB5 | | | |V61 a|V62 a|V0 a|V1 a|V21 a| 229.#114 V21 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a|V21 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 233.#115 BB10 PredBB9 | | | |V61 i|V62 i|V0 i|V1 a| | 241.#116 V1 Use * Keep rdi | | | |V61 i|V62 i|V0 i|V1 i| | 248.#117 V5 Def Alloc rax |V5 a| | |V61 i|V62 i|V0 i|V1 i| | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+ 249.#118 BB11 PredBB9 |V5 i| | |V61 a|V62 a|V0 a|V1 a| | 256.#119 C71 Def Alloc rcx |V5 i|C71 a| |V61 a|V62 a|V0 a|V1 a| | 257.#120 C71 Use * Keep rcx |V5 i|C71 a| |V61 a|V62 a|V0 a|V1 a| | 258.#121 V96 Def Alloc rcx |V5 i|V96 a| |V61 a|V62 a|V0 a|V1 a| | 261.#122 V96 Use * Keep rcx |V5 i|V96 a| |V61 a|V62 a|V0 a|V1 a| | 266.#123 C72 Def Alloc rcx |V5 i|C72 a| |V61 a|V62 a|V0 a|V1 a| | 269.#124 C72 Use * Keep rcx |V5 i|C72 a| |V61 a|V62 a|V0 a|V1 a| | 270.#125 I73 Def Alloc r14 |V5 i|C72 i| |V61 a|V62 a|V0 a|V1 a|I73 a| 271.#126 I73 Use * Keep r14 |V5 i|C72 i| |V61 a|V62 a|V0 a|V1 a|I73 a| 272.#127 V30 Def Alloc r14 |V5 i|C72 i| |V61 a|V62 a|V0 a|V1 a|V30 a| 281.#128 V30 Use Keep r14 |V5 i|C72 i| |V61 a|V62 a|V0 a|V1 a|V30 a| 282.#129 I74 Def Alloc rcx |V5 i|I74 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 283.#130 rcx Fixd Keep rcx |V5 i|I74 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 283.#131 I74 Use * Keep rcx |V5 i|I74 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 284.#132 rcx Fixd Keep rcx |V5 i| | |V61 a|V62 a|V0 a|V1 a|V30 a| 284.#133 I75 Def Alloc rcx |V5 i|I75 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 285.#134 rcx Fixd Keep rcx |V5 i|I75 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 285.#135 I75 Use * Keep rcx |V5 i|I75 a| |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#136 rax Kill Keep rax | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#137 rcx Kill Keep rcx | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#138 rdx Kill Keep rdx | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#139 r8 Kill Keep r8 | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#140 r9 Kill Keep r9 | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#141 r10 Kill Keep r10 | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 286.#142 r11 Kill Keep r11 | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 295.#143 V30 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a|V30 a| 296.#144 V77 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a|V77 a| 301.#145 V77 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a|V77 a| 302.#146 V79 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a|V79 a| 305.#147 V61 Use Keep rbx | | | |V61 a|V62 a|V0 a|V1 a|V79 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 306.#148 V63 Def Alloc r15 | | | |V61 a|V62 a|V0 a|V1 a|V79 a|V63 a| 309.#149 V79 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a|V79 a|V63 a| 310.#150 V64 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 319.#151 V0 Use Keep rsi | | | |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 320.#152 I76 Def Alloc rcx | |I76 a| |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 321.#153 I76 Use * Keep rcx | |I76 a| |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 322.#154 V85 Def Alloc rcx | |V85 a| |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 327.#155 V0 Use Keep rsi | |V85 a| |V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 328.#156 I77 Def Alloc rdx | |V85 a|I77 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 329.#157 I77 Use * Keep rdx | |V85 a|I77 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 330.#158 V86 Def Alloc rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 337.#159 V64 Use Keep r14 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 337.#160 V86 Use Keep rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 338.#161 I78 Def Alloc rax |I78 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 339.#162 I78 Use * Keep rax |I78 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 340.#163 V35 Def Alloc rax |V35 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| 347.#164 V35 Use * Keep rax |V35 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 351.#165 BB15 PredBB11 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 356.#166 C79 Def Alloc r12 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|C79 a|V64 a|V63 a| 357.#167 C79 Use * Keep r12 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|C79 a|V64 a|V63 a| 358.#168 V37 Def Alloc r12 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 359.#169 BB16 PredBB11 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 367.#170 V86 Use Keep rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 368.#171 I80 Def Alloc rax |I80 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 369.#172 I80 Use * Keep rax |I80 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 370.#173 V36 Def Alloc rax |V36 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 377.#174 V36 Use * Keep rax |V36 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 381.#175 BB17 PredBB16 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 388.#176 V37 Def Keep r12 | |V85 i|V86 i|V61 i|V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#177 BB18 PredBB16 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 394.#178 I81 Def Alloc rax |I81 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 395.#179 I81 Use * Keep rax |I81 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 396.#180 V101 Def Alloc rax |V101a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 403.#181 V101 Use Keep rax |V101a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 403.#182 V61 Use * Keep rbx |V101a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 411.#183 V101 Use * Keep rax |V101a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 411.#184 V64 Use Keep r14 |V101a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 414.#185 I82 Def Alloc rax |I82 a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 415.#186 I82 Use * Keep rax |I82 a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 416.#187 V102 Def Alloc rax |V102a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 423.#188 V102 Use Keep rax |V102a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 423.#189 V85 Use * Keep rcx |V102a|V85 a|V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 431.#190 V102 Use * Keep rax |V102a| |V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 431.#191 V86 Use * Keep rdx |V102a| |V86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 434.#192 I83 Def Alloc rcx | |I83 a| | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 435.#193 rcx Fixd Keep rcx | |I83 a| | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 435.#194 I83 Use * Keep rcx | |I83 a| | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 436.#195 rcx Fixd Keep rcx | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 436.#196 I84 Def Alloc rcx | |I84 a| | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 438.#197 I85 Def Alloc rdx | |I84 a|I85 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 439.#198 rdx Fixd Keep rdx | |I84 a|I85 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 439.#199 I85 Use * Keep rdx | |I84 a|I85 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 440.#200 rdx Fixd Keep rdx | |I84 a| | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 440.#201 I86 Def Alloc rdx | |I84 a|I86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 441.#202 rcx Fixd Keep rcx | |I84 a|I86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 441.#203 I84 Use * Keep rcx | |I84 a|I86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 441.#204 rdx Fixd Keep rdx | |I84 a|I86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 441.#205 I86 Use * Keep rdx | |I84 a|I86 a| |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#206 rax Kill Keep rax | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#207 rcx Kill Keep rcx | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#208 rdx Kill Keep rdx | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#209 r8 Kill Keep r8 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#210 r9 Kill Keep r9 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#211 r10 Kill Keep r10 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#212 r11 Kill Keep r11 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#213 rax Fixd Keep rax | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 442.#214 I87 Def Alloc rax |I87 a| | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 445.#215 I87 Use * Keep rax |I87 a| | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 446.#216 I88 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|I88 a|V64 a|V63 a| 447.#217 I88 Use * Keep r12 | | | | |V62 a|V0 a|V1 a|I88 a|V64 a|V63 a| Restr r12 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| 448.#218 V37 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 449.#219 BB19 PredBB15 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| 457.#220 V37 Use * Keep r12 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 461.#221 BB20 PredBB19 | | | | |V62 i|V0 i|V1 a| |V64 i|V63 i| 469.#222 V1 Use * Keep rdi | | | | |V62 i|V0 i|V1 i| |V64 i|V63 i| 476.#223 V5 Def Alloc rax |V5 a| | | |V62 i|V0 i|V1 i| |V64 i|V63 i| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 477.#224 BB21 PredBB19 |V5 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#225 I89 Def Alloc mm0 |V5 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#226 V0 Use Keep rsi |V5 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#227 I89 Use * Keep mm0 |V5 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 493.#228 rcx Fixd Keep rcx |V5 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 493.#229 V0 Use Copy rcx |V5 i|V0 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 494.#230 rcx Fixd Keep rcx |V5 i|V0 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 494.#231 I90 Def Alloc rcx |V5 i|I90 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 496.#232 I91 Def Alloc rdx |V5 i|I90 a|I91 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 497.#233 rdx Fixd Keep rdx |V5 i|I90 a|I91 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 497.#234 I91 Use * Keep rdx |V5 i|I90 a|I91 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 498.#235 rdx Fixd Keep rdx |V5 i|I90 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 498.#236 I92 Def Alloc rdx |V5 i|I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#237 rcx Fixd Keep rcx |V5 i|I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#238 I90 Use * Keep rcx |V5 i|I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#239 rdx Fixd Keep rdx |V5 i|I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#240 I92 Use * Keep rdx |V5 i|I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#241 rax Kill Keep rax | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#242 rcx Kill Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#243 rdx Kill Keep rdx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#244 r8 Kill Keep r8 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#245 r9 Kill Keep r9 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#246 r10 Kill Keep r10 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#247 r11 Kill Keep r11 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 505.#248 V62 Use * Keep rbp | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 506.#249 V88 Def Alloc rbp | | | | |V88 a|V0 a|V1 a| |V64 a|V63 a| 513.#250 V0 Use Keep rsi | | | | |V88 a|V0 a|V1 a| |V64 a|V63 a| 514.#251 I93 Def Alloc rcx | |I93 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 515.#252 I93 Use * Keep rcx | |I93 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 516.#253 V89 Def Alloc rcx | |V89 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 521.#254 V0 Use Keep rsi | |V89 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 522.#255 I94 Def Alloc rdx | |V89 a|I94 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 523.#256 I94 Use * Keep rdx | |V89 a|I94 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 524.#257 V90 Def Alloc rdx | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 531.#258 V88 Use Keep rbp | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 531.#259 V90 Use Keep rdx | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 532.#260 I95 Def Alloc rax |I95 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 533.#261 I95 Use * Keep rax |I95 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 534.#262 V44 Def Alloc rax |V44 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 541.#263 V44 Use * Keep rax |V44 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 545.#264 BB22 PredBB21 | |V89 i|V90 i| |V88 i|V0 a|V1 a| |V64 a|V63 a| 550.#265 C96 Def Alloc rbx | |V89 i|V90 i|C96 a|V88 i|V0 a|V1 a| |V64 a|V63 a| 551.#266 C96 Use * Keep rbx | |V89 i|V90 i|C96 a|V88 i|V0 a|V1 a| |V64 a|V63 a| 552.#267 V46 Def Alloc rbx | |V89 i|V90 i|V46 a|V88 i|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 553.#268 BB23 PredBB21 | |V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 561.#269 V90 Use Keep rdx | |V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 562.#270 I97 Def Alloc rax |I97 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 563.#271 I97 Use * Keep rax |I97 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 564.#272 V45 Def Alloc rax |V45 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 571.#273 V45 Use * Keep rax |V45 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 575.#274 BB24 PredBB23 | |V89 i|V90 i|V46 i|V88 i|V0 a|V1 a| |V64 a|V63 a| 582.#275 V46 Def Keep rbx | |V89 i|V90 i|V46 a|V88 i|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 583.#276 BB25 PredBB23 | |V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 588.#277 I98 Def Alloc rax |I98 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 589.#278 I98 Use * Keep rax |I98 a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 590.#279 V104 Def Alloc rax |V104a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 597.#280 V104 Use Keep rax |V104a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 597.#281 V63 Use Keep r15 |V104a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 605.#282 V104 Use * Keep rax |V104a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 605.#283 V88 Use * Keep rbp |V104a|V89 a|V90 a|V46 i|V88 a|V0 a|V1 a| |V64 a|V63 a| 608.#284 I99 Def Alloc rax |I99 a|V89 a|V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 609.#285 I99 Use * Keep rax |I99 a|V89 a|V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 610.#286 V105 Def Alloc rax |V105a|V89 a|V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 617.#287 V105 Use Keep rax |V105a|V89 a|V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 617.#288 V89 Use * Keep rcx |V105a|V89 a|V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 625.#289 V105 Use * Keep rax |V105a| |V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 625.#290 V90 Use * Keep rdx |V105a| |V90 a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 628.#291 I100 Def Alloc rcx | |I100a| |V46 i| |V0 a|V1 a| |V64 a|V63 a| 629.#292 rcx Fixd Keep rcx | |I100a| |V46 i| |V0 a|V1 a| |V64 a|V63 a| 629.#293 I100 Use * Keep rcx | |I100a| |V46 i| |V0 a|V1 a| |V64 a|V63 a| 630.#294 rcx Fixd Keep rcx | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 630.#295 I101 Def Alloc rcx | |I101a| |V46 i| |V0 a|V1 a| |V64 a|V63 a| 632.#296 I102 Def Alloc rdx | |I101a|I102a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 633.#297 rdx Fixd Keep rdx | |I101a|I102a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 633.#298 I102 Use * Keep rdx | |I101a|I102a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 634.#299 rdx Fixd Keep rdx | |I101a| |V46 i| |V0 a|V1 a| |V64 a|V63 a| 634.#300 I103 Def Alloc rdx | |I101a|I103a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 635.#301 rcx Fixd Keep rcx | |I101a|I103a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 635.#302 I101 Use * Keep rcx | |I101a|I103a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 635.#303 rdx Fixd Keep rdx | |I101a|I103a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 635.#304 I103 Use * Keep rdx | |I101a|I103a|V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#305 rax Kill Keep rax | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#306 rcx Kill Keep rcx | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#307 rdx Kill Keep rdx | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#308 r8 Kill Keep r8 | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#309 r9 Kill Keep r9 | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#310 r10 Kill Keep r10 | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#311 r11 Kill Keep r11 | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#312 rax Fixd Keep rax | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 636.#313 I104 Def Alloc rax |I104a| | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 639.#314 I104 Use * Keep rax |I104a| | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 640.#315 I105 Def Alloc rbx | | | |I105a| |V0 a|V1 a| |V64 a|V63 a| 641.#316 I105 Use * Keep rbx | | | |I105a| |V0 a|V1 a| |V64 a|V63 a| Restr rbx | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| 642.#317 V46 Def Alloc rbx | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 643.#318 BB26 PredBB22 | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| 651.#319 V46 Use * Keep rbx | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 655.#320 BB27 PredBB26 | | | | | |V0 i|V1 a| |V64 i|V63 i| 663.#321 V1 Use * Keep rdi | | | | | |V0 i|V1 i| |V64 i|V63 i| 670.#322 V5 Def Alloc rax |V5 a| | | | |V0 i|V1 i| |V64 i|V63 i| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 671.#323 BB28 PredBB26 |V5 i| | | | |V0 a|V1 a| |V64 a|V63 a| 677.#324 V63 Use * Keep r15 |V5 i| | | | |V0 a|V1 a| |V64 a|V63 a| 678.#325 V91 Def Alloc r15 |V5 i| | | | |V0 a|V1 a| |V64 a|V91 a| 681.#326 V64 Use * Keep r14 |V5 i| | | | |V0 a|V1 a| |V64 a|V91 a| 682.#327 V92 Def Alloc r14 |V5 i| | | | |V0 a|V1 a| |V92 a|V91 a| 689.#328 V0 Use Keep rsi |V5 i| | | | |V0 a|V1 a| |V92 a|V91 a| 690.#329 I106 Def Alloc rcx |V5 i|I106a| | | |V0 a|V1 a| |V92 a|V91 a| 691.#330 I106 Use * Keep rcx |V5 i|I106a| | | |V0 a|V1 a| |V92 a|V91 a| 692.#331 V93 Def Alloc rcx |V5 i|V93 a| | | |V0 a|V1 a| |V92 a|V91 a| 697.#332 V0 Use * Keep rsi |V5 i|V93 a| | | |V0 a|V1 a| |V92 a|V91 a| 698.#333 I107 Def Alloc rdx |V5 i|V93 a|I107a| | | |V1 a| |V92 a|V91 a| 699.#334 I107 Use * Keep rdx |V5 i|V93 a|I107a| | | |V1 a| |V92 a|V91 a| 700.#335 V94 Def Alloc rdx |V5 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 707.#336 V92 Use Keep r14 |V5 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 707.#337 V94 Use Keep rdx |V5 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 708.#338 I108 Def Alloc rax |I108a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 709.#339 I108 Use * Keep rax |I108a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| Restr rax |V5 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 710.#340 V53 Def Alloc rax |V53 a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 717.#341 V53 Use * Keep rax |V53 a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| Restr rax |V5 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 721.#342 BB29 PredBB28 |V5 i|V93 i|V94 i| | | |V1 a| |V92 i|V91 i| 726.#343 C109 Def Alloc rsi |V5 i|V93 i|V94 i| | |C109a|V1 a| |V92 i|V91 i| 727.#344 C109 Use * Keep rsi |V5 i|V93 i|V94 i| | |C109a|V1 a| |V92 i|V91 i| 728.#345 V55 Def Alloc rsi |V5 i|V93 i|V94 i| | |V55 a|V1 a| |V92 i|V91 i| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 729.#346 BB30 PredBB28 |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 737.#347 V94 Use Keep rdx |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 738.#348 I110 Def Alloc rax |I110a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 739.#349 I110 Use * Keep rax |I110a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| Restr rax |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 740.#350 V54 Def Alloc rax |V54 a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 747.#351 V54 Use * Keep rax |V54 a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| Restr rax |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 751.#352 BB31 PredBB30 |V5 i|V93 i|V94 i| | |V55 i|V1 a| |V92 i|V91 i| 758.#353 V55 Def Keep rsi |V5 i|V93 i|V94 i| | |V55 a|V1 a| |V92 i|V91 i| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 759.#354 BB32 PredBB30 |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 764.#355 I111 Def Alloc rax |I111a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 765.#356 I111 Use * Keep rax |I111a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| Restr rax |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 766.#357 V106 Def Alloc rax |V106a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 773.#358 V106 Use Keep rax |V106a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 773.#359 V91 Use * Keep r15 |V106a|V93 a|V94 a| | |V55 i|V1 a| |V92 a|V91 a| 781.#360 V106 Use * Keep rax |V106a|V93 a|V94 a| | |V55 i|V1 a| |V92 a| | 781.#361 V92 Use * Keep r14 |V106a|V93 a|V94 a| | |V55 i|V1 a| |V92 a| | Restr rax |V5 i|V93 a|V94 a| | |V55 i|V1 a| |V92 a| | 784.#362 I112 Def Alloc rax |I112a|V93 a|V94 a| | |V55 i|V1 a| | | | 785.#363 I112 Use * Keep rax |I112a|V93 a|V94 a| | |V55 i|V1 a| | | | Restr rax |V5 i|V93 a|V94 a| | |V55 i|V1 a| | | | 786.#364 V107 Def Alloc rax |V107a|V93 a|V94 a| | |V55 i|V1 a| | | | 793.#365 V107 Use Keep rax |V107a|V93 a|V94 a| | |V55 i|V1 a| | | | 793.#366 V93 Use * Keep rcx |V107a|V93 a|V94 a| | |V55 i|V1 a| | | | 801.#367 V107 Use * Keep rax |V107a| |V94 a| | |V55 i|V1 a| | | | 801.#368 V94 Use * Keep rdx |V107a| |V94 a| | |V55 i|V1 a| | | | Restr rax |V5 i| |V94 a| | |V55 i|V1 a| | | | 804.#369 I113 Def Alloc rcx |V5 i|I113a| | | |V55 i|V1 a| | | | 805.#370 rcx Fixd Keep rcx |V5 i|I113a| | | |V55 i|V1 a| | | | 805.#371 I113 Use * Keep rcx |V5 i|I113a| | | |V55 i|V1 a| | | | 806.#372 rcx Fixd Keep rcx |V5 i| | | | |V55 i|V1 a| | | | 806.#373 I114 Def Alloc rcx |V5 i|I114a| | | |V55 i|V1 a| | | | 808.#374 I115 Def Alloc rdx |V5 i|I114a|I115a| | |V55 i|V1 a| | | | 809.#375 rdx Fixd Keep rdx |V5 i|I114a|I115a| | |V55 i|V1 a| | | | 809.#376 I115 Use * Keep rdx |V5 i|I114a|I115a| | |V55 i|V1 a| | | | 810.#377 rdx Fixd Keep rdx |V5 i|I114a| | | |V55 i|V1 a| | | | 810.#378 I116 Def Alloc rdx |V5 i|I114a|I116a| | |V55 i|V1 a| | | | 811.#379 rcx Fixd Keep rcx |V5 i|I114a|I116a| | |V55 i|V1 a| | | | 811.#380 I114 Use * Keep rcx |V5 i|I114a|I116a| | |V55 i|V1 a| | | | 811.#381 rdx Fixd Keep rdx |V5 i|I114a|I116a| | |V55 i|V1 a| | | | 811.#382 I116 Use * Keep rdx |V5 i|I114a|I116a| | |V55 i|V1 a| | | | 812.#383 rax Kill Keep rax | | | | | |V55 i|V1 a| | | | 812.#384 rcx Kill Keep rcx | | | | | |V55 i|V1 a| | | | 812.#385 rdx Kill Keep rdx | | | | | |V55 i|V1 a| | | | 812.#386 r8 Kill Keep r8 | | | | | |V55 i|V1 a| | | | 812.#387 r9 Kill Keep r9 | | | | | |V55 i|V1 a| | | | 812.#388 r10 Kill Keep r10 | | | | | |V55 i|V1 a| | | | 812.#389 r11 Kill Keep r11 | | | | | |V55 i|V1 a| | | | 812.#390 rax Fixd Keep rax | | | | | |V55 i|V1 a| | | | 812.#391 I117 Def Alloc rax |I117a| | | | |V55 i|V1 a| | | | 815.#392 I117 Use * Keep rax |I117a| | | | |V55 i|V1 a| | | | 816.#393 I118 Def Alloc rsi | | | | | |I118a|V1 a| | | | 817.#394 I118 Use * Keep rsi | | | | | |I118a|V1 a| | | | Restr rsi | | | | | |V55 i|V1 a| | | | 818.#395 V55 Def Alloc rsi | | | | | |V55 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 819.#396 BB33 PredBB29 | | | | | |V55 a|V1 a| | | | 827.#397 V55 Use * Keep rsi | | | | | |V55 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 831.#398 BB34 PredBB33 | | | | | | |V1 a| | | | 839.#399 V1 Use * Keep rdi | | | | | | |V1 i| | | | 846.#400 V5 Def Alloc rax |V5 a| | | | | |V1 i| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 847.#401 BB35 PredBB33 |V5 i| | | | | |V1 a| | | | 855.#402 V1 Use * Keep rdi |V5 i| | | | | |V1 a| | | | 860.#403 C119 Def Alloc rax |C119a| | | | | | | | | | 861.#404 C119 Use * Keep rax |C119a| | | | | | | | | | 862.#405 V5 Def Restr rax |V5 i| | | | | | | | | | Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 863.#406 BB36 PredBB10 |V5 a| | | | | | | | | | 869.#407 rax Fixd Keep rax |V5 a| | | | | | | | | | 869.#408 V5 Use * Keep rax | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ #45 RefTypeParamDef BB00 regmask=[rsi] minReg=1 fixed> #116 RefTypeParamDef BB00 regmask=[rdi] minReg=1 fixed> #4 RefTypeDef CNS_INT BB01 regmask=[rbx] minReg=1> BB01 regmask=[rbx] minReg=1 last> #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[rbx] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[rbx] minReg=1 last> #9 RefTypeDef ADD BB01 regmask=[rbx] minReg=1> BB01 regmask=[rbx] minReg=1 last> #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #12 RefTypeDef CNS_INT BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last> #14 RefTypeDef IND BB01 regmask=[rbp] minReg=1> BB01 regmask=[rbp] minReg=1 last> #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[rbp] minReg=1 regOptional> #19 RefTypeDef GE BB01 regmask=[rcx] minReg=1> #20 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB01 regmask=[rcx] minReg=1 fixed> #25 RefTypeFixedReg BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last fixed> #100 RefTypeKill BB01 regmask=[rax] minReg=1 last> #87 RefTypeKill BB01 regmask=[rcx] minReg=1 last> #92 RefTypeKill BB01 regmask=[rdx] minReg=1 last> #103 RefTypeKill BB01 regmask=[r8] minReg=1 last> #104 RefTypeKill BB01 regmask=[r9] minReg=1 last> #105 RefTypeKill BB01 regmask=[r10] minReg=1 last> #106 RefTypeKill BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[rbx] minReg=1 last> #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbp] minReg=1 last> #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbp] minReg=1 last> #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbp] minReg=1 last> #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> #49 RefTypeUse LCL_VAR BB01 regmask=[rsi] minReg=1> #47 RefTypeDef IND BB01 regmask=[rcx] minReg=1> BB01 regmask=[rcx] minReg=1 last> #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[rcx] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[rsi] minReg=1> #51 RefTypeDef IND BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last> #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[rdx] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[rbp] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[rdx] minReg=1 regOptional> #56 RefTypeDef NE BB01 regmask=[rax] minReg=1> BB01 regmask=[rax] minReg=1 last> #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional> #61 RefTypeDef CNS_INT BB05 regmask=[r14] minReg=1> BB05 regmask=[r14] minReg=1 last> #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[r14] minReg=1> #85 RefTypeUse LCL_VAR BB06 regmask=[rdx] minReg=1 regOptional> #66 RefTypeDef EQ BB06 regmask=[rax] minReg=1> BB06 regmask=[rax] minReg=1 last> #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[rax] minReg=1> LCL_VAR BB06 regmask=[rax] minReg=1 last regOptional> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[r14] minReg=1> #73 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rax] minReg=1> BB08 regmask=[rax] minReg=1 last> #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[rax] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[rax] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[rbx] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last> #248 RefTypeUse LCL_VAR BB08 regmask=[rbp] minReg=1> #80 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rax] minReg=1> BB08 regmask=[rax] minReg=1 last> #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[rax] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rcx] minReg=1 last> LCL_VAR BB08 regmask=[rax] minReg=1 last> LCL_VAR BB08 regmask=[rdx] minReg=1 last> #88 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rcx] minReg=1> #89 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #96 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> #97 RefTypeDef PUTARG_REG BB08 regmask=[rcx] minReg=1 fixed> #93 RefTypeDef LCL_VAR_ADDR BB08 regmask=[rdx] minReg=1> #94 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #98 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> #99 RefTypeDef PUTARG_REG BB08 regmask=[rdx] minReg=1 fixed> #101 RefTypeFixedReg BB08 regmask=[rcx] minReg=1> BB08 regmask=[rcx] minReg=1 last fixed> #102 RefTypeFixedReg BB08 regmask=[rdx] minReg=1> BB08 regmask=[rdx] minReg=1 last fixed> #107 RefTypeKill BB08 regmask=[rax] minReg=1 last> #130 RefTypeKill BB08 regmask=[rcx] minReg=1 last> #138 RefTypeKill BB08 regmask=[rdx] minReg=1 last> #139 RefTypeKill BB08 regmask=[r8] minReg=1 last> #140 RefTypeKill BB08 regmask=[r9] minReg=1 last> #141 RefTypeKill BB08 regmask=[r10] minReg=1 last> #142 RefTypeKill BB08 regmask=[r11] minReg=1 last> #136 RefTypeFixedReg BB08 regmask=[rax] minReg=1> #109 RefTypeDef CALL BB08 regmask=[rax] minReg=1 fixed> BB08 regmask=[rax] minReg=1 last regOptional> #111 RefTypeDef EQ BB08 regmask=[r14] minReg=1> BB08 regmask=[r14] minReg=1 last> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[r14] minReg=1> LCL_VAR BB09 regmask=[r14] minReg=1 last regOptional> #222 RefTypeUse LCL_VAR BB10 regmask=[rdi] minReg=1 last> #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[rax] minReg=1> #120 RefTypeDef CNS_INT BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last> #124 RefTypeDef CNS_INT BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last> #126 RefTypeDef IND BB11 regmask=[r14] minReg=1> BB11 regmask=[r14] minReg=1 last> #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[r14] minReg=1 regOptional> #131 RefTypeDef GE BB11 regmask=[rcx] minReg=1> #132 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #134 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #135 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #137 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #206 RefTypeKill BB11 regmask=[rax] minReg=1 last> #193 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #198 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #209 RefTypeKill BB11 regmask=[r8] minReg=1 last> #210 RefTypeKill BB11 regmask=[r9] minReg=1 last> #211 RefTypeKill BB11 regmask=[r10] minReg=1 last> #212 RefTypeKill BB11 regmask=[r11] minReg=1 last> LCL_VAR BB11 regmask=[r14] minReg=1 last> #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> LCL_VAR BB11 regmask=[r14] minReg=1 last> #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[rbx] minReg=1> #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[r15] minReg=1> LCL_VAR BB11 regmask=[r14] minReg=1 last> #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[rsi] minReg=1> #153 RefTypeDef IND BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[rcx] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[rsi] minReg=1> #157 RefTypeDef IND BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last> #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[rdx] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[r14] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[rdx] minReg=1 regOptional> #162 RefTypeDef NE BB11 regmask=[rax] minReg=1> BB11 regmask=[rax] minReg=1 last> #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[rax] minReg=1> LCL_VAR BB11 regmask=[rax] minReg=1 last regOptional> #167 RefTypeDef CNS_INT BB15 regmask=[r12] minReg=1> BB15 regmask=[r12] minReg=1 last> #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[r12] minReg=1> #191 RefTypeUse LCL_VAR BB16 regmask=[rdx] minReg=1 regOptional> #172 RefTypeDef EQ BB16 regmask=[rax] minReg=1> BB16 regmask=[rax] minReg=1 last> #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 last regOptional> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[r12] minReg=1> #179 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rax] minReg=1> BB18 regmask=[rax] minReg=1 last> #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[rax] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rbx] minReg=1 last> LCL_VAR BB18 regmask=[rax] minReg=1 last> #326 RefTypeUse LCL_VAR BB18 regmask=[r14] minReg=1> #186 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rax] minReg=1> BB18 regmask=[rax] minReg=1 last> #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[rax] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rcx] minReg=1 last> LCL_VAR BB18 regmask=[rax] minReg=1 last> LCL_VAR BB18 regmask=[rdx] minReg=1 last> #194 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rcx] minReg=1> #195 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB18 regmask=[rcx] minReg=1 fixed> #199 RefTypeDef LCL_VAR_ADDR BB18 regmask=[rdx] minReg=1> #200 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB18 regmask=[rdx] minReg=1 fixed> #207 RefTypeFixedReg BB18 regmask=[rcx] minReg=1> BB18 regmask=[rcx] minReg=1 last fixed> #208 RefTypeFixedReg BB18 regmask=[rdx] minReg=1> BB18 regmask=[rdx] minReg=1 last fixed> #213 RefTypeKill BB18 regmask=[rax] minReg=1 last> #228 RefTypeKill BB18 regmask=[rcx] minReg=1 last> #233 RefTypeKill BB18 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB18 regmask=[r8] minReg=1 last> #245 RefTypeKill BB18 regmask=[r9] minReg=1 last> #246 RefTypeKill BB18 regmask=[r10] minReg=1 last> #247 RefTypeKill BB18 regmask=[r11] minReg=1 last> #241 RefTypeFixedReg BB18 regmask=[rax] minReg=1> #215 RefTypeDef CALL BB18 regmask=[rax] minReg=1 fixed> BB18 regmask=[rax] minReg=1 last regOptional> #217 RefTypeDef EQ BB18 regmask=[r12] minReg=1> BB18 regmask=[r12] minReg=1 last> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[r12] minReg=1> LCL_VAR BB19 regmask=[r12] minReg=1 last regOptional> #321 RefTypeUse LCL_VAR BB20 regmask=[rdi] minReg=1 last> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[rax] minReg=1> #227 RefTypeDef STORE_BLK BB21 regmask=[mm0] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> STORE_BLK BB21 regmask=[mm0] minReg=1 last> #230 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 copy fixed> #237 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> #238 RefTypeDef PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> #234 RefTypeDef LCL_VAR_ADDR BB21 regmask=[rdx] minReg=1> #235 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #239 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> #240 RefTypeDef PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> #242 RefTypeFixedReg BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> #243 RefTypeFixedReg BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB21 regmask=[rax] minReg=1 last> #292 RefTypeKill BB21 regmask=[rcx] minReg=1 last> #297 RefTypeKill BB21 regmask=[rdx] minReg=1 last> #308 RefTypeKill BB21 regmask=[r8] minReg=1 last> #309 RefTypeKill BB21 regmask=[r9] minReg=1 last> #310 RefTypeKill BB21 regmask=[r10] minReg=1 last> #311 RefTypeKill BB21 regmask=[r11] minReg=1 last> LCL_VAR BB21 regmask=[rbp] minReg=1 last> #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[rbp] minReg=1> #254 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> #252 RefTypeDef IND BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last> #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[rcx] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> #256 RefTypeDef IND BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last> #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[rdx] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[rbp] minReg=1 regOptional> #269 RefTypeUse LCL_VAR BB21 regmask=[rdx] minReg=1> #261 RefTypeDef NE BB21 regmask=[rax] minReg=1> BB21 regmask=[rax] minReg=1 last> #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[rax] minReg=1> LCL_VAR BB21 regmask=[rax] minReg=1 last regOptional> #266 RefTypeDef CNS_INT BB22 regmask=[rbx] minReg=1> BB22 regmask=[rbx] minReg=1 last> #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[rbx] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[rdx] minReg=1 regOptional> #271 RefTypeDef EQ BB23 regmask=[rax] minReg=1> BB23 regmask=[rax] minReg=1 last> #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1 last regOptional> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[rbx] minReg=1> #278 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rax] minReg=1> BB25 regmask=[rax] minReg=1 last> #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[rax] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[rax] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[r15] minReg=1> LCL_VAR BB25 regmask=[rax] minReg=1 last> LCL_VAR BB25 regmask=[rbp] minReg=1 last> #285 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rax] minReg=1> BB25 regmask=[rax] minReg=1 last> #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[rax] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[rax] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 last> LCL_VAR BB25 regmask=[rax] minReg=1 last> LCL_VAR BB25 regmask=[rdx] minReg=1 last> #293 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rcx] minReg=1> #294 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #301 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> #302 RefTypeDef PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> #298 RefTypeDef LCL_VAR_ADDR BB25 regmask=[rdx] minReg=1> #299 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #303 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> #304 RefTypeDef PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> #306 RefTypeFixedReg BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> #307 RefTypeFixedReg BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> #312 RefTypeKill BB25 regmask=[rax] minReg=1 last> #370 RefTypeKill BB25 regmask=[rcx] minReg=1 last> #375 RefTypeKill BB25 regmask=[rdx] minReg=1 last> #386 RefTypeKill BB25 regmask=[r8] minReg=1 last> #387 RefTypeKill BB25 regmask=[r9] minReg=1 last> #388 RefTypeKill BB25 regmask=[r10] minReg=1 last> #389 RefTypeKill BB25 regmask=[r11] minReg=1 last> #383 RefTypeFixedReg BB25 regmask=[rax] minReg=1> #314 RefTypeDef CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[rax] minReg=1 last regOptional> #316 RefTypeDef EQ BB25 regmask=[rbx] minReg=1> BB25 regmask=[rbx] minReg=1 last> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[rbx] minReg=1> LCL_VAR BB26 regmask=[rbx] minReg=1 last regOptional> #399 RefTypeUse LCL_VAR BB27 regmask=[rdi] minReg=1 last> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[rax] minReg=1> LCL_VAR BB28 regmask=[r15] minReg=1 last> #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[r15] minReg=1> LCL_VAR BB28 regmask=[r14] minReg=1 last> #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[r14] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[rsi] minReg=1> #330 RefTypeDef IND BB28 regmask=[rcx] minReg=1> BB28 regmask=[rcx] minReg=1 last> #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[rcx] minReg=1> LCL_VAR BB28 regmask=[rsi] minReg=1 last> #334 RefTypeDef IND BB28 regmask=[rdx] minReg=1> BB28 regmask=[rdx] minReg=1 last> #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[rdx] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[r14] minReg=1 regOptional> #347 RefTypeUse LCL_VAR BB28 regmask=[rdx] minReg=1> #339 RefTypeDef NE BB28 regmask=[rax] minReg=1> BB28 regmask=[rax] minReg=1 last> #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[rax] minReg=1> LCL_VAR BB28 regmask=[rax] minReg=1 last regOptional> #344 RefTypeDef CNS_INT BB29 regmask=[rsi] minReg=1> BB29 regmask=[rsi] minReg=1 last> #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[rsi] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[rdx] minReg=1 regOptional> #349 RefTypeDef EQ BB30 regmask=[rax] minReg=1> BB30 regmask=[rax] minReg=1 last> #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[rax] minReg=1> LCL_VAR BB30 regmask=[rax] minReg=1 last regOptional> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[rsi] minReg=1> #356 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rax] minReg=1> BB32 regmask=[rax] minReg=1 last> #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[rax] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR BB32 regmask=[r15] minReg=1 last> LCL_VAR BB32 regmask=[rax] minReg=1 last> LCL_VAR BB32 regmask=[r14] minReg=1 last> #363 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rax] minReg=1> BB32 regmask=[rax] minReg=1 last> #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[rax] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last> LCL_VAR BB32 regmask=[rax] minReg=1 last> LCL_VAR BB32 regmask=[rdx] minReg=1 last> #371 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rcx] minReg=1> #372 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #379 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> #380 RefTypeDef PUTARG_REG BB32 regmask=[rcx] minReg=1 fixed> #376 RefTypeDef LCL_VAR_ADDR BB32 regmask=[rdx] minReg=1> #377 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #381 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> #382 RefTypeDef PUTARG_REG BB32 regmask=[rdx] minReg=1 fixed> #384 RefTypeFixedReg BB32 regmask=[rcx] minReg=1> BB32 regmask=[rcx] minReg=1 last fixed> #385 RefTypeFixedReg BB32 regmask=[rdx] minReg=1> BB32 regmask=[rdx] minReg=1 last fixed> #390 RefTypeKill BB32 regmask=[rax] minReg=1 last> BB32 regmask=[rcx] minReg=1 last> BB32 regmask=[rdx] minReg=1 last> BB32 regmask=[r8] minReg=1 last> BB32 regmask=[r9] minReg=1 last> BB32 regmask=[r10] minReg=1 last> BB32 regmask=[r11] minReg=1 last> #407 RefTypeFixedReg BB32 regmask=[rax] minReg=1> #392 RefTypeDef CALL BB32 regmask=[rax] minReg=1 fixed> BB32 regmask=[rax] minReg=1 last regOptional> #394 RefTypeDef EQ BB32 regmask=[rsi] minReg=1> BB32 regmask=[rsi] minReg=1 last> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[rsi] minReg=1> LCL_VAR BB33 regmask=[rsi] minReg=1 last regOptional> #402 RefTypeUse LCL_VAR BB34 regmask=[rdi] minReg=1 last> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[rax] minReg=1> LCL_VAR BB35 regmask=[rdi] minReg=1 last> #404 RefTypeDef CNS_INT BB35 regmask=[rax] minReg=1> BB35 regmask=[rax] minReg=1 last> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[rax] minReg=1> BB36 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> VAR REFPOSITIONS AFTER ALLOCATION --- V00 #45 RefTypeParamDef BB00 regmask=[rsi] minReg=1 fixed> #49 RefTypeUse LCL_VAR BB01 regmask=[rsi] minReg=1> #151 RefTypeUse LCL_VAR BB01 regmask=[rsi] minReg=1> #155 RefTypeUse LCL_VAR BB11 regmask=[rsi] minReg=1> #226 RefTypeUse LCL_VAR BB11 regmask=[rsi] minReg=1> #229 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> #250 RefTypeUse LCL_VAR BB21 regmask=[rcx] minReg=1 copy fixed> #254 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> #328 RefTypeUse LCL_VAR BB21 regmask=[rsi] minReg=1> #332 RefTypeUse LCL_VAR BB28 regmask=[rsi] minReg=1> LCL_VAR BB28 regmask=[rsi] minReg=1 last> --- V01 #116 RefTypeParamDef BB00 regmask=[rdi] minReg=1 fixed> #222 RefTypeUse LCL_VAR BB10 regmask=[rdi] minReg=1 last> #321 RefTypeUse LCL_VAR BB20 regmask=[rdi] minReg=1 last> #399 RefTypeUse LCL_VAR BB27 regmask=[rdi] minReg=1 last> #402 RefTypeUse LCL_VAR BB34 regmask=[rdi] minReg=1 last> LCL_VAR BB35 regmask=[rdi] minReg=1 last> --- V02 --- V03 --- V04 --- V05 #223 RefTypeDef STORE_LCL_VAR BB10 regmask=[rax] minReg=1> #322 RefTypeDef STORE_LCL_VAR BB20 regmask=[rax] minReg=1> #400 RefTypeDef STORE_LCL_VAR BB27 regmask=[rax] minReg=1> #405 RefTypeDef STORE_LCL_VAR BB34 regmask=[rax] minReg=1> #408 RefTypeDef STORE_LCL_VAR BB35 regmask=[rax] minReg=1> LCL_VAR BB36 regmask=[rax] minReg=1 last fixed> --- V06 --- V07 --- V08 --- V09 --- V10 #31 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> --- V11 --- V12 --- V13 --- V14 #16 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> #35 RefTypeUse LCL_VAR BB01 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB01 regmask=[rbp] minReg=1 last> --- V15 --- V16 --- V17 --- V18 --- V19 #58 RefTypeDef STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last regOptional> --- V20 #68 RefTypeDef STORE_LCL_VAR BB06 regmask=[rax] minReg=1> LCL_VAR BB06 regmask=[rax] minReg=1 last regOptional> --- V21 #70 RefTypeDef STORE_LCL_VAR BB05 regmask=[r14] minReg=1> #112 RefTypeDef STORE_LCL_VAR BB07 regmask=[r14] minReg=1> #114 RefTypeDef STORE_LCL_VAR BB08 regmask=[r14] minReg=1> LCL_VAR BB09 regmask=[r14] minReg=1 last regOptional> --- V22 --- V23 --- V24 --- V25 --- V26 --- V27 --- V28 --- V29 --- V30 #128 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> #143 RefTypeUse LCL_VAR BB11 regmask=[r14] minReg=1 regOptional> LCL_VAR BB11 regmask=[r14] minReg=1 last> --- V31 --- V32 --- V33 --- V34 --- V35 #164 RefTypeDef STORE_LCL_VAR BB11 regmask=[rax] minReg=1> LCL_VAR BB11 regmask=[rax] minReg=1 last regOptional> --- V36 #174 RefTypeDef STORE_LCL_VAR BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 last regOptional> --- V37 #176 RefTypeDef STORE_LCL_VAR BB15 regmask=[r12] minReg=1> #218 RefTypeDef STORE_LCL_VAR BB17 regmask=[r12] minReg=1> #220 RefTypeDef STORE_LCL_VAR BB18 regmask=[r12] minReg=1> LCL_VAR BB19 regmask=[r12] minReg=1 last regOptional> --- V38 --- V39 --- V40 --- V41 --- V42 --- V43 --- V44 #263 RefTypeDef STORE_LCL_VAR BB21 regmask=[rax] minReg=1> LCL_VAR BB21 regmask=[rax] minReg=1 last regOptional> --- V45 #273 RefTypeDef STORE_LCL_VAR BB23 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[rax] minReg=1 last regOptional> --- V46 #275 RefTypeDef STORE_LCL_VAR BB22 regmask=[rbx] minReg=1> #317 RefTypeDef STORE_LCL_VAR BB24 regmask=[rbx] minReg=1> #319 RefTypeDef STORE_LCL_VAR BB25 regmask=[rbx] minReg=1> LCL_VAR BB26 regmask=[rbx] minReg=1 last regOptional> --- V47 --- V48 --- V49 --- V50 --- V51 --- V52 --- V53 #341 RefTypeDef STORE_LCL_VAR BB28 regmask=[rax] minReg=1> LCL_VAR BB28 regmask=[rax] minReg=1 last regOptional> --- V54 #351 RefTypeDef STORE_LCL_VAR BB30 regmask=[rax] minReg=1> LCL_VAR BB30 regmask=[rax] minReg=1 last regOptional> --- V55 #353 RefTypeDef STORE_LCL_VAR BB29 regmask=[rsi] minReg=1> #395 RefTypeDef STORE_LCL_VAR BB31 regmask=[rsi] minReg=1> #397 RefTypeDef STORE_LCL_VAR BB32 regmask=[rsi] minReg=1> LCL_VAR BB33 regmask=[rsi] minReg=1 last regOptional> --- V56 --- V57 --- V58 --- V59 --- V60 --- V61 #76 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #147 RefTypeUse LCL_VAR BB08 regmask=[rbx] minReg=1> #182 RefTypeUse LCL_VAR BB11 regmask=[rbx] minReg=1> LCL_VAR BB18 regmask=[rbx] minReg=1 last> --- V62 #53 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> #78 RefTypeUse LCL_VAR BB01 regmask=[rbp] minReg=1> #248 RefTypeUse LCL_VAR BB08 regmask=[rbp] minReg=1> LCL_VAR BB21 regmask=[rbp] minReg=1 last> --- V63 #281 RefTypeDef STORE_LCL_VAR BB11 regmask=[r15] minReg=1> #324 RefTypeUse LCL_VAR BB25 regmask=[r15] minReg=1> LCL_VAR BB28 regmask=[r15] minReg=1 last> --- V64 #159 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> #184 RefTypeUse LCL_VAR BB11 regmask=[r14] minReg=1> #326 RefTypeUse LCL_VAR BB18 regmask=[r14] minReg=1> LCL_VAR BB28 regmask=[r14] minReg=1 last> --- V65 #37 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> --- V66 #39 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB01 regmask=[rbp] minReg=1 last> --- V67 #41 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> --- V68 #43 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbp] minReg=1> LCL_VAR BB01 regmask=[rbp] minReg=1 last> --- V69 --- V70 --- V71 #33 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> --- V72 --- V73 --- V74 #83 RefTypeDef STORE_LCL_VAR BB01 regmask=[rcx] minReg=1> LCL_VAR BB08 regmask=[rcx] minReg=1 last> --- V75 #54 RefTypeDef STORE_LCL_VAR BB01 regmask=[rdx] minReg=1> #64 RefTypeUse LCL_VAR BB01 regmask=[rdx] minReg=1 regOptional> #85 RefTypeUse LCL_VAR BB06 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB08 regmask=[rdx] minReg=1 last> --- V76 --- V77 #145 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> LCL_VAR BB11 regmask=[r14] minReg=1 last> --- V78 --- V79 #149 RefTypeDef STORE_LCL_VAR BB11 regmask=[r14] minReg=1> LCL_VAR BB11 regmask=[r14] minReg=1 last> --- V80 --- V81 --- V82 --- V83 --- V84 --- V85 #189 RefTypeDef STORE_LCL_VAR BB11 regmask=[rcx] minReg=1> LCL_VAR BB18 regmask=[rcx] minReg=1 last> --- V86 #160 RefTypeDef STORE_LCL_VAR BB11 regmask=[rdx] minReg=1> #170 RefTypeUse LCL_VAR BB11 regmask=[rdx] minReg=1 regOptional> #191 RefTypeUse LCL_VAR BB16 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB18 regmask=[rdx] minReg=1 last> --- V87 --- V88 #258 RefTypeDef STORE_LCL_VAR BB21 regmask=[rbp] minReg=1> #283 RefTypeUse LCL_VAR BB21 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB25 regmask=[rbp] minReg=1 last> --- V89 #288 RefTypeDef STORE_LCL_VAR BB21 regmask=[rcx] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 last> --- V90 #259 RefTypeDef STORE_LCL_VAR BB21 regmask=[rdx] minReg=1> #269 RefTypeUse LCL_VAR BB21 regmask=[rdx] minReg=1> #290 RefTypeUse LCL_VAR BB23 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB25 regmask=[rdx] minReg=1 last> --- V91 #359 RefTypeDef STORE_LCL_VAR BB28 regmask=[r15] minReg=1> LCL_VAR BB32 regmask=[r15] minReg=1 last> --- V92 #336 RefTypeDef STORE_LCL_VAR BB28 regmask=[r14] minReg=1> #361 RefTypeUse LCL_VAR BB28 regmask=[r14] minReg=1 regOptional> LCL_VAR BB32 regmask=[r14] minReg=1 last> --- V93 #366 RefTypeDef STORE_LCL_VAR BB28 regmask=[rcx] minReg=1> LCL_VAR BB32 regmask=[rcx] minReg=1 last> --- V94 #337 RefTypeDef STORE_LCL_VAR BB28 regmask=[rdx] minReg=1> #347 RefTypeUse LCL_VAR BB28 regmask=[rdx] minReg=1> #368 RefTypeUse LCL_VAR BB30 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB32 regmask=[rdx] minReg=1 last> --- V95 --- V96 #6 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #7 RefTypeUse LCL_VAR BB01 regmask=[rbx] minReg=1> #121 RefTypeUse LCL_VAR BB01 regmask=[rbx] minReg=1 last> #122 RefTypeDef STORE_LCL_VAR BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last> --- V97 --- V98 #75 RefTypeDef STORE_LCL_VAR BB08 regmask=[rax] minReg=1> #77 RefTypeUse LCL_VAR BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last> --- V99 --- V100 #82 RefTypeDef STORE_LCL_VAR BB08 regmask=[rax] minReg=1> #84 RefTypeUse LCL_VAR BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last> --- V101 #181 RefTypeDef STORE_LCL_VAR BB18 regmask=[rax] minReg=1> #183 RefTypeUse LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 last> --- V102 #188 RefTypeDef STORE_LCL_VAR BB18 regmask=[rax] minReg=1> #190 RefTypeUse LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 last> --- V103 --- V104 #280 RefTypeDef STORE_LCL_VAR BB25 regmask=[rax] minReg=1> #282 RefTypeUse LCL_VAR BB25 regmask=[rax] minReg=1> LCL_VAR BB25 regmask=[rax] minReg=1 last> --- V105 #287 RefTypeDef STORE_LCL_VAR BB25 regmask=[rax] minReg=1> #289 RefTypeUse LCL_VAR BB25 regmask=[rax] minReg=1> LCL_VAR BB25 regmask=[rax] minReg=1 last> --- V106 #358 RefTypeDef STORE_LCL_VAR BB32 regmask=[rax] minReg=1> #360 RefTypeUse LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR BB32 regmask=[rax] minReg=1 last> --- V107 #365 RefTypeDef STORE_LCL_VAR BB32 regmask=[rax] minReg=1> #367 RefTypeUse LCL_VAR BB32 regmask=[rax] minReg=1> LCL_VAR BB32 regmask=[rax] minReg=1 last> --- V108 Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V05 V21 V37 V46 V55 V61 V62 V63 V64 V74 V75 V85 V86 V88 V89 V90 V91 V92 V93 V94} Has NoCritical Edges Prior to Resolution BB01 use def in out {V00} {V09 V10 V14 V19 V61 V62 V65 V66 V67 V68 V71 V72 V73 V74 V75 V96} {V00 V01} {V00 V01 V61 V62 V74 V75} Var=Reg beg of BB01: V00=rsi V01=rdi Var=Reg end of BB01: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx BB05 use def in out {} {V21} {V00 V01 V61 V62} {V00 V01 V21 V61 V62} Var=Reg beg of BB05: V00=rsi V01=rdi V61=rbx V62=rbp Var=Reg end of BB05: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB06 use def in out {V75} {V20} {V00 V01 V61 V62 V74 V75} {V00 V01 V61 V62 V74 V75} Var=Reg beg of BB06: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx Var=Reg end of BB06: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx BB07 use def in out {} {V21} {V00 V01 V61 V62} {V00 V01 V21 V61 V62} Var=Reg beg of BB07: V00=rsi V01=rdi V61=rbx V62=rbp Var=Reg end of BB07: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB08 use def in out {V61 V62 V74 V75} {V21 V98 V100} {V00 V01 V61 V62 V74 V75} {V00 V01 V21 V61 V62} Var=Reg beg of BB08: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx Var=Reg end of BB08: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB09 use def in out {V21} {} {V00 V01 V21 V61 V62} {V00 V01 V61 V62} Var=Reg beg of BB09: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 Var=Reg end of BB09: V00=rsi V01=rdi V61=rbx V62=rbp BB10 use def in out {V01} {V05} {V01} {V05} Var=Reg beg of BB10: V01=rdi Var=Reg end of BB10: V05=rax BB11 use def in out {V00 V61} {V25 V26 V30 V35 V63 V64 V76 V77 V78 V79 V82 V83 V84 V85 V86 V96} {V00 V01 V61 V62} {V00 V01 V61 V62 V63 V64 V85 V86} Var=Reg beg of BB11: V00=rsi V01=rdi V61=rbx V62=rbp Var=Reg end of BB11: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx BB15 use def in out {} {V37} {V00 V01 V62 V63 V64} {V00 V01 V37 V62 V63 V64} Var=Reg beg of BB15: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 Var=Reg end of BB15: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB16 use def in out {V86} {V36} {V00 V01 V61 V62 V63 V64 V85 V86} {V00 V01 V61 V62 V63 V64 V85 V86} Var=Reg beg of BB16: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx Var=Reg end of BB16: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx BB17 use def in out {} {V37} {V00 V01 V62 V63 V64} {V00 V01 V37 V62 V63 V64} Var=Reg beg of BB17: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 Var=Reg end of BB17: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB18 use def in out {V61 V64 V85 V86} {V37 V101 V102} {V00 V01 V61 V62 V63 V64 V85 V86} {V00 V01 V37 V62 V63 V64} Var=Reg beg of BB18: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx Var=Reg end of BB18: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB19 use def in out {V37} {} {V00 V01 V37 V62 V63 V64} {V00 V01 V62 V63 V64} Var=Reg beg of BB19: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 Var=Reg end of BB19: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 BB20 use def in out {V01} {V05} {V01} {V05} Var=Reg beg of BB20: V01=rdi Var=Reg end of BB20: V05=rax BB21 use def in out {V00 V62 V63} {V44 V87 V88 V89 V90 V103} {V00 V01 V62 V63 V64} {V00 V01 V63 V64 V88 V89 V90} Var=Reg beg of BB21: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 Var=Reg end of BB21: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx BB22 use def in out {} {V46} {V00 V01 V63 V64} {V00 V01 V46 V63 V64} Var=Reg beg of BB22: V00=rsi V01=rdi V64=r14 V63=r15 Var=Reg end of BB22: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB23 use def in out {V90} {V45} {V00 V01 V63 V64 V88 V89 V90} {V00 V01 V63 V64 V88 V89 V90} Var=Reg beg of BB23: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx Var=Reg end of BB23: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx BB24 use def in out {} {V46} {V00 V01 V63 V64} {V00 V01 V46 V63 V64} Var=Reg beg of BB24: V00=rsi V01=rdi V64=r14 V63=r15 Var=Reg end of BB24: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB25 use def in out {V63 V88 V89 V90} {V46 V104 V105} {V00 V01 V63 V64 V88 V89 V90} {V00 V01 V46 V63 V64} Var=Reg beg of BB25: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx Var=Reg end of BB25: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB26 use def in out {V46} {} {V00 V01 V46 V63 V64} {V00 V01 V63 V64} Var=Reg beg of BB26: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx Var=Reg end of BB26: V00=rsi V01=rdi V64=r14 V63=r15 BB27 use def in out {V01} {V05} {V01} {V05} Var=Reg beg of BB27: V01=rdi Var=Reg end of BB27: V05=rax BB28 use def in out {V00 V63 V64} {V53 V91 V92 V93 V94} {V00 V01 V63 V64} {V01 V91 V92 V93 V94} Var=Reg beg of BB28: V00=rsi V01=rdi V64=r14 V63=r15 Var=Reg end of BB28: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx BB29 use def in out {} {V55} {V01} {V01 V55} Var=Reg beg of BB29: V01=rdi Var=Reg end of BB29: V01=rdi V55=rsi BB30 use def in out {V94} {V54} {V01 V91 V92 V93 V94} {V01 V91 V92 V93 V94} Var=Reg beg of BB30: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx Var=Reg end of BB30: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx BB31 use def in out {} {V55} {V01} {V01 V55} Var=Reg beg of BB31: V01=rdi Var=Reg end of BB31: V01=rdi V55=rsi BB32 use def in out {V91 V92 V93 V94} {V55 V106 V107} {V01 V91 V92 V93 V94} {V01 V55} Var=Reg beg of BB32: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx Var=Reg end of BB32: V01=rdi V55=rsi BB33 use def in out {V55} {} {V01 V55} {V01} Var=Reg beg of BB33: V01=rdi V55=rsi Var=Reg end of BB33: V01=rdi BB34 use def in out {V01} {V05} {V01} {V05} Var=Reg beg of BB34: V01=rdi Var=Reg end of BB34: V05=rax BB35 use def in out {V01} {V05} {V01} {V05} Var=Reg beg of BB35: V01=rdi Var=Reg end of BB35: V05=rax BB36 use def in out {V05} {} {V05} {} Var=Reg beg of BB36: V05=rax Var=Reg end of BB36: none RESOLVING EDGES Set V00 argument initial register to rsi Set V01 argument initial register to rdi Trees after linear scan register allocator (LSRA) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} N001 ( 0, 0) [001446] ------------ t1446 = PHI_ARG int V68 tmp59 u:5 rbp N002 ( 0, 0) [001442] ------------ t1442 = PHI_ARG int V68 tmp59 u:4 rbp /--* t1446 int +--* t1442 int N005 ( 2, 2) [001397] ------------ t1397 = * PHI int /--* t1397 int N007 ( 6, 5) [001398] DA---------- * STORE_LCL_VAR int V68 tmp59 d:3 rbp N001 ( 0, 0) [001448] ------------ t1448 = PHI_ARG byref V67 tmp58 u:5 rbx N002 ( 0, 0) [001444] ------------ t1444 = PHI_ARG byref V67 tmp58 u:4 rbx $VN.Null /--* t1448 byref +--* t1444 byref N005 ( 2, 2) [001393] ------------ t1393 = * PHI byref /--* t1393 byref N007 ( 6, 5) [001394] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:3 rbx N003 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 REG NA N005 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 REG NA N007 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG rbx $180 /--* t947 ref N009 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 rbx REG rbx N011 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 rbx REG rbx $180 /--* t940 ref N013 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte REG NA $241 N015 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 rbx (last use) REG rbx $180 N017 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] REG NA $280 /--* t943 ref +--* t944 long N019 ( 5, 4) [000945] ------------ t945 = * ADD byref REG rbx $VN.Null /--* t945 byref N021 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 rbx REG rbx N023 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 REG NA N025 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG rcx $180 /--* t955 ref N027 (???,???) [001478] -c---------- t1478 = * LEA(b+8) byref REG NA /--* t1478 byref N029 ( 6, 13) [000236] x---G------- t236 = * IND int REG rbp /--* t236 int N031 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 rbp REG rbp N033 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 REG NA N035 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 REG NA N037 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 rbp REG rbp N039 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 REG NA $40 /--* t240 int +--* t250 int N041 ( 8, 4) [000251] ------------ t251 = * GE int REG rcx /--* t251 int N043 (???,???) [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx N045 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void N047 ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 REG NA N049 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 rbx (last use) REG rbx $VN.Null /--* t188 byref N051 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 rbx REG rbx N053 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 REG NA N055 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 rbx (last use) REG rbx $VN.Null /--* t970 byref N057 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 rbx REG rbx N059 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 REG NA N061 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 rbp (last use) REG rbp /--* t276 int N063 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 rbp REG rbp N065 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 REG NA N067 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 rbx (last use) REG rbx $VN.Null /--* t973 byref N069 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 rbx REG rbx N071 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 rbp (last use) REG rbp /--* t976 int N073 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 rbp REG rbp N075 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 rbx (last use) REG rbx $VN.Null /--* t980 byref N077 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 rbx REG rbx N079 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 rbp (last use) REG rbp $3c0 /--* t983 int N081 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 rbp REG rbp N083 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc REG NA N085 ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc REG NA N087 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t995 byref N089 (???,???) [001480] -c---------- t1480 = * LEA(b+0) byref REG NA /--* t1480 byref N091 ( 4, 3) [000998] x----------- t998 = * IND byref REG rcx /--* t998 byref N093 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 rcx REG rcx N095 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1001 byref N097 (???,???) [001481] -c---------- t1481 = * LEA(b+8) byref REG NA /--* t1481 byref N099 ( 4, 4) [001004] x----------- t1004 = * IND int REG rdx /--* t1004 int N101 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 rdx REG rdx N103 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc REG NA N105 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 rbp REG rbp $3c0 N107 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 rdx REG rdx /--* t295 int +--* t393 int N109 ( 6, 3) [000297] ------------ t297 = * NE int REG rax /--* t297 int N111 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 rax REG rax N113 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc REG NA N115 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 rax (last use) REG rax N117 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 REG NA $40 /--* t303 int +--* t304 int N119 ( 3, 3) [000305] J------N---- * EQ void REG NA N121 ( 5, 5) [000306] ------------ * JTRUE void REG NA ------------ BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} N125 ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc REG NA N127 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 REG r14 $40 /--* t348 int N129 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 r14 REG r14 ------------ BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} N133 ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc REG NA N135 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 rdx REG rdx N137 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 REG NA $40 /--* t406 int +--* t314 int N139 ( 6, 3) [000315] ------------ t315 = * EQ int REG rax /--* t315 int N141 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 rax REG rax N143 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc REG NA N145 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 rax (last use) REG rax N147 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 REG NA $40 /--* t319 int +--* t320 int N149 ( 5, 4) [000321] J------N---- * EQ void REG NA N151 ( 7, 6) [000322] ------------ * JTRUE void REG NA ------------ BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} N155 ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc REG NA N157 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 REG NA $41 /--* t343 int N159 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 r14 REG r14 ------------ BB08 [00C..00D), preds={BB06} succs={BB09} N163 ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc REG NA N165 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax /--* t1016 byref N167 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 rax REG rax N169 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 rax REG rax $2ca /--* t1019 byref N171 (???,???) [001482] -c---------- t1482 = * LEA(b+0) byref REG NA N173 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 rbx REG rbx $VN.Null /--* t1482 byref +--* t1023 byref N175 (???,???) [001456] -A---------- * STOREIND byref REG NA N177 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 rax (last use) REG rax $2ca /--* t1026 byref N179 (???,???) [001483] -c---------- t1483 = * LEA(b+8) byref REG NA N181 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 rbp REG rbp $3c0 /--* t1483 byref +--* t1030 int N183 (???,???) [001457] -A--------L- * STOREIND int REG NA N185 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax /--* t1037 byref N187 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 rax REG rax N189 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 rax REG rax $2cc /--* t1040 byref N191 (???,???) [001484] -c---------- t1484 = * LEA(b+0) byref REG NA N193 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 rcx (last use) REG rcx /--* t1484 byref +--* t1044 byref N195 (???,???) [001458] -A---------- * STOREIND byref REG NA N197 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 rax (last use) REG rax $2cc /--* t1047 byref N199 (???,???) [001485] -c---------- t1485 = * LEA(b+8) byref REG NA N201 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 rdx (last use) REG rdx /--* t1485 byref +--* t1051 int N203 (???,???) [001459] -A--------L- * STOREIND int REG NA N205 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx /--* t1054 byref N207 (???,???) [001486] ------------ t1486 = * PUTARG_REG byref REG rcx N209 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx /--* t1057 byref N211 (???,???) [001487] ------------ t1487 = * PUTARG_REG byref REG rdx /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx N213 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce N215 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 REG NA $40 /--* t327 int +--* t334 int N217 ( 81, 55) [000335] ---XG------- t335 = * EQ int REG r14 $30d /--* t335 int N219 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 r14 REG r14 ------------ BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} N001 ( 0, 0) [001404] ------------ t1404 = PHI_ARG bool V21 tmp12 u:5 r14 N002 ( 0, 0) [001402] ------------ t1402 = PHI_ARG bool V21 tmp12 u:4 r14 $41 N003 ( 0, 0) [001400] ------------ t1400 = PHI_ARG bool V21 tmp12 u:3 r14 $30d /--* t1404 bool +--* t1402 bool +--* t1400 bool N007 ( 3, 3) [001389] ------------ t1389 = * PHI bool /--* t1389 bool N009 ( 8, 7) [001390] DA---------- * STORE_LCL_VAR bool V21 tmp12 d:6 r14 N223 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 REG NA N225 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 r14 (last use) REG r14 $500 N227 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 REG NA $40 /--* t25 int +--* t26 int N229 ( 3, 3) [000027] J------N---- * EQ void REG NA $30e N231 ( 5, 5) [000028] ------------ * JTRUE void REG NA ------------ BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} N235 ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 REG NA N237 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 N239 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 REG NA $41 /--* t156 byref +--* t157 int N241 (???,???) [001460] -A-XG------- * STOREIND byte REG NA N243 ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b REG NA N245 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 REG NA $41 /--* t161 int N247 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 rax REG rax ------------ BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} N001 ( 0, 0) [001436] ------------ t1436 = PHI_ARG int V79 tmp70 u:5 r14 N002 ( 0, 0) [001432] ------------ t1432 = PHI_ARG int V79 tmp70 u:4 r14 /--* t1436 int +--* t1432 int N005 ( 2, 2) [001385] ------------ t1385 = * PHI int /--* t1385 int N007 ( 6, 5) [001386] DA---------- * STORE_LCL_VAR int V79 tmp70 d:3 r14 N001 ( 0, 0) [001438] ------------ t1438 = PHI_ARG byref V78 tmp69 u:5 N002 ( 0, 0) [001434] ------------ t1434 = PHI_ARG byref V78 tmp69 u:4 $VN.Null /--* t1438 byref +--* t1434 byref N005 ( 2, 2) [001381] ------------ t1381 = * PHI byref /--* t1381 byref N007 ( 6, 5) [001382] DA---------- * STORE_LCL_VAR byref V78 tmp69 d:3 N251 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f REG NA N253 ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f REG NA N255 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG rcx $184 /--* t1089 ref N257 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 rcx REG rcx N259 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 rcx (last use) REG rcx $184 /--* t1082 ref N261 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte REG NA $24c N263 ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f REG NA N265 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG rcx $184 /--* t1097 ref N267 (???,???) [001488] -c---------- t1488 = * LEA(b+8) byref REG NA /--* t1488 byref N269 ( 6, 13) [000483] x---G------- t483 = * IND int REG r14 /--* t483 int N271 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 r14 REG r14 N273 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f REG NA N275 ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f REG NA N277 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 r14 REG r14 N279 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 REG NA $40 /--* t487 int +--* t497 int N281 ( 8, 4) [000498] ------------ t498 = * GE int REG rcx /--* t498 int N283 (???,???) [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx N285 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void N287 ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f REG NA N289 ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f REG NA N291 ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f REG NA N293 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 r14 (last use) REG r14 /--* t523 int N295 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 r14 REG r14 N297 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f REG NA N299 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 r14 (last use) REG r14 /--* t1118 int N301 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 r14 REG r14 N303 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 rbx REG rbx $VN.Null /--* t1122 byref N305 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 r15 REG r15 N307 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 r14 (last use) REG r14 $3c2 /--* t1125 int N309 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 r14 REG r14 N311 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a REG NA N313 ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a REG NA N315 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1137 byref N317 (???,???) [001490] -c---------- t1490 = * LEA(b+0) byref REG NA /--* t1490 byref N319 ( 4, 3) [001140] x----------- t1140 = * IND byref REG rcx /--* t1140 byref N321 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 rcx REG rcx N323 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1143 byref N325 (???,???) [001491] -c---------- t1491 = * LEA(b+8) byref REG NA /--* t1491 byref N327 ( 4, 4) [001146] x----------- t1146 = * IND int REG rdx /--* t1146 int N329 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 rdx REG rdx N331 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a REG NA N333 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 r14 REG r14 $3c2 N335 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 rdx REG rdx /--* t542 int +--* t640 int N337 ( 10, 5) [000544] ------------ t544 = * NE int REG rax /--* t544 int N339 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 rax REG rax N341 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a REG NA N343 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 rax (last use) REG rax N345 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 REG NA $40 /--* t550 int +--* t551 int N347 ( 5, 4) [000552] J------N---- * EQ void REG NA N349 ( 7, 6) [000553] ------------ * JTRUE void REG NA ------------ BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} N353 ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a REG NA N355 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 REG r12 $40 /--* t595 int N357 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 r12 REG r12 ------------ BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} N361 ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a REG NA N363 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 rdx REG rdx N365 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 REG NA $40 /--* t653 int +--* t561 int N367 ( 8, 4) [000562] ------------ t562 = * EQ int REG rax /--* t562 int N369 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 rax REG rax N371 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a REG NA N373 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 rax (last use) REG rax N375 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 REG NA $40 /--* t566 int +--* t567 int N377 ( 5, 4) [000568] J------N---- * EQ void REG NA N379 ( 7, 6) [000569] ------------ * JTRUE void REG NA ------------ BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} N383 ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a REG NA N385 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 REG NA $41 /--* t590 int N387 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 r12 REG r12 ------------ BB18 [02A..02B), preds={BB16} succs={BB19} N391 ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a REG NA N393 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax /--* t1158 byref N395 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 rax REG rax N397 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 rax REG rax $2da /--* t1161 byref N399 (???,???) [001492] -c---------- t1492 = * LEA(b+0) byref REG NA N401 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 rbx (last use) REG rbx $VN.Null /--* t1492 byref +--* t1165 byref N403 (???,???) [001461] -A---------- * STOREIND byref REG NA N405 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 rax (last use) REG rax $2da /--* t1168 byref N407 (???,???) [001493] -c---------- t1493 = * LEA(b+8) byref REG NA N409 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 r14 REG r14 $3c2 /--* t1493 byref +--* t1172 int N411 (???,???) [001462] -A--------L- * STOREIND int REG NA N413 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax /--* t1179 byref N415 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 rax REG rax N417 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 rax REG rax $2dc /--* t1182 byref N419 (???,???) [001494] -c---------- t1494 = * LEA(b+0) byref REG NA N421 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 rcx (last use) REG rcx /--* t1494 byref +--* t1186 byref N423 (???,???) [001463] -A---------- * STOREIND byref REG NA N425 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 rax (last use) REG rax $2dc /--* t1189 byref N427 (???,???) [001495] -c---------- t1495 = * LEA(b+8) byref REG NA N429 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 rdx (last use) REG rdx /--* t1495 byref +--* t1193 int N431 (???,???) [001464] -A--------L- * STOREIND int REG NA N433 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx /--* t1196 byref N435 (???,???) [001496] ------------ t1496 = * PUTARG_REG byref REG rcx N437 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx /--* t1199 byref N439 (???,???) [001497] ------------ t1497 = * PUTARG_REG byref REG rdx /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx N441 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 N443 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 REG NA $40 /--* t574 int +--* t581 int N445 ( 85, 57) [000582] ---XG------- t582 = * EQ int REG r12 $31e /--* t582 int N447 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 r12 REG r12 ------------ BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} N001 ( 0, 0) [001410] ------------ t1410 = PHI_ARG bool V37 tmp28 u:5 r12 N002 ( 0, 0) [001408] ------------ t1408 = PHI_ARG bool V37 tmp28 u:4 r12 $31e N003 ( 0, 0) [001406] ------------ t1406 = PHI_ARG bool V37 tmp28 u:3 r12 $41 /--* t1410 bool +--* t1408 bool +--* t1406 bool N007 ( 3, 3) [001377] ------------ t1377 = * PHI bool /--* t1377 bool N009 ( 8, 7) [001378] DA---------- * STORE_LCL_VAR bool V37 tmp28 d:6 r12 N451 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 REG NA N453 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 r12 (last use) REG r12 $501 N455 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 REG NA $40 /--* t55 int +--* t56 int N457 ( 5, 4) [000057] J------N---- * EQ void REG NA $31f N459 ( 7, 6) [000058] ------------ * JTRUE void REG NA ------------ BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} N463 ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 REG NA N465 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 N467 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 REG NA $40 /--* t146 byref +--* t147 int N469 (???,???) [001465] -A-XG------- * STOREIND byte REG NA N471 ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b REG NA N473 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 REG NA $41 /--* t151 int N475 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 rax REG rax ------------ BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} N479 ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f REG NA N481 ( 5, 4) [001206] -----O----L- NOP void REG NA N483 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t61 byref N485 ( 3, 2) [000064] xc-----N---- t64 = * IND struct REG NA N487 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 NA REG NA /--* t1203 byref +--* t64 struct N489 (???,???) [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) REG NA N491 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1207 byref N493 (???,???) [001498] ------------ t1498 = * PUTARG_REG byref REG rcx N495 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 rdx REG rdx /--* t1209 byref N497 (???,???) [001499] ------------ t1499 = * PUTARG_REG byref REG rdx /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx N499 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void N501 ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 REG NA N503 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 rbp (last use) REG rbp $3c0 /--* t1216 int N505 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 rbp REG rbp N507 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 REG NA N509 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1221 byref N511 (???,???) [001500] -c---------- t1500 = * LEA(b+0) byref REG NA /--* t1500 byref N513 ( 4, 3) [001224] x----------- t1224 = * IND byref REG rcx /--* t1224 byref N515 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 rcx REG rcx N517 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1227 byref N519 (???,???) [001501] -c---------- t1501 = * LEA(b+8) byref REG NA /--* t1501 byref N521 ( 4, 4) [001230] x----------- t1230 = * IND int REG rdx /--* t1230 int N523 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 rdx REG rdx N525 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 REG NA N527 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 rbp REG rbp $3c0 N529 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 rdx REG rdx /--* t672 int +--* t770 int N531 ( 10, 5) [000674] ------------ t674 = * NE int REG rax /--* t674 int N533 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 rax REG rax N535 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 REG NA N537 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 rax (last use) REG rax N539 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 REG NA $40 /--* t680 int +--* t681 int N541 ( 5, 4) [000682] J------N---- * EQ void REG NA N543 ( 7, 6) [000683] ------------ * JTRUE void REG NA ------------ BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} N547 ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 REG NA N549 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 REG rbx $40 /--* t725 int N551 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 rbx REG rbx ------------ BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} N555 ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 REG NA N557 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 rdx REG rdx N559 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 REG NA $40 /--* t783 int +--* t691 int N561 ( 8, 4) [000692] ------------ t692 = * EQ int REG rax /--* t692 int N563 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 rax REG rax N565 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 REG NA N567 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 rax (last use) REG rax N569 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 REG NA $40 /--* t696 int +--* t697 int N571 ( 5, 4) [000698] J------N---- * EQ void REG NA N573 ( 7, 6) [000699] ------------ * JTRUE void REG NA ------------ BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} N577 ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 REG NA N579 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 REG NA $41 /--* t720 int N581 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 rbx REG rbx ------------ BB25 [047..048), preds={BB23} succs={BB26} N585 ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 REG NA N587 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax /--* t1242 byref N589 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 rax REG rax N591 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 rax REG rax $2e5 /--* t1245 byref N593 (???,???) [001502] -c---------- t1502 = * LEA(b+0) byref REG NA N595 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 r15 REG r15 $VN.Null /--* t1502 byref +--* t1249 byref N597 (???,???) [001467] -A---------- * STOREIND byref REG NA N599 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 rax (last use) REG rax $2e5 /--* t1252 byref N601 (???,???) [001503] -c---------- t1503 = * LEA(b+8) byref REG NA N603 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 rbp (last use) REG rbp $3c0 /--* t1503 byref +--* t1256 int N605 (???,???) [001468] -A--------L- * STOREIND int REG NA N607 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax /--* t1263 byref N609 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 rax REG rax N611 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 rax REG rax $2e7 /--* t1266 byref N613 (???,???) [001504] -c---------- t1504 = * LEA(b+0) byref REG NA N615 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 rcx (last use) REG rcx /--* t1504 byref +--* t1270 byref N617 (???,???) [001469] -A---------- * STOREIND byref REG NA N619 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 rax (last use) REG rax $2e7 /--* t1273 byref N621 (???,???) [001505] -c---------- t1505 = * LEA(b+8) byref REG NA N623 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 rdx (last use) REG rdx /--* t1505 byref +--* t1277 int N625 (???,???) [001470] -A--------L- * STOREIND int REG NA N627 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx /--* t1280 byref N629 (???,???) [001506] ------------ t1506 = * PUTARG_REG byref REG rcx N631 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx /--* t1283 byref N633 (???,???) [001507] ------------ t1507 = * PUTARG_REG byref REG rdx /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx N635 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 N637 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 REG NA $40 /--* t704 int +--* t711 int N639 ( 85, 57) [000712] ---XG------- t712 = * EQ int REG rbx $328 /--* t712 int N641 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 rbx REG rbx ------------ BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} N001 ( 0, 0) [001428] ------------ t1428 = PHI_ARG bool V46 tmp37 u:6 rbx N002 ( 0, 0) [001426] ------------ t1426 = PHI_ARG bool V46 tmp37 u:5 rbx $41 N003 ( 0, 0) [001424] ------------ t1424 = PHI_ARG bool V46 tmp37 u:4 rbx $328 /--* t1428 bool +--* t1426 bool +--* t1424 bool N007 ( 3, 3) [001373] ------------ t1373 = * PHI bool /--* t1373 bool N009 ( 8, 7) [001374] DA---------- * STORE_LCL_VAR bool V46 tmp37 d:3 rbx N645 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 REG NA N647 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 rbx (last use) REG rbx $502 N649 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 REG NA $40 /--* t85 int +--* t86 int N651 ( 5, 4) [000087] J------N---- * EQ void REG NA $329 N653 ( 7, 6) [000088] ------------ * JTRUE void REG NA ------------ BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} N657 ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 REG NA N659 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 N661 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 REG NA $41 /--* t136 byref +--* t137 int N663 (???,???) [001471] -A-XG------- * STOREIND byte REG NA N665 ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 REG NA N667 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 REG NA $41 /--* t141 int N669 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 rax REG rax ------------ BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} N673 ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c REG NA N675 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 r15 (last use) REG r15 $VN.Null /--* t1288 byref N677 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 r15 REG r15 N679 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 r14 (last use) REG r14 $3c2 /--* t1291 int N681 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 r14 REG r14 N683 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c REG NA N685 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1296 byref N687 (???,???) [001508] -c---------- t1508 = * LEA(b+0) byref REG NA /--* t1508 byref N689 ( 4, 3) [001299] x----------- t1299 = * IND byref REG rcx /--* t1299 byref N691 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 rcx REG rcx N693 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 rsi (last use) REG rsi $80 /--* t1302 byref N695 (???,???) [001509] -c---------- t1509 = * LEA(b+8) byref REG NA /--* t1509 byref N697 ( 4, 4) [001305] x----------- t1305 = * IND int REG rdx /--* t1305 int N699 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 rdx REG rdx N701 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c REG NA N703 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 r14 REG r14 $3c2 N705 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 rdx REG rdx /--* t802 int +--* t900 int N707 ( 10, 5) [000804] ------------ t804 = * NE int REG rax /--* t804 int N709 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 rax REG rax N711 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c REG NA N713 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 rax (last use) REG rax N715 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 REG NA $40 /--* t810 int +--* t811 int N717 ( 5, 4) [000812] J------N---- * EQ void REG NA N719 ( 7, 6) [000813] ------------ * JTRUE void REG NA ------------ BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} N723 ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c REG NA N725 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 REG rsi $40 /--* t855 int N727 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 rsi REG rsi ------------ BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} N731 ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c REG NA N733 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 rdx REG rdx N735 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 REG NA $40 /--* t913 int +--* t821 int N737 ( 8, 4) [000822] ------------ t822 = * EQ int REG rax /--* t822 int N739 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 rax REG rax N741 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c REG NA N743 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 rax (last use) REG rax N745 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 REG NA $40 /--* t826 int +--* t827 int N747 ( 5, 4) [000828] J------N---- * EQ void REG NA N749 ( 7, 6) [000829] ------------ * JTRUE void REG NA ------------ BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} N753 ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c REG NA N755 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 REG NA $41 /--* t850 int N757 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 rsi REG rsi ------------ BB32 [05C..05D), preds={BB30} succs={BB33} N761 ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c REG NA N763 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax /--* t1317 byref N765 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 rax REG rax N767 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 rax REG rax $2ee /--* t1320 byref N769 (???,???) [001510] -c---------- t1510 = * LEA(b+0) byref REG NA N771 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 r15 (last use) REG r15 $VN.Null /--* t1510 byref +--* t1324 byref N773 (???,???) [001472] -A---------- * STOREIND byref REG NA N775 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 rax (last use) REG rax $2ee /--* t1327 byref N777 (???,???) [001511] -c---------- t1511 = * LEA(b+8) byref REG NA N779 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 r14 (last use) REG r14 $3c2 /--* t1511 byref +--* t1331 int N781 (???,???) [001473] -A--------L- * STOREIND int REG NA N783 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax /--* t1338 byref N785 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 rax REG rax N787 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 rax REG rax $2f0 /--* t1341 byref N789 (???,???) [001512] -c---------- t1512 = * LEA(b+0) byref REG NA N791 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 rcx (last use) REG rcx /--* t1512 byref +--* t1345 byref N793 (???,???) [001474] -A---------- * STOREIND byref REG NA N795 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 rax (last use) REG rax $2f0 /--* t1348 byref N797 (???,???) [001513] -c---------- t1513 = * LEA(b+8) byref REG NA N799 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 rdx (last use) REG rdx /--* t1513 byref +--* t1352 int N801 (???,???) [001475] -A--------L- * STOREIND int REG NA N803 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx /--* t1355 byref N805 (???,???) [001514] ------------ t1514 = * PUTARG_REG byref REG rcx N807 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx /--* t1358 byref N809 (???,???) [001515] ------------ t1515 = * PUTARG_REG byref REG rdx /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx N811 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 N813 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 REG NA $40 /--* t834 int +--* t841 int N815 ( 85, 57) [000842] ---XG------- t842 = * EQ int REG rsi $332 /--* t842 int N817 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 rsi REG rsi ------------ BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} N001 ( 0, 0) [001420] ------------ t1420 = PHI_ARG bool V55 tmp46 u:6 rsi N002 ( 0, 0) [001418] ------------ t1418 = PHI_ARG bool V55 tmp46 u:5 rsi $41 N003 ( 0, 0) [001416] ------------ t1416 = PHI_ARG bool V55 tmp46 u:4 rsi $332 /--* t1420 bool +--* t1418 bool +--* t1416 bool N007 ( 3, 3) [001369] ------------ t1369 = * PHI bool /--* t1369 bool N009 ( 8, 7) [001370] DA---------- * STORE_LCL_VAR bool V55 tmp46 d:3 rsi N821 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 REG NA N823 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 rsi (last use) REG rsi $503 N825 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 REG NA $40 /--* t106 int +--* t107 int N827 ( 5, 4) [000108] J------N---- * EQ void REG NA $333 N829 ( 7, 6) [000109] ------------ * JTRUE void REG NA ------------ BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} N833 ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a REG NA N835 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 N837 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 REG NA $40 /--* t126 byref +--* t127 int N839 (???,???) [001476] -A-XG------- * STOREIND byte REG NA N841 ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d REG NA N843 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 REG NA $41 /--* t131 int N845 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 rax REG rax ------------ BB35 [071..078), preds={BB33} succs={BB36} N849 ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 REG NA N851 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 N853 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 REG NA $40 /--* t112 byref +--* t113 int N855 (???,???) [001477] -A-XG------- * STOREIND byte REG NA N857 ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 REG NA N859 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 REG rax $40 /--* t117 int N861 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 rax REG rax ------------ BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} N001 ( 0, 0) [001440] ------------ t1440 = PHI_ARG bool V05 loc3 u:7 rax N002 ( 0, 0) [001430] ------------ t1430 = PHI_ARG bool V05 loc3 u:6 rax $41 N003 ( 0, 0) [001422] ------------ t1422 = PHI_ARG bool V05 loc3 u:5 rax $41 N004 ( 0, 0) [001414] ------------ t1414 = PHI_ARG bool V05 loc3 u:4 rax $41 N005 ( 0, 0) [001412] ------------ t1412 = PHI_ARG bool V05 loc3 u:3 rax $40 /--* t1440 bool +--* t1430 bool +--* t1422 bool +--* t1414 bool +--* t1412 bool N011 ( 5, 5) [001365] ------------ t1365 = * PHI bool /--* t1365 bool N013 ( 5, 5) [001366] DA---------- * STORE_LCL_VAR bool V05 loc3 d:8 rax N865 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 REG NA N867 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 rax (last use) REG rax $504 /--* t122 int N869 ( 2, 2) [000123] ------------ * RETURN int REG NA $1fb ------------------------------------------------------------------------------------------------------------------- Final allocation ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | | | 0.#1 V1 Parm Alloc rdi | | | | | |V0 a|V1 a| | | | 1.#2 BB1 PredBB0 | | | | | |V0 a|V1 a| | | | 8.#3 C52 Def Alloc rbx | | | |C52 a| |V0 a|V1 a| | | | 9.#4 C52 Use * Keep rbx | | | |C52 i| |V0 a|V1 a| | | | 10.#5 V96 Def Alloc rbx | | | |V96 a| |V0 a|V1 a| | | | 13.#6 V96 Use Keep rbx | | | |V96 a| |V0 a|V1 a| | | | 19.#7 V96 Use * Keep rbx | | | |V96 i| |V0 a|V1 a| | | | 20.#8 I53 Def Alloc rbx | | | |I53 a| |V0 a|V1 a| | | | 21.#9 I53 Use * Keep rbx | | | |I53 i| |V0 a|V1 a| | | | 22.#10 V10 Def Alloc rbx | | | |V10 a| |V0 a|V1 a| | | | 26.#11 C54 Def Alloc rcx | |C54 a| |V10 a| |V0 a|V1 a| | | | 29.#12 C54 Use * Keep rcx | |C54 i| |V10 a| |V0 a|V1 a| | | | 30.#13 I55 Def Alloc rbp | | | |V10 a|I55 a|V0 a|V1 a| | | | 31.#14 I55 Use * Keep rbp | | | |V10 a|I55 i|V0 a|V1 a| | | | 32.#15 V14 Def Alloc rbp | | | |V10 a|V14 a|V0 a|V1 a| | | | 41.#16 V14 Use Keep rbp | | | |V10 a|V14 a|V0 a|V1 a| | | | 42.#17 I56 Def Alloc rcx | |I56 a| |V10 a|V14 a|V0 a|V1 a| | | | 43.#18 rcx Fixd Keep rcx | |I56 a| |V10 a|V14 a|V0 a|V1 a| | | | 43.#19 I56 Use * Keep rcx | |I56 i| |V10 a|V14 a|V0 a|V1 a| | | | 44.#20 rcx Fixd Keep rcx | | | |V10 a|V14 a|V0 a|V1 a| | | | 44.#21 I57 Def Alloc rcx | |I57 a| |V10 a|V14 a|V0 a|V1 a| | | | 45.#22 rcx Fixd Keep rcx | |I57 a| |V10 a|V14 a|V0 a|V1 a| | | | 45.#23 I57 Use * Keep rcx | |I57 i| |V10 a|V14 a|V0 a|V1 a| | | | 46.#24 rax Kill Keep rax | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#25 rcx Kill Keep rcx | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#26 rdx Kill Keep rdx | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#27 r8 Kill Keep r8 | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#28 r9 Kill Keep r9 | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#29 r10 Kill Keep r10 | | | |V10 a|V14 a|V0 a|V1 a| | | | 46.#30 r11 Kill Keep r11 | | | |V10 a|V14 a|V0 a|V1 a| | | | 51.#31 V10 Use * Keep rbx | | | |V10 i|V14 a|V0 a|V1 a| | | | 52.#32 V71 Def Alloc rbx | | | |V71 a|V14 a|V0 a|V1 a| | | | 57.#33 V71 Use * Keep rbx | | | |V71 i|V14 a|V0 a|V1 a| | | | 58.#34 V65 Def Alloc rbx | | | |V65 a|V14 a|V0 a|V1 a| | | | 63.#35 V14 Use * Keep rbp | | | |V65 a|V14 i|V0 a|V1 a| | | | 64.#36 V66 Def Alloc rbp | | | |V65 a|V66 a|V0 a|V1 a| | | | 69.#37 V65 Use * Keep rbx | | | |V65 i|V66 a|V0 a|V1 a| | | | 70.#38 V67 Def Alloc rbx | | | |V67 a|V66 a|V0 a|V1 a| | | | 73.#39 V66 Use * Keep rbp | | | |V67 a|V66 i|V0 a|V1 a| | | | 74.#40 V68 Def Alloc rbp | | | |V67 a|V68 a|V0 a|V1 a| | | | 77.#41 V67 Use * Keep rbx | | | |V67 i|V68 a|V0 a|V1 a| | | | 78.#42 V61 Def Alloc rbx | | | |V61 a|V68 a|V0 a|V1 a| | | | 81.#43 V68 Use * Keep rbp | | | |V61 a|V68 i|V0 a|V1 a| | | | 82.#44 V62 Def Alloc rbp | | | |V61 a|V62 a|V0 a|V1 a| | | | 91.#45 V0 Use Keep rsi | | | |V61 a|V62 a|V0 a|V1 a| | | | 92.#46 I58 Def Alloc rcx | |I58 a| |V61 a|V62 a|V0 a|V1 a| | | | 93.#47 I58 Use * Keep rcx | |I58 i| |V61 a|V62 a|V0 a|V1 a| | | | 94.#48 V74 Def Alloc rcx | |V74 a| |V61 a|V62 a|V0 a|V1 a| | | | 99.#49 V0 Use Keep rsi | |V74 a| |V61 a|V62 a|V0 a|V1 a| | | | 100.#50 I59 Def Alloc rdx | |V74 a|I59 a|V61 a|V62 a|V0 a|V1 a| | | | 101.#51 I59 Use * Keep rdx | |V74 a|I59 i|V61 a|V62 a|V0 a|V1 a| | | | 102.#52 V75 Def Alloc rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 109.#53 V62 Use Keep rbp | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 109.#54 V75 Use Keep rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 110.#55 I60 Def Alloc rax |I60 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 111.#56 I60 Use * Keep rax |I60 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 112.#57 V19 Def Alloc rax |V19 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 119.#58 V19 Use * Keep rax |V19 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 123.#59 BB5 PredBB1 | | | |V61 a|V62 a|V0 a|V1 a| | | | 128.#60 C61 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |C61 a| | 129.#61 C61 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |C61 i| | 130.#62 V21 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V21 a| | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 131.#63 BB6 PredBB1 | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 139.#64 V75 Use Keep rdx | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 140.#65 I62 Def Alloc rax |I62 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 141.#66 I62 Use * Keep rax |I62 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 142.#67 V20 Def Alloc rax |V20 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 149.#68 V20 Use * Keep rax |V20 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 153.#69 BB7 PredBB6 | | | |V61 a|V62 a|V0 a|V1 a| | | | 160.#70 V21 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V21 a| | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 161.#71 BB8 PredBB6 | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 166.#72 I63 Def Alloc rax |I63 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 167.#73 I63 Use * Keep rax |I63 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 168.#74 V98 Def Alloc rax |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 175.#75 V98 Use Keep rax |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 175.#76 V61 Use Keep rbx |V98 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 183.#77 V98 Use * Keep rax |V98 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 183.#78 V62 Use Keep rbp | |V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 186.#79 I64 Def Alloc rax |I64 a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 187.#80 I64 Use * Keep rax |I64 i|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 188.#81 V100 Def Alloc rax |V100a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 195.#82 V100 Use Keep rax |V100a|V74 a|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 195.#83 V74 Use * Keep rcx |V100a|V74 i|V75 a|V61 a|V62 a|V0 a|V1 a| | | | 203.#84 V100 Use * Keep rax |V100i| |V75 a|V61 a|V62 a|V0 a|V1 a| | | | 203.#85 V75 Use * Keep rdx | | |V75 i|V61 a|V62 a|V0 a|V1 a| | | | 206.#86 I65 Def Alloc rcx | |I65 a| |V61 a|V62 a|V0 a|V1 a| | | | 207.#87 rcx Fixd Keep rcx | |I65 a| |V61 a|V62 a|V0 a|V1 a| | | | 207.#88 I65 Use * Keep rcx | |I65 i| |V61 a|V62 a|V0 a|V1 a| | | | 208.#89 rcx Fixd Keep rcx | | | |V61 a|V62 a|V0 a|V1 a| | | | 208.#90 I66 Def Alloc rcx | |I66 a| |V61 a|V62 a|V0 a|V1 a| | | | 210.#91 I67 Def Alloc rdx | |I66 a|I67 a|V61 a|V62 a|V0 a|V1 a| | | | 211.#92 rdx Fixd Keep rdx | |I66 a|I67 a|V61 a|V62 a|V0 a|V1 a| | | | 211.#93 I67 Use * Keep rdx | |I66 a|I67 i|V61 a|V62 a|V0 a|V1 a| | | | 212.#94 rdx Fixd Keep rdx | |I66 a| |V61 a|V62 a|V0 a|V1 a| | | | 212.#95 I68 Def Alloc rdx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a| | | | 213.#96 rcx Fixd Keep rcx | |I66 a|I68 a|V61 a|V62 a|V0 a|V1 a| | | | 213.#97 I66 Use * Keep rcx | |I66 i|I68 a|V61 a|V62 a|V0 a|V1 a| | | | 213.#98 rdx Fixd Keep rdx | | |I68 a|V61 a|V62 a|V0 a|V1 a| | | | 213.#99 I68 Use * Keep rdx | | |I68 i|V61 a|V62 a|V0 a|V1 a| | | | 214.#100 rax Kill Keep rax | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#101 rcx Kill Keep rcx | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#102 rdx Kill Keep rdx | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#103 r8 Kill Keep r8 | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#104 r9 Kill Keep r9 | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#105 r10 Kill Keep r10 | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#106 r11 Kill Keep r11 | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#107 rax Fixd Keep rax | | | |V61 a|V62 a|V0 a|V1 a| | | | 214.#108 I69 Def Alloc rax |I69 a| | |V61 a|V62 a|V0 a|V1 a| | | | 217.#109 I69 Use * Keep rax |I69 i| | |V61 a|V62 a|V0 a|V1 a| | | | 218.#110 I70 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |I70 a| | 219.#111 I70 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |I70 i| | 220.#112 V21 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V21 a| | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 221.#113 BB9 PredBB5 | | | |V61 a|V62 a|V0 a|V1 a| |V21 a| | 229.#114 V21 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |V21 i| | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 233.#115 BB10 PredBB9 | | | | | | |V1 a| | | | 241.#116 V1 Use * Keep rdi | | | | | | |V1 i| | | | 248.#117 V5 Def Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 249.#118 BB11 PredBB9 | | | |V61 a|V62 a|V0 a|V1 a| | | | 256.#119 C71 Def Alloc rcx | |C71 a| |V61 a|V62 a|V0 a|V1 a| | | | 257.#120 C71 Use * Keep rcx | |C71 i| |V61 a|V62 a|V0 a|V1 a| | | | 258.#121 V96 Def Alloc rcx | |V96 a| |V61 a|V62 a|V0 a|V1 a| | | | 261.#122 V96 Use * Keep rcx | |V96 i| |V61 a|V62 a|V0 a|V1 a| | | | 266.#123 C72 Def Alloc rcx | |C72 a| |V61 a|V62 a|V0 a|V1 a| | | | 269.#124 C72 Use * Keep rcx | |C72 i| |V61 a|V62 a|V0 a|V1 a| | | | 270.#125 I73 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |I73 a| | 271.#126 I73 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |I73 i| | 272.#127 V30 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 281.#128 V30 Use Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 282.#129 I74 Def Alloc rcx | |I74 a| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 283.#130 rcx Fixd Keep rcx | |I74 a| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 283.#131 I74 Use * Keep rcx | |I74 i| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 284.#132 rcx Fixd Keep rcx | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 284.#133 I75 Def Alloc rcx | |I75 a| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 285.#134 rcx Fixd Keep rcx | |I75 a| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 285.#135 I75 Use * Keep rcx | |I75 i| |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#136 rax Kill Keep rax | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#137 rcx Kill Keep rcx | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#138 rdx Kill Keep rdx | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#139 r8 Kill Keep r8 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#140 r9 Kill Keep r9 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#141 r10 Kill Keep r10 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 286.#142 r11 Kill Keep r11 | | | |V61 a|V62 a|V0 a|V1 a| |V30 a| | 295.#143 V30 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |V30 i| | 296.#144 V77 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V77 a| | 301.#145 V77 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |V77 i| | 302.#146 V79 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V79 a| | 305.#147 V61 Use Keep rbx | | | |V61 a|V62 a|V0 a|V1 a| |V79 a| | 306.#148 V63 Def Alloc r15 | | | |V61 a|V62 a|V0 a|V1 a| |V79 a|V63 a| 309.#149 V79 Use * Keep r14 | | | |V61 a|V62 a|V0 a|V1 a| |V79 i|V63 a| 310.#150 V64 Def Alloc r14 | | | |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 319.#151 V0 Use Keep rsi | | | |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 320.#152 I76 Def Alloc rcx | |I76 a| |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 321.#153 I76 Use * Keep rcx | |I76 i| |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 322.#154 V85 Def Alloc rcx | |V85 a| |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 327.#155 V0 Use Keep rsi | |V85 a| |V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 328.#156 I77 Def Alloc rdx | |V85 a|I77 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 329.#157 I77 Use * Keep rdx | |V85 a|I77 i|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 330.#158 V86 Def Alloc rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 337.#159 V64 Use Keep r14 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 337.#160 V86 Use Keep rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 338.#161 I78 Def Alloc rax |I78 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 339.#162 I78 Use * Keep rax |I78 i|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 340.#163 V35 Def Alloc rax |V35 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 347.#164 V35 Use * Keep rax |V35 i|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 351.#165 BB15 PredBB11 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 356.#166 C79 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|C79 a|V64 a|V63 a| 357.#167 C79 Use * Keep r12 | | | | |V62 a|V0 a|V1 a|C79 i|V64 a|V63 a| 358.#168 V37 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 359.#169 BB16 PredBB11 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 367.#170 V86 Use Keep rdx | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 368.#171 I80 Def Alloc rax |I80 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 369.#172 I80 Use * Keep rax |I80 i|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 370.#173 V36 Def Alloc rax |V36 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 377.#174 V36 Use * Keep rax |V36 i|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 381.#175 BB17 PredBB16 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 388.#176 V37 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#177 BB18 PredBB16 | |V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 394.#178 I81 Def Alloc rax |I81 a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 395.#179 I81 Use * Keep rax |I81 i|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 396.#180 V101 Def Alloc rax |V101a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 403.#181 V101 Use Keep rax |V101a|V85 a|V86 a|V61 a|V62 a|V0 a|V1 a| |V64 a|V63 a| 403.#182 V61 Use * Keep rbx |V101a|V85 a|V86 a|V61 i|V62 a|V0 a|V1 a| |V64 a|V63 a| 411.#183 V101 Use * Keep rax |V101i|V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 411.#184 V64 Use Keep r14 | |V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 414.#185 I82 Def Alloc rax |I82 a|V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 415.#186 I82 Use * Keep rax |I82 i|V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 416.#187 V102 Def Alloc rax |V102a|V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 423.#188 V102 Use Keep rax |V102a|V85 a|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 423.#189 V85 Use * Keep rcx |V102a|V85 i|V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 431.#190 V102 Use * Keep rax |V102i| |V86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 431.#191 V86 Use * Keep rdx | | |V86 i| |V62 a|V0 a|V1 a| |V64 a|V63 a| 434.#192 I83 Def Alloc rcx | |I83 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 435.#193 rcx Fixd Keep rcx | |I83 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 435.#194 I83 Use * Keep rcx | |I83 i| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 436.#195 rcx Fixd Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 436.#196 I84 Def Alloc rcx | |I84 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 438.#197 I85 Def Alloc rdx | |I84 a|I85 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 439.#198 rdx Fixd Keep rdx | |I84 a|I85 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 439.#199 I85 Use * Keep rdx | |I84 a|I85 i| |V62 a|V0 a|V1 a| |V64 a|V63 a| 440.#200 rdx Fixd Keep rdx | |I84 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 440.#201 I86 Def Alloc rdx | |I84 a|I86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 441.#202 rcx Fixd Keep rcx | |I84 a|I86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 441.#203 I84 Use * Keep rcx | |I84 i|I86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 441.#204 rdx Fixd Keep rdx | | |I86 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 441.#205 I86 Use * Keep rdx | | |I86 i| |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#206 rax Kill Keep rax | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#207 rcx Kill Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#208 rdx Kill Keep rdx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#209 r8 Kill Keep r8 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#210 r9 Kill Keep r9 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#211 r10 Kill Keep r10 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#212 r11 Kill Keep r11 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#213 rax Fixd Keep rax | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 442.#214 I87 Def Alloc rax |I87 a| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 445.#215 I87 Use * Keep rax |I87 i| | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 446.#216 I88 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|I88 a|V64 a|V63 a| 447.#217 I88 Use * Keep r12 | | | | |V62 a|V0 a|V1 a|I88 i|V64 a|V63 a| 448.#218 V37 Def Alloc r12 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 449.#219 BB19 PredBB15 | | | | |V62 a|V0 a|V1 a|V37 a|V64 a|V63 a| 457.#220 V37 Use * Keep r12 | | | | |V62 a|V0 a|V1 a|V37 i|V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 461.#221 BB20 PredBB19 | | | | | | |V1 a| | | | 469.#222 V1 Use * Keep rdi | | | | | | |V1 i| | | | 476.#223 V5 Def Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 477.#224 BB21 PredBB19 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#225 I89 Def Alloc mm0 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#226 V0 Use Keep rsi | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 489.#227 I89 Use * Keep mm0 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 493.#228 rcx Fixd Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 493.#229 V0 Use Copy rcx | |V0 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 494.#230 rcx Fixd Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 494.#231 I90 Def Alloc rcx | |I90 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 496.#232 I91 Def Alloc rdx | |I90 a|I91 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 497.#233 rdx Fixd Keep rdx | |I90 a|I91 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 497.#234 I91 Use * Keep rdx | |I90 a|I91 i| |V62 a|V0 a|V1 a| |V64 a|V63 a| 498.#235 rdx Fixd Keep rdx | |I90 a| | |V62 a|V0 a|V1 a| |V64 a|V63 a| 498.#236 I92 Def Alloc rdx | |I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#237 rcx Fixd Keep rcx | |I90 a|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#238 I90 Use * Keep rcx | |I90 i|I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#239 rdx Fixd Keep rdx | | |I92 a| |V62 a|V0 a|V1 a| |V64 a|V63 a| 499.#240 I92 Use * Keep rdx | | |I92 i| |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#241 rax Kill Keep rax | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#242 rcx Kill Keep rcx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#243 rdx Kill Keep rdx | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#244 r8 Kill Keep r8 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#245 r9 Kill Keep r9 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#246 r10 Kill Keep r10 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 500.#247 r11 Kill Keep r11 | | | | |V62 a|V0 a|V1 a| |V64 a|V63 a| 505.#248 V62 Use * Keep rbp | | | | |V62 i|V0 a|V1 a| |V64 a|V63 a| 506.#249 V88 Def Alloc rbp | | | | |V88 a|V0 a|V1 a| |V64 a|V63 a| 513.#250 V0 Use Keep rsi | | | | |V88 a|V0 a|V1 a| |V64 a|V63 a| 514.#251 I93 Def Alloc rcx | |I93 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 515.#252 I93 Use * Keep rcx | |I93 i| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 516.#253 V89 Def Alloc rcx | |V89 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 521.#254 V0 Use Keep rsi | |V89 a| | |V88 a|V0 a|V1 a| |V64 a|V63 a| 522.#255 I94 Def Alloc rdx | |V89 a|I94 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 523.#256 I94 Use * Keep rdx | |V89 a|I94 i| |V88 a|V0 a|V1 a| |V64 a|V63 a| 524.#257 V90 Def Alloc rdx | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 531.#258 V88 Use Keep rbp | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 531.#259 V90 Use Keep rdx | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 532.#260 I95 Def Alloc rax |I95 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 533.#261 I95 Use * Keep rax |I95 i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 534.#262 V44 Def Alloc rax |V44 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 541.#263 V44 Use * Keep rax |V44 i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 545.#264 BB22 PredBB21 | | | | | |V0 a|V1 a| |V64 a|V63 a| 550.#265 C96 Def Alloc rbx | | | |C96 a| |V0 a|V1 a| |V64 a|V63 a| 551.#266 C96 Use * Keep rbx | | | |C96 i| |V0 a|V1 a| |V64 a|V63 a| 552.#267 V46 Def Alloc rbx | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 553.#268 BB23 PredBB21 | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 561.#269 V90 Use Keep rdx | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 562.#270 I97 Def Alloc rax |I97 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 563.#271 I97 Use * Keep rax |I97 i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 564.#272 V45 Def Alloc rax |V45 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 571.#273 V45 Use * Keep rax |V45 i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 575.#274 BB24 PredBB23 | | | | | |V0 a|V1 a| |V64 a|V63 a| 582.#275 V46 Def Alloc rbx | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 583.#276 BB25 PredBB23 | |V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 588.#277 I98 Def Alloc rax |I98 a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 589.#278 I98 Use * Keep rax |I98 i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 590.#279 V104 Def Alloc rax |V104a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 597.#280 V104 Use Keep rax |V104a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 597.#281 V63 Use Keep r15 |V104a|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 605.#282 V104 Use * Keep rax |V104i|V89 a|V90 a| |V88 a|V0 a|V1 a| |V64 a|V63 a| 605.#283 V88 Use * Keep rbp | |V89 a|V90 a| |V88 i|V0 a|V1 a| |V64 a|V63 a| 608.#284 I99 Def Alloc rax |I99 a|V89 a|V90 a| | |V0 a|V1 a| |V64 a|V63 a| 609.#285 I99 Use * Keep rax |I99 i|V89 a|V90 a| | |V0 a|V1 a| |V64 a|V63 a| 610.#286 V105 Def Alloc rax |V105a|V89 a|V90 a| | |V0 a|V1 a| |V64 a|V63 a| 617.#287 V105 Use Keep rax |V105a|V89 a|V90 a| | |V0 a|V1 a| |V64 a|V63 a| 617.#288 V89 Use * Keep rcx |V105a|V89 i|V90 a| | |V0 a|V1 a| |V64 a|V63 a| 625.#289 V105 Use * Keep rax |V105i| |V90 a| | |V0 a|V1 a| |V64 a|V63 a| 625.#290 V90 Use * Keep rdx | | |V90 i| | |V0 a|V1 a| |V64 a|V63 a| 628.#291 I100 Def Alloc rcx | |I100a| | | |V0 a|V1 a| |V64 a|V63 a| 629.#292 rcx Fixd Keep rcx | |I100a| | | |V0 a|V1 a| |V64 a|V63 a| 629.#293 I100 Use * Keep rcx | |I100i| | | |V0 a|V1 a| |V64 a|V63 a| 630.#294 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| |V64 a|V63 a| 630.#295 I101 Def Alloc rcx | |I101a| | | |V0 a|V1 a| |V64 a|V63 a| 632.#296 I102 Def Alloc rdx | |I101a|I102a| | |V0 a|V1 a| |V64 a|V63 a| 633.#297 rdx Fixd Keep rdx | |I101a|I102a| | |V0 a|V1 a| |V64 a|V63 a| 633.#298 I102 Use * Keep rdx | |I101a|I102i| | |V0 a|V1 a| |V64 a|V63 a| 634.#299 rdx Fixd Keep rdx | |I101a| | | |V0 a|V1 a| |V64 a|V63 a| 634.#300 I103 Def Alloc rdx | |I101a|I103a| | |V0 a|V1 a| |V64 a|V63 a| 635.#301 rcx Fixd Keep rcx | |I101a|I103a| | |V0 a|V1 a| |V64 a|V63 a| 635.#302 I101 Use * Keep rcx | |I101i|I103a| | |V0 a|V1 a| |V64 a|V63 a| 635.#303 rdx Fixd Keep rdx | | |I103a| | |V0 a|V1 a| |V64 a|V63 a| 635.#304 I103 Use * Keep rdx | | |I103i| | |V0 a|V1 a| |V64 a|V63 a| 636.#305 rax Kill Keep rax | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#306 rcx Kill Keep rcx | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#307 rdx Kill Keep rdx | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#308 r8 Kill Keep r8 | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#309 r9 Kill Keep r9 | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#310 r10 Kill Keep r10 | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#311 r11 Kill Keep r11 | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#312 rax Fixd Keep rax | | | | | |V0 a|V1 a| |V64 a|V63 a| 636.#313 I104 Def Alloc rax |I104a| | | | |V0 a|V1 a| |V64 a|V63 a| 639.#314 I104 Use * Keep rax |I104i| | | | |V0 a|V1 a| |V64 a|V63 a| 640.#315 I105 Def Alloc rbx | | | |I105a| |V0 a|V1 a| |V64 a|V63 a| 641.#316 I105 Use * Keep rbx | | | |I105i| |V0 a|V1 a| |V64 a|V63 a| 642.#317 V46 Def Alloc rbx | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 643.#318 BB26 PredBB22 | | | |V46 a| |V0 a|V1 a| |V64 a|V63 a| 651.#319 V46 Use * Keep rbx | | | |V46 i| |V0 a|V1 a| |V64 a|V63 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 655.#320 BB27 PredBB26 | | | | | | |V1 a| | | | 663.#321 V1 Use * Keep rdi | | | | | | |V1 i| | | | 670.#322 V5 Def Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 671.#323 BB28 PredBB26 | | | | | |V0 a|V1 a| |V64 a|V63 a| 677.#324 V63 Use * Keep r15 | | | | | |V0 a|V1 a| |V64 a|V63 i| 678.#325 V91 Def Alloc r15 | | | | | |V0 a|V1 a| |V64 a|V91 a| 681.#326 V64 Use * Keep r14 | | | | | |V0 a|V1 a| |V64 i|V91 a| 682.#327 V92 Def Alloc r14 | | | | | |V0 a|V1 a| |V92 a|V91 a| 689.#328 V0 Use Keep rsi | | | | | |V0 a|V1 a| |V92 a|V91 a| 690.#329 I106 Def Alloc rcx | |I106a| | | |V0 a|V1 a| |V92 a|V91 a| 691.#330 I106 Use * Keep rcx | |I106i| | | |V0 a|V1 a| |V92 a|V91 a| 692.#331 V93 Def Alloc rcx | |V93 a| | | |V0 a|V1 a| |V92 a|V91 a| 697.#332 V0 Use * Keep rsi | |V93 a| | | |V0 i|V1 a| |V92 a|V91 a| 698.#333 I107 Def Alloc rdx | |V93 a|I107a| | | |V1 a| |V92 a|V91 a| 699.#334 I107 Use * Keep rdx | |V93 a|I107i| | | |V1 a| |V92 a|V91 a| 700.#335 V94 Def Alloc rdx | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 707.#336 V92 Use Keep r14 | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 707.#337 V94 Use Keep rdx | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 708.#338 I108 Def Alloc rax |I108a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 709.#339 I108 Use * Keep rax |I108i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 710.#340 V53 Def Alloc rax |V53 a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 717.#341 V53 Use * Keep rax |V53 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 721.#342 BB29 PredBB28 | | | | | | |V1 a| | | | 726.#343 C109 Def Alloc rsi | | | | | |C109a|V1 a| | | | 727.#344 C109 Use * Keep rsi | | | | | |C109i|V1 a| | | | 728.#345 V55 Def Alloc rsi | | | | | |V55 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 729.#346 BB30 PredBB28 | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 737.#347 V94 Use Keep rdx | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 738.#348 I110 Def Alloc rax |I110a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 739.#349 I110 Use * Keep rax |I110i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 740.#350 V54 Def Alloc rax |V54 a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 747.#351 V54 Use * Keep rax |V54 i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 751.#352 BB31 PredBB30 | | | | | | |V1 a| | | | 758.#353 V55 Def Alloc rsi | | | | | |V55 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 759.#354 BB32 PredBB30 | |V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 764.#355 I111 Def Alloc rax |I111a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 765.#356 I111 Use * Keep rax |I111i|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 766.#357 V106 Def Alloc rax |V106a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 773.#358 V106 Use Keep rax |V106a|V93 a|V94 a| | | |V1 a| |V92 a|V91 a| 773.#359 V91 Use * Keep r15 |V106a|V93 a|V94 a| | | |V1 a| |V92 a|V91 i| 781.#360 V106 Use * Keep rax |V106i|V93 a|V94 a| | | |V1 a| |V92 a| | 781.#361 V92 Use * Keep r14 | |V93 a|V94 a| | | |V1 a| |V92 i| | 784.#362 I112 Def Alloc rax |I112a|V93 a|V94 a| | | |V1 a| | | | 785.#363 I112 Use * Keep rax |I112i|V93 a|V94 a| | | |V1 a| | | | 786.#364 V107 Def Alloc rax |V107a|V93 a|V94 a| | | |V1 a| | | | 793.#365 V107 Use Keep rax |V107a|V93 a|V94 a| | | |V1 a| | | | 793.#366 V93 Use * Keep rcx |V107a|V93 i|V94 a| | | |V1 a| | | | 801.#367 V107 Use * Keep rax |V107i| |V94 a| | | |V1 a| | | | 801.#368 V94 Use * Keep rdx | | |V94 i| | | |V1 a| | | | 804.#369 I113 Def Alloc rcx | |I113a| | | | |V1 a| | | | 805.#370 rcx Fixd Keep rcx | |I113a| | | | |V1 a| | | | 805.#371 I113 Use * Keep rcx | |I113i| | | | |V1 a| | | | 806.#372 rcx Fixd Keep rcx | | | | | | |V1 a| | | | 806.#373 I114 Def Alloc rcx | |I114a| | | | |V1 a| | | | 808.#374 I115 Def Alloc rdx | |I114a|I115a| | | |V1 a| | | | 809.#375 rdx Fixd Keep rdx | |I114a|I115a| | | |V1 a| | | | 809.#376 I115 Use * Keep rdx | |I114a|I115i| | | |V1 a| | | | 810.#377 rdx Fixd Keep rdx | |I114a| | | | |V1 a| | | | 810.#378 I116 Def Alloc rdx | |I114a|I116a| | | |V1 a| | | | 811.#379 rcx Fixd Keep rcx | |I114a|I116a| | | |V1 a| | | | 811.#380 I114 Use * Keep rcx | |I114i|I116a| | | |V1 a| | | | 811.#381 rdx Fixd Keep rdx | | |I116a| | | |V1 a| | | | 811.#382 I116 Use * Keep rdx | | |I116i| | | |V1 a| | | | 812.#383 rax Kill Keep rax | | | | | | |V1 a| | | | 812.#384 rcx Kill Keep rcx | | | | | | |V1 a| | | | 812.#385 rdx Kill Keep rdx | | | | | | |V1 a| | | | 812.#386 r8 Kill Keep r8 | | | | | | |V1 a| | | | 812.#387 r9 Kill Keep r9 | | | | | | |V1 a| | | | 812.#388 r10 Kill Keep r10 | | | | | | |V1 a| | | | 812.#389 r11 Kill Keep r11 | | | | | | |V1 a| | | | 812.#390 rax Fixd Keep rax | | | | | | |V1 a| | | | 812.#391 I117 Def Alloc rax |I117a| | | | | |V1 a| | | | 815.#392 I117 Use * Keep rax |I117i| | | | | |V1 a| | | | 816.#393 I118 Def Alloc rsi | | | | | |I118a|V1 a| | | | 817.#394 I118 Use * Keep rsi | | | | | |I118i|V1 a| | | | 818.#395 V55 Def Alloc rsi | | | | | |V55 a|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 819.#396 BB33 PredBB29 | | | | | |V55 a|V1 a| | | | 827.#397 V55 Use * Keep rsi | | | | | |V55 i|V1 a| | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 831.#398 BB34 PredBB33 | | | | | | |V1 a| | | | 839.#399 V1 Use * Keep rdi | | | | | | |V1 i| | | | 846.#400 V5 Def Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 847.#401 BB35 PredBB33 | | | | | | |V1 a| | | | 855.#402 V1 Use * Keep rdi | | | | | | |V1 i| | | | 860.#403 C119 Def Alloc rax |C119a| | | | | | | | | | 861.#404 C119 Use * Keep rax |C119i| | | | | | | | | | 862.#405 V5 Def Alloc rax |V5 a| | | | | | | | | | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r12 |r14 |r15 | ---------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 863.#406 BB36 PredBB10 |V5 a| | | | | | | | | | 869.#407 rax Fixd Keep rax |V5 a| | | | | | | | | | 869.#408 V5 Use * Keep rax |V5 i| | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 61 Total Reg Cand Vars: 52 Total number of Intervals: 119 Total number of RefPositions: 408 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rcx=>rsi) V01(rdx=>rdi) BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} ===== N003. IL_OFFSET IL offset: 0x1 REG NA N005. IL_OFFSET IL offset: 0x1 REG NA N007. rbx = CNS_INT(h) 0x421150 [ICON_STR_HDL] REG rbx * N009. V96(rbx); rbx N011. V96(rbx) N013. NULLCHECK; rbx N015. V96(rbx*) N017. CNS_INT 12 field offset Fseq[_firstChar] REG NA N019. rbx = ADD ; rbx* * N021. V10(rbx); rbx N023. IL_OFFSET IL offset: 0x1 REG NA N025. rcx = CNS_INT(h) 0x421150 [ICON_STR_HDL] REG rcx N027. STK = LEA(b+8) ; rcx N029. rbp = IND ; STK * N031. V14(rbp); rbp N033. IL_OFFSET IL offset: 0x1 REG NA N035. IL_OFFSET IL offset: 0x1 REG NA N037. V14(rbp) N039. CNS_INT 0 REG NA N041. rcx = GE ; rbp N043. rcx = PUTARG_REG; rcx N045. CALL ; rcx N047. IL_OFFSET IL offset: 0x1 REG NA N049. V10(rbx*) * N051. V71(rbx); rbx* N053. IL_OFFSET IL offset: 0x1 REG NA N055. V71(rbx*) * N057. V65(rbx); rbx* N059. IL_OFFSET IL offset: 0x1 REG NA N061. V14(rbp*) * N063. V66(rbp); rbp* N065. IL_OFFSET IL offset: 0x1 REG NA N067. V65(rbx*) * N069. V67(rbx); rbx* N071. V66(rbp*) * N073. V68(rbp); rbp* N075. V67(rbx*) * N077. V61(rbx); rbx* N079. V68(rbp*) * N081. V62(rbp); rbp* N083. IL_OFFSET IL offset: 0xc REG NA N085. IL_OFFSET IL offset: 0xc REG NA N087. V00(rsi) N089. STK = LEA(b+0) ; rsi N091. rcx = IND ; STK * N093. V74(rcx); rcx N095. V00(rsi) N097. STK = LEA(b+8) ; rsi N099. rdx = IND ; STK * N101. V75(rdx); rdx N103. IL_OFFSET IL offset: 0xc REG NA N105. V62(rbp) N107. V75(rdx) N109. rax = NE ; rbp,rdx * N111. V19(rax); rax N113. IL_OFFSET IL offset: 0xc REG NA N115. V19(rax*) N117. CNS_INT 0 REG NA N119. EQ ; rax* N121. JTRUE Var=Reg end of BB01: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB05: V00=rsi V01=rdi V61=rbx V62=rbp N125. IL_OFFSET IL offset: 0xc REG NA N127. r14 = CNS_INT 0 REG r14 * N129. V21(r14); r14 Var=Reg end of BB05: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB06: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx N133. IL_OFFSET IL offset: 0xc REG NA N135. V75(rdx) N137. CNS_INT 0 REG NA N139. rax = EQ ; rdx * N141. V20(rax); rax N143. IL_OFFSET IL offset: 0xc REG NA N145. V20(rax*) N147. CNS_INT 0 REG NA N149. EQ ; rax* N151. JTRUE Var=Reg end of BB06: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V00=rsi V01=rdi V61=rbx V62=rbp N155. IL_OFFSET IL offset: 0xc REG NA N157. CNS_INT 1 REG NA * N159. V21(r14) Var=Reg end of BB07: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB08 [00C..00D), preds={BB06} succs={BB09} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB08: V00=rsi V01=rdi V61=rbx V62=rbp V75=rdx V74=rcx N163. IL_OFFSET IL offset: 0xc REG NA N165. rax = LCL_VAR_ADDR V97 tmp88 rax REG rax * N167. V98(rax); rax N169. V98(rax) N171. STK = LEA(b+0) ; rax N173. V61(rbx) N175. STOREIND ; STK,rbx N177. V98(rax*) N179. STK = LEA(b+8) ; rax* N181. V62(rbp) N183. STOREIND ; STK,rbp N185. rax = LCL_VAR_ADDR V99 tmp90 rax REG rax * N187. V100(rax); rax N189. V100(rax) N191. STK = LEA(b+0) ; rax N193. V74(rcx*) N195. STOREIND ; STK,rcx* N197. V100(rax*) N199. STK = LEA(b+8) ; rax* N201. V75(rdx*) N203. STOREIND ; STK,rdx* N205. rcx = LCL_VAR_ADDR V97 tmp88 rcx REG rcx N207. rcx = PUTARG_REG; rcx N209. rdx = LCL_VAR_ADDR V99 tmp90 rdx REG rdx N211. rdx = PUTARG_REG; rdx N213. rax = CALL ; rcx,rdx N215. CNS_INT 0 REG NA N217. r14 = EQ ; rax * N219. V21(r14); r14 Var=Reg end of BB08: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB09: V00=rsi V01=rdi V61=rbx V62=rbp V21=r14 N223. IL_OFFSET IL offset: 0x14 REG NA N225. V21(r14*) N227. CNS_INT 0 REG NA N229. EQ ; r14* N231. JTRUE Var=Reg end of BB09: V00=rsi V01=rdi V61=rbx V62=rbp BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB10: V01=rdi N235. IL_OFFSET IL offset: 0x18 REG NA N237. V01(rdi*) N239. CNS_INT 1 REG NA N241. STOREIND ; rdi* N243. IL_OFFSET IL offset: 0x1b REG NA N245. CNS_INT 1 REG NA * N247. V05(rax) Var=Reg end of BB10: V05=rax BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB11: V00=rsi V01=rdi V61=rbx V62=rbp N251. IL_OFFSET IL offset: 0x1f REG NA N253. IL_OFFSET IL offset: 0x1f REG NA N255. rcx = CNS_INT(h) 0x421158 [ICON_STR_HDL] REG rcx * N257. V96(rcx); rcx N259. V96(rcx*) N261. NULLCHECK; rcx* N263. IL_OFFSET IL offset: 0x1f REG NA N265. rcx = CNS_INT(h) 0x421158 [ICON_STR_HDL] REG rcx N267. STK = LEA(b+8) ; rcx N269. r14 = IND ; STK * N271. V30(r14); r14 N273. IL_OFFSET IL offset: 0x1f REG NA N275. IL_OFFSET IL offset: 0x1f REG NA N277. V30(r14) N279. CNS_INT 0 REG NA N281. rcx = GE ; r14 N283. rcx = PUTARG_REG; rcx N285. CALL ; rcx N287. IL_OFFSET IL offset: 0x1f REG NA N289. IL_OFFSET IL offset: 0x1f REG NA N291. IL_OFFSET IL offset: 0x1f REG NA N293. V30(r14*) * N295. V77(r14); r14* N297. IL_OFFSET IL offset: 0x1f REG NA N299. V77(r14*) * N301. V79(r14); r14* N303. V61(rbx) * N305. V63(r15); rbx N307. V79(r14*) * N309. V64(r14); r14* N311. IL_OFFSET IL offset: 0x2a REG NA N313. IL_OFFSET IL offset: 0x2a REG NA N315. V00(rsi) N317. STK = LEA(b+0) ; rsi N319. rcx = IND ; STK * N321. V85(rcx); rcx N323. V00(rsi) N325. STK = LEA(b+8) ; rsi N327. rdx = IND ; STK * N329. V86(rdx); rdx N331. IL_OFFSET IL offset: 0x2a REG NA N333. V64(r14) N335. V86(rdx) N337. rax = NE ; r14,rdx * N339. V35(rax); rax N341. IL_OFFSET IL offset: 0x2a REG NA N343. V35(rax*) N345. CNS_INT 0 REG NA N347. EQ ; rax* N349. JTRUE Var=Reg end of BB11: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB15: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 N353. IL_OFFSET IL offset: 0x2a REG NA N355. r12 = CNS_INT 0 REG r12 * N357. V37(r12); r12 Var=Reg end of BB15: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB16: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx N361. IL_OFFSET IL offset: 0x2a REG NA N363. V86(rdx) N365. CNS_INT 0 REG NA N367. rax = EQ ; rdx * N369. V36(rax); rax N371. IL_OFFSET IL offset: 0x2a REG NA N373. V36(rax*) N375. CNS_INT 0 REG NA N377. EQ ; rax* N379. JTRUE Var=Reg end of BB16: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} ===== Predecessor for variable locations: BB16 Var=Reg beg of BB17: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 N383. IL_OFFSET IL offset: 0x2a REG NA N385. CNS_INT 1 REG NA * N387. V37(r12) Var=Reg end of BB17: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB18 [02A..02B), preds={BB16} succs={BB19} ===== Predecessor for variable locations: BB16 Var=Reg beg of BB18: V00=rsi V01=rdi V61=rbx V62=rbp V64=r14 V63=r15 V86=rdx V85=rcx N391. IL_OFFSET IL offset: 0x2a REG NA N393. rax = LCL_VAR_ADDR V97 tmp88 rax REG rax * N395. V101(rax); rax N397. V101(rax) N399. STK = LEA(b+0) ; rax N401. V61(rbx*) N403. STOREIND ; STK,rbx* N405. V101(rax*) N407. STK = LEA(b+8) ; rax* N409. V64(r14) N411. STOREIND ; STK,r14 N413. rax = LCL_VAR_ADDR V99 tmp90 rax REG rax * N415. V102(rax); rax N417. V102(rax) N419. STK = LEA(b+0) ; rax N421. V85(rcx*) N423. STOREIND ; STK,rcx* N425. V102(rax*) N427. STK = LEA(b+8) ; rax* N429. V86(rdx*) N431. STOREIND ; STK,rdx* N433. rcx = LCL_VAR_ADDR V97 tmp88 rcx REG rcx N435. rcx = PUTARG_REG; rcx N437. rdx = LCL_VAR_ADDR V99 tmp90 rdx REG rdx N439. rdx = PUTARG_REG; rdx N441. rax = CALL ; rcx,rdx N443. CNS_INT 0 REG NA N445. r12 = EQ ; rax * N447. V37(r12); r12 Var=Reg end of BB18: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} ===== Predecessor for variable locations: BB15 Var=Reg beg of BB19: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 V37=r12 N451. IL_OFFSET IL offset: 0x33 REG NA N453. V37(r12*) N455. CNS_INT 0 REG NA N457. EQ ; r12* N459. JTRUE Var=Reg end of BB19: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB20: V01=rdi N463. IL_OFFSET IL offset: 0x38 REG NA N465. V01(rdi*) N467. CNS_INT 0 REG NA N469. STOREIND ; rdi* N471. IL_OFFSET IL offset: 0x3b REG NA N473. CNS_INT 1 REG NA * N475. V05(rax) Var=Reg end of BB20: V05=rax BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB21: V00=rsi V01=rdi V62=rbp V64=r14 V63=r15 N479. IL_OFFSET IL offset: 0x3f REG NA N481. NOP N483. V00(rsi) N485. STK = IND ; rsi N487. LCL_VAR_ADDR V97 tmp88 NA REG NA N489. STORE_BLK(16); STK N491. V00(rsi) N493. rcx = PUTARG_REG; rsi N495. rdx = LCL_VAR_ADDR V97 tmp88 rdx REG rdx N497. rdx = PUTARG_REG; rdx N499. CALL ; rcx,rdx N501. IL_OFFSET IL offset: 0x47 REG NA N503. V62(rbp*) * N505. V88(rbp); rbp* N507. IL_OFFSET IL offset: 0x47 REG NA N509. V00(rsi) N511. STK = LEA(b+0) ; rsi N513. rcx = IND ; STK * N515. V89(rcx); rcx N517. V00(rsi) N519. STK = LEA(b+8) ; rsi N521. rdx = IND ; STK * N523. V90(rdx); rdx N525. IL_OFFSET IL offset: 0x47 REG NA N527. V88(rbp) N529. V90(rdx) N531. rax = NE ; rbp,rdx * N533. V44(rax); rax N535. IL_OFFSET IL offset: 0x47 REG NA N537. V44(rax*) N539. CNS_INT 0 REG NA N541. EQ ; rax* N543. JTRUE Var=Reg end of BB21: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} ===== Predecessor for variable locations: BB21 Var=Reg beg of BB22: V00=rsi V01=rdi V64=r14 V63=r15 N547. IL_OFFSET IL offset: 0x47 REG NA N549. rbx = CNS_INT 0 REG rbx * N551. V46(rbx); rbx Var=Reg end of BB22: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ===== Predecessor for variable locations: BB21 Var=Reg beg of BB23: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx N555. IL_OFFSET IL offset: 0x47 REG NA N557. V90(rdx) N559. CNS_INT 0 REG NA N561. rax = EQ ; rdx * N563. V45(rax); rax N565. IL_OFFSET IL offset: 0x47 REG NA N567. V45(rax*) N569. CNS_INT 0 REG NA N571. EQ ; rax* N573. JTRUE Var=Reg end of BB23: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB24: V00=rsi V01=rdi V64=r14 V63=r15 N577. IL_OFFSET IL offset: 0x47 REG NA N579. CNS_INT 1 REG NA * N581. V46(rbx) Var=Reg end of BB24: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB25 [047..048), preds={BB23} succs={BB26} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB25: V00=rsi V01=rdi V64=r14 V63=r15 V90=rdx V88=rbp V89=rcx N585. IL_OFFSET IL offset: 0x47 REG NA N587. rax = LCL_VAR_ADDR V97 tmp88 rax REG rax * N589. V104(rax); rax N591. V104(rax) N593. STK = LEA(b+0) ; rax N595. V63(r15) N597. STOREIND ; STK,r15 N599. V104(rax*) N601. STK = LEA(b+8) ; rax* N603. V88(rbp*) N605. STOREIND ; STK,rbp* N607. rax = LCL_VAR_ADDR V99 tmp90 rax REG rax * N609. V105(rax); rax N611. V105(rax) N613. STK = LEA(b+0) ; rax N615. V89(rcx*) N617. STOREIND ; STK,rcx* N619. V105(rax*) N621. STK = LEA(b+8) ; rax* N623. V90(rdx*) N625. STOREIND ; STK,rdx* N627. rcx = LCL_VAR_ADDR V97 tmp88 rcx REG rcx N629. rcx = PUTARG_REG; rcx N631. rdx = LCL_VAR_ADDR V99 tmp90 rdx REG rdx N633. rdx = PUTARG_REG; rdx N635. rax = CALL ; rcx,rdx N637. CNS_INT 0 REG NA N639. rbx = EQ ; rax * N641. V46(rbx); rbx Var=Reg end of BB25: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} ===== Predecessor for variable locations: BB22 Var=Reg beg of BB26: V00=rsi V01=rdi V64=r14 V63=r15 V46=rbx N645. IL_OFFSET IL offset: 0x50 REG NA N647. V46(rbx*) N649. CNS_INT 0 REG NA N651. EQ ; rbx* N653. JTRUE Var=Reg end of BB26: V00=rsi V01=rdi V64=r14 V63=r15 BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB27: V01=rdi N657. IL_OFFSET IL offset: 0x55 REG NA N659. V01(rdi*) N661. CNS_INT 1 REG NA N663. STOREIND ; rdi* N665. IL_OFFSET IL offset: 0x58 REG NA N667. CNS_INT 1 REG NA * N669. V05(rax) Var=Reg end of BB27: V05=rax BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB28: V00=rsi V01=rdi V64=r14 V63=r15 N673. IL_OFFSET IL offset: 0x5c REG NA N675. V63(r15*) * N677. V91(r15); r15* N679. V64(r14*) * N681. V92(r14); r14* N683. IL_OFFSET IL offset: 0x5c REG NA N685. V00(rsi) N687. STK = LEA(b+0) ; rsi N689. rcx = IND ; STK * N691. V93(rcx); rcx N693. V00(rsi*) N695. STK = LEA(b+8) ; rsi* N697. rdx = IND ; STK * N699. V94(rdx); rdx N701. IL_OFFSET IL offset: 0x5c REG NA N703. V92(r14) N705. V94(rdx) N707. rax = NE ; r14,rdx * N709. V53(rax); rax N711. IL_OFFSET IL offset: 0x5c REG NA N713. V53(rax*) N715. CNS_INT 0 REG NA N717. EQ ; rax* N719. JTRUE Var=Reg end of BB28: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB29: V01=rdi N723. IL_OFFSET IL offset: 0x5c REG NA N725. rsi = CNS_INT 0 REG rsi * N727. V55(rsi); rsi Var=Reg end of BB29: V01=rdi V55=rsi BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB30: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx N731. IL_OFFSET IL offset: 0x5c REG NA N733. V94(rdx) N735. CNS_INT 0 REG NA N737. rax = EQ ; rdx * N739. V54(rax); rax N741. IL_OFFSET IL offset: 0x5c REG NA N743. V54(rax*) N745. CNS_INT 0 REG NA N747. EQ ; rax* N749. JTRUE Var=Reg end of BB30: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} ===== Predecessor for variable locations: BB30 Var=Reg beg of BB31: V01=rdi N753. IL_OFFSET IL offset: 0x5c REG NA N755. CNS_INT 1 REG NA * N757. V55(rsi) Var=Reg end of BB31: V01=rdi V55=rsi BB32 [05C..05D), preds={BB30} succs={BB33} ===== Predecessor for variable locations: BB30 Var=Reg beg of BB32: V01=rdi V94=rdx V92=r14 V91=r15 V93=rcx N761. IL_OFFSET IL offset: 0x5c REG NA N763. rax = LCL_VAR_ADDR V97 tmp88 rax REG rax * N765. V106(rax); rax N767. V106(rax) N769. STK = LEA(b+0) ; rax N771. V91(r15*) N773. STOREIND ; STK,r15* N775. V106(rax*) N777. STK = LEA(b+8) ; rax* N779. V92(r14*) N781. STOREIND ; STK,r14* N783. rax = LCL_VAR_ADDR V99 tmp90 rax REG rax * N785. V107(rax); rax N787. V107(rax) N789. STK = LEA(b+0) ; rax N791. V93(rcx*) N793. STOREIND ; STK,rcx* N795. V107(rax*) N797. STK = LEA(b+8) ; rax* N799. V94(rdx*) N801. STOREIND ; STK,rdx* N803. rcx = LCL_VAR_ADDR V97 tmp88 rcx REG rcx N805. rcx = PUTARG_REG; rcx N807. rdx = LCL_VAR_ADDR V99 tmp90 rdx REG rdx N809. rdx = PUTARG_REG; rdx N811. rax = CALL ; rcx,rdx N813. CNS_INT 0 REG NA N815. rsi = EQ ; rax * N817. V55(rsi); rsi Var=Reg end of BB32: V01=rdi V55=rsi BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} ===== Predecessor for variable locations: BB29 Var=Reg beg of BB33: V01=rdi V55=rsi N821. IL_OFFSET IL offset: 0x65 REG NA N823. V55(rsi*) N825. CNS_INT 0 REG NA N827. EQ ; rsi* N829. JTRUE Var=Reg end of BB33: V01=rdi BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} ===== Predecessor for variable locations: BB33 Var=Reg beg of BB34: V01=rdi N833. IL_OFFSET IL offset: 0x6a REG NA N835. V01(rdi*) N837. CNS_INT 0 REG NA N839. STOREIND ; rdi* N841. IL_OFFSET IL offset: 0x6d REG NA N843. CNS_INT 1 REG NA * N845. V05(rax) Var=Reg end of BB34: V05=rax BB35 [071..078), preds={BB33} succs={BB36} ===== Predecessor for variable locations: BB33 Var=Reg beg of BB35: V01=rdi N849. IL_OFFSET IL offset: 0x71 REG NA N851. V01(rdi*) N853. CNS_INT 0 REG NA N855. STOREIND ; rdi* N857. IL_OFFSET IL offset: 0x74 REG NA N859. rax = CNS_INT 0 REG rax * N861. V05(rax); rax Var=Reg end of BB35: V05=rax BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB36: V05=rax N865. IL_OFFSET IL offset: 0x78 REG NA N867. V05(rax*) N869. RETURN ; rax* Var=Reg end of BB36: none *************** In genGenerateCode() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB06 ( cond ) i label target gcsafe LIR BB05 [0019] 1 BB01 0.25 [00C..00D)-> BB09 (always) i LIR BB06 [0020] 1 BB01 0.25 [00C..00D)-> BB08 ( cond ) i label target LIR BB07 [0021] 1 BB06 0.25 [00C..00D)-> BB09 (always) i LIR BB08 [0022] 1 BB06 0.25 [00C..00D) i label target gcsafe LIR BB09 [0023] 3 BB05,BB07,BB08 1 [00C..00D)-> BB11 ( cond ) i label target LIR BB10 [0001] 1 BB09 0.50 [017..01F)-> BB36 (always) i LIR BB11 [0002] 1 BB09 0.50 [01F..037)-> BB16 ( cond ) i label target gcsafe LIR BB15 [0037] 1 BB11 0.25 [02A..02B)-> BB19 (always) i LIR BB16 [0038] 1 BB11 0.25 [02A..02B)-> BB18 ( cond ) i label target LIR BB17 [0039] 1 BB16 0.25 [02A..02B)-> BB19 (always) i LIR BB18 [0040] 1 BB16 0.25 [02A..02B) i label target gcsafe LIR BB19 [0041] 3 BB15,BB17,BB18 0.50 [02A..02B)-> BB21 ( cond ) i label target LIR BB20 [0003] 1 BB19 0.50 [037..03F)-> BB36 (always) i LIR BB21 [0004] 1 BB19 0.50 [03F..054)-> BB23 ( cond ) i label target gcsafe LIR BB22 [0047] 1 BB21 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB23 [0048] 1 BB21 0.25 [047..048)-> BB25 ( cond ) i label target gcsafe LIR BB24 [0049] 1 BB23 0.25 [047..048)-> BB26 (always) i gcsafe LIR BB25 [0050] 1 BB23 0.25 [047..048) i label target gcsafe LIR BB26 [0051] 3 BB22,BB24,BB25 0.50 [047..048)-> BB28 ( cond ) i label target gcsafe LIR BB27 [0005] 1 BB26 0.50 [054..05C)-> BB36 (always) i gcsafe LIR BB28 [0006] 1 BB26 0.50 [05C..069)-> BB30 ( cond ) i label target gcsafe LIR BB29 [0057] 1 BB28 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB30 [0058] 1 BB28 0.25 [05C..05D)-> BB32 ( cond ) i label target gcsafe LIR BB31 [0059] 1 BB30 0.25 [05C..05D)-> BB33 (always) i gcsafe LIR BB32 [0060] 1 BB30 0.25 [05C..05D) i label target gcsafe LIR BB33 [0061] 3 BB29,BB31,BB32 0.50 [05C..05D)-> BB35 ( cond ) i label target gcsafe LIR BB34 [0007] 1 BB33 0.50 [069..071)-> BB36 (always) i gcsafe LIR BB35 [0008] 1 BB33 0.50 [071..078) i label target gcsafe LIR BB36 [0009] 5 BB10,BB20,BB27,BB34,BB35 1 [078..07A) (return) i label target LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rsi) V01(rdi) Modified regs: [rax rcx rdx rbx rbp rsi rdi r8-r12 r14-r15 mm0] Callee-saved registers pushed: 7 [rbx rbp rsi rdi r12 r14-r15] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V09 tmp0, size=4, stkOffs=-0x44 Assign V25 tmp16, size=4, stkOffs=-0x48 Assign V97 tmp88, size=16, stkOffs=-0x58 Assign V99 tmp90, size=16, stkOffs=-0x68 Assign V26 tmp17, size=8, stkOffs=-0x70 Assign V108 OutArgs, size=32, stkOffs=-0x90 ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 12, 16 ) byref -> rsi ; V01 arg1 [V01,T01] ( 7, 4.50) byref -> rdi ;* V02 loc0 [V02 ] ( 0, 0 ) struct (16) zero-ref ;* V03 loc1 [V03 ] ( 0, 0 ) struct (16) zero-ref ;* V04 loc2 [V04 ] ( 0, 0 ) bool -> zero-ref ; V05 loc3 [V05,T04] ( 6, 3.50) bool -> rax ;* V06 loc4 [V06 ] ( 0, 0 ) bool -> zero-ref ;* V07 loc5 [V07 ] ( 0, 0 ) bool -> zero-ref ;* V08 loc6 [V08 ] ( 0, 0 ) bool -> zero-ref ; V09 tmp0 [V09,T08] ( 1, 1 ) bool -> [rsp+0x4C] ; V10 tmp1 [V10,T15] ( 3, 1.50) byref -> rbx ;* V11 tmp2 [V11 ] ( 0, 0 ) struct (16) zero-ref ;* V12 tmp3 [V12 ] ( 0, 0 ) struct (16) zero-ref ;* V13 tmp4 [V13 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V14 tmp5 [V14,T40] ( 3, 0.75) int -> rbp ;* V15 tmp6 [V15 ] ( 0, 0 ) struct ( 8) zero-ref ;* V16 tmp7 [V16 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V17 tmp8 [V17 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref ; V19 tmp10 [V19,T09] ( 2, 2 ) bool -> rax ; V20 tmp11 [V20,T49] ( 2, 0.50) bool -> rax ; V21 tmp12 [V21,T11] ( 4, 1.75) bool -> r14 ;* V22 tmp13 [V22 ] ( 0, 0 ) int -> zero-ref ;* V23 tmp14 [V23 ] ( 0, 0 ) int -> zero-ref ;* V24 tmp15 [V24 ] ( 0, 0 ) int -> zero-ref ; V25 tmp16 [V25,T33] ( 1, 0.50) bool -> [rsp+0x48] ; V26 tmp17 [V26,T32] ( 1, 0 ) byref -> [rsp+0x20] ;* V27 tmp18 [V27 ] ( 0, 0 ) struct (16) zero-ref ;* V28 tmp19 [V28 ] ( 0, 0 ) struct (16) zero-ref ;* V29 tmp20 [V29 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V30 tmp21 [V30,T41] ( 3, 0.75) int -> r14 ;* V31 tmp22 [V31 ] ( 0, 0 ) struct ( 8) zero-ref ;* V32 tmp23 [V32 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V33 tmp24 [V33 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V34 tmp25 [V34 ] ( 0, 0 ) int -> zero-ref ; V35 tmp26 [V35,T34] ( 2, 1 ) bool -> rax ; V36 tmp27 [V36,T50] ( 2, 0.50) bool -> rax ; V37 tmp28 [V37,T24] ( 4, 1.25) bool -> r12 ;* V38 tmp29 [V38 ] ( 0, 0 ) int -> zero-ref ;* V39 tmp30 [V39 ] ( 0, 0 ) int -> zero-ref ;* V40 tmp31 [V40 ] ( 0, 0 ) int -> zero-ref ;* V41 tmp32 [V41 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V42 tmp33 [V42 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V43 tmp34 [V43 ] ( 0, 0 ) int -> zero-ref ; V44 tmp35 [V44,T35] ( 2, 1 ) bool -> rax ; V45 tmp36 [V45,T51] ( 2, 0.50) bool -> rax ; V46 tmp37 [V46,T25] ( 4, 1.25) bool -> rbx ;* V47 tmp38 [V47 ] ( 0, 0 ) int -> zero-ref ;* V48 tmp39 [V48 ] ( 0, 0 ) int -> zero-ref ;* V49 tmp40 [V49 ] ( 0, 0 ) int -> zero-ref ;* V50 tmp41 [V50 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V51 tmp42 [V51 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V52 tmp43 [V52 ] ( 0, 0 ) int -> zero-ref ; V53 tmp44 [V53,T36] ( 2, 1 ) bool -> rax ; V54 tmp45 [V54,T52] ( 2, 0.50) bool -> rax ; V55 tmp46 [V55,T26] ( 4, 1.25) bool -> rsi ;* V56 tmp47 [V56 ] ( 0, 0 ) int -> zero-ref ;* V57 tmp48 [V57 ] ( 0, 0 ) int -> zero-ref ;* V58 tmp49 [V58 ] ( 0, 0 ) int -> zero-ref ;* V59 tmp50 [V59 ] ( 0, 0 ) byref -> zero-ref do-not-enreg[] V95._pointer(offs=0x00) P-DEP ;* V60 tmp51 [V60 ] ( 0, 0 ) int -> zero-ref do-not-enreg[] V95._length(offs=0x08) P-DEP ; V61 tmp52 [V61,T02] ( 4, 1.25) byref -> rbx V02._pointer(offs=0x00) P-INDEP ; V62 tmp53 [V62,T03] ( 4, 2.75) int -> rbp V02._length(offs=0x08) P-INDEP ; V63 tmp54 [V63,T10] ( 3, 1.25) byref -> r15 V03._pointer(offs=0x00) P-INDEP ; V64 tmp55 [V64,T07] ( 4, 1.75) int -> r14 V03._length(offs=0x08) P-INDEP ; V65 tmp56 [V65,T47] ( 2, 0.50) byref -> rbx V11._pointer(offs=0x00) P-INDEP ; V66 tmp57 [V66,T53] ( 2, 0.50) int -> rbp V11._length(offs=0x08) P-INDEP ; V67 tmp58 [V67,T29] ( 2, 1.25) byref -> rbx V12._pointer(offs=0x00) P-INDEP ; V68 tmp59 [V68,T31] ( 2, 1.25) int -> rbp V12._length(offs=0x08) P-INDEP ;* V69 tmp60 [V69 ] ( 0, 0 ) byref -> zero-ref V13._pointer(offs=0x00) P-INDEP ;* V70 tmp61 [V70 ] ( 0, 0 ) int -> zero-ref V13._length(offs=0x08) P-INDEP ; V71 tmp62 [V71,T48] ( 2, 0.50) byref -> rbx V15._value(offs=0x00) P-INDEP ;* V72 tmp63 [V72,T37] ( 0, 0 ) byref -> zero-ref V16._pointer(offs=0x00) P-INDEP ;* V73 tmp64 [V73,T39] ( 0, 0 ) int -> zero-ref V16._length(offs=0x08) P-INDEP ; V74 tmp65 [V74,T30] ( 2, 1.25) byref -> rcx V17._pointer(offs=0x00) P-INDEP ; V75 tmp66 [V75,T06] ( 4, 2.50) int -> rdx V17._length(offs=0x08) P-INDEP ;* V76 tmp67 [V76,T58] ( 0, 0 ) byref -> zero-ref V27._pointer(offs=0x00) P-INDEP ; V77 tmp68 [V77,T54] ( 2, 0.50) int -> r14 V27._length(offs=0x08) P-INDEP ;* V78 tmp69 [V78,T59] ( 0, 0 ) byref -> zero-ref V28._pointer(offs=0x00) P-INDEP ; V79 tmp70 [V79,T46] ( 2, 0.75) int -> r14 V28._length(offs=0x08) P-INDEP ;* V80 tmp71 [V80 ] ( 0, 0 ) byref -> zero-ref V29._pointer(offs=0x00) P-INDEP ;* V81 tmp72 [V81 ] ( 0, 0 ) int -> zero-ref V29._length(offs=0x08) P-INDEP ;* V82 tmp73 [V82,T60] ( 0, 0 ) byref -> zero-ref V31._value(offs=0x00) P-INDEP ;* V83 tmp74 [V83,T55] ( 0, 0 ) byref -> zero-ref V32._pointer(offs=0x00) P-INDEP ;* V84 tmp75 [V84,T57] ( 0, 0 ) int -> zero-ref V32._length(offs=0x08) P-INDEP ; V85 tmp76 [V85,T42] ( 2, 0.75) byref -> rcx V33._pointer(offs=0x00) P-INDEP ; V86 tmp77 [V86,T12] ( 4, 1.50) int -> rdx V33._length(offs=0x08) P-INDEP ;* V87 tmp78 [V87,T56] ( 0, 0 ) byref -> zero-ref V41._pointer(offs=0x00) P-INDEP ; V88 tmp79 [V88,T27] ( 3, 1.25) int -> rbp V41._length(offs=0x08) P-INDEP ; V89 tmp80 [V89,T43] ( 2, 0.75) byref -> rcx V42._pointer(offs=0x00) P-INDEP ; V90 tmp81 [V90,T13] ( 4, 1.50) int -> rdx V42._length(offs=0x08) P-INDEP ; V91 tmp82 [V91,T44] ( 2, 0.75) byref -> r15 V50._pointer(offs=0x00) P-INDEP ; V92 tmp83 [V92,T28] ( 3, 1.25) int -> r14 V50._length(offs=0x08) P-INDEP ; V93 tmp84 [V93,T45] ( 2, 0.75) byref -> rcx V51._pointer(offs=0x00) P-INDEP ; V94 tmp85 [V94,T14] ( 4, 1.50) int -> rdx V51._length(offs=0x08) P-INDEP ;* V95 tmp86 [V95 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[S] ; V96 tmp87 [V96,T05] ( 11, 2.50) ref -> registers ; V97 tmp88 [V97 ] ( 15, 12 ) struct (16) [rsp+0x38] do-not-enreg[XSB] must-init addr-exposed ; V98 tmp89 [V98,T16] ( 3, 1.50) byref -> rax stack-byref ; V99 tmp90 [V99 ] ( 12, 8 ) struct (16) [rsp+0x28] do-not-enreg[XSB] must-init addr-exposed ; V100 tmp91 [V100,T17] ( 3, 1.50) byref -> rax stack-byref ; V101 tmp92 [V101,T18] ( 3, 1.50) byref -> rax stack-byref ; V102 tmp93 [V102,T19] ( 3, 1.50) byref -> rax stack-byref ;* V103 tmp94 [V103,T38] ( 0, 0 ) byref -> zero-ref ; V104 tmp95 [V104,T20] ( 3, 1.50) byref -> rax stack-byref ; V105 tmp96 [V105,T21] ( 3, 1.50) byref -> rax stack-byref ; V106 tmp97 [V106,T22] ( 3, 1.50) byref -> rax stack-byref ; V107 tmp98 [V107,T23] ( 3, 1.50) byref -> rax stack-byref ; V108 OutArgs [V108 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; ; Lcl frame size = 80 =============== Generating BB01 [000..017) -> BB06 (cond), preds={} succs={BB05,BB06} flags=0x00000000.400b0020: i label target gcsafe LIR BB01 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rsi) V01(rdi) Change life 0000000000000000 {} -> 0000000000000003 {V00 V01} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V01 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} Live regs: (unchanged) 000000C0 {rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 000000C0 {rsi rdi} L_M57450_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi} Setting stack level from -572662307 to 0 Scope info: begin block BB01, IL range [000..017) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x0001 STACK_EMPTY (G_M57450_IG02,ins#0,ofs#0) label Generating: N003 ( 1, 3) [000171] ------------ IL_OFFSET void IL offset: 0x1 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N005 ( 20, 23) [000187] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N007 ( 3, 10) [000947] ------------ t947 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG rbx $180 IN0001: lea rbx, [(reloc 0x421150)] GC regs: 00000000 {} => 00000008 {rbx} /--* t947 ref Generating: N009 ( 7, 13) [000939] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:4 rbx REG rbx GC regs: 00000008 {rbx} => 00000000 {} V96 in reg rbx is becoming live [000939] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01} => {V00 V01 V96} GC regs: 00000000 {} => 00000008 {rbx} Generating: N011 ( 3, 2) [000940] ------------ t940 = LCL_VAR ref V96 tmp87 u:4 rbx REG rbx $180 /--* t940 ref Generating: N013 ( 4, 3) [000941] ---X---N---- * NULLCHECK byte REG NA $241 IN0002: cmp dword ptr [rbx], ebx Generating: N015 ( 3, 2) [000943] ------------ t943 = LCL_VAR ref V96 tmp87 u:4 rbx (last use) REG rbx $180 Generating: N017 ( 1, 1) [000944] -c---------- t944 = CNS_INT long 12 field offset Fseq[_firstChar] REG NA $280 /--* t943 ref +--* t944 long Generating: N019 ( 5, 4) [000945] ------------ t945 = * ADD byref REG rbx $VN.Null V96 in reg rbx is becoming dead [000943] Live regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V96} => {V00 V01} GC regs: 00000008 {rbx} => 00000000 {} IN0003: add rbx, 12 Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} /--* t945 byref Generating: N021 ( 20, 23) [000186] DA-XG------- * STORE_LCL_VAR byref V10 tmp1 d:3 rbx REG rbx Byref regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} V10 in reg rbx is becoming live [000186] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01} => {V00 V01 V10} Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N023 ( 10, 16) [000239] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N025 ( 3, 10) [000955] ------------ t955 = CNS_INT(h) ref 0x421150 [ICON_STR_HDL] REG rcx $180 IN0004: lea rcx, [(reloc 0x421150)] GC regs: 00000000 {} => 00000002 {rcx} /--* t955 ref Generating: N027 (???,???) [001478] -c---------- t1478 = * LEA(b+8) byref REG NA /--* t1478 byref Generating: N029 ( 6, 13) [000236] x---G------- t236 = * IND int REG rbp GC regs: 00000002 {rcx} => 00000000 {} IN0005: mov ebp, dword ptr [rcx+8] /--* t236 int Generating: N031 ( 10, 16) [000238] DA--G------- * STORE_LCL_VAR int V14 tmp5 d:3 rbp REG rbp V14 in reg rbp is becoming live [000238] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V10} => {V00 V01 V10 V14} genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N033 ( 0, 0) [000193] ------------ IL_OFFSET void IL offset: 0x1 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N035 ( 22, 10) [000256] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N037 ( 3, 2) [000240] ------------ t240 = LCL_VAR int V14 tmp5 u:3 rbp REG rbp Generating: N039 ( 1, 1) [000250] -c---------- t250 = CNS_INT int 0 REG NA $40 /--* t240 int +--* t250 int Generating: N041 ( 8, 4) [000251] ------------ t251 = * GE int REG rcx IN0006: test ebp, ebp IN0007: setge cl IN0008: movzx rcx, cl /--* t251 int Generating: N043 (???,???) [001479] ------------ t1479 = * PUTARG_REG int REG rcx /--* t1479 int arg0 in rcx Generating: N045 ( 22, 10) [000254] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi} IN0009: call System.Diagnostics.Debug:Assert(bool) genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N047 ( 7, 5) [000268] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N049 ( 3, 2) [000188] ------------ t188 = LCL_VAR byref V10 tmp1 u:3 rbx (last use) REG rbx $VN.Null /--* t188 byref Generating: N051 ( 7, 5) [000266] DA---------- * STORE_LCL_VAR byref V71 tmp62 d:3 rbx REG rbx V10 in reg rbx is becoming dead [000188] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000E0 {rbp rsi rdi} Live vars: {V00 V01 V10 V14} => {V00 V01 V14} Byref regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} V71 in reg rbx is becoming live [000266] Live regs: 000000E0 {rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V14} => {V00 V01 V14 V71} Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N053 ( 7, 5) [000273] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N055 ( 3, 2) [000970] -------N---- t970 = LCL_VAR byref V71 tmp62 u:3 rbx (last use) REG rbx $VN.Null /--* t970 byref Generating: N057 ( 7, 5) [000971] DA---------- * STORE_LCL_VAR byref V65 tmp56 d:3 rbx REG rbx V71 in reg rbx is becoming dead [000970] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000E0 {rbp rsi rdi} Live vars: {V00 V01 V14 V71} => {V00 V01 V14} Byref regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} V65 in reg rbx is becoming live [000971] Live regs: 000000E0 {rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V14} => {V00 V01 V14 V65} Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N059 ( 7, 5) [000279] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N061 ( 3, 2) [000276] ------------ t276 = LCL_VAR int V14 tmp5 u:3 rbp (last use) REG rbp /--* t276 int Generating: N063 ( 7, 5) [000278] DA---------- * STORE_LCL_VAR int V66 tmp57 d:3 rbp REG rbp V14 in reg rbp is becoming dead [000276] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V14 V65} => {V00 V01 V65} V66 in reg rbp is becoming live [000278] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V65} => {V00 V01 V65 V66} genIPmappingAdd: ignoring duplicate IL offset 0x1 Generating: N065 ( 14, 10) [000204] ------------ IL_OFFSET void IL offset: 0x1 REG NA Generating: N067 ( 3, 2) [000973] -------N---- t973 = LCL_VAR byref V65 tmp56 u:3 rbx (last use) REG rbx $VN.Null /--* t973 byref Generating: N069 ( 7, 5) [000974] DA---------- * STORE_LCL_VAR byref V67 tmp58 d:4 rbx REG rbx V65 in reg rbx is becoming dead [000973] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000E0 {rbp rsi rdi} Live vars: {V00 V01 V65 V66} => {V00 V01 V66} Byref regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} V67 in reg rbx is becoming live [000974] Live regs: 000000E0 {rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V66} => {V00 V01 V66 V67} Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} Generating: N071 ( 3, 2) [000976] -------N---- t976 = LCL_VAR int V66 tmp57 u:3 rbp (last use) REG rbp /--* t976 int Generating: N073 ( 7, 5) [000977] DA---------- * STORE_LCL_VAR int V68 tmp59 d:4 rbp REG rbp V66 in reg rbp is becoming dead [000976] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V66 V67} => {V00 V01 V67} V68 in reg rbp is becoming live [000977] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V67} => {V00 V01 V67 V68} Generating: N075 ( 3, 2) [000980] -------N---- t980 = LCL_VAR byref V67 tmp58 u:3 rbx (last use) REG rbx $VN.Null /--* t980 byref Generating: N077 ( 7, 5) [000981] DA---------- * STORE_LCL_VAR byref V61 tmp52 d:3 rbx REG rbx V67 in reg rbx is becoming dead [000980] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000E0 {rbp rsi rdi} Live vars: {V00 V01 V67 V68} => {V00 V01 V68} Byref regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} V61 in reg rbx is becoming live [000981] Live regs: 000000E0 {rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V68} => {V00 V01 V61 V68} Byref regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} Generating: N079 ( 3, 2) [000983] -------N---- t983 = LCL_VAR int V68 tmp59 u:3 rbp (last use) REG rbp $3c0 /--* t983 int Generating: N081 ( 7, 5) [000984] DA---------- * STORE_LCL_VAR int V62 tmp53 d:3 rbp REG rbp V68 in reg rbp is becoming dead [000983] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V61 V68} => {V00 V01 V61} V62 in reg rbp is becoming live [000984] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V61} => {V00 V01 V61 V62} Added IP mapping: 0x000C STACK_EMPTY (G_M57450_IG02,ins#9,ofs#36) Generating: N083 ( 10, 8) [000355] ------------ IL_OFFSET void IL offset: 0xc REG NA genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N085 ( 12, 10) [000359] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N087 ( 1, 1) [000995] ------------ t995 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t995 byref Generating: N089 (???,???) [001480] -c---------- t1480 = * LEA(b+0) byref REG NA /--* t1480 byref Generating: N091 ( 4, 3) [000998] x----------- t998 = * IND byref REG rcx IN000a: mov rcx, bword ptr [rsi] Byref regs: 000000C8 {rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} /--* t998 byref Generating: N093 ( 8, 6) [000999] DA---------- * STORE_LCL_VAR byref V74 tmp65 d:3 rcx REG rcx Byref regs: 000000CA {rcx rbx rsi rdi} => 000000C8 {rbx rsi rdi} V74 in reg rcx is becoming live [000999] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000EA {rcx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V74} Byref regs: 000000C8 {rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} Generating: N095 ( 1, 1) [001001] ------------ t1001 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1001 byref Generating: N097 (???,???) [001481] -c---------- t1481 = * LEA(b+8) byref REG NA /--* t1481 byref Generating: N099 ( 4, 4) [001004] x----------- t1004 = * IND int REG rdx IN000b: mov edx, dword ptr [rsi+8] /--* t1004 int Generating: N101 ( 4, 4) [001005] DA---------- * STORE_LCL_VAR int V75 tmp66 d:3 rdx REG rdx V75 in reg rdx is becoming live [001005] Live regs: 000000EA {rcx rbx rbp rsi rdi} => 000000EE {rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74} => {V00 V01 V61 V62 V74 V75} genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N103 ( 6, 3) [000302] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N105 ( 1, 1) [000295] ------------ t295 = LCL_VAR int V62 tmp53 u:3 rbp REG rbp $3c0 Generating: N107 ( 1, 1) [000393] ------------ t393 = LCL_VAR int V75 tmp66 u:3 rdx REG rdx /--* t295 int +--* t393 int Generating: N109 ( 6, 3) [000297] ------------ t297 = * NE int REG rax IN000c: cmp ebp, edx IN000d: setne al IN000e: movzx rax, al /--* t297 int Generating: N111 ( 6, 3) [000301] DA---------- * STORE_LCL_VAR int V19 tmp10 d:3 rax REG rax V19 in reg rax is becoming live [000301] Live regs: 000000EE {rcx rdx rbx rbp rsi rdi} => 000000EF {rax rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75} => {V00 V01 V19 V61 V62 V74 V75} genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N113 ( 5, 5) [000307] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N115 ( 1, 1) [000303] ------------ t303 = LCL_VAR int V19 tmp10 u:3 rax (last use) REG rax Generating: N117 ( 1, 1) [000304] -c---------- t304 = CNS_INT int 0 REG NA $40 /--* t303 int +--* t304 int Generating: N119 ( 3, 3) [000305] J------N---- * EQ void REG NA V19 in reg rax is becoming dead [000303] Live regs: 000000EF {rax rcx rdx rbx rbp rsi rdi} => 000000EE {rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V19 V61 V62 V74 V75} => {V00 V01 V61 V62 V74 V75} IN000f: test eax, eax Generating: N121 ( 5, 5) [000306] ------------ * JTRUE void REG NA IN0010: je L_M57450_BB06 Scope info: end block BB01, IL range [000..017) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB05 [00C..00D) -> BB09 (always), preds={BB01} succs={BB09} flags=0x00000000.40000020: i LIR BB05 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V00(rsi) V01(rdi) V61(rbx) V62(rbp) Change life 000000004000004F {V00 V01 V61 V62 V74 V75} -> 000000000000000F {V00 V01 V61 V62} V75 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V74 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000000C8 {rbx rsi rdi} L_M57450_BB05: Scope info: begin block BB05, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N125 ( 1, 3) [000351] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N127 ( 1, 1) [000348] ------------ t348 = CNS_INT int 0 REG r14 $40 IN0011: xor r14d, r14d /--* t348 int Generating: N129 ( 1, 3) [000350] DA---------- * STORE_LCL_VAR int V21 tmp12 d:5 r14 REG r14 V21 in reg r14 is becoming live [000350] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Scope info: end block BB05, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN0012: jmp L_M57450_BB09 =============== Generating BB06 [00C..00D) -> BB08 (cond), preds={BB01} succs={BB07,BB08} flags=0x00000000.40030020: i label target LIR BB06 IN (6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap OUT(6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V00(rsi) V01(rdi) V61(rbx) V62(rbp) V75(rdx) V74(rcx) Change life 000000000000080F {V00 V01 V21 V61 V62} -> 000000004000004F {V00 V01 V61 V62 V74 V75} V21 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V75 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V74 in reg rcx is becoming live [------] Live regs: 00000004 {rdx} => 00000006 {rcx rdx} Live regs: 00000006 {rcx rdx} => 000000EE {rcx rdx rbx rbp rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000002 {rcx} => 000000CA {rcx rbx rsi rdi} L_M57450_BB06: G_M57450_IG02: ; offs=000000H, funclet=00 Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi} Scope info: begin block BB06, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N133 ( 10, 6) [000318] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N135 ( 1, 1) [000406] ------------ t406 = LCL_VAR int V75 tmp66 u:3 rdx REG rdx Generating: N137 ( 1, 1) [000314] -c---------- t314 = CNS_INT int 0 REG NA $40 /--* t406 int +--* t314 int Generating: N139 ( 6, 3) [000315] ------------ t315 = * EQ int REG rax IN0013: test edx, edx IN0014: sete al IN0015: movzx rax, al /--* t315 int Generating: N141 ( 10, 6) [000317] DA---------- * STORE_LCL_VAR int V20 tmp11 d:3 rax REG rax V20 in reg rax is becoming live [000317] Live regs: 000000EE {rcx rdx rbx rbp rsi rdi} => 000000EF {rax rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75} => {V00 V01 V20 V61 V62 V74 V75} genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N143 ( 7, 6) [000323] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N145 ( 3, 2) [000319] ------------ t319 = LCL_VAR int V20 tmp11 u:3 rax (last use) REG rax Generating: N147 ( 1, 1) [000320] -c---------- t320 = CNS_INT int 0 REG NA $40 /--* t319 int +--* t320 int Generating: N149 ( 5, 4) [000321] J------N---- * EQ void REG NA V20 in reg rax is becoming dead [000319] Live regs: 000000EF {rax rcx rdx rbx rbp rsi rdi} => 000000EE {rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V20 V61 V62 V74 V75} => {V00 V01 V61 V62 V74 V75} IN0016: test eax, eax Generating: N151 ( 7, 6) [000322] ------------ * JTRUE void REG NA IN0017: je L_M57450_BB08 Scope info: end block BB06, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB07 [00C..00D) -> BB09 (always), preds={BB06} succs={BB09} flags=0x00000000.40000020: i LIR BB07 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V00(rsi) V01(rdi) V61(rbx) V62(rbp) Change life 000000004000004F {V00 V01 V61 V62 V74 V75} -> 000000000000000F {V00 V01 V61 V62} V75 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V74 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000000C8 {rbx rsi rdi} L_M57450_BB07: Scope info: begin block BB07, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N155 ( 1, 3) [000346] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N157 ( 1, 1) [000343] -c---------- t343 = CNS_INT int 1 REG NA $41 /--* t343 int Generating: N159 ( 1, 3) [000345] DA---------- * STORE_LCL_VAR int V21 tmp12 d:4 r14 REG r14 IN0018: mov r14d, 1 V21 in reg r14 is becoming live [000345] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Scope info: end block BB07, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN0019: jmp L_M57450_BB09 =============== Generating BB08 [00C..00D), preds={BB06} succs={BB09} flags=0x00000000.400b0020: i label target gcsafe LIR BB08 IN (6)={V00 V01 V61 V62 V75 V74} + ByrefExposed + GcHeap OUT(5)={V00 V01 V61 V62 V21 } + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V00(rsi) V01(rdi) V61(rbx) V62(rbp) V75(rdx) V74(rcx) Change life 000000000000080F {V00 V01 V21 V61 V62} -> 000000004000004F {V00 V01 V61 V62 V74 V75} V21 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V75 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V74 in reg rcx is becoming live [------] Live regs: 00000004 {rdx} => 00000006 {rcx rdx} Live regs: 00000006 {rcx rdx} => 000000EE {rcx rdx rbx rbp rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000002 {rcx} => 000000CA {rcx rbx rsi rdi} L_M57450_BB08: G_M57450_IG03: ; offs=000042H, funclet=00 Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi} Scope info: begin block BB08, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N163 ( 81, 55) [000338] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N165 ( 3, 2) [001016] -------N---- t1016 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax IN001a: lea rax, bword ptr [V97 rsp+38H] Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CB {rax rcx rbx rsi rdi} /--* t1016 byref Generating: N167 ( 7, 6) [001018] DA---------- * STORE_LCL_VAR byref V98 tmp89 d:3 rax REG rax Byref regs: 000000CB {rax rcx rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} V98 in reg rax is becoming live [001018] Live regs: 000000EE {rcx rdx rbx rbp rsi rdi} => 000000EF {rax rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75} => {V00 V01 V61 V62 V74 V75 V98} Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CB {rax rcx rbx rsi rdi} Generating: N169 ( 3, 2) [001019] ------------ t1019 = LCL_VAR byref V98 tmp89 u:3 rax REG rax $2ca /--* t1019 byref Generating: N171 (???,???) [001482] -c---------- t1482 = * LEA(b+0) byref REG NA Generating: N173 ( 3, 2) [001023] -------N---- t1023 = LCL_VAR byref V61 tmp52 u:3 rbx REG rbx $VN.Null /--* t1482 byref +--* t1023 byref Generating: N175 (???,???) [001456] -A---------- * STOREIND byref REG NA IN001b: mov bword ptr [rax], rbx Generating: N177 ( 3, 2) [001026] ------------ t1026 = LCL_VAR byref V98 tmp89 u:3 rax (last use) REG rax $2ca /--* t1026 byref Generating: N179 (???,???) [001483] -c---------- t1483 = * LEA(b+8) byref REG NA Generating: N181 ( 1, 1) [001030] -------N---- t1030 = LCL_VAR int V62 tmp53 u:3 rbp REG rbp $3c0 /--* t1483 byref +--* t1030 int Generating: N183 (???,???) [001457] -A--------L- * STOREIND int REG NA V98 in reg rax is becoming dead [001026] Live regs: 000000EF {rax rcx rdx rbx rbp rsi rdi} => 000000EE {rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75 V98} => {V00 V01 V61 V62 V74 V75} Byref regs: 000000CB {rax rcx rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} IN001c: mov dword ptr [rax+8], ebp Generating: N185 ( 3, 2) [001037] -------N---- t1037 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax IN001d: lea rax, bword ptr [V99 rsp+28H] Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CB {rax rcx rbx rsi rdi} /--* t1037 byref Generating: N187 ( 7, 6) [001039] DA---------- * STORE_LCL_VAR byref V100 tmp91 d:3 rax REG rax Byref regs: 000000CB {rax rcx rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} V100 in reg rax is becoming live [001039] Live regs: 000000EE {rcx rdx rbx rbp rsi rdi} => 000000EF {rax rcx rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75} => {V00 V01 V61 V62 V74 V75 V100} Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CB {rax rcx rbx rsi rdi} Generating: N189 ( 3, 2) [001040] ------------ t1040 = LCL_VAR byref V100 tmp91 u:3 rax REG rax $2cc /--* t1040 byref Generating: N191 (???,???) [001484] -c---------- t1484 = * LEA(b+0) byref REG NA Generating: N193 ( 3, 2) [001044] -------N---- t1044 = LCL_VAR byref V74 tmp65 u:3 rcx (last use) REG rcx /--* t1484 byref +--* t1044 byref Generating: N195 (???,???) [001458] -A---------- * STOREIND byref REG NA V74 in reg rcx is becoming dead [001044] Live regs: 000000EF {rax rcx rdx rbx rbp rsi rdi} => 000000ED {rax rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V74 V75 V100} => {V00 V01 V61 V62 V75 V100} Byref regs: 000000CB {rax rcx rbx rsi rdi} => 000000C9 {rax rbx rsi rdi} IN001e: mov bword ptr [rax], rcx Generating: N197 ( 3, 2) [001047] ------------ t1047 = LCL_VAR byref V100 tmp91 u:3 rax (last use) REG rax $2cc /--* t1047 byref Generating: N199 (???,???) [001485] -c---------- t1485 = * LEA(b+8) byref REG NA Generating: N201 ( 1, 1) [001051] -------N---- t1051 = LCL_VAR int V75 tmp66 u:3 rdx (last use) REG rdx /--* t1485 byref +--* t1051 int Generating: N203 (???,???) [001459] -A--------L- * STOREIND int REG NA V100 in reg rax is becoming dead [001047] Live regs: 000000ED {rax rdx rbx rbp rsi rdi} => 000000EC {rdx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V75 V100} => {V00 V01 V61 V62 V75} Byref regs: 000000C9 {rax rbx rsi rdi} => 000000C8 {rbx rsi rdi} V75 in reg rdx is becoming dead [001051] Live regs: 000000EC {rdx rbx rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V75} => {V00 V01 V61 V62} IN001f: mov dword ptr [rax+8], edx Generating: N205 ( 3, 2) [001054] -------N---- t1054 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx IN0020: lea rcx, bword ptr [V97 rsp+38H] Byref regs: 000000C8 {rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} /--* t1054 byref Generating: N207 (???,???) [001486] ------------ t1486 = * PUTARG_REG byref REG rcx Byref regs: 000000CA {rcx rbx rsi rdi} => 000000C8 {rbx rsi rdi} Byref regs: 000000C8 {rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} Generating: N209 ( 3, 2) [001057] -------N---- t1057 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx IN0021: lea rdx, bword ptr [V99 rsp+28H] Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CE {rcx rdx rbx rsi rdi} /--* t1057 byref Generating: N211 (???,???) [001487] ------------ t1487 = * PUTARG_REG byref REG rdx Byref regs: 000000CE {rcx rdx rbx rsi rdi} => 000000CA {rcx rbx rsi rdi} Byref regs: 000000CA {rcx rbx rsi rdi} => 000000CE {rcx rdx rbx rsi rdi} /--* t1486 byref arg0 in rcx +--* t1487 byref arg1 in rdx Generating: N213 ( 76, 53) [000327] --CXG------- t327 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1ce Byref regs: 000000CE {rcx rdx rbx rsi rdi} => 000000CC {rdx rbx rsi rdi} Byref regs: 000000CC {rdx rbx rsi rdi} => 000000C8 {rbx rsi rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi} IN0022: call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int Generating: N215 ( 1, 1) [000334] -c---------- t334 = CNS_INT int 0 REG NA $40 /--* t327 int +--* t334 int Generating: N217 ( 81, 55) [000335] ---XG------- t335 = * EQ int REG r14 $30d IN0023: test eax, eax IN0024: sete r14b IN0025: movzx r14, r14b /--* t335 int Generating: N219 ( 81, 55) [000337] DA-XG------- * STORE_LCL_VAR int V21 tmp12 d:3 r14 REG r14 V21 in reg r14 is becoming live [000337] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V21 V61 V62} Scope info: end block BB08, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB09 [00C..00D) -> BB11 (cond), preds={BB05,BB07,BB08} succs={BB10,BB11} flags=0x00000000.40030020: i label target LIR BB09 IN (5)={V00 V01 V61 V62 V21} + ByrefExposed + GcHeap OUT(4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V00(rsi) V01(rdi) V61(rbx) V62(rbp) V21(r14) Liveness not changing: 000000000000080F {V00 V01 V21 V61 V62} Live regs: 00000000 {} => 000040E8 {rbx rbp rsi rdi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000000C8 {rbx rsi rdi} L_M57450_BB09: G_M57450_IG04: ; offs=00005DH, funclet=00 Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi} Scope info: begin block BB09, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x0014 STACK_EMPTY (G_M57450_IG05,ins#0,ofs#0) label Generating: N223 ( 5, 5) [000029] ------------ IL_OFFSET void IL offset: 0x14 REG NA Generating: N225 ( 1, 1) [000025] ------------ t25 = LCL_VAR int V21 tmp12 u:6 r14 (last use) REG r14 $500 Generating: N227 ( 1, 1) [000026] -c---------- t26 = CNS_INT int 0 REG NA $40 /--* t25 int +--* t26 int Generating: N229 ( 3, 3) [000027] J------N---- * EQ void REG NA $30e V21 in reg r14 is becoming dead [000025] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V21 V61 V62} => {V00 V01 V61 V62} IN0026: test r14d, r14d Generating: N231 ( 5, 5) [000028] ------------ * JTRUE void REG NA IN0027: je L_M57450_BB11 Scope info: end block BB09, IL range [00C..00D) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB10 [017..01F) -> BB36 (always), preds={BB09} succs={BB36} flags=0x00000000.40000020: i LIR BB10 IN (1)={V01 } OUT(1)={ V05} Recording Var Locations at start of BB10 V01(rdi) Change life 000000000000000F {V00 V01 V61 V62} -> 0000000000000002 {V01} V00 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V61 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V62 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB10: Scope info: begin block BB10, IL range [017..01F) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x0018 STACK_EMPTY (G_M57450_IG05,ins#2,ofs#9) label Generating: N235 ( 6, 5) [000160] ------------ IL_OFFSET void IL offset: 0x18 REG NA Generating: N237 ( 1, 1) [000156] ------------ t156 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 Generating: N239 ( 1, 1) [000157] -c---------- t157 = CNS_INT int 1 REG NA $41 /--* t156 byref +--* t157 int Generating: N241 (???,???) [001460] -A-XG------- * STOREIND byte REG NA V01 in reg rdi is becoming dead [000156] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0028: mov byte ptr [rdi], 1 Added IP mapping: 0x001B STACK_EMPTY (G_M57450_IG05,ins#3,ofs#12) Generating: N243 ( 1, 3) [000164] ------------ IL_OFFSET void IL offset: 0x1b REG NA Generating: N245 ( 1, 1) [000161] -c---------- t161 = CNS_INT int 1 REG NA $41 /--* t161 int Generating: N247 ( 1, 3) [000163] DA---------- * STORE_LCL_VAR int V05 loc3 d:7 rax REG rax IN0029: mov eax, 1 V05 in reg rax is becoming live [000163] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V05} Scope info: end block BB10, IL range [017..01F) Scope info: open scopes = IN002a: jmp L_M57450_BB36 =============== Generating BB11 [01F..037) -> BB16 (cond), preds={BB09} succs={BB15,BB16} flags=0x00000000.400b0020: i label target gcsafe LIR BB11 IN (4)={V00 V01 V61 V62 } + ByrefExposed + GcHeap OUT(8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap Recording Var Locations at start of BB11 V00(rsi) V01(rdi) V61(rbx) V62(rbp) Change life 0000000000000010 {V05} -> 000000000000000F {V00 V01 V61 V62} V05 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V01 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V61 in reg rbx is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} V62 in reg rbp is becoming live [------] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live regs: (unchanged) 000000E8 {rbx rbp rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 000000C8 {rbx rsi rdi} L_M57450_BB11: G_M57450_IG05: ; offs=00008CH, funclet=00 Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi} Scope info: begin block BB11, IL range [01F..037) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x001F STACK_EMPTY (G_M57450_IG06,ins#0,ofs#0) label Generating: N251 ( 5, 4) [000418] ------------ IL_OFFSET void IL offset: 0x1f REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N253 ( 12, 18) [000434] ------------ IL_OFFSET void IL offset: 0x1f REG NA Generating: N255 ( 3, 10) [001089] ------------ t1089 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG rcx $184 IN002b: lea rcx, [(reloc 0x421158)] GC regs: 00000000 {} => 00000002 {rcx} /--* t1089 ref Generating: N257 ( 3, 10) [001081] DA---------- * STORE_LCL_VAR ref V96 tmp87 d:3 rcx REG rcx GC regs: 00000002 {rcx} => 00000000 {} V96 in reg rcx is becoming live [001081] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000EA {rcx rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V96} GC regs: 00000000 {} => 00000002 {rcx} Generating: N259 ( 1, 1) [001082] ------------ t1082 = LCL_VAR ref V96 tmp87 u:3 rcx (last use) REG rcx $184 /--* t1082 ref Generating: N261 ( 2, 2) [001083] ---X---N---- * NULLCHECK byte REG NA $24c V96 in reg rcx is becoming dead [001082] Live regs: 000000EA {rcx rbx rbp rsi rdi} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V96} => {V00 V01 V61 V62} GC regs: 00000002 {rcx} => 00000000 {} IN002c: cmp dword ptr [rcx], ecx genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N263 ( 10, 16) [000486] ------------ IL_OFFSET void IL offset: 0x1f REG NA Generating: N265 ( 3, 10) [001097] ------------ t1097 = CNS_INT(h) ref 0x421158 [ICON_STR_HDL] REG rcx $184 IN002d: lea rcx, [(reloc 0x421158)] GC regs: 00000000 {} => 00000002 {rcx} /--* t1097 ref Generating: N267 (???,???) [001488] -c---------- t1488 = * LEA(b+8) byref REG NA /--* t1488 byref Generating: N269 ( 6, 13) [000483] x---G------- t483 = * IND int REG r14 GC regs: 00000002 {rcx} => 00000000 {} IN002e: mov r14d, dword ptr [rcx+8] /--* t483 int Generating: N271 ( 10, 16) [000485] DA--G------- * STORE_LCL_VAR int V30 tmp21 d:3 r14 REG r14 V30 in reg r14 is becoming live [000485] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V30 V61 V62} genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N273 ( 0, 0) [000440] ------------ IL_OFFSET void IL offset: 0x1f REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N275 ( 22, 10) [000503] ------------ IL_OFFSET void IL offset: 0x1f REG NA Generating: N277 ( 3, 2) [000487] ------------ t487 = LCL_VAR int V30 tmp21 u:3 r14 REG r14 Generating: N279 ( 1, 1) [000497] -c---------- t497 = CNS_INT int 0 REG NA $40 /--* t487 int +--* t497 int Generating: N281 ( 8, 4) [000498] ------------ t498 = * GE int REG rcx IN002f: test r14d, r14d IN0030: setge cl IN0031: movzx rcx, cl /--* t498 int Generating: N283 (???,???) [001489] ------------ t1489 = * PUTARG_REG int REG rcx /--* t1489 int arg0 in rcx Generating: N285 ( 22, 10) [000501] --CXG------- * CALL void System.Diagnostics.Debug.Assert $VN.Void Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi} IN0032: call System.Diagnostics.Debug:Assert(bool) genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N287 ( 7, 5) [000515] ------------ IL_OFFSET void IL offset: 0x1f REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N289 ( 7, 5) [000520] ------------ IL_OFFSET void IL offset: 0x1f REG NA genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N291 ( 7, 5) [000526] ------------ IL_OFFSET void IL offset: 0x1f REG NA Generating: N293 ( 3, 2) [000523] ------------ t523 = LCL_VAR int V30 tmp21 u:3 r14 (last use) REG r14 /--* t523 int Generating: N295 ( 7, 5) [000525] DA---------- * STORE_LCL_VAR int V77 tmp68 d:3 r14 REG r14 V30 in reg r14 is becoming dead [000523] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V30 V61 V62} => {V00 V01 V61 V62} V77 in reg r14 is becoming live [000525] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V77} genIPmappingAdd: ignoring duplicate IL offset 0x1f Generating: N297 ( 14, 10) [000451] ------------ IL_OFFSET void IL offset: 0x1f REG NA Generating: N299 ( 3, 2) [001118] -------N---- t1118 = LCL_VAR int V77 tmp68 u:3 r14 (last use) REG r14 /--* t1118 int Generating: N301 ( 7, 5) [001119] DA---------- * STORE_LCL_VAR int V79 tmp70 d:4 r14 REG r14 V77 in reg r14 is becoming dead [001118] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 000000E8 {rbx rbp rsi rdi} Live vars: {V00 V01 V61 V62 V77} => {V00 V01 V61 V62} V79 in reg r14 is becoming live [001119] Live regs: 000000E8 {rbx rbp rsi rdi} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V61 V62} => {V00 V01 V61 V62 V79} Generating: N303 ( 3, 2) [001122] -------N---- t1122 = LCL_VAR byref V61 tmp52 u:3 rbx REG rbx $VN.Null /--* t1122 byref Generating: N305 ( 7, 5) [001123] DA---------- * STORE_LCL_VAR byref V63 tmp54 d:3 r15 REG r15 IN0033: mov r15, rbx V63 in reg r15 is becoming live [001123] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V79} => {V00 V01 V61 V62 V63 V79} Byref regs: 000000C8 {rbx rsi rdi} => 000080C8 {rbx rsi rdi r15} Generating: N307 ( 3, 2) [001125] -------N---- t1125 = LCL_VAR int V79 tmp70 u:3 r14 (last use) REG r14 $3c2 /--* t1125 int Generating: N309 ( 7, 5) [001126] DA---------- * STORE_LCL_VAR int V64 tmp55 d:3 r14 REG r14 V79 in reg r14 is becoming dead [001125] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 000080E8 {rbx rbp rsi rdi r15} Live vars: {V00 V01 V61 V62 V63 V79} => {V00 V01 V61 V62 V63} V64 in reg r14 is becoming live [001126] Live regs: 000080E8 {rbx rbp rsi rdi r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63} => {V00 V01 V61 V62 V63 V64} Added IP mapping: 0x002A STACK_EMPTY (G_M57450_IG06,ins#9,ofs#37) Generating: N311 ( 14, 10) [000602] ------------ IL_OFFSET void IL offset: 0x2a REG NA genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N313 ( 16, 13) [000606] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N315 ( 1, 1) [001137] ------------ t1137 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1137 byref Generating: N317 (???,???) [001490] -c---------- t1490 = * LEA(b+0) byref REG NA /--* t1490 byref Generating: N319 ( 4, 3) [001140] x----------- t1140 = * IND byref REG rcx IN0034: mov rcx, bword ptr [rsi] Byref regs: 000080C8 {rbx rsi rdi r15} => 000080CA {rcx rbx rsi rdi r15} /--* t1140 byref Generating: N321 ( 8, 6) [001141] DA---------- * STORE_LCL_VAR byref V85 tmp76 d:3 rcx REG rcx Byref regs: 000080CA {rcx rbx rsi rdi r15} => 000080C8 {rbx rsi rdi r15} V85 in reg rcx is becoming live [001141] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0EA {rcx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64} => {V00 V01 V61 V62 V63 V64 V85} Byref regs: 000080C8 {rbx rsi rdi r15} => 000080CA {rcx rbx rsi rdi r15} Generating: N323 ( 1, 1) [001143] ------------ t1143 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1143 byref Generating: N325 (???,???) [001491] -c---------- t1491 = * LEA(b+8) byref REG NA /--* t1491 byref Generating: N327 ( 4, 4) [001146] x----------- t1146 = * IND int REG rdx IN0035: mov edx, dword ptr [rsi+8] /--* t1146 int Generating: N329 ( 8, 7) [001147] DA---------- * STORE_LCL_VAR int V86 tmp77 d:3 rdx REG rdx V86 in reg rdx is becoming live [001147] Live regs: 0000C0EA {rcx rbx rbp rsi rdi r14 r15} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64 V85} => {V00 V01 V61 V62 V63 V64 V85 V86} genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N331 ( 14, 8) [000549] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N333 ( 3, 2) [000542] ------------ t542 = LCL_VAR int V64 tmp55 u:3 r14 REG r14 $3c2 Generating: N335 ( 3, 2) [000640] ------------ t640 = LCL_VAR int V86 tmp77 u:3 rdx REG rdx /--* t542 int +--* t640 int Generating: N337 ( 10, 5) [000544] ------------ t544 = * NE int REG rax IN0036: cmp r14d, edx IN0037: setne al IN0038: movzx rax, al /--* t544 int Generating: N339 ( 14, 8) [000548] DA---------- * STORE_LCL_VAR int V35 tmp26 d:3 rax REG rax V35 in reg rax is becoming live [000548] Live regs: 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64 V85 V86} => {V00 V01 V35 V61 V62 V63 V64 V85 V86} genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N341 ( 7, 6) [000554] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N343 ( 3, 2) [000550] ------------ t550 = LCL_VAR int V35 tmp26 u:3 rax (last use) REG rax Generating: N345 ( 1, 1) [000551] -c---------- t551 = CNS_INT int 0 REG NA $40 /--* t550 int +--* t551 int Generating: N347 ( 5, 4) [000552] J------N---- * EQ void REG NA V35 in reg rax is becoming dead [000550] Live regs: 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V35 V61 V62 V63 V64 V85 V86} => {V00 V01 V61 V62 V63 V64 V85 V86} IN0039: test eax, eax Generating: N349 ( 7, 6) [000553] ------------ * JTRUE void REG NA IN003a: je L_M57450_BB16 Scope info: end block BB11, IL range [01F..037) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB15 [02A..02B) -> BB19 (always), preds={BB11} succs={BB19} flags=0x00000000.40000020: i LIR BB15 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V00(rsi) V01(rdi) V62(rbp) V64(r14) V63(r15) Change life 000004000000148F {V00 V01 V61 V62 V63 V64 V85 V86} -> 000000000000048B {V00 V01 V62 V63 V64} V61 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V86 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V85 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB15: Scope info: begin block BB15, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N353 ( 5, 4) [000598] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N355 ( 1, 1) [000595] ------------ t595 = CNS_INT int 0 REG r12 $40 IN003b: xor r12d, r12d /--* t595 int Generating: N357 ( 5, 4) [000597] DA---------- * STORE_LCL_VAR int V37 tmp28 d:5 r12 REG r12 V37 in reg r12 is becoming live [000597] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V62 V63 V64} => {V00 V01 V37 V62 V63 V64} Scope info: end block BB15, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN003c: jmp L_M57450_BB19 =============== Generating BB16 [02A..02B) -> BB18 (cond), preds={BB11} succs={BB17,BB18} flags=0x00000000.40030020: i label target LIR BB16 IN (8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap OUT(8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap Recording Var Locations at start of BB16 V00(rsi) V01(rdi) V61(rbx) V62(rbp) V64(r14) V63(r15) V86(rdx) V85(rcx) Change life 000000000100048B {V00 V01 V37 V62 V63 V64} -> 000004000000148F {V00 V01 V61 V62 V63 V64 V85 V86} V37 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V61 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V86 in reg rdx is becoming live [------] Live regs: 00000008 {rbx} => 0000000C {rdx rbx} V85 in reg rcx is becoming live [------] Live regs: 0000000C {rdx rbx} => 0000000E {rcx rdx rbx} Live regs: 0000000E {rcx rdx rbx} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 0000000A {rcx rbx} => 000080CA {rcx rbx rsi rdi r15} L_M57450_BB16: G_M57450_IG06: ; offs=0000A2H, funclet=00 Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15} Scope info: begin block BB16, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N361 ( 12, 7) [000565] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N363 ( 3, 2) [000653] ------------ t653 = LCL_VAR int V86 tmp77 u:3 rdx REG rdx Generating: N365 ( 1, 1) [000561] -c---------- t561 = CNS_INT int 0 REG NA $40 /--* t653 int +--* t561 int Generating: N367 ( 8, 4) [000562] ------------ t562 = * EQ int REG rax IN003d: test edx, edx IN003e: sete al IN003f: movzx rax, al /--* t562 int Generating: N369 ( 12, 7) [000564] DA---------- * STORE_LCL_VAR int V36 tmp27 d:3 rax REG rax V36 in reg rax is becoming live [000564] Live regs: 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64 V85 V86} => {V00 V01 V36 V61 V62 V63 V64 V85 V86} genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N371 ( 7, 6) [000570] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N373 ( 3, 2) [000566] ------------ t566 = LCL_VAR int V36 tmp27 u:3 rax (last use) REG rax Generating: N375 ( 1, 1) [000567] -c---------- t567 = CNS_INT int 0 REG NA $40 /--* t566 int +--* t567 int Generating: N377 ( 5, 4) [000568] J------N---- * EQ void REG NA V36 in reg rax is becoming dead [000566] Live regs: 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V36 V61 V62 V63 V64 V85 V86} => {V00 V01 V61 V62 V63 V64 V85 V86} IN0040: test eax, eax Generating: N379 ( 7, 6) [000569] ------------ * JTRUE void REG NA IN0041: je L_M57450_BB18 Scope info: end block BB16, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB17 [02A..02B) -> BB19 (always), preds={BB16} succs={BB19} flags=0x00000000.40000020: i LIR BB17 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap Recording Var Locations at start of BB17 V00(rsi) V01(rdi) V62(rbp) V64(r14) V63(r15) Change life 000004000000148F {V00 V01 V61 V62 V63 V64 V85 V86} -> 000000000000048B {V00 V01 V62 V63 V64} V61 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V86 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V85 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB17: Scope info: begin block BB17, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N383 ( 5, 4) [000593] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N385 ( 1, 1) [000590] -c---------- t590 = CNS_INT int 1 REG NA $41 /--* t590 int Generating: N387 ( 5, 4) [000592] DA---------- * STORE_LCL_VAR int V37 tmp28 d:3 r12 REG r12 IN0042: mov r12d, 1 V37 in reg r12 is becoming live [000592] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V62 V63 V64} => {V00 V01 V37 V62 V63 V64} Scope info: end block BB17, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN0043: jmp L_M57450_BB19 =============== Generating BB18 [02A..02B), preds={BB16} succs={BB19} flags=0x00000000.400b0020: i label target gcsafe LIR BB18 IN (8)={V00 V01 V61 V62 V64 V63 V86 V85} + ByrefExposed + GcHeap OUT(6)={V00 V01 V62 V64 V63 V37 } + ByrefExposed + GcHeap Recording Var Locations at start of BB18 V00(rsi) V01(rdi) V61(rbx) V62(rbp) V64(r14) V63(r15) V86(rdx) V85(rcx) Change life 000000000100048B {V00 V01 V37 V62 V63 V64} -> 000004000000148F {V00 V01 V61 V62 V63 V64 V85 V86} V37 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V61 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V86 in reg rdx is becoming live [------] Live regs: 00000008 {rbx} => 0000000C {rdx rbx} V85 in reg rcx is becoming live [------] Live regs: 0000000C {rdx rbx} => 0000000E {rcx rdx rbx} Live regs: 0000000E {rcx rdx rbx} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 0000000A {rcx rbx} => 000080CA {rcx rbx rsi rdi r15} L_M57450_BB18: G_M57450_IG07: ; offs=0000E6H, funclet=00 Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15} Scope info: begin block BB18, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x2a Generating: N391 ( 89, 60) [000585] ------------ IL_OFFSET void IL offset: 0x2a REG NA Generating: N393 ( 3, 2) [001158] -------N---- t1158 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax IN0044: lea rax, bword ptr [V97 rsp+38H] Byref regs: 000080CA {rcx rbx rsi rdi r15} => 000080CB {rax rcx rbx rsi rdi r15} /--* t1158 byref Generating: N395 ( 7, 6) [001160] DA---------- * STORE_LCL_VAR byref V101 tmp92 d:3 rax REG rax Byref regs: 000080CB {rax rcx rbx rsi rdi r15} => 000080CA {rcx rbx rsi rdi r15} V101 in reg rax is becoming live [001160] Live regs: 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64 V85 V86} => {V00 V01 V61 V62 V63 V64 V85 V86 V101} Byref regs: 000080CA {rcx rbx rsi rdi r15} => 000080CB {rax rcx rbx rsi rdi r15} Generating: N397 ( 3, 2) [001161] ------------ t1161 = LCL_VAR byref V101 tmp92 u:3 rax REG rax $2da /--* t1161 byref Generating: N399 (???,???) [001492] -c---------- t1492 = * LEA(b+0) byref REG NA Generating: N401 ( 3, 2) [001165] -------N---- t1165 = LCL_VAR byref V61 tmp52 u:3 rbx (last use) REG rbx $VN.Null /--* t1492 byref +--* t1165 byref Generating: N403 (???,???) [001461] -A---------- * STOREIND byref REG NA V61 in reg rbx is becoming dead [001165] Live regs: 0000C0EF {rax rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V61 V62 V63 V64 V85 V86 V101} => {V00 V01 V62 V63 V64 V85 V86 V101} Byref regs: 000080CB {rax rcx rbx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} IN0045: mov bword ptr [rax], rbx Generating: N405 ( 3, 2) [001168] ------------ t1168 = LCL_VAR byref V101 tmp92 u:3 rax (last use) REG rax $2da /--* t1168 byref Generating: N407 (???,???) [001493] -c---------- t1493 = * LEA(b+8) byref REG NA Generating: N409 ( 3, 2) [001172] -------N---- t1172 = LCL_VAR int V64 tmp55 u:3 r14 REG r14 $3c2 /--* t1493 byref +--* t1172 int Generating: N411 (???,???) [001462] -A--------L- * STOREIND int REG NA V101 in reg rax is becoming dead [001168] Live regs: 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64 V85 V86 V101} => {V00 V01 V62 V63 V64 V85 V86} Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} IN0046: mov dword ptr [rax+8], r14d Generating: N413 ( 3, 2) [001179] -------N---- t1179 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax IN0047: lea rax, bword ptr [V99 rsp+28H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} /--* t1179 byref Generating: N415 ( 7, 6) [001181] DA---------- * STORE_LCL_VAR byref V102 tmp93 d:3 rax REG rax Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} V102 in reg rax is becoming live [001181] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64 V85 V86} => {V00 V01 V62 V63 V64 V85 V86 V102} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} Generating: N417 ( 3, 2) [001182] ------------ t1182 = LCL_VAR byref V102 tmp93 u:3 rax REG rax $2dc /--* t1182 byref Generating: N419 (???,???) [001494] -c---------- t1494 = * LEA(b+0) byref REG NA Generating: N421 ( 3, 2) [001186] -------N---- t1186 = LCL_VAR byref V85 tmp76 u:3 rcx (last use) REG rcx /--* t1494 byref +--* t1186 byref Generating: N423 (???,???) [001463] -A---------- * STOREIND byref REG NA V85 in reg rcx is becoming dead [001186] Live regs: 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} => 0000C0E5 {rax rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64 V85 V86 V102} => {V00 V01 V62 V63 V64 V86 V102} Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C1 {rax rsi rdi r15} IN0048: mov bword ptr [rax], rcx Generating: N425 ( 3, 2) [001189] ------------ t1189 = LCL_VAR byref V102 tmp93 u:3 rax (last use) REG rax $2dc /--* t1189 byref Generating: N427 (???,???) [001495] -c---------- t1495 = * LEA(b+8) byref REG NA Generating: N429 ( 3, 2) [001193] -------N---- t1193 = LCL_VAR int V86 tmp77 u:3 rdx (last use) REG rdx /--* t1495 byref +--* t1193 int Generating: N431 (???,???) [001464] -A--------L- * STOREIND int REG NA V102 in reg rax is becoming dead [001189] Live regs: 0000C0E5 {rax rdx rbp rsi rdi r14 r15} => 0000C0E4 {rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64 V86 V102} => {V00 V01 V62 V63 V64 V86} Byref regs: 000080C1 {rax rsi rdi r15} => 000080C0 {rsi rdi r15} V86 in reg rdx is becoming dead [001193] Live regs: 0000C0E4 {rdx rbp rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64 V86} => {V00 V01 V62 V63 V64} IN0049: mov dword ptr [rax+8], edx Generating: N433 ( 3, 2) [001196] -------N---- t1196 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx IN004a: lea rcx, bword ptr [V97 rsp+38H] Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} /--* t1196 byref Generating: N435 (???,???) [001496] ------------ t1496 = * PUTARG_REG byref REG rcx Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C0 {rsi rdi r15} Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Generating: N437 ( 3, 2) [001199] -------N---- t1199 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx IN004b: lea rdx, bword ptr [V99 rsp+28H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1199 byref Generating: N439 (???,???) [001497] ------------ t1497 = * PUTARG_REG byref REG rdx Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1496 byref arg0 in rcx +--* t1497 byref arg1 in rdx Generating: N441 ( 80, 55) [000574] --CXG------- t574 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e0 Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C4 {rdx rsi rdi r15} Byref regs: 000080C4 {rdx rsi rdi r15} => 000080C0 {rsi rdi r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} IN004c: call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int Generating: N443 ( 1, 1) [000581] -c---------- t581 = CNS_INT int 0 REG NA $40 /--* t574 int +--* t581 int Generating: N445 ( 85, 57) [000582] ---XG------- t582 = * EQ int REG r12 $31e IN004d: test eax, eax IN004e: sete r12b IN004f: movzx r12, r12b /--* t582 int Generating: N447 ( 89, 60) [000584] DA-XG------- * STORE_LCL_VAR int V37 tmp28 d:4 r12 REG r12 V37 in reg r12 is becoming live [000584] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V62 V63 V64} => {V00 V01 V37 V62 V63 V64} Scope info: end block BB18, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB19 [02A..02B) -> BB21 (cond), preds={BB15,BB17,BB18} succs={BB20,BB21} flags=0x00000000.40030020: i label target LIR BB19 IN (6)={V00 V01 V62 V64 V63 V37} + ByrefExposed + GcHeap OUT(5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap Recording Var Locations at start of BB19 V00(rsi) V01(rdi) V62(rbp) V64(r14) V63(r15) V37(r12) Liveness not changing: 000000000100048B {V00 V01 V37 V62 V63 V64} Live regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB19: G_M57450_IG08: ; offs=000101H, funclet=00 Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} Scope info: begin block BB19, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x0033 STACK_EMPTY (G_M57450_IG09,ins#0,ofs#0) label Generating: N451 ( 7, 6) [000059] ------------ IL_OFFSET void IL offset: 0x33 REG NA Generating: N453 ( 3, 2) [000055] ------------ t55 = LCL_VAR int V37 tmp28 u:6 r12 (last use) REG r12 $501 Generating: N455 ( 1, 1) [000056] -c---------- t56 = CNS_INT int 0 REG NA $40 /--* t55 int +--* t56 int Generating: N457 ( 5, 4) [000057] J------N---- * EQ void REG NA $31f V37 in reg r12 is becoming dead [000055] Live regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V00 V01 V37 V62 V63 V64} => {V00 V01 V62 V63 V64} IN0050: test r12d, r12d Generating: N459 ( 7, 6) [000058] ------------ * JTRUE void REG NA IN0051: je L_M57450_BB21 Scope info: end block BB19, IL range [02A..02B) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB20 [037..03F) -> BB36 (always), preds={BB19} succs={BB36} flags=0x00000000.40000020: i LIR BB20 IN (1)={V01 } OUT(1)={ V05} Recording Var Locations at start of BB20 V01(rdi) Change life 000000000000048B {V00 V01 V62 V63 V64} -> 0000000000000002 {V01} V00 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V62 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V64 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V63 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB20: Scope info: begin block BB20, IL range [037..03F) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x0038 STACK_EMPTY (G_M57450_IG09,ins#2,ofs#9) label Generating: N463 ( 6, 5) [000150] ------------ IL_OFFSET void IL offset: 0x38 REG NA Generating: N465 ( 1, 1) [000146] ------------ t146 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 Generating: N467 ( 1, 1) [000147] -c---------- t147 = CNS_INT int 0 REG NA $40 /--* t146 byref +--* t147 int Generating: N469 (???,???) [001465] -A-XG------- * STOREIND byte REG NA V01 in reg rdi is becoming dead [000146] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0052: mov byte ptr [rdi], 0 Added IP mapping: 0x003B STACK_EMPTY (G_M57450_IG09,ins#3,ofs#12) Generating: N471 ( 1, 3) [000154] ------------ IL_OFFSET void IL offset: 0x3b REG NA Generating: N473 ( 1, 1) [000151] -c---------- t151 = CNS_INT int 1 REG NA $41 /--* t151 int Generating: N475 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR int V05 loc3 d:6 rax REG rax IN0053: mov eax, 1 V05 in reg rax is becoming live [000153] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V05} Scope info: end block BB20, IL range [037..03F) Scope info: open scopes = IN0054: jmp L_M57450_BB36 =============== Generating BB21 [03F..054) -> BB23 (cond), preds={BB19} succs={BB22,BB23} flags=0x00000000.400b0020: i label target gcsafe LIR BB21 IN (5)={V00 V01 V62 V64 V63 } + ByrefExposed + GcHeap OUT(7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap Recording Var Locations at start of BB21 V00(rsi) V01(rdi) V62(rbp) V64(r14) V63(r15) Change life 0000000000000010 {V05} -> 000000000000048B {V00 V01 V62 V63 V64} V05 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V01 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V62 in reg rbp is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000000E0 {rbp rsi rdi} V64 in reg r14 is becoming live [------] Live regs: 000000E0 {rbp rsi rdi} => 000040E0 {rbp rsi rdi r14} V63 in reg r15 is becoming live [------] Live regs: 000040E0 {rbp rsi rdi r14} => 0000C0E0 {rbp rsi rdi r14 r15} Live regs: (unchanged) 0000C0E0 {rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 000080C0 {rsi rdi r15} L_M57450_BB21: G_M57450_IG09: ; offs=000131H, funclet=00 Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} Scope info: begin block BB21, IL range [03F..054) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x003F STACK_EMPTY (G_M57450_IG10,ins#0,ofs#0) label Generating: N479 ( 38, 21) [000069] ------------ IL_OFFSET void IL offset: 0x3f REG NA Generating: N481 ( 5, 4) [001206] -----O----L- NOP void REG NA Generating: N483 ( 1, 1) [000061] ------------ t61 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t61 byref Generating: N485 ( 3, 2) [000064] xc-----N---- t64 = * IND struct REG NA Generating: N487 ( 3, 2) [001203] Dc-----N---- t1203 = LCL_VAR_ADDR byref V97 tmp88 NA REG NA /--* t1203 byref +--* t64 struct Generating: N489 (???,???) [001466] xA--------L- * STORE_BLK(16) struct (copy) (Unroll) REG NA IN0055: movdqu xmm0, qword ptr [rsi] IN0056: movdqu qword ptr [V97 rsp+38H], xmm0 Generating: N491 ( 3, 2) [001207] ------------ t1207 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1207 byref Generating: N493 (???,???) [001498] ------------ t1498 = * PUTARG_REG byref REG rcx G_M57450_IG10: ; offs=000147H, funclet=00 IN0057: mov rcx, rsi Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Generating: N495 ( 3, 2) [001209] -------N---- t1209 = LCL_VAR_ADDR byref V97 tmp88 rdx REG rdx IN0058: lea rdx, bword ptr [V97 rsp+38H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1209 byref Generating: N497 (???,???) [001499] ------------ t1499 = * PUTARG_REG byref REG rdx Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1498 byref arg0 in rcx +--* t1499 byref arg1 in rdx Generating: N499 ( 38, 21) [000062] S-CXG------- * CALL void System.Boolean.TrimWhiteSpaceAndNull $VN.Void Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C4 {rdx rsi rdi r15} Byref regs: 000080C4 {rdx rsi rdi r15} => 000080C0 {rsi rdi r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} IN0059: call System.Boolean:TrimWhiteSpaceAndNull(struct):struct Added IP mapping: 0x0047 STACK_EMPTY (G_M57450_IG11,ins#3,ofs#13) Generating: N501 ( 14, 10) [000732] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N503 ( 3, 2) [001216] -------N---- t1216 = LCL_VAR int V62 tmp53 u:3 rbp (last use) REG rbp $3c0 /--* t1216 int Generating: N505 ( 7, 5) [001217] DA---------- * STORE_LCL_VAR int V88 tmp79 d:3 rbp REG rbp V62 in reg rbp is becoming dead [001216] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V00 V01 V62 V63 V64} => {V00 V01 V63 V64} V88 in reg rbp is becoming live [001217] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64} => {V00 V01 V63 V64 V88} genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N507 ( 16, 13) [000736] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N509 ( 1, 1) [001221] ------------ t1221 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1221 byref Generating: N511 (???,???) [001500] -c---------- t1500 = * LEA(b+0) byref REG NA /--* t1500 byref Generating: N513 ( 4, 3) [001224] x----------- t1224 = * IND byref REG rcx IN005a: mov rcx, bword ptr [rsi] Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} /--* t1224 byref Generating: N515 ( 8, 6) [001225] DA---------- * STORE_LCL_VAR byref V89 tmp80 d:3 rcx REG rcx Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C0 {rsi rdi r15} V89 in reg rcx is becoming live [001225] Live regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88} => {V00 V01 V63 V64 V88 V89} Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Generating: N517 ( 1, 1) [001227] ------------ t1227 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1227 byref Generating: N519 (???,???) [001501] -c---------- t1501 = * LEA(b+8) byref REG NA /--* t1501 byref Generating: N521 ( 4, 4) [001230] x----------- t1230 = * IND int REG rdx IN005b: mov edx, dword ptr [rsi+8] /--* t1230 int Generating: N523 ( 8, 7) [001231] DA---------- * STORE_LCL_VAR int V90 tmp81 d:3 rdx REG rdx V90 in reg rdx is becoming live [001231] Live regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89} => {V00 V01 V63 V64 V88 V89 V90} genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N525 ( 14, 8) [000679] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N527 ( 3, 2) [000672] ------------ t672 = LCL_VAR int V88 tmp79 u:3 rbp REG rbp $3c0 Generating: N529 ( 3, 2) [000770] ------------ t770 = LCL_VAR int V90 tmp81 u:3 rdx REG rdx /--* t672 int +--* t770 int Generating: N531 ( 10, 5) [000674] ------------ t674 = * NE int REG rax IN005c: cmp ebp, edx IN005d: setne al IN005e: movzx rax, al /--* t674 int Generating: N533 ( 14, 8) [000678] DA---------- * STORE_LCL_VAR int V44 tmp35 d:3 rax REG rax V44 in reg rax is becoming live [000678] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89 V90} => {V00 V01 V44 V63 V64 V88 V89 V90} genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N535 ( 7, 6) [000684] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N537 ( 3, 2) [000680] ------------ t680 = LCL_VAR int V44 tmp35 u:3 rax (last use) REG rax Generating: N539 ( 1, 1) [000681] -c---------- t681 = CNS_INT int 0 REG NA $40 /--* t680 int +--* t681 int Generating: N541 ( 5, 4) [000682] J------N---- * EQ void REG NA V44 in reg rax is becoming dead [000680] Live regs: 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V44 V63 V64 V88 V89 V90} => {V00 V01 V63 V64 V88 V89 V90} IN005f: test eax, eax Generating: N543 ( 7, 6) [000683] ------------ * JTRUE void REG NA IN0060: je L_M57450_BB23 Scope info: end block BB21, IL range [03F..054) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB22 [047..048) -> BB26 (always), preds={BB21} succs={BB26} flags=0x00000000.40080020: i gcsafe LIR BB22 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap Recording Var Locations at start of BB22 V00(rsi) V01(rdi) V64(r14) V63(r15) Change life 0000080008002483 {V00 V01 V63 V64 V88 V89 V90} -> 0000000000000483 {V00 V01 V63 V64} V90 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V88 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V89 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0C0 {rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB22: Scope info: begin block BB22, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N547 ( 5, 4) [000728] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N549 ( 1, 1) [000725] ------------ t725 = CNS_INT int 0 REG rbx $40 IN0061: xor ebx, ebx /--* t725 int Generating: N551 ( 5, 4) [000727] DA---------- * STORE_LCL_VAR int V46 tmp37 d:6 rbx REG rbx V46 in reg rbx is becoming live [000727] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Scope info: end block BB22, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN0062: jmp L_M57450_BB26 =============== Generating BB23 [047..048) -> BB25 (cond), preds={BB21} succs={BB24,BB25} flags=0x00000000.400b0020: i label target gcsafe LIR BB23 IN (7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap OUT(7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V00(rsi) V01(rdi) V64(r14) V63(r15) V90(rdx) V88(rbp) V89(rcx) Change life 0000000002000483 {V00 V01 V46 V63 V64} -> 0000080008002483 {V00 V01 V63 V64 V88 V89 V90} V46 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V90 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V88 in reg rbp is becoming live [------] Live regs: 00000004 {rdx} => 00000024 {rdx rbp} V89 in reg rcx is becoming live [------] Live regs: 00000024 {rdx rbp} => 00000026 {rcx rdx rbp} Live regs: 00000026 {rcx rdx rbp} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000002 {rcx} => 000080C2 {rcx rsi rdi r15} L_M57450_BB23: G_M57450_IG11: ; offs=000151H, funclet=00 Label: IG12, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15} Scope info: begin block BB23, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N555 ( 12, 7) [000695] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N557 ( 3, 2) [000783] ------------ t783 = LCL_VAR int V90 tmp81 u:3 rdx REG rdx Generating: N559 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 REG NA $40 /--* t783 int +--* t691 int Generating: N561 ( 8, 4) [000692] ------------ t692 = * EQ int REG rax IN0063: test edx, edx IN0064: sete al IN0065: movzx rax, al /--* t692 int Generating: N563 ( 12, 7) [000694] DA---------- * STORE_LCL_VAR int V45 tmp36 d:3 rax REG rax V45 in reg rax is becoming live [000694] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89 V90} => {V00 V01 V45 V63 V64 V88 V89 V90} genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N565 ( 7, 6) [000700] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N567 ( 3, 2) [000696] ------------ t696 = LCL_VAR int V45 tmp36 u:3 rax (last use) REG rax Generating: N569 ( 1, 1) [000697] -c---------- t697 = CNS_INT int 0 REG NA $40 /--* t696 int +--* t697 int Generating: N571 ( 5, 4) [000698] J------N---- * EQ void REG NA V45 in reg rax is becoming dead [000696] Live regs: 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V45 V63 V64 V88 V89 V90} => {V00 V01 V63 V64 V88 V89 V90} IN0066: test eax, eax Generating: N573 ( 7, 6) [000699] ------------ * JTRUE void REG NA IN0067: je L_M57450_BB25 Scope info: end block BB23, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB24 [047..048) -> BB26 (always), preds={BB23} succs={BB26} flags=0x00000000.40080020: i gcsafe LIR BB24 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap Recording Var Locations at start of BB24 V00(rsi) V01(rdi) V64(r14) V63(r15) Change life 0000080008002483 {V00 V01 V63 V64 V88 V89 V90} -> 0000000000000483 {V00 V01 V63 V64} V90 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V88 in reg rbp is becoming dead [------] Live regs: (unchanged) 00000000 {} V89 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000C0C0 {rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB24: Scope info: begin block BB24, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N577 ( 5, 4) [000723] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N579 ( 1, 1) [000720] -c---------- t720 = CNS_INT int 1 REG NA $41 /--* t720 int Generating: N581 ( 5, 4) [000722] DA---------- * STORE_LCL_VAR int V46 tmp37 d:5 rbx REG rbx IN0068: mov ebx, 1 V46 in reg rbx is becoming live [000722] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Scope info: end block BB24, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) IN0069: jmp L_M57450_BB26 =============== Generating BB25 [047..048), preds={BB23} succs={BB26} flags=0x00000000.400b0020: i label target gcsafe LIR BB25 IN (7)={V00 V01 V64 V63 V90 V88 V89} + ByrefExposed + GcHeap OUT(5)={V00 V01 V64 V63 V46 } + ByrefExposed + GcHeap Recording Var Locations at start of BB25 V00(rsi) V01(rdi) V64(r14) V63(r15) V90(rdx) V88(rbp) V89(rcx) Change life 0000000002000483 {V00 V01 V46 V63 V64} -> 0000080008002483 {V00 V01 V63 V64 V88 V89 V90} V46 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V90 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V88 in reg rbp is becoming live [------] Live regs: 00000004 {rdx} => 00000024 {rdx rbp} V89 in reg rcx is becoming live [------] Live regs: 00000024 {rdx rbp} => 00000026 {rcx rdx rbp} Live regs: 00000026 {rcx rdx rbp} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000002 {rcx} => 000080C2 {rcx rsi rdi r15} L_M57450_BB25: G_M57450_IG12: ; offs=00017BH, funclet=00 Label: IG13, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15} Scope info: begin block BB25, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N585 ( 89, 60) [000715] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N587 ( 3, 2) [001242] -------N---- t1242 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax IN006a: lea rax, bword ptr [V97 rsp+38H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} /--* t1242 byref Generating: N589 ( 7, 6) [001244] DA---------- * STORE_LCL_VAR byref V104 tmp95 d:3 rax REG rax Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} V104 in reg rax is becoming live [001244] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89 V90} => {V00 V01 V63 V64 V88 V89 V90 V104} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} Generating: N591 ( 3, 2) [001245] ------------ t1245 = LCL_VAR byref V104 tmp95 u:3 rax REG rax $2e5 /--* t1245 byref Generating: N593 (???,???) [001502] -c---------- t1502 = * LEA(b+0) byref REG NA Generating: N595 ( 3, 2) [001249] -------N---- t1249 = LCL_VAR byref V63 tmp54 u:3 r15 REG r15 $VN.Null /--* t1502 byref +--* t1249 byref Generating: N597 (???,???) [001467] -A---------- * STOREIND byref REG NA IN006b: mov bword ptr [rax], r15 Generating: N599 ( 3, 2) [001252] ------------ t1252 = LCL_VAR byref V104 tmp95 u:3 rax (last use) REG rax $2e5 /--* t1252 byref Generating: N601 (???,???) [001503] -c---------- t1503 = * LEA(b+8) byref REG NA Generating: N603 ( 3, 2) [001256] -------N---- t1256 = LCL_VAR int V88 tmp79 u:3 rbp (last use) REG rbp $3c0 /--* t1503 byref +--* t1256 int Generating: N605 (???,???) [001468] -A--------L- * STOREIND int REG NA V104 in reg rax is becoming dead [001252] Live regs: 0000C0E7 {rax rcx rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89 V90 V104} => {V00 V01 V63 V64 V88 V89 V90} Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} V88 in reg rbp is becoming dead [001256] Live regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0C6 {rcx rdx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V88 V89 V90} => {V00 V01 V63 V64 V89 V90} IN006c: mov dword ptr [rax+8], ebp Generating: N607 ( 3, 2) [001263] -------N---- t1263 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax IN006d: lea rax, bword ptr [V99 rsp+28H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} /--* t1263 byref Generating: N609 ( 7, 6) [001265] DA---------- * STORE_LCL_VAR byref V105 tmp96 d:3 rax REG rax Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} V105 in reg rax is becoming live [001265] Live regs: 0000C0C6 {rcx rdx rsi rdi r14 r15} => 0000C0C7 {rax rcx rdx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V89 V90} => {V00 V01 V63 V64 V89 V90 V105} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C3 {rax rcx rsi rdi r15} Generating: N611 ( 3, 2) [001266] ------------ t1266 = LCL_VAR byref V105 tmp96 u:3 rax REG rax $2e7 /--* t1266 byref Generating: N613 (???,???) [001504] -c---------- t1504 = * LEA(b+0) byref REG NA Generating: N615 ( 3, 2) [001270] -------N---- t1270 = LCL_VAR byref V89 tmp80 u:3 rcx (last use) REG rcx /--* t1504 byref +--* t1270 byref Generating: N617 (???,???) [001469] -A---------- * STOREIND byref REG NA V89 in reg rcx is becoming dead [001270] Live regs: 0000C0C7 {rax rcx rdx rsi rdi r14 r15} => 0000C0C5 {rax rdx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V89 V90 V105} => {V00 V01 V63 V64 V90 V105} Byref regs: 000080C3 {rax rcx rsi rdi r15} => 000080C1 {rax rsi rdi r15} IN006e: mov bword ptr [rax], rcx Generating: N619 ( 3, 2) [001273] ------------ t1273 = LCL_VAR byref V105 tmp96 u:3 rax (last use) REG rax $2e7 /--* t1273 byref Generating: N621 (???,???) [001505] -c---------- t1505 = * LEA(b+8) byref REG NA Generating: N623 ( 3, 2) [001277] -------N---- t1277 = LCL_VAR int V90 tmp81 u:3 rdx (last use) REG rdx /--* t1505 byref +--* t1277 int Generating: N625 (???,???) [001470] -A--------L- * STOREIND int REG NA V105 in reg rax is becoming dead [001273] Live regs: 0000C0C5 {rax rdx rsi rdi r14 r15} => 0000C0C4 {rdx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V90 V105} => {V00 V01 V63 V64 V90} Byref regs: 000080C1 {rax rsi rdi r15} => 000080C0 {rsi rdi r15} V90 in reg rdx is becoming dead [001277] Live regs: 0000C0C4 {rdx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V00 V01 V63 V64 V90} => {V00 V01 V63 V64} IN006f: mov dword ptr [rax+8], edx Generating: N627 ( 3, 2) [001280] -------N---- t1280 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx IN0070: lea rcx, bword ptr [V97 rsp+38H] Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} /--* t1280 byref Generating: N629 (???,???) [001506] ------------ t1506 = * PUTARG_REG byref REG rcx Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C0 {rsi rdi r15} Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Generating: N631 ( 3, 2) [001283] -------N---- t1283 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx IN0071: lea rdx, bword ptr [V99 rsp+28H] Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1283 byref Generating: N633 (???,???) [001507] ------------ t1507 = * PUTARG_REG byref REG rdx Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C6 {rcx rdx rsi rdi r15} /--* t1506 byref arg0 in rcx +--* t1507 byref arg1 in rdx Generating: N635 ( 80, 55) [000704] --CXG------- t704 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1e9 Byref regs: 000080C6 {rcx rdx rsi rdi r15} => 000080C4 {rdx rsi rdi r15} Byref regs: 000080C4 {rdx rsi rdi r15} => 000080C0 {rsi rdi r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} IN0072: call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int Generating: N637 ( 1, 1) [000711] -c---------- t711 = CNS_INT int 0 REG NA $40 /--* t704 int +--* t711 int Generating: N639 ( 85, 57) [000712] ---XG------- t712 = * EQ int REG rbx $328 IN0073: test eax, eax IN0074: sete bl IN0075: movzx rbx, bl /--* t712 int Generating: N641 ( 89, 60) [000714] DA-XG------- * STORE_LCL_VAR int V46 tmp37 d:4 rbx REG rbx V46 in reg rbx is becoming live [000714] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C8 {rbx rsi rdi r14 r15} Live vars: {V00 V01 V63 V64} => {V00 V01 V46 V63 V64} Scope info: end block BB25, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB26 [047..048) -> BB28 (cond), preds={BB22,BB24,BB25} succs={BB27,BB28} flags=0x00000000.400b0020: i label target gcsafe LIR BB26 IN (5)={V00 V01 V64 V63 V46} + ByrefExposed + GcHeap OUT(4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap Recording Var Locations at start of BB26 V00(rsi) V01(rdi) V64(r14) V63(r15) V46(rbx) Liveness not changing: 0000000002000483 {V00 V01 V46 V63 V64} Live regs: 00000000 {} => 0000C0C8 {rbx rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 000080C0 {rsi rdi r15} L_M57450_BB26: G_M57450_IG13: ; offs=000195H, funclet=00 Label: IG14, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} Scope info: begin block BB26, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x0050 STACK_EMPTY (G_M57450_IG14,ins#0,ofs#0) label Generating: N645 ( 7, 6) [000089] ------------ IL_OFFSET void IL offset: 0x50 REG NA Generating: N647 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V46 tmp37 u:3 rbx (last use) REG rbx $502 Generating: N649 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 0 REG NA $40 /--* t85 int +--* t86 int Generating: N651 ( 5, 4) [000087] J------N---- * EQ void REG NA $329 V46 in reg rbx is becoming dead [000085] Live regs: 0000C0C8 {rbx rsi rdi r14 r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V00 V01 V46 V63 V64} => {V00 V01 V63 V64} IN0076: test ebx, ebx Generating: N653 ( 7, 6) [000088] ------------ * JTRUE void REG NA IN0077: je L_M57450_BB28 Scope info: end block BB26, IL range [047..048) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) =============== Generating BB27 [054..05C) -> BB36 (always), preds={BB26} succs={BB36} flags=0x00000000.40080020: i gcsafe LIR BB27 IN (1)={V01 } OUT(1)={ V05} Recording Var Locations at start of BB27 V01(rdi) Change life 0000000000000483 {V00 V01 V63 V64} -> 0000000000000002 {V01} V00 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V64 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V63 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB27: Scope info: begin block BB27, IL range [054..05C) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x0055 STACK_EMPTY (G_M57450_IG14,ins#2,ofs#8) label Generating: N657 ( 6, 5) [000140] ------------ IL_OFFSET void IL offset: 0x55 REG NA Generating: N659 ( 1, 1) [000136] ------------ t136 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 Generating: N661 ( 1, 1) [000137] -c---------- t137 = CNS_INT int 1 REG NA $41 /--* t136 byref +--* t137 int Generating: N663 (???,???) [001471] -A-XG------- * STOREIND byte REG NA V01 in reg rdi is becoming dead [000136] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0078: mov byte ptr [rdi], 1 Added IP mapping: 0x0058 STACK_EMPTY (G_M57450_IG14,ins#3,ofs#11) Generating: N665 ( 1, 3) [000144] ------------ IL_OFFSET void IL offset: 0x58 REG NA Generating: N667 ( 1, 1) [000141] -c---------- t141 = CNS_INT int 1 REG NA $41 /--* t141 int Generating: N669 ( 1, 3) [000143] DA---------- * STORE_LCL_VAR int V05 loc3 d:5 rax REG rax IN0079: mov eax, 1 V05 in reg rax is becoming live [000143] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V05} Scope info: end block BB27, IL range [054..05C) Scope info: open scopes = IN007a: jmp L_M57450_BB36 =============== Generating BB28 [05C..069) -> BB30 (cond), preds={BB26} succs={BB29,BB30} flags=0x00000000.400b0020: i label target gcsafe LIR BB28 IN (4)={V00 V01 V64 V63 } + ByrefExposed + GcHeap OUT(5)={ V01 V94 V92 V91 V93} + ByrefExposed + GcHeap Recording Var Locations at start of BB28 V00(rsi) V01(rdi) V64(r14) V63(r15) Change life 0000000000000010 {V05} -> 0000000000000483 {V00 V01 V63 V64} V05 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V01 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} V64 in reg r14 is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000040C0 {rsi rdi r14} V63 in reg r15 is becoming live [------] Live regs: 000040C0 {rsi rdi r14} => 0000C0C0 {rsi rdi r14 r15} Live regs: (unchanged) 0000C0C0 {rsi rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 000080C0 {rsi rdi r15} L_M57450_BB28: G_M57450_IG14: ; offs=0001C2H, funclet=00 Label: IG15, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15} Scope info: begin block BB28, IL range [05C..069) Scope info: open scopes = 0 (V00 arg0) [000..07A) 1 (V01 arg1) [000..07A) Added IP mapping: 0x005C STACK_EMPTY (G_M57450_IG15,ins#0,ofs#0) label Generating: N673 ( 14, 10) [000862] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N675 ( 3, 2) [001288] -------N---- t1288 = LCL_VAR byref V63 tmp54 u:3 r15 (last use) REG r15 $VN.Null /--* t1288 byref Generating: N677 ( 7, 5) [001289] DA---------- * STORE_LCL_VAR byref V91 tmp82 d:3 r15 REG r15 V63 in reg r15 is becoming dead [001288] Live regs: 0000C0C0 {rsi rdi r14 r15} => 000040C0 {rsi rdi r14} Live vars: {V00 V01 V63 V64} => {V00 V01 V64} Byref regs: 000080C0 {rsi rdi r15} => 000000C0 {rsi rdi} V91 in reg r15 is becoming live [001289] Live regs: 000040C0 {rsi rdi r14} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V00 V01 V64} => {V00 V01 V64 V91} Byref regs: 000000C0 {rsi rdi} => 000080C0 {rsi rdi r15} Generating: N679 ( 3, 2) [001291] -------N---- t1291 = LCL_VAR int V64 tmp55 u:3 r14 (last use) REG r14 $3c2 /--* t1291 int Generating: N681 ( 7, 5) [001292] DA---------- * STORE_LCL_VAR int V92 tmp83 d:3 r14 REG r14 V64 in reg r14 is becoming dead [001291] Live regs: 0000C0C0 {rsi rdi r14 r15} => 000080C0 {rsi rdi r15} Live vars: {V00 V01 V64 V91} => {V00 V01 V91} V92 in reg r14 is becoming live [001292] Live regs: 000080C0 {rsi rdi r15} => 0000C0C0 {rsi rdi r14 r15} Live vars: {V00 V01 V91} => {V00 V01 V91 V92} genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N683 ( 16, 13) [000866] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N685 ( 1, 1) [001296] ------------ t1296 = LCL_VAR byref V00 arg0 u:2 rsi REG rsi $80 /--* t1296 byref Generating: N687 (???,???) [001508] -c---------- t1508 = * LEA(b+0) byref REG NA /--* t1508 byref Generating: N689 ( 4, 3) [001299] x----------- t1299 = * IND byref REG rcx IN007b: mov rcx, bword ptr [rsi] Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} /--* t1299 byref Generating: N691 ( 8, 6) [001300] DA---------- * STORE_LCL_VAR byref V93 tmp84 d:3 rcx REG rcx Byref regs: 000080C2 {rcx rsi rdi r15} => 000080C0 {rsi rdi r15} V93 in reg rcx is becoming live [001300] Live regs: 0000C0C0 {rsi rdi r14 r15} => 0000C0C2 {rcx rsi rdi r14 r15} Live vars: {V00 V01 V91 V92} => {V00 V01 V91 V92 V93} Byref regs: 000080C0 {rsi rdi r15} => 000080C2 {rcx rsi rdi r15} Generating: N693 ( 1, 1) [001302] ------------ t1302 = LCL_VAR byref V00 arg0 u:2 rsi (last use) REG rsi $80 /--* t1302 byref Generating: N695 (???,???) [001509] -c---------- t1509 = * LEA(b+8) byref REG NA /--* t1509 byref Generating: N697 ( 4, 4) [001305] x----------- t1305 = * IND int REG rdx V00 in reg rsi is becoming dead [001302] Live regs: 0000C0C2 {rcx rsi rdi r14 r15} => 0000C082 {rcx rdi r14 r15} Live vars: {V00 V01 V91 V92 V93} => {V01 V91 V92 V93} Byref regs: 000080C2 {rcx rsi rdi r15} => 00008082 {rcx rdi r15} IN007c: mov edx, dword ptr [rsi+8] /--* t1305 int Generating: N699 ( 8, 7) [001306] DA---------- * STORE_LCL_VAR int V94 tmp85 d:3 rdx REG rdx V94 in reg rdx is becoming live [001306] Live regs: 0000C082 {rcx rdi r14 r15} => 0000C086 {rcx rdx rdi r14 r15} Live vars: {V01 V91 V92 V93} => {V01 V91 V92 V93 V94} genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N701 ( 14, 8) [000809] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N703 ( 3, 2) [000802] ------------ t802 = LCL_VAR int V92 tmp83 u:3 r14 REG r14 $3c2 Generating: N705 ( 3, 2) [000900] ------------ t900 = LCL_VAR int V94 tmp85 u:3 rdx REG rdx /--* t802 int +--* t900 int Generating: N707 ( 10, 5) [000804] ------------ t804 = * NE int REG rax IN007d: cmp r14d, edx IN007e: setne al IN007f: movzx rax, al /--* t804 int Generating: N709 ( 14, 8) [000808] DA---------- * STORE_LCL_VAR int V53 tmp44 d:3 rax REG rax V53 in reg rax is becoming live [000808] Live regs: 0000C086 {rcx rdx rdi r14 r15} => 0000C087 {rax rcx rdx rdi r14 r15} Live vars: {V01 V91 V92 V93 V94} => {V01 V53 V91 V92 V93 V94} genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N711 ( 7, 6) [000814] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N713 ( 3, 2) [000810] ------------ t810 = LCL_VAR int V53 tmp44 u:3 rax (last use) REG rax Generating: N715 ( 1, 1) [000811] -c---------- t811 = CNS_INT int 0 REG NA $40 /--* t810 int +--* t811 int Generating: N717 ( 5, 4) [000812] J------N---- * EQ void REG NA V53 in reg rax is becoming dead [000810] Live regs: 0000C087 {rax rcx rdx rdi r14 r15} => 0000C086 {rcx rdx rdi r14 r15} Live vars: {V01 V53 V91 V92 V93 V94} => {V01 V91 V92 V93 V94} IN0080: test eax, eax Generating: N719 ( 7, 6) [000813] ------------ * JTRUE void REG NA IN0081: je L_M57450_BB30 Scope info: end block BB28, IL range [05C..069) Scope info: open scopes = 1 (V01 arg1) [000..07A) =============== Generating BB29 [05C..05D) -> BB33 (always), preds={BB28} succs={BB33} flags=0x00000000.40080020: i gcsafe LIR BB29 IN (1)={V01 } OUT(2)={V01 V55} Recording Var Locations at start of BB29 V01(rdi) Change life 0000300010004002 {V01 V91 V92 V93 V94} -> 0000000000000002 {V01} V94 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V92 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V91 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V93 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB29: Scope info: begin block BB29, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N723 ( 5, 4) [000858] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N725 ( 1, 1) [000855] ------------ t855 = CNS_INT int 0 REG rsi $40 IN0082: xor esi, esi /--* t855 int Generating: N727 ( 5, 4) [000857] DA---------- * STORE_LCL_VAR int V55 tmp46 d:6 rsi REG rsi V55 in reg rsi is becoming live [000857] Live regs: 00000080 {rdi} => 000000C0 {rsi rdi} Live vars: {V01} => {V01 V55} Scope info: end block BB29, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) IN0083: jmp L_M57450_BB33 =============== Generating BB30 [05C..05D) -> BB32 (cond), preds={BB28} succs={BB31,BB32} flags=0x00000000.400b0020: i label target gcsafe LIR BB30 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap Recording Var Locations at start of BB30 V01(rdi) V94(rdx) V92(r14) V91(r15) V93(rcx) Change life 0000000004000002 {V01 V55} -> 0000300010004002 {V01 V91 V92 V93 V94} V55 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V94 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V92 in reg r14 is becoming live [------] Live regs: 00000004 {rdx} => 00004004 {rdx r14} V91 in reg r15 is becoming live [------] Live regs: 00004004 {rdx r14} => 0000C004 {rdx r14 r15} V93 in reg rcx is becoming live [------] Live regs: 0000C004 {rdx r14 r15} => 0000C006 {rcx rdx r14 r15} Live regs: 0000C006 {rcx rdx r14 r15} => 0000C086 {rcx rdx rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00008002 {rcx r15} => 00008082 {rcx rdi r15} L_M57450_BB30: G_M57450_IG15: ; offs=0001D7H, funclet=00 Label: IG16, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15} Scope info: begin block BB30, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N731 ( 12, 7) [000825] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N733 ( 3, 2) [000913] ------------ t913 = LCL_VAR int V94 tmp85 u:3 rdx REG rdx Generating: N735 ( 1, 1) [000821] -c---------- t821 = CNS_INT int 0 REG NA $40 /--* t913 int +--* t821 int Generating: N737 ( 8, 4) [000822] ------------ t822 = * EQ int REG rax IN0084: test edx, edx IN0085: sete al IN0086: movzx rax, al /--* t822 int Generating: N739 ( 12, 7) [000824] DA---------- * STORE_LCL_VAR int V54 tmp45 d:3 rax REG rax V54 in reg rax is becoming live [000824] Live regs: 0000C086 {rcx rdx rdi r14 r15} => 0000C087 {rax rcx rdx rdi r14 r15} Live vars: {V01 V91 V92 V93 V94} => {V01 V54 V91 V92 V93 V94} genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N741 ( 7, 6) [000830] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N743 ( 3, 2) [000826] ------------ t826 = LCL_VAR int V54 tmp45 u:3 rax (last use) REG rax Generating: N745 ( 1, 1) [000827] -c---------- t827 = CNS_INT int 0 REG NA $40 /--* t826 int +--* t827 int Generating: N747 ( 5, 4) [000828] J------N---- * EQ void REG NA V54 in reg rax is becoming dead [000826] Live regs: 0000C087 {rax rcx rdx rdi r14 r15} => 0000C086 {rcx rdx rdi r14 r15} Live vars: {V01 V54 V91 V92 V93 V94} => {V01 V91 V92 V93 V94} IN0087: test eax, eax Generating: N749 ( 7, 6) [000829] ------------ * JTRUE void REG NA IN0088: je L_M57450_BB32 Scope info: end block BB30, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) =============== Generating BB31 [05C..05D) -> BB33 (always), preds={BB30} succs={BB33} flags=0x00000000.40080020: i gcsafe LIR BB31 IN (1)={V01 } OUT(2)={V01 V55} Recording Var Locations at start of BB31 V01(rdi) Change life 0000300010004002 {V01 V91 V92 V93 V94} -> 0000000000000002 {V01} V94 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V92 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V91 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V93 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB31: Scope info: begin block BB31, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N753 ( 5, 4) [000853] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N755 ( 1, 1) [000850] -c---------- t850 = CNS_INT int 1 REG NA $41 /--* t850 int Generating: N757 ( 5, 4) [000852] DA---------- * STORE_LCL_VAR int V55 tmp46 d:5 rsi REG rsi IN0089: mov esi, 1 V55 in reg rsi is becoming live [000852] Live regs: 00000080 {rdi} => 000000C0 {rsi rdi} Live vars: {V01} => {V01 V55} Scope info: end block BB31, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) IN008a: jmp L_M57450_BB33 =============== Generating BB32 [05C..05D), preds={BB30} succs={BB33} flags=0x00000000.400b0020: i label target gcsafe LIR BB32 IN (5)={V01 V94 V92 V91 V93} + ByrefExposed + GcHeap OUT(2)={V01 V55 } Recording Var Locations at start of BB32 V01(rdi) V94(rdx) V92(r14) V91(r15) V93(rcx) Change life 0000000004000002 {V01 V55} -> 0000300010004002 {V01 V91 V92 V93 V94} V55 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V94 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V92 in reg r14 is becoming live [------] Live regs: 00000004 {rdx} => 00004004 {rdx r14} V91 in reg r15 is becoming live [------] Live regs: 00004004 {rdx r14} => 0000C004 {rdx r14 r15} V93 in reg rcx is becoming live [------] Live regs: 0000C004 {rdx r14 r15} => 0000C006 {rcx rdx r14 r15} Live regs: 0000C006 {rcx rdx r14 r15} => 0000C086 {rcx rdx rdi r14 r15} GC regs: (unchanged) 00000000 {} Byref regs: 00008002 {rcx r15} => 00008082 {rcx rdi r15} L_M57450_BB32: G_M57450_IG16: ; offs=0001F5H, funclet=00 Label: IG17, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15} Scope info: begin block BB32, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) genIPmappingAdd: ignoring duplicate IL offset 0x5c Generating: N761 ( 89, 60) [000845] ------------ IL_OFFSET void IL offset: 0x5c REG NA Generating: N763 ( 3, 2) [001317] -------N---- t1317 = LCL_VAR_ADDR byref V97 tmp88 rax REG rax IN008b: lea rax, bword ptr [V97 rsp+38H] Byref regs: 00008082 {rcx rdi r15} => 00008083 {rax rcx rdi r15} /--* t1317 byref Generating: N765 ( 7, 6) [001319] DA---------- * STORE_LCL_VAR byref V106 tmp97 d:3 rax REG rax Byref regs: 00008083 {rax rcx rdi r15} => 00008082 {rcx rdi r15} V106 in reg rax is becoming live [001319] Live regs: 0000C086 {rcx rdx rdi r14 r15} => 0000C087 {rax rcx rdx rdi r14 r15} Live vars: {V01 V91 V92 V93 V94} => {V01 V91 V92 V93 V94 V106} Byref regs: 00008082 {rcx rdi r15} => 00008083 {rax rcx rdi r15} Generating: N767 ( 3, 2) [001320] ------------ t1320 = LCL_VAR byref V106 tmp97 u:3 rax REG rax $2ee /--* t1320 byref Generating: N769 (???,???) [001510] -c---------- t1510 = * LEA(b+0) byref REG NA Generating: N771 ( 3, 2) [001324] -------N---- t1324 = LCL_VAR byref V91 tmp82 u:3 r15 (last use) REG r15 $VN.Null /--* t1510 byref +--* t1324 byref Generating: N773 (???,???) [001472] -A---------- * STOREIND byref REG NA V91 in reg r15 is becoming dead [001324] Live regs: 0000C087 {rax rcx rdx rdi r14 r15} => 00004087 {rax rcx rdx rdi r14} Live vars: {V01 V91 V92 V93 V94 V106} => {V01 V92 V93 V94 V106} Byref regs: 00008083 {rax rcx rdi r15} => 00000083 {rax rcx rdi} IN008c: mov bword ptr [rax], r15 Generating: N775 ( 3, 2) [001327] ------------ t1327 = LCL_VAR byref V106 tmp97 u:3 rax (last use) REG rax $2ee /--* t1327 byref Generating: N777 (???,???) [001511] -c---------- t1511 = * LEA(b+8) byref REG NA Generating: N779 ( 3, 2) [001331] -------N---- t1331 = LCL_VAR int V92 tmp83 u:3 r14 (last use) REG r14 $3c2 /--* t1511 byref +--* t1331 int Generating: N781 (???,???) [001473] -A--------L- * STOREIND int REG NA V106 in reg rax is becoming dead [001327] Live regs: 00004087 {rax rcx rdx rdi r14} => 00004086 {rcx rdx rdi r14} Live vars: {V01 V92 V93 V94 V106} => {V01 V92 V93 V94} Byref regs: 00000083 {rax rcx rdi} => 00000082 {rcx rdi} V92 in reg r14 is becoming dead [001331] Live regs: 00004086 {rcx rdx rdi r14} => 00000086 {rcx rdx rdi} Live vars: {V01 V92 V93 V94} => {V01 V93 V94} IN008d: mov dword ptr [rax+8], r14d Generating: N783 ( 3, 2) [001338] -------N---- t1338 = LCL_VAR_ADDR byref V99 tmp90 rax REG rax IN008e: lea rax, bword ptr [V99 rsp+28H] Byref regs: 00000082 {rcx rdi} => 00000083 {rax rcx rdi} /--* t1338 byref Generating: N785 ( 7, 6) [001340] DA---------- * STORE_LCL_VAR byref V107 tmp98 d:3 rax REG rax Byref regs: 00000083 {rax rcx rdi} => 00000082 {rcx rdi} V107 in reg rax is becoming live [001340] Live regs: 00000086 {rcx rdx rdi} => 00000087 {rax rcx rdx rdi} Live vars: {V01 V93 V94} => {V01 V93 V94 V107} Byref regs: 00000082 {rcx rdi} => 00000083 {rax rcx rdi} Generating: N787 ( 3, 2) [001341] ------------ t1341 = LCL_VAR byref V107 tmp98 u:3 rax REG rax $2f0 /--* t1341 byref Generating: N789 (???,???) [001512] -c---------- t1512 = * LEA(b+0) byref REG NA Generating: N791 ( 3, 2) [001345] -------N---- t1345 = LCL_VAR byref V93 tmp84 u:3 rcx (last use) REG rcx /--* t1512 byref +--* t1345 byref Generating: N793 (???,???) [001474] -A---------- * STOREIND byref REG NA V93 in reg rcx is becoming dead [001345] Live regs: 00000087 {rax rcx rdx rdi} => 00000085 {rax rdx rdi} Live vars: {V01 V93 V94 V107} => {V01 V94 V107} Byref regs: 00000083 {rax rcx rdi} => 00000081 {rax rdi} IN008f: mov bword ptr [rax], rcx Generating: N795 ( 3, 2) [001348] ------------ t1348 = LCL_VAR byref V107 tmp98 u:3 rax (last use) REG rax $2f0 /--* t1348 byref Generating: N797 (???,???) [001513] -c---------- t1513 = * LEA(b+8) byref REG NA Generating: N799 ( 3, 2) [001352] -------N---- t1352 = LCL_VAR int V94 tmp85 u:3 rdx (last use) REG rdx /--* t1513 byref +--* t1352 int Generating: N801 (???,???) [001475] -A--------L- * STOREIND int REG NA V107 in reg rax is becoming dead [001348] Live regs: 00000085 {rax rdx rdi} => 00000084 {rdx rdi} Live vars: {V01 V94 V107} => {V01 V94} Byref regs: 00000081 {rax rdi} => 00000080 {rdi} V94 in reg rdx is becoming dead [001352] Live regs: 00000084 {rdx rdi} => 00000080 {rdi} Live vars: {V01 V94} => {V01} IN0090: mov dword ptr [rax+8], edx Generating: N803 ( 3, 2) [001355] -------N---- t1355 = LCL_VAR_ADDR byref V97 tmp88 rcx REG rcx IN0091: lea rcx, bword ptr [V97 rsp+38H] Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} /--* t1355 byref Generating: N805 (???,???) [001514] ------------ t1514 = * PUTARG_REG byref REG rcx Byref regs: 00000082 {rcx rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000082 {rcx rdi} Generating: N807 ( 3, 2) [001358] -------N---- t1358 = LCL_VAR_ADDR byref V99 tmp90 rdx REG rdx IN0092: lea rdx, bword ptr [V99 rsp+28H] Byref regs: 00000082 {rcx rdi} => 00000086 {rcx rdx rdi} /--* t1358 byref Generating: N809 (???,???) [001515] ------------ t1515 = * PUTARG_REG byref REG rdx Byref regs: 00000086 {rcx rdx rdi} => 00000082 {rcx rdi} Byref regs: 00000082 {rcx rdi} => 00000086 {rcx rdx rdi} /--* t1514 byref arg0 in rcx +--* t1515 byref arg1 in rdx Generating: N811 ( 80, 55) [000834] --CXG------- t834 = * CALL int System.Globalization.CompareInfo.CompareOrdinalIgnoreCase $1f2 Byref regs: 00000086 {rcx rdx rdi} => 00000084 {rdx rdi} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} IN0093: call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int Generating: N813 ( 1, 1) [000841] -c---------- t841 = CNS_INT int 0 REG NA $40 /--* t834 int +--* t841 int Generating: N815 ( 85, 57) [000842] ---XG------- t842 = * EQ int REG rsi $332 IN0094: test eax, eax IN0095: sete sil IN0096: movzx rsi, sil /--* t842 int Generating: N817 ( 89, 60) [000844] DA-XG------- * STORE_LCL_VAR int V55 tmp46 d:4 rsi REG rsi V55 in reg rsi is becoming live [000844] Live regs: 00000080 {rdi} => 000000C0 {rsi rdi} Live vars: {V01} => {V01 V55} Scope info: end block BB32, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) =============== Generating BB33 [05C..05D) -> BB35 (cond), preds={BB29,BB31,BB32} succs={BB34,BB35} flags=0x00000000.400b0020: i label target gcsafe LIR BB33 IN (2)={V01 V55} OUT(1)={V01 } Recording Var Locations at start of BB33 V01(rdi) V55(rsi) Liveness not changing: 0000000004000002 {V01 V55} Live regs: 00000000 {} => 000000C0 {rsi rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB33: G_M57450_IG17: ; offs=00020FH, funclet=00 Label: IG18, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} Scope info: begin block BB33, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x0065 STACK_EMPTY (G_M57450_IG18,ins#0,ofs#0) label Generating: N821 ( 7, 6) [000110] ------------ IL_OFFSET void IL offset: 0x65 REG NA Generating: N823 ( 3, 2) [000106] ------------ t106 = LCL_VAR int V55 tmp46 u:3 rsi (last use) REG rsi $503 Generating: N825 ( 1, 1) [000107] -c---------- t107 = CNS_INT int 0 REG NA $40 /--* t106 int +--* t107 int Generating: N827 ( 5, 4) [000108] J------N---- * EQ void REG NA $333 V55 in reg rsi is becoming dead [000106] Live regs: 000000C0 {rsi rdi} => 00000080 {rdi} Live vars: {V01 V55} => {V01} IN0097: test esi, esi Generating: N829 ( 7, 6) [000109] ------------ * JTRUE void REG NA IN0098: je L_M57450_BB35 Scope info: end block BB33, IL range [05C..05D) Scope info: open scopes = 1 (V01 arg1) [000..07A) =============== Generating BB34 [069..071) -> BB36 (always), preds={BB33} succs={BB36} flags=0x00000000.40080020: i gcsafe LIR BB34 IN (1)={V01 } OUT(1)={ V05} Recording Var Locations at start of BB34 V01(rdi) Liveness not changing: 0000000000000002 {V01} Live regs: 00000000 {} => 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00000080 {rdi} L_M57450_BB34: Scope info: begin block BB34, IL range [069..071) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x006A STACK_EMPTY (G_M57450_IG18,ins#2,ofs#8) label Generating: N833 ( 6, 5) [000130] ------------ IL_OFFSET void IL offset: 0x6a REG NA Generating: N835 ( 1, 1) [000126] ------------ t126 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 Generating: N837 ( 1, 1) [000127] -c---------- t127 = CNS_INT int 0 REG NA $40 /--* t126 byref +--* t127 int Generating: N839 (???,???) [001476] -A-XG------- * STOREIND byte REG NA V01 in reg rdi is becoming dead [000126] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN0099: mov byte ptr [rdi], 0 Added IP mapping: 0x006D STACK_EMPTY (G_M57450_IG18,ins#3,ofs#11) Generating: N841 ( 1, 3) [000134] ------------ IL_OFFSET void IL offset: 0x6d REG NA Generating: N843 ( 1, 1) [000131] -c---------- t131 = CNS_INT int 1 REG NA $41 /--* t131 int Generating: N845 ( 1, 3) [000133] DA---------- * STORE_LCL_VAR int V05 loc3 d:4 rax REG rax IN009a: mov eax, 1 V05 in reg rax is becoming live [000133] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V05} Scope info: end block BB34, IL range [069..071) Scope info: open scopes = IN009b: jmp L_M57450_BB36 =============== Generating BB35 [071..078), preds={BB33} succs={BB36} flags=0x00000000.400b0020: i label target gcsafe LIR BB35 IN (1)={V01 } OUT(1)={ V05} Recording Var Locations at start of BB35 V01(rdi) Change life 0000000000000010 {V05} -> 0000000000000002 {V01} V05 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg rdi is becoming live [------] Live regs: 00000000 {} => 00000080 {rdi} Live regs: (unchanged) 00000080 {rdi} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000080 {rdi} L_M57450_BB35: G_M57450_IG18: ; offs=00023FH, funclet=00 Label: IG19, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi} Scope info: begin block BB35, IL range [071..078) Scope info: open scopes = 1 (V01 arg1) [000..07A) Added IP mapping: 0x0071 STACK_EMPTY (G_M57450_IG19,ins#0,ofs#0) label Generating: N849 ( 6, 5) [000116] ------------ IL_OFFSET void IL offset: 0x71 REG NA Generating: N851 ( 1, 1) [000112] ------------ t112 = LCL_VAR byref V01 arg1 u:2 rdi (last use) REG rdi $81 Generating: N853 ( 1, 1) [000113] -c---------- t113 = CNS_INT int 0 REG NA $40 /--* t112 byref +--* t113 int Generating: N855 (???,???) [001477] -A-XG------- * STOREIND byte REG NA V01 in reg rdi is becoming dead [000112] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01} => {} Byref regs: 00000080 {rdi} => 00000000 {} IN009c: mov byte ptr [rdi], 0 Added IP mapping: 0x0074 STACK_EMPTY (G_M57450_IG19,ins#1,ofs#3) Generating: N857 ( 1, 3) [000120] ------------ IL_OFFSET void IL offset: 0x74 REG NA Generating: N859 ( 1, 1) [000117] ------------ t117 = CNS_INT int 0 REG rax $40 IN009d: xor eax, eax /--* t117 int Generating: N861 ( 1, 3) [000119] DA---------- * STORE_LCL_VAR int V05 loc3 d:3 rax REG rax V05 in reg rax is becoming live [000119] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V05} Scope info: end block BB35, IL range [071..078) Scope info: open scopes = =============== Generating BB36 [078..07A) (return), preds={BB10,BB20,BB27,BB34,BB35} succs={} flags=0x00000000.40030020: i label target LIR BB36 IN (1)={V05} OUT(0)={ } Recording Var Locations at start of BB36 V05(rax) Liveness not changing: 0000000000000010 {V05} Live regs: 00000000 {} => 00000001 {rax} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M57450_BB36: G_M57450_IG19: ; offs=000254H, funclet=00 Label: IG20, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB36, IL range [078..07A) Scope info: open scopes = 5 (V05 loc3) [000..07A) Added IP mapping: 0x0078 STACK_EMPTY (G_M57450_IG20,ins#0,ofs#0) label Generating: N865 ( 2, 2) [000124] ------------ IL_OFFSET void IL offset: 0x78 REG NA Generating: N867 ( 1, 1) [000122] ------------ t122 = LCL_VAR int V05 loc3 u:8 rax (last use) REG rax $504 /--* t122 int Generating: N869 ( 2, 2) [000123] ------------ * RETURN int REG NA $1fb V05 in reg rax is becoming dead [000122] Live regs: 00000001 {rax} => 00000000 {} Live vars: {V05} => {} Scope info: end block BB36, IL range [078..07A) Scope info: ending scope, LVnum=0 [000..07A) Scope info: ending scope, LVnum=1 [000..07A) Scope info: ending scope, LVnum=2 [000..07A) Scope info: ending scope, LVnum=3 [000..07A) Scope info: ending scope, LVnum=4 [000..07A) Scope info: ending scope, LVnum=5 [000..07A) Scope info: ending scope, LVnum=6 [000..07A) Scope info: ending scope, LVnum=7 [000..07A) Scope info: ending scope, LVnum=8 [000..07A) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M57450_IG20,ins#0,ofs#0) label Reserving epilog IG for block BB36 *************** After placeholder IG creation G_M57450_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M57450_IG02: ; offs=000000H, size=0042H, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi}, byref G_M57450_IG03: ; offs=000042H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG04: ; offs=00005DH, size=002FH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG05: ; offs=00008CH, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG06: ; offs=0000A2H, size=0044H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG07: ; offs=0000E6H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG08: ; offs=000101H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG09: ; offs=000131H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG10: ; offs=000147H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, nogc G_M57450_IG11: ; offs=000151H, size=002AH, emitadd G_M57450_IG12: ; offs=00017BH, size=001AH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG13: ; offs=000195H, size=002DH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG14: ; offs=0001C2H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG15: ; offs=0001D7H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG16: ; offs=0001F5H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG17: ; offs=00020FH, size=0030H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG18: ; offs=00023FH, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG19: ; offs=000254H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG20: ; epilog placeholder, next placeholder=, BB36 [0009], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Liveness not changing: 0000000000000000 {} # compCycleEstimate = 1002, compSizeEstimate = 762 System.Boolean:TryParse(struct,byref):bool ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 12, 16 ) byref -> rsi ; V01 arg1 [V01,T01] ( 7, 4.50) byref -> rdi ;* V02 loc0 [V02 ] ( 0, 0 ) struct (16) zero-ref ;* V03 loc1 [V03 ] ( 0, 0 ) struct (16) zero-ref ;* V04 loc2 [V04 ] ( 0, 0 ) bool -> zero-ref ; V05 loc3 [V05,T04] ( 6, 3.50) bool -> rax ;* V06 loc4 [V06 ] ( 0, 0 ) bool -> zero-ref ;* V07 loc5 [V07 ] ( 0, 0 ) bool -> zero-ref ;* V08 loc6 [V08 ] ( 0, 0 ) bool -> zero-ref ; V09 tmp0 [V09,T08] ( 1, 1 ) bool -> [rsp+0x4C] ; V10 tmp1 [V10,T15] ( 3, 1.50) byref -> rbx ;* V11 tmp2 [V11 ] ( 0, 0 ) struct (16) zero-ref ;* V12 tmp3 [V12 ] ( 0, 0 ) struct (16) zero-ref ;* V13 tmp4 [V13 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V14 tmp5 [V14,T40] ( 3, 0.75) int -> rbp ;* V15 tmp6 [V15 ] ( 0, 0 ) struct ( 8) zero-ref ;* V16 tmp7 [V16 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V17 tmp8 [V17 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V18 tmp9 [V18 ] ( 0, 0 ) int -> zero-ref ; V19 tmp10 [V19,T09] ( 2, 2 ) bool -> rax ; V20 tmp11 [V20,T49] ( 2, 0.50) bool -> rax ; V21 tmp12 [V21,T11] ( 4, 1.75) bool -> r14 ;* V22 tmp13 [V22 ] ( 0, 0 ) int -> zero-ref ;* V23 tmp14 [V23 ] ( 0, 0 ) int -> zero-ref ;* V24 tmp15 [V24 ] ( 0, 0 ) int -> zero-ref ; V25 tmp16 [V25,T33] ( 1, 0.50) bool -> [rsp+0x48] ; V26 tmp17 [V26,T32] ( 1, 0 ) byref -> [rsp+0x20] ;* V27 tmp18 [V27 ] ( 0, 0 ) struct (16) zero-ref ;* V28 tmp19 [V28 ] ( 0, 0 ) struct (16) zero-ref ;* V29 tmp20 [V29 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V30 tmp21 [V30,T41] ( 3, 0.75) int -> r14 ;* V31 tmp22 [V31 ] ( 0, 0 ) struct ( 8) zero-ref ;* V32 tmp23 [V32 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V33 tmp24 [V33 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V34 tmp25 [V34 ] ( 0, 0 ) int -> zero-ref ; V35 tmp26 [V35,T34] ( 2, 1 ) bool -> rax ; V36 tmp27 [V36,T50] ( 2, 0.50) bool -> rax ; V37 tmp28 [V37,T24] ( 4, 1.25) bool -> r12 ;* V38 tmp29 [V38 ] ( 0, 0 ) int -> zero-ref ;* V39 tmp30 [V39 ] ( 0, 0 ) int -> zero-ref ;* V40 tmp31 [V40 ] ( 0, 0 ) int -> zero-ref ;* V41 tmp32 [V41 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V42 tmp33 [V42 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V43 tmp34 [V43 ] ( 0, 0 ) int -> zero-ref ; V44 tmp35 [V44,T35] ( 2, 1 ) bool -> rax ; V45 tmp36 [V45,T51] ( 2, 0.50) bool -> rax ; V46 tmp37 [V46,T25] ( 4, 1.25) bool -> rbx ;* V47 tmp38 [V47 ] ( 0, 0 ) int -> zero-ref ;* V48 tmp39 [V48 ] ( 0, 0 ) int -> zero-ref ;* V49 tmp40 [V49 ] ( 0, 0 ) int -> zero-ref ;* V50 tmp41 [V50 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V51 tmp42 [V51 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ;* V52 tmp43 [V52 ] ( 0, 0 ) int -> zero-ref ; V53 tmp44 [V53,T36] ( 2, 1 ) bool -> rax ; V54 tmp45 [V54,T52] ( 2, 0.50) bool -> rax ; V55 tmp46 [V55,T26] ( 4, 1.25) bool -> rsi ;* V56 tmp47 [V56 ] ( 0, 0 ) int -> zero-ref ;* V57 tmp48 [V57 ] ( 0, 0 ) int -> zero-ref ;* V58 tmp49 [V58 ] ( 0, 0 ) int -> zero-ref ;* V59 tmp50 [V59 ] ( 0, 0 ) byref -> zero-ref do-not-enreg[] V95._pointer(offs=0x00) P-DEP ;* V60 tmp51 [V60 ] ( 0, 0 ) int -> zero-ref do-not-enreg[] V95._length(offs=0x08) P-DEP ; V61 tmp52 [V61,T02] ( 4, 1.25) byref -> rbx V02._pointer(offs=0x00) P-INDEP ; V62 tmp53 [V62,T03] ( 4, 2.75) int -> rbp V02._length(offs=0x08) P-INDEP ; V63 tmp54 [V63,T10] ( 3, 1.25) byref -> r15 V03._pointer(offs=0x00) P-INDEP ; V64 tmp55 [V64,T07] ( 4, 1.75) int -> r14 V03._length(offs=0x08) P-INDEP ; V65 tmp56 [V65,T47] ( 2, 0.50) byref -> rbx V11._pointer(offs=0x00) P-INDEP ; V66 tmp57 [V66,T53] ( 2, 0.50) int -> rbp V11._length(offs=0x08) P-INDEP ; V67 tmp58 [V67,T29] ( 2, 1.25) byref -> rbx V12._pointer(offs=0x00) P-INDEP ; V68 tmp59 [V68,T31] ( 2, 1.25) int -> rbp V12._length(offs=0x08) P-INDEP ;* V69 tmp60 [V69 ] ( 0, 0 ) byref -> zero-ref V13._pointer(offs=0x00) P-INDEP ;* V70 tmp61 [V70 ] ( 0, 0 ) int -> zero-ref V13._length(offs=0x08) P-INDEP ; V71 tmp62 [V71,T48] ( 2, 0.50) byref -> rbx V15._value(offs=0x00) P-INDEP ;* V72 tmp63 [V72,T37] ( 0, 0 ) byref -> zero-ref V16._pointer(offs=0x00) P-INDEP ;* V73 tmp64 [V73,T39] ( 0, 0 ) int -> zero-ref V16._length(offs=0x08) P-INDEP ; V74 tmp65 [V74,T30] ( 2, 1.25) byref -> rcx V17._pointer(offs=0x00) P-INDEP ; V75 tmp66 [V75,T06] ( 4, 2.50) int -> rdx V17._length(offs=0x08) P-INDEP ;* V76 tmp67 [V76,T58] ( 0, 0 ) byref -> zero-ref V27._pointer(offs=0x00) P-INDEP ; V77 tmp68 [V77,T54] ( 2, 0.50) int -> r14 V27._length(offs=0x08) P-INDEP ;* V78 tmp69 [V78,T59] ( 0, 0 ) byref -> zero-ref V28._pointer(offs=0x00) P-INDEP ; V79 tmp70 [V79,T46] ( 2, 0.75) int -> r14 V28._length(offs=0x08) P-INDEP ;* V80 tmp71 [V80 ] ( 0, 0 ) byref -> zero-ref V29._pointer(offs=0x00) P-INDEP ;* V81 tmp72 [V81 ] ( 0, 0 ) int -> zero-ref V29._length(offs=0x08) P-INDEP ;* V82 tmp73 [V82,T60] ( 0, 0 ) byref -> zero-ref V31._value(offs=0x00) P-INDEP ;* V83 tmp74 [V83,T55] ( 0, 0 ) byref -> zero-ref V32._pointer(offs=0x00) P-INDEP ;* V84 tmp75 [V84,T57] ( 0, 0 ) int -> zero-ref V32._length(offs=0x08) P-INDEP ; V85 tmp76 [V85,T42] ( 2, 0.75) byref -> rcx V33._pointer(offs=0x00) P-INDEP ; V86 tmp77 [V86,T12] ( 4, 1.50) int -> rdx V33._length(offs=0x08) P-INDEP ;* V87 tmp78 [V87,T56] ( 0, 0 ) byref -> zero-ref V41._pointer(offs=0x00) P-INDEP ; V88 tmp79 [V88,T27] ( 3, 1.25) int -> rbp V41._length(offs=0x08) P-INDEP ; V89 tmp80 [V89,T43] ( 2, 0.75) byref -> rcx V42._pointer(offs=0x00) P-INDEP ; V90 tmp81 [V90,T13] ( 4, 1.50) int -> rdx V42._length(offs=0x08) P-INDEP ; V91 tmp82 [V91,T44] ( 2, 0.75) byref -> r15 V50._pointer(offs=0x00) P-INDEP ; V92 tmp83 [V92,T28] ( 3, 1.25) int -> r14 V50._length(offs=0x08) P-INDEP ; V93 tmp84 [V93,T45] ( 2, 0.75) byref -> rcx V51._pointer(offs=0x00) P-INDEP ; V94 tmp85 [V94,T14] ( 4, 1.50) int -> rdx V51._length(offs=0x08) P-INDEP ;* V95 tmp86 [V95 ] ( 0, 0 ) struct (16) zero-ref do-not-enreg[S] ; V96 tmp87 [V96,T05] ( 11, 2.50) ref -> registers ; V97 tmp88 [V97 ] ( 15, 12 ) struct (16) [rsp+0x38] do-not-enreg[XSB] must-init addr-exposed ; V98 tmp89 [V98,T16] ( 3, 1.50) byref -> rax stack-byref ; V99 tmp90 [V99 ] ( 12, 8 ) struct (16) [rsp+0x28] do-not-enreg[XSB] must-init addr-exposed ; V100 tmp91 [V100,T17] ( 3, 1.50) byref -> rax stack-byref ; V101 tmp92 [V101,T18] ( 3, 1.50) byref -> rax stack-byref ; V102 tmp93 [V102,T19] ( 3, 1.50) byref -> rax stack-byref ;* V103 tmp94 [V103,T38] ( 0, 0 ) byref -> zero-ref ; V104 tmp95 [V104,T20] ( 3, 1.50) byref -> rax stack-byref ; V105 tmp96 [V105,T21] ( 3, 1.50) byref -> rax stack-byref ; V106 tmp97 [V106,T22] ( 3, 1.50) byref -> rax stack-byref ; V107 tmp98 [V107,T23] ( 3, 1.50) byref -> rax stack-byref ; V108 OutArgs [V108 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; ; Lcl frame size = 80 *************** Before prolog / epilog generation G_M57450_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M57450_IG02: ; offs=000000H, size=0042H, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi}, byref G_M57450_IG03: ; offs=000042H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG04: ; offs=00005DH, size=002FH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG05: ; offs=00008CH, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG06: ; offs=0000A2H, size=0044H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG07: ; offs=0000E6H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG08: ; offs=000101H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG09: ; offs=000131H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG10: ; offs=000147H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, nogc G_M57450_IG11: ; offs=000151H, size=002AH, emitadd G_M57450_IG12: ; offs=00017BH, size=001AH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG13: ; offs=000195H, size=002DH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG14: ; offs=0001C2H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG15: ; offs=0001D7H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG16: ; offs=0001F5H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG17: ; offs=00020FH, size=0030H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG18: ; offs=00023FH, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG19: ; offs=000254H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG20: ; epilog placeholder, next placeholder=, BB36 [0009], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000080 {rdi} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Recording Var Locations at start of BB01 V00(rsi) V01(rdi) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M57450_IG01,ins#0,ofs#0) label __prolog: Found 8 lvMustInit stk vars, frame offsets -40 through -72 IN009e: push r15 IN009f: push r14 IN00a0: push r12 IN00a1: push rdi IN00a2: push rsi IN00a3: push rbp IN00a4: push rbx IN00a5: sub rsp, 80 IN00a6: mov rsi, rcx IN00a7: lea rdi, [rsp+28H] IN00a8: mov ecx, 8 IN00a9: xor rax, rax IN00aa: rep stosd IN00ab: mov rcx, rsi *************** In genFnPrologCalleeRegArgs() for int regs IN00ac: mov rsi, rcx IN00ad: mov rdi, rdx *************** In genEnregisterIncomingStackArgs() 1 tracked GC refs are at stack offsets 0020 ... 0028 G_M57450_IG01: ; offs=000000H, funclet=00 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN00ae: add rsp, 80 IN00af: pop rbx IN00b0: pop rbp IN00b1: pop rsi IN00b2: pop rdi IN00b3: pop r12 IN00b4: pop r14 IN00b5: pop r15 IN00b6: ret G_M57450_IG20: ; offs=000259H, funclet=00 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M57450_IG01: ; func=00, offs=000000H, size=0028H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M57450_IG02: ; offs=000028H, size=0042H, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi}, byref G_M57450_IG03: ; offs=00006AH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG04: ; offs=000085H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref G_M57450_IG05: ; offs=0000B4H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG06: ; offs=0000CAH, size=0044H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref G_M57450_IG07: ; offs=00010EH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG08: ; offs=000129H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref G_M57450_IG09: ; offs=000159H, size=0016H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG10: ; offs=00016FH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, nogc G_M57450_IG11: ; offs=000179H, size=002AH, emitadd G_M57450_IG12: ; offs=0001A3H, size=001AH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG13: ; offs=0001BDH, size=002DH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref G_M57450_IG14: ; offs=0001EAH, size=0015H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG15: ; offs=0001FFH, size=001EH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref G_M57450_IG16: ; offs=00021DH, size=001AH, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG17: ; offs=000237H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref G_M57450_IG18: ; offs=000267H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG19: ; offs=00027CH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref G_M57450_IG20: ; offs=000281H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc *************** In emitJumpDistBind() Binding: IN0010: 000000 je L_M57450_BB06 Binding L_M57450_BB06 to G_M57450_IG03 Estimate of fwd jump [1DA2B8F4/016]: 005C -> 006A = 000C Shrinking jump [1DA2B8F4/016] Binding: IN0012: 000000 jmp L_M57450_BB09 Binding L_M57450_BB09 to G_M57450_IG05 Estimate of fwd jump [1DA2B93C/018]: 0061 -> 00B0 = 004D Shrinking jump [1DA2B93C/018] Binding: IN0017: 000000 je L_M57450_BB08 Binding L_M57450_BB08 to G_M57450_IG04 Estimate of fwd jump [1DA2BBBC/023]: 006D -> 007E = 000F Shrinking jump [1DA2BBBC/023] Binding: IN0019: 000000 jmp L_M57450_BB09 Binding L_M57450_BB09 to G_M57450_IG05 Estimate of fwd jump [1DA2BC04/025]: 0075 -> 00A9 = 0032 Shrinking jump [1DA2BC04/025] Binding: IN0027: 000000 je L_M57450_BB11 Binding L_M57450_BB11 to G_M57450_IG06 Estimate of fwd jump [1DA2C2AC/039]: 00A9 -> 00BC = 0011 Shrinking jump [1DA2C2AC/039] Binding: IN002a: 000000 jmp L_M57450_BB36 Binding L_M57450_BB36 to G_M57450_IG20 Estimate of fwd jump [1DA2C30C/042]: 00B3 -> 026F = 01BA Binding: IN003a: 000000 je L_M57450_BB16 Binding L_M57450_BB16 to G_M57450_IG07 Estimate of fwd jump [1DA2C9C4/058]: 00EE -> 00FC = 000C Shrinking jump [1DA2C9C4/058] Binding: IN003c: 000000 jmp L_M57450_BB19 Binding L_M57450_BB19 to G_M57450_IG09 Estimate of fwd jump [1DA2CA0C/060]: 00F3 -> 0143 = 004E Shrinking jump [1DA2CA0C/060] Binding: IN0041: 000000 je L_M57450_BB18 Binding L_M57450_BB18 to G_M57450_IG08 Estimate of fwd jump [1DA2CC8C/065]: 00FF -> 0110 = 000F Shrinking jump [1DA2CC8C/065] Binding: IN0043: 000000 jmp L_M57450_BB19 Binding L_M57450_BB19 to G_M57450_IG09 Estimate of fwd jump [1DA2CCD4/067]: 0107 -> 013C = 0033 Shrinking jump [1DA2CCD4/067] Binding: IN0051: 000000 je L_M57450_BB21 Binding L_M57450_BB21 to G_M57450_IG10 Estimate of fwd jump [1DA2D37C/081]: 013C -> 014F = 0011 Shrinking jump [1DA2D37C/081] Binding: IN0054: 000000 jmp L_M57450_BB36 Binding L_M57450_BB36 to G_M57450_IG20 Estimate of fwd jump [1DA2D3DC/084]: 0146 -> 025D = 0115 Binding: IN0060: 000000 je L_M57450_BB23 Binding L_M57450_BB23 to G_M57450_IG12 Estimate of fwd jump [1DA2D9C8/096]: 0172 -> 017F = 000B Shrinking jump [1DA2D9C8/096] Binding: IN0062: 000000 jmp L_M57450_BB26 Binding L_M57450_BB26 to G_M57450_IG14 Estimate of fwd jump [1DA2DA10/098]: 0176 -> 01C2 = 004A Shrinking jump [1DA2DA10/098] Binding: IN0067: 000000 je L_M57450_BB25 Binding L_M57450_BB25 to G_M57450_IG13 Estimate of fwd jump [1DA2DC8C/103]: 0182 -> 0192 = 000E Shrinking jump [1DA2DC8C/103] Binding: IN0069: 000000 jmp L_M57450_BB26 Binding L_M57450_BB26 to G_M57450_IG14 Estimate of fwd jump [1DA2DCD4/105]: 0189 -> 01BB = 0030 Shrinking jump [1DA2DCD4/105] Binding: IN0077: 000000 je L_M57450_BB28 Binding L_M57450_BB28 to G_M57450_IG15 Estimate of fwd jump [1DA2E37C/119]: 01BA -> 01CD = 0011 Shrinking jump [1DA2E37C/119] Binding: IN007a: 000000 jmp L_M57450_BB36 Binding L_M57450_BB36 to G_M57450_IG20 Estimate of fwd jump [1DA2E3DC/122]: 01C4 -> 024B = 0085 Binding: IN0081: 000000 je L_M57450_BB30 Binding L_M57450_BB30 to G_M57450_IG16 Estimate of fwd jump [1DA2E794/129]: 01DA -> 01E7 = 000B Shrinking jump [1DA2E794/129] Binding: IN0083: 000000 jmp L_M57450_BB33 Binding L_M57450_BB33 to G_M57450_IG18 Estimate of fwd jump [1DA2E7DC/131]: 01DE -> 022D = 004D Shrinking jump [1DA2E7DC/131] Binding: IN0088: 000000 je L_M57450_BB32 Binding L_M57450_BB32 to G_M57450_IG17 Estimate of fwd jump [1DA2EA5C/136]: 01EA -> 01FA = 000E Shrinking jump [1DA2EA5C/136] Binding: IN008a: 000000 jmp L_M57450_BB33 Binding L_M57450_BB33 to G_M57450_IG18 Estimate of fwd jump [1DA2EAA4/138]: 01F1 -> 0226 = 0033 Shrinking jump [1DA2EAA4/138] Binding: IN0098: 000000 je L_M57450_BB35 Binding L_M57450_BB35 to G_M57450_IG19 Estimate of fwd jump [1DA2F134/152]: 0225 -> 0238 = 0011 Shrinking jump [1DA2F134/152] Binding: IN009b: 000000 jmp L_M57450_BB36 Binding L_M57450_BB36 to G_M57450_IG20 Estimate of fwd jump [1DA2F194/155]: 022F -> 0239 = 0008 Shrinking jump [1DA2F194/155] Total shrinkage = 75, min extra jump size = 6 Iterating branch shortening. Iteration = 2 Estimate of fwd jump [1DA2C30C/042]: 00B3 -> 0236 = 0181 Estimate of fwd jump [1DA2D3DC/084]: 0146 -> 0236 = 00EE Estimate of fwd jump [1DA2E3DC/122]: 01C4 -> 0236 = 0070 Shrinking jump [1DA2E3DC/122] Total shrinkage = 3, min extra jump size = 111 Hot code size = 0x242 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x14) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M57450_IG01: ; func=00, offs=000000H, size=0028H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN009e: 000000 4157 push r15 IN009f: 000002 4156 push r14 IN00a0: 000004 4154 push r12 IN00a1: 000006 57 push rdi IN00a2: 000007 56 push rsi IN00a3: 000008 55 push rbp IN00a4: 000009 53 push rbx IN00a5: 00000A 4883EC50 sub rsp, 80 IN00a6: 00000E 488BF1 mov rsi, rcx IN00a7: 000011 488D7C2428 lea rdi, [rsp+28H] IN00a8: 000016 B908000000 mov ecx, 8 IN00a9: 00001B 33C0 xor rax, rax IN00aa: 00001D F3AB rep stosd IN00ab: 00001F 488BCE mov rcx, rsi byrReg +[rsi] IN00ac: 000022 488BF1 mov rsi, rcx byrReg +[rdi] IN00ad: 000025 488BFA mov rdi, rdx G_M57450_IG02: ; func=00, offs=000028H, size=003BH, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi}, byref, isz IN0001: 000028 488D1D00000000 lea rbx, [(reloc 0x421150)] IN0002: 00002F 391B cmp dword ptr [rbx], ebx byrReg +[rbx] IN0003: 000031 4883C30C add rbx, 12 IN0004: 000035 488D0D00000000 lea rcx, [(reloc 0x421150)] IN0005: 00003C 8B6908 mov ebp, dword ptr [rcx+8] IN0006: 00003F 85ED test ebp, ebp IN0007: 000041 0F9DC1 setge cl IN0008: 000044 0FB6C9 movzx rcx, cl [1DA2FD80] ptr arg pop 0 IN0009: 000047 E800000000 call System.Diagnostics.Debug:Assert(bool) byrReg +[rcx] IN000a: 00004C 488B0E mov rcx, bword ptr [rsi] IN000b: 00004F 8B5608 mov edx, dword ptr [rsi+8] IN000c: 000052 3BEA cmp ebp, edx IN000d: 000054 0F95C0 setne al IN000e: 000057 0FB6C0 movzx rax, al IN000f: 00005A 85C0 test eax, eax IN0010: 00005C 7405 je SHORT G_M57450_IG03 IN0011: 00005E 4533F6 xor r14d, r14d IN0012: 000061 EB43 jmp SHORT G_M57450_IG05 G_M57450_IG03: ; func=00, offs=000063H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref, isz IN0013: 000063 85D2 test edx, edx IN0014: 000065 0F94C0 sete al IN0015: 000068 0FB6C0 movzx rax, al IN0016: 00006B 85C0 test eax, eax IN0017: 00006D 7408 je SHORT G_M57450_IG04 IN0018: 00006F 41BE01000000 mov r14d, 1 IN0019: 000075 EB2F jmp SHORT G_M57450_IG05 G_M57450_IG04: ; func=00, offs=000077H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref byrReg +[rax] IN001a: 000077 488D442438 lea rax, bword ptr [rsp+38H] IN001b: 00007C 488918 mov bword ptr [rax], rbx IN001c: 00007F 896808 mov dword ptr [rax+8], ebp IN001d: 000082 488D442428 lea rax, bword ptr [rsp+28H] IN001e: 000087 488908 mov bword ptr [rax], rcx IN001f: 00008A 895008 mov dword ptr [rax+8], edx IN0020: 00008D 488D4C2438 lea rcx, bword ptr [rsp+38H] byrReg +[rdx] IN0021: 000092 488D542428 lea rdx, bword ptr [rsp+28H] New byrReg live regs=000000C8 {rbx rsi rdi} byrReg -[rax] byrReg -[rcx] byrReg -[rdx] [1DA2FE88] ptr arg pop 0 IN0022: 000097 E800000000 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0023: 00009C 85C0 test eax, eax IN0024: 00009E 410F94C6 sete r14b IN0025: 0000A2 450FB6F6 movzx r14, r14b G_M57450_IG05: ; func=00, offs=0000A6H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref, isz IN0026: 0000A6 4585F6 test r14d, r14d IN0027: 0000A9 740D je SHORT G_M57450_IG06 IN0028: 0000AB C60701 mov byte ptr [rdi], 1 IN0029: 0000AE B801000000 mov eax, 1 IN002a: 0000B3 E97B010000 jmp G_M57450_IG20 G_M57450_IG06: ; func=00, offs=0000B8H, size=003DH, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref, isz IN002b: 0000B8 488D0D00000000 lea rcx, [(reloc 0x421158)] IN002c: 0000BF 3909 cmp dword ptr [rcx], ecx IN002d: 0000C1 488D0D00000000 lea rcx, [(reloc 0x421158)] IN002e: 0000C8 448B7108 mov r14d, dword ptr [rcx+8] IN002f: 0000CC 4585F6 test r14d, r14d IN0030: 0000CF 0F9DC1 setge cl IN0031: 0000D2 0FB6C9 movzx rcx, cl [1DA2FEF8] ptr arg pop 0 IN0032: 0000D5 E800000000 call System.Diagnostics.Debug:Assert(bool) byrReg +[r15] IN0033: 0000DA 4C8BFB mov r15, rbx byrReg +[rcx] IN0034: 0000DD 488B0E mov rcx, bword ptr [rsi] IN0035: 0000E0 8B5608 mov edx, dword ptr [rsi+8] IN0036: 0000E3 443BF2 cmp r14d, edx IN0037: 0000E6 0F95C0 setne al IN0038: 0000E9 0FB6C0 movzx rax, al IN0039: 0000EC 85C0 test eax, eax IN003a: 0000EE 7405 je SHORT G_M57450_IG07 IN003b: 0000F0 4533E4 xor r12d, r12d IN003c: 0000F3 EB44 jmp SHORT G_M57450_IG09 G_M57450_IG07: ; func=00, offs=0000F5H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref, isz IN003d: 0000F5 85D2 test edx, edx IN003e: 0000F7 0F94C0 sete al IN003f: 0000FA 0FB6C0 movzx rax, al IN0040: 0000FD 85C0 test eax, eax IN0041: 0000FF 7408 je SHORT G_M57450_IG08 IN0042: 000101 41BC01000000 mov r12d, 1 IN0043: 000107 EB30 jmp SHORT G_M57450_IG09 G_M57450_IG08: ; func=00, offs=000109H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref byrReg +[rax] IN0044: 000109 488D442438 lea rax, bword ptr [rsp+38H] IN0045: 00010E 488918 mov bword ptr [rax], rbx IN0046: 000111 44897008 mov dword ptr [rax+8], r14d IN0047: 000115 488D442428 lea rax, bword ptr [rsp+28H] IN0048: 00011A 488908 mov bword ptr [rax], rcx IN0049: 00011D 895008 mov dword ptr [rax+8], edx IN004a: 000120 488D4C2438 lea rcx, bword ptr [rsp+38H] byrReg +[rdx] IN004b: 000125 488D542428 lea rdx, bword ptr [rsp+28H] New byrReg live regs=000080C0 {rsi rdi r15} byrReg -[rax] byrReg -[rcx] byrReg -[rdx] byrReg -[rbx] [1DA30040] ptr arg pop 0 IN004c: 00012A E800000000 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN004d: 00012F 85C0 test eax, eax IN004e: 000131 410F94C4 sete r12b IN004f: 000135 450FB6E4 movzx r12, r12b G_M57450_IG09: ; func=00, offs=000139H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz IN0050: 000139 4585E4 test r12d, r12d IN0051: 00013C 740D je SHORT G_M57450_IG10 IN0052: 00013E C60700 mov byte ptr [rdi], 0 IN0053: 000141 B801000000 mov eax, 1 IN0054: 000146 E9E8000000 jmp G_M57450_IG20 G_M57450_IG10: ; func=00, offs=00014BH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, nogc IN0055: 00014B F30F6F06 movdqu xmm0, qword ptr [rsi] IN0056: 00014F F30F7F442438 movdqu qword ptr [rsp+38H], xmm0 G_M57450_IG11: ; func=00, offs=000155H, size=0023H, isz, emitadd byrReg +[rcx] IN0057: 000155 488BCE mov rcx, rsi byrReg +[rdx] IN0058: 000158 488D542438 lea rdx, bword ptr [rsp+38H] New byrReg live regs=000080C0 {rsi rdi r15} byrReg -[rcx] byrReg -[rdx] [1D8F3F20] ptr arg pop 0 IN0059: 00015D E800000000 call System.Boolean:TrimWhiteSpaceAndNull(struct):struct byrReg +[rcx] IN005a: 000162 488B0E mov rcx, bword ptr [rsi] IN005b: 000165 8B5608 mov edx, dword ptr [rsi+8] IN005c: 000168 3BEA cmp ebp, edx IN005d: 00016A 0F95C0 setne al IN005e: 00016D 0FB6C0 movzx rax, al IN005f: 000170 85C0 test eax, eax IN0060: 000172 7404 je SHORT G_M57450_IG12 IN0061: 000174 33DB xor ebx, ebx IN0062: 000176 EB40 jmp SHORT G_M57450_IG14 G_M57450_IG12: ; func=00, offs=000178H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref, isz IN0063: 000178 85D2 test edx, edx IN0064: 00017A 0F94C0 sete al IN0065: 00017D 0FB6C0 movzx rax, al IN0066: 000180 85C0 test eax, eax IN0067: 000182 7407 je SHORT G_M57450_IG13 IN0068: 000184 BB01000000 mov ebx, 1 IN0069: 000189 EB2D jmp SHORT G_M57450_IG14 G_M57450_IG13: ; func=00, offs=00018BH, size=002DH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref byrReg +[rax] IN006a: 00018B 488D442438 lea rax, bword ptr [rsp+38H] IN006b: 000190 4C8938 mov bword ptr [rax], r15 IN006c: 000193 896808 mov dword ptr [rax+8], ebp IN006d: 000196 488D442428 lea rax, bword ptr [rsp+28H] IN006e: 00019B 488908 mov bword ptr [rax], rcx IN006f: 00019E 895008 mov dword ptr [rax+8], edx IN0070: 0001A1 488D4C2438 lea rcx, bword ptr [rsp+38H] byrReg +[rdx] IN0071: 0001A6 488D542428 lea rdx, bword ptr [rsp+28H] New byrReg live regs=000080C0 {rsi rdi r15} byrReg -[rax] byrReg -[rcx] byrReg -[rdx] [1D8F4038] ptr arg pop 0 IN0072: 0001AB E800000000 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0073: 0001B0 85C0 test eax, eax IN0074: 0001B2 0F94C3 sete bl IN0075: 0001B5 0FB6DB movzx rbx, bl G_M57450_IG14: ; func=00, offs=0001B8H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz IN0076: 0001B8 85DB test ebx, ebx IN0077: 0001BA 740A je SHORT G_M57450_IG15 IN0078: 0001BC C60701 mov byte ptr [rdi], 1 IN0079: 0001BF B801000000 mov eax, 1 IN007a: 0001C4 EB6D jmp SHORT G_M57450_IG20 G_M57450_IG15: ; func=00, offs=0001C6H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz byrReg +[rcx] IN007b: 0001C6 488B0E mov rcx, bword ptr [rsi] IN007c: 0001C9 8B5608 mov edx, dword ptr [rsi+8] IN007d: 0001CC 443BF2 cmp r14d, edx IN007e: 0001CF 0F95C0 setne al IN007f: 0001D2 0FB6C0 movzx rax, al IN0080: 0001D5 85C0 test eax, eax IN0081: 0001D7 7404 je SHORT G_M57450_IG16 byrReg -[rsi] IN0082: 0001D9 33F6 xor esi, esi IN0083: 0001DB EB43 jmp SHORT G_M57450_IG18 G_M57450_IG16: ; func=00, offs=0001DDH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref, isz IN0084: 0001DD 85D2 test edx, edx IN0085: 0001DF 0F94C0 sete al IN0086: 0001E2 0FB6C0 movzx rax, al IN0087: 0001E5 85C0 test eax, eax IN0088: 0001E7 7407 je SHORT G_M57450_IG17 IN0089: 0001E9 BE01000000 mov esi, 1 IN008a: 0001EE EB30 jmp SHORT G_M57450_IG18 G_M57450_IG17: ; func=00, offs=0001F0H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref byrReg +[rax] IN008b: 0001F0 488D442438 lea rax, bword ptr [rsp+38H] IN008c: 0001F5 4C8938 mov bword ptr [rax], r15 IN008d: 0001F8 44897008 mov dword ptr [rax+8], r14d IN008e: 0001FC 488D442428 lea rax, bword ptr [rsp+28H] IN008f: 000201 488908 mov bword ptr [rax], rcx IN0090: 000204 895008 mov dword ptr [rax+8], edx IN0091: 000207 488D4C2438 lea rcx, bword ptr [rsp+38H] byrReg +[rdx] IN0092: 00020C 488D542428 lea rdx, bword ptr [rsp+28H] New byrReg live regs=00000080 {rdi} byrReg -[rax] byrReg -[rcx] byrReg -[rdx] byrReg -[r15] [1D8F41A8] ptr arg pop 0 IN0093: 000211 E800000000 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0094: 000216 85C0 test eax, eax IN0095: 000218 400F94C6 sete sil IN0096: 00021C 400FB6F6 movzx rsi, sil G_M57450_IG18: ; func=00, offs=000220H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref, isz IN0097: 000220 85F6 test esi, esi IN0098: 000222 740A je SHORT G_M57450_IG19 IN0099: 000224 C60700 mov byte ptr [rdi], 0 IN009a: 000227 B801000000 mov eax, 1 IN009b: 00022C EB05 jmp SHORT G_M57450_IG20 G_M57450_IG19: ; func=00, offs=00022EH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref IN009c: 00022E C60700 mov byte ptr [rdi], 0 IN009d: 000231 33C0 xor eax, eax G_M57450_IG20: ; func=00, offs=000233H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc New byrReg live regs=00000000 {} byrReg -[rdi] IN00ae: 000233 4883C450 add rsp, 80 IN00af: 000237 5B pop rbx IN00b0: 000238 5D pop rbp IN00b1: 000239 5E pop rsi IN00b2: 00023A 5F pop rdi IN00b3: 00023B 415C pop r12 IN00b4: 00023D 415E pop r14 IN00b5: 00023F 415F pop r15 IN00b6: 000241 C3 ret Allocated method code size = 578 , actual size = 578 *************** After end code gen, before unwindEmit() G_M57450_IG01: ; func=00, offs=000000H, size=0028H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN009e: 000000 push r15 IN009f: 000002 push r14 IN00a0: 000004 push r12 IN00a1: 000006 push rdi IN00a2: 000007 push rsi IN00a3: 000008 push rbp IN00a4: 000009 push rbx IN00a5: 00000A sub rsp, 80 IN00a6: 00000E mov rsi, rcx IN00a7: 000011 lea rdi, [rsp+28H] IN00a8: 000016 mov ecx, 8 IN00a9: 00001B xor rax, rax IN00aa: 00001D rep stosd IN00ab: 00001F mov rcx, rsi IN00ac: 000022 mov rsi, rcx IN00ad: 000025 mov rdi, rdx G_M57450_IG02: ; offs=000028H, size=003BH, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi}, byref, isz IN0001: 000028 lea rbx, [(reloc 0x421150)] IN0002: 00002F cmp dword ptr [rbx], ebx IN0003: 000031 add rbx, 12 IN0004: 000035 lea rcx, [(reloc 0x421150)] IN0005: 00003C mov ebp, dword ptr [rcx+8] IN0006: 00003F test ebp, ebp IN0007: 000041 setge cl IN0008: 000044 movzx rcx, cl IN0009: 000047 call System.Diagnostics.Debug:Assert(bool) IN000a: 00004C mov rcx, bword ptr [rsi] IN000b: 00004F mov edx, dword ptr [rsi+8] IN000c: 000052 cmp ebp, edx IN000d: 000054 setne al IN000e: 000057 movzx rax, al IN000f: 00005A test eax, eax IN0010: 00005C je SHORT G_M57450_IG03 IN0011: 00005E xor r14d, r14d IN0012: 000061 jmp SHORT G_M57450_IG05 G_M57450_IG03: ; offs=000063H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref, isz IN0013: 000063 test edx, edx IN0014: 000065 sete al IN0015: 000068 movzx rax, al IN0016: 00006B test eax, eax IN0017: 00006D je SHORT G_M57450_IG04 IN0018: 00006F mov r14d, 1 IN0019: 000075 jmp SHORT G_M57450_IG05 G_M57450_IG04: ; offs=000077H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=000000CA {rcx rbx rsi rdi}, byref IN001a: 000077 lea rax, bword ptr [V97 rsp+38H] IN001b: 00007C mov bword ptr [rax], rbx IN001c: 00007F mov dword ptr [rax+8], ebp IN001d: 000082 lea rax, bword ptr [V99 rsp+28H] IN001e: 000087 mov bword ptr [rax], rcx IN001f: 00008A mov dword ptr [rax+8], edx IN0020: 00008D lea rcx, bword ptr [V97 rsp+38H] IN0021: 000092 lea rdx, bword ptr [V99 rsp+28H] IN0022: 000097 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0023: 00009C test eax, eax IN0024: 00009E sete r14b IN0025: 0000A2 movzx r14, r14b G_M57450_IG05: ; offs=0000A6H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref, isz IN0026: 0000A6 test r14d, r14d IN0027: 0000A9 je SHORT G_M57450_IG06 IN0028: 0000AB mov byte ptr [rdi], 1 IN0029: 0000AE mov eax, 1 IN002a: 0000B3 jmp G_M57450_IG20 G_M57450_IG06: ; offs=0000B8H, size=003DH, gcrefRegs=00000000 {}, byrefRegs=000000C8 {rbx rsi rdi}, byref, isz IN002b: 0000B8 lea rcx, [(reloc 0x421158)] IN002c: 0000BF cmp dword ptr [rcx], ecx IN002d: 0000C1 lea rcx, [(reloc 0x421158)] IN002e: 0000C8 mov r14d, dword ptr [rcx+8] IN002f: 0000CC test r14d, r14d IN0030: 0000CF setge cl IN0031: 0000D2 movzx rcx, cl IN0032: 0000D5 call System.Diagnostics.Debug:Assert(bool) IN0033: 0000DA mov r15, rbx IN0034: 0000DD mov rcx, bword ptr [rsi] IN0035: 0000E0 mov edx, dword ptr [rsi+8] IN0036: 0000E3 cmp r14d, edx IN0037: 0000E6 setne al IN0038: 0000E9 movzx rax, al IN0039: 0000EC test eax, eax IN003a: 0000EE je SHORT G_M57450_IG07 IN003b: 0000F0 xor r12d, r12d IN003c: 0000F3 jmp SHORT G_M57450_IG09 G_M57450_IG07: ; offs=0000F5H, size=0014H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref, isz IN003d: 0000F5 test edx, edx IN003e: 0000F7 sete al IN003f: 0000FA movzx rax, al IN0040: 0000FD test eax, eax IN0041: 0000FF je SHORT G_M57450_IG08 IN0042: 000101 mov r12d, 1 IN0043: 000107 jmp SHORT G_M57450_IG09 G_M57450_IG08: ; offs=000109H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=000080CA {rcx rbx rsi rdi r15}, byref IN0044: 000109 lea rax, bword ptr [V97 rsp+38H] IN0045: 00010E mov bword ptr [rax], rbx IN0046: 000111 mov dword ptr [rax+8], r14d IN0047: 000115 lea rax, bword ptr [V99 rsp+28H] IN0048: 00011A mov bword ptr [rax], rcx IN0049: 00011D mov dword ptr [rax+8], edx IN004a: 000120 lea rcx, bword ptr [V97 rsp+38H] IN004b: 000125 lea rdx, bword ptr [V99 rsp+28H] IN004c: 00012A call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN004d: 00012F test eax, eax IN004e: 000131 sete r12b IN004f: 000135 movzx r12, r12b G_M57450_IG09: ; offs=000139H, size=0012H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz IN0050: 000139 test r12d, r12d IN0051: 00013C je SHORT G_M57450_IG10 IN0052: 00013E mov byte ptr [rdi], 0 IN0053: 000141 mov eax, 1 IN0054: 000146 jmp G_M57450_IG20 G_M57450_IG10: ; offs=00014BH, size=000AH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, nogc IN0055: 00014B movdqu xmm0, qword ptr [rsi] IN0056: 00014F movdqu qword ptr [V97 rsp+38H], xmm0 G_M57450_IG11: ; offs=000155H, size=0023H, isz, emitadd IN0057: 000155 mov rcx, rsi IN0058: 000158 lea rdx, bword ptr [V97 rsp+38H] IN0059: 00015D call System.Boolean:TrimWhiteSpaceAndNull(struct):struct IN005a: 000162 mov rcx, bword ptr [rsi] IN005b: 000165 mov edx, dword ptr [rsi+8] IN005c: 000168 cmp ebp, edx IN005d: 00016A setne al IN005e: 00016D movzx rax, al IN005f: 000170 test eax, eax IN0060: 000172 je SHORT G_M57450_IG12 IN0061: 000174 xor ebx, ebx IN0062: 000176 jmp SHORT G_M57450_IG14 G_M57450_IG12: ; offs=000178H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref, isz IN0063: 000178 test edx, edx IN0064: 00017A sete al IN0065: 00017D movzx rax, al IN0066: 000180 test eax, eax IN0067: 000182 je SHORT G_M57450_IG13 IN0068: 000184 mov ebx, 1 IN0069: 000189 jmp SHORT G_M57450_IG14 G_M57450_IG13: ; offs=00018BH, size=002DH, gcrefRegs=00000000 {}, byrefRegs=000080C2 {rcx rsi rdi r15}, byref IN006a: 00018B lea rax, bword ptr [V97 rsp+38H] IN006b: 000190 mov bword ptr [rax], r15 IN006c: 000193 mov dword ptr [rax+8], ebp IN006d: 000196 lea rax, bword ptr [V99 rsp+28H] IN006e: 00019B mov bword ptr [rax], rcx IN006f: 00019E mov dword ptr [rax+8], edx IN0070: 0001A1 lea rcx, bword ptr [V97 rsp+38H] IN0071: 0001A6 lea rdx, bword ptr [V99 rsp+28H] IN0072: 0001AB call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0073: 0001B0 test eax, eax IN0074: 0001B2 sete bl IN0075: 0001B5 movzx rbx, bl G_M57450_IG14: ; offs=0001B8H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz IN0076: 0001B8 test ebx, ebx IN0077: 0001BA je SHORT G_M57450_IG15 IN0078: 0001BC mov byte ptr [rdi], 1 IN0079: 0001BF mov eax, 1 IN007a: 0001C4 jmp SHORT G_M57450_IG20 G_M57450_IG15: ; offs=0001C6H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=000080C0 {rsi rdi r15}, byref, isz IN007b: 0001C6 mov rcx, bword ptr [rsi] IN007c: 0001C9 mov edx, dword ptr [rsi+8] IN007d: 0001CC cmp r14d, edx IN007e: 0001CF setne al IN007f: 0001D2 movzx rax, al IN0080: 0001D5 test eax, eax IN0081: 0001D7 je SHORT G_M57450_IG16 IN0082: 0001D9 xor esi, esi IN0083: 0001DB jmp SHORT G_M57450_IG18 G_M57450_IG16: ; offs=0001DDH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref, isz IN0084: 0001DD test edx, edx IN0085: 0001DF sete al IN0086: 0001E2 movzx rax, al IN0087: 0001E5 test eax, eax IN0088: 0001E7 je SHORT G_M57450_IG17 IN0089: 0001E9 mov esi, 1 IN008a: 0001EE jmp SHORT G_M57450_IG18 G_M57450_IG17: ; offs=0001F0H, size=0030H, gcrefRegs=00000000 {}, byrefRegs=00008082 {rcx rdi r15}, byref IN008b: 0001F0 lea rax, bword ptr [V97 rsp+38H] IN008c: 0001F5 mov bword ptr [rax], r15 IN008d: 0001F8 mov dword ptr [rax+8], r14d IN008e: 0001FC lea rax, bword ptr [V99 rsp+28H] IN008f: 000201 mov bword ptr [rax], rcx IN0090: 000204 mov dword ptr [rax+8], edx IN0091: 000207 lea rcx, bword ptr [V97 rsp+38H] IN0092: 00020C lea rdx, bword ptr [V99 rsp+28H] IN0093: 000211 call System.Globalization.CompareInfo:CompareOrdinalIgnoreCase(struct,struct):int IN0094: 000216 test eax, eax IN0095: 000218 sete sil IN0096: 00021C movzx rsi, sil G_M57450_IG18: ; offs=000220H, size=000EH, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref, isz IN0097: 000220 test esi, esi IN0098: 000222 je SHORT G_M57450_IG19 IN0099: 000224 mov byte ptr [rdi], 0 IN009a: 000227 mov eax, 1 IN009b: 00022C jmp SHORT G_M57450_IG20 G_M57450_IG19: ; offs=00022EH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000080 {rdi}, byref IN009c: 00022E mov byte ptr [rdi], 0 IN009d: 000231 xor eax, eax G_M57450_IG20: ; offs=000233H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc IN00ae: 000233 add rsp, 80 IN00af: 000237 pop rbx IN00b0: 000238 pop rbp IN00b1: 000239 pop rsi IN00b2: 00023A pop rdi IN00b3: 00023B pop r12 IN00b4: 00023D pop r14 IN00b5: 00023F pop r15 IN00b6: 000241 ret Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x000242 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x0E CountOfUnwindCodes: 8 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x0E UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 9 * 8 + 8 = 80 = 0x50 CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12) CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15) allocUnwindInfo(pHotCode=0x000001C306CE5DC8, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x242, unwindSize=0x14, pUnwindBlock=0x000001C31D9D562C, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 24 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0001 : 0x00000028 ( STACK_EMPTY ) IL offs 0x000C : 0x0000004C ( STACK_EMPTY ) IL offs 0x0014 : 0x000000A6 ( STACK_EMPTY ) IL offs 0x0018 : 0x000000AB ( STACK_EMPTY ) IL offs 0x001B : 0x000000AE ( STACK_EMPTY ) IL offs 0x001F : 0x000000B8 ( STACK_EMPTY ) IL offs 0x002A : 0x000000DD ( STACK_EMPTY ) IL offs 0x0033 : 0x00000139 ( STACK_EMPTY ) IL offs 0x0038 : 0x0000013E ( STACK_EMPTY ) IL offs 0x003B : 0x00000141 ( STACK_EMPTY ) IL offs 0x003F : 0x0000014B ( STACK_EMPTY ) IL offs 0x0047 : 0x00000162 ( STACK_EMPTY ) IL offs 0x0050 : 0x000001B8 ( STACK_EMPTY ) IL offs 0x0055 : 0x000001BC ( STACK_EMPTY ) IL offs 0x0058 : 0x000001BF ( STACK_EMPTY ) IL offs 0x005C : 0x000001C6 ( STACK_EMPTY ) IL offs 0x0065 : 0x00000220 ( STACK_EMPTY ) IL offs 0x006A : 0x00000224 ( STACK_EMPTY ) IL offs 0x006D : 0x00000227 ( STACK_EMPTY ) IL offs 0x0071 : 0x0000022E ( STACK_EMPTY ) IL offs 0x0074 : 0x00000231 ( STACK_EMPTY ) IL offs 0x0078 : 0x00000233 ( STACK_EMPTY ) IL offs EPILOG : 0x00000233 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 10 *************** Variable debug info 10 vars 0( UNKNOWN) : From 00000000h to 00000028h, in rcx 1( UNKNOWN) : From 00000000h to 00000028h, in rdx 0( UNKNOWN) : From 00000028h to 000000ABh, in rsi 1( UNKNOWN) : From 00000028h to 000000ABh, in rdi 0( UNKNOWN) : From 000000B8h to 0000013Eh, in rsi 1( UNKNOWN) : From 000000B8h to 0000013Eh, in rdi 0( UNKNOWN) : From 0000014Bh to 000001BCh, in rsi 1( UNKNOWN) : From 0000014Bh to 000001BCh, in rdi 0( UNKNOWN) : From 000001C6h to 000001C9h, in rsi 1( UNKNOWN) : From 000001C6h to 00000224h, in rdi *************** In gcInfoBlockHdrSave() Set code length to 578. Set ReturnKind to Scalar. Set Outgoing stack arg area size to 32. Stack slot id for offset 56 (0x38) (sp) (byref, untracked) = 0. Stack slot id for offset 40 (0x28) (sp) (byref, untracked) = 1. Register slot id for reg rbx (byref) = 2. Register slot id for reg rsi (byref) = 3. Register slot id for reg rdi (byref) = 4. Register slot id for reg r15 (byref) = 5. Set state of slot 2 at instr offset 0x47 to Live. Set state of slot 3 at instr offset 0x47 to Live. Set state of slot 4 at instr offset 0x47 to Live. Set state of slot 2 at instr offset 0x4c to Dead. Set state of slot 3 at instr offset 0x4c to Dead. Set state of slot 4 at instr offset 0x4c to Dead. Set state of slot 2 at instr offset 0x97 to Live. Set state of slot 3 at instr offset 0x97 to Live. Set state of slot 4 at instr offset 0x97 to Live. Set state of slot 2 at instr offset 0x9c to Dead. Set state of slot 3 at instr offset 0x9c to Dead. Set state of slot 4 at instr offset 0x9c to Dead. Set state of slot 2 at instr offset 0xd5 to Live. Set state of slot 3 at instr offset 0xd5 to Live. Set state of slot 4 at instr offset 0xd5 to Live. Set state of slot 2 at instr offset 0xda to Dead. Set state of slot 3 at instr offset 0xda to Dead. Set state of slot 4 at instr offset 0xda to Dead. Set state of slot 3 at instr offset 0x12a to Live. Set state of slot 4 at instr offset 0x12a to Live. Set state of slot 5 at instr offset 0x12a to Live. Set state of slot 3 at instr offset 0x12f to Dead. Set state of slot 4 at instr offset 0x12f to Dead. Set state of slot 5 at instr offset 0x12f to Dead. Set state of slot 3 at instr offset 0x15d to Live. Set state of slot 4 at instr offset 0x15d to Live. Set state of slot 5 at instr offset 0x15d to Live. Set state of slot 3 at instr offset 0x162 to Dead. Set state of slot 4 at instr offset 0x162 to Dead. Set state of slot 5 at instr offset 0x162 to Dead. Set state of slot 3 at instr offset 0x1ab to Live. Set state of slot 4 at instr offset 0x1ab to Live. Set state of slot 5 at instr offset 0x1ab to Live. Set state of slot 3 at instr offset 0x1b0 to Dead. Set state of slot 4 at instr offset 0x1b0 to Dead. Set state of slot 5 at instr offset 0x1b0 to Dead. Set state of slot 4 at instr offset 0x211 to Live. Set state of slot 4 at instr offset 0x216 to Dead. Defining 7 call sites: Offset 0x47, size 5. Offset 0x97, size 5. Offset 0xd5, size 5. Offset 0x12a, size 5. Offset 0x15d, size 5. Offset 0x1ab, size 5. Offset 0x211, size 5. Method code size: 578 Allocations for System.Boolean:TryParse(struct,byref):bool (MethodHash=cf443699) count: 9748, size: 617629, max = 20128 allocateMemory: 851968, nraUsed: 764536 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 1.05% ASTNode | 117680 | 19.05% InstDesc | 16320 | 2.64% ImpStack | 0 | 0.00% BasicBlock | 5128 | 0.83% fgArgInfo | 672 | 0.11% fgArgInfoPtrArr | 96 | 0.02% FlowList | 1952 | 0.32% TreeStatementList | 0 | 0.00% SiScope | 784 | 0.13% FlatFPStateX87 | 0 | 0.00% DominatorMemory | 1448 | 0.23% LSRA | 10964 | 1.78% LSRA_Interval | 10560 | 1.71% LSRA_RefPosition | 26176 | 4.24% Reachability | 16 | 0.00% SSA | 26340 | 4.26% ValueNumber | 26229 | 4.25% LvaTable | 56156 | 9.09% UnwindInfo | 0 | 0.00% hashBv | 2056 | 0.33% bitset | 19264 | 3.12% FixedBitVect | 0 | 0.00% Generic | 16892 | 2.73% IndirAssignMap | 696 | 0.11% FieldSeqStore | 336 | 0.05% ZeroOffsetFieldMap | 56 | 0.01% ArrayInfoMap | 112 | 0.02% MemoryPhiArg | 384 | 0.06% CSE | 2624 | 0.42% GC | 4243 | 0.69% CorSig | 728 | 0.12% Inlining | 10816 | 1.75% ArrayStack | 11136 | 1.80% DebugInfo | 1392 | 0.23% DebugOnly | 222917 | 36.09% Codegen | 0 | 0.00% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 1780 | 0.29% RangeCheck | 0 | 0.00% CopyProp | 15216 | 2.46% ****** DONE compiling System.Boolean:TryParse(struct,byref):bool *** Methods compiled but not scanned: [S.P.CoreLib]System.InvalidProgramException..ctor(string) [S.P.CoreLib]Internal.Runtime.TypeLoaderExceptionHelper.CreateInvalidProgramException(ExceptionStringID,string) [S.P.CoreLib]Internal.Runtime.CompilerHelpers.ThrowHelpers.ThrowInvalidProgramExceptionWithArgument(ExceptionStringID,string)