From 07f6b7731015c0ad3e77e5e38ce3b08c70dfbc7b Mon Sep 17 00:00:00 2001 From: Khushal Modi Date: Fri, 8 Mar 2024 01:17:10 -0800 Subject: [PATCH] Enable the accelerated instructions for conversion for X86 --- src/coreclr/jit/compiler.h | 4 ++-- src/coreclr/jit/gentree.cpp | 29 ++++++++++++++++++--------- src/coreclr/jit/hwintrinsicxarch.cpp | 9 +-------- src/coreclr/jit/simdashwintrinsic.cpp | 12 ++--------- 4 files changed, 25 insertions(+), 29 deletions(-) diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h index 066a3f15769071..d5d4f01ccb59d0 100644 --- a/src/coreclr/jit/compiler.h +++ b/src/coreclr/jit/compiler.h @@ -3172,7 +3172,7 @@ class Compiler GenTree* op3, CorInfoType simdBaseJitType, unsigned simdSize); -#if defined(TARGET_AMD64) +#if defined(TARGET_XARCH) GenTree* gtNewSimdCvtNode(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, @@ -3184,7 +3184,7 @@ class Compiler var_types sourceType, var_types targetType, unsigned simdSize); -#endif //TARGET_AMD64 +#endif //TARGET_XARCH GenTree* gtNewSimdCreateBroadcastNode( var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize); diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index ef46aae3ca161b..1ecf5058ea7fe3 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -21251,7 +21251,7 @@ GenTree* Compiler::gtNewSimdCeilNode(var_types type, GenTree* op1, CorInfoType s return gtNewSimdHWIntrinsicNode(type, op1, intrinsic, simdBaseJitType, simdSize); } -#if defined(TARGET_AMD64) +#if defined(TARGET_XARCH) GenTreeVecCon* Compiler::gtCvtCtrlTbl(var_types type, var_types sourceType, var_types targetType, unsigned simdSize) { assert(IsBaselineSimdIsaSupportedDebugOnly()); @@ -21350,13 +21350,24 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type, if (varTypeIsSigned(simdTargetBaseType)) { - ssize_t actualMaxVal = (varTypeIsInt(simdTargetBaseType)) ? INT32_MAX : INT64_MAX; - - GenTree* maxVal = gtNewDconNode(static_cast(actualMaxVal), simdSourceBaseType); - - maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize); - GenTree* maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType), - simdTargetBaseJitType, simdSize); + GenTree* maxVal; + GenTree* maxValDup; + if (varTypeIsLong(simdTargetBaseType)) + { + long long actualMaxVal = INT64_MAX; + maxVal = gtNewDconNode(static_cast(actualMaxVal), simdSourceBaseType); + maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize); + maxValDup = + gtNewSimdCreateBroadcastNode(type, gtNewLconNode(actualMaxVal), simdTargetBaseJitType, simdSize); + } + else + { + ssize_t actualMaxVal = INT32_MAX; + maxVal = gtNewDconNode(static_cast(actualMaxVal), simdSourceBaseType); + maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize); + maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType), + simdTargetBaseJitType, simdSize); + } // we will be using the input value twice GenTree* fixupValDup = fgMakeMultiUse(&fixupVal); @@ -21375,7 +21386,7 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type, return gtNewSimdHWIntrinsicNode(type, fixupVal, hwIntrinsicID, simdSourceBaseJitType, simdSize); } } -#endif // TARGET_AMD64 +#endif // TARGET_XARCH GenTree* Compiler::gtNewSimdCmpOpNode( genTreeOps op, var_types type, GenTree* op1, GenTree* op2, CorInfoType simdBaseJitType, unsigned simdSize) diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp index 7c782aa5e3131a..b4a8e6495b1ff0 100644 --- a/src/coreclr/jit/hwintrinsicxarch.cpp +++ b/src/coreclr/jit/hwintrinsicxarch.cpp @@ -1446,7 +1446,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_DOUBLE); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { op1 = impSIMDPopStack(); @@ -1457,7 +1456,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize); } -#endif break; } @@ -1467,7 +1465,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_FLOAT); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { op1 = impSIMDPopStack(); @@ -1477,7 +1474,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize); } -#endif +# break; } @@ -1487,7 +1484,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_DOUBLE); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { op1 = impSIMDPopStack(); @@ -1497,7 +1493,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize); } -#endif break; } @@ -1507,7 +1502,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_FLOAT); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { op1 = impSIMDPopStack(); @@ -1517,7 +1511,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize); } -#endif break; } diff --git a/src/coreclr/jit/simdashwintrinsic.cpp b/src/coreclr/jit/simdashwintrinsic.cpp index 8c07d6aab0b06f..bad5f1c1111ed6 100644 --- a/src/coreclr/jit/simdashwintrinsic.cpp +++ b/src/coreclr/jit/simdashwintrinsic.cpp @@ -532,12 +532,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, case NI_VectorT_ConvertToUInt32: case NI_VectorT_ConvertToUInt64: { -#ifdef TARGET_AMD64 +#ifdef TARGET_XARCH if (IsBaselineVector512IsaSupportedOpportunistically()) { break; } -#endif // TARGET_AMD64 +#endif // TARGET_XARCH return nullptr; } @@ -1181,7 +1181,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_DOUBLE); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { NamedIntrinsic intrinsic = @@ -1191,7 +1190,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize); } -#endif return nullptr; } @@ -1199,7 +1197,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_FLOAT); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { NamedIntrinsic intrinsic = @@ -1209,7 +1206,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize); } -#endif return nullptr; } @@ -1217,7 +1213,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, { assert(sig->numArgs == 1); assert(simdBaseType == TYP_DOUBLE); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { NamedIntrinsic intrinsic = @@ -1227,14 +1222,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize); } -#endif return nullptr; } case NI_VectorT_ConvertToInt32: { assert(simdBaseType == TYP_FLOAT); -#if defined(TARGET_AMD64) if (IsBaselineVector512IsaSupportedOpportunistically()) { NamedIntrinsic intrinsic = @@ -1244,7 +1237,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic, return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize); } -#endif return nullptr; }