diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 4da5ba3dd174f..250a23904944a 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -3356,6 +3356,9 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree) else { // issue a full memory barrier before a volatile StInd + // Note: We cannot issue store barrier ishst because it is a weaker barrier. + // The loads can get rearranged around the barrier causing to read wrong + // value. instGen_MemoryBarrier(); } } diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 206b326ed6b7b..543c83af19a88 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -3886,6 +3886,14 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree) } } } +#ifdef TARGET_ARM64 + if (tree->gtFlags & GTF_IND_VOLATILE) + { + // For volatile store/loads when address is contained we always emit `dmb` + // if it's not - we emit one-way barriers i.e. ldar/stlr + doAddrMode = false; + } +#endif // TARGET_ARM64 if (doAddrMode && gtMarkAddrMode(addr, &costEx, &costSz, tree->TypeGet())) { goto DONE;