From 6d10e4c8bcd9f96ccd73748ff827561afa09af57 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 1 Sep 2022 10:05:58 -0700 Subject: [PATCH] [release/7.0] Fix use of uninitialized memory for Vector3 constants (#74880) * Fix use of uninitialized memory for Vector3 constants * Formatting * Update src/coreclr/jit/codegenarm64.cpp Co-authored-by: Jakob Botsch Nielsen * Apply the same fix for x64 * PR feedback Co-authored-by: Jan Kotas Co-authored-by: Jakob Botsch Nielsen --- src/coreclr/jit/codegenarm64.cpp | 10 ++++++++-- src/coreclr/jit/codegenxarch.cpp | 10 ++++++++-- src/coreclr/jit/instr.cpp | 8 +++++++- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 6850014a1d710..40d6e7cbbadbd 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2412,8 +2412,14 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre // Get a temp integer register to compute long address. regNumber addrReg = tree->GetSingleTempReg(); - simd16_t constValue = vecCon->gtSimd16Val; - CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); + simd16_t constValue = {}; + + if (vecCon->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t)); + else + constValue = vecCon->gtSimd16Val; + + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0); } diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index 9c95e410eb3d9..c788bbbe253a1 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -561,8 +561,14 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre case TYP_SIMD12: case TYP_SIMD16: { - simd16_t constValue = vecCon->gtSimd16Val; - CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); + simd16_t constValue = {}; + + if (vecCon->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t)); + else + constValue = vecCon->gtSimd16Val; + + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0); break; diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index 6d9494e59b541..572a556c0858d 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -765,7 +765,13 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) case TYP_SIMD12: case TYP_SIMD16: { - simd16_t constValue = op->AsVecCon()->gtSimd16Val; + simd16_t constValue = {}; + + if (op->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &op->AsVecCon()->gtSimd12Val, sizeof(simd12_t)); + else + constValue = op->AsVecCon()->gtSimd16Val; + return OperandDesc(emit->emitSimd16Const(constValue)); }