****** START compiling ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) (MethodHash=7798599a) Generating code for Unix arm64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = true OPTIONS: compDbgInfo = false OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 16 ldc.i4.0 IL_0001 0a stloc.0 IL_0002 00 nop IL_0003 02 ldarg.0 IL_0004 16 ldc.i4.0 IL_0005 fe 01 ceq IL_0007 16 ldc.i4.0 IL_0008 fe 01 ceq IL_000a 0b stloc.1 IL_000b 00 nop IL_000c 00 nop IL_000d 03 ldarg.1 IL_000e 16 ldc.i4.0 IL_000f fe 01 ceq IL_0011 16 ldc.i4.0 IL_0012 fe 01 ceq IL_0014 0c stloc.2 IL_0015 00 nop IL_0016 00 nop IL_0017 04 ldarg.2 IL_0018 16 ldc.i4.0 IL_0019 fe 01 ceq IL_001b 16 ldc.i4.0 IL_001c fe 01 ceq IL_001e 0d stloc.3 IL_001f 00 nop IL_0020 00 nop IL_0021 05 ldarg.3 IL_0022 16 ldc.i4.0 IL_0023 fe 01 ceq IL_0025 16 ldc.i4.0 IL_0026 fe 01 ceq IL_0028 13 04 stloc.s 0x4 IL_002a 00 nop IL_002b 00 nop IL_002c 0e 04 ldarg.s 0x4 IL_002e 16 ldc.i4.0 IL_002f fe 01 ceq IL_0031 16 ldc.i4.0 IL_0032 fe 01 ceq IL_0034 13 05 stloc.s 0x5 IL_0036 00 nop IL_0037 00 nop IL_0038 0e 05 ldarg.s 0x5 IL_003a 16 ldc.i4.0 IL_003b fe 01 ceq IL_003d 16 ldc.i4.0 IL_003e fe 01 ceq IL_0040 13 06 stloc.s 0x6 IL_0042 00 nop IL_0043 00 nop IL_0044 0e 06 ldarg.s 0x6 IL_0046 16 ldc.i4.0 IL_0047 fe 01 ceq IL_0049 16 ldc.i4.0 IL_004a fe 01 ceq IL_004c 13 07 stloc.s 0x7 IL_004e 00 nop IL_004f 00 nop IL_0050 0e 07 ldarg.s 0x7 IL_0052 16 ldc.i4.0 IL_0053 fe 01 ceq IL_0055 16 ldc.i4.0 IL_0056 fe 01 ceq IL_0058 13 08 stloc.s 0x8 IL_005a 00 nop IL_005b 00 nop IL_005c 0e 08 ldarg.s 0x8 IL_005e 16 ldc.i4.0 IL_005f fe 01 ceq IL_0061 16 ldc.i4.0 IL_0062 fe 01 ceq IL_0064 13 09 stloc.s 0x9 IL_0066 00 nop IL_0067 00 nop IL_0068 0e 09 ldarg.s 0x9 IL_006a 16 ldc.i4.0 IL_006b fe 01 ceq IL_006d 16 ldc.i4.0 IL_006e fe 01 ceq IL_0070 13 0a stloc.s 0xA IL_0072 00 nop IL_0073 00 nop IL_0074 0e 0a ldarg.s 0xA IL_0076 16 ldc.i4.0 IL_0077 fe 01 ceq IL_0079 16 ldc.i4.0 IL_007a fe 01 ceq IL_007c 13 0b stloc.s 0xB IL_007e 00 nop IL_007f 00 nop IL_0080 0e 0b ldarg.s 0xB IL_0082 16 ldc.i4.0 IL_0083 fe 01 ceq IL_0085 16 ldc.i4.0 IL_0086 fe 01 ceq IL_0088 13 0c stloc.s 0xC IL_008a 00 nop IL_008b 00 nop IL_008c 0e 0c ldarg.s 0xC IL_008e 16 ldc.i4.0 IL_008f fe 01 ceq IL_0091 16 ldc.i4.0 IL_0092 fe 01 ceq IL_0094 13 0d stloc.s 0xD IL_0096 00 nop IL_0097 00 nop IL_0098 0e 0d ldarg.s 0xD IL_009a 16 ldc.i4.0 IL_009b fe 01 ceq IL_009d 16 ldc.i4.0 IL_009e fe 01 ceq IL_00a0 13 0e stloc.s 0xE IL_00a2 00 nop IL_00a3 00 nop IL_00a4 0e 0e ldarg.s 0xE IL_00a6 16 ldc.i4.0 IL_00a7 fe 01 ceq IL_00a9 16 ldc.i4.0 IL_00aa fe 01 ceq IL_00ac 13 0f stloc.s 0xF IL_00ae 00 nop IL_00af 00 nop IL_00b0 0e 0f ldarg.s 0xF IL_00b2 16 ldc.i4.0 IL_00b3 fe 01 ceq IL_00b5 16 ldc.i4.0 IL_00b6 fe 01 ceq IL_00b8 13 10 stloc.s 0x10 IL_00ba 00 nop IL_00bb 00 nop IL_00bc 0e 10 ldarg.s 0x10 IL_00be 13 11 stloc.s 0x11 IL_00c0 00 nop IL_00c1 07 ldloc.1 IL_00c2 08 ldloc.2 IL_00c3 09 ldloc.3 IL_00c4 11 04 ldloc.s 0x4 IL_00c6 11 05 ldloc.s 0x5 IL_00c8 11 06 ldloc.s 0x6 IL_00ca 11 07 ldloc.s 0x7 IL_00cc 11 08 ldloc.s 0x8 IL_00ce 11 09 ldloc.s 0x9 IL_00d0 11 0a ldloc.s 0xA IL_00d2 11 0b ldloc.s 0xB IL_00d4 11 0c ldloc.s 0xC IL_00d6 11 0d ldloc.s 0xD IL_00d8 11 0e ldloc.s 0xE IL_00da 11 0f ldloc.s 0xF IL_00dc 11 10 ldloc.s 0x10 IL_00de 11 11 ldloc.s 0x11 IL_00e0 28 01 00 00 06 call 0x6000001 IL_00e5 1f 48 ldc.i4.s 0x48 IL_00e7 58 add IL_00e8 4d ldind.i IL_00e9 4d ldind.i IL_00ea 29 ff ff ff 11 calli 0x11FFFFFF IL_00ef 00 nop IL_00f0 00 nop IL_00f1 00 nop IL_00f2 00 nop IL_00f3 00 nop IL_00f4 00 nop IL_00f5 00 nop IL_00f6 00 nop IL_00f7 00 nop IL_00f8 00 nop IL_00f9 00 nop IL_00fa 00 nop IL_00fb 00 nop IL_00fc 00 nop IL_00fd 00 nop IL_00fe 00 nop IL_00ff 00 nop IL_0100 00 nop IL_0101 00 nop IL_0102 00 nop IL_0103 00 nop IL_0104 00 nop IL_0105 00 nop IL_0106 00 nop IL_0107 00 nop IL_0108 00 nop IL_0109 00 nop IL_010a 00 nop IL_010b 00 nop IL_010c 00 nop IL_010d 00 nop IL_010e 00 nop IL_010f 00 nop IL_0110 00 nop IL_0111 2a ret Arg #0 passed in register(s) x0 Arg #1 passed in register(s) x1 Arg #2 passed in register(s) x2 Arg #3 passed in register(s) x3 Arg #4 passed in register(s) x4 Arg #5 passed in register(s) x5 Arg #6 passed in register(s) x6 Arg #7 passed in register(s) x7 lvaGrabTemp returning 35 (V35 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 arg0 bool ; V01 arg1 bool ; V02 arg2 bool ; V03 arg3 bool ; V04 arg4 bool ; V05 arg5 bool ; V06 arg6 bool ; V07 arg7 bool ; V08 arg8 bool ; V09 arg9 bool ; V10 arg10 bool ; V11 arg11 bool ; V12 arg12 bool ; V13 arg13 bool ; V14 arg14 bool ; V15 arg15 bool ; V16 arg16 long ; V17 loc0 int ; V18 loc1 int ; V19 loc2 int ; V20 loc3 int ; V21 loc4 int ; V22 loc5 int ; V23 loc6 int ; V24 loc7 int ; V25 loc8 int ; V26 loc9 int ; V27 loc10 int ; V28 loc11 int ; V29 loc12 int ; V30 loc13 int ; V31 loc14 int ; V32 loc15 int ; V33 loc16 int ; V34 loc17 long ; V35 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) *************** In fgFindBasicBlocks() for ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) Marked V17 as a single def local Marked V18 as a single def local Marked V19 as a single def local Marked V20 as a single def local Marked V21 as a single def local Marked V22 as a single def local Marked V23 as a single def local Marked V24 as a single def local Marked V25 as a single def local Marked V26 as a single def local Marked V27 as a single def local Marked V28 as a single def local Marked V29 as a single def local Marked V30 as a single def local Marked V31 as a single def local Marked V32 as a single def local Marked V33 as a single def local Marked V34 as a single def local Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..112) CLFLG_MINOPT set for method ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) IL Code Size,Instr 274, 192, Basic Block count 1, Local Variable Num,Ref count 36, 52 for method ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) IL Code Size,Instr 274, 192, Basic Block count 1, Local Variable Num,Ref count 36, 52 for method ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) OPTIONS: opts.MinOpts() == true Basic block list for 'ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..112) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Compiling 1525 ILStubClass::IL_STUB_PInvoke, IL size = 274, hash=0x7798599a MinOpts *************** Starting PHASE Pre-import lvaGrabTemp returning 36 (V36 tmp1) (a long lifetime temp) called for stub argument. Local V36 should not be enregistered because: it is address exposed *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) impImportBlockPending for BB01 Importing BB01 (PC=000) of 'ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long)' [ 0] 0 (0x000) ldc.i4.0 0 [ 1] 1 (0x001) stloc.0 [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V17 loc0 [000000] ------------ \--* CNS_INT int 0 [ 0] 2 (0x002) nop [000003] ------------ * NO_OP void [ 0] 3 (0x003) ldarg.0 [ 1] 4 (0x004) ldc.i4.0 0 [ 2] 5 (0x005) ceq [ 1] 7 (0x007) ldc.i4.0 0 [ 2] 8 (0x008) ceq [ 1] 10 (0x00a) stloc.1 [000010] -A---------- * ASG int [000009] D------N---- +--* LCL_VAR int V18 loc1 [000008] ------------ \--* EQ int [000006] ------------ +--* EQ int [000004] ------------ | +--* LCL_VAR bool V00 arg0 [000005] ------------ | \--* CNS_INT int 0 [000007] ------------ \--* CNS_INT int 0 [ 0] 11 (0x00b) nop [000011] ------------ * NO_OP void [ 0] 12 (0x00c) nop [000012] ------------ * NO_OP void [ 0] 13 (0x00d) ldarg.1 [ 1] 14 (0x00e) ldc.i4.0 0 [ 2] 15 (0x00f) ceq [ 1] 17 (0x011) ldc.i4.0 0 [ 2] 18 (0x012) ceq [ 1] 20 (0x014) stloc.2 [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V19 loc2 [000017] ------------ \--* EQ int [000015] ------------ +--* EQ int [000013] ------------ | +--* LCL_VAR bool V01 arg1 [000014] ------------ | \--* CNS_INT int 0 [000016] ------------ \--* CNS_INT int 0 [ 0] 21 (0x015) nop [000020] ------------ * NO_OP void [ 0] 22 (0x016) nop [000021] ------------ * NO_OP void [ 0] 23 (0x017) ldarg.2 [ 1] 24 (0x018) ldc.i4.0 0 [ 2] 25 (0x019) ceq [ 1] 27 (0x01b) ldc.i4.0 0 [ 2] 28 (0x01c) ceq [ 1] 30 (0x01e) stloc.3 [000028] -A---------- * ASG int [000027] D------N---- +--* LCL_VAR int V20 loc3 [000026] ------------ \--* EQ int [000024] ------------ +--* EQ int [000022] ------------ | +--* LCL_VAR bool V02 arg2 [000023] ------------ | \--* CNS_INT int 0 [000025] ------------ \--* CNS_INT int 0 [ 0] 31 (0x01f) nop [000029] ------------ * NO_OP void [ 0] 32 (0x020) nop [000030] ------------ * NO_OP void [ 0] 33 (0x021) ldarg.3 [ 1] 34 (0x022) ldc.i4.0 0 [ 2] 35 (0x023) ceq [ 1] 37 (0x025) ldc.i4.0 0 [ 2] 38 (0x026) ceq [ 1] 40 (0x028) stloc.s 4 [000037] -A---------- * ASG int [000036] D------N---- +--* LCL_VAR int V21 loc4 [000035] ------------ \--* EQ int [000033] ------------ +--* EQ int [000031] ------------ | +--* LCL_VAR bool V03 arg3 [000032] ------------ | \--* CNS_INT int 0 [000034] ------------ \--* CNS_INT int 0 [ 0] 42 (0x02a) nop [000038] ------------ * NO_OP void [ 0] 43 (0x02b) nop [000039] ------------ * NO_OP void [ 0] 44 (0x02c) ldarg.s 4 [ 1] 46 (0x02e) ldc.i4.0 0 [ 2] 47 (0x02f) ceq [ 1] 49 (0x031) ldc.i4.0 0 [ 2] 50 (0x032) ceq [ 1] 52 (0x034) stloc.s 5 [000046] -A---------- * ASG int [000045] D------N---- +--* LCL_VAR int V22 loc5 [000044] ------------ \--* EQ int [000042] ------------ +--* EQ int [000040] ------------ | +--* LCL_VAR bool V04 arg4 [000041] ------------ | \--* CNS_INT int 0 [000043] ------------ \--* CNS_INT int 0 [ 0] 54 (0x036) nop [000047] ------------ * NO_OP void [ 0] 55 (0x037) nop [000048] ------------ * NO_OP void [ 0] 56 (0x038) ldarg.s 5 [ 1] 58 (0x03a) ldc.i4.0 0 [ 2] 59 (0x03b) ceq [ 1] 61 (0x03d) ldc.i4.0 0 [ 2] 62 (0x03e) ceq [ 1] 64 (0x040) stloc.s 6 [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V23 loc6 [000053] ------------ \--* EQ int [000051] ------------ +--* EQ int [000049] ------------ | +--* LCL_VAR bool V05 arg5 [000050] ------------ | \--* CNS_INT int 0 [000052] ------------ \--* CNS_INT int 0 [ 0] 66 (0x042) nop [000056] ------------ * NO_OP void [ 0] 67 (0x043) nop [000057] ------------ * NO_OP void [ 0] 68 (0x044) ldarg.s 6 [ 1] 70 (0x046) ldc.i4.0 0 [ 2] 71 (0x047) ceq [ 1] 73 (0x049) ldc.i4.0 0 [ 2] 74 (0x04a) ceq [ 1] 76 (0x04c) stloc.s 7 [000064] -A---------- * ASG int [000063] D------N---- +--* LCL_VAR int V24 loc7 [000062] ------------ \--* EQ int [000060] ------------ +--* EQ int [000058] ------------ | +--* LCL_VAR bool V06 arg6 [000059] ------------ | \--* CNS_INT int 0 [000061] ------------ \--* CNS_INT int 0 [ 0] 78 (0x04e) nop [000065] ------------ * NO_OP void [ 0] 79 (0x04f) nop [000066] ------------ * NO_OP void [ 0] 80 (0x050) ldarg.s 7 [ 1] 82 (0x052) ldc.i4.0 0 [ 2] 83 (0x053) ceq [ 1] 85 (0x055) ldc.i4.0 0 [ 2] 86 (0x056) ceq [ 1] 88 (0x058) stloc.s 8 [000073] -A---------- * ASG int [000072] D------N---- +--* LCL_VAR int V25 loc8 [000071] ------------ \--* EQ int [000069] ------------ +--* EQ int [000067] ------------ | +--* LCL_VAR bool V07 arg7 [000068] ------------ | \--* CNS_INT int 0 [000070] ------------ \--* CNS_INT int 0 [ 0] 90 (0x05a) nop [000074] ------------ * NO_OP void [ 0] 91 (0x05b) nop [000075] ------------ * NO_OP void [ 0] 92 (0x05c) ldarg.s 8 [ 1] 94 (0x05e) ldc.i4.0 0 [ 2] 95 (0x05f) ceq [ 1] 97 (0x061) ldc.i4.0 0 [ 2] 98 (0x062) ceq [ 1] 100 (0x064) stloc.s 9 [000082] -A---------- * ASG int [000081] D------N---- +--* LCL_VAR int V26 loc9 [000080] ------------ \--* EQ int [000078] ------------ +--* EQ int [000076] ------------ | +--* LCL_VAR bool V08 arg8 [000077] ------------ | \--* CNS_INT int 0 [000079] ------------ \--* CNS_INT int 0 [ 0] 102 (0x066) nop [000083] ------------ * NO_OP void [ 0] 103 (0x067) nop [000084] ------------ * NO_OP void [ 0] 104 (0x068) ldarg.s 9 [ 1] 106 (0x06a) ldc.i4.0 0 [ 2] 107 (0x06b) ceq [ 1] 109 (0x06d) ldc.i4.0 0 [ 2] 110 (0x06e) ceq [ 1] 112 (0x070) stloc.s 10 [000091] -A---------- * ASG int [000090] D------N---- +--* LCL_VAR int V27 loc10 [000089] ------------ \--* EQ int [000087] ------------ +--* EQ int [000085] ------------ | +--* LCL_VAR bool V09 arg9 [000086] ------------ | \--* CNS_INT int 0 [000088] ------------ \--* CNS_INT int 0 [ 0] 114 (0x072) nop [000092] ------------ * NO_OP void [ 0] 115 (0x073) nop [000093] ------------ * NO_OP void [ 0] 116 (0x074) ldarg.s 10 [ 1] 118 (0x076) ldc.i4.0 0 [ 2] 119 (0x077) ceq [ 1] 121 (0x079) ldc.i4.0 0 [ 2] 122 (0x07a) ceq [ 1] 124 (0x07c) stloc.s 11 [000100] -A---------- * ASG int [000099] D------N---- +--* LCL_VAR int V28 loc11 [000098] ------------ \--* EQ int [000096] ------------ +--* EQ int [000094] ------------ | +--* LCL_VAR bool V10 arg10 [000095] ------------ | \--* CNS_INT int 0 [000097] ------------ \--* CNS_INT int 0 [ 0] 126 (0x07e) nop [000101] ------------ * NO_OP void [ 0] 127 (0x07f) nop [000102] ------------ * NO_OP void [ 0] 128 (0x080) ldarg.s 11 [ 1] 130 (0x082) ldc.i4.0 0 [ 2] 131 (0x083) ceq [ 1] 133 (0x085) ldc.i4.0 0 [ 2] 134 (0x086) ceq [ 1] 136 (0x088) stloc.s 12 [000109] -A---------- * ASG int [000108] D------N---- +--* LCL_VAR int V29 loc12 [000107] ------------ \--* EQ int [000105] ------------ +--* EQ int [000103] ------------ | +--* LCL_VAR bool V11 arg11 [000104] ------------ | \--* CNS_INT int 0 [000106] ------------ \--* CNS_INT int 0 [ 0] 138 (0x08a) nop [000110] ------------ * NO_OP void [ 0] 139 (0x08b) nop [000111] ------------ * NO_OP void [ 0] 140 (0x08c) ldarg.s 12 [ 1] 142 (0x08e) ldc.i4.0 0 [ 2] 143 (0x08f) ceq [ 1] 145 (0x091) ldc.i4.0 0 [ 2] 146 (0x092) ceq [ 1] 148 (0x094) stloc.s 13 [000118] -A---------- * ASG int [000117] D------N---- +--* LCL_VAR int V30 loc13 [000116] ------------ \--* EQ int [000114] ------------ +--* EQ int [000112] ------------ | +--* LCL_VAR bool V12 arg12 [000113] ------------ | \--* CNS_INT int 0 [000115] ------------ \--* CNS_INT int 0 [ 0] 150 (0x096) nop [000119] ------------ * NO_OP void [ 0] 151 (0x097) nop [000120] ------------ * NO_OP void [ 0] 152 (0x098) ldarg.s 13 [ 1] 154 (0x09a) ldc.i4.0 0 [ 2] 155 (0x09b) ceq [ 1] 157 (0x09d) ldc.i4.0 0 [ 2] 158 (0x09e) ceq [ 1] 160 (0x0a0) stloc.s 14 [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V31 loc14 [000125] ------------ \--* EQ int [000123] ------------ +--* EQ int [000121] ------------ | +--* LCL_VAR bool V13 arg13 [000122] ------------ | \--* CNS_INT int 0 [000124] ------------ \--* CNS_INT int 0 [ 0] 162 (0x0a2) nop [000128] ------------ * NO_OP void [ 0] 163 (0x0a3) nop [000129] ------------ * NO_OP void [ 0] 164 (0x0a4) ldarg.s 14 [ 1] 166 (0x0a6) ldc.i4.0 0 [ 2] 167 (0x0a7) ceq [ 1] 169 (0x0a9) ldc.i4.0 0 [ 2] 170 (0x0aa) ceq [ 1] 172 (0x0ac) stloc.s 15 [000136] -A---------- * ASG int [000135] D------N---- +--* LCL_VAR int V32 loc15 [000134] ------------ \--* EQ int [000132] ------------ +--* EQ int [000130] ------------ | +--* LCL_VAR bool V14 arg14 [000131] ------------ | \--* CNS_INT int 0 [000133] ------------ \--* CNS_INT int 0 [ 0] 174 (0x0ae) nop [000137] ------------ * NO_OP void [ 0] 175 (0x0af) nop [000138] ------------ * NO_OP void [ 0] 176 (0x0b0) ldarg.s 15 [ 1] 178 (0x0b2) ldc.i4.0 0 [ 2] 179 (0x0b3) ceq [ 1] 181 (0x0b5) ldc.i4.0 0 [ 2] 182 (0x0b6) ceq [ 1] 184 (0x0b8) stloc.s 16 [000145] -A---------- * ASG int [000144] D------N---- +--* LCL_VAR int V33 loc16 [000143] ------------ \--* EQ int [000141] ------------ +--* EQ int [000139] ------------ | +--* LCL_VAR bool V15 arg15 [000140] ------------ | \--* CNS_INT int 0 [000142] ------------ \--* CNS_INT int 0 [ 0] 186 (0x0ba) nop [000146] ------------ * NO_OP void [ 0] 187 (0x0bb) nop [000147] ------------ * NO_OP void [ 0] 188 (0x0bc) ldarg.s 16 [ 1] 190 (0x0be) stloc.s 17 [000150] -A---------- * ASG long [000149] D------N---- +--* LCL_VAR long V34 loc17 [000148] ------------ \--* LCL_VAR long V16 arg16 [ 0] 192 (0x0c0) nop [000151] ------------ * NO_OP void [ 0] 193 (0x0c1) ldloc.1 [ 1] 194 (0x0c2) ldloc.2 [ 2] 195 (0x0c3) ldloc.3 [ 3] 196 (0x0c4) ldloc.s 4 [ 4] 198 (0x0c6) ldloc.s 5 [ 5] 200 (0x0c8) ldloc.s 6 [ 6] 202 (0x0ca) ldloc.s 7 [ 7] 204 (0x0cc) ldloc.s 8 [ 8] 206 (0x0ce) ldloc.s 9 [ 9] 208 (0x0d0) ldloc.s 10 [10] 210 (0x0d2) ldloc.s 11 [11] 212 (0x0d4) ldloc.s 12 [12] 214 (0x0d6) ldloc.s 13 [13] 216 (0x0d8) ldloc.s 14 [14] 218 (0x0da) ldloc.s 15 [15] 220 (0x0dc) ldloc.s 16 [16] 222 (0x0de) ldloc.s 17 [17] 224 (0x0e0) call 06000001 In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 [18] 229 (0x0e5) ldc.i4.s 72 [19] 231 (0x0e7) add [18] 232 (0x0e8) ldind.i [18] 233 (0x0e9) ldind.i [18] 234 (0x0ea) calli 11FFFFFF lvaGrabTemp returning 37 (V37 tmp2) called for impImportIndirectCall. [000176] -A-XG------- * ASG long [000175] D------N---- +--* LCL_VAR long V37 tmp2 [000174] *--XG------- \--* IND long [000173] *--XG------- \--* IND long [000172] ------------ \--* ADD long [000169] ------------ +--* LCL_VAR long (AX) V36 tmp1 [000171] ------------ \--* CAST long <- int [000170] ------------ \--* CNS_INT int 72 In Compiler::impImportCall: opcode is calli, kind=0, callRetType is void, structSize is 0 Inline a CALLI PINVOKE call from method ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) [000178] --CXG------- * CALL ind unman popargs void [000152] ------------ arg0 +--* LCL_VAR int V18 loc1 [000153] ------------ arg1 +--* LCL_VAR int V19 loc2 [000154] ------------ arg2 +--* LCL_VAR int V20 loc3 [000155] ------------ arg3 +--* LCL_VAR int V21 loc4 [000156] ------------ arg4 +--* LCL_VAR int V22 loc5 [000157] ------------ arg5 +--* LCL_VAR int V23 loc6 [000158] ------------ arg6 +--* LCL_VAR int V24 loc7 [000159] ------------ arg7 +--* LCL_VAR int V25 loc8 [000160] ------------ arg8 +--* LCL_VAR int V26 loc9 [000161] ------------ arg9 +--* LCL_VAR int V27 loc10 [000162] ------------ arg10 +--* LCL_VAR int V28 loc11 [000163] ------------ arg11 +--* LCL_VAR int V29 loc12 [000164] ------------ arg12 +--* LCL_VAR int V30 loc13 [000165] ------------ arg13 +--* LCL_VAR int V31 loc14 [000166] ------------ arg14 +--* LCL_VAR int V32 loc15 [000167] ------------ arg15 +--* LCL_VAR int V33 loc16 [000168] ------------ arg16 +--* LCL_VAR long V34 loc17 [000177] ------------ calli tgt \--* LCL_VAR long V37 tmp2 [ 0] 239 (0x0ef) nop [000179] ------------ * NO_OP void [ 0] 240 (0x0f0) nop [000180] ------------ * NO_OP void [ 0] 241 (0x0f1) nop [000181] ------------ * NO_OP void [ 0] 242 (0x0f2) nop [000182] ------------ * NO_OP void [ 0] 243 (0x0f3) nop [000183] ------------ * NO_OP void [ 0] 244 (0x0f4) nop [000184] ------------ * NO_OP void [ 0] 245 (0x0f5) nop [000185] ------------ * NO_OP void [ 0] 246 (0x0f6) nop [000186] ------------ * NO_OP void [ 0] 247 (0x0f7) nop [000187] ------------ * NO_OP void [ 0] 248 (0x0f8) nop [000188] ------------ * NO_OP void [ 0] 249 (0x0f9) nop [000189] ------------ * NO_OP void [ 0] 250 (0x0fa) nop [000190] ------------ * NO_OP void [ 0] 251 (0x0fb) nop [000191] ------------ * NO_OP void [ 0] 252 (0x0fc) nop [000192] ------------ * NO_OP void [ 0] 253 (0x0fd) nop [000193] ------------ * NO_OP void [ 0] 254 (0x0fe) nop [000194] ------------ * NO_OP void [ 0] 255 (0x0ff) nop [000195] ------------ * NO_OP void [ 0] 256 (0x100) nop [000196] ------------ * NO_OP void [ 0] 257 (0x101) nop [000197] ------------ * NO_OP void [ 0] 258 (0x102) nop [000198] ------------ * NO_OP void [ 0] 259 (0x103) nop [000199] ------------ * NO_OP void [ 0] 260 (0x104) nop [000200] ------------ * NO_OP void [ 0] 261 (0x105) nop [000201] ------------ * NO_OP void [ 0] 262 (0x106) nop [000202] ------------ * NO_OP void [ 0] 263 (0x107) nop [000203] ------------ * NO_OP void [ 0] 264 (0x108) nop [000204] ------------ * NO_OP void [ 0] 265 (0x109) nop [000205] ------------ * NO_OP void [ 0] 266 (0x10a) nop [000206] ------------ * NO_OP void [ 0] 267 (0x10b) nop [000207] ------------ * NO_OP void [ 0] 268 (0x10c) nop [000208] ------------ * NO_OP void [ 0] 269 (0x10d) nop [000209] ------------ * NO_OP void [ 0] 270 (0x10e) nop [000210] ------------ * NO_OP void [ 0] 271 (0x10f) nop [000211] ------------ * NO_OP void [ 0] 272 (0x110) nop [000212] ------------ * NO_OP void [ 0] 273 (0x111) ret [000213] ------------ * RETURN void *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..112) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..112) (return), preds={} succs={} ***** BB01 [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V17 loc0 [000000] ------------ \--* CNS_INT int 0 ***** BB01 [000003] ------------ * NO_OP void ***** BB01 [000010] -A---------- * ASG int [000009] D------N---- +--* LCL_VAR int V18 loc1 [000008] ------------ \--* EQ int [000006] ------------ +--* EQ int [000004] ------------ | +--* LCL_VAR bool V00 arg0 [000005] ------------ | \--* CNS_INT int 0 [000007] ------------ \--* CNS_INT int 0 ***** BB01 [000011] ------------ * NO_OP void ***** BB01 [000012] ------------ * NO_OP void ***** BB01 [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V19 loc2 [000017] ------------ \--* EQ int [000015] ------------ +--* EQ int [000013] ------------ | +--* LCL_VAR bool V01 arg1 [000014] ------------ | \--* CNS_INT int 0 [000016] ------------ \--* CNS_INT int 0 ***** BB01 [000020] ------------ * NO_OP void ***** BB01 [000021] ------------ * NO_OP void ***** BB01 [000028] -A---------- * ASG int [000027] D------N---- +--* LCL_VAR int V20 loc3 [000026] ------------ \--* EQ int [000024] ------------ +--* EQ int [000022] ------------ | +--* LCL_VAR bool V02 arg2 [000023] ------------ | \--* CNS_INT int 0 [000025] ------------ \--* CNS_INT int 0 ***** BB01 [000029] ------------ * NO_OP void ***** BB01 [000030] ------------ * NO_OP void ***** BB01 [000037] -A---------- * ASG int [000036] D------N---- +--* LCL_VAR int V21 loc4 [000035] ------------ \--* EQ int [000033] ------------ +--* EQ int [000031] ------------ | +--* LCL_VAR bool V03 arg3 [000032] ------------ | \--* CNS_INT int 0 [000034] ------------ \--* CNS_INT int 0 ***** BB01 [000038] ------------ * NO_OP void ***** BB01 [000039] ------------ * NO_OP void ***** BB01 [000046] -A---------- * ASG int [000045] D------N---- +--* LCL_VAR int V22 loc5 [000044] ------------ \--* EQ int [000042] ------------ +--* EQ int [000040] ------------ | +--* LCL_VAR bool V04 arg4 [000041] ------------ | \--* CNS_INT int 0 [000043] ------------ \--* CNS_INT int 0 ***** BB01 [000047] ------------ * NO_OP void ***** BB01 [000048] ------------ * NO_OP void ***** BB01 [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V23 loc6 [000053] ------------ \--* EQ int [000051] ------------ +--* EQ int [000049] ------------ | +--* LCL_VAR bool V05 arg5 [000050] ------------ | \--* CNS_INT int 0 [000052] ------------ \--* CNS_INT int 0 ***** BB01 [000056] ------------ * NO_OP void ***** BB01 [000057] ------------ * NO_OP void ***** BB01 [000064] -A---------- * ASG int [000063] D------N---- +--* LCL_VAR int V24 loc7 [000062] ------------ \--* EQ int [000060] ------------ +--* EQ int [000058] ------------ | +--* LCL_VAR bool V06 arg6 [000059] ------------ | \--* CNS_INT int 0 [000061] ------------ \--* CNS_INT int 0 ***** BB01 [000065] ------------ * NO_OP void ***** BB01 [000066] ------------ * NO_OP void ***** BB01 [000073] -A---------- * ASG int [000072] D------N---- +--* LCL_VAR int V25 loc8 [000071] ------------ \--* EQ int [000069] ------------ +--* EQ int [000067] ------------ | +--* LCL_VAR bool V07 arg7 [000068] ------------ | \--* CNS_INT int 0 [000070] ------------ \--* CNS_INT int 0 ***** BB01 [000074] ------------ * NO_OP void ***** BB01 [000075] ------------ * NO_OP void ***** BB01 [000082] -A---------- * ASG int [000081] D------N---- +--* LCL_VAR int V26 loc9 [000080] ------------ \--* EQ int [000078] ------------ +--* EQ int [000076] ------------ | +--* LCL_VAR bool V08 arg8 [000077] ------------ | \--* CNS_INT int 0 [000079] ------------ \--* CNS_INT int 0 ***** BB01 [000083] ------------ * NO_OP void ***** BB01 [000084] ------------ * NO_OP void ***** BB01 [000091] -A---------- * ASG int [000090] D------N---- +--* LCL_VAR int V27 loc10 [000089] ------------ \--* EQ int [000087] ------------ +--* EQ int [000085] ------------ | +--* LCL_VAR bool V09 arg9 [000086] ------------ | \--* CNS_INT int 0 [000088] ------------ \--* CNS_INT int 0 ***** BB01 [000092] ------------ * NO_OP void ***** BB01 [000093] ------------ * NO_OP void ***** BB01 [000100] -A---------- * ASG int [000099] D------N---- +--* LCL_VAR int V28 loc11 [000098] ------------ \--* EQ int [000096] ------------ +--* EQ int [000094] ------------ | +--* LCL_VAR bool V10 arg10 [000095] ------------ | \--* CNS_INT int 0 [000097] ------------ \--* CNS_INT int 0 ***** BB01 [000101] ------------ * NO_OP void ***** BB01 [000102] ------------ * NO_OP void ***** BB01 [000109] -A---------- * ASG int [000108] D------N---- +--* LCL_VAR int V29 loc12 [000107] ------------ \--* EQ int [000105] ------------ +--* EQ int [000103] ------------ | +--* LCL_VAR bool V11 arg11 [000104] ------------ | \--* CNS_INT int 0 [000106] ------------ \--* CNS_INT int 0 ***** BB01 [000110] ------------ * NO_OP void ***** BB01 [000111] ------------ * NO_OP void ***** BB01 [000118] -A---------- * ASG int [000117] D------N---- +--* LCL_VAR int V30 loc13 [000116] ------------ \--* EQ int [000114] ------------ +--* EQ int [000112] ------------ | +--* LCL_VAR bool V12 arg12 [000113] ------------ | \--* CNS_INT int 0 [000115] ------------ \--* CNS_INT int 0 ***** BB01 [000119] ------------ * NO_OP void ***** BB01 [000120] ------------ * NO_OP void ***** BB01 [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V31 loc14 [000125] ------------ \--* EQ int [000123] ------------ +--* EQ int [000121] ------------ | +--* LCL_VAR bool V13 arg13 [000122] ------------ | \--* CNS_INT int 0 [000124] ------------ \--* CNS_INT int 0 ***** BB01 [000128] ------------ * NO_OP void ***** BB01 [000129] ------------ * NO_OP void ***** BB01 [000136] -A---------- * ASG int [000135] D------N---- +--* LCL_VAR int V32 loc15 [000134] ------------ \--* EQ int [000132] ------------ +--* EQ int [000130] ------------ | +--* LCL_VAR bool V14 arg14 [000131] ------------ | \--* CNS_INT int 0 [000133] ------------ \--* CNS_INT int 0 ***** BB01 [000137] ------------ * NO_OP void ***** BB01 [000138] ------------ * NO_OP void ***** BB01 [000145] -A---------- * ASG int [000144] D------N---- +--* LCL_VAR int V33 loc16 [000143] ------------ \--* EQ int [000141] ------------ +--* EQ int [000139] ------------ | +--* LCL_VAR bool V15 arg15 [000140] ------------ | \--* CNS_INT int 0 [000142] ------------ \--* CNS_INT int 0 ***** BB01 [000146] ------------ * NO_OP void ***** BB01 [000147] ------------ * NO_OP void ***** BB01 [000150] -A---------- * ASG long [000149] D------N---- +--* LCL_VAR long V34 loc17 [000148] ------------ \--* LCL_VAR long V16 arg16 ***** BB01 [000151] ------------ * NO_OP void ***** BB01 [000176] -A-XG------- * ASG long [000175] D------N---- +--* LCL_VAR long V37 tmp2 [000174] *--XG------- \--* IND long [000173] *--XG------- \--* IND long [000172] ------------ \--* ADD long [000169] ------------ +--* LCL_VAR long (AX) V36 tmp1 [000171] ------------ \--* CAST long <- int [000170] ------------ \--* CNS_INT int 72 ***** BB01 [000178] --CXG------- * CALL ind unman popargs void [000152] ------------ arg0 +--* LCL_VAR int V18 loc1 [000153] ------------ arg1 +--* LCL_VAR int V19 loc2 [000154] ------------ arg2 +--* LCL_VAR int V20 loc3 [000155] ------------ arg3 +--* LCL_VAR int V21 loc4 [000156] ------------ arg4 +--* LCL_VAR int V22 loc5 [000157] ------------ arg5 +--* LCL_VAR int V23 loc6 [000158] ------------ arg6 +--* LCL_VAR int V24 loc7 [000159] ------------ arg7 +--* LCL_VAR int V25 loc8 [000160] ------------ arg8 +--* LCL_VAR int V26 loc9 [000161] ------------ arg9 +--* LCL_VAR int V27 loc10 [000162] ------------ arg10 +--* LCL_VAR int V28 loc11 [000163] ------------ arg11 +--* LCL_VAR int V29 loc12 [000164] ------------ arg12 +--* LCL_VAR int V30 loc13 [000165] ------------ arg13 +--* LCL_VAR int V31 loc14 [000166] ------------ arg14 +--* LCL_VAR int V32 loc15 [000167] ------------ arg15 +--* LCL_VAR int V33 loc16 [000168] ------------ arg16 +--* LCL_VAR long V34 loc17 [000177] ------------ calli tgt \--* LCL_VAR long V37 tmp2 ***** BB01 [000179] ------------ * NO_OP void ***** BB01 [000180] ------------ * NO_OP void ***** BB01 [000181] ------------ * NO_OP void ***** BB01 [000182] ------------ * NO_OP void ***** BB01 [000183] ------------ * NO_OP void ***** BB01 [000184] ------------ * NO_OP void ***** BB01 [000185] ------------ * NO_OP void ***** BB01 [000186] ------------ * NO_OP void ***** BB01 [000187] ------------ * NO_OP void ***** BB01 [000188] ------------ * NO_OP void ***** BB01 [000189] ------------ * NO_OP void ***** BB01 [000190] ------------ * NO_OP void ***** BB01 [000191] ------------ * NO_OP void ***** BB01 [000192] ------------ * NO_OP void ***** BB01 [000193] ------------ * NO_OP void ***** BB01 [000194] ------------ * NO_OP void ***** BB01 [000195] ------------ * NO_OP void ***** BB01 [000196] ------------ * NO_OP void ***** BB01 [000197] ------------ * NO_OP void ***** BB01 [000198] ------------ * NO_OP void ***** BB01 [000199] ------------ * NO_OP void ***** BB01 [000200] ------------ * NO_OP void ***** BB01 [000201] ------------ * NO_OP void ***** BB01 [000202] ------------ * NO_OP void ***** BB01 [000203] ------------ * NO_OP void ***** BB01 [000204] ------------ * NO_OP void ***** BB01 [000205] ------------ * NO_OP void ***** BB01 [000206] ------------ * NO_OP void ***** BB01 [000207] ------------ * NO_OP void ***** BB01 [000208] ------------ * NO_OP void ***** BB01 [000209] ------------ * NO_OP void ***** BB01 [000210] ------------ * NO_OP void ***** BB01 [000211] ------------ * NO_OP void ***** BB01 [000212] ------------ * NO_OP void ***** BB01 [000213] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining *************** Finishing PHASE Morph - Inlining [no changes] *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks New Basic Block BB02 [0001] created. New scratch BB02 fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB01 New Basic Block BB03 [0002] created. newReturnBB [BB03] created mergeReturns statement tree [000214] added to genReturnBB BB03 [0002] [000214] ------------ * RETURN void lvaGrabTemp returning 38 (V38 tmp3) (a long lifetime temp) called for Pinvoke FrameListRoot. lvaGrabTemp returning 39 (V39 tmp4) (a long lifetime temp) called for Pinvoke FrameVar. Local V39 should not be enregistered because: it is address exposed *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [???..???) keep i internal label target BB01 [0000] 1 1 [000..112) (return) i BB03 [0002] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [???..???) keep i internal label target BB01 [0000] 1 1 [000..112) (return) i BB03 [0002] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB02 to BB01 Renumber BB01 to BB02 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 1 [000..112) (return) i BB03 [0002] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 4, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 1 [000..112) (return) i BB03 [0002] 1 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 BB01 1 [000..112) (return) i BB03 [0002] 0 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Morph - Promote Structs *************** In fgResetImplicitByRefRefCount() *************** In fgPromoteStructs() promotion opt flag not enabled *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V17 loc0 [000000] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000003] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000010] -A---------- * ASG int [000009] D------N---- +--* LCL_VAR int V18 loc1 [000008] ------------ \--* EQ int [000006] ------------ +--* EQ int [000004] ------------ | +--* LCL_VAR bool V00 arg0 [000005] ------------ | \--* CNS_INT int 0 [000007] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000011] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000012] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V19 loc2 [000017] ------------ \--* EQ int [000015] ------------ +--* EQ int [000013] ------------ | +--* LCL_VAR bool V01 arg1 [000014] ------------ | \--* CNS_INT int 0 [000016] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000020] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000021] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000028] -A---------- * ASG int [000027] D------N---- +--* LCL_VAR int V20 loc3 [000026] ------------ \--* EQ int [000024] ------------ +--* EQ int [000022] ------------ | +--* LCL_VAR bool V02 arg2 [000023] ------------ | \--* CNS_INT int 0 [000025] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000029] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000030] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000037] -A---------- * ASG int [000036] D------N---- +--* LCL_VAR int V21 loc4 [000035] ------------ \--* EQ int [000033] ------------ +--* EQ int [000031] ------------ | +--* LCL_VAR bool V03 arg3 [000032] ------------ | \--* CNS_INT int 0 [000034] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000038] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000039] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000046] -A---------- * ASG int [000045] D------N---- +--* LCL_VAR int V22 loc5 [000044] ------------ \--* EQ int [000042] ------------ +--* EQ int [000040] ------------ | +--* LCL_VAR bool V04 arg4 [000041] ------------ | \--* CNS_INT int 0 [000043] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000047] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000048] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V23 loc6 [000053] ------------ \--* EQ int [000051] ------------ +--* EQ int [000049] ------------ | +--* LCL_VAR bool V05 arg5 [000050] ------------ | \--* CNS_INT int 0 [000052] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000056] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000057] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000064] -A---------- * ASG int [000063] D------N---- +--* LCL_VAR int V24 loc7 [000062] ------------ \--* EQ int [000060] ------------ +--* EQ int [000058] ------------ | +--* LCL_VAR bool V06 arg6 [000059] ------------ | \--* CNS_INT int 0 [000061] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000065] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000066] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000073] -A---------- * ASG int [000072] D------N---- +--* LCL_VAR int V25 loc8 [000071] ------------ \--* EQ int [000069] ------------ +--* EQ int [000067] ------------ | +--* LCL_VAR bool V07 arg7 [000068] ------------ | \--* CNS_INT int 0 [000070] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000074] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000075] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000082] -A---------- * ASG int [000081] D------N---- +--* LCL_VAR int V26 loc9 [000080] ------------ \--* EQ int [000078] ------------ +--* EQ int [000076] ------------ | +--* LCL_VAR bool V08 arg8 [000077] ------------ | \--* CNS_INT int 0 [000079] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000083] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000084] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000091] -A---------- * ASG int [000090] D------N---- +--* LCL_VAR int V27 loc10 [000089] ------------ \--* EQ int [000087] ------------ +--* EQ int [000085] ------------ | +--* LCL_VAR bool V09 arg9 [000086] ------------ | \--* CNS_INT int 0 [000088] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000092] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000093] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000100] -A---------- * ASG int [000099] D------N---- +--* LCL_VAR int V28 loc11 [000098] ------------ \--* EQ int [000096] ------------ +--* EQ int [000094] ------------ | +--* LCL_VAR bool V10 arg10 [000095] ------------ | \--* CNS_INT int 0 [000097] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000101] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000102] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000109] -A---------- * ASG int [000108] D------N---- +--* LCL_VAR int V29 loc12 [000107] ------------ \--* EQ int [000105] ------------ +--* EQ int [000103] ------------ | +--* LCL_VAR bool V11 arg11 [000104] ------------ | \--* CNS_INT int 0 [000106] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000110] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000111] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000118] -A---------- * ASG int [000117] D------N---- +--* LCL_VAR int V30 loc13 [000116] ------------ \--* EQ int [000114] ------------ +--* EQ int [000112] ------------ | +--* LCL_VAR bool V12 arg12 [000113] ------------ | \--* CNS_INT int 0 [000115] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000119] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000120] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V31 loc14 [000125] ------------ \--* EQ int [000123] ------------ +--* EQ int [000121] ------------ | +--* LCL_VAR bool V13 arg13 [000122] ------------ | \--* CNS_INT int 0 [000124] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000128] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000129] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000136] -A---------- * ASG int [000135] D------N---- +--* LCL_VAR int V32 loc15 [000134] ------------ \--* EQ int [000132] ------------ +--* EQ int [000130] ------------ | +--* LCL_VAR bool V14 arg14 [000131] ------------ | \--* CNS_INT int 0 [000133] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000137] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000138] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000145] -A---------- * ASG int [000144] D------N---- +--* LCL_VAR int V33 loc16 [000143] ------------ \--* EQ int [000141] ------------ +--* EQ int [000139] ------------ | +--* LCL_VAR bool V15 arg15 [000140] ------------ | \--* CNS_INT int 0 [000142] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: [000146] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000147] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000150] -A---------- * ASG long [000149] D------N---- +--* LCL_VAR long V34 loc17 [000148] ------------ \--* LCL_VAR long V16 arg16 LocalAddressVisitor visiting statement: [000151] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000176] -A-XG------- * ASG long [000175] D------N---- +--* LCL_VAR long V37 tmp2 [000174] *--XG------- \--* IND long [000173] *--XG------- \--* IND long [000172] ------------ \--* ADD long [000169] ------------ +--* LCL_VAR long (AX) V36 tmp1 [000171] ------------ \--* CAST long <- int [000170] ------------ \--* CNS_INT int 72 LocalAddressVisitor visiting statement: [000178] --CXG------- * CALL ind unman popargs void [000152] ------------ arg0 +--* LCL_VAR int V18 loc1 [000153] ------------ arg1 +--* LCL_VAR int V19 loc2 [000154] ------------ arg2 +--* LCL_VAR int V20 loc3 [000155] ------------ arg3 +--* LCL_VAR int V21 loc4 [000156] ------------ arg4 +--* LCL_VAR int V22 loc5 [000157] ------------ arg5 +--* LCL_VAR int V23 loc6 [000158] ------------ arg6 +--* LCL_VAR int V24 loc7 [000159] ------------ arg7 +--* LCL_VAR int V25 loc8 [000160] ------------ arg8 +--* LCL_VAR int V26 loc9 [000161] ------------ arg9 +--* LCL_VAR int V27 loc10 [000162] ------------ arg10 +--* LCL_VAR int V28 loc11 [000163] ------------ arg11 +--* LCL_VAR int V29 loc12 [000164] ------------ arg12 +--* LCL_VAR int V30 loc13 [000165] ------------ arg13 +--* LCL_VAR int V31 loc14 [000166] ------------ arg14 +--* LCL_VAR int V32 loc15 [000167] ------------ arg15 +--* LCL_VAR int V33 loc16 [000168] ------------ arg16 +--* LCL_VAR long V34 loc17 [000177] ------------ calli tgt \--* LCL_VAR long V37 tmp2 LocalAddressVisitor visiting statement: [000179] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000180] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000181] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000182] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000183] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000184] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000185] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000186] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000187] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000188] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000189] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000190] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000191] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000192] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000193] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000194] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000195] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000196] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000197] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000198] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000199] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000200] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000201] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000202] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000203] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000204] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000205] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000206] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000207] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000208] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000209] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000210] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000211] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000212] ------------ * NO_OP void LocalAddressVisitor visiting statement: [000213] ------------ * RETURN void LocalAddressVisitor visiting statement: [000214] ------------ * RETURN void *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** In fgRetypeImplicitByRefArgs() *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long)' Morphing BB02 of 'ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long)' fgMorphTree BB02, STMT00000 (before) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V17 loc0 [000000] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00001 (before) [000003] ------------ * NO_OP void fgMorphTree BB02, STMT00002 (before) [000010] -A---------- * ASG int [000009] D------N---- +--* LCL_VAR int V18 loc1 [000008] ------------ \--* EQ int [000006] ------------ +--* EQ int [000004] ------------ | +--* LCL_VAR bool V00 arg0 [000005] ------------ | \--* CNS_INT int 0 [000007] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00002 (after) [000010] -A---+------ * ASG int [000009] D----+-N---- +--* LCL_VAR int V18 loc1 [000006] -----+------ \--* NE int [000215] -----+------ +--* CAST int <- bool <- int [000004] -----+------ | \--* LCL_VAR int V00 arg0 [000005] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00003 (before) [000011] ------------ * NO_OP void fgMorphTree BB02, STMT00004 (before) [000012] ------------ * NO_OP void fgMorphTree BB02, STMT00005 (before) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V19 loc2 [000017] ------------ \--* EQ int [000015] ------------ +--* EQ int [000013] ------------ | +--* LCL_VAR bool V01 arg1 [000014] ------------ | \--* CNS_INT int 0 [000016] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00005 (after) [000019] -A---+------ * ASG int [000018] D----+-N---- +--* LCL_VAR int V19 loc2 [000015] -----+------ \--* NE int [000216] -----+------ +--* CAST int <- bool <- int [000013] -----+------ | \--* LCL_VAR int V01 arg1 [000014] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00006 (before) [000020] ------------ * NO_OP void fgMorphTree BB02, STMT00007 (before) [000021] ------------ * NO_OP void fgMorphTree BB02, STMT00008 (before) [000028] -A---------- * ASG int [000027] D------N---- +--* LCL_VAR int V20 loc3 [000026] ------------ \--* EQ int [000024] ------------ +--* EQ int [000022] ------------ | +--* LCL_VAR bool V02 arg2 [000023] ------------ | \--* CNS_INT int 0 [000025] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00008 (after) [000028] -A---+------ * ASG int [000027] D----+-N---- +--* LCL_VAR int V20 loc3 [000024] -----+------ \--* NE int [000217] -----+------ +--* CAST int <- bool <- int [000022] -----+------ | \--* LCL_VAR int V02 arg2 [000023] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00009 (before) [000029] ------------ * NO_OP void fgMorphTree BB02, STMT00010 (before) [000030] ------------ * NO_OP void fgMorphTree BB02, STMT00011 (before) [000037] -A---------- * ASG int [000036] D------N---- +--* LCL_VAR int V21 loc4 [000035] ------------ \--* EQ int [000033] ------------ +--* EQ int [000031] ------------ | +--* LCL_VAR bool V03 arg3 [000032] ------------ | \--* CNS_INT int 0 [000034] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00011 (after) [000037] -A---+------ * ASG int [000036] D----+-N---- +--* LCL_VAR int V21 loc4 [000033] -----+------ \--* NE int [000218] -----+------ +--* CAST int <- bool <- int [000031] -----+------ | \--* LCL_VAR int V03 arg3 [000032] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00012 (before) [000038] ------------ * NO_OP void fgMorphTree BB02, STMT00013 (before) [000039] ------------ * NO_OP void fgMorphTree BB02, STMT00014 (before) [000046] -A---------- * ASG int [000045] D------N---- +--* LCL_VAR int V22 loc5 [000044] ------------ \--* EQ int [000042] ------------ +--* EQ int [000040] ------------ | +--* LCL_VAR bool V04 arg4 [000041] ------------ | \--* CNS_INT int 0 [000043] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00014 (after) [000046] -A---+------ * ASG int [000045] D----+-N---- +--* LCL_VAR int V22 loc5 [000042] -----+------ \--* NE int [000219] -----+------ +--* CAST int <- bool <- int [000040] -----+------ | \--* LCL_VAR int V04 arg4 [000041] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00015 (before) [000047] ------------ * NO_OP void fgMorphTree BB02, STMT00016 (before) [000048] ------------ * NO_OP void fgMorphTree BB02, STMT00017 (before) [000055] -A---------- * ASG int [000054] D------N---- +--* LCL_VAR int V23 loc6 [000053] ------------ \--* EQ int [000051] ------------ +--* EQ int [000049] ------------ | +--* LCL_VAR bool V05 arg5 [000050] ------------ | \--* CNS_INT int 0 [000052] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00017 (after) [000055] -A---+------ * ASG int [000054] D----+-N---- +--* LCL_VAR int V23 loc6 [000051] -----+------ \--* NE int [000220] -----+------ +--* CAST int <- bool <- int [000049] -----+------ | \--* LCL_VAR int V05 arg5 [000050] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00018 (before) [000056] ------------ * NO_OP void fgMorphTree BB02, STMT00019 (before) [000057] ------------ * NO_OP void fgMorphTree BB02, STMT00020 (before) [000064] -A---------- * ASG int [000063] D------N---- +--* LCL_VAR int V24 loc7 [000062] ------------ \--* EQ int [000060] ------------ +--* EQ int [000058] ------------ | +--* LCL_VAR bool V06 arg6 [000059] ------------ | \--* CNS_INT int 0 [000061] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00020 (after) [000064] -A---+------ * ASG int [000063] D----+-N---- +--* LCL_VAR int V24 loc7 [000060] -----+------ \--* NE int [000221] -----+------ +--* CAST int <- bool <- int [000058] -----+------ | \--* LCL_VAR int V06 arg6 [000059] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00021 (before) [000065] ------------ * NO_OP void fgMorphTree BB02, STMT00022 (before) [000066] ------------ * NO_OP void fgMorphTree BB02, STMT00023 (before) [000073] -A---------- * ASG int [000072] D------N---- +--* LCL_VAR int V25 loc8 [000071] ------------ \--* EQ int [000069] ------------ +--* EQ int [000067] ------------ | +--* LCL_VAR bool V07 arg7 [000068] ------------ | \--* CNS_INT int 0 [000070] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00023 (after) [000073] -A---+------ * ASG int [000072] D----+-N---- +--* LCL_VAR int V25 loc8 [000069] -----+------ \--* NE int [000222] -----+------ +--* CAST int <- bool <- int [000067] -----+------ | \--* LCL_VAR int V07 arg7 [000068] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00024 (before) [000074] ------------ * NO_OP void fgMorphTree BB02, STMT00025 (before) [000075] ------------ * NO_OP void fgMorphTree BB02, STMT00026 (before) [000082] -A---------- * ASG int [000081] D------N---- +--* LCL_VAR int V26 loc9 [000080] ------------ \--* EQ int [000078] ------------ +--* EQ int [000076] ------------ | +--* LCL_VAR bool V08 arg8 [000077] ------------ | \--* CNS_INT int 0 [000079] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00026 (after) [000082] -A---+------ * ASG int [000081] D----+-N---- +--* LCL_VAR int V26 loc9 [000078] -----+------ \--* NE int [000223] -----+------ +--* CAST int <- bool <- int [000076] -----+------ | \--* LCL_VAR int V08 arg8 [000077] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00027 (before) [000083] ------------ * NO_OP void fgMorphTree BB02, STMT00028 (before) [000084] ------------ * NO_OP void fgMorphTree BB02, STMT00029 (before) [000091] -A---------- * ASG int [000090] D------N---- +--* LCL_VAR int V27 loc10 [000089] ------------ \--* EQ int [000087] ------------ +--* EQ int [000085] ------------ | +--* LCL_VAR bool V09 arg9 [000086] ------------ | \--* CNS_INT int 0 [000088] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00029 (after) [000091] -A---+------ * ASG int [000090] D----+-N---- +--* LCL_VAR int V27 loc10 [000087] -----+------ \--* NE int [000224] -----+------ +--* CAST int <- bool <- int [000085] -----+------ | \--* LCL_VAR int V09 arg9 [000086] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00030 (before) [000092] ------------ * NO_OP void fgMorphTree BB02, STMT00031 (before) [000093] ------------ * NO_OP void fgMorphTree BB02, STMT00032 (before) [000100] -A---------- * ASG int [000099] D------N---- +--* LCL_VAR int V28 loc11 [000098] ------------ \--* EQ int [000096] ------------ +--* EQ int [000094] ------------ | +--* LCL_VAR bool V10 arg10 [000095] ------------ | \--* CNS_INT int 0 [000097] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00032 (after) [000100] -A---+------ * ASG int [000099] D----+-N---- +--* LCL_VAR int V28 loc11 [000096] -----+------ \--* NE int [000225] -----+------ +--* CAST int <- bool <- int [000094] -----+------ | \--* LCL_VAR int V10 arg10 [000095] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00033 (before) [000101] ------------ * NO_OP void fgMorphTree BB02, STMT00034 (before) [000102] ------------ * NO_OP void fgMorphTree BB02, STMT00035 (before) [000109] -A---------- * ASG int [000108] D------N---- +--* LCL_VAR int V29 loc12 [000107] ------------ \--* EQ int [000105] ------------ +--* EQ int [000103] ------------ | +--* LCL_VAR bool V11 arg11 [000104] ------------ | \--* CNS_INT int 0 [000106] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00035 (after) [000109] -A---+------ * ASG int [000108] D----+-N---- +--* LCL_VAR int V29 loc12 [000105] -----+------ \--* NE int [000226] -----+------ +--* CAST int <- bool <- int [000103] -----+------ | \--* LCL_VAR int V11 arg11 [000104] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00036 (before) [000110] ------------ * NO_OP void fgMorphTree BB02, STMT00037 (before) [000111] ------------ * NO_OP void fgMorphTree BB02, STMT00038 (before) [000118] -A---------- * ASG int [000117] D------N---- +--* LCL_VAR int V30 loc13 [000116] ------------ \--* EQ int [000114] ------------ +--* EQ int [000112] ------------ | +--* LCL_VAR bool V12 arg12 [000113] ------------ | \--* CNS_INT int 0 [000115] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00038 (after) [000118] -A---+------ * ASG int [000117] D----+-N---- +--* LCL_VAR int V30 loc13 [000114] -----+------ \--* NE int [000227] -----+------ +--* CAST int <- bool <- int [000112] -----+------ | \--* LCL_VAR int V12 arg12 [000113] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00039 (before) [000119] ------------ * NO_OP void fgMorphTree BB02, STMT00040 (before) [000120] ------------ * NO_OP void fgMorphTree BB02, STMT00041 (before) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V31 loc14 [000125] ------------ \--* EQ int [000123] ------------ +--* EQ int [000121] ------------ | +--* LCL_VAR bool V13 arg13 [000122] ------------ | \--* CNS_INT int 0 [000124] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00041 (after) [000127] -A---+------ * ASG int [000126] D----+-N---- +--* LCL_VAR int V31 loc14 [000123] -----+------ \--* NE int [000228] -----+------ +--* CAST int <- bool <- int [000121] -----+------ | \--* LCL_VAR int V13 arg13 [000122] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00042 (before) [000128] ------------ * NO_OP void fgMorphTree BB02, STMT00043 (before) [000129] ------------ * NO_OP void fgMorphTree BB02, STMT00044 (before) [000136] -A---------- * ASG int [000135] D------N---- +--* LCL_VAR int V32 loc15 [000134] ------------ \--* EQ int [000132] ------------ +--* EQ int [000130] ------------ | +--* LCL_VAR bool V14 arg14 [000131] ------------ | \--* CNS_INT int 0 [000133] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00044 (after) [000136] -A---+------ * ASG int [000135] D----+-N---- +--* LCL_VAR int V32 loc15 [000132] -----+------ \--* NE int [000229] -----+------ +--* CAST int <- bool <- int [000130] -----+------ | \--* LCL_VAR int V14 arg14 [000131] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00045 (before) [000137] ------------ * NO_OP void fgMorphTree BB02, STMT00046 (before) [000138] ------------ * NO_OP void fgMorphTree BB02, STMT00047 (before) [000145] -A---------- * ASG int [000144] D------N---- +--* LCL_VAR int V33 loc16 [000143] ------------ \--* EQ int [000141] ------------ +--* EQ int [000139] ------------ | +--* LCL_VAR bool V15 arg15 [000140] ------------ | \--* CNS_INT int 0 [000142] ------------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00047 (after) [000145] -A---+------ * ASG int [000144] D----+-N---- +--* LCL_VAR int V33 loc16 [000141] -----+------ \--* NE int [000230] -----+------ +--* CAST int <- bool <- int [000139] -----+------ | \--* LCL_VAR int V15 arg15 [000140] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00048 (before) [000146] ------------ * NO_OP void fgMorphTree BB02, STMT00049 (before) [000147] ------------ * NO_OP void fgMorphTree BB02, STMT00050 (before) [000150] -A---------- * ASG long [000149] D------N---- +--* LCL_VAR long V34 loc17 [000148] ------------ \--* LCL_VAR long V16 arg16 fgMorphTree BB02, STMT00051 (before) [000151] ------------ * NO_OP void fgMorphTree BB02, STMT00052 (before) [000176] -A-XG------- * ASG long [000175] D------N---- +--* LCL_VAR long V37 tmp2 [000174] *--XG------- \--* IND long [000173] *--XG------- \--* IND long [000172] ------------ \--* ADD long [000169] ------------ +--* LCL_VAR long (AX) V36 tmp1 [000171] ------------ \--* CAST long <- int [000170] ------------ \--* CNS_INT int 72 fgMorphTree BB02, STMT00053 (before) [000178] --CXG------- * CALL ind unman popargs void [000152] ------------ arg0 +--* LCL_VAR int V18 loc1 [000153] ------------ arg1 +--* LCL_VAR int V19 loc2 [000154] ------------ arg2 +--* LCL_VAR int V20 loc3 [000155] ------------ arg3 +--* LCL_VAR int V21 loc4 [000156] ------------ arg4 +--* LCL_VAR int V22 loc5 [000157] ------------ arg5 +--* LCL_VAR int V23 loc6 [000158] ------------ arg6 +--* LCL_VAR int V24 loc7 [000159] ------------ arg7 +--* LCL_VAR int V25 loc8 [000160] ------------ arg8 +--* LCL_VAR int V26 loc9 [000161] ------------ arg9 +--* LCL_VAR int V27 loc10 [000162] ------------ arg10 +--* LCL_VAR int V28 loc11 [000163] ------------ arg11 +--* LCL_VAR int V29 loc12 [000164] ------------ arg12 +--* LCL_VAR int V30 loc13 [000165] ------------ arg13 +--* LCL_VAR int V31 loc14 [000166] ------------ arg14 +--* LCL_VAR int V32 loc15 [000167] ------------ arg15 +--* LCL_VAR int V33 loc16 [000168] ------------ arg16 +--* LCL_VAR long V34 loc17 [000177] ------------ calli tgt \--* LCL_VAR long V37 tmp2 Initializing arg info for 178.CALL: ArgTable for 178.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 152.LCL_VAR int (By ref), 1 reg: x0, byteAlignment=4] fgArgTabEntry[arg 1 153.LCL_VAR int (By ref), 1 reg: x1, byteAlignment=4] fgArgTabEntry[arg 2 154.LCL_VAR int (By ref), 1 reg: x2, byteAlignment=4] fgArgTabEntry[arg 3 155.LCL_VAR int (By ref), 1 reg: x3, byteAlignment=4] fgArgTabEntry[arg 4 156.LCL_VAR int (By ref), 1 reg: x4, byteAlignment=4] fgArgTabEntry[arg 5 157.LCL_VAR int (By ref), 1 reg: x5, byteAlignment=4] fgArgTabEntry[arg 6 158.LCL_VAR int (By ref), 1 reg: x6, byteAlignment=4] fgArgTabEntry[arg 7 159.LCL_VAR int (By ref), 1 reg: x7, byteAlignment=4] fgArgTabEntry[arg 8 160.LCL_VAR int (By ref), byteSize=4, byteOffset=0, byteAlignment=4] fgArgTabEntry[arg 9 161.LCL_VAR int (By ref), byteSize=4, byteOffset=4, byteAlignment=4] fgArgTabEntry[arg 10 162.LCL_VAR int (By ref), byteSize=4, byteOffset=8, byteAlignment=4] fgArgTabEntry[arg 11 163.LCL_VAR int (By ref), byteSize=4, byteOffset=12, byteAlignment=4] fgArgTabEntry[arg 12 164.LCL_VAR int (By ref), byteSize=4, byteOffset=16, byteAlignment=4] fgArgTabEntry[arg 13 165.LCL_VAR int (By ref), byteSize=4, byteOffset=20, byteAlignment=4] fgArgTabEntry[arg 14 166.LCL_VAR int (By ref), byteSize=4, byteOffset=24, byteAlignment=4] fgArgTabEntry[arg 15 167.LCL_VAR int (By ref), byteSize=4, byteOffset=28, byteAlignment=4] fgArgTabEntry[arg 16 168.LCL_VAR long (By ref), byteSize=8, byteOffset=32, byteAlignment=8] Morphing args for 178.CALL: nextSlotByteOffset=40, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('x0'): [000152] -----+------ * LCL_VAR int V18 loc1 Replaced with placeholder node: [000231] ----------L- * ARGPLACE int Deferred argument ('x1'): [000153] -----+------ * LCL_VAR int V19 loc2 Replaced with placeholder node: [000232] ----------L- * ARGPLACE int Deferred argument ('x2'): [000154] -----+------ * LCL_VAR int V20 loc3 Replaced with placeholder node: [000233] ----------L- * ARGPLACE int Deferred argument ('x3'): [000155] -----+------ * LCL_VAR int V21 loc4 Replaced with placeholder node: [000234] ----------L- * ARGPLACE int Deferred argument ('x4'): [000156] -----+------ * LCL_VAR int V22 loc5 Replaced with placeholder node: [000235] ----------L- * ARGPLACE int Deferred argument ('x5'): [000157] -----+------ * LCL_VAR int V23 loc6 Replaced with placeholder node: [000236] ----------L- * ARGPLACE int Deferred argument ('x6'): [000158] -----+------ * LCL_VAR int V24 loc7 Replaced with placeholder node: [000237] ----------L- * ARGPLACE int Deferred argument ('x7'): [000159] -----+------ * LCL_VAR int V25 loc8 Replaced with placeholder node: [000238] ----------L- * ARGPLACE int Shuffled argument table: x0 x1 x2 x3 x4 x5 x6 x7 ArgTable for 178.CALL after fgMorphArgs: fgArgTabEntry[arg 0 152.LCL_VAR int (By ref), 1 reg: x0, byteAlignment=4, lateArgInx=0, processed] fgArgTabEntry[arg 1 153.LCL_VAR int (By ref), 1 reg: x1, byteAlignment=4, lateArgInx=1, processed] fgArgTabEntry[arg 2 154.LCL_VAR int (By ref), 1 reg: x2, byteAlignment=4, lateArgInx=2, processed] fgArgTabEntry[arg 3 155.LCL_VAR int (By ref), 1 reg: x3, byteAlignment=4, lateArgInx=3, processed] fgArgTabEntry[arg 4 156.LCL_VAR int (By ref), 1 reg: x4, byteAlignment=4, lateArgInx=4, processed] fgArgTabEntry[arg 5 157.LCL_VAR int (By ref), 1 reg: x5, byteAlignment=4, lateArgInx=5, processed] fgArgTabEntry[arg 6 158.LCL_VAR int (By ref), 1 reg: x6, byteAlignment=4, lateArgInx=6, processed] fgArgTabEntry[arg 7 159.LCL_VAR int (By ref), 1 reg: x7, byteAlignment=4, lateArgInx=7, processed] fgArgTabEntry[arg 8 160.LCL_VAR int (By ref), byteSize=4, byteOffset=0, byteAlignment=4, processed] fgArgTabEntry[arg 9 161.LCL_VAR int (By ref), byteSize=4, byteOffset=4, byteAlignment=4, processed] fgArgTabEntry[arg 10 162.LCL_VAR int (By ref), byteSize=4, byteOffset=8, byteAlignment=4, processed] fgArgTabEntry[arg 11 163.LCL_VAR int (By ref), byteSize=4, byteOffset=12, byteAlignment=4, processed] fgArgTabEntry[arg 12 164.LCL_VAR int (By ref), byteSize=4, byteOffset=16, byteAlignment=4, processed] fgArgTabEntry[arg 13 165.LCL_VAR int (By ref), byteSize=4, byteOffset=20, byteAlignment=4, processed] fgArgTabEntry[arg 14 166.LCL_VAR int (By ref), byteSize=4, byteOffset=24, byteAlignment=4, processed] fgArgTabEntry[arg 15 167.LCL_VAR int (By ref), byteSize=4, byteOffset=28, byteAlignment=4, processed] fgArgTabEntry[arg 16 168.LCL_VAR long (By ref), byteSize=8, byteOffset=32, byteAlignment=8, processed] fgMorphTree BB02, STMT00053 (after) [000178] --CXG+------ * CALL ind unman popargs void [000160] -----+------ arg8 out+00 +--* LCL_VAR int V26 loc9 [000161] -----+------ arg9 out+04 +--* LCL_VAR int V27 loc10 [000162] -----+------ arg10 out+08 +--* LCL_VAR int V28 loc11 [000163] -----+------ arg11 out+0c +--* LCL_VAR int V29 loc12 [000164] -----+------ arg12 out+10 +--* LCL_VAR int V30 loc13 [000165] -----+------ arg13 out+14 +--* LCL_VAR int V31 loc14 [000166] -----+------ arg14 out+18 +--* LCL_VAR int V32 loc15 [000167] -----+------ arg15 out+1c +--* LCL_VAR int V33 loc16 [000168] -----+------ arg16 out+20 +--* LCL_VAR long V34 loc17 [000177] -----+------ calli tgt \--* LCL_VAR long V37 tmp2 [000152] -----+------ arg0 in x0 +--* LCL_VAR int V18 loc1 [000153] -----+------ arg1 in x1 +--* LCL_VAR int V19 loc2 [000154] -----+------ arg2 in x2 +--* LCL_VAR int V20 loc3 [000155] -----+------ arg3 in x3 +--* LCL_VAR int V21 loc4 [000156] -----+------ arg4 in x4 +--* LCL_VAR int V22 loc5 [000157] -----+------ arg5 in x5 +--* LCL_VAR int V23 loc6 [000158] -----+------ arg6 in x6 +--* LCL_VAR int V24 loc7 [000159] -----+------ arg7 in x7 \--* LCL_VAR int V25 loc8 fgMorphTree BB02, STMT00054 (before) [000179] ------------ * NO_OP void fgMorphTree BB02, STMT00055 (before) [000180] ------------ * NO_OP void fgMorphTree BB02, STMT00056 (before) [000181] ------------ * NO_OP void fgMorphTree BB02, STMT00057 (before) [000182] ------------ * NO_OP void fgMorphTree BB02, STMT00058 (before) [000183] ------------ * NO_OP void fgMorphTree BB02, STMT00059 (before) [000184] ------------ * NO_OP void fgMorphTree BB02, STMT00060 (before) [000185] ------------ * NO_OP void fgMorphTree BB02, STMT00061 (before) [000186] ------------ * NO_OP void fgMorphTree BB02, STMT00062 (before) [000187] ------------ * NO_OP void fgMorphTree BB02, STMT00063 (before) [000188] ------------ * NO_OP void fgMorphTree BB02, STMT00064 (before) [000189] ------------ * NO_OP void fgMorphTree BB02, STMT00065 (before) [000190] ------------ * NO_OP void fgMorphTree BB02, STMT00066 (before) [000191] ------------ * NO_OP void fgMorphTree BB02, STMT00067 (before) [000192] ------------ * NO_OP void fgMorphTree BB02, STMT00068 (before) [000193] ------------ * NO_OP void fgMorphTree BB02, STMT00069 (before) [000194] ------------ * NO_OP void fgMorphTree BB02, STMT00070 (before) [000195] ------------ * NO_OP void fgMorphTree BB02, STMT00071 (before) [000196] ------------ * NO_OP void fgMorphTree BB02, STMT00072 (before) [000197] ------------ * NO_OP void fgMorphTree BB02, STMT00073 (before) [000198] ------------ * NO_OP void fgMorphTree BB02, STMT00074 (before) [000199] ------------ * NO_OP void fgMorphTree BB02, STMT00075 (before) [000200] ------------ * NO_OP void fgMorphTree BB02, STMT00076 (before) [000201] ------------ * NO_OP void fgMorphTree BB02, STMT00077 (before) [000202] ------------ * NO_OP void fgMorphTree BB02, STMT00078 (before) [000203] ------------ * NO_OP void fgMorphTree BB02, STMT00079 (before) [000204] ------------ * NO_OP void fgMorphTree BB02, STMT00080 (before) [000205] ------------ * NO_OP void fgMorphTree BB02, STMT00081 (before) [000206] ------------ * NO_OP void fgMorphTree BB02, STMT00082 (before) [000207] ------------ * NO_OP void fgMorphTree BB02, STMT00083 (before) [000208] ------------ * NO_OP void fgMorphTree BB02, STMT00084 (before) [000209] ------------ * NO_OP void fgMorphTree BB02, STMT00085 (before) [000210] ------------ * NO_OP void fgMorphTree BB02, STMT00086 (before) [000211] ------------ * NO_OP void fgMorphTree BB02, STMT00087 (before) [000212] ------------ * NO_OP void fgMorphTree BB02, STMT00088 (before) [000213] ------------ * RETURN void Removing statement [000213] -----+------ * RETURN void in BB02 as useless: morph BB02 to point at onereturn. New block is BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe Morphing BB03 of 'ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long)' fgMorphTree BB03, STMT00089 (before) [000214] ------------ * RETURN void *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} ***** BB02 [000002] -A---+------ * ASG int [000001] D----+-N---- +--* LCL_VAR int V17 loc0 [000000] -----+------ \--* CNS_INT int 0 ***** BB02 [000003] -----+------ * NO_OP void ***** BB02 [000010] -A---+------ * ASG int [000009] D----+-N---- +--* LCL_VAR int V18 loc1 [000006] -----+------ \--* NE int [000215] -----+------ +--* CAST int <- bool <- int [000004] -----+------ | \--* LCL_VAR int V00 arg0 [000005] -----+------ \--* CNS_INT int 0 ***** BB02 [000011] -----+------ * NO_OP void ***** BB02 [000012] -----+------ * NO_OP void ***** BB02 [000019] -A---+------ * ASG int [000018] D----+-N---- +--* LCL_VAR int V19 loc2 [000015] -----+------ \--* NE int [000216] -----+------ +--* CAST int <- bool <- int [000013] -----+------ | \--* LCL_VAR int V01 arg1 [000014] -----+------ \--* CNS_INT int 0 ***** BB02 [000020] -----+------ * NO_OP void ***** BB02 [000021] -----+------ * NO_OP void ***** BB02 [000028] -A---+------ * ASG int [000027] D----+-N---- +--* LCL_VAR int V20 loc3 [000024] -----+------ \--* NE int [000217] -----+------ +--* CAST int <- bool <- int [000022] -----+------ | \--* LCL_VAR int V02 arg2 [000023] -----+------ \--* CNS_INT int 0 ***** BB02 [000029] -----+------ * NO_OP void ***** BB02 [000030] -----+------ * NO_OP void ***** BB02 [000037] -A---+------ * ASG int [000036] D----+-N---- +--* LCL_VAR int V21 loc4 [000033] -----+------ \--* NE int [000218] -----+------ +--* CAST int <- bool <- int [000031] -----+------ | \--* LCL_VAR int V03 arg3 [000032] -----+------ \--* CNS_INT int 0 ***** BB02 [000038] -----+------ * NO_OP void ***** BB02 [000039] -----+------ * NO_OP void ***** BB02 [000046] -A---+------ * ASG int [000045] D----+-N---- +--* LCL_VAR int V22 loc5 [000042] -----+------ \--* NE int [000219] -----+------ +--* CAST int <- bool <- int [000040] -----+------ | \--* LCL_VAR int V04 arg4 [000041] -----+------ \--* CNS_INT int 0 ***** BB02 [000047] -----+------ * NO_OP void ***** BB02 [000048] -----+------ * NO_OP void ***** BB02 [000055] -A---+------ * ASG int [000054] D----+-N---- +--* LCL_VAR int V23 loc6 [000051] -----+------ \--* NE int [000220] -----+------ +--* CAST int <- bool <- int [000049] -----+------ | \--* LCL_VAR int V05 arg5 [000050] -----+------ \--* CNS_INT int 0 ***** BB02 [000056] -----+------ * NO_OP void ***** BB02 [000057] -----+------ * NO_OP void ***** BB02 [000064] -A---+------ * ASG int [000063] D----+-N---- +--* LCL_VAR int V24 loc7 [000060] -----+------ \--* NE int [000221] -----+------ +--* CAST int <- bool <- int [000058] -----+------ | \--* LCL_VAR int V06 arg6 [000059] -----+------ \--* CNS_INT int 0 ***** BB02 [000065] -----+------ * NO_OP void ***** BB02 [000066] -----+------ * NO_OP void ***** BB02 [000073] -A---+------ * ASG int [000072] D----+-N---- +--* LCL_VAR int V25 loc8 [000069] -----+------ \--* NE int [000222] -----+------ +--* CAST int <- bool <- int [000067] -----+------ | \--* LCL_VAR int V07 arg7 [000068] -----+------ \--* CNS_INT int 0 ***** BB02 [000074] -----+------ * NO_OP void ***** BB02 [000075] -----+------ * NO_OP void ***** BB02 [000082] -A---+------ * ASG int [000081] D----+-N---- +--* LCL_VAR int V26 loc9 [000078] -----+------ \--* NE int [000223] -----+------ +--* CAST int <- bool <- int [000076] -----+------ | \--* LCL_VAR int V08 arg8 [000077] -----+------ \--* CNS_INT int 0 ***** BB02 [000083] -----+------ * NO_OP void ***** BB02 [000084] -----+------ * NO_OP void ***** BB02 [000091] -A---+------ * ASG int [000090] D----+-N---- +--* LCL_VAR int V27 loc10 [000087] -----+------ \--* NE int [000224] -----+------ +--* CAST int <- bool <- int [000085] -----+------ | \--* LCL_VAR int V09 arg9 [000086] -----+------ \--* CNS_INT int 0 ***** BB02 [000092] -----+------ * NO_OP void ***** BB02 [000093] -----+------ * NO_OP void ***** BB02 [000100] -A---+------ * ASG int [000099] D----+-N---- +--* LCL_VAR int V28 loc11 [000096] -----+------ \--* NE int [000225] -----+------ +--* CAST int <- bool <- int [000094] -----+------ | \--* LCL_VAR int V10 arg10 [000095] -----+------ \--* CNS_INT int 0 ***** BB02 [000101] -----+------ * NO_OP void ***** BB02 [000102] -----+------ * NO_OP void ***** BB02 [000109] -A---+------ * ASG int [000108] D----+-N---- +--* LCL_VAR int V29 loc12 [000105] -----+------ \--* NE int [000226] -----+------ +--* CAST int <- bool <- int [000103] -----+------ | \--* LCL_VAR int V11 arg11 [000104] -----+------ \--* CNS_INT int 0 ***** BB02 [000110] -----+------ * NO_OP void ***** BB02 [000111] -----+------ * NO_OP void ***** BB02 [000118] -A---+------ * ASG int [000117] D----+-N---- +--* LCL_VAR int V30 loc13 [000114] -----+------ \--* NE int [000227] -----+------ +--* CAST int <- bool <- int [000112] -----+------ | \--* LCL_VAR int V12 arg12 [000113] -----+------ \--* CNS_INT int 0 ***** BB02 [000119] -----+------ * NO_OP void ***** BB02 [000120] -----+------ * NO_OP void ***** BB02 [000127] -A---+------ * ASG int [000126] D----+-N---- +--* LCL_VAR int V31 loc14 [000123] -----+------ \--* NE int [000228] -----+------ +--* CAST int <- bool <- int [000121] -----+------ | \--* LCL_VAR int V13 arg13 [000122] -----+------ \--* CNS_INT int 0 ***** BB02 [000128] -----+------ * NO_OP void ***** BB02 [000129] -----+------ * NO_OP void ***** BB02 [000136] -A---+------ * ASG int [000135] D----+-N---- +--* LCL_VAR int V32 loc15 [000132] -----+------ \--* NE int [000229] -----+------ +--* CAST int <- bool <- int [000130] -----+------ | \--* LCL_VAR int V14 arg14 [000131] -----+------ \--* CNS_INT int 0 ***** BB02 [000137] -----+------ * NO_OP void ***** BB02 [000138] -----+------ * NO_OP void ***** BB02 [000145] -A---+------ * ASG int [000144] D----+-N---- +--* LCL_VAR int V33 loc16 [000141] -----+------ \--* NE int [000230] -----+------ +--* CAST int <- bool <- int [000139] -----+------ | \--* LCL_VAR int V15 arg15 [000140] -----+------ \--* CNS_INT int 0 ***** BB02 [000146] -----+------ * NO_OP void ***** BB02 [000147] -----+------ * NO_OP void ***** BB02 [000150] -A---+------ * ASG long [000149] D----+-N---- +--* LCL_VAR long V34 loc17 [000148] -----+------ \--* LCL_VAR long V16 arg16 ***** BB02 [000151] -----+------ * NO_OP void ***** BB02 [000176] -A-XG+------ * ASG long [000175] D----+-N---- +--* LCL_VAR long V37 tmp2 [000174] *--XG+------ \--* IND long [000173] *--XG+------ \--* IND long [000172] ----G+------ \--* ADD long [000169] ----G+------ +--* LCL_VAR long (AX) V36 tmp1 [000171] -----+------ \--* CAST long <- int [000170] -----+------ \--* CNS_INT int 72 ***** BB02 [000178] --CXG+------ * CALL ind unman popargs void [000160] -----+------ arg8 out+00 +--* LCL_VAR int V26 loc9 [000161] -----+------ arg9 out+04 +--* LCL_VAR int V27 loc10 [000162] -----+------ arg10 out+08 +--* LCL_VAR int V28 loc11 [000163] -----+------ arg11 out+0c +--* LCL_VAR int V29 loc12 [000164] -----+------ arg12 out+10 +--* LCL_VAR int V30 loc13 [000165] -----+------ arg13 out+14 +--* LCL_VAR int V31 loc14 [000166] -----+------ arg14 out+18 +--* LCL_VAR int V32 loc15 [000167] -----+------ arg15 out+1c +--* LCL_VAR int V33 loc16 [000168] -----+------ arg16 out+20 +--* LCL_VAR long V34 loc17 [000177] -----+------ calli tgt \--* LCL_VAR long V37 tmp2 [000152] -----+------ arg0 in x0 +--* LCL_VAR int V18 loc1 [000153] -----+------ arg1 in x1 +--* LCL_VAR int V19 loc2 [000154] -----+------ arg2 in x2 +--* LCL_VAR int V20 loc3 [000155] -----+------ arg3 in x3 +--* LCL_VAR int V21 loc4 [000156] -----+------ arg4 in x4 +--* LCL_VAR int V22 loc5 [000157] -----+------ arg5 in x5 +--* LCL_VAR int V23 loc6 [000158] -----+------ arg6 in x6 +--* LCL_VAR int V24 loc7 [000159] -----+------ arg7 in x7 \--* LCL_VAR int V25 loc8 ***** BB02 [000179] -----+------ * NO_OP void ***** BB02 [000180] -----+------ * NO_OP void ***** BB02 [000181] -----+------ * NO_OP void ***** BB02 [000182] -----+------ * NO_OP void ***** BB02 [000183] -----+------ * NO_OP void ***** BB02 [000184] -----+------ * NO_OP void ***** BB02 [000185] -----+------ * NO_OP void ***** BB02 [000186] -----+------ * NO_OP void ***** BB02 [000187] -----+------ * NO_OP void ***** BB02 [000188] -----+------ * NO_OP void ***** BB02 [000189] -----+------ * NO_OP void ***** BB02 [000190] -----+------ * NO_OP void ***** BB02 [000191] -----+------ * NO_OP void ***** BB02 [000192] -----+------ * NO_OP void ***** BB02 [000193] -----+------ * NO_OP void ***** BB02 [000194] -----+------ * NO_OP void ***** BB02 [000195] -----+------ * NO_OP void ***** BB02 [000196] -----+------ * NO_OP void ***** BB02 [000197] -----+------ * NO_OP void ***** BB02 [000198] -----+------ * NO_OP void ***** BB02 [000199] -----+------ * NO_OP void ***** BB02 [000200] -----+------ * NO_OP void ***** BB02 [000201] -----+------ * NO_OP void ***** BB02 [000202] -----+------ * NO_OP void ***** BB02 [000203] -----+------ * NO_OP void ***** BB02 [000204] -----+------ * NO_OP void ***** BB02 [000205] -----+------ * NO_OP void ***** BB02 [000206] -----+------ * NO_OP void ***** BB02 [000207] -----+------ * NO_OP void ***** BB02 [000208] -----+------ * NO_OP void ***** BB02 [000209] -----+------ * NO_OP void ***** BB02 [000210] -----+------ * NO_OP void ***** BB02 [000211] -----+------ * NO_OP void ***** BB02 [000212] -----+------ * NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} ***** BB03 [000214] -----+------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *************** Finishing PHASE Mark local vars *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 27 tree nodes *************** Finishing PHASE Set block order *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} ***** BB02 N003 ( 5, 5) [000002] -A------R--- * ASG int N002 ( 3, 2) [000001] D------N---- +--* LCL_VAR int V17 loc0 N001 ( 1, 2) [000000] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000003] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000010] -A------R--- * ASG int N005 ( 3, 2) [000009] D------N---- +--* LCL_VAR int V18 loc1 N004 ( 9, 7) [000006] ------------ \--* NE int N002 ( 4, 4) [000215] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000004] ------------ | \--* LCL_VAR int V00 arg0 N003 ( 1, 2) [000005] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000011] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000012] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000019] -A------R--- * ASG int N005 ( 3, 2) [000018] D------N---- +--* LCL_VAR int V19 loc2 N004 ( 9, 7) [000015] ------------ \--* NE int N002 ( 4, 4) [000216] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000013] ------------ | \--* LCL_VAR int V01 arg1 N003 ( 1, 2) [000014] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000020] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000021] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000028] -A------R--- * ASG int N005 ( 3, 2) [000027] D------N---- +--* LCL_VAR int V20 loc3 N004 ( 9, 7) [000024] ------------ \--* NE int N002 ( 4, 4) [000217] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000022] ------------ | \--* LCL_VAR int V02 arg2 N003 ( 1, 2) [000023] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000029] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000030] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000037] -A------R--- * ASG int N005 ( 3, 2) [000036] D------N---- +--* LCL_VAR int V21 loc4 N004 ( 9, 7) [000033] ------------ \--* NE int N002 ( 4, 4) [000218] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000031] ------------ | \--* LCL_VAR int V03 arg3 N003 ( 1, 2) [000032] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000038] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000039] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000046] -A------R--- * ASG int N005 ( 3, 2) [000045] D------N---- +--* LCL_VAR int V22 loc5 N004 ( 9, 7) [000042] ------------ \--* NE int N002 ( 4, 4) [000219] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000040] ------------ | \--* LCL_VAR int V04 arg4 N003 ( 1, 2) [000041] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000047] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000048] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000055] -A------R--- * ASG int N005 ( 3, 2) [000054] D------N---- +--* LCL_VAR int V23 loc6 N004 ( 9, 7) [000051] ------------ \--* NE int N002 ( 4, 4) [000220] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000049] ------------ | \--* LCL_VAR int V05 arg5 N003 ( 1, 2) [000050] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000056] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000057] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000064] -A------R--- * ASG int N005 ( 3, 2) [000063] D------N---- +--* LCL_VAR int V24 loc7 N004 ( 9, 7) [000060] ------------ \--* NE int N002 ( 4, 4) [000221] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000058] ------------ | \--* LCL_VAR int V06 arg6 N003 ( 1, 2) [000059] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000065] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000066] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000073] -A------R--- * ASG int N005 ( 3, 2) [000072] D------N---- +--* LCL_VAR int V25 loc8 N004 ( 9, 7) [000069] ------------ \--* NE int N002 ( 4, 4) [000222] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000067] ------------ | \--* LCL_VAR int V07 arg7 N003 ( 1, 2) [000068] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000074] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000075] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000082] -A------R--- * ASG int N005 ( 3, 2) [000081] D------N---- +--* LCL_VAR int V26 loc9 N004 ( 9, 7) [000078] ------------ \--* NE int N002 ( 4, 4) [000223] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000076] ------------ | \--* LCL_VAR int V08 arg8 N003 ( 1, 2) [000077] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000083] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000084] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000091] -A------R--- * ASG int N005 ( 3, 2) [000090] D------N---- +--* LCL_VAR int V27 loc10 N004 ( 9, 7) [000087] ------------ \--* NE int N002 ( 4, 4) [000224] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000085] ------------ | \--* LCL_VAR int V09 arg9 N003 ( 1, 2) [000086] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000092] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000093] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000100] -A------R--- * ASG int N005 ( 3, 2) [000099] D------N---- +--* LCL_VAR int V28 loc11 N004 ( 9, 7) [000096] ------------ \--* NE int N002 ( 4, 4) [000225] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000094] ------------ | \--* LCL_VAR int V10 arg10 N003 ( 1, 2) [000095] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000101] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000102] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000109] -A------R--- * ASG int N005 ( 3, 2) [000108] D------N---- +--* LCL_VAR int V29 loc12 N004 ( 9, 7) [000105] ------------ \--* NE int N002 ( 4, 4) [000226] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000103] ------------ | \--* LCL_VAR int V11 arg11 N003 ( 1, 2) [000104] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000110] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000111] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000118] -A------R--- * ASG int N005 ( 3, 2) [000117] D------N---- +--* LCL_VAR int V30 loc13 N004 ( 9, 7) [000114] ------------ \--* NE int N002 ( 4, 4) [000227] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000112] ------------ | \--* LCL_VAR int V12 arg12 N003 ( 1, 2) [000113] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000119] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000120] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000127] -A------R--- * ASG int N005 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V31 loc14 N004 ( 9, 7) [000123] ------------ \--* NE int N002 ( 4, 4) [000228] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000121] ------------ | \--* LCL_VAR int V13 arg13 N003 ( 1, 2) [000122] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000128] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000129] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000136] -A------R--- * ASG int N005 ( 3, 2) [000135] D------N---- +--* LCL_VAR int V32 loc15 N004 ( 9, 7) [000132] ------------ \--* NE int N002 ( 4, 4) [000229] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000130] ------------ | \--* LCL_VAR int V14 arg14 N003 ( 1, 2) [000131] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000137] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000138] ------------ * NO_OP void ***** BB02 N006 ( 13, 10) [000145] -A------R--- * ASG int N005 ( 3, 2) [000144] D------N---- +--* LCL_VAR int V33 loc16 N004 ( 9, 7) [000141] ------------ \--* NE int N002 ( 4, 4) [000230] ------------ +--* CAST int <- bool <- int N001 ( 3, 2) [000139] ------------ | \--* LCL_VAR int V15 arg15 N003 ( 1, 2) [000140] ------------ \--* CNS_INT int 0 ***** BB02 N001 ( 1, 1) [000146] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000147] ------------ * NO_OP void ***** BB02 N003 ( 7, 5) [000150] -A------R--- * ASG long N002 ( 3, 2) [000149] D------N---- +--* LCL_VAR long V34 loc17 N001 ( 3, 2) [000148] ------------ \--* LCL_VAR long V16 arg16 ***** BB02 N001 ( 1, 1) [000151] ------------ * NO_OP void ***** BB02 N008 ( 15, 13) [000176] -A-XG---R--- * ASG long N007 ( 3, 2) [000175] D------N---- +--* LCL_VAR long V37 tmp2 N006 ( 11, 10) [000174] *--XG------- \--* IND long N005 ( 8, 8) [000173] *--XG------- \--* IND long N004 ( 6, 7) [000172] ----G--N---- \--* ADD long N001 ( 3, 2) [000169] ----G------- +--* LCL_VAR long (AX) V36 tmp1 N003 ( 2, 4) [000171] ------------ \--* CAST long <- int N002 ( 1, 2) [000170] ------------ \--* CNS_INT int 72 ***** BB02 N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void N009 ( 3, 2) [000160] ------------ arg8 out+00 +--* LCL_VAR int V26 loc9 N010 ( 3, 2) [000161] ------------ arg9 out+04 +--* LCL_VAR int V27 loc10 N011 ( 3, 2) [000162] ------------ arg10 out+08 +--* LCL_VAR int V28 loc11 N012 ( 3, 2) [000163] ------------ arg11 out+0c +--* LCL_VAR int V29 loc12 N013 ( 3, 2) [000164] ------------ arg12 out+10 +--* LCL_VAR int V30 loc13 N014 ( 3, 2) [000165] ------------ arg13 out+14 +--* LCL_VAR int V31 loc14 N015 ( 3, 2) [000166] ------------ arg14 out+18 +--* LCL_VAR int V32 loc15 N016 ( 3, 2) [000167] ------------ arg15 out+1c +--* LCL_VAR int V33 loc16 N017 ( 3, 2) [000168] ------------ arg16 out+20 +--* LCL_VAR long V34 loc17 N026 ( 3, 2) [000177] ------------ calli tgt \--* LCL_VAR long V37 tmp2 N018 ( 3, 2) [000152] ------------ arg0 in x0 +--* LCL_VAR int V18 loc1 N019 ( 3, 2) [000153] ------------ arg1 in x1 +--* LCL_VAR int V19 loc2 N020 ( 3, 2) [000154] ------------ arg2 in x2 +--* LCL_VAR int V20 loc3 N021 ( 3, 2) [000155] ------------ arg3 in x3 +--* LCL_VAR int V21 loc4 N022 ( 3, 2) [000156] ------------ arg4 in x4 +--* LCL_VAR int V22 loc5 N023 ( 3, 2) [000157] ------------ arg5 in x5 +--* LCL_VAR int V23 loc6 N024 ( 3, 2) [000158] ------------ arg6 in x6 +--* LCL_VAR int V24 loc7 N025 ( 3, 2) [000159] ------------ arg7 in x7 \--* LCL_VAR int V25 loc8 ***** BB02 N001 ( 1, 1) [000179] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000180] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000181] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000182] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000183] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000184] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000185] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000186] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000187] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000188] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000189] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000190] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000191] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000192] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000193] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000194] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000195] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000196] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000197] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000198] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000199] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000200] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000201] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000202] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000203] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000204] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000205] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000206] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000207] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000208] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000209] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000210] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000211] ------------ * NO_OP void ***** BB02 N001 ( 1, 1) [000212] ------------ * NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} ***** BB03 N001 ( 0, 0) [000214] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} [000239] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 N001 ( 1, 1) [000003] ------------ NO_OP void N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] ------------ t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 N001 ( 1, 1) [000011] ------------ NO_OP void N001 ( 1, 1) [000012] ------------ NO_OP void N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] ------------ t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 N001 ( 1, 1) [000020] ------------ NO_OP void N001 ( 1, 1) [000021] ------------ NO_OP void N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] ------------ t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 N001 ( 1, 1) [000029] ------------ NO_OP void N001 ( 1, 1) [000030] ------------ NO_OP void N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] ------------ t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 N001 ( 1, 1) [000038] ------------ NO_OP void N001 ( 1, 1) [000039] ------------ NO_OP void N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] ------------ t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 N001 ( 1, 1) [000047] ------------ NO_OP void N001 ( 1, 1) [000048] ------------ NO_OP void N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] ------------ t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 N001 ( 1, 1) [000056] ------------ NO_OP void N001 ( 1, 1) [000057] ------------ NO_OP void N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] ------------ t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 N001 ( 1, 1) [000065] ------------ NO_OP void N001 ( 1, 1) [000066] ------------ NO_OP void N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] ------------ t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 N001 ( 1, 1) [000074] ------------ NO_OP void N001 ( 1, 1) [000075] ------------ NO_OP void N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] ------------ t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 N001 ( 1, 1) [000083] ------------ NO_OP void N001 ( 1, 1) [000084] ------------ NO_OP void N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] ------------ t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 N001 ( 1, 1) [000092] ------------ NO_OP void N001 ( 1, 1) [000093] ------------ NO_OP void N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] ------------ t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 N001 ( 1, 1) [000101] ------------ NO_OP void N001 ( 1, 1) [000102] ------------ NO_OP void N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] ------------ t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 N001 ( 1, 1) [000110] ------------ NO_OP void N001 ( 1, 1) [000111] ------------ NO_OP void N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] ------------ t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 N001 ( 1, 1) [000119] ------------ NO_OP void N001 ( 1, 1) [000120] ------------ NO_OP void N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] ------------ t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 N001 ( 1, 1) [000128] ------------ NO_OP void N001 ( 1, 1) [000129] ------------ NO_OP void N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] ------------ t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 N001 ( 1, 1) [000137] ------------ NO_OP void N001 ( 1, 1) [000138] ------------ NO_OP void N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] ------------ t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 N001 ( 1, 1) [000146] ------------ NO_OP void N001 ( 1, 1) [000147] ------------ NO_OP void N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 N001 ( 1, 1) [000151] ------------ NO_OP void N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] ----G--N---- t172 = * ADD long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 /--* t160 int arg8 out+00 +--* t161 int arg9 out+04 +--* t162 int arg10 out+08 +--* t163 int arg11 out+0c +--* t164 int arg12 out+10 +--* t165 int arg13 out+14 +--* t166 int arg14 out+18 +--* t167 int arg15 out+1c +--* t168 long arg16 out+20 +--* t152 int arg0 in x0 +--* t153 int arg1 in x1 +--* t154 int arg2 in x2 +--* t155 int arg3 in x3 +--* t156 int arg4 in x4 +--* t157 int arg5 in x5 +--* t158 int arg6 in x6 +--* t159 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void N001 ( 1, 1) [000179] ------------ NO_OP void N001 ( 1, 1) [000180] ------------ NO_OP void N001 ( 1, 1) [000181] ------------ NO_OP void N001 ( 1, 1) [000182] ------------ NO_OP void N001 ( 1, 1) [000183] ------------ NO_OP void N001 ( 1, 1) [000184] ------------ NO_OP void N001 ( 1, 1) [000185] ------------ NO_OP void N001 ( 1, 1) [000186] ------------ NO_OP void N001 ( 1, 1) [000187] ------------ NO_OP void N001 ( 1, 1) [000188] ------------ NO_OP void N001 ( 1, 1) [000189] ------------ NO_OP void N001 ( 1, 1) [000190] ------------ NO_OP void N001 ( 1, 1) [000191] ------------ NO_OP void N001 ( 1, 1) [000192] ------------ NO_OP void N001 ( 1, 1) [000193] ------------ NO_OP void N001 ( 1, 1) [000194] ------------ NO_OP void N001 ( 1, 1) [000195] ------------ NO_OP void N001 ( 1, 1) [000196] ------------ NO_OP void N001 ( 1, 1) [000197] ------------ NO_OP void N001 ( 1, 1) [000198] ------------ NO_OP void N001 ( 1, 1) [000199] ------------ NO_OP void N001 ( 1, 1) [000200] ------------ NO_OP void N001 ( 1, 1) [000201] ------------ NO_OP void N001 ( 1, 1) [000202] ------------ NO_OP void N001 ( 1, 1) [000203] ------------ NO_OP void N001 ( 1, 1) [000204] ------------ NO_OP void N001 ( 1, 1) [000205] ------------ NO_OP void N001 ( 1, 1) [000206] ------------ NO_OP void N001 ( 1, 1) [000207] ------------ NO_OP void N001 ( 1, 1) [000208] ------------ NO_OP void N001 ( 1, 1) [000209] ------------ NO_OP void N001 ( 1, 1) [000210] ------------ NO_OP void N001 ( 1, 1) [000211] ------------ NO_OP void N001 ( 1, 1) [000212] ------------ NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} N001 ( 0, 0) [000214] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering Bumping outgoingArgSpaceSize to 40 for call [000178] *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} [000239] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 N001 ( 1, 1) [000003] ------------ NO_OP void N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] ------------ t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 N001 ( 1, 1) [000011] ------------ NO_OP void N001 ( 1, 1) [000012] ------------ NO_OP void N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] ------------ t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 N001 ( 1, 1) [000020] ------------ NO_OP void N001 ( 1, 1) [000021] ------------ NO_OP void N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] ------------ t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 N001 ( 1, 1) [000029] ------------ NO_OP void N001 ( 1, 1) [000030] ------------ NO_OP void N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] ------------ t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 N001 ( 1, 1) [000038] ------------ NO_OP void N001 ( 1, 1) [000039] ------------ NO_OP void N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] ------------ t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 N001 ( 1, 1) [000047] ------------ NO_OP void N001 ( 1, 1) [000048] ------------ NO_OP void N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] ------------ t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 N001 ( 1, 1) [000056] ------------ NO_OP void N001 ( 1, 1) [000057] ------------ NO_OP void N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] ------------ t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 N001 ( 1, 1) [000065] ------------ NO_OP void N001 ( 1, 1) [000066] ------------ NO_OP void N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] ------------ t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 N001 ( 1, 1) [000074] ------------ NO_OP void N001 ( 1, 1) [000075] ------------ NO_OP void N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] ------------ t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 N001 ( 1, 1) [000083] ------------ NO_OP void N001 ( 1, 1) [000084] ------------ NO_OP void N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] ------------ t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 N001 ( 1, 1) [000092] ------------ NO_OP void N001 ( 1, 1) [000093] ------------ NO_OP void N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] ------------ t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 N001 ( 1, 1) [000101] ------------ NO_OP void N001 ( 1, 1) [000102] ------------ NO_OP void N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] ------------ t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 N001 ( 1, 1) [000110] ------------ NO_OP void N001 ( 1, 1) [000111] ------------ NO_OP void N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] ------------ t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 N001 ( 1, 1) [000119] ------------ NO_OP void N001 ( 1, 1) [000120] ------------ NO_OP void N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] ------------ t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 N001 ( 1, 1) [000128] ------------ NO_OP void N001 ( 1, 1) [000129] ------------ NO_OP void N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] ------------ t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 N001 ( 1, 1) [000137] ------------ NO_OP void N001 ( 1, 1) [000138] ------------ NO_OP void N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] ------------ t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 N001 ( 1, 1) [000146] ------------ NO_OP void N001 ( 1, 1) [000147] ------------ NO_OP void N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 N001 ( 1, 1) [000151] ------------ NO_OP void N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] ----G--N---- t172 = * ADD long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 /--* t160 int arg8 out+00 +--* t161 int arg9 out+04 +--* t162 int arg10 out+08 +--* t163 int arg11 out+0c +--* t164 int arg12 out+10 +--* t165 int arg13 out+14 +--* t166 int arg14 out+18 +--* t167 int arg15 out+1c +--* t168 long arg16 out+20 +--* t152 int arg0 in x0 +--* t153 int arg1 in x1 +--* t154 int arg2 in x2 +--* t155 int arg3 in x3 +--* t156 int arg4 in x4 +--* t157 int arg5 in x5 +--* t158 int arg6 in x6 +--* t159 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void N001 ( 1, 1) [000179] ------------ NO_OP void N001 ( 1, 1) [000180] ------------ NO_OP void N001 ( 1, 1) [000181] ------------ NO_OP void N001 ( 1, 1) [000182] ------------ NO_OP void N001 ( 1, 1) [000183] ------------ NO_OP void N001 ( 1, 1) [000184] ------------ NO_OP void N001 ( 1, 1) [000185] ------------ NO_OP void N001 ( 1, 1) [000186] ------------ NO_OP void N001 ( 1, 1) [000187] ------------ NO_OP void N001 ( 1, 1) [000188] ------------ NO_OP void N001 ( 1, 1) [000189] ------------ NO_OP void N001 ( 1, 1) [000190] ------------ NO_OP void N001 ( 1, 1) [000191] ------------ NO_OP void N001 ( 1, 1) [000192] ------------ NO_OP void N001 ( 1, 1) [000193] ------------ NO_OP void N001 ( 1, 1) [000194] ------------ NO_OP void N001 ( 1, 1) [000195] ------------ NO_OP void N001 ( 1, 1) [000196] ------------ NO_OP void N001 ( 1, 1) [000197] ------------ NO_OP void N001 ( 1, 1) [000198] ------------ NO_OP void N001 ( 1, 1) [000199] ------------ NO_OP void N001 ( 1, 1) [000200] ------------ NO_OP void N001 ( 1, 1) [000201] ------------ NO_OP void N001 ( 1, 1) [000202] ------------ NO_OP void N001 ( 1, 1) [000203] ------------ NO_OP void N001 ( 1, 1) [000204] ------------ NO_OP void N001 ( 1, 1) [000205] ------------ NO_OP void N001 ( 1, 1) [000206] ------------ NO_OP void N001 ( 1, 1) [000207] ------------ NO_OP void N001 ( 1, 1) [000208] ------------ NO_OP void N001 ( 1, 1) [000209] ------------ NO_OP void N001 ( 1, 1) [000210] ------------ NO_OP void N001 ( 1, 1) [000211] ------------ NO_OP void N001 ( 1, 1) [000212] ------------ NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} N001 ( 0, 0) [000214] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo ======= Inserting PInvoke method prolog Initializing arg info for 242.CALL: ArgTable for 242.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 240.LCL_FLD_ADDR long (By ref), 1 reg: x0, byteAlignment=8] fgArgTabEntry[arg 1 241.PHYSREG long (By ref), 1 reg: x1, byteAlignment=8] Morphing args for 242.CALL: nextSlotByteOffset=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('x0'): ( 3, 3) [000240] ------------ * LCL_FLD_ADDR long V39 PInvokeFrame [+8] Replaced with placeholder node: [000244] ----------L- * ARGPLACE long Deferred argument ('x1'): ( 1, 1) [000241] ------------ * PHYSREG long x12 Replaced with placeholder node: [000245] ----------L- * ARGPLACE long Shuffled argument table: x0 x1 ArgTable for 242.CALL after fgMorphArgs: fgArgTabEntry[arg 0 240.LCL_FLD_ADDR long (By ref), 1 reg: x0, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 241.PHYSREG long (By ref), 1 reg: x1, byteAlignment=8, lateArgInx=1, processed] N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t240 long arg0 in x0 +--* t241 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long N004 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot N001 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp /--* t247 long N002 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] N001 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp /--* t249 long N002 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] N001 ( 3, 2) [000250] ------------ t250 = LCL_VAR long V38 FramesRoot /--* t250 long N002 ( 4, 3) [000251] -c---------- t251 = * LEA(b+16) long N003 ( 3, 3) [000252] ------------ t252 = LCL_FLD_ADDR byref V39 PInvokeFrame [+8] /--* t251 long +--* t252 byref N004 ( 8, 7) [000253] ------------ * STOREIND long lowering call (before): N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t240 long arg0 in x0 +--* t241 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME objp: ====== args: ====== lowering arg : ( 0, 0) [000244] ----------L- * ARGPLACE long lowering arg : ( 0, 0) [000245] ----------L- * ARGPLACE long late: ====== lowering arg : N001 ( 3, 3) [000240] ------------ * LCL_FLD_ADDR long V39 PInvokeFrame [+8] new node is : [000254] ------------ * PUTARG_REG long REG x0 lowering arg : N002 ( 1, 1) [000241] ------------ * PHYSREG long x12 new node is : [000255] ------------ * PUTARG_REG long REG x1 lowering call (after): N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] /--* t240 long [000254] ------------ t254 = * PUTARG_REG long REG x0 N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t241 long [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME lowering store lcl var/field (before): N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] /--* t240 long [000254] ------------ t254 = * PUTARG_REG long REG x0 N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t241 long [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long N004 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot lowering store lcl var/field (after): N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] /--* t240 long [000254] ------------ t254 = * PUTARG_REG long REG x0 N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t241 long [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long N004 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot lowering store lcl var/field (before): N001 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp /--* t247 long N002 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] lowering store lcl var/field (after): N001 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp /--* t247 long N002 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] lowering store lcl var/field (before): N001 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp /--* t249 long N002 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] lowering store lcl var/field (after): N001 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp /--* t249 long N002 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] lowering store lcl var/field (before): N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 lowering store lcl var/field (after): N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 LowerCast for: N002 ( 4, 4) [000215] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 lowering store lcl var/field (after): N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 LowerCast for: N002 ( 4, 4) [000216] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 lowering store lcl var/field (after): N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 LowerCast for: N002 ( 4, 4) [000217] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 lowering store lcl var/field (after): N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 LowerCast for: N002 ( 4, 4) [000218] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 lowering store lcl var/field (after): N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 LowerCast for: N002 ( 4, 4) [000219] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 lowering store lcl var/field (after): N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 LowerCast for: N002 ( 4, 4) [000220] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 lowering store lcl var/field (after): N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 LowerCast for: N002 ( 4, 4) [000221] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 lowering store lcl var/field (after): N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 LowerCast for: N002 ( 4, 4) [000222] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 lowering store lcl var/field (after): N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 LowerCast for: N002 ( 4, 4) [000223] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 lowering store lcl var/field (after): N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 LowerCast for: N002 ( 4, 4) [000224] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 lowering store lcl var/field (after): N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 LowerCast for: N002 ( 4, 4) [000225] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 lowering store lcl var/field (after): N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 LowerCast for: N002 ( 4, 4) [000226] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 lowering store lcl var/field (after): N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 LowerCast for: N002 ( 4, 4) [000227] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 lowering store lcl var/field (after): N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 LowerCast for: N002 ( 4, 4) [000228] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 lowering store lcl var/field (after): N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 LowerCast for: N002 ( 4, 4) [000229] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 lowering store lcl var/field (after): N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 LowerCast for: N002 ( 4, 4) [000230] ------------ * CAST int <- bool <- int lowering store lcl var/field (before): N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 lowering store lcl var/field (after): N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 lowering store lcl var/field (before): N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 lowering store lcl var/field (after): N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 LowerCast for: N003 ( 2, 4) [000171] ------------ * CAST long <- int Addressing mode: Base N001 ( 3, 2) [000169] ------------ * LCL_VAR long (AX) V36 tmp1 + Index * 1 + 0 N003 ( 2, 4) [000171] ------------ * CAST long <- int New addressing mode node: N004 ( 6, 7) [000172] ------------ * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 lowering store lcl var/field (after): N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 lowering call (before): N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 /--* t160 int arg8 out+00 +--* t161 int arg9 out+04 +--* t162 int arg10 out+08 +--* t163 int arg11 out+0c +--* t164 int arg12 out+10 +--* t165 int arg13 out+14 +--* t166 int arg14 out+18 +--* t167 int arg15 out+1c +--* t168 long arg16 out+20 +--* t152 int arg0 in x0 +--* t153 int arg1 in x1 +--* t154 int arg2 in x2 +--* t155 int arg3 in x3 +--* t156 int arg4 in x4 +--* t157 int arg5 in x5 +--* t158 int arg6 in x6 +--* t159 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000231] ----------L- * ARGPLACE int lowering arg : N002 ( 0, 0) [000232] ----------L- * ARGPLACE int lowering arg : N003 ( 0, 0) [000233] ----------L- * ARGPLACE int lowering arg : N004 ( 0, 0) [000234] ----------L- * ARGPLACE int lowering arg : N005 ( 0, 0) [000235] ----------L- * ARGPLACE int lowering arg : N006 ( 0, 0) [000236] ----------L- * ARGPLACE int lowering arg : N007 ( 0, 0) [000237] ----------L- * ARGPLACE int lowering arg : N008 ( 0, 0) [000238] ----------L- * ARGPLACE int lowering arg : N009 ( 3, 2) [000160] ------------ * LCL_VAR int V26 loc9 new node is : [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) lowering arg : N010 ( 3, 2) [000161] ------------ * LCL_VAR int V27 loc10 new node is : [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) lowering arg : N011 ( 3, 2) [000162] ------------ * LCL_VAR int V28 loc11 new node is : [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) lowering arg : N012 ( 3, 2) [000163] ------------ * LCL_VAR int V29 loc12 new node is : [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) lowering arg : N013 ( 3, 2) [000164] ------------ * LCL_VAR int V30 loc13 new node is : [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) lowering arg : N014 ( 3, 2) [000165] ------------ * LCL_VAR int V31 loc14 new node is : [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) lowering arg : N015 ( 3, 2) [000166] ------------ * LCL_VAR int V32 loc15 new node is : [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) lowering arg : N016 ( 3, 2) [000167] ------------ * LCL_VAR int V33 loc16 new node is : [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) lowering arg : N017 ( 3, 2) [000168] ------------ * LCL_VAR long V34 loc17 new node is : [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) late: ====== lowering arg : N018 ( 3, 2) [000152] ------------ * LCL_VAR int V18 loc1 new node is : [000265] ------------ * PUTARG_REG int REG x0 lowering arg : N019 ( 3, 2) [000153] ------------ * LCL_VAR int V19 loc2 new node is : [000266] ------------ * PUTARG_REG int REG x1 lowering arg : N020 ( 3, 2) [000154] ------------ * LCL_VAR int V20 loc3 new node is : [000267] ------------ * PUTARG_REG int REG x2 lowering arg : N021 ( 3, 2) [000155] ------------ * LCL_VAR int V21 loc4 new node is : [000268] ------------ * PUTARG_REG int REG x3 lowering arg : N022 ( 3, 2) [000156] ------------ * LCL_VAR int V22 loc5 new node is : [000269] ------------ * PUTARG_REG int REG x4 lowering arg : N023 ( 3, 2) [000157] ------------ * LCL_VAR int V23 loc6 new node is : [000270] ------------ * PUTARG_REG int REG x5 lowering arg : N024 ( 3, 2) [000158] ------------ * LCL_VAR int V24 loc7 new node is : [000271] ------------ * PUTARG_REG int REG x6 lowering arg : N025 ( 3, 2) [000159] ------------ * LCL_VAR int V25 loc8 new node is : [000272] ------------ * PUTARG_REG int REG x7 ======= Inserting PInvoke call prolog ======= Inserting PInvoke call epilog lowering call (after): N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 /--* t160 int [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 /--* t161 int [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 /--* t162 int [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 /--* t163 int [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 /--* t164 int [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 /--* t165 int [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 /--* t166 int [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 /--* t167 int [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 /--* t168 long [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 /--* t152 int [000265] ------------ t265 = * PUTARG_REG int REG x0 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 /--* t153 int [000266] ------------ t266 = * PUTARG_REG int REG x1 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 /--* t154 int [000267] ------------ t267 = * PUTARG_REG int REG x2 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 /--* t155 int [000268] ------------ t268 = * PUTARG_REG int REG x3 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 /--* t156 int [000269] ------------ t269 = * PUTARG_REG int REG x4 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 /--* t157 int [000270] ------------ t270 = * PUTARG_REG int REG x5 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 /--* t158 int [000271] ------------ t271 = * PUTARG_REG int REG x6 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 /--* t159 int [000272] ------------ t272 = * PUTARG_REG int REG x7 N001 ( 3, 2) [000274] ------------ t274 = LCL_VAR long (AX) V36 tmp1 /--* t274 long N002 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] N001 ( 1, 1) [000277] ------------ t277 = LABEL long /--* t277 long N002 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] N001 ( 3, 2) [000278] ------------ t278 = LCL_VAR long V38 FramesRoot /--* t278 long N002 ( 4, 3) [000280] -c---------- t280 = * LEA(b+12) long N003 ( 1, 2) [000279] -c---------- t279 = CNS_INT byte 0 /--* t280 long +--* t279 byte N004 ( 6, 6) [000281] ------------ * STOREIND byte [000282] ------------ START_PREEMPTGC void N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 [000273] ------------ PINVOKE_PROLOG void /--* t265 int arg0 in x0 +--* t266 int arg1 in x1 +--* t267 int arg2 in x2 +--* t268 int arg3 in x3 +--* t269 int arg4 in x4 +--* t270 int arg5 in x5 +--* t271 int arg6 in x6 +--* t272 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void lowering GT_RETURN N001 ( 0, 0) [000214] ------------ * RETURN void =================== Inserting PInvoke method epilog Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] /--* t240 long [000254] ------------ t254 = * PUTARG_REG long REG x0 N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t241 long [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long N004 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot N001 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp /--* t247 long N002 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] N001 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp /--* t249 long N002 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] N001 ( 3, 2) [000250] ------------ t250 = LCL_VAR long V38 FramesRoot /--* t250 long N002 ( 4, 3) [000251] -c---------- t251 = * LEA(b+16) long N003 ( 3, 3) [000252] ------------ t252 = LCL_FLD_ADDR byref V39 PInvokeFrame [+8] /--* t251 long +--* t252 byref N004 ( 8, 7) [000253] ------------ * STOREIND long ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} [000239] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 N001 ( 1, 1) [000003] ------------ NO_OP void N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 N001 ( 1, 1) [000011] ------------ NO_OP void N001 ( 1, 1) [000012] ------------ NO_OP void N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 N001 ( 1, 1) [000020] ------------ NO_OP void N001 ( 1, 1) [000021] ------------ NO_OP void N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 N001 ( 1, 1) [000029] ------------ NO_OP void N001 ( 1, 1) [000030] ------------ NO_OP void N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 N001 ( 1, 1) [000038] ------------ NO_OP void N001 ( 1, 1) [000039] ------------ NO_OP void N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 N001 ( 1, 1) [000047] ------------ NO_OP void N001 ( 1, 1) [000048] ------------ NO_OP void N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 N001 ( 1, 1) [000056] ------------ NO_OP void N001 ( 1, 1) [000057] ------------ NO_OP void N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 N001 ( 1, 1) [000065] ------------ NO_OP void N001 ( 1, 1) [000066] ------------ NO_OP void N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 N001 ( 1, 1) [000074] ------------ NO_OP void N001 ( 1, 1) [000075] ------------ NO_OP void N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 N001 ( 1, 1) [000083] ------------ NO_OP void N001 ( 1, 1) [000084] ------------ NO_OP void N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 N001 ( 1, 1) [000092] ------------ NO_OP void N001 ( 1, 1) [000093] ------------ NO_OP void N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 N001 ( 1, 1) [000101] ------------ NO_OP void N001 ( 1, 1) [000102] ------------ NO_OP void N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 N001 ( 1, 1) [000110] ------------ NO_OP void N001 ( 1, 1) [000111] ------------ NO_OP void N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 N001 ( 1, 1) [000119] ------------ NO_OP void N001 ( 1, 1) [000120] ------------ NO_OP void N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 N001 ( 1, 1) [000128] ------------ NO_OP void N001 ( 1, 1) [000129] ------------ NO_OP void N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 N001 ( 1, 1) [000137] ------------ NO_OP void N001 ( 1, 1) [000138] ------------ NO_OP void N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 N001 ( 1, 1) [000146] ------------ NO_OP void N001 ( 1, 1) [000147] ------------ NO_OP void N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 N001 ( 1, 1) [000151] ------------ NO_OP void N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 /--* t160 int [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 /--* t161 int [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 /--* t162 int [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 /--* t163 int [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 /--* t164 int [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 /--* t165 int [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 /--* t166 int [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 /--* t167 int [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 /--* t168 long [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 /--* t152 int [000265] ------------ t265 = * PUTARG_REG int REG x0 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 /--* t153 int [000266] ------------ t266 = * PUTARG_REG int REG x1 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 /--* t154 int [000267] ------------ t267 = * PUTARG_REG int REG x2 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 /--* t155 int [000268] ------------ t268 = * PUTARG_REG int REG x3 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 /--* t156 int [000269] ------------ t269 = * PUTARG_REG int REG x4 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 /--* t157 int [000270] ------------ t270 = * PUTARG_REG int REG x5 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 /--* t158 int [000271] ------------ t271 = * PUTARG_REG int REG x6 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 /--* t159 int [000272] ------------ t272 = * PUTARG_REG int REG x7 N001 ( 3, 2) [000274] ------------ t274 = LCL_VAR long (AX) V36 tmp1 /--* t274 long N002 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] N001 ( 1, 1) [000277] ------------ t277 = LABEL long /--* t277 long N002 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] N001 ( 3, 2) [000278] ------------ t278 = LCL_VAR long V38 FramesRoot /--* t278 long N002 ( 4, 3) [000280] -c---------- t280 = * LEA(b+12) long N003 ( 1, 2) [000279] -c---------- t279 = CNS_INT byte 0 /--* t280 long +--* t279 byte N004 ( 6, 6) [000281] ------------ * STOREIND byte [000282] ------------ START_PREEMPTGC void N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 [000273] ------------ PINVOKE_PROLOG void /--* t265 int arg0 in x0 +--* t266 int arg1 in x1 +--* t267 int arg2 in x2 +--* t268 int arg3 in x3 +--* t269 int arg4 in x4 +--* t270 int arg5 in x5 +--* t271 int arg6 in x6 +--* t272 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR long V38 FramesRoot /--* t283 long N002 ( 4, 3) [000285] -c---------- t285 = * LEA(b+12) long N003 ( 1, 2) [000284] ------------ t284 = CNS_INT byte 1 /--* t285 long +--* t284 byte N004 ( 6, 6) [000286] ------------ * STOREIND byte N001 ( 3, 12) [000287] H----------- t287 = CNS_INT(h) long 0x1021dd928 ftn /--* t287 long N002 ( 6, 14) [000288] ------------ t288 = * IND int /--* t288 int N003 ( 7, 15) [000289] ------------ * RETURNTRAP int N001 ( 1, 1) [000179] ------------ NO_OP void N001 ( 1, 1) [000180] ------------ NO_OP void N001 ( 1, 1) [000181] ------------ NO_OP void N001 ( 1, 1) [000182] ------------ NO_OP void N001 ( 1, 1) [000183] ------------ NO_OP void N001 ( 1, 1) [000184] ------------ NO_OP void N001 ( 1, 1) [000185] ------------ NO_OP void N001 ( 1, 1) [000186] ------------ NO_OP void N001 ( 1, 1) [000187] ------------ NO_OP void N001 ( 1, 1) [000188] ------------ NO_OP void N001 ( 1, 1) [000189] ------------ NO_OP void N001 ( 1, 1) [000190] ------------ NO_OP void N001 ( 1, 1) [000191] ------------ NO_OP void N001 ( 1, 1) [000192] ------------ NO_OP void N001 ( 1, 1) [000193] ------------ NO_OP void N001 ( 1, 1) [000194] ------------ NO_OP void N001 ( 1, 1) [000195] ------------ NO_OP void N001 ( 1, 1) [000196] ------------ NO_OP void N001 ( 1, 1) [000197] ------------ NO_OP void N001 ( 1, 1) [000198] ------------ NO_OP void N001 ( 1, 1) [000199] ------------ NO_OP void N001 ( 1, 1) [000200] ------------ NO_OP void N001 ( 1, 1) [000201] ------------ NO_OP void N001 ( 1, 1) [000202] ------------ NO_OP void N001 ( 1, 1) [000203] ------------ NO_OP void N001 ( 1, 1) [000204] ------------ NO_OP void N001 ( 1, 1) [000205] ------------ NO_OP void N001 ( 1, 1) [000206] ------------ NO_OP void N001 ( 1, 1) [000207] ------------ NO_OP void N001 ( 1, 1) [000208] ------------ NO_OP void N001 ( 1, 1) [000209] ------------ NO_OP void N001 ( 1, 1) [000210] ------------ NO_OP void N001 ( 1, 1) [000211] ------------ NO_OP void N001 ( 1, 1) [000212] ------------ NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} N001 ( 3, 2) [000290] ------------ t290 = LCL_VAR long V38 FramesRoot /--* t290 long N002 ( 4, 3) [000291] -c---------- t291 = * LEA(b+16) long N003 ( 3, 4) [000292] ------------ t292 = LCL_FLD byref V39 PInvokeFrame [+16] /--* t291 long +--* t292 byref N004 ( 8, 8) [000293] ------------ * STOREIND long N001 ( 0, 0) [000214] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 bool ; V01 arg1 bool ; V02 arg2 bool ; V03 arg3 bool ; V04 arg4 bool ; V05 arg5 bool ; V06 arg6 bool ; V07 arg7 bool ; V08 arg8 bool ; V09 arg9 bool ; V10 arg10 bool ; V11 arg11 bool ; V12 arg12 bool ; V13 arg13 bool ; V14 arg14 bool ; V15 arg15 bool ; V16 arg16 long ; V17 loc0 int ; V18 loc1 int ; V19 loc2 int ; V20 loc3 int ; V21 loc4 int ; V22 loc5 int ; V23 loc6 int ; V24 loc7 int ; V25 loc8 int ; V26 loc9 int ; V27 loc10 int ; V28 loc11 int ; V29 loc12 int ; V30 loc13 int ; V31 loc14 int ; V32 loc15 int ; V33 loc16 int ; V34 loc17 long ; V35 OutArgs lclBlk <40> "OutgoingArgSpace" ; V36 tmp1 long do-not-enreg[X] addr-exposed "stub argument" ; V37 tmp2 long "impImportIndirectCall" ; V38 FramesRoot long "Pinvoke FrameListRoot" ; V39 PInvokeFrame blk do-not-enreg[X] addr-exposed "Pinvoke FrameVar" In fgLocalVarLivenessInit *************** In fgPerBlockLocalVarLiveness() *************** In fgInterBlockLocalVarLiveness() *** lvaComputeRefCounts *** *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] /--* t240 long [000254] ------------ t254 = * PUTARG_REG long REG x0 N002 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 /--* t241 long [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N003 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long N004 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot N001 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp /--* t247 long N002 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] N001 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp /--* t249 long N002 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] N001 ( 3, 2) [000250] ------------ t250 = LCL_VAR long V38 FramesRoot /--* t250 long N002 ( 4, 3) [000251] -c---------- t251 = * LEA(b+16) long N003 ( 3, 3) [000252] ------------ t252 = LCL_FLD_ADDR byref V39 PInvokeFrame [+8] /--* t251 long +--* t252 byref N004 ( 8, 7) [000253] ------------ * STOREIND long ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} [000239] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 /--* t0 int N003 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 N001 ( 1, 1) [000003] ------------ NO_OP void N001 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 /--* t4 int N002 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int N003 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 /--* t215 int +--* t5 int N004 ( 9, 7) [000006] ------------ t6 = * NE int /--* t6 int N006 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 N001 ( 1, 1) [000011] ------------ NO_OP void N001 ( 1, 1) [000012] ------------ NO_OP void N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 /--* t13 int N002 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int N003 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 /--* t216 int +--* t14 int N004 ( 9, 7) [000015] ------------ t15 = * NE int /--* t15 int N006 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 N001 ( 1, 1) [000020] ------------ NO_OP void N001 ( 1, 1) [000021] ------------ NO_OP void N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 /--* t22 int N002 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int N003 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 /--* t217 int +--* t23 int N004 ( 9, 7) [000024] ------------ t24 = * NE int /--* t24 int N006 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 N001 ( 1, 1) [000029] ------------ NO_OP void N001 ( 1, 1) [000030] ------------ NO_OP void N001 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 /--* t31 int N002 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int N003 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 /--* t218 int +--* t32 int N004 ( 9, 7) [000033] ------------ t33 = * NE int /--* t33 int N006 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 N001 ( 1, 1) [000038] ------------ NO_OP void N001 ( 1, 1) [000039] ------------ NO_OP void N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 /--* t40 int N002 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int N003 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 /--* t219 int +--* t41 int N004 ( 9, 7) [000042] ------------ t42 = * NE int /--* t42 int N006 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 N001 ( 1, 1) [000047] ------------ NO_OP void N001 ( 1, 1) [000048] ------------ NO_OP void N001 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 /--* t49 int N002 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int N003 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 /--* t220 int +--* t50 int N004 ( 9, 7) [000051] ------------ t51 = * NE int /--* t51 int N006 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 N001 ( 1, 1) [000056] ------------ NO_OP void N001 ( 1, 1) [000057] ------------ NO_OP void N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 /--* t58 int N002 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int N003 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 /--* t221 int +--* t59 int N004 ( 9, 7) [000060] ------------ t60 = * NE int /--* t60 int N006 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 N001 ( 1, 1) [000065] ------------ NO_OP void N001 ( 1, 1) [000066] ------------ NO_OP void N001 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 /--* t67 int N002 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int N003 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 /--* t222 int +--* t68 int N004 ( 9, 7) [000069] ------------ t69 = * NE int /--* t69 int N006 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 N001 ( 1, 1) [000074] ------------ NO_OP void N001 ( 1, 1) [000075] ------------ NO_OP void N001 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 /--* t76 int N002 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int N003 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 /--* t223 int +--* t77 int N004 ( 9, 7) [000078] ------------ t78 = * NE int /--* t78 int N006 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 N001 ( 1, 1) [000083] ------------ NO_OP void N001 ( 1, 1) [000084] ------------ NO_OP void N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 /--* t85 int N002 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int N003 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 /--* t224 int +--* t86 int N004 ( 9, 7) [000087] ------------ t87 = * NE int /--* t87 int N006 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 N001 ( 1, 1) [000092] ------------ NO_OP void N001 ( 1, 1) [000093] ------------ NO_OP void N001 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 /--* t94 int N002 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int N003 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 /--* t225 int +--* t95 int N004 ( 9, 7) [000096] ------------ t96 = * NE int /--* t96 int N006 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 N001 ( 1, 1) [000101] ------------ NO_OP void N001 ( 1, 1) [000102] ------------ NO_OP void N001 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 /--* t103 int N002 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int N003 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 /--* t226 int +--* t104 int N004 ( 9, 7) [000105] ------------ t105 = * NE int /--* t105 int N006 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 N001 ( 1, 1) [000110] ------------ NO_OP void N001 ( 1, 1) [000111] ------------ NO_OP void N001 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 /--* t112 int N002 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int N003 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 /--* t227 int +--* t113 int N004 ( 9, 7) [000114] ------------ t114 = * NE int /--* t114 int N006 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 N001 ( 1, 1) [000119] ------------ NO_OP void N001 ( 1, 1) [000120] ------------ NO_OP void N001 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 /--* t121 int N002 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int N003 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 /--* t228 int +--* t122 int N004 ( 9, 7) [000123] ------------ t123 = * NE int /--* t123 int N006 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 N001 ( 1, 1) [000128] ------------ NO_OP void N001 ( 1, 1) [000129] ------------ NO_OP void N001 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 /--* t130 int N002 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int N003 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 /--* t229 int +--* t131 int N004 ( 9, 7) [000132] ------------ t132 = * NE int /--* t132 int N006 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 N001 ( 1, 1) [000137] ------------ NO_OP void N001 ( 1, 1) [000138] ------------ NO_OP void N001 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 /--* t139 int N002 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int N003 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 /--* t230 int +--* t140 int N004 ( 9, 7) [000141] ------------ t141 = * NE int /--* t141 int N006 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 N001 ( 1, 1) [000146] ------------ NO_OP void N001 ( 1, 1) [000147] ------------ NO_OP void N001 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 /--* t148 long N003 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 N001 ( 1, 1) [000151] ------------ NO_OP void N001 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 N002 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 /--* t170 int N003 ( 2, 4) [000171] ------------ t171 = * CAST long <- int /--* t169 long +--* t171 long N004 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long /--* t172 long N005 ( 8, 8) [000173] *--XG------- t173 = * IND long /--* t173 long N006 ( 11, 10) [000174] *--XG------- t174 = * IND long /--* t174 long N008 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 N009 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 /--* t160 int [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) N010 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 /--* t161 int [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) N011 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 /--* t162 int [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) N012 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 /--* t163 int [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) N013 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 /--* t164 int [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) N014 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 /--* t165 int [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) N015 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 /--* t166 int [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) N016 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 /--* t167 int [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) N017 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 /--* t168 long [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) N018 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 /--* t152 int [000265] ------------ t265 = * PUTARG_REG int REG x0 N019 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 /--* t153 int [000266] ------------ t266 = * PUTARG_REG int REG x1 N020 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 /--* t154 int [000267] ------------ t267 = * PUTARG_REG int REG x2 N021 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 /--* t155 int [000268] ------------ t268 = * PUTARG_REG int REG x3 N022 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 /--* t156 int [000269] ------------ t269 = * PUTARG_REG int REG x4 N023 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 /--* t157 int [000270] ------------ t270 = * PUTARG_REG int REG x5 N024 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 /--* t158 int [000271] ------------ t271 = * PUTARG_REG int REG x6 N025 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 /--* t159 int [000272] ------------ t272 = * PUTARG_REG int REG x7 N001 ( 3, 2) [000274] ------------ t274 = LCL_VAR long (AX) V36 tmp1 /--* t274 long N002 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] N001 ( 1, 1) [000277] ------------ t277 = LABEL long /--* t277 long N002 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] N001 ( 3, 2) [000278] ------------ t278 = LCL_VAR long V38 FramesRoot /--* t278 long N002 ( 4, 3) [000280] -c---------- t280 = * LEA(b+12) long N003 ( 1, 2) [000279] -c---------- t279 = CNS_INT byte 0 /--* t280 long +--* t279 byte N004 ( 6, 6) [000281] ------------ * STOREIND byte [000282] ------------ START_PREEMPTGC void N026 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 [000273] ------------ PINVOKE_PROLOG void /--* t265 int arg0 in x0 +--* t266 int arg1 in x1 +--* t267 int arg2 in x2 +--* t268 int arg3 in x3 +--* t269 int arg4 in x4 +--* t270 int arg5 in x5 +--* t271 int arg6 in x6 +--* t272 int arg7 in x7 +--* t177 long calli tgt N027 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void N001 ( 3, 2) [000283] ------------ t283 = LCL_VAR long V38 FramesRoot /--* t283 long N002 ( 4, 3) [000285] -c---------- t285 = * LEA(b+12) long N003 ( 1, 2) [000284] ------------ t284 = CNS_INT byte 1 /--* t285 long +--* t284 byte N004 ( 6, 6) [000286] ------------ * STOREIND byte N001 ( 3, 12) [000287] H----------- t287 = CNS_INT(h) long 0x1021dd928 ftn /--* t287 long N002 ( 6, 14) [000288] ------------ t288 = * IND int /--* t288 int N003 ( 7, 15) [000289] ------------ * RETURNTRAP int N001 ( 1, 1) [000179] ------------ NO_OP void N001 ( 1, 1) [000180] ------------ NO_OP void N001 ( 1, 1) [000181] ------------ NO_OP void N001 ( 1, 1) [000182] ------------ NO_OP void N001 ( 1, 1) [000183] ------------ NO_OP void N001 ( 1, 1) [000184] ------------ NO_OP void N001 ( 1, 1) [000185] ------------ NO_OP void N001 ( 1, 1) [000186] ------------ NO_OP void N001 ( 1, 1) [000187] ------------ NO_OP void N001 ( 1, 1) [000188] ------------ NO_OP void N001 ( 1, 1) [000189] ------------ NO_OP void N001 ( 1, 1) [000190] ------------ NO_OP void N001 ( 1, 1) [000191] ------------ NO_OP void N001 ( 1, 1) [000192] ------------ NO_OP void N001 ( 1, 1) [000193] ------------ NO_OP void N001 ( 1, 1) [000194] ------------ NO_OP void N001 ( 1, 1) [000195] ------------ NO_OP void N001 ( 1, 1) [000196] ------------ NO_OP void N001 ( 1, 1) [000197] ------------ NO_OP void N001 ( 1, 1) [000198] ------------ NO_OP void N001 ( 1, 1) [000199] ------------ NO_OP void N001 ( 1, 1) [000200] ------------ NO_OP void N001 ( 1, 1) [000201] ------------ NO_OP void N001 ( 1, 1) [000202] ------------ NO_OP void N001 ( 1, 1) [000203] ------------ NO_OP void N001 ( 1, 1) [000204] ------------ NO_OP void N001 ( 1, 1) [000205] ------------ NO_OP void N001 ( 1, 1) [000206] ------------ NO_OP void N001 ( 1, 1) [000207] ------------ NO_OP void N001 ( 1, 1) [000208] ------------ NO_OP void N001 ( 1, 1) [000209] ------------ NO_OP void N001 ( 1, 1) [000210] ------------ NO_OP void N001 ( 1, 1) [000211] ------------ NO_OP void N001 ( 1, 1) [000212] ------------ NO_OP void ------------ BB03 [???..???) (return), preds={BB02} succs={} N001 ( 3, 2) [000290] ------------ t290 = LCL_VAR long V38 FramesRoot /--* t290 long N002 ( 4, 3) [000291] -c---------- t291 = * LEA(b+16) long N003 ( 3, 4) [000292] ------------ t292 = LCL_FLD byref V39 PInvokeFrame [+16] /--* t291 long +--* t292 byref N004 ( 8, 8) [000293] ------------ * STOREIND long N001 ( 0, 0) [000214] ------------ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {} {} {} {} BB02 use def in out {} {} {} {} BB03 use def in out {} {} {} {} FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 *************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false Assign V00 arg0, size=4, stkOffs=-0x54 Assign V01 arg1, size=4, stkOffs=-0x58 Assign V02 arg2, size=4, stkOffs=-0x5c Assign V03 arg3, size=4, stkOffs=-0x60 Assign V04 arg4, size=4, stkOffs=-0x64 Assign V05 arg5, size=4, stkOffs=-0x68 Assign V06 arg6, size=4, stkOffs=-0x6c Assign V07 arg7, size=4, stkOffs=-0x70 Assign V17 loc0, size=4, stkOffs=-0x74 Assign V18 loc1, size=4, stkOffs=-0x78 Assign V19 loc2, size=4, stkOffs=-0x7c Assign V20 loc3, size=4, stkOffs=-0x80 Assign V21 loc4, size=4, stkOffs=-0x84 Assign V22 loc5, size=4, stkOffs=-0x88 Assign V23 loc6, size=4, stkOffs=-0x8c Assign V24 loc7, size=4, stkOffs=-0x90 Assign V25 loc8, size=4, stkOffs=-0x94 Assign V26 loc9, size=4, stkOffs=-0x98 Assign V27 loc10, size=4, stkOffs=-0x9c Assign V28 loc11, size=4, stkOffs=-0xa0 Assign V29 loc12, size=4, stkOffs=-0xa4 Assign V30 loc13, size=4, stkOffs=-0xa8 Assign V31 loc14, size=4, stkOffs=-0xac Assign V32 loc15, size=4, stkOffs=-0xb0 Assign V33 loc16, size=4, stkOffs=-0xb4 Pad V34 loc17, size=8, stkOffs=-0xbb, pad=7 Assign V34 loc17, size=8, stkOffs=-0xc3 Pad V37 tmp2, size=8, stkOffs=-0xca, pad=7 Assign V37 tmp2, size=8, stkOffs=-0xd2 Pad V38 FramesRoot, size=8, stkOffs=-0xd9, pad=7 Assign V38 FramesRoot, size=8, stkOffs=-0xe1 Pad V36 tmp1, size=8, stkOffs=-0xe8, pad=7 Assign V36 tmp1, size=8, stkOffs=-0xf0 Pad V39 PInvokeFrame, size=72, stkOffs=-0xf7, pad=7 Assign V39 PInvokeFrame, size=72, stkOffs=-0x13f Pad V35 OutArgs, size=40, stkOffs=-0x156, pad=7 Assign V35 OutArgs, size=40, stkOffs=-0x17e --- delta bump 352 for RBP frame --- virtual stack offset to actual stack offset delta is 352 -- V00 was -84, now 268 -- V01 was -88, now 264 -- V02 was -92, now 260 -- V03 was -96, now 256 -- V04 was -100, now 252 -- V05 was -104, now 248 -- V06 was -108, now 244 -- V07 was -112, now 240 -- V08 was 0, now 352 -- V09 was 1, now 353 -- V10 was 2, now 354 -- V11 was 3, now 355 -- V12 was 4, now 356 -- V13 was 5, now 357 -- V14 was 6, now 358 -- V15 was 7, now 359 -- V16 was 8, now 360 -- V17 was -116, now 236 -- V18 was -120, now 232 -- V19 was -124, now 228 -- V20 was -128, now 224 -- V21 was -132, now 220 -- V22 was -136, now 216 -- V23 was -140, now 212 -- V24 was -144, now 208 -- V25 was -148, now 204 -- V26 was -152, now 200 -- V27 was -156, now 196 -- V28 was -160, now 192 -- V29 was -164, now 188 -- V30 was -168, now 184 -- V31 was -172, now 180 -- V32 was -176, now 176 -- V33 was -180, now 172 -- V34 was -195, now 157 -- V35 was -382, now -30 -- V36 was -240, now 112 -- V37 was -210, now 142 -- V38 was -225, now 127 -- V39 was -319, now 33 compRsvdRegCheck frame size = 392 compArgSize = 24 Returning true (MinOpts) Reserved REG_OPT_RSVD (xip1) due to large frame TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 1 ) BB01 [???..???), preds={} succs={BB02} ===== N001. t240 = LCL_FLD_ADDR V39 PInvokeFrame [+8] N000. t254 = PUTARG_REG; t240 N002. t241 = PHYSREG x12 N000. t255 = PUTARG_REG; t241 N003. t242 = CALL help; t254,t255 N004. V38 MEM; t242 N001. t247 = PHYSREG sp N002. V39 MEM; t247 N001. t249 = PHYSREG fp N002. V39 MEM; t249 N001. t250 = V38 MEM N002. t251 = LEA(b+16); t250 N003. t252 = LCL_FLD_ADDR V39 PInvokeFrame [+8] N004. STOREIND ; t251,t252 BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} ===== N000. IL_OFFSET IL offset: 0x0 N001. t0 = CNS_INT 0 N003. V17 MEM; t0 N001. NO_OP N001. t4 = V00 MEM N002. t215 = CAST ; t4 N003. CNS_INT 0 N004. t6 = NE ; t215 N006. V18 MEM; t6 N001. NO_OP N001. NO_OP N001. t13 = V01 MEM N002. t216 = CAST ; t13 N003. CNS_INT 0 N004. t15 = NE ; t216 N006. V19 MEM; t15 N001. NO_OP N001. NO_OP N001. t22 = V02 MEM N002. t217 = CAST ; t22 N003. CNS_INT 0 N004. t24 = NE ; t217 N006. V20 MEM; t24 N001. NO_OP N001. NO_OP N001. t31 = V03 MEM N002. t218 = CAST ; t31 N003. CNS_INT 0 N004. t33 = NE ; t218 N006. V21 MEM; t33 N001. NO_OP N001. NO_OP N001. t40 = V04 MEM N002. t219 = CAST ; t40 N003. CNS_INT 0 N004. t42 = NE ; t219 N006. V22 MEM; t42 N001. NO_OP N001. NO_OP N001. t49 = V05 MEM N002. t220 = CAST ; t49 N003. CNS_INT 0 N004. t51 = NE ; t220 N006. V23 MEM; t51 N001. NO_OP N001. NO_OP N001. t58 = V06 MEM N002. t221 = CAST ; t58 N003. CNS_INT 0 N004. t60 = NE ; t221 N006. V24 MEM; t60 N001. NO_OP N001. NO_OP N001. t67 = V07 MEM N002. t222 = CAST ; t67 N003. CNS_INT 0 N004. t69 = NE ; t222 N006. V25 MEM; t69 N001. NO_OP N001. NO_OP N001. t76 = V08 MEM N002. t223 = CAST ; t76 N003. CNS_INT 0 N004. t78 = NE ; t223 N006. V26 MEM; t78 N001. NO_OP N001. NO_OP N001. t85 = V09 MEM N002. t224 = CAST ; t85 N003. CNS_INT 0 N004. t87 = NE ; t224 N006. V27 MEM; t87 N001. NO_OP N001. NO_OP N001. t94 = V10 MEM N002. t225 = CAST ; t94 N003. CNS_INT 0 N004. t96 = NE ; t225 N006. V28 MEM; t96 N001. NO_OP N001. NO_OP N001. t103 = V11 MEM N002. t226 = CAST ; t103 N003. CNS_INT 0 N004. t105 = NE ; t226 N006. V29 MEM; t105 N001. NO_OP N001. NO_OP N001. t112 = V12 MEM N002. t227 = CAST ; t112 N003. CNS_INT 0 N004. t114 = NE ; t227 N006. V30 MEM; t114 N001. NO_OP N001. NO_OP N001. t121 = V13 MEM N002. t228 = CAST ; t121 N003. CNS_INT 0 N004. t123 = NE ; t228 N006. V31 MEM; t123 N001. NO_OP N001. NO_OP N001. t130 = V14 MEM N002. t229 = CAST ; t130 N003. CNS_INT 0 N004. t132 = NE ; t229 N006. V32 MEM; t132 N001. NO_OP N001. NO_OP N001. t139 = V15 MEM N002. t230 = CAST ; t139 N003. CNS_INT 0 N004. t141 = NE ; t230 N006. V33 MEM; t141 N001. NO_OP N001. NO_OP N001. t148 = V16 MEM N003. V34 MEM; t148 N001. NO_OP N001. t169 = V36 MEM N002. t170 = CNS_INT 72 N003. t171 = CAST ; t170 N004. t172 = LEA(b+(i*1)+0); t169,t171 N005. t173 = IND ; t172 N006. t174 = IND ; t173 N008. V37 MEM; t174 N009. t160 = V26 MEM N000. PUTARG_STK [+0x00]; t160 N010. t161 = V27 MEM N000. PUTARG_STK [+0x04]; t161 N011. t162 = V28 MEM N000. PUTARG_STK [+0x08]; t162 N012. t163 = V29 MEM N000. PUTARG_STK [+0x0c]; t163 N013. t164 = V30 MEM N000. PUTARG_STK [+0x10]; t164 N014. t165 = V31 MEM N000. PUTARG_STK [+0x14]; t165 N015. t166 = V32 MEM N000. PUTARG_STK [+0x18]; t166 N016. t167 = V33 MEM N000. PUTARG_STK [+0x1c]; t167 N017. t168 = V34 MEM N000. PUTARG_STK [+0x20]; t168 N018. t152 = V18 MEM N000. t265 = PUTARG_REG; t152 N019. t153 = V19 MEM N000. t266 = PUTARG_REG; t153 N020. t154 = V20 MEM N000. t267 = PUTARG_REG; t154 N021. t155 = V21 MEM N000. t268 = PUTARG_REG; t155 N022. t156 = V22 MEM N000. t269 = PUTARG_REG; t156 N023. t157 = V23 MEM N000. t270 = PUTARG_REG; t157 N024. t158 = V24 MEM N000. t271 = PUTARG_REG; t158 N025. t159 = V25 MEM N000. t272 = PUTARG_REG; t159 N001. t274 = V36 MEM N002. V39 MEM; t274 N001. t277 = LABEL N002. V39 MEM; t277 N001. t278 = V38 MEM N002. t280 = LEA(b+12); t278 N003. CNS_INT 0 N004. STOREIND ; t280 N000. START_PREEMPTGC N026. t177 = V37 MEM N000. PINVOKE_PROLOG N027. CALL ind unman popargs; t265,t266,t267,t268,t269,t270,t271,t272,t177 N001. t283 = V38 MEM N002. t285 = LEA(b+12); t283 N003. t284 = CNS_INT 1 N004. STOREIND ; t285,t284 N001. t287 = CNS_INT(h) 0x1021dd928 ftn N002. t288 = IND ; t287 N003. RETURNTRAP; t288 N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP N001. NO_OP BB03 [???..???) (return), preds={BB02} succs={} ===== N001. t290 = V38 MEM N002. t291 = LEA(b+16); t290 N003. t292 = V39 MEM N004. STOREIND ; t291,t292 N001. RETURN buildIntervals second part ======== Int arg V00 in reg x0 Int arg V01 in reg x1 Int arg V02 in reg x2 Int arg V03 in reg x3 Int arg V04 in reg x4 Int arg V05 in reg x5 Int arg V06 in reg x6 Int arg V07 in reg x7 NEW BLOCK BB01 DefList: { } N002 ( 3, 3) [000240] ------------ * LCL_FLD_ADDR long V39 PInvokeFrame [+8] NA REG NA Interval 0: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD_ADDR BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N002.t240. LCL_FLD_ADDR } N004 (???,???) [000254] ------------ * PUTARG_REG long REG x0 BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> Interval 1: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x0] minReg=1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed> DefList: { N004.t254. PUTARG_REG } N006 ( 1, 1) [000241] ------------ * PHYSREG long x12 REG NA Interval 2: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N004.t254. PUTARG_REG; N006.t241. PHYSREG } N008 (???,???) [000255] ------------ * PUTARG_REG long REG x1 BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> Interval 3: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x1] minReg=1> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed> DefList: { N004.t254. PUTARG_REG; N008.t255. PUTARG_REG } N010 ( 18, 8) [000242] --C-G------- * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME REG NA BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x0] minReg=1> BB01 regmask=[x1] minReg=1> BB01 regmask=[x2] minReg=1> BB01 regmask=[x3] minReg=1> BB01 regmask=[x4] minReg=1> BB01 regmask=[x5] minReg=1> BB01 regmask=[x6] minReg=1> BB01 regmask=[x7] minReg=1> BB01 regmask=[x8] minReg=1> BB01 regmask=[x9] minReg=1> BB01 regmask=[x10] minReg=1> BB01 regmask=[x11] minReg=1> BB01 regmask=[x12] minReg=1> BB01 regmask=[x13] minReg=1> BB01 regmask=[x14] minReg=1> BB01 regmask=[x15] minReg=1> BB01 regmask=[xip0] minReg=1> BB01 regmask=[xip1] minReg=1> BB01 regmask=[lr] minReg=1> Interval 4: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x0] minReg=1> CALL BB01 regmask=[x0] minReg=1 fixed> DefList: { N010.t242. CALL } N012 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N014 ( 1, 1) [000247] ------------ * PHYSREG long sp REG NA Interval 5: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N014.t247. PHYSREG } N016 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N018 ( 1, 1) [000249] ------------ * PHYSREG long fp REG NA Interval 6: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N018.t249. PHYSREG } N020 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N022 ( 3, 2) [000250] ------------ * LCL_VAR long V38 FramesRoot NA REG NA Interval 7: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N022.t250. LCL_VAR } N024 ( 4, 3) [000251] -c---------- * LEA(b+16) long REG NA Contained DefList: { N022.t250. LCL_VAR } N026 ( 3, 3) [000252] ------------ * LCL_FLD_ADDR byref V39 PInvokeFrame [+8] NA REG NA Interval 8: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD_ADDR BB01 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N022.t250. LCL_VAR; N026.t252. LCL_FLD_ADDR } N028 ( 8, 7) [000253] ------------ * STOREIND long REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N032 (???,???) [000239] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N034 ( 1, 2) [000000] ------------ * CNS_INT int 0 REG NA Interval 9: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N034.t0. CNS_INT } N036 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N038 ( 1, 1) [000003] ------------ * NO_OP void REG NA DefList: { } N040 ( 3, 2) [000004] ------------ * LCL_VAR int V00 arg0 NA REG NA Interval 10: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N040.t4. LCL_VAR } N042 ( 4, 4) [000215] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 11: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N042.t215. CAST } N044 ( 1, 2) [000005] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N042.t215. CAST } N046 ( 9, 7) [000006] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 12: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N046.t6. NE } N048 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N050 ( 1, 1) [000011] ------------ * NO_OP void REG NA DefList: { } N052 ( 1, 1) [000012] ------------ * NO_OP void REG NA DefList: { } N054 ( 3, 2) [000013] ------------ * LCL_VAR int V01 arg1 NA REG NA Interval 13: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N054.t13. LCL_VAR } N056 ( 4, 4) [000216] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 14: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N056.t216. CAST } N058 ( 1, 2) [000014] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N056.t216. CAST } N060 ( 9, 7) [000015] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 15: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N060.t15. NE } N062 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N064 ( 1, 1) [000020] ------------ * NO_OP void REG NA DefList: { } N066 ( 1, 1) [000021] ------------ * NO_OP void REG NA DefList: { } N068 ( 3, 2) [000022] ------------ * LCL_VAR int V02 arg2 NA REG NA Interval 16: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N068.t22. LCL_VAR } N070 ( 4, 4) [000217] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 17: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N070.t217. CAST } N072 ( 1, 2) [000023] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N070.t217. CAST } N074 ( 9, 7) [000024] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 18: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N074.t24. NE } N076 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N078 ( 1, 1) [000029] ------------ * NO_OP void REG NA DefList: { } N080 ( 1, 1) [000030] ------------ * NO_OP void REG NA DefList: { } N082 ( 3, 2) [000031] ------------ * LCL_VAR int V03 arg3 NA REG NA Interval 19: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N082.t31. LCL_VAR } N084 ( 4, 4) [000218] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 20: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N084.t218. CAST } N086 ( 1, 2) [000032] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N084.t218. CAST } N088 ( 9, 7) [000033] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 21: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N088.t33. NE } N090 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N092 ( 1, 1) [000038] ------------ * NO_OP void REG NA DefList: { } N094 ( 1, 1) [000039] ------------ * NO_OP void REG NA DefList: { } N096 ( 3, 2) [000040] ------------ * LCL_VAR int V04 arg4 NA REG NA Interval 22: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N096.t40. LCL_VAR } N098 ( 4, 4) [000219] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 23: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N098.t219. CAST } N100 ( 1, 2) [000041] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N098.t219. CAST } N102 ( 9, 7) [000042] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 24: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N102.t42. NE } N104 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N106 ( 1, 1) [000047] ------------ * NO_OP void REG NA DefList: { } N108 ( 1, 1) [000048] ------------ * NO_OP void REG NA DefList: { } N110 ( 3, 2) [000049] ------------ * LCL_VAR int V05 arg5 NA REG NA Interval 25: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N110.t49. LCL_VAR } N112 ( 4, 4) [000220] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 26: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N112.t220. CAST } N114 ( 1, 2) [000050] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N112.t220. CAST } N116 ( 9, 7) [000051] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 27: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N116.t51. NE } N118 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N120 ( 1, 1) [000056] ------------ * NO_OP void REG NA DefList: { } N122 ( 1, 1) [000057] ------------ * NO_OP void REG NA DefList: { } N124 ( 3, 2) [000058] ------------ * LCL_VAR int V06 arg6 NA REG NA Interval 28: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N124.t58. LCL_VAR } N126 ( 4, 4) [000221] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 29: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N126.t221. CAST } N128 ( 1, 2) [000059] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N126.t221. CAST } N130 ( 9, 7) [000060] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 30: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N130.t60. NE } N132 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N134 ( 1, 1) [000065] ------------ * NO_OP void REG NA DefList: { } N136 ( 1, 1) [000066] ------------ * NO_OP void REG NA DefList: { } N138 ( 3, 2) [000067] ------------ * LCL_VAR int V07 arg7 NA REG NA Interval 31: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N138.t67. LCL_VAR } N140 ( 4, 4) [000222] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 32: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N140.t222. CAST } N142 ( 1, 2) [000068] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N140.t222. CAST } N144 ( 9, 7) [000069] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 33: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N144.t69. NE } N146 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N148 ( 1, 1) [000074] ------------ * NO_OP void REG NA DefList: { } N150 ( 1, 1) [000075] ------------ * NO_OP void REG NA DefList: { } N152 ( 3, 2) [000076] ------------ * LCL_VAR int V08 arg8 NA REG NA Interval 34: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N152.t76. LCL_VAR } N154 ( 4, 4) [000223] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 35: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N154.t223. CAST } N156 ( 1, 2) [000077] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N154.t223. CAST } N158 ( 9, 7) [000078] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 36: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N158.t78. NE } N160 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N162 ( 1, 1) [000083] ------------ * NO_OP void REG NA DefList: { } N164 ( 1, 1) [000084] ------------ * NO_OP void REG NA DefList: { } N166 ( 3, 2) [000085] ------------ * LCL_VAR int V09 arg9 NA REG NA Interval 37: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N166.t85. LCL_VAR } N168 ( 4, 4) [000224] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 38: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N168.t224. CAST } N170 ( 1, 2) [000086] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N168.t224. CAST } N172 ( 9, 7) [000087] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 39: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N172.t87. NE } N174 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N176 ( 1, 1) [000092] ------------ * NO_OP void REG NA DefList: { } N178 ( 1, 1) [000093] ------------ * NO_OP void REG NA DefList: { } N180 ( 3, 2) [000094] ------------ * LCL_VAR int V10 arg10 NA REG NA Interval 40: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N180.t94. LCL_VAR } N182 ( 4, 4) [000225] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 41: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N182.t225. CAST } N184 ( 1, 2) [000095] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N182.t225. CAST } N186 ( 9, 7) [000096] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 42: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N186.t96. NE } N188 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N190 ( 1, 1) [000101] ------------ * NO_OP void REG NA DefList: { } N192 ( 1, 1) [000102] ------------ * NO_OP void REG NA DefList: { } N194 ( 3, 2) [000103] ------------ * LCL_VAR int V11 arg11 NA REG NA Interval 43: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N194.t103. LCL_VAR } N196 ( 4, 4) [000226] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 44: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N196.t226. CAST } N198 ( 1, 2) [000104] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N196.t226. CAST } N200 ( 9, 7) [000105] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 45: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N200.t105. NE } N202 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N204 ( 1, 1) [000110] ------------ * NO_OP void REG NA DefList: { } N206 ( 1, 1) [000111] ------------ * NO_OP void REG NA DefList: { } N208 ( 3, 2) [000112] ------------ * LCL_VAR int V12 arg12 NA REG NA Interval 46: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N208.t112. LCL_VAR } N210 ( 4, 4) [000227] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 47: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N210.t227. CAST } N212 ( 1, 2) [000113] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N210.t227. CAST } N214 ( 9, 7) [000114] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 48: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N214.t114. NE } N216 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N218 ( 1, 1) [000119] ------------ * NO_OP void REG NA DefList: { } N220 ( 1, 1) [000120] ------------ * NO_OP void REG NA DefList: { } N222 ( 3, 2) [000121] ------------ * LCL_VAR int V13 arg13 NA REG NA Interval 49: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N222.t121. LCL_VAR } N224 ( 4, 4) [000228] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 50: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N224.t228. CAST } N226 ( 1, 2) [000122] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N224.t228. CAST } N228 ( 9, 7) [000123] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 51: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N228.t123. NE } N230 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N232 ( 1, 1) [000128] ------------ * NO_OP void REG NA DefList: { } N234 ( 1, 1) [000129] ------------ * NO_OP void REG NA DefList: { } N236 ( 3, 2) [000130] ------------ * LCL_VAR int V14 arg14 NA REG NA Interval 52: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N236.t130. LCL_VAR } N238 ( 4, 4) [000229] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 53: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N238.t229. CAST } N240 ( 1, 2) [000131] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N238.t229. CAST } N242 ( 9, 7) [000132] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 54: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N242.t132. NE } N244 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N246 ( 1, 1) [000137] ------------ * NO_OP void REG NA DefList: { } N248 ( 1, 1) [000138] ------------ * NO_OP void REG NA DefList: { } N250 ( 3, 2) [000139] ------------ * LCL_VAR int V15 arg15 NA REG NA Interval 55: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N250.t139. LCL_VAR } N252 ( 4, 4) [000230] ------------ * CAST int <- bool <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 56: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N252.t230. CAST } N254 ( 1, 2) [000140] -c---------- * CNS_INT int 0 REG NA Contained DefList: { N252.t230. CAST } N256 ( 9, 7) [000141] ------------ * NE int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 57: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N256.t141. NE } N258 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N260 ( 1, 1) [000146] ------------ * NO_OP void REG NA DefList: { } N262 ( 1, 1) [000147] ------------ * NO_OP void REG NA DefList: { } N264 ( 3, 2) [000148] ------------ * LCL_VAR long V16 arg16 NA REG NA Interval 58: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N264.t148. LCL_VAR } N266 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N268 ( 1, 1) [000151] ------------ * NO_OP void REG NA DefList: { } N270 ( 3, 2) [000169] ------------ * LCL_VAR long (AX) V36 tmp1 NA REG NA Interval 59: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N270.t169. LCL_VAR } N272 ( 1, 2) [000170] ------------ * CNS_INT int 72 REG NA Interval 60: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N270.t169. LCL_VAR; N272.t170. CNS_INT } N274 ( 2, 4) [000171] ------------ * CAST long <- int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 61: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N270.t169. LCL_VAR; N274.t171. CAST } N276 ( 6, 7) [000172] -c---------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { N270.t169. LCL_VAR; N274.t171. CAST } N278 ( 8, 8) [000173] *--XG------- * IND long REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 62: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N278.t173. IND } N280 ( 11, 10) [000174] *--XG------- * IND long REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 63: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N280.t174. IND } N282 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N284 ( 3, 2) [000160] ------------ * LCL_VAR int V26 loc9 NA REG NA Interval 64: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N284.t160. LCL_VAR } N286 (???,???) [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N288 ( 3, 2) [000161] ------------ * LCL_VAR int V27 loc10 NA REG NA Interval 65: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N288.t161. LCL_VAR } N290 (???,???) [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N292 ( 3, 2) [000162] ------------ * LCL_VAR int V28 loc11 NA REG NA Interval 66: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N292.t162. LCL_VAR } N294 (???,???) [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N296 ( 3, 2) [000163] ------------ * LCL_VAR int V29 loc12 NA REG NA Interval 67: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N296.t163. LCL_VAR } N298 (???,???) [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N300 ( 3, 2) [000164] ------------ * LCL_VAR int V30 loc13 NA REG NA Interval 68: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N300.t164. LCL_VAR } N302 (???,???) [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N304 ( 3, 2) [000165] ------------ * LCL_VAR int V31 loc14 NA REG NA Interval 69: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N304.t165. LCL_VAR } N306 (???,???) [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N308 ( 3, 2) [000166] ------------ * LCL_VAR int V32 loc15 NA REG NA Interval 70: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N308.t166. LCL_VAR } N310 (???,???) [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N312 ( 3, 2) [000167] ------------ * LCL_VAR int V33 loc16 NA REG NA Interval 71: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N312.t167. LCL_VAR } N314 (???,???) [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N316 ( 3, 2) [000168] ------------ * LCL_VAR long V34 loc17 NA REG NA Interval 72: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N316.t168. LCL_VAR } N318 (???,???) [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N320 ( 3, 2) [000152] ------------ * LCL_VAR int V18 loc1 NA REG NA Interval 73: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N320.t152. LCL_VAR } N322 (???,???) [000265] ------------ * PUTARG_REG int REG x0 BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> Interval 74: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x0] minReg=1> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG } N324 ( 3, 2) [000153] ------------ * LCL_VAR int V19 loc2 NA REG NA Interval 75: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N324.t153. LCL_VAR } N326 (???,???) [000266] ------------ * PUTARG_REG int REG x1 BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> Interval 76: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x1] minReg=1> PUTARG_REG BB02 regmask=[x1] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG } N328 ( 3, 2) [000154] ------------ * LCL_VAR int V20 loc3 NA REG NA Interval 77: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N328.t154. LCL_VAR } N330 (???,???) [000267] ------------ * PUTARG_REG int REG x2 BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> Interval 78: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x2] minReg=1> PUTARG_REG BB02 regmask=[x2] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG } N332 ( 3, 2) [000155] ------------ * LCL_VAR int V21 loc4 NA REG NA Interval 79: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N332.t155. LCL_VAR } N334 (???,???) [000268] ------------ * PUTARG_REG int REG x3 BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> Interval 80: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x3] minReg=1> PUTARG_REG BB02 regmask=[x3] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG } N336 ( 3, 2) [000156] ------------ * LCL_VAR int V22 loc5 NA REG NA Interval 81: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N336.t156. LCL_VAR } N338 (???,???) [000269] ------------ * PUTARG_REG int REG x4 BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> Interval 82: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x4] minReg=1> PUTARG_REG BB02 regmask=[x4] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG } N340 ( 3, 2) [000157] ------------ * LCL_VAR int V23 loc6 NA REG NA Interval 83: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N340.t157. LCL_VAR } N342 (???,???) [000270] ------------ * PUTARG_REG int REG x5 BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> Interval 84: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x5] minReg=1> PUTARG_REG BB02 regmask=[x5] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG } N344 ( 3, 2) [000158] ------------ * LCL_VAR int V24 loc7 NA REG NA Interval 85: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N344.t158. LCL_VAR } N346 (???,???) [000271] ------------ * PUTARG_REG int REG x6 BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> Interval 86: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x6] minReg=1> PUTARG_REG BB02 regmask=[x6] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG } N348 ( 3, 2) [000159] ------------ * LCL_VAR int V25 loc8 NA REG NA Interval 87: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N348.t159. LCL_VAR } N350 (???,???) [000272] ------------ * PUTARG_REG int REG x7 BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> Interval 88: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB02 regmask=[x7] minReg=1> PUTARG_REG BB02 regmask=[x7] minReg=1 fixed> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG } N352 ( 3, 2) [000274] ------------ * LCL_VAR long (AX) V36 tmp1 NA REG NA Interval 89: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N352.t274. LCL_VAR } N354 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG } N356 ( 1, 1) [000277] ------------ * LABEL long REG NA Interval 90: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LABEL BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N356.t277. LABEL } N358 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] NA REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG } N360 ( 3, 2) [000278] ------------ * LCL_VAR long V38 FramesRoot NA REG NA Interval 91: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N360.t278. LCL_VAR } N362 ( 4, 3) [000280] -c---------- * LEA(b+12) long REG NA Contained DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N360.t278. LCL_VAR } N364 ( 1, 2) [000279] -c---------- * CNS_INT byte 0 REG NA Contained DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N360.t278. LCL_VAR } N366 ( 6, 6) [000281] ------------ * STOREIND byte REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG } N368 (???,???) [000282] ------------ * START_PREEMPTGC void REG NA DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG } N370 ( 3, 2) [000177] ------------ * LCL_VAR long V37 tmp2 NA REG NA Interval 92: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N370.t177. LCL_VAR } N372 (???,???) [000273] ------------ * PINVOKE_PROLOG void REG NA DefList: { N322.t265. PUTARG_REG; N326.t266. PUTARG_REG; N330.t267. PUTARG_REG; N334.t268. PUTARG_REG; N338.t269. PUTARG_REG; N342.t270. PUTARG_REG; N346.t271. PUTARG_REG; N350.t272. PUTARG_REG; N370.t177. LCL_VAR } N374 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void REG NA BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1> BB02 regmask=[x1] minReg=1> BB02 regmask=[x2] minReg=1> BB02 regmask=[x3] minReg=1> BB02 regmask=[x4] minReg=1> BB02 regmask=[x5] minReg=1> BB02 regmask=[x6] minReg=1> BB02 regmask=[x7] minReg=1> BB02 regmask=[x8] minReg=1> BB02 regmask=[x9] minReg=1> BB02 regmask=[x10] minReg=1> BB02 regmask=[x11] minReg=1> BB02 regmask=[x12] minReg=1> BB02 regmask=[x13] minReg=1> BB02 regmask=[x14] minReg=1> BB02 regmask=[x15] minReg=1> BB02 regmask=[xip0] minReg=1> BB02 regmask=[xip1] minReg=1> BB02 regmask=[lr] minReg=1> DefList: { } N376 ( 3, 2) [000283] ------------ * LCL_VAR long V38 FramesRoot NA REG NA Interval 93: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N376.t283. LCL_VAR } N378 ( 4, 3) [000285] -c---------- * LEA(b+12) long REG NA Contained DefList: { N376.t283. LCL_VAR } N380 ( 1, 2) [000284] ------------ * CNS_INT byte 1 REG NA Interval 94: byte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N376.t283. LCL_VAR; N380.t284. CNS_INT } N382 ( 6, 6) [000286] ------------ * STOREIND byte REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N384 ( 3, 12) [000287] H----------- * CNS_INT(h) long 0x1021dd928 ftn REG NA Interval 95: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N384.t287. CNS_INT } N386 ( 6, 14) [000288] ------------ * IND int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> Interval 96: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N386.t288. IND } N388 ( 7, 15) [000289] ------------ * RETURNTRAP int REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1> BB02 regmask=[x1] minReg=1> BB02 regmask=[x2] minReg=1> BB02 regmask=[x3] minReg=1> BB02 regmask=[x4] minReg=1> BB02 regmask=[x5] minReg=1> BB02 regmask=[x6] minReg=1> BB02 regmask=[x7] minReg=1> BB02 regmask=[x8] minReg=1> BB02 regmask=[x9] minReg=1> BB02 regmask=[x10] minReg=1> BB02 regmask=[x11] minReg=1> BB02 regmask=[x12] minReg=1> BB02 regmask=[x13] minReg=1> BB02 regmask=[x14] minReg=1> BB02 regmask=[x15] minReg=1> BB02 regmask=[xip0] minReg=1> BB02 regmask=[xip1] minReg=1> BB02 regmask=[lr] minReg=1> BB02 regmask=[d0] minReg=1> BB02 regmask=[d1] minReg=1> BB02 regmask=[d2] minReg=1> BB02 regmask=[d3] minReg=1> BB02 regmask=[d4] minReg=1> BB02 regmask=[d5] minReg=1> BB02 regmask=[d6] minReg=1> BB02 regmask=[d7] minReg=1> BB02 regmask=[d16] minReg=1> BB02 regmask=[d17] minReg=1> BB02 regmask=[d18] minReg=1> BB02 regmask=[d19] minReg=1> BB02 regmask=[d20] minReg=1> BB02 regmask=[d21] minReg=1> BB02 regmask=[d22] minReg=1> BB02 regmask=[d23] minReg=1> BB02 regmask=[d24] minReg=1> BB02 regmask=[d25] minReg=1> BB02 regmask=[d26] minReg=1> BB02 regmask=[d27] minReg=1> BB02 regmask=[d28] minReg=1> BB02 regmask=[d29] minReg=1> BB02 regmask=[d30] minReg=1> BB02 regmask=[d31] minReg=1> DefList: { } N390 ( 1, 1) [000179] ------------ * NO_OP void REG NA DefList: { } N392 ( 1, 1) [000180] ------------ * NO_OP void REG NA DefList: { } N394 ( 1, 1) [000181] ------------ * NO_OP void REG NA DefList: { } N396 ( 1, 1) [000182] ------------ * NO_OP void REG NA DefList: { } N398 ( 1, 1) [000183] ------------ * NO_OP void REG NA DefList: { } N400 ( 1, 1) [000184] ------------ * NO_OP void REG NA DefList: { } N402 ( 1, 1) [000185] ------------ * NO_OP void REG NA DefList: { } N404 ( 1, 1) [000186] ------------ * NO_OP void REG NA DefList: { } N406 ( 1, 1) [000187] ------------ * NO_OP void REG NA DefList: { } N408 ( 1, 1) [000188] ------------ * NO_OP void REG NA DefList: { } N410 ( 1, 1) [000189] ------------ * NO_OP void REG NA DefList: { } N412 ( 1, 1) [000190] ------------ * NO_OP void REG NA DefList: { } N414 ( 1, 1) [000191] ------------ * NO_OP void REG NA DefList: { } N416 ( 1, 1) [000192] ------------ * NO_OP void REG NA DefList: { } N418 ( 1, 1) [000193] ------------ * NO_OP void REG NA DefList: { } N420 ( 1, 1) [000194] ------------ * NO_OP void REG NA DefList: { } N422 ( 1, 1) [000195] ------------ * NO_OP void REG NA DefList: { } N424 ( 1, 1) [000196] ------------ * NO_OP void REG NA DefList: { } N426 ( 1, 1) [000197] ------------ * NO_OP void REG NA DefList: { } N428 ( 1, 1) [000198] ------------ * NO_OP void REG NA DefList: { } N430 ( 1, 1) [000199] ------------ * NO_OP void REG NA DefList: { } N432 ( 1, 1) [000200] ------------ * NO_OP void REG NA DefList: { } N434 ( 1, 1) [000201] ------------ * NO_OP void REG NA DefList: { } N436 ( 1, 1) [000202] ------------ * NO_OP void REG NA DefList: { } N438 ( 1, 1) [000203] ------------ * NO_OP void REG NA DefList: { } N440 ( 1, 1) [000204] ------------ * NO_OP void REG NA DefList: { } N442 ( 1, 1) [000205] ------------ * NO_OP void REG NA DefList: { } N444 ( 1, 1) [000206] ------------ * NO_OP void REG NA DefList: { } N446 ( 1, 1) [000207] ------------ * NO_OP void REG NA DefList: { } N448 ( 1, 1) [000208] ------------ * NO_OP void REG NA DefList: { } N450 ( 1, 1) [000209] ------------ * NO_OP void REG NA DefList: { } N452 ( 1, 1) [000210] ------------ * NO_OP void REG NA DefList: { } N454 ( 1, 1) [000211] ------------ * NO_OP void REG NA DefList: { } N456 ( 1, 1) [000212] ------------ * NO_OP void REG NA NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N460 ( 3, 2) [000290] ------------ * LCL_VAR long V38 FramesRoot NA REG NA Interval 97: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N460.t290. LCL_VAR } N462 ( 4, 3) [000291] -c---------- * LEA(b+16) long REG NA Contained DefList: { N460.t290. LCL_VAR } N464 ( 3, 4) [000292] ------------ * LCL_FLD byref V39 PInvokeFrame [+16] NA REG NA Interval 98: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD BB03 regmask=[x0-xip0 x19-x28] minReg=1> DefList: { N460.t290. LCL_VAR; N464.t292. LCL_FLD } N466 ( 8, 8) [000293] ------------ * STOREIND long REG NA BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> DefList: { } N468 ( 0, 0) [000214] ------------ * RETURN void REG NA Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: long RefPositions {#1@3 #3@4} physReg:NA Preferences=[x0] Interval 1: long RefPositions {#5@5 #12@10} physReg:NA Preferences=[x0] Interval 2: long RefPositions {#6@7 #8@8} physReg:NA Preferences=[x1] Interval 3: long RefPositions {#10@9 #14@10} physReg:NA Preferences=[x1] Interval 4: long RefPositions {#35@11 #36@12} physReg:NA Preferences=[x0] Interval 5: long RefPositions {#37@15 #38@16} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: long RefPositions {#39@19 #40@20} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 7: long RefPositions {#41@23 #43@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 8: byref RefPositions {#42@27 #44@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 9: int (constant) RefPositions {#46@35 #47@36} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: int RefPositions {#48@41 #49@42} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int RefPositions {#50@43 #51@46} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 12: int RefPositions {#52@47 #53@48} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: int RefPositions {#54@55 #55@56} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 14: int RefPositions {#56@57 #57@60} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 15: int RefPositions {#58@61 #59@62} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 16: int RefPositions {#60@69 #61@70} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 17: int RefPositions {#62@71 #63@74} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 18: int RefPositions {#64@75 #65@76} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 19: int RefPositions {#66@83 #67@84} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 20: int RefPositions {#68@85 #69@88} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: int RefPositions {#70@89 #71@90} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 22: int RefPositions {#72@97 #73@98} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 23: int RefPositions {#74@99 #75@102} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 24: int RefPositions {#76@103 #77@104} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 25: int RefPositions {#78@111 #79@112} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 26: int RefPositions {#80@113 #81@116} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: int RefPositions {#82@117 #83@118} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 28: int RefPositions {#84@125 #85@126} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 29: int RefPositions {#86@127 #87@130} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 30: int RefPositions {#88@131 #89@132} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 31: int RefPositions {#90@139 #91@140} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 32: int RefPositions {#92@141 #93@144} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 33: int RefPositions {#94@145 #95@146} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 34: int RefPositions {#96@153 #97@154} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 35: int RefPositions {#98@155 #99@158} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 36: int RefPositions {#100@159 #101@160} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 37: int RefPositions {#102@167 #103@168} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: int RefPositions {#104@169 #105@172} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 39: int RefPositions {#106@173 #107@174} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: int RefPositions {#108@181 #109@182} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: int RefPositions {#110@183 #111@186} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: int RefPositions {#112@187 #113@188} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 43: int RefPositions {#114@195 #115@196} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 44: int RefPositions {#116@197 #117@200} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: int RefPositions {#118@201 #119@202} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: int RefPositions {#120@209 #121@210} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: int RefPositions {#122@211 #123@214} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: int RefPositions {#124@215 #125@216} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: int RefPositions {#126@223 #127@224} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: int RefPositions {#128@225 #129@228} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 51: int RefPositions {#130@229 #131@230} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: int RefPositions {#132@237 #133@238} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: int RefPositions {#134@239 #135@242} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 54: int RefPositions {#136@243 #137@244} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: int RefPositions {#138@251 #139@252} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 56: int RefPositions {#140@253 #141@256} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: int RefPositions {#142@257 #143@258} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 58: long RefPositions {#144@265 #145@266} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 59: long RefPositions {#146@271 #150@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: int (constant) RefPositions {#147@273 #148@274} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: long RefPositions {#149@275 #151@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: long RefPositions {#152@279 #153@280} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 63: long RefPositions {#154@281 #155@282} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: int RefPositions {#156@285 #157@286} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: int RefPositions {#158@289 #159@290} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: int RefPositions {#160@293 #161@294} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 67: int RefPositions {#162@297 #163@298} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: int RefPositions {#164@301 #165@302} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 69: int RefPositions {#166@305 #167@306} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: int RefPositions {#168@309 #169@310} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: int RefPositions {#170@313 #171@314} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: long RefPositions {#172@317 #173@318} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: int RefPositions {#174@321 #176@322} physReg:NA Preferences=[x0] Interval 74: int RefPositions {#178@323 #223@374} physReg:NA Preferences=[x0] Interval 75: int RefPositions {#179@325 #181@326} physReg:NA Preferences=[x1] Interval 76: int RefPositions {#183@327 #225@374} physReg:NA Preferences=[x1] Interval 77: int RefPositions {#184@329 #186@330} physReg:NA Preferences=[x2] Interval 78: int RefPositions {#188@331 #227@374} physReg:NA Preferences=[x2] Interval 79: int RefPositions {#189@333 #191@334} physReg:NA Preferences=[x3] Interval 80: int RefPositions {#193@335 #229@374} physReg:NA Preferences=[x3] Interval 81: int RefPositions {#194@337 #196@338} physReg:NA Preferences=[x4] Interval 82: int RefPositions {#198@339 #231@374} physReg:NA Preferences=[x4] Interval 83: int RefPositions {#199@341 #201@342} physReg:NA Preferences=[x5] Interval 84: int RefPositions {#203@343 #233@374} physReg:NA Preferences=[x5] Interval 85: int RefPositions {#204@345 #206@346} physReg:NA Preferences=[x6] Interval 86: int RefPositions {#208@347 #235@374} physReg:NA Preferences=[x6] Interval 87: int RefPositions {#209@349 #211@350} physReg:NA Preferences=[x7] Interval 88: int RefPositions {#213@351 #237@374} physReg:NA Preferences=[x7] Interval 89: long RefPositions {#214@353 #215@354} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 90: long RefPositions {#216@357 #217@358} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: long RefPositions {#218@361 #219@366} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: long RefPositions {#221@371 #238@374} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: long RefPositions {#259@377 #261@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: byte (constant) RefPositions {#260@381 #262@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: long (constant) RefPositions {#263@385 #264@386} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: int RefPositions {#265@387 #266@388} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 97: long RefPositions {#311@461 #313@466} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: byref RefPositions {#312@465 #314@466} physReg:NA Preferences=[x0-xip0 x19-x28] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ LCL_FLD_ADDR BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x0] minReg=1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed> PHYSREG BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x0] minReg=1 last> BB01 regmask=[x1] minReg=1 last> BB01 regmask=[x2] minReg=1 last> BB01 regmask=[x3] minReg=1 last> BB01 regmask=[x4] minReg=1 last> BB01 regmask=[x5] minReg=1 last> BB01 regmask=[x6] minReg=1 last> BB01 regmask=[x7] minReg=1 last> BB01 regmask=[x8] minReg=1 last> BB01 regmask=[x9] minReg=1 last> BB01 regmask=[x10] minReg=1 last> BB01 regmask=[x11] minReg=1 last> BB01 regmask=[x12] minReg=1 last> BB01 regmask=[x13] minReg=1 last> BB01 regmask=[x14] minReg=1 last> BB01 regmask=[x15] minReg=1 last> BB01 regmask=[xip0] minReg=1 last> BB01 regmask=[xip1] minReg=1 last> BB01 regmask=[lr] minReg=1 last> BB01 regmask=[x0] minReg=1> CALL BB01 regmask=[x0] minReg=1 fixed> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1> LCL_FLD_ADDR BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x0] minReg=1> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed> LCL_VAR BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> PUTARG_REG BB02 regmask=[x1] minReg=1 fixed> LCL_VAR BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> PUTARG_REG BB02 regmask=[x2] minReg=1 fixed> LCL_VAR BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> PUTARG_REG BB02 regmask=[x3] minReg=1 fixed> LCL_VAR BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> PUTARG_REG BB02 regmask=[x4] minReg=1 fixed> LCL_VAR BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> PUTARG_REG BB02 regmask=[x5] minReg=1 fixed> LCL_VAR BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> PUTARG_REG BB02 regmask=[x6] minReg=1 fixed> LCL_VAR BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> PUTARG_REG BB02 regmask=[x7] minReg=1 fixed> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LABEL BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> BB02 regmask=[d0] minReg=1 last> BB02 regmask=[d1] minReg=1 last> BB02 regmask=[d2] minReg=1 last> BB02 regmask=[d3] minReg=1 last> BB02 regmask=[d4] minReg=1 last> BB02 regmask=[d5] minReg=1 last> BB02 regmask=[d6] minReg=1 last> BB02 regmask=[d7] minReg=1 last> BB02 regmask=[d16] minReg=1 last> BB02 regmask=[d17] minReg=1 last> BB02 regmask=[d18] minReg=1 last> BB02 regmask=[d19] minReg=1 last> BB02 regmask=[d20] minReg=1 last> BB02 regmask=[d21] minReg=1 last> BB02 regmask=[d22] minReg=1 last> BB02 regmask=[d23] minReg=1 last> BB02 regmask=[d24] minReg=1 last> BB02 regmask=[d25] minReg=1 last> BB02 regmask=[d26] minReg=1 last> BB02 regmask=[d27] minReg=1 last> BB02 regmask=[d28] minReg=1 last> BB02 regmask=[d29] minReg=1 last> BB02 regmask=[d30] minReg=1 last> BB02 regmask=[d31] minReg=1 last> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1> LCL_FLD BB03 regmask=[x0-xip0 x19-x28] minReg=1> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: BB01 [???..???), preds={} succs={BB02} ===== N002. LCL_FLD_ADDR V39 PInvokeFrame [+8] NA Def:(#1) N004. PUTARG_REG Use:(#3) Fixed:x0(#2) * Def:(#5) x0 N006. PHYSREG x12 Def:(#6) N008. PUTARG_REG Use:(#8) Fixed:x1(#7) * Def:(#10) x1 N010. CALL help Use:(#12) Fixed:x0(#11) * Use:(#14) Fixed:x1(#13) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Def:(#35) x0 N012. V38 MEM Use:(#36) * N014. PHYSREG sp Def:(#37) N016. V39 MEM Use:(#38) * N018. PHYSREG fp Def:(#39) N020. V39 MEM Use:(#40) * N022. V38 MEM Def:(#41) N024. LEA(b+16) N026. LCL_FLD_ADDR V39 PInvokeFrame [+8] NA Def:(#42) N028. STOREIND Use:(#43) * Use:(#44) * BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} ===== N032. IL_OFFSET IL offset: 0x0 N034. CNS_INT 0 Def:(#46) N036. V17 MEM Use:(#47) * N038. NO_OP N040. V00 MEM Def:(#48) N042. CAST Use:(#49) * Def:(#50) N044. CNS_INT 0 N046. NE Use:(#51) * Def:(#52) N048. V18 MEM Use:(#53) * N050. NO_OP N052. NO_OP N054. V01 MEM Def:(#54) N056. CAST Use:(#55) * Def:(#56) N058. CNS_INT 0 N060. NE Use:(#57) * Def:(#58) N062. V19 MEM Use:(#59) * N064. NO_OP N066. NO_OP N068. V02 MEM Def:(#60) N070. CAST Use:(#61) * Def:(#62) N072. CNS_INT 0 N074. NE Use:(#63) * Def:(#64) N076. V20 MEM Use:(#65) * N078. NO_OP N080. NO_OP N082. V03 MEM Def:(#66) N084. CAST Use:(#67) * Def:(#68) N086. CNS_INT 0 N088. NE Use:(#69) * Def:(#70) N090. V21 MEM Use:(#71) * N092. NO_OP N094. NO_OP N096. V04 MEM Def:(#72) N098. CAST Use:(#73) * Def:(#74) N100. CNS_INT 0 N102. NE Use:(#75) * Def:(#76) N104. V22 MEM Use:(#77) * N106. NO_OP N108. NO_OP N110. V05 MEM Def:(#78) N112. CAST Use:(#79) * Def:(#80) N114. CNS_INT 0 N116. NE Use:(#81) * Def:(#82) N118. V23 MEM Use:(#83) * N120. NO_OP N122. NO_OP N124. V06 MEM Def:(#84) N126. CAST Use:(#85) * Def:(#86) N128. CNS_INT 0 N130. NE Use:(#87) * Def:(#88) N132. V24 MEM Use:(#89) * N134. NO_OP N136. NO_OP N138. V07 MEM Def:(#90) N140. CAST Use:(#91) * Def:(#92) N142. CNS_INT 0 N144. NE Use:(#93) * Def:(#94) N146. V25 MEM Use:(#95) * N148. NO_OP N150. NO_OP N152. V08 MEM Def:(#96) N154. CAST Use:(#97) * Def:(#98) N156. CNS_INT 0 N158. NE Use:(#99) * Def:(#100) N160. V26 MEM Use:(#101) * N162. NO_OP N164. NO_OP N166. V09 MEM Def:(#102) N168. CAST Use:(#103) * Def:(#104) N170. CNS_INT 0 N172. NE Use:(#105) * Def:(#106) N174. V27 MEM Use:(#107) * N176. NO_OP N178. NO_OP N180. V10 MEM Def:(#108) N182. CAST Use:(#109) * Def:(#110) N184. CNS_INT 0 N186. NE Use:(#111) * Def:(#112) N188. V28 MEM Use:(#113) * N190. NO_OP N192. NO_OP N194. V11 MEM Def:(#114) N196. CAST Use:(#115) * Def:(#116) N198. CNS_INT 0 N200. NE Use:(#117) * Def:(#118) N202. V29 MEM Use:(#119) * N204. NO_OP N206. NO_OP N208. V12 MEM Def:(#120) N210. CAST Use:(#121) * Def:(#122) N212. CNS_INT 0 N214. NE Use:(#123) * Def:(#124) N216. V30 MEM Use:(#125) * N218. NO_OP N220. NO_OP N222. V13 MEM Def:(#126) N224. CAST Use:(#127) * Def:(#128) N226. CNS_INT 0 N228. NE Use:(#129) * Def:(#130) N230. V31 MEM Use:(#131) * N232. NO_OP N234. NO_OP N236. V14 MEM Def:(#132) N238. CAST Use:(#133) * Def:(#134) N240. CNS_INT 0 N242. NE Use:(#135) * Def:(#136) N244. V32 MEM Use:(#137) * N246. NO_OP N248. NO_OP N250. V15 MEM Def:(#138) N252. CAST Use:(#139) * Def:(#140) N254. CNS_INT 0 N256. NE Use:(#141) * Def:(#142) N258. V33 MEM Use:(#143) * N260. NO_OP N262. NO_OP N264. V16 MEM Def:(#144) N266. V34 MEM Use:(#145) * N268. NO_OP N270. V36 MEM Def:(#146) N272. CNS_INT 72 Def:(#147) N274. CAST Use:(#148) * Def:(#149) N276. LEA(b+(i*1)+0) N278. IND Use:(#150) * Use:(#151) * Def:(#152) N280. IND Use:(#153) * Def:(#154) N282. V37 MEM Use:(#155) * N284. V26 MEM Def:(#156) N286. PUTARG_STK [+0x00] Use:(#157) * N288. V27 MEM Def:(#158) N290. PUTARG_STK [+0x04] Use:(#159) * N292. V28 MEM Def:(#160) N294. PUTARG_STK [+0x08] Use:(#161) * N296. V29 MEM Def:(#162) N298. PUTARG_STK [+0x0c] Use:(#163) * N300. V30 MEM Def:(#164) N302. PUTARG_STK [+0x10] Use:(#165) * N304. V31 MEM Def:(#166) N306. PUTARG_STK [+0x14] Use:(#167) * N308. V32 MEM Def:(#168) N310. PUTARG_STK [+0x18] Use:(#169) * N312. V33 MEM Def:(#170) N314. PUTARG_STK [+0x1c] Use:(#171) * N316. V34 MEM Def:(#172) N318. PUTARG_STK [+0x20] Use:(#173) * N320. V18 MEM Def:(#174) N322. PUTARG_REG Use:(#176) Fixed:x0(#175) * Def:(#178) x0 N324. V19 MEM Def:(#179) N326. PUTARG_REG Use:(#181) Fixed:x1(#180) * Def:(#183) x1 N328. V20 MEM Def:(#184) N330. PUTARG_REG Use:(#186) Fixed:x2(#185) * Def:(#188) x2 N332. V21 MEM Def:(#189) N334. PUTARG_REG Use:(#191) Fixed:x3(#190) * Def:(#193) x3 N336. V22 MEM Def:(#194) N338. PUTARG_REG Use:(#196) Fixed:x4(#195) * Def:(#198) x4 N340. V23 MEM Def:(#199) N342. PUTARG_REG Use:(#201) Fixed:x5(#200) * Def:(#203) x5 N344. V24 MEM Def:(#204) N346. PUTARG_REG Use:(#206) Fixed:x6(#205) * Def:(#208) x6 N348. V25 MEM Def:(#209) N350. PUTARG_REG Use:(#211) Fixed:x7(#210) * Def:(#213) x7 N352. V36 MEM Def:(#214) N354. V39 MEM Use:(#215) * N356. LABEL Def:(#216) N358. V39 MEM Use:(#217) * N360. V38 MEM Def:(#218) N362. LEA(b+12) N364. CNS_INT 0 N366. STOREIND Use:(#219) * N368. START_PREEMPTGC N370. V37 MEM N372. PINVOKE_PROLOG N374. CALL ind unman popargs N376. V38 MEM N378. LEA(b+12) N380. CNS_INT 1 N382. STOREIND N384. CNS_INT(h) 0x1021dd928 ftn N386. IND N388. RETURNTRAP N390. NO_OP N392. NO_OP N394. NO_OP N396. NO_OP N398. NO_OP N400. NO_OP N402. NO_OP N404. NO_OP N406. NO_OP N408. NO_OP N410. NO_OP N412. NO_OP N414. NO_OP N416. NO_OP N418. NO_OP N420. NO_OP N422. NO_OP N424. NO_OP N426. NO_OP N428. NO_OP N430. NO_OP N432. NO_OP N434. NO_OP N436. NO_OP N438. NO_OP N440. NO_OP N442. NO_OP N444. NO_OP N446. NO_OP N448. NO_OP N450. NO_OP N452. NO_OP N454. NO_OP N456. NO_OP N460. V38 MEM N462. LEA(b+16) N464. V39 MEM N466. STOREIND N468. RETURN Linear scan intervals after buildIntervals: Interval 0: long RefPositions {#1@3 #3@4} physReg:NA Preferences=[x0] Interval 1: long RefPositions {#5@5 #12@10} physReg:NA Preferences=[x0] Interval 2: long RefPositions {#6@7 #8@8} physReg:NA Preferences=[x1] Interval 3: long RefPositions {#10@9 #14@10} physReg:NA Preferences=[x1] Interval 4: long RefPositions {#35@11 #36@12} physReg:NA Preferences=[x0] Interval 5: long RefPositions {#37@15 #38@16} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: long RefPositions {#39@19 #40@20} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 7: long RefPositions {#41@23 #43@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 8: byref RefPositions {#42@27 #44@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 9: int (constant) RefPositions {#46@35 #47@36} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: int RefPositions {#48@41 #49@42} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int RefPositions {#50@43 #51@46} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 12: int RefPositions {#52@47 #53@48} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: int RefPositions {#54@55 #55@56} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 14: int RefPositions {#56@57 #57@60} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 15: int RefPositions {#58@61 #59@62} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 16: int RefPositions {#60@69 #61@70} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 17: int RefPositions {#62@71 #63@74} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 18: int RefPositions {#64@75 #65@76} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 19: int RefPositions {#66@83 #67@84} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 20: int RefPositions {#68@85 #69@88} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: int RefPositions {#70@89 #71@90} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 22: int RefPositions {#72@97 #73@98} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 23: int RefPositions {#74@99 #75@102} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 24: int RefPositions {#76@103 #77@104} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 25: int RefPositions {#78@111 #79@112} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 26: int RefPositions {#80@113 #81@116} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: int RefPositions {#82@117 #83@118} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 28: int RefPositions {#84@125 #85@126} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 29: int RefPositions {#86@127 #87@130} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 30: int RefPositions {#88@131 #89@132} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 31: int RefPositions {#90@139 #91@140} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 32: int RefPositions {#92@141 #93@144} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 33: int RefPositions {#94@145 #95@146} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 34: int RefPositions {#96@153 #97@154} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 35: int RefPositions {#98@155 #99@158} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 36: int RefPositions {#100@159 #101@160} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 37: int RefPositions {#102@167 #103@168} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: int RefPositions {#104@169 #105@172} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 39: int RefPositions {#106@173 #107@174} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: int RefPositions {#108@181 #109@182} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: int RefPositions {#110@183 #111@186} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: int RefPositions {#112@187 #113@188} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 43: int RefPositions {#114@195 #115@196} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 44: int RefPositions {#116@197 #117@200} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: int RefPositions {#118@201 #119@202} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: int RefPositions {#120@209 #121@210} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: int RefPositions {#122@211 #123@214} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: int RefPositions {#124@215 #125@216} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: int RefPositions {#126@223 #127@224} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: int RefPositions {#128@225 #129@228} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 51: int RefPositions {#130@229 #131@230} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: int RefPositions {#132@237 #133@238} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: int RefPositions {#134@239 #135@242} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 54: int RefPositions {#136@243 #137@244} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: int RefPositions {#138@251 #139@252} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 56: int RefPositions {#140@253 #141@256} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: int RefPositions {#142@257 #143@258} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 58: long RefPositions {#144@265 #145@266} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 59: long RefPositions {#146@271 #150@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: int (constant) RefPositions {#147@273 #148@274} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: long RefPositions {#149@275 #151@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: long RefPositions {#152@279 #153@280} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 63: long RefPositions {#154@281 #155@282} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: int RefPositions {#156@285 #157@286} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: int RefPositions {#158@289 #159@290} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: int RefPositions {#160@293 #161@294} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 67: int RefPositions {#162@297 #163@298} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: int RefPositions {#164@301 #165@302} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 69: int RefPositions {#166@305 #167@306} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: int RefPositions {#168@309 #169@310} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: int RefPositions {#170@313 #171@314} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: long RefPositions {#172@317 #173@318} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: int RefPositions {#174@321 #176@322} physReg:NA Preferences=[x0] Interval 74: int RefPositions {#178@323 #223@374} physReg:NA Preferences=[x0] Interval 75: int RefPositions {#179@325 #181@326} physReg:NA Preferences=[x1] Interval 76: int RefPositions {#183@327 #225@374} physReg:NA Preferences=[x1] Interval 77: int RefPositions {#184@329 #186@330} physReg:NA Preferences=[x2] Interval 78: int RefPositions {#188@331 #227@374} physReg:NA Preferences=[x2] Interval 79: int RefPositions {#189@333 #191@334} physReg:NA Preferences=[x3] Interval 80: int RefPositions {#193@335 #229@374} physReg:NA Preferences=[x3] Interval 81: int RefPositions {#194@337 #196@338} physReg:NA Preferences=[x4] Interval 82: int RefPositions {#198@339 #231@374} physReg:NA Preferences=[x4] Interval 83: int RefPositions {#199@341 #201@342} physReg:NA Preferences=[x5] Interval 84: int RefPositions {#203@343 #233@374} physReg:NA Preferences=[x5] Interval 85: int RefPositions {#204@345 #206@346} physReg:NA Preferences=[x6] Interval 86: int RefPositions {#208@347 #235@374} physReg:NA Preferences=[x6] Interval 87: int RefPositions {#209@349 #211@350} physReg:NA Preferences=[x7] Interval 88: int RefPositions {#213@351 #237@374} physReg:NA Preferences=[x7] Interval 89: long RefPositions {#214@353 #215@354} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 90: long RefPositions {#216@357 #217@358} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: long RefPositions {#218@361 #219@366} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: long RefPositions {#221@371 #238@374} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: long RefPositions {#259@377 #261@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: byte (constant) RefPositions {#260@381 #262@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: long (constant) RefPositions {#263@385 #264@386} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: int RefPositions {#265@387 #266@388} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 97: long RefPositions {#311@461 #313@466} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: byref RefPositions {#312@465 #314@466} physReg:NA Preferences=[x0-xip0 x19-x28] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: long RefPositions {#1@3 #3@4} physReg:NA Preferences=[x0] Interval 1: long RefPositions {#5@5 #12@10} physReg:NA Preferences=[x0] Interval 2: long RefPositions {#6@7 #8@8} physReg:NA Preferences=[x1] Interval 3: long RefPositions {#10@9 #14@10} physReg:NA Preferences=[x1] Interval 4: long RefPositions {#35@11 #36@12} physReg:NA Preferences=[x0] Interval 5: long RefPositions {#37@15 #38@16} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: long RefPositions {#39@19 #40@20} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 7: long RefPositions {#41@23 #43@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 8: byref RefPositions {#42@27 #44@28} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 9: int (constant) RefPositions {#46@35 #47@36} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: int RefPositions {#48@41 #49@42} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int RefPositions {#50@43 #51@46} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 12: int RefPositions {#52@47 #53@48} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: int RefPositions {#54@55 #55@56} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 14: int RefPositions {#56@57 #57@60} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 15: int RefPositions {#58@61 #59@62} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 16: int RefPositions {#60@69 #61@70} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 17: int RefPositions {#62@71 #63@74} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 18: int RefPositions {#64@75 #65@76} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 19: int RefPositions {#66@83 #67@84} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 20: int RefPositions {#68@85 #69@88} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: int RefPositions {#70@89 #71@90} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 22: int RefPositions {#72@97 #73@98} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 23: int RefPositions {#74@99 #75@102} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 24: int RefPositions {#76@103 #77@104} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 25: int RefPositions {#78@111 #79@112} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 26: int RefPositions {#80@113 #81@116} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: int RefPositions {#82@117 #83@118} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 28: int RefPositions {#84@125 #85@126} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 29: int RefPositions {#86@127 #87@130} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 30: int RefPositions {#88@131 #89@132} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 31: int RefPositions {#90@139 #91@140} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 32: int RefPositions {#92@141 #93@144} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 33: int RefPositions {#94@145 #95@146} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 34: int RefPositions {#96@153 #97@154} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 35: int RefPositions {#98@155 #99@158} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 36: int RefPositions {#100@159 #101@160} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 37: int RefPositions {#102@167 #103@168} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: int RefPositions {#104@169 #105@172} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 39: int RefPositions {#106@173 #107@174} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: int RefPositions {#108@181 #109@182} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: int RefPositions {#110@183 #111@186} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: int RefPositions {#112@187 #113@188} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 43: int RefPositions {#114@195 #115@196} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 44: int RefPositions {#116@197 #117@200} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: int RefPositions {#118@201 #119@202} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: int RefPositions {#120@209 #121@210} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: int RefPositions {#122@211 #123@214} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: int RefPositions {#124@215 #125@216} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: int RefPositions {#126@223 #127@224} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: int RefPositions {#128@225 #129@228} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 51: int RefPositions {#130@229 #131@230} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: int RefPositions {#132@237 #133@238} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: int RefPositions {#134@239 #135@242} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 54: int RefPositions {#136@243 #137@244} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: int RefPositions {#138@251 #139@252} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 56: int RefPositions {#140@253 #141@256} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: int RefPositions {#142@257 #143@258} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 58: long RefPositions {#144@265 #145@266} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 59: long RefPositions {#146@271 #150@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: int (constant) RefPositions {#147@273 #148@274} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: long RefPositions {#149@275 #151@278} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: long RefPositions {#152@279 #153@280} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 63: long RefPositions {#154@281 #155@282} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: int RefPositions {#156@285 #157@286} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: int RefPositions {#158@289 #159@290} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: int RefPositions {#160@293 #161@294} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 67: int RefPositions {#162@297 #163@298} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: int RefPositions {#164@301 #165@302} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 69: int RefPositions {#166@305 #167@306} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: int RefPositions {#168@309 #169@310} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: int RefPositions {#170@313 #171@314} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: long RefPositions {#172@317 #173@318} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: int RefPositions {#174@321 #176@322} physReg:NA Preferences=[x0] Interval 74: int RefPositions {#178@323 #223@374} physReg:NA Preferences=[x0] Interval 75: int RefPositions {#179@325 #181@326} physReg:NA Preferences=[x1] Interval 76: int RefPositions {#183@327 #225@374} physReg:NA Preferences=[x1] Interval 77: int RefPositions {#184@329 #186@330} physReg:NA Preferences=[x2] Interval 78: int RefPositions {#188@331 #227@374} physReg:NA Preferences=[x2] Interval 79: int RefPositions {#189@333 #191@334} physReg:NA Preferences=[x3] Interval 80: int RefPositions {#193@335 #229@374} physReg:NA Preferences=[x3] Interval 81: int RefPositions {#194@337 #196@338} physReg:NA Preferences=[x4] Interval 82: int RefPositions {#198@339 #231@374} physReg:NA Preferences=[x4] Interval 83: int RefPositions {#199@341 #201@342} physReg:NA Preferences=[x5] Interval 84: int RefPositions {#203@343 #233@374} physReg:NA Preferences=[x5] Interval 85: int RefPositions {#204@345 #206@346} physReg:NA Preferences=[x6] Interval 86: int RefPositions {#208@347 #235@374} physReg:NA Preferences=[x6] Interval 87: int RefPositions {#209@349 #211@350} physReg:NA Preferences=[x7] Interval 88: int RefPositions {#213@351 #237@374} physReg:NA Preferences=[x7] Interval 89: long RefPositions {#214@353 #215@354} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 90: long RefPositions {#216@357 #217@358} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: long RefPositions {#218@361 #219@366} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: long RefPositions {#221@371 #238@374} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: long RefPositions {#259@377 #261@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: byte (constant) RefPositions {#260@381 #262@382} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: long (constant) RefPositions {#263@385 #264@386} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: int RefPositions {#265@387 #266@388} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 97: long RefPositions {#311@461 #313@466} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: byref RefPositions {#312@465 #314@466} physReg:NA Preferences=[x0-xip0 x19-x28] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ LCL_FLD_ADDR BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x0] minReg=1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed> PHYSREG BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x0] minReg=1 last> BB01 regmask=[x1] minReg=1 last> BB01 regmask=[x2] minReg=1 last> BB01 regmask=[x3] minReg=1 last> BB01 regmask=[x4] minReg=1 last> BB01 regmask=[x5] minReg=1 last> BB01 regmask=[x6] minReg=1 last> BB01 regmask=[x7] minReg=1 last> BB01 regmask=[x8] minReg=1 last> BB01 regmask=[x9] minReg=1 last> BB01 regmask=[x10] minReg=1 last> BB01 regmask=[x11] minReg=1 last> BB01 regmask=[x12] minReg=1 last> BB01 regmask=[x13] minReg=1 last> BB01 regmask=[x14] minReg=1 last> BB01 regmask=[x15] minReg=1 last> BB01 regmask=[xip0] minReg=1 last> BB01 regmask=[xip1] minReg=1 last> BB01 regmask=[lr] minReg=1 last> BB01 regmask=[x0] minReg=1> CALL BB01 regmask=[x0] minReg=1 fixed> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> PHYSREG BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1> LCL_FLD_ADDR BB01 regmask=[x0-xip0 x19-x28] minReg=1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> NE BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x0] minReg=1> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed> LCL_VAR BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> PUTARG_REG BB02 regmask=[x1] minReg=1 fixed> LCL_VAR BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> PUTARG_REG BB02 regmask=[x2] minReg=1 fixed> LCL_VAR BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> PUTARG_REG BB02 regmask=[x3] minReg=1 fixed> LCL_VAR BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> PUTARG_REG BB02 regmask=[x4] minReg=1 fixed> LCL_VAR BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> PUTARG_REG BB02 regmask=[x5] minReg=1 fixed> LCL_VAR BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> PUTARG_REG BB02 regmask=[x6] minReg=1 fixed> LCL_VAR BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> PUTARG_REG BB02 regmask=[x7] minReg=1 fixed> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LABEL BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> BB02 regmask=[d0] minReg=1 last> BB02 regmask=[d1] minReg=1 last> BB02 regmask=[d2] minReg=1 last> BB02 regmask=[d3] minReg=1 last> BB02 regmask=[d4] minReg=1 last> BB02 regmask=[d5] minReg=1 last> BB02 regmask=[d6] minReg=1 last> BB02 regmask=[d7] minReg=1 last> BB02 regmask=[d16] minReg=1 last> BB02 regmask=[d17] minReg=1 last> BB02 regmask=[d18] minReg=1 last> BB02 regmask=[d19] minReg=1 last> BB02 regmask=[d20] minReg=1 last> BB02 regmask=[d21] minReg=1 last> BB02 regmask=[d22] minReg=1 last> BB02 regmask=[d23] minReg=1 last> BB02 regmask=[d24] minReg=1 last> BB02 regmask=[d25] minReg=1 last> BB02 regmask=[d26] minReg=1 last> BB02 regmask=[d27] minReg=1 last> BB02 regmask=[d28] minReg=1 last> BB02 regmask=[d29] minReg=1 last> BB02 regmask=[d30] minReg=1 last> BB02 regmask=[d31] minReg=1 last> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1> LCL_FLD BB03 regmask=[x0-xip0 x19-x28] minReg=1> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> BB03 regmask=[x0-xip0 x19-x28] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | | | | | | | | | | | 0.#0 BB1 PredBB0 | | | | | | | | | | | 3.#1 I0 Def Alloc x0 |I0 a| | | | | | | | | | 4.#2 x0 Fixd Keep x0 |I0 a| | | | | | | | | | 4.#3 I0 Use * Keep x0 |I0 a| | | | | | | | | | 5.#4 x0 Fixd Keep x0 | | | | | | | | | | | 5.#5 I1 Def Alloc x0 |I1 a| | | | | | | | | | 7.#6 I2 Def Alloc x1 |I1 a|I2 a| | | | | | | | | 8.#7 x1 Fixd Keep x1 |I1 a|I2 a| | | | | | | | | 8.#8 I2 Use * Keep x1 |I1 a|I2 a| | | | | | | | | 9.#9 x1 Fixd Keep x1 |I1 a| | | | | | | | | | 9.#10 I3 Def Alloc x1 |I1 a|I3 a| | | | | | | | | 10.#11 x0 Fixd Keep x0 |I1 a|I3 a| | | | | | | | | 10.#12 I1 Use * Keep x0 |I1 a|I3 a| | | | | | | | | 10.#13 x1 Fixd Keep x1 |I1 a|I3 a| | | | | | | | | 10.#14 I3 Use * Keep x1 |I1 a|I3 a| | | | | | | | | 11.#15 x0 Kill Keep x0 | | | | | | | | | | | 11.#16 x1 Kill Keep x1 | | | | | | | | | | | 11.#17 x2 Kill Keep x2 | | | | | | | | | | | 11.#18 x3 Kill Keep x3 | | | | | | | | | | | 11.#19 x4 Kill Keep x4 | | | | | | | | | | | 11.#20 x5 Kill Keep x5 | | | | | | | | | | | 11.#21 x6 Kill Keep x6 | | | | | | | | | | | 11.#22 x7 Kill Keep x7 | | | | | | | | | | | 11.#23 x8 Kill Keep x8 | | | | | | | | | | | 11.#24 x9 Kill Keep x9 | | | | | | | | | | | 11.#25 x10 Kill Keep x10 | | | | | | | | | | | 11.#26 x11 Kill Keep x11 | | | | | | | | | | | 11.#27 x12 Kill Keep x12 | | | | | | | | | | | 11.#28 x13 Kill Keep x13 | | | | | | | | | | | 11.#29 x14 Kill Keep x14 | | | | | | | | | | | 11.#30 x15 Kill Keep x15 | | | | | | | | | | | 11.#31 xip0 Kill Keep xip0 | | | | | | | | | | | 11.#32 xip1 Kill Keep xip1 | | | | | | | | | | | 11.#33 lr Kill Keep lr | | | | | | | | | | | 11.#34 x0 Fixd Keep x0 | | | | | | | | | | | 11.#35 I4 Def Alloc x0 |I4 a| | | | | | | | | | 12.#36 I4 Use * Keep x0 |I4 a| | | | | | | | | | 15.#37 I5 Def Alloc x0 |I5 a| | | | | | | | | | 16.#38 I5 Use * Keep x0 |I5 a| | | | | | | | | | 19.#39 I6 Def Alloc x0 |I6 a| | | | | | | | | | 20.#40 I6 Use * Keep x0 |I6 a| | | | | | | | | | 23.#41 I7 Def Alloc x0 |I7 a| | | | | | | | | | 27.#42 I8 Def Alloc x1 |I7 a|I8 a| | | | | | | | | 28.#43 I7 Use * Keep x0 |I7 a|I8 a| | | | | | | | | 28.#44 I8 Use * Keep x1 |I7 a|I8 a| | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 30.#45 BB2 PredBB1 | | | | | | | | | | | 35.#46 C9 Def Alloc x0 |C9 a| | | | | | | | | | 36.#47 C9 Use * Keep x0 |C9 a| | | | | | | | | | 41.#48 I10 Def Alloc x0 |I10a| | | | | | | | | | 42.#49 I10 Use * Keep x0 |I10a| | | | | | | | | | 43.#50 I11 Def Alloc x0 |I11a| | | | | | | | | | 46.#51 I11 Use * Keep x0 |I11a| | | | | | | | | | 47.#52 I12 Def Alloc x0 |I12a| | | | | | | | | | 48.#53 I12 Use * Keep x0 |I12a| | | | | | | | | | 55.#54 I13 Def Alloc x0 |I13a| | | | | | | | | | 56.#55 I13 Use * Keep x0 |I13a| | | | | | | | | | 57.#56 I14 Def Alloc x0 |I14a| | | | | | | | | | 60.#57 I14 Use * Keep x0 |I14a| | | | | | | | | | 61.#58 I15 Def Alloc x0 |I15a| | | | | | | | | | 62.#59 I15 Use * Keep x0 |I15a| | | | | | | | | | 69.#60 I16 Def Alloc x0 |I16a| | | | | | | | | | 70.#61 I16 Use * Keep x0 |I16a| | | | | | | | | | 71.#62 I17 Def Alloc x0 |I17a| | | | | | | | | | 74.#63 I17 Use * Keep x0 |I17a| | | | | | | | | | 75.#64 I18 Def Alloc x0 |I18a| | | | | | | | | | 76.#65 I18 Use * Keep x0 |I18a| | | | | | | | | | 83.#66 I19 Def Alloc x0 |I19a| | | | | | | | | | 84.#67 I19 Use * Keep x0 |I19a| | | | | | | | | | 85.#68 I20 Def Alloc x0 |I20a| | | | | | | | | | 88.#69 I20 Use * Keep x0 |I20a| | | | | | | | | | 89.#70 I21 Def Alloc x0 |I21a| | | | | | | | | | 90.#71 I21 Use * Keep x0 |I21a| | | | | | | | | | 97.#72 I22 Def Alloc x0 |I22a| | | | | | | | | | 98.#73 I22 Use * Keep x0 |I22a| | | | | | | | | | 99.#74 I23 Def Alloc x0 |I23a| | | | | | | | | | 102.#75 I23 Use * Keep x0 |I23a| | | | | | | | | | 103.#76 I24 Def Alloc x0 |I24a| | | | | | | | | | 104.#77 I24 Use * Keep x0 |I24a| | | | | | | | | | 111.#78 I25 Def Alloc x0 |I25a| | | | | | | | | | 112.#79 I25 Use * Keep x0 |I25a| | | | | | | | | | 113.#80 I26 Def Alloc x0 |I26a| | | | | | | | | | 116.#81 I26 Use * Keep x0 |I26a| | | | | | | | | | 117.#82 I27 Def Alloc x0 |I27a| | | | | | | | | | 118.#83 I27 Use * Keep x0 |I27a| | | | | | | | | | 125.#84 I28 Def Alloc x0 |I28a| | | | | | | | | | 126.#85 I28 Use * Keep x0 |I28a| | | | | | | | | | 127.#86 I29 Def Alloc x0 |I29a| | | | | | | | | | 130.#87 I29 Use * Keep x0 |I29a| | | | | | | | | | 131.#88 I30 Def Alloc x0 |I30a| | | | | | | | | | 132.#89 I30 Use * Keep x0 |I30a| | | | | | | | | | 139.#90 I31 Def Alloc x0 |I31a| | | | | | | | | | 140.#91 I31 Use * Keep x0 |I31a| | | | | | | | | | 141.#92 I32 Def Alloc x0 |I32a| | | | | | | | | | 144.#93 I32 Use * Keep x0 |I32a| | | | | | | | | | 145.#94 I33 Def Alloc x0 |I33a| | | | | | | | | | 146.#95 I33 Use * Keep x0 |I33a| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 153.#96 I34 Def Alloc x0 |I34a| | | | | | | | | | 154.#97 I34 Use * Keep x0 |I34a| | | | | | | | | | 155.#98 I35 Def Alloc x0 |I35a| | | | | | | | | | 158.#99 I35 Use * Keep x0 |I35a| | | | | | | | | | 159.#100 I36 Def Alloc x0 |I36a| | | | | | | | | | 160.#101 I36 Use * Keep x0 |I36a| | | | | | | | | | 167.#102 I37 Def Alloc x0 |I37a| | | | | | | | | | 168.#103 I37 Use * Keep x0 |I37a| | | | | | | | | | 169.#104 I38 Def Alloc x0 |I38a| | | | | | | | | | 172.#105 I38 Use * Keep x0 |I38a| | | | | | | | | | 173.#106 I39 Def Alloc x0 |I39a| | | | | | | | | | 174.#107 I39 Use * Keep x0 |I39a| | | | | | | | | | 181.#108 I40 Def Alloc x0 |I40a| | | | | | | | | | 182.#109 I40 Use * Keep x0 |I40a| | | | | | | | | | 183.#110 I41 Def Alloc x0 |I41a| | | | | | | | | | 186.#111 I41 Use * Keep x0 |I41a| | | | | | | | | | 187.#112 I42 Def Alloc x0 |I42a| | | | | | | | | | 188.#113 I42 Use * Keep x0 |I42a| | | | | | | | | | 195.#114 I43 Def Alloc x0 |I43a| | | | | | | | | | 196.#115 I43 Use * Keep x0 |I43a| | | | | | | | | | 197.#116 I44 Def Alloc x0 |I44a| | | | | | | | | | 200.#117 I44 Use * Keep x0 |I44a| | | | | | | | | | 201.#118 I45 Def Alloc x0 |I45a| | | | | | | | | | 202.#119 I45 Use * Keep x0 |I45a| | | | | | | | | | 209.#120 I46 Def Alloc x0 |I46a| | | | | | | | | | 210.#121 I46 Use * Keep x0 |I46a| | | | | | | | | | 211.#122 I47 Def Alloc x0 |I47a| | | | | | | | | | 214.#123 I47 Use * Keep x0 |I47a| | | | | | | | | | 215.#124 I48 Def Alloc x0 |I48a| | | | | | | | | | 216.#125 I48 Use * Keep x0 |I48a| | | | | | | | | | 223.#126 I49 Def Alloc x0 |I49a| | | | | | | | | | 224.#127 I49 Use * Keep x0 |I49a| | | | | | | | | | 225.#128 I50 Def Alloc x0 |I50a| | | | | | | | | | 228.#129 I50 Use * Keep x0 |I50a| | | | | | | | | | 229.#130 I51 Def Alloc x0 |I51a| | | | | | | | | | 230.#131 I51 Use * Keep x0 |I51a| | | | | | | | | | 237.#132 I52 Def Alloc x0 |I52a| | | | | | | | | | 238.#133 I52 Use * Keep x0 |I52a| | | | | | | | | | 239.#134 I53 Def Alloc x0 |I53a| | | | | | | | | | 242.#135 I53 Use * Keep x0 |I53a| | | | | | | | | | 243.#136 I54 Def Alloc x0 |I54a| | | | | | | | | | 244.#137 I54 Use * Keep x0 |I54a| | | | | | | | | | 251.#138 I55 Def Alloc x0 |I55a| | | | | | | | | | 252.#139 I55 Use * Keep x0 |I55a| | | | | | | | | | 253.#140 I56 Def Alloc x0 |I56a| | | | | | | | | | 256.#141 I56 Use * Keep x0 |I56a| | | | | | | | | | 257.#142 I57 Def Alloc x0 |I57a| | | | | | | | | | 258.#143 I57 Use * Keep x0 |I57a| | | | | | | | | | 265.#144 I58 Def Alloc x0 |I58a| | | | | | | | | | 266.#145 I58 Use * Keep x0 |I58a| | | | | | | | | | 271.#146 I59 Def Alloc x0 |I59a| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 273.#147 C60 Def Alloc x1 |I59a|C60a| | | | | | | | | 274.#148 C60 Use * Keep x1 |I59a|C60a| | | | | | | | | 275.#149 I61 Def Alloc x1 |I59a|I61a| | | | | | | | | 278.#150 I59 Use * Keep x0 |I59a|I61a| | | | | | | | | 278.#151 I61 Use * Keep x1 |I59a|I61a| | | | | | | | | 279.#152 I62 Def Alloc x0 |I62a| | | | | | | | | | 280.#153 I62 Use * Keep x0 |I62a| | | | | | | | | | 281.#154 I63 Def Alloc x0 |I63a| | | | | | | | | | 282.#155 I63 Use * Keep x0 |I63a| | | | | | | | | | 285.#156 I64 Def Alloc x0 |I64a| | | | | | | | | | 286.#157 I64 Use * Keep x0 |I64a| | | | | | | | | | 289.#158 I65 Def Alloc x0 |I65a| | | | | | | | | | 290.#159 I65 Use * Keep x0 |I65a| | | | | | | | | | 293.#160 I66 Def Alloc x0 |I66a| | | | | | | | | | 294.#161 I66 Use * Keep x0 |I66a| | | | | | | | | | 297.#162 I67 Def Alloc x0 |I67a| | | | | | | | | | 298.#163 I67 Use * Keep x0 |I67a| | | | | | | | | | 301.#164 I68 Def Alloc x0 |I68a| | | | | | | | | | 302.#165 I68 Use * Keep x0 |I68a| | | | | | | | | | 305.#166 I69 Def Alloc x0 |I69a| | | | | | | | | | 306.#167 I69 Use * Keep x0 |I69a| | | | | | | | | | 309.#168 I70 Def Alloc x0 |I70a| | | | | | | | | | 310.#169 I70 Use * Keep x0 |I70a| | | | | | | | | | 313.#170 I71 Def Alloc x0 |I71a| | | | | | | | | | 314.#171 I71 Use * Keep x0 |I71a| | | | | | | | | | 317.#172 I72 Def Alloc x0 |I72a| | | | | | | | | | 318.#173 I72 Use * Keep x0 |I72a| | | | | | | | | | 321.#174 I73 Def Alloc x0 |I73a| | | | | | | | | | 322.#175 x0 Fixd Keep x0 |I73a| | | | | | | | | | 322.#176 I73 Use * Keep x0 |I73a| | | | | | | | | | 323.#177 x0 Fixd Keep x0 | | | | | | | | | | | 323.#178 I74 Def Alloc x0 |I74a| | | | | | | | | | 325.#179 I75 Def Alloc x1 |I74a|I75a| | | | | | | | | 326.#180 x1 Fixd Keep x1 |I74a|I75a| | | | | | | | | 326.#181 I75 Use * Keep x1 |I74a|I75a| | | | | | | | | 327.#182 x1 Fixd Keep x1 |I74a| | | | | | | | | | 327.#183 I76 Def Alloc x1 |I74a|I76a| | | | | | | | | 329.#184 I77 Def Alloc x2 |I74a|I76a|I77a| | | | | | | | 330.#185 x2 Fixd Keep x2 |I74a|I76a|I77a| | | | | | | | 330.#186 I77 Use * Keep x2 |I74a|I76a|I77a| | | | | | | | 331.#187 x2 Fixd Keep x2 |I74a|I76a| | | | | | | | | 331.#188 I78 Def Alloc x2 |I74a|I76a|I78a| | | | | | | | 333.#189 I79 Def Alloc x3 |I74a|I76a|I78a|I79a| | | | | | | 334.#190 x3 Fixd Keep x3 |I74a|I76a|I78a|I79a| | | | | | | 334.#191 I79 Use * Keep x3 |I74a|I76a|I78a|I79a| | | | | | | 335.#192 x3 Fixd Keep x3 |I74a|I76a|I78a| | | | | | | | 335.#193 I80 Def Alloc x3 |I74a|I76a|I78a|I80a| | | | | | | 337.#194 I81 Def Alloc x4 |I74a|I76a|I78a|I80a|I81a| | | | | | 338.#195 x4 Fixd Keep x4 |I74a|I76a|I78a|I80a|I81a| | | | | | 338.#196 I81 Use * Keep x4 |I74a|I76a|I78a|I80a|I81a| | | | | | 339.#197 x4 Fixd Keep x4 |I74a|I76a|I78a|I80a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 339.#198 I82 Def Alloc x4 |I74a|I76a|I78a|I80a|I82a| | | | | | 341.#199 I83 Def Alloc x5 |I74a|I76a|I78a|I80a|I82a|I83a| | | | | 342.#200 x5 Fixd Keep x5 |I74a|I76a|I78a|I80a|I82a|I83a| | | | | 342.#201 I83 Use * Keep x5 |I74a|I76a|I78a|I80a|I82a|I83a| | | | | 343.#202 x5 Fixd Keep x5 |I74a|I76a|I78a|I80a|I82a| | | | | | 343.#203 I84 Def Alloc x5 |I74a|I76a|I78a|I80a|I82a|I84a| | | | | 345.#204 I85 Def Alloc x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85a| | | | 346.#205 x6 Fixd Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85a| | | | 346.#206 I85 Use * Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85a| | | | 347.#207 x6 Fixd Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a| | | | | 347.#208 I86 Def Alloc x6 |I74a|I76a|I78a|I80a|I82a|I84a|I86a| | | | 349.#209 I87 Def Alloc x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87a| | | 350.#210 x7 Fixd Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87a| | | 350.#211 I87 Use * Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87a| | | 351.#212 x7 Fixd Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a| | | | 351.#213 I88 Def Alloc x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a| | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 353.#214 I89 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I89a| | | 354.#215 I89 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I89a| | | 357.#216 I90 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I90a| | | 358.#217 I90 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I90a| | | 361.#218 I91 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I91a| | | 366.#219 I91 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I91a| | | 369.#220 KlGC None |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a| | | | 371.#221 I92 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#222 x0 Fixd Keep x0 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#223 I74 Use * Keep x0 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#224 x1 Fixd Keep x1 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#225 I76 Use * Keep x1 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#226 x2 Fixd Keep x2 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#227 I78 Use * Keep x2 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#228 x3 Fixd Keep x3 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#229 I80 Use * Keep x3 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#230 x4 Fixd Keep x4 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#231 I82 Use * Keep x4 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#232 x5 Fixd Keep x5 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#233 I84 Use * Keep x5 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#234 x6 Fixd Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#235 I86 Use * Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#236 x7 Fixd Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#237 I88 Use * Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#238 I92 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 375.#239 x0 Kill Keep x0 | | | | | | | | | | | | 375.#240 x1 Kill Keep x1 | | | | | | | | | | | | 375.#241 x2 Kill Keep x2 | | | | | | | | | | | | 375.#242 x3 Kill Keep x3 | | | | | | | | | | | | 375.#243 x4 Kill Keep x4 | | | | | | | | | | | | 375.#244 x5 Kill Keep x5 | | | | | | | | | | | | 375.#245 x6 Kill Keep x6 | | | | | | | | | | | | 375.#246 x7 Kill Keep x7 | | | | | | | | | | | | 375.#247 x8 Kill Keep x8 | | | | | | | | | | | | 375.#248 x9 Kill Keep x9 | | | | | | | | | | | | 375.#249 x10 Kill Keep x10 | | | | | | | | | | | | 375.#250 x11 Kill Keep x11 | | | | | | | | | | | | 375.#251 x12 Kill Keep x12 | | | | | | | | | | | | 375.#252 x13 Kill Keep x13 | | | | | | | | | | | | 375.#253 x14 Kill Keep x14 | | | | | | | | | | | | 375.#254 x15 Kill Keep x15 | | | | | | | | | | | | 375.#255 xip0 Kill Keep xip0 | | | | | | | | | | | | 375.#256 xip1 Kill Keep xip1 | | | | | | | | | | | | 375.#257 lr Kill Keep lr | | | | | | | | | | | | 375.#258 KlGC None | | | | | | | | | | | | 377.#259 I93 Def Alloc x0 |I93a| | | | | | | | | | | 381.#260 C94 Def Alloc x1 |I93a|C94a| | | | | | | | | | 382.#261 I93 Use * Keep x0 |I93a|C94a| | | | | | | | | | 382.#262 C94 Use * Keep x1 |I93a|C94a| | | | | | | | | | 385.#263 C95 Def Alloc x0 |C95a|C94i| | | | | | | | | | 386.#264 C95 Use * Keep x0 |C95a|C94i| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 387.#265 I96 Def Alloc x0 |I96a|C94i| | | | | | | | | | 388.#266 I96 Use * Keep x0 |I96a|C94i| | | | | | | | | | 389.#267 x0 Kill Keep x0 | |C94i| | | | | | | | | | 389.#268 x1 Kill Keep x1 | | | | | | | | | | | | 389.#269 x2 Kill Keep x2 | | | | | | | | | | | | 389.#270 x3 Kill Keep x3 | | | | | | | | | | | | 389.#271 x4 Kill Keep x4 | | | | | | | | | | | | 389.#272 x5 Kill Keep x5 | | | | | | | | | | | | 389.#273 x6 Kill Keep x6 | | | | | | | | | | | | 389.#274 x7 Kill Keep x7 | | | | | | | | | | | | 389.#275 x8 Kill Keep x8 | | | | | | | | | | | | 389.#276 x9 Kill Keep x9 | | | | | | | | | | | | 389.#277 x10 Kill Keep x10 | | | | | | | | | | | | 389.#278 x11 Kill Keep x11 | | | | | | | | | | | | 389.#279 x12 Kill Keep x12 | | | | | | | | | | | | 389.#280 x13 Kill Keep x13 | | | | | | | | | | | | 389.#281 x14 Kill Keep x14 | | | | | | | | | | | | 389.#282 x15 Kill Keep x15 | | | | | | | | | | | | 389.#283 xip0 Kill Keep xip0 | | | | | | | | | | | | 389.#284 xip1 Kill Keep xip1 | | | | | | | | | | | | 389.#285 lr Kill Keep lr | | | | | | | | | | | | 389.#286 d0 Kill Keep d0 | | | | | | | | | | | | 389.#287 d1 Kill Keep d1 | | | | | | | | | | | | 389.#288 d2 Kill Keep d2 | | | | | | | | | | | | 389.#289 d3 Kill Keep d3 | | | | | | | | | | | | 389.#290 d4 Kill Keep d4 | | | | | | | | | | | | 389.#291 d5 Kill Keep d5 | | | | | | | | | | | | 389.#292 d6 Kill Keep d6 | | | | | | | | | | | | 389.#293 d7 Kill Keep d7 | | | | | | | | | | | | 389.#294 d16 Kill Keep d16 | | | | | | | | | | | | 389.#295 d17 Kill Keep d17 | | | | | | | | | | | | 389.#296 d18 Kill Keep d18 | | | | | | | | | | | | 389.#297 d19 Kill Keep d19 | | | | | | | | | | | | 389.#298 d20 Kill Keep d20 | | | | | | | | | | | | 389.#299 d21 Kill Keep d21 | | | | | | | | | | | | 389.#300 d22 Kill Keep d22 | | | | | | | | | | | | 389.#301 d23 Kill Keep d23 | | | | | | | | | | | | 389.#302 d24 Kill Keep d24 | | | | | | | | | | | | 389.#303 d25 Kill Keep d25 | | | | | | | | | | | | 389.#304 d26 Kill Keep d26 | | | | | | | | | | | | 389.#305 d27 Kill Keep d27 | | | | | | | | | | | | 389.#306 d28 Kill Keep d28 | | | | | | | | | | | | 389.#307 d29 Kill Keep d29 | | | | | | | | | | | | 389.#308 d30 Kill Keep d30 | | | | | | | | | | | | 389.#309 d31 Kill Keep d31 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 458.#310 BB3 PredBB2 | | | | | | | | | | | | 461.#311 I97 Def Alloc x0 |I97a| | | | | | | | | | | 465.#312 I98 Def Alloc x1 |I97a|I98a| | | | | | | | | | 466.#313 I97 Use * Keep x0 |I97a|I98a| | | | | | | | | | 466.#314 I98 Use * Keep x1 | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ LCL_FLD_ADDR BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x0] minReg=1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed> PHYSREG BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed> BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last fixed> BB01 regmask=[x1] minReg=1> BB01 regmask=[x1] minReg=1 last fixed> BB01 regmask=[x0] minReg=1 last> BB01 regmask=[x1] minReg=1 last> BB01 regmask=[x2] minReg=1 last> BB01 regmask=[x3] minReg=1 last> BB01 regmask=[x4] minReg=1 last> BB01 regmask=[x5] minReg=1 last> BB01 regmask=[x6] minReg=1 last> BB01 regmask=[x7] minReg=1 last> BB01 regmask=[x8] minReg=1 last> BB01 regmask=[x9] minReg=1 last> BB01 regmask=[x10] minReg=1 last> BB01 regmask=[x11] minReg=1 last> BB01 regmask=[x12] minReg=1 last> BB01 regmask=[x13] minReg=1 last> BB01 regmask=[x14] minReg=1 last> BB01 regmask=[x15] minReg=1 last> BB01 regmask=[xip0] minReg=1 last> BB01 regmask=[xip1] minReg=1 last> BB01 regmask=[lr] minReg=1 last> BB01 regmask=[x0] minReg=1> CALL BB01 regmask=[x0] minReg=1 fixed> BB01 regmask=[x0] minReg=1 last> PHYSREG BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last> PHYSREG BB01 regmask=[x0] minReg=1> BB01 regmask=[x0] minReg=1 last> LCL_VAR BB01 regmask=[x0] minReg=1> LCL_FLD_ADDR BB01 regmask=[x1] minReg=1> BB01 regmask=[x0] minReg=1 last> BB01 regmask=[x1] minReg=1 last> CNS_INT BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> CAST BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> NE BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> CNS_INT BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last> CAST BB02 regmask=[x1] minReg=1> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> IND BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> IND BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x0] minReg=1> PUTARG_REG BB02 regmask=[x0] minReg=1 fixed> LCL_VAR BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> PUTARG_REG BB02 regmask=[x1] minReg=1 fixed> LCL_VAR BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> PUTARG_REG BB02 regmask=[x2] minReg=1 fixed> LCL_VAR BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> PUTARG_REG BB02 regmask=[x3] minReg=1 fixed> LCL_VAR BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> PUTARG_REG BB02 regmask=[x4] minReg=1 fixed> LCL_VAR BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> PUTARG_REG BB02 regmask=[x5] minReg=1 fixed> LCL_VAR BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> PUTARG_REG BB02 regmask=[x6] minReg=1 fixed> LCL_VAR BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> PUTARG_REG BB02 regmask=[x7] minReg=1 fixed> LCL_VAR BB02 regmask=[x8] minReg=1> BB02 regmask=[x8] minReg=1 last> LABEL BB02 regmask=[x8] minReg=1> BB02 regmask=[x8] minReg=1 last> LCL_VAR BB02 regmask=[x8] minReg=1> BB02 regmask=[x8] minReg=1 last> LCL_VAR BB02 regmask=[x8] minReg=1> BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last fixed> BB02 regmask=[x1] minReg=1> BB02 regmask=[x1] minReg=1 last fixed> BB02 regmask=[x2] minReg=1> BB02 regmask=[x2] minReg=1 last fixed> BB02 regmask=[x3] minReg=1> BB02 regmask=[x3] minReg=1 last fixed> BB02 regmask=[x4] minReg=1> BB02 regmask=[x4] minReg=1 last fixed> BB02 regmask=[x5] minReg=1> BB02 regmask=[x5] minReg=1 last fixed> BB02 regmask=[x6] minReg=1> BB02 regmask=[x6] minReg=1 last fixed> BB02 regmask=[x7] minReg=1> BB02 regmask=[x7] minReg=1 last fixed> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> LCL_VAR BB02 regmask=[x0] minReg=1> CNS_INT BB02 regmask=[x1] minReg=1> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> CNS_INT BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> IND BB02 regmask=[x0] minReg=1> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x0] minReg=1 last> BB02 regmask=[x1] minReg=1 last> BB02 regmask=[x2] minReg=1 last> BB02 regmask=[x3] minReg=1 last> BB02 regmask=[x4] minReg=1 last> BB02 regmask=[x5] minReg=1 last> BB02 regmask=[x6] minReg=1 last> BB02 regmask=[x7] minReg=1 last> BB02 regmask=[x8] minReg=1 last> BB02 regmask=[x9] minReg=1 last> BB02 regmask=[x10] minReg=1 last> BB02 regmask=[x11] minReg=1 last> BB02 regmask=[x12] minReg=1 last> BB02 regmask=[x13] minReg=1 last> BB02 regmask=[x14] minReg=1 last> BB02 regmask=[x15] minReg=1 last> BB02 regmask=[xip0] minReg=1 last> BB02 regmask=[xip1] minReg=1 last> BB02 regmask=[lr] minReg=1 last> BB02 regmask=[d0] minReg=1 last> BB02 regmask=[d1] minReg=1 last> BB02 regmask=[d2] minReg=1 last> BB02 regmask=[d3] minReg=1 last> BB02 regmask=[d4] minReg=1 last> BB02 regmask=[d5] minReg=1 last> BB02 regmask=[d6] minReg=1 last> BB02 regmask=[d7] minReg=1 last> BB02 regmask=[d16] minReg=1 last> BB02 regmask=[d17] minReg=1 last> BB02 regmask=[d18] minReg=1 last> BB02 regmask=[d19] minReg=1 last> BB02 regmask=[d20] minReg=1 last> BB02 regmask=[d21] minReg=1 last> BB02 regmask=[d22] minReg=1 last> BB02 regmask=[d23] minReg=1 last> BB02 regmask=[d24] minReg=1 last> BB02 regmask=[d25] minReg=1 last> BB02 regmask=[d26] minReg=1 last> BB02 regmask=[d27] minReg=1 last> BB02 regmask=[d28] minReg=1 last> BB02 regmask=[d29] minReg=1 last> BB02 regmask=[d30] minReg=1 last> BB02 regmask=[d31] minReg=1 last> LCL_VAR BB03 regmask=[x0] minReg=1> LCL_FLD BB03 regmask=[x1] minReg=1> BB03 regmask=[x0] minReg=1 last> BB03 regmask=[x1] minReg=1 last> Active intervals at end of allocation: Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N002 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] x0 REG x0 /--* t240 long N004 (???,???) [000254] ------------ t254 = * PUTARG_REG long REG x0 N006 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 REG x1 /--* t241 long N008 (???,???) [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 N010 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME REG x0 /--* t242 long N012 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot NA REG NA N014 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp REG x0 /--* t247 long N016 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] NA REG NA N018 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp REG x0 /--* t249 long N020 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] NA REG NA N022 ( 3, 2) [000250] ------------ t250 = LCL_VAR long V38 FramesRoot x0 REG x0 /--* t250 long N024 ( 4, 3) [000251] -c---------- t251 = * LEA(b+16) long REG NA N026 ( 3, 3) [000252] ------------ t252 = LCL_FLD_ADDR byref V39 PInvokeFrame [+8] x1 REG x1 /--* t251 long +--* t252 byref N028 ( 8, 7) [000253] ------------ * STOREIND long REG NA ------------ BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} N032 (???,???) [000239] ------------ IL_OFFSET void IL offset: 0x0 REG NA N034 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 REG x0 /--* t0 int N036 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 NA REG NA N038 ( 1, 1) [000003] ------------ NO_OP void REG NA N040 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 x0 REG x0 /--* t4 int N042 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int REG x0 N044 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 REG NA /--* t215 int +--* t5 int N046 ( 9, 7) [000006] ------------ t6 = * NE int REG x0 /--* t6 int N048 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 NA REG NA N050 ( 1, 1) [000011] ------------ NO_OP void REG NA N052 ( 1, 1) [000012] ------------ NO_OP void REG NA N054 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 x0 REG x0 /--* t13 int N056 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int REG x0 N058 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 REG NA /--* t216 int +--* t14 int N060 ( 9, 7) [000015] ------------ t15 = * NE int REG x0 /--* t15 int N062 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 NA REG NA N064 ( 1, 1) [000020] ------------ NO_OP void REG NA N066 ( 1, 1) [000021] ------------ NO_OP void REG NA N068 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 x0 REG x0 /--* t22 int N070 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int REG x0 N072 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 REG NA /--* t217 int +--* t23 int N074 ( 9, 7) [000024] ------------ t24 = * NE int REG x0 /--* t24 int N076 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 NA REG NA N078 ( 1, 1) [000029] ------------ NO_OP void REG NA N080 ( 1, 1) [000030] ------------ NO_OP void REG NA N082 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 x0 REG x0 /--* t31 int N084 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int REG x0 N086 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 REG NA /--* t218 int +--* t32 int N088 ( 9, 7) [000033] ------------ t33 = * NE int REG x0 /--* t33 int N090 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 NA REG NA N092 ( 1, 1) [000038] ------------ NO_OP void REG NA N094 ( 1, 1) [000039] ------------ NO_OP void REG NA N096 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 x0 REG x0 /--* t40 int N098 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int REG x0 N100 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 REG NA /--* t219 int +--* t41 int N102 ( 9, 7) [000042] ------------ t42 = * NE int REG x0 /--* t42 int N104 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 NA REG NA N106 ( 1, 1) [000047] ------------ NO_OP void REG NA N108 ( 1, 1) [000048] ------------ NO_OP void REG NA N110 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 x0 REG x0 /--* t49 int N112 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int REG x0 N114 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 REG NA /--* t220 int +--* t50 int N116 ( 9, 7) [000051] ------------ t51 = * NE int REG x0 /--* t51 int N118 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 NA REG NA N120 ( 1, 1) [000056] ------------ NO_OP void REG NA N122 ( 1, 1) [000057] ------------ NO_OP void REG NA N124 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 x0 REG x0 /--* t58 int N126 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int REG x0 N128 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 REG NA /--* t221 int +--* t59 int N130 ( 9, 7) [000060] ------------ t60 = * NE int REG x0 /--* t60 int N132 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 NA REG NA N134 ( 1, 1) [000065] ------------ NO_OP void REG NA N136 ( 1, 1) [000066] ------------ NO_OP void REG NA N138 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 x0 REG x0 /--* t67 int N140 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int REG x0 N142 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 REG NA /--* t222 int +--* t68 int N144 ( 9, 7) [000069] ------------ t69 = * NE int REG x0 /--* t69 int N146 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 NA REG NA N148 ( 1, 1) [000074] ------------ NO_OP void REG NA N150 ( 1, 1) [000075] ------------ NO_OP void REG NA N152 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 x0 REG x0 /--* t76 int N154 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int REG x0 N156 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 REG NA /--* t223 int +--* t77 int N158 ( 9, 7) [000078] ------------ t78 = * NE int REG x0 /--* t78 int N160 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 NA REG NA N162 ( 1, 1) [000083] ------------ NO_OP void REG NA N164 ( 1, 1) [000084] ------------ NO_OP void REG NA N166 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 x0 REG x0 /--* t85 int N168 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int REG x0 N170 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 REG NA /--* t224 int +--* t86 int N172 ( 9, 7) [000087] ------------ t87 = * NE int REG x0 /--* t87 int N174 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 NA REG NA N176 ( 1, 1) [000092] ------------ NO_OP void REG NA N178 ( 1, 1) [000093] ------------ NO_OP void REG NA N180 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 x0 REG x0 /--* t94 int N182 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int REG x0 N184 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 REG NA /--* t225 int +--* t95 int N186 ( 9, 7) [000096] ------------ t96 = * NE int REG x0 /--* t96 int N188 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 NA REG NA N190 ( 1, 1) [000101] ------------ NO_OP void REG NA N192 ( 1, 1) [000102] ------------ NO_OP void REG NA N194 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 x0 REG x0 /--* t103 int N196 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int REG x0 N198 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 REG NA /--* t226 int +--* t104 int N200 ( 9, 7) [000105] ------------ t105 = * NE int REG x0 /--* t105 int N202 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 NA REG NA N204 ( 1, 1) [000110] ------------ NO_OP void REG NA N206 ( 1, 1) [000111] ------------ NO_OP void REG NA N208 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 x0 REG x0 /--* t112 int N210 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int REG x0 N212 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 REG NA /--* t227 int +--* t113 int N214 ( 9, 7) [000114] ------------ t114 = * NE int REG x0 /--* t114 int N216 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 NA REG NA N218 ( 1, 1) [000119] ------------ NO_OP void REG NA N220 ( 1, 1) [000120] ------------ NO_OP void REG NA N222 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 x0 REG x0 /--* t121 int N224 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int REG x0 N226 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 REG NA /--* t228 int +--* t122 int N228 ( 9, 7) [000123] ------------ t123 = * NE int REG x0 /--* t123 int N230 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 NA REG NA N232 ( 1, 1) [000128] ------------ NO_OP void REG NA N234 ( 1, 1) [000129] ------------ NO_OP void REG NA N236 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 x0 REG x0 /--* t130 int N238 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int REG x0 N240 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 REG NA /--* t229 int +--* t131 int N242 ( 9, 7) [000132] ------------ t132 = * NE int REG x0 /--* t132 int N244 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 NA REG NA N246 ( 1, 1) [000137] ------------ NO_OP void REG NA N248 ( 1, 1) [000138] ------------ NO_OP void REG NA N250 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 x0 REG x0 /--* t139 int N252 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int REG x0 N254 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 REG NA /--* t230 int +--* t140 int N256 ( 9, 7) [000141] ------------ t141 = * NE int REG x0 /--* t141 int N258 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 NA REG NA N260 ( 1, 1) [000146] ------------ NO_OP void REG NA N262 ( 1, 1) [000147] ------------ NO_OP void REG NA N264 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 x0 REG x0 /--* t148 long N266 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 NA REG NA N268 ( 1, 1) [000151] ------------ NO_OP void REG NA N270 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 x0 REG x0 N272 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 REG x1 /--* t170 int N274 ( 2, 4) [000171] ------------ t171 = * CAST long <- int REG x1 /--* t169 long +--* t171 long N276 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long REG NA /--* t172 long N278 ( 8, 8) [000173] *--XG------- t173 = * IND long REG x0 /--* t173 long N280 ( 11, 10) [000174] *--XG------- t174 = * IND long REG x0 /--* t174 long N282 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 NA REG NA N284 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 x0 REG x0 /--* t160 int N286 (???,???) [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) REG NA N288 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 x0 REG x0 /--* t161 int N290 (???,???) [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) REG NA N292 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 x0 REG x0 /--* t162 int N294 (???,???) [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) REG NA N296 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 x0 REG x0 /--* t163 int N298 (???,???) [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) REG NA N300 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 x0 REG x0 /--* t164 int N302 (???,???) [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) REG NA N304 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 x0 REG x0 /--* t165 int N306 (???,???) [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) REG NA N308 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 x0 REG x0 /--* t166 int N310 (???,???) [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) REG NA N312 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 x0 REG x0 /--* t167 int N314 (???,???) [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) REG NA N316 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 x0 REG x0 /--* t168 long N318 (???,???) [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) REG NA N320 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 x0 REG x0 /--* t152 int N322 (???,???) [000265] ------------ t265 = * PUTARG_REG int REG x0 N324 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 x1 REG x1 /--* t153 int N326 (???,???) [000266] ------------ t266 = * PUTARG_REG int REG x1 N328 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 x2 REG x2 /--* t154 int N330 (???,???) [000267] ------------ t267 = * PUTARG_REG int REG x2 N332 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 x3 REG x3 /--* t155 int N334 (???,???) [000268] ------------ t268 = * PUTARG_REG int REG x3 N336 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 x4 REG x4 /--* t156 int N338 (???,???) [000269] ------------ t269 = * PUTARG_REG int REG x4 N340 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 x5 REG x5 /--* t157 int N342 (???,???) [000270] ------------ t270 = * PUTARG_REG int REG x5 N344 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 x6 REG x6 /--* t158 int N346 (???,???) [000271] ------------ t271 = * PUTARG_REG int REG x6 N348 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 x7 REG x7 /--* t159 int N350 (???,???) [000272] ------------ t272 = * PUTARG_REG int REG x7 N352 ( 3, 2) [000274] ------------ t274 = LCL_VAR long (AX) V36 tmp1 x8 REG x8 /--* t274 long N354 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] NA REG NA N356 ( 1, 1) [000277] ------------ t277 = LABEL long REG x8 /--* t277 long N358 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] NA REG NA N360 ( 3, 2) [000278] ------------ t278 = LCL_VAR long V38 FramesRoot x8 REG x8 /--* t278 long N362 ( 4, 3) [000280] -c---------- t280 = * LEA(b+12) long REG NA N364 ( 1, 2) [000279] -c---------- t279 = CNS_INT byte 0 REG NA /--* t280 long +--* t279 byte N366 ( 6, 6) [000281] ------------ * STOREIND byte REG NA N368 (???,???) [000282] ------------ START_PREEMPTGC void REG NA N370 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 x8 REG x8 N372 (???,???) [000273] ------------ PINVOKE_PROLOG void REG NA /--* t265 int arg0 in x0 +--* t266 int arg1 in x1 +--* t267 int arg2 in x2 +--* t268 int arg3 in x3 +--* t269 int arg4 in x4 +--* t270 int arg5 in x5 +--* t271 int arg6 in x6 +--* t272 int arg7 in x7 +--* t177 long calli tgt N374 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void REG NA N376 ( 3, 2) [000283] ------------ t283 = LCL_VAR long V38 FramesRoot x0 REG x0 /--* t283 long N378 ( 4, 3) [000285] -c---------- t285 = * LEA(b+12) long REG NA N380 ( 1, 2) [000284] ------------ t284 = CNS_INT byte 1 REG x1 /--* t285 long +--* t284 byte N382 ( 6, 6) [000286] ------------ * STOREIND byte REG NA N384 ( 3, 12) [000287] H----------- t287 = CNS_INT(h) long 0x1021dd928 ftn REG x0 /--* t287 long N386 ( 6, 14) [000288] ------------ t288 = * IND int REG x0 /--* t288 int N388 ( 7, 15) [000289] ------------ * RETURNTRAP int REG NA N390 ( 1, 1) [000179] ------------ NO_OP void REG NA N392 ( 1, 1) [000180] ------------ NO_OP void REG NA N394 ( 1, 1) [000181] ------------ NO_OP void REG NA N396 ( 1, 1) [000182] ------------ NO_OP void REG NA N398 ( 1, 1) [000183] ------------ NO_OP void REG NA N400 ( 1, 1) [000184] ------------ NO_OP void REG NA N402 ( 1, 1) [000185] ------------ NO_OP void REG NA N404 ( 1, 1) [000186] ------------ NO_OP void REG NA N406 ( 1, 1) [000187] ------------ NO_OP void REG NA N408 ( 1, 1) [000188] ------------ NO_OP void REG NA N410 ( 1, 1) [000189] ------------ NO_OP void REG NA N412 ( 1, 1) [000190] ------------ NO_OP void REG NA N414 ( 1, 1) [000191] ------------ NO_OP void REG NA N416 ( 1, 1) [000192] ------------ NO_OP void REG NA N418 ( 1, 1) [000193] ------------ NO_OP void REG NA N420 ( 1, 1) [000194] ------------ NO_OP void REG NA N422 ( 1, 1) [000195] ------------ NO_OP void REG NA N424 ( 1, 1) [000196] ------------ NO_OP void REG NA N426 ( 1, 1) [000197] ------------ NO_OP void REG NA N428 ( 1, 1) [000198] ------------ NO_OP void REG NA N430 ( 1, 1) [000199] ------------ NO_OP void REG NA N432 ( 1, 1) [000200] ------------ NO_OP void REG NA N434 ( 1, 1) [000201] ------------ NO_OP void REG NA N436 ( 1, 1) [000202] ------------ NO_OP void REG NA N438 ( 1, 1) [000203] ------------ NO_OP void REG NA N440 ( 1, 1) [000204] ------------ NO_OP void REG NA N442 ( 1, 1) [000205] ------------ NO_OP void REG NA N444 ( 1, 1) [000206] ------------ NO_OP void REG NA N446 ( 1, 1) [000207] ------------ NO_OP void REG NA N448 ( 1, 1) [000208] ------------ NO_OP void REG NA N450 ( 1, 1) [000209] ------------ NO_OP void REG NA N452 ( 1, 1) [000210] ------------ NO_OP void REG NA N454 ( 1, 1) [000211] ------------ NO_OP void REG NA N456 ( 1, 1) [000212] ------------ NO_OP void REG NA ------------ BB03 [???..???) (return), preds={BB02} succs={} N460 ( 3, 2) [000290] ------------ t290 = LCL_VAR long V38 FramesRoot x0 REG x0 /--* t290 long N462 ( 4, 3) [000291] -c---------- t291 = * LEA(b+16) long REG NA N464 ( 3, 4) [000292] ------------ t292 = LCL_FLD byref V39 PInvokeFrame [+16] x1 REG x1 /--* t291 long +--* t292 byref N466 ( 8, 8) [000293] ------------ * STOREIND long REG NA N468 ( 0, 0) [000214] ------------ RETURN void REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 BB1 PredBB0 | | | | | | | | | | | | 3.#1 I0 Def Alloc x0 |I0 a| | | | | | | | | | | 4.#2 x0 Fixd Keep x0 |I0 a| | | | | | | | | | | 4.#3 I0 Use * Keep x0 |I0 i| | | | | | | | | | | 5.#4 x0 Fixd Keep x0 | | | | | | | | | | | | 5.#5 I1 Def Alloc x0 |I1 a| | | | | | | | | | | 7.#6 I2 Def Alloc x1 |I1 a|I2 a| | | | | | | | | | 8.#7 x1 Fixd Keep x1 |I1 a|I2 a| | | | | | | | | | 8.#8 I2 Use * Keep x1 |I1 a|I2 i| | | | | | | | | | 9.#9 x1 Fixd Keep x1 |I1 a| | | | | | | | | | | 9.#10 I3 Def Alloc x1 |I1 a|I3 a| | | | | | | | | | 10.#11 x0 Fixd Keep x0 |I1 a|I3 a| | | | | | | | | | 10.#12 I1 Use * Keep x0 |I1 i|I3 a| | | | | | | | | | 10.#13 x1 Fixd Keep x1 | |I3 a| | | | | | | | | | 10.#14 I3 Use * Keep x1 | |I3 i| | | | | | | | | | 11.#15 x0 Kill Keep x0 | | | | | | | | | | | | 11.#16 x1 Kill Keep x1 | | | | | | | | | | | | 11.#17 x2 Kill Keep x2 | | | | | | | | | | | | 11.#18 x3 Kill Keep x3 | | | | | | | | | | | | 11.#19 x4 Kill Keep x4 | | | | | | | | | | | | 11.#20 x5 Kill Keep x5 | | | | | | | | | | | | 11.#21 x6 Kill Keep x6 | | | | | | | | | | | | 11.#22 x7 Kill Keep x7 | | | | | | | | | | | | 11.#23 x8 Kill Keep x8 | | | | | | | | | | | | 11.#24 x9 Kill Keep x9 | | | | | | | | | | | | 11.#25 x10 Kill Keep x10 | | | | | | | | | | | | 11.#26 x11 Kill Keep x11 | | | | | | | | | | | | 11.#27 x12 Kill Keep x12 | | | | | | | | | | | | 11.#28 x13 Kill Keep x13 | | | | | | | | | | | | 11.#29 x14 Kill Keep x14 | | | | | | | | | | | | 11.#30 x15 Kill Keep x15 | | | | | | | | | | | | 11.#31 xip0 Kill Keep xip0 | | | | | | | | | | | | 11.#32 xip1 Kill Keep xip1 | | | | | | | | | | | | 11.#33 lr Kill Keep lr | | | | | | | | | | | | 11.#34 x0 Fixd Keep x0 | | | | | | | | | | | | 11.#35 I4 Def Alloc x0 |I4 a| | | | | | | | | | | 12.#36 I4 Use * Keep x0 |I4 i| | | | | | | | | | | 15.#37 I5 Def Alloc x0 |I5 a| | | | | | | | | | | 16.#38 I5 Use * Keep x0 |I5 i| | | | | | | | | | | 19.#39 I6 Def Alloc x0 |I6 a| | | | | | | | | | | 20.#40 I6 Use * Keep x0 |I6 i| | | | | | | | | | | 23.#41 I7 Def Alloc x0 |I7 a| | | | | | | | | | | 27.#42 I8 Def Alloc x1 |I7 a|I8 a| | | | | | | | | | 28.#43 I7 Use * Keep x0 |I7 i|I8 a| | | | | | | | | | 28.#44 I8 Use * Keep x1 | |I8 i| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 30.#45 BB2 PredBB1 | | | | | | | | | | | | 35.#46 C9 Def Alloc x0 |C9 a| | | | | | | | | | | 36.#47 C9 Use * Keep x0 |C9 i| | | | | | | | | | | 41.#48 I10 Def Alloc x0 |I10a| | | | | | | | | | | 42.#49 I10 Use * Keep x0 |I10i| | | | | | | | | | | 43.#50 I11 Def Alloc x0 |I11a| | | | | | | | | | | 46.#51 I11 Use * Keep x0 |I11i| | | | | | | | | | | 47.#52 I12 Def Alloc x0 |I12a| | | | | | | | | | | 48.#53 I12 Use * Keep x0 |I12i| | | | | | | | | | | 55.#54 I13 Def Alloc x0 |I13a| | | | | | | | | | | 56.#55 I13 Use * Keep x0 |I13i| | | | | | | | | | | 57.#56 I14 Def Alloc x0 |I14a| | | | | | | | | | | 60.#57 I14 Use * Keep x0 |I14i| | | | | | | | | | | 61.#58 I15 Def Alloc x0 |I15a| | | | | | | | | | | 62.#59 I15 Use * Keep x0 |I15i| | | | | | | | | | | 69.#60 I16 Def Alloc x0 |I16a| | | | | | | | | | | 70.#61 I16 Use * Keep x0 |I16i| | | | | | | | | | | 71.#62 I17 Def Alloc x0 |I17a| | | | | | | | | | | 74.#63 I17 Use * Keep x0 |I17i| | | | | | | | | | | 75.#64 I18 Def Alloc x0 |I18a| | | | | | | | | | | 76.#65 I18 Use * Keep x0 |I18i| | | | | | | | | | | 83.#66 I19 Def Alloc x0 |I19a| | | | | | | | | | | 84.#67 I19 Use * Keep x0 |I19i| | | | | | | | | | | 85.#68 I20 Def Alloc x0 |I20a| | | | | | | | | | | 88.#69 I20 Use * Keep x0 |I20i| | | | | | | | | | | 89.#70 I21 Def Alloc x0 |I21a| | | | | | | | | | | 90.#71 I21 Use * Keep x0 |I21i| | | | | | | | | | | 97.#72 I22 Def Alloc x0 |I22a| | | | | | | | | | | 98.#73 I22 Use * Keep x0 |I22i| | | | | | | | | | | 99.#74 I23 Def Alloc x0 |I23a| | | | | | | | | | | 102.#75 I23 Use * Keep x0 |I23i| | | | | | | | | | | 103.#76 I24 Def Alloc x0 |I24a| | | | | | | | | | | 104.#77 I24 Use * Keep x0 |I24i| | | | | | | | | | | 111.#78 I25 Def Alloc x0 |I25a| | | | | | | | | | | 112.#79 I25 Use * Keep x0 |I25i| | | | | | | | | | | 113.#80 I26 Def Alloc x0 |I26a| | | | | | | | | | | 116.#81 I26 Use * Keep x0 |I26i| | | | | | | | | | | 117.#82 I27 Def Alloc x0 |I27a| | | | | | | | | | | 118.#83 I27 Use * Keep x0 |I27i| | | | | | | | | | | 125.#84 I28 Def Alloc x0 |I28a| | | | | | | | | | | 126.#85 I28 Use * Keep x0 |I28i| | | | | | | | | | | 127.#86 I29 Def Alloc x0 |I29a| | | | | | | | | | | 130.#87 I29 Use * Keep x0 |I29i| | | | | | | | | | | 131.#88 I30 Def Alloc x0 |I30a| | | | | | | | | | | 132.#89 I30 Use * Keep x0 |I30i| | | | | | | | | | | 139.#90 I31 Def Alloc x0 |I31a| | | | | | | | | | | 140.#91 I31 Use * Keep x0 |I31i| | | | | | | | | | | 141.#92 I32 Def Alloc x0 |I32a| | | | | | | | | | | 144.#93 I32 Use * Keep x0 |I32i| | | | | | | | | | | 145.#94 I33 Def Alloc x0 |I33a| | | | | | | | | | | 146.#95 I33 Use * Keep x0 |I33i| | | | | | | | | | | 153.#96 I34 Def Alloc x0 |I34a| | | | | | | | | | | 154.#97 I34 Use * Keep x0 |I34i| | | | | | | | | | | 155.#98 I35 Def Alloc x0 |I35a| | | | | | | | | | | 158.#99 I35 Use * Keep x0 |I35i| | | | | | | | | | | 159.#100 I36 Def Alloc x0 |I36a| | | | | | | | | | | 160.#101 I36 Use * Keep x0 |I36i| | | | | | | | | | | 167.#102 I37 Def Alloc x0 |I37a| | | | | | | | | | | 168.#103 I37 Use * Keep x0 |I37i| | | | | | | | | | | 169.#104 I38 Def Alloc x0 |I38a| | | | | | | | | | | 172.#105 I38 Use * Keep x0 |I38i| | | | | | | | | | | 173.#106 I39 Def Alloc x0 |I39a| | | | | | | | | | | 174.#107 I39 Use * Keep x0 |I39i| | | | | | | | | | | 181.#108 I40 Def Alloc x0 |I40a| | | | | | | | | | | 182.#109 I40 Use * Keep x0 |I40i| | | | | | | | | | | 183.#110 I41 Def Alloc x0 |I41a| | | | | | | | | | | 186.#111 I41 Use * Keep x0 |I41i| | | | | | | | | | | 187.#112 I42 Def Alloc x0 |I42a| | | | | | | | | | | 188.#113 I42 Use * Keep x0 |I42i| | | | | | | | | | | 195.#114 I43 Def Alloc x0 |I43a| | | | | | | | | | | 196.#115 I43 Use * Keep x0 |I43i| | | | | | | | | | | 197.#116 I44 Def Alloc x0 |I44a| | | | | | | | | | | 200.#117 I44 Use * Keep x0 |I44i| | | | | | | | | | | 201.#118 I45 Def Alloc x0 |I45a| | | | | | | | | | | 202.#119 I45 Use * Keep x0 |I45i| | | | | | | | | | | 209.#120 I46 Def Alloc x0 |I46a| | | | | | | | | | | 210.#121 I46 Use * Keep x0 |I46i| | | | | | | | | | | 211.#122 I47 Def Alloc x0 |I47a| | | | | | | | | | | 214.#123 I47 Use * Keep x0 |I47i| | | | | | | | | | | 215.#124 I48 Def Alloc x0 |I48a| | | | | | | | | | | 216.#125 I48 Use * Keep x0 |I48i| | | | | | | | | | | 223.#126 I49 Def Alloc x0 |I49a| | | | | | | | | | | 224.#127 I49 Use * Keep x0 |I49i| | | | | | | | | | | 225.#128 I50 Def Alloc x0 |I50a| | | | | | | | | | | 228.#129 I50 Use * Keep x0 |I50i| | | | | | | | | | | 229.#130 I51 Def Alloc x0 |I51a| | | | | | | | | | | 230.#131 I51 Use * Keep x0 |I51i| | | | | | | | | | | 237.#132 I52 Def Alloc x0 |I52a| | | | | | | | | | | 238.#133 I52 Use * Keep x0 |I52i| | | | | | | | | | | 239.#134 I53 Def Alloc x0 |I53a| | | | | | | | | | | 242.#135 I53 Use * Keep x0 |I53i| | | | | | | | | | | 243.#136 I54 Def Alloc x0 |I54a| | | | | | | | | | | 244.#137 I54 Use * Keep x0 |I54i| | | | | | | | | | | 251.#138 I55 Def Alloc x0 |I55a| | | | | | | | | | | 252.#139 I55 Use * Keep x0 |I55i| | | | | | | | | | | 253.#140 I56 Def Alloc x0 |I56a| | | | | | | | | | | 256.#141 I56 Use * Keep x0 |I56i| | | | | | | | | | | 257.#142 I57 Def Alloc x0 |I57a| | | | | | | | | | | 258.#143 I57 Use * Keep x0 |I57i| | | | | | | | | | | 265.#144 I58 Def Alloc x0 |I58a| | | | | | | | | | | 266.#145 I58 Use * Keep x0 |I58i| | | | | | | | | | | 271.#146 I59 Def Alloc x0 |I59a| | | | | | | | | | | 273.#147 C60 Def Alloc x1 |I59a|C60a| | | | | | | | | | 274.#148 C60 Use * Keep x1 |I59a|C60i| | | | | | | | | | 275.#149 I61 Def Alloc x1 |I59a|I61a| | | | | | | | | | 278.#150 I59 Use * Keep x0 |I59i|I61a| | | | | | | | | | 278.#151 I61 Use * Keep x1 | |I61i| | | | | | | | | | 279.#152 I62 Def Alloc x0 |I62a| | | | | | | | | | | 280.#153 I62 Use * Keep x0 |I62i| | | | | | | | | | | 281.#154 I63 Def Alloc x0 |I63a| | | | | | | | | | | 282.#155 I63 Use * Keep x0 |I63i| | | | | | | | | | | 285.#156 I64 Def Alloc x0 |I64a| | | | | | | | | | | 286.#157 I64 Use * Keep x0 |I64i| | | | | | | | | | | 289.#158 I65 Def Alloc x0 |I65a| | | | | | | | | | | 290.#159 I65 Use * Keep x0 |I65i| | | | | | | | | | | 293.#160 I66 Def Alloc x0 |I66a| | | | | | | | | | | 294.#161 I66 Use * Keep x0 |I66i| | | | | | | | | | | 297.#162 I67 Def Alloc x0 |I67a| | | | | | | | | | | 298.#163 I67 Use * Keep x0 |I67i| | | | | | | | | | | 301.#164 I68 Def Alloc x0 |I68a| | | | | | | | | | | 302.#165 I68 Use * Keep x0 |I68i| | | | | | | | | | | 305.#166 I69 Def Alloc x0 |I69a| | | | | | | | | | | 306.#167 I69 Use * Keep x0 |I69i| | | | | | | | | | | 309.#168 I70 Def Alloc x0 |I70a| | | | | | | | | | | 310.#169 I70 Use * Keep x0 |I70i| | | | | | | | | | | 313.#170 I71 Def Alloc x0 |I71a| | | | | | | | | | | 314.#171 I71 Use * Keep x0 |I71i| | | | | | | | | | | 317.#172 I72 Def Alloc x0 |I72a| | | | | | | | | | | 318.#173 I72 Use * Keep x0 |I72i| | | | | | | | | | | 321.#174 I73 Def Alloc x0 |I73a| | | | | | | | | | | 322.#175 x0 Fixd Keep x0 |I73a| | | | | | | | | | | 322.#176 I73 Use * Keep x0 |I73i| | | | | | | | | | | 323.#177 x0 Fixd Keep x0 | | | | | | | | | | | | 323.#178 I74 Def Alloc x0 |I74a| | | | | | | | | | | 325.#179 I75 Def Alloc x1 |I74a|I75a| | | | | | | | | | 326.#180 x1 Fixd Keep x1 |I74a|I75a| | | | | | | | | | 326.#181 I75 Use * Keep x1 |I74a|I75i| | | | | | | | | | 327.#182 x1 Fixd Keep x1 |I74a| | | | | | | | | | | 327.#183 I76 Def Alloc x1 |I74a|I76a| | | | | | | | | | 329.#184 I77 Def Alloc x2 |I74a|I76a|I77a| | | | | | | | | 330.#185 x2 Fixd Keep x2 |I74a|I76a|I77a| | | | | | | | | 330.#186 I77 Use * Keep x2 |I74a|I76a|I77i| | | | | | | | | 331.#187 x2 Fixd Keep x2 |I74a|I76a| | | | | | | | | | 331.#188 I78 Def Alloc x2 |I74a|I76a|I78a| | | | | | | | | 333.#189 I79 Def Alloc x3 |I74a|I76a|I78a|I79a| | | | | | | | 334.#190 x3 Fixd Keep x3 |I74a|I76a|I78a|I79a| | | | | | | | 334.#191 I79 Use * Keep x3 |I74a|I76a|I78a|I79i| | | | | | | | 335.#192 x3 Fixd Keep x3 |I74a|I76a|I78a| | | | | | | | | 335.#193 I80 Def Alloc x3 |I74a|I76a|I78a|I80a| | | | | | | | 337.#194 I81 Def Alloc x4 |I74a|I76a|I78a|I80a|I81a| | | | | | | 338.#195 x4 Fixd Keep x4 |I74a|I76a|I78a|I80a|I81a| | | | | | | 338.#196 I81 Use * Keep x4 |I74a|I76a|I78a|I80a|I81i| | | | | | | 339.#197 x4 Fixd Keep x4 |I74a|I76a|I78a|I80a| | | | | | | | 339.#198 I82 Def Alloc x4 |I74a|I76a|I78a|I80a|I82a| | | | | | | 341.#199 I83 Def Alloc x5 |I74a|I76a|I78a|I80a|I82a|I83a| | | | | | 342.#200 x5 Fixd Keep x5 |I74a|I76a|I78a|I80a|I82a|I83a| | | | | | 342.#201 I83 Use * Keep x5 |I74a|I76a|I78a|I80a|I82a|I83i| | | | | | 343.#202 x5 Fixd Keep x5 |I74a|I76a|I78a|I80a|I82a| | | | | | | 343.#203 I84 Def Alloc x5 |I74a|I76a|I78a|I80a|I82a|I84a| | | | | | 345.#204 I85 Def Alloc x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85a| | | | | 346.#205 x6 Fixd Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85a| | | | | 346.#206 I85 Use * Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a|I85i| | | | | 347.#207 x6 Fixd Keep x6 |I74a|I76a|I78a|I80a|I82a|I84a| | | | | | 347.#208 I86 Def Alloc x6 |I74a|I76a|I78a|I80a|I82a|I84a|I86a| | | | | 349.#209 I87 Def Alloc x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87a| | | | 350.#210 x7 Fixd Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87a| | | | 350.#211 I87 Use * Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I87i| | | | 351.#212 x7 Fixd Keep x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a| | | | | 351.#213 I88 Def Alloc x7 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a| | | | 353.#214 I89 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I89a| | | 354.#215 I89 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I89i| | | 357.#216 I90 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I90a| | | 358.#217 I90 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I90i| | | 361.#218 I91 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I91a| | | 366.#219 I91 Use * Keep x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I91i| | | |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a| | | | 371.#221 I92 Def Alloc x8 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#222 x0 Fixd Keep x0 |I74a|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#223 I74 Use * Keep x0 |I74i|I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#224 x1 Fixd Keep x1 | |I76a|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#225 I76 Use * Keep x1 | |I76i|I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#226 x2 Fixd Keep x2 | | |I78a|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#227 I78 Use * Keep x2 | | |I78i|I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#228 x3 Fixd Keep x3 | | | |I80a|I82a|I84a|I86a|I88a|I92a| | | 374.#229 I80 Use * Keep x3 | | | |I80i|I82a|I84a|I86a|I88a|I92a| | | 374.#230 x4 Fixd Keep x4 | | | | |I82a|I84a|I86a|I88a|I92a| | | 374.#231 I82 Use * Keep x4 | | | | |I82i|I84a|I86a|I88a|I92a| | | 374.#232 x5 Fixd Keep x5 | | | | | |I84a|I86a|I88a|I92a| | | 374.#233 I84 Use * Keep x5 | | | | | |I84i|I86a|I88a|I92a| | | 374.#234 x6 Fixd Keep x6 | | | | | | |I86a|I88a|I92a| | | 374.#235 I86 Use * Keep x6 | | | | | | |I86i|I88a|I92a| | | 374.#236 x7 Fixd Keep x7 | | | | | | | |I88a|I92a| | | 374.#237 I88 Use * Keep x7 | | | | | | | |I88i|I92a| | | 374.#238 I92 Use * Keep x8 | | | | | | | | |I92i| | | 375.#239 x0 Kill Keep x0 | | | | | | | | | | | | 375.#240 x1 Kill Keep x1 | | | | | | | | | | | | 375.#241 x2 Kill Keep x2 | | | | | | | | | | | | 375.#242 x3 Kill Keep x3 | | | | | | | | | | | | 375.#243 x4 Kill Keep x4 | | | | | | | | | | | | 375.#244 x5 Kill Keep x5 | | | | | | | | | | | | 375.#245 x6 Kill Keep x6 | | | | | | | | | | | | 375.#246 x7 Kill Keep x7 | | | | | | | | | | | | 375.#247 x8 Kill Keep x8 | | | | | | | | | | | | 375.#248 x9 Kill Keep x9 | | | | | | | | | | | | 375.#249 x10 Kill Keep x10 | | | | | | | | | | | | 375.#250 x11 Kill Keep x11 | | | | | | | | | | | | 375.#251 x12 Kill Keep x12 | | | | | | | | | | | | 375.#252 x13 Kill Keep x13 | | | | | | | | | | | | 375.#253 x14 Kill Keep x14 | | | | | | | | | | | | 375.#254 x15 Kill Keep x15 | | | | | | | | | | | | 375.#255 xip0 Kill Keep xip0 | | | | | | | | | | | | 375.#256 xip1 Kill Keep xip1 | | | | | | | | | | | | 375.#257 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | 377.#259 I93 Def Alloc x0 |I93a| | | | | | | | | | | 381.#260 C94 Def Alloc x1 |I93a|C94a| | | | | | | | | | 382.#261 I93 Use * Keep x0 |I93i|C94a| | | | | | | | | | 382.#262 C94 Use * Keep x1 | |C94i| | | | | | | | | | 385.#263 C95 Def Alloc x0 |C95a| | | | | | | | | | | 386.#264 C95 Use * Keep x0 |C95i| | | | | | | | | | | 387.#265 I96 Def Alloc x0 |I96a| | | | | | | | | | | 388.#266 I96 Use * Keep x0 |I96i| | | | | | | | | | | 389.#267 x0 Kill Keep x0 | | | | | | | | | | | | 389.#268 x1 Kill Keep x1 | | | | | | | | | | | | 389.#269 x2 Kill Keep x2 | | | | | | | | | | | | 389.#270 x3 Kill Keep x3 | | | | | | | | | | | | 389.#271 x4 Kill Keep x4 | | | | | | | | | | | | 389.#272 x5 Kill Keep x5 | | | | | | | | | | | | 389.#273 x6 Kill Keep x6 | | | | | | | | | | | | 389.#274 x7 Kill Keep x7 | | | | | | | | | | | | 389.#275 x8 Kill Keep x8 | | | | | | | | | | | | 389.#276 x9 Kill Keep x9 | | | | | | | | | | | | 389.#277 x10 Kill Keep x10 | | | | | | | | | | | | 389.#278 x11 Kill Keep x11 | | | | | | | | | | | | 389.#279 x12 Kill Keep x12 | | | | | | | | | | | | 389.#280 x13 Kill Keep x13 | | | | | | | | | | | | 389.#281 x14 Kill Keep x14 | | | | | | | | | | | | 389.#282 x15 Kill Keep x15 | | | | | | | | | | | | 389.#283 xip0 Kill Keep xip0 | | | | | | | | | | | | 389.#284 xip1 Kill Keep xip1 | | | | | | | | | | | | 389.#285 lr Kill Keep lr | | | | | | | | | | | | 389.#286 d0 Kill Keep d0 | | | | | | | | | | | | 389.#287 d1 Kill Keep d1 | | | | | | | | | | | | 389.#288 d2 Kill Keep d2 | | | | | | | | | | | | 389.#289 d3 Kill Keep d3 | | | | | | | | | | | | 389.#290 d4 Kill Keep d4 | | | | | | | | | | | | 389.#291 d5 Kill Keep d5 | | | | | | | | | | | | 389.#292 d6 Kill Keep d6 | | | | | | | | | | | | 389.#293 d7 Kill Keep d7 | | | | | | | | | | | | 389.#294 d16 Kill Keep d16 | | | | | | | | | | | | 389.#295 d17 Kill Keep d17 | | | | | | | | | | | | 389.#296 d18 Kill Keep d18 | | | | | | | | | | | | 389.#297 d19 Kill Keep d19 | | | | | | | | | | | | 389.#298 d20 Kill Keep d20 | | | | | | | | | | | | 389.#299 d21 Kill Keep d21 | | | | | | | | | | | | 389.#300 d22 Kill Keep d22 | | | | | | | | | | | | 389.#301 d23 Kill Keep d23 | | | | | | | | | | | | 389.#302 d24 Kill Keep d24 | | | | | | | | | | | | 389.#303 d25 Kill Keep d25 | | | | | | | | | | | | 389.#304 d26 Kill Keep d26 | | | | | | | | | | | | 389.#305 d27 Kill Keep d27 | | | | | | | | | | | | 389.#306 d28 Kill Keep d28 | | | | | | | | | | | | 389.#307 d29 Kill Keep d29 | | | | | | | | | | | | 389.#308 d30 Kill Keep d30 | | | | | | | | | | | | 389.#309 d31 Kill Keep d31 | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x19 |x20 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 458.#310 BB3 PredBB2 | | | | | | | | | | | | 461.#311 I97 Def Alloc x0 |I97a| | | | | | | | | | | 465.#312 I98 Def Alloc x1 |I97a|I98a| | | | | | | | | | 466.#313 I97 Use * Keep x0 |I97i|I98a| | | | | | | | | | 466.#314 I98 Use * Keep x1 | |I98i| | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 0 Total Reg Cand Vars: 0 Total number of Intervals: 98 Total number of RefPositions: 314 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: BB01 [???..???), preds={} succs={BB02} ===== N002. x0 = LCL_FLD_ADDR V39 PInvokeFrame [+8] x0 N004. x0 = PUTARG_REG; x0 N006. x1 = PHYSREG x12 N008. x1 = PUTARG_REG; x1 N010. x0 = CALL help; x0,x1 N012. V38 MEM; x0 N014. x0 = PHYSREG sp N016. V39 MEM; x0 N018. x0 = PHYSREG fp N020. V39 MEM; x0 N022. x0 = V38 MEM N024. STK = LEA(b+16); x0 N026. x1 = LCL_FLD_ADDR V39 PInvokeFrame [+8] x1 N028. STOREIND ; STK,x1 BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} ===== N032. IL_OFFSET IL offset: 0x0 N034. x0 = CNS_INT 0 N036. V17 MEM; x0 N038. NO_OP N040. x0 = V00 MEM N042. x0 = CAST ; x0 N044. CNS_INT 0 N046. x0 = NE ; x0 N048. V18 MEM; x0 N050. NO_OP N052. NO_OP N054. x0 = V01 MEM N056. x0 = CAST ; x0 N058. CNS_INT 0 N060. x0 = NE ; x0 N062. V19 MEM; x0 N064. NO_OP N066. NO_OP N068. x0 = V02 MEM N070. x0 = CAST ; x0 N072. CNS_INT 0 N074. x0 = NE ; x0 N076. V20 MEM; x0 N078. NO_OP N080. NO_OP N082. x0 = V03 MEM N084. x0 = CAST ; x0 N086. CNS_INT 0 N088. x0 = NE ; x0 N090. V21 MEM; x0 N092. NO_OP N094. NO_OP N096. x0 = V04 MEM N098. x0 = CAST ; x0 N100. CNS_INT 0 N102. x0 = NE ; x0 N104. V22 MEM; x0 N106. NO_OP N108. NO_OP N110. x0 = V05 MEM N112. x0 = CAST ; x0 N114. CNS_INT 0 N116. x0 = NE ; x0 N118. V23 MEM; x0 N120. NO_OP N122. NO_OP N124. x0 = V06 MEM N126. x0 = CAST ; x0 N128. CNS_INT 0 N130. x0 = NE ; x0 N132. V24 MEM; x0 N134. NO_OP N136. NO_OP N138. x0 = V07 MEM N140. x0 = CAST ; x0 N142. CNS_INT 0 N144. x0 = NE ; x0 N146. V25 MEM; x0 N148. NO_OP N150. NO_OP N152. x0 = V08 MEM N154. x0 = CAST ; x0 N156. CNS_INT 0 N158. x0 = NE ; x0 N160. V26 MEM; x0 N162. NO_OP N164. NO_OP N166. x0 = V09 MEM N168. x0 = CAST ; x0 N170. CNS_INT 0 N172. x0 = NE ; x0 N174. V27 MEM; x0 N176. NO_OP N178. NO_OP N180. x0 = V10 MEM N182. x0 = CAST ; x0 N184. CNS_INT 0 N186. x0 = NE ; x0 N188. V28 MEM; x0 N190. NO_OP N192. NO_OP N194. x0 = V11 MEM N196. x0 = CAST ; x0 N198. CNS_INT 0 N200. x0 = NE ; x0 N202. V29 MEM; x0 N204. NO_OP N206. NO_OP N208. x0 = V12 MEM N210. x0 = CAST ; x0 N212. CNS_INT 0 N214. x0 = NE ; x0 N216. V30 MEM; x0 N218. NO_OP N220. NO_OP N222. x0 = V13 MEM N224. x0 = CAST ; x0 N226. CNS_INT 0 N228. x0 = NE ; x0 N230. V31 MEM; x0 N232. NO_OP N234. NO_OP N236. x0 = V14 MEM N238. x0 = CAST ; x0 N240. CNS_INT 0 N242. x0 = NE ; x0 N244. V32 MEM; x0 N246. NO_OP N248. NO_OP N250. x0 = V15 MEM N252. x0 = CAST ; x0 N254. CNS_INT 0 N256. x0 = NE ; x0 N258. V33 MEM; x0 N260. NO_OP N262. NO_OP N264. x0 = V16 MEM N266. V34 MEM; x0 N268. NO_OP N270. x0 = V36 MEM N272. x1 = CNS_INT 72 N274. x1 = CAST ; x1 N276. STK = LEA(b+(i*1)+0); x0,x1 N278. x0 = IND ; STK N280. x0 = IND ; x0 N282. V37 MEM; x0 N284. x0 = V26 MEM N286. PUTARG_STK [+0x00]; x0 N288. x0 = V27 MEM N290. PUTARG_STK [+0x04]; x0 N292. x0 = V28 MEM N294. PUTARG_STK [+0x08]; x0 N296. x0 = V29 MEM N298. PUTARG_STK [+0x0c]; x0 N300. x0 = V30 MEM N302. PUTARG_STK [+0x10]; x0 N304. x0 = V31 MEM N306. PUTARG_STK [+0x14]; x0 N308. x0 = V32 MEM N310. PUTARG_STK [+0x18]; x0 N312. x0 = V33 MEM N314. PUTARG_STK [+0x1c]; x0 N316. x0 = V34 MEM N318. PUTARG_STK [+0x20]; x0 N320. x0 = V18 MEM N322. x0 = PUTARG_REG; x0 N324. x1 = V19 MEM N326. x1 = PUTARG_REG; x1 N328. x2 = V20 MEM N330. x2 = PUTARG_REG; x2 N332. x3 = V21 MEM N334. x3 = PUTARG_REG; x3 N336. x4 = V22 MEM N338. x4 = PUTARG_REG; x4 N340. x5 = V23 MEM N342. x5 = PUTARG_REG; x5 N344. x6 = V24 MEM N346. x6 = PUTARG_REG; x6 N348. x7 = V25 MEM N350. x7 = PUTARG_REG; x7 N352. x8 = V36 MEM N354. V39 MEM; x8 N356. x8 = LABEL N358. V39 MEM; x8 N360. x8 = V38 MEM N362. STK = LEA(b+12); x8 N364. CNS_INT 0 N366. STOREIND ; STK N368. START_PREEMPTGC N370. x8 = V37 MEM N372. PINVOKE_PROLOG N374. CALL ind unman popargs; x0,x1,x2,x3,x4,x5,x6,x7,x8 N376. x0 = V38 MEM N378. STK = LEA(b+12); x0 N380. x1 = CNS_INT 1 N382. STOREIND ; STK,x1 N384. x0 = CNS_INT(h) 0x1021dd928 ftn N386. x0 = IND ; x0 N388. RETURNTRAP; x0 N390. NO_OP N392. NO_OP N394. NO_OP N396. NO_OP N398. NO_OP N400. NO_OP N402. NO_OP N404. NO_OP N406. NO_OP N408. NO_OP N410. NO_OP N412. NO_OP N414. NO_OP N416. NO_OP N418. NO_OP N420. NO_OP N422. NO_OP N424. NO_OP N426. NO_OP N428. NO_OP N430. NO_OP N432. NO_OP N434. NO_OP N436. NO_OP N438. NO_OP N440. NO_OP N442. NO_OP N444. NO_OP N446. NO_OP N448. NO_OP N450. NO_OP N452. NO_OP N454. NO_OP N456. NO_OP BB03 [???..???) (return), preds={BB02} succs={} ===== N460. x0 = V38 MEM N462. STK = LEA(b+16); x0 N464. x1 = V39 MEM N466. STOREIND ; STK,x1 N468. RETURN *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0001] 1 1 [???..???) keep i internal label target LIR BB02 [0000] 1 BB01 1 [000..112)-> BB03 (always) i hascall gcsafe LIR BB03 [0002] 1 BB02 1 [???..???) (return) keep internal target hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Modified regs: [x0-xip1 lr d0-d7 d16-d31] Marking regs modified: [x19-x28] ([x0-xip1 lr d0-d7 d16-d31] => [x0-xip1 x19-x28 lr d0-d7 d16-d31]) Callee-saved registers pushed: 12 [x19-x28 fp lr] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false Assign V00 arg0, size=4, stkOffs=-0x54 Assign V01 arg1, size=4, stkOffs=-0x58 Assign V02 arg2, size=4, stkOffs=-0x5c Assign V03 arg3, size=4, stkOffs=-0x60 Assign V04 arg4, size=4, stkOffs=-0x64 Assign V05 arg5, size=4, stkOffs=-0x68 Assign V06 arg6, size=4, stkOffs=-0x6c Assign V07 arg7, size=4, stkOffs=-0x70 Assign V17 loc0, size=4, stkOffs=-0x74 Assign V18 loc1, size=4, stkOffs=-0x78 Assign V19 loc2, size=4, stkOffs=-0x7c Assign V20 loc3, size=4, stkOffs=-0x80 Assign V21 loc4, size=4, stkOffs=-0x84 Assign V22 loc5, size=4, stkOffs=-0x88 Assign V23 loc6, size=4, stkOffs=-0x8c Assign V24 loc7, size=4, stkOffs=-0x90 Assign V25 loc8, size=4, stkOffs=-0x94 Assign V26 loc9, size=4, stkOffs=-0x98 Assign V27 loc10, size=4, stkOffs=-0x9c Assign V28 loc11, size=4, stkOffs=-0xa0 Assign V29 loc12, size=4, stkOffs=-0xa4 Assign V30 loc13, size=4, stkOffs=-0xa8 Assign V31 loc14, size=4, stkOffs=-0xac Assign V32 loc15, size=4, stkOffs=-0xb0 Assign V33 loc16, size=4, stkOffs=-0xb4 Pad V34 loc17, size=8, stkOffs=-0xb8, pad=4 Assign V34 loc17, size=8, stkOffs=-0xc0 Assign V37 tmp2, size=8, stkOffs=-0xc8 Assign V38 FramesRoot, size=8, stkOffs=-0xd0 Assign V36 tmp1, size=8, stkOffs=-0xd8 Assign V39 PInvokeFrame, size=72, stkOffs=-0x120 Assign V35 OutArgs, size=40, stkOffs=-0x158 --- delta bump 312 for RBP frame --- virtual stack offset to actual stack offset delta is 312 -- V00 was -84, now 228 -- V01 was -88, now 224 -- V02 was -92, now 220 -- V03 was -96, now 216 -- V04 was -100, now 212 -- V05 was -104, now 208 -- V06 was -108, now 204 -- V07 was -112, now 200 -- V08 was 0, now 312 -- V09 was 1, now 313 -- V10 was 2, now 314 -- V11 was 3, now 315 -- V12 was 4, now 316 -- V13 was 5, now 317 -- V14 was 6, now 318 -- V15 was 7, now 319 -- V16 was 8, now 320 -- V17 was -116, now 196 -- V18 was -120, now 192 -- V19 was -124, now 188 -- V20 was -128, now 184 -- V21 was -132, now 180 -- V22 was -136, now 176 -- V23 was -140, now 172 -- V24 was -144, now 168 -- V25 was -148, now 164 -- V26 was -152, now 160 -- V27 was -156, now 156 -- V28 was -160, now 152 -- V29 was -164, now 148 -- V30 was -168, now 144 -- V31 was -172, now 140 -- V32 was -176, now 136 -- V33 was -180, now 132 -- V34 was -192, now 120 -- V35 was -344, now -32 -- V36 was -216, now 96 -- V37 was -200, now 112 -- V38 was -208, now 104 -- V39 was -288, now 24 ; Final local variable assignments ; ; V00 arg0 [V00 ] ( 1, 1 ) bool -> [fp+0xE4] ; V01 arg1 [V01 ] ( 1, 1 ) bool -> [fp+0xE0] ; V02 arg2 [V02 ] ( 1, 1 ) bool -> [fp+0xDC] ; V03 arg3 [V03 ] ( 1, 1 ) bool -> [fp+0xD8] ; V04 arg4 [V04 ] ( 1, 1 ) bool -> [fp+0xD4] ; V05 arg5 [V05 ] ( 1, 1 ) bool -> [fp+0xD0] ; V06 arg6 [V06 ] ( 1, 1 ) bool -> [fp+0xCC] ; V07 arg7 [V07 ] ( 1, 1 ) bool -> [fp+0xC8] ; V08 arg8 [V08 ] ( 1, 1 ) bool -> [fp+0x138] ; V09 arg9 [V09 ] ( 1, 1 ) bool -> [fp+0x139] ; V10 arg10 [V10 ] ( 1, 1 ) bool -> [fp+0x13A] ; V11 arg11 [V11 ] ( 1, 1 ) bool -> [fp+0x13B] ; V12 arg12 [V12 ] ( 1, 1 ) bool -> [fp+0x13C] ; V13 arg13 [V13 ] ( 1, 1 ) bool -> [fp+0x13D] ; V14 arg14 [V14 ] ( 1, 1 ) bool -> [fp+0x13E] ; V15 arg15 [V15 ] ( 1, 1 ) bool -> [fp+0x13F] ; V16 arg16 [V16 ] ( 1, 1 ) long -> [fp+0x140] ; V17 loc0 [V17 ] ( 1, 1 ) int -> [fp+0xC4] ; V18 loc1 [V18 ] ( 1, 1 ) int -> [fp+0xC0] ; V19 loc2 [V19 ] ( 1, 1 ) int -> [fp+0xBC] ; V20 loc3 [V20 ] ( 1, 1 ) int -> [fp+0xB8] ; V21 loc4 [V21 ] ( 1, 1 ) int -> [fp+0xB4] ; V22 loc5 [V22 ] ( 1, 1 ) int -> [fp+0xB0] ; V23 loc6 [V23 ] ( 1, 1 ) int -> [fp+0xAC] ; V24 loc7 [V24 ] ( 1, 1 ) int -> [fp+0xA8] ; V25 loc8 [V25 ] ( 1, 1 ) int -> [fp+0xA4] ; V26 loc9 [V26 ] ( 1, 1 ) int -> [fp+0xA0] ; V27 loc10 [V27 ] ( 1, 1 ) int -> [fp+0x9C] ; V28 loc11 [V28 ] ( 1, 1 ) int -> [fp+0x98] ; V29 loc12 [V29 ] ( 1, 1 ) int -> [fp+0x94] ; V30 loc13 [V30 ] ( 1, 1 ) int -> [fp+0x90] ; V31 loc14 [V31 ] ( 1, 1 ) int -> [fp+0x8C] ; V32 loc15 [V32 ] ( 1, 1 ) int -> [fp+0x88] ; V33 loc16 [V33 ] ( 1, 1 ) int -> [fp+0x84] ; V34 loc17 [V34 ] ( 1, 1 ) long -> [fp+0x78] ; V35 OutArgs [V35 ] ( 1, 1 ) lclBlk (40) [sp+0x00] "OutgoingArgSpace" ; V36 tmp1 [V36 ] ( 1, 1 ) long -> [fp+0x60] do-not-enreg[X] addr-exposed "stub argument" ; V37 tmp2 [V37 ] ( 1, 1 ) long -> [fp+0x70] "impImportIndirectCall" ; V38 FramesRoot [V38 ] ( 1, 1 ) long -> [fp+0x68] "Pinvoke FrameListRoot" ; V39 PInvokeFrame [V39 ] ( 1, 1 ) blk (72) [fp+0x18] do-not-enreg[X] addr-exposed "Pinvoke FrameVar" ; ; Lcl frame size = 256 Setting stack level from -572662307 to 0 =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030070: keep i internal label target LIR BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: {} Live regs: (unchanged) 0000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M42597_BB01: Label: IG02, GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Generating: N002 ( 3, 3) [000240] ------------ t240 = LCL_FLD_ADDR long V39 PInvokeFrame [+8] x0 REG x0 IN0001: add x0, fp, #32 /--* t240 long Generating: N004 (???,???) [000254] ------------ t254 = * PUTARG_REG long REG x0 Generating: N006 ( 1, 1) [000241] ------------ t241 = PHYSREG long x12 REG x1 IN0002: mov x1, x12 /--* t241 long Generating: N008 (???,???) [000255] ------------ t255 = * PUTARG_REG long REG x1 /--* t254 long arg0 in x0 +--* t255 long arg1 in x1 Generating: N010 ( 18, 8) [000242] --C-G------- t242 = * CALL help long HELPER.CORINFO_HELP_INIT_PINVOKE_FRAME REG x0 NoGC Call: savedSet=5FF86FFF {x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x13 x14 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 lr} Call: GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN0003: bl CORINFO_HELP_INIT_PINVOKE_FRAME /--* t242 long Generating: N012 ( 19, 9) [000243] D-C-G------- * STORE_LCL_VAR long V38 FramesRoot NA REG NA IN0004: str x0, [fp,#104] // [V38 FramesRoot] Generating: N014 ( 1, 1) [000247] ------------ t247 = PHYSREG long sp REG x0 IN0005: mov x0, sp /--* t247 long Generating: N016 ( 2, 2) [000246] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+40] NA REG NA IN0006: str x0, [fp,#64] // [V39 PInvokeFrame+0x28] Generating: N018 ( 1, 1) [000249] ------------ t249 = PHYSREG long fp REG x0 IN0007: mov x0, fp /--* t249 long Generating: N020 ( 2, 2) [000248] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+56] NA REG NA IN0008: str x0, [fp,#80] // [V39 PInvokeFrame+0x38] Generating: N022 ( 3, 2) [000250] ------------ t250 = LCL_VAR long V38 FramesRoot x0 REG x0 IN0009: ldr x0, [fp,#104] // [V38 FramesRoot] /--* t250 long Generating: N024 ( 4, 3) [000251] -c---------- t251 = * LEA(b+16) long REG NA Generating: N026 ( 3, 3) [000252] ------------ t252 = LCL_FLD_ADDR byref V39 PInvokeFrame [+8] x1 REG x1 IN000a: add x1, fp, #32 // [V39 PInvokeFrame+0x08] Byref regs: 0000 {} => 0002 {x1} /--* t251 long +--* t252 byref Generating: N028 ( 8, 7) [000253] ------------ * STOREIND long REG NA Byref regs: 0002 {x1} => 0000 {} IN000b: str x1, [x0,#16] =============== Generating BB02 [000..112) -> BB03 (always), preds={BB01} succs={BB03} flags=0x00000004.40080020: i hascall gcsafe LIR BB02 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: {} Live regs: (unchanged) 0000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M42597_BB02: Generating: N032 (???,???) [000239] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N034 ( 1, 2) [000000] ------------ t0 = CNS_INT int 0 REG x0 IN000c: mov w0, #0 /--* t0 int Generating: N036 ( 5, 5) [000002] DA---------- * STORE_LCL_VAR int V17 loc0 NA REG NA IN000d: str w0, [fp,#196] // [V17 loc0] Generating: N038 ( 1, 1) [000003] ------------ NO_OP void REG NA IN000e: nop Generating: N040 ( 3, 2) [000004] ------------ t4 = LCL_VAR int V00 arg0 x0 REG x0 IN000f: ldr w0, [fp,#228] // [V00 arg0] /--* t4 int Generating: N042 ( 4, 4) [000215] ------------ t215 = * CAST int <- bool <- int REG x0 IN0010: uxtb w0, w0 Generating: N044 ( 1, 2) [000005] -c---------- t5 = CNS_INT int 0 REG NA /--* t215 int +--* t5 int Generating: N046 ( 9, 7) [000006] ------------ t6 = * NE int REG x0 IN0011: cmp w0, #0 IN0012: cset x0, ne /--* t6 int Generating: N048 ( 13, 10) [000010] DA---------- * STORE_LCL_VAR int V18 loc1 NA REG NA IN0013: str w0, [fp,#192] // [V18 loc1] Generating: N050 ( 1, 1) [000011] ------------ NO_OP void REG NA IN0014: nop Generating: N052 ( 1, 1) [000012] ------------ NO_OP void REG NA IN0015: nop Generating: N054 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V01 arg1 x0 REG x0 IN0016: ldr w0, [fp,#224] // [V01 arg1] /--* t13 int Generating: N056 ( 4, 4) [000216] ------------ t216 = * CAST int <- bool <- int REG x0 IN0017: uxtb w0, w0 Generating: N058 ( 1, 2) [000014] -c---------- t14 = CNS_INT int 0 REG NA /--* t216 int +--* t14 int Generating: N060 ( 9, 7) [000015] ------------ t15 = * NE int REG x0 IN0018: cmp w0, #0 IN0019: cset x0, ne /--* t15 int Generating: N062 ( 13, 10) [000019] DA---------- * STORE_LCL_VAR int V19 loc2 NA REG NA IN001a: str w0, [fp,#188] // [V19 loc2] Generating: N064 ( 1, 1) [000020] ------------ NO_OP void REG NA IN001b: nop Generating: N066 ( 1, 1) [000021] ------------ NO_OP void REG NA IN001c: nop Generating: N068 ( 3, 2) [000022] ------------ t22 = LCL_VAR int V02 arg2 x0 REG x0 IN001d: ldr w0, [fp,#220] // [V02 arg2] /--* t22 int Generating: N070 ( 4, 4) [000217] ------------ t217 = * CAST int <- bool <- int REG x0 IN001e: uxtb w0, w0 Generating: N072 ( 1, 2) [000023] -c---------- t23 = CNS_INT int 0 REG NA /--* t217 int +--* t23 int Generating: N074 ( 9, 7) [000024] ------------ t24 = * NE int REG x0 IN001f: cmp w0, #0 IN0020: cset x0, ne /--* t24 int Generating: N076 ( 13, 10) [000028] DA---------- * STORE_LCL_VAR int V20 loc3 NA REG NA IN0021: str w0, [fp,#184] // [V20 loc3] Generating: N078 ( 1, 1) [000029] ------------ NO_OP void REG NA IN0022: nop Generating: N080 ( 1, 1) [000030] ------------ NO_OP void REG NA IN0023: nop Generating: N082 ( 3, 2) [000031] ------------ t31 = LCL_VAR int V03 arg3 x0 REG x0 IN0024: ldr w0, [fp,#216] // [V03 arg3] /--* t31 int Generating: N084 ( 4, 4) [000218] ------------ t218 = * CAST int <- bool <- int REG x0 IN0025: uxtb w0, w0 Generating: N086 ( 1, 2) [000032] -c---------- t32 = CNS_INT int 0 REG NA /--* t218 int +--* t32 int Generating: N088 ( 9, 7) [000033] ------------ t33 = * NE int REG x0 IN0026: cmp w0, #0 IN0027: cset x0, ne /--* t33 int Generating: N090 ( 13, 10) [000037] DA---------- * STORE_LCL_VAR int V21 loc4 NA REG NA IN0028: str w0, [fp,#180] // [V21 loc4] Generating: N092 ( 1, 1) [000038] ------------ NO_OP void REG NA IN0029: nop Generating: N094 ( 1, 1) [000039] ------------ NO_OP void REG NA IN002a: nop Generating: N096 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V04 arg4 x0 REG x0 IN002b: ldr w0, [fp,#212] // [V04 arg4] /--* t40 int Generating: N098 ( 4, 4) [000219] ------------ t219 = * CAST int <- bool <- int REG x0 IN002c: uxtb w0, w0 Generating: N100 ( 1, 2) [000041] -c---------- t41 = CNS_INT int 0 REG NA /--* t219 int +--* t41 int Generating: N102 ( 9, 7) [000042] ------------ t42 = * NE int REG x0 IN002d: cmp w0, #0 IN002e: cset x0, ne /--* t42 int Generating: N104 ( 13, 10) [000046] DA---------- * STORE_LCL_VAR int V22 loc5 NA REG NA IN002f: str w0, [fp,#176] // [V22 loc5] Generating: N106 ( 1, 1) [000047] ------------ NO_OP void REG NA IN0030: nop Generating: N108 ( 1, 1) [000048] ------------ NO_OP void REG NA IN0031: nop Generating: N110 ( 3, 2) [000049] ------------ t49 = LCL_VAR int V05 arg5 x0 REG x0 IN0032: ldr w0, [fp,#208] // [V05 arg5] /--* t49 int Generating: N112 ( 4, 4) [000220] ------------ t220 = * CAST int <- bool <- int REG x0 IN0033: uxtb w0, w0 Generating: N114 ( 1, 2) [000050] -c---------- t50 = CNS_INT int 0 REG NA /--* t220 int +--* t50 int Generating: N116 ( 9, 7) [000051] ------------ t51 = * NE int REG x0 IN0034: cmp w0, #0 IN0035: cset x0, ne /--* t51 int Generating: N118 ( 13, 10) [000055] DA---------- * STORE_LCL_VAR int V23 loc6 NA REG NA IN0036: str w0, [fp,#172] // [V23 loc6] Generating: N120 ( 1, 1) [000056] ------------ NO_OP void REG NA IN0037: nop Generating: N122 ( 1, 1) [000057] ------------ NO_OP void REG NA IN0038: nop Generating: N124 ( 3, 2) [000058] ------------ t58 = LCL_VAR int V06 arg6 x0 REG x0 IN0039: ldr w0, [fp,#204] // [V06 arg6] /--* t58 int Generating: N126 ( 4, 4) [000221] ------------ t221 = * CAST int <- bool <- int REG x0 IN003a: uxtb w0, w0 Generating: N128 ( 1, 2) [000059] -c---------- t59 = CNS_INT int 0 REG NA /--* t221 int +--* t59 int Generating: N130 ( 9, 7) [000060] ------------ t60 = * NE int REG x0 IN003b: cmp w0, #0 IN003c: cset x0, ne /--* t60 int Generating: N132 ( 13, 10) [000064] DA---------- * STORE_LCL_VAR int V24 loc7 NA REG NA IN003d: str w0, [fp,#168] // [V24 loc7] Generating: N134 ( 1, 1) [000065] ------------ NO_OP void REG NA IN003e: nop Generating: N136 ( 1, 1) [000066] ------------ NO_OP void REG NA IN003f: nop Generating: N138 ( 3, 2) [000067] ------------ t67 = LCL_VAR int V07 arg7 x0 REG x0 IN0040: ldr w0, [fp,#200] // [V07 arg7] /--* t67 int Generating: N140 ( 4, 4) [000222] ------------ t222 = * CAST int <- bool <- int REG x0 IN0041: uxtb w0, w0 Generating: N142 ( 1, 2) [000068] -c---------- t68 = CNS_INT int 0 REG NA /--* t222 int +--* t68 int Generating: N144 ( 9, 7) [000069] ------------ t69 = * NE int REG x0 IN0042: cmp w0, #0 IN0043: cset x0, ne /--* t69 int Generating: N146 ( 13, 10) [000073] DA---------- * STORE_LCL_VAR int V25 loc8 NA REG NA IN0044: str w0, [fp,#164] // [V25 loc8] Generating: N148 ( 1, 1) [000074] ------------ NO_OP void REG NA IN0045: nop Generating: N150 ( 1, 1) [000075] ------------ NO_OP void REG NA IN0046: nop Generating: N152 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V08 arg8 x0 REG x0 IN0047: ldr w0, [fp,#312] // [V08 arg8] /--* t76 int Generating: N154 ( 4, 4) [000223] ------------ t223 = * CAST int <- bool <- int REG x0 IN0048: uxtb w0, w0 Generating: N156 ( 1, 2) [000077] -c---------- t77 = CNS_INT int 0 REG NA /--* t223 int +--* t77 int Generating: N158 ( 9, 7) [000078] ------------ t78 = * NE int REG x0 IN0049: cmp w0, #0 IN004a: cset x0, ne /--* t78 int Generating: N160 ( 13, 10) [000082] DA---------- * STORE_LCL_VAR int V26 loc9 NA REG NA IN004b: str w0, [fp,#160] // [V26 loc9] Generating: N162 ( 1, 1) [000083] ------------ NO_OP void REG NA IN004c: nop Generating: N164 ( 1, 1) [000084] ------------ NO_OP void REG NA IN004d: nop Generating: N166 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V09 arg9 x0 REG x0 IN004e: mov xip1, #313 IN004f: ldr w0, [fp, xip1] // [V09 arg9] /--* t85 int Generating: N168 ( 4, 4) [000224] ------------ t224 = * CAST int <- bool <- int REG x0 IN0050: uxtb w0, w0 Generating: N170 ( 1, 2) [000086] -c---------- t86 = CNS_INT int 0 REG NA /--* t224 int +--* t86 int Generating: N172 ( 9, 7) [000087] ------------ t87 = * NE int REG x0 IN0051: cmp w0, #0 IN0052: cset x0, ne /--* t87 int Generating: N174 ( 13, 10) [000091] DA---------- * STORE_LCL_VAR int V27 loc10 NA REG NA IN0053: str w0, [fp,#156] // [V27 loc10] Generating: N176 ( 1, 1) [000092] ------------ NO_OP void REG NA IN0054: nop Generating: N178 ( 1, 1) [000093] ------------ NO_OP void REG NA IN0055: nop Generating: N180 ( 3, 2) [000094] ------------ t94 = LCL_VAR int V10 arg10 x0 REG x0 IN0056: mov xip1, #314 IN0057: ldr w0, [fp, xip1] // [V10 arg10] /--* t94 int Generating: N182 ( 4, 4) [000225] ------------ t225 = * CAST int <- bool <- int REG x0 IN0058: uxtb w0, w0 Generating: N184 ( 1, 2) [000095] -c---------- t95 = CNS_INT int 0 REG NA /--* t225 int +--* t95 int Generating: N186 ( 9, 7) [000096] ------------ t96 = * NE int REG x0 IN0059: cmp w0, #0 IN005a: cset x0, ne /--* t96 int Generating: N188 ( 13, 10) [000100] DA---------- * STORE_LCL_VAR int V28 loc11 NA REG NA IN005b: str w0, [fp,#152] // [V28 loc11] Generating: N190 ( 1, 1) [000101] ------------ NO_OP void REG NA IN005c: nop Generating: N192 ( 1, 1) [000102] ------------ NO_OP void REG NA IN005d: nop Generating: N194 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V11 arg11 x0 REG x0 IN005e: mov xip1, #315 IN005f: ldr w0, [fp, xip1] // [V11 arg11] /--* t103 int Generating: N196 ( 4, 4) [000226] ------------ t226 = * CAST int <- bool <- int REG x0 IN0060: uxtb w0, w0 Generating: N198 ( 1, 2) [000104] -c---------- t104 = CNS_INT int 0 REG NA /--* t226 int +--* t104 int Generating: N200 ( 9, 7) [000105] ------------ t105 = * NE int REG x0 IN0061: cmp w0, #0 IN0062: cset x0, ne /--* t105 int Generating: N202 ( 13, 10) [000109] DA---------- * STORE_LCL_VAR int V29 loc12 NA REG NA IN0063: str w0, [fp,#148] // [V29 loc12] Generating: N204 ( 1, 1) [000110] ------------ NO_OP void REG NA IN0064: nop Generating: N206 ( 1, 1) [000111] ------------ NO_OP void REG NA IN0065: nop Generating: N208 ( 3, 2) [000112] ------------ t112 = LCL_VAR int V12 arg12 x0 REG x0 IN0066: ldr w0, [fp,#316] // [V12 arg12] /--* t112 int Generating: N210 ( 4, 4) [000227] ------------ t227 = * CAST int <- bool <- int REG x0 IN0067: uxtb w0, w0 Generating: N212 ( 1, 2) [000113] -c---------- t113 = CNS_INT int 0 REG NA /--* t227 int +--* t113 int Generating: N214 ( 9, 7) [000114] ------------ t114 = * NE int REG x0 IN0068: cmp w0, #0 IN0069: cset x0, ne /--* t114 int Generating: N216 ( 13, 10) [000118] DA---------- * STORE_LCL_VAR int V30 loc13 NA REG NA IN006a: str w0, [fp,#144] // [V30 loc13] Generating: N218 ( 1, 1) [000119] ------------ NO_OP void REG NA IN006b: nop Generating: N220 ( 1, 1) [000120] ------------ NO_OP void REG NA IN006c: nop Generating: N222 ( 3, 2) [000121] ------------ t121 = LCL_VAR int V13 arg13 x0 REG x0 IN006d: mov xip1, #317 IN006e: ldr w0, [fp, xip1] // [V13 arg13] /--* t121 int Generating: N224 ( 4, 4) [000228] ------------ t228 = * CAST int <- bool <- int REG x0 IN006f: uxtb w0, w0 Generating: N226 ( 1, 2) [000122] -c---------- t122 = CNS_INT int 0 REG NA /--* t228 int +--* t122 int Generating: N228 ( 9, 7) [000123] ------------ t123 = * NE int REG x0 IN0070: cmp w0, #0 IN0071: cset x0, ne /--* t123 int Generating: N230 ( 13, 10) [000127] DA---------- * STORE_LCL_VAR int V31 loc14 NA REG NA IN0072: str w0, [fp,#140] // [V31 loc14] Generating: N232 ( 1, 1) [000128] ------------ NO_OP void REG NA IN0073: nop Generating: N234 ( 1, 1) [000129] ------------ NO_OP void REG NA IN0074: nop Generating: N236 ( 3, 2) [000130] ------------ t130 = LCL_VAR int V14 arg14 x0 REG x0 IN0075: mov xip1, #318 IN0076: ldr w0, [fp, xip1] // [V14 arg14] /--* t130 int Generating: N238 ( 4, 4) [000229] ------------ t229 = * CAST int <- bool <- int REG x0 IN0077: uxtb w0, w0 Generating: N240 ( 1, 2) [000131] -c---------- t131 = CNS_INT int 0 REG NA /--* t229 int +--* t131 int Generating: N242 ( 9, 7) [000132] ------------ t132 = * NE int REG x0 IN0078: cmp w0, #0 IN0079: cset x0, ne /--* t132 int Generating: N244 ( 13, 10) [000136] DA---------- * STORE_LCL_VAR int V32 loc15 NA REG NA IN007a: str w0, [fp,#136] // [V32 loc15] Generating: N246 ( 1, 1) [000137] ------------ NO_OP void REG NA IN007b: nop Generating: N248 ( 1, 1) [000138] ------------ NO_OP void REG NA IN007c: nop Generating: N250 ( 3, 2) [000139] ------------ t139 = LCL_VAR int V15 arg15 x0 REG x0 IN007d: mov xip1, #319 IN007e: ldr w0, [fp, xip1] // [V15 arg15] /--* t139 int Generating: N252 ( 4, 4) [000230] ------------ t230 = * CAST int <- bool <- int REG x0 IN007f: uxtb w0, w0 Generating: N254 ( 1, 2) [000140] -c---------- t140 = CNS_INT int 0 REG NA /--* t230 int +--* t140 int Generating: N256 ( 9, 7) [000141] ------------ t141 = * NE int REG x0 IN0080: cmp w0, #0 IN0081: cset x0, ne /--* t141 int Generating: N258 ( 13, 10) [000145] DA---------- * STORE_LCL_VAR int V33 loc16 NA REG NA IN0082: str w0, [fp,#132] // [V33 loc16] Generating: N260 ( 1, 1) [000146] ------------ NO_OP void REG NA IN0083: nop Generating: N262 ( 1, 1) [000147] ------------ NO_OP void REG NA IN0084: nop Generating: N264 ( 3, 2) [000148] ------------ t148 = LCL_VAR long V16 arg16 x0 REG x0 IN0085: ldr x0, [fp,#320] // [V16 arg16] /--* t148 long Generating: N266 ( 7, 5) [000150] DA---------- * STORE_LCL_VAR long V34 loc17 NA REG NA IN0086: str x0, [fp,#120] // [V34 loc17] Generating: N268 ( 1, 1) [000151] ------------ NO_OP void REG NA IN0087: nop Generating: N270 ( 3, 2) [000169] ------------ t169 = LCL_VAR long (AX) V36 tmp1 x0 REG x0 IN0088: ldr x0, [fp,#96] // [V36 tmp1] Generating: N272 ( 1, 2) [000170] ------------ t170 = CNS_INT int 72 REG x1 IN0089: mov w1, #72 /--* t170 int Generating: N274 ( 2, 4) [000171] ------------ t171 = * CAST long <- int REG x1 IN008a: sxtw x1, w1 /--* t169 long +--* t171 long Generating: N276 ( 6, 7) [000172] -c---------- t172 = * LEA(b+(i*1)+0) long REG NA /--* t172 long Generating: N278 ( 8, 8) [000173] *--XG------- t173 = * IND long REG x0 IN008b: ldr x0, [x0, x1] /--* t173 long Generating: N280 ( 11, 10) [000174] *--XG------- t174 = * IND long REG x0 IN008c: ldr x0, [x0] /--* t174 long Generating: N282 ( 15, 13) [000176] DA-XG------- * STORE_LCL_VAR long V37 tmp2 NA REG NA IN008d: str x0, [fp,#112] // [V37 tmp2] Generating: N284 ( 3, 2) [000160] ------------ t160 = LCL_VAR int V26 loc9 x0 REG x0 G_M42597_IG02: ; offs=000000H, funclet=00, bbWeight=1 IN008e: ldr w0, [fp,#160] // [V26 loc9] /--* t160 int Generating: N286 (???,???) [000256] ------------ * PUTARG_STK [+0x00] void (4 stackByteSize), (0 byteOffset) REG NA IN008f: str w0, [sp] // [V35 OutArgs] Generating: N288 ( 3, 2) [000161] ------------ t161 = LCL_VAR int V27 loc10 x0 REG x0 IN0090: ldr w0, [fp,#156] // [V27 loc10] /--* t161 int Generating: N290 (???,???) [000257] ------------ * PUTARG_STK [+0x04] void (4 stackByteSize), (4 byteOffset) REG NA IN0091: str w0, [sp,#4] // [V35 OutArgs+0x04] Generating: N292 ( 3, 2) [000162] ------------ t162 = LCL_VAR int V28 loc11 x0 REG x0 IN0092: ldr w0, [fp,#152] // [V28 loc11] /--* t162 int Generating: N294 (???,???) [000258] ------------ * PUTARG_STK [+0x08] void (4 stackByteSize), (8 byteOffset) REG NA IN0093: str w0, [sp,#8] // [V35 OutArgs+0x08] Generating: N296 ( 3, 2) [000163] ------------ t163 = LCL_VAR int V29 loc12 x0 REG x0 IN0094: ldr w0, [fp,#148] // [V29 loc12] /--* t163 int Generating: N298 (???,???) [000259] ------------ * PUTARG_STK [+0x0c] void (4 stackByteSize), (12 byteOffset) REG NA IN0095: str w0, [sp,#12] // [V35 OutArgs+0x0c] Generating: N300 ( 3, 2) [000164] ------------ t164 = LCL_VAR int V30 loc13 x0 REG x0 IN0096: ldr w0, [fp,#144] // [V30 loc13] /--* t164 int Generating: N302 (???,???) [000260] ------------ * PUTARG_STK [+0x10] void (4 stackByteSize), (16 byteOffset) REG NA IN0097: str w0, [sp,#16] // [V35 OutArgs+0x10] Generating: N304 ( 3, 2) [000165] ------------ t165 = LCL_VAR int V31 loc14 x0 REG x0 IN0098: ldr w0, [fp,#140] // [V31 loc14] /--* t165 int Generating: N306 (???,???) [000261] ------------ * PUTARG_STK [+0x14] void (4 stackByteSize), (20 byteOffset) REG NA IN0099: str w0, [sp,#20] // [V35 OutArgs+0x14] Generating: N308 ( 3, 2) [000166] ------------ t166 = LCL_VAR int V32 loc15 x0 REG x0 IN009a: ldr w0, [fp,#136] // [V32 loc15] /--* t166 int Generating: N310 (???,???) [000262] ------------ * PUTARG_STK [+0x18] void (4 stackByteSize), (24 byteOffset) REG NA IN009b: str w0, [sp,#24] // [V35 OutArgs+0x18] Generating: N312 ( 3, 2) [000167] ------------ t167 = LCL_VAR int V33 loc16 x0 REG x0 IN009c: ldr w0, [fp,#132] // [V33 loc16] /--* t167 int Generating: N314 (???,???) [000263] ------------ * PUTARG_STK [+0x1c] void (4 stackByteSize), (28 byteOffset) REG NA IN009d: str w0, [sp,#28] // [V35 OutArgs+0x1c] Generating: N316 ( 3, 2) [000168] ------------ t168 = LCL_VAR long V34 loc17 x0 REG x0 IN009e: ldr x0, [fp,#120] // [V34 loc17] /--* t168 long Generating: N318 (???,???) [000264] ------------ * PUTARG_STK [+0x20] void (8 stackByteSize), (32 byteOffset) REG NA IN009f: str x0, [sp,#32] // [V35 OutArgs+0x20] Generating: N320 ( 3, 2) [000152] ------------ t152 = LCL_VAR int V18 loc1 x0 REG x0 IN00a0: ldr w0, [fp,#192] // [V18 loc1] /--* t152 int Generating: N322 (???,???) [000265] ------------ t265 = * PUTARG_REG int REG x0 Generating: N324 ( 3, 2) [000153] ------------ t153 = LCL_VAR int V19 loc2 x1 REG x1 IN00a1: ldr w1, [fp,#188] // [V19 loc2] /--* t153 int Generating: N326 (???,???) [000266] ------------ t266 = * PUTARG_REG int REG x1 Generating: N328 ( 3, 2) [000154] ------------ t154 = LCL_VAR int V20 loc3 x2 REG x2 IN00a2: ldr w2, [fp,#184] // [V20 loc3] /--* t154 int Generating: N330 (???,???) [000267] ------------ t267 = * PUTARG_REG int REG x2 Generating: N332 ( 3, 2) [000155] ------------ t155 = LCL_VAR int V21 loc4 x3 REG x3 IN00a3: ldr w3, [fp,#180] // [V21 loc4] /--* t155 int Generating: N334 (???,???) [000268] ------------ t268 = * PUTARG_REG int REG x3 Generating: N336 ( 3, 2) [000156] ------------ t156 = LCL_VAR int V22 loc5 x4 REG x4 IN00a4: ldr w4, [fp,#176] // [V22 loc5] /--* t156 int Generating: N338 (???,???) [000269] ------------ t269 = * PUTARG_REG int REG x4 Generating: N340 ( 3, 2) [000157] ------------ t157 = LCL_VAR int V23 loc6 x5 REG x5 IN00a5: ldr w5, [fp,#172] // [V23 loc6] /--* t157 int Generating: N342 (???,???) [000270] ------------ t270 = * PUTARG_REG int REG x5 Generating: N344 ( 3, 2) [000158] ------------ t158 = LCL_VAR int V24 loc7 x6 REG x6 IN00a6: ldr w6, [fp,#168] // [V24 loc7] /--* t158 int Generating: N346 (???,???) [000271] ------------ t271 = * PUTARG_REG int REG x6 Generating: N348 ( 3, 2) [000159] ------------ t159 = LCL_VAR int V25 loc8 x7 REG x7 IN00a7: ldr w7, [fp,#164] // [V25 loc8] /--* t159 int Generating: N350 (???,???) [000272] ------------ t272 = * PUTARG_REG int REG x7 Generating: N352 ( 3, 2) [000274] ------------ t274 = LCL_VAR long (AX) V36 tmp1 x8 REG x8 IN00a8: ldr x8, [fp,#96] // [V36 tmp1] /--* t274 long Generating: N354 ( 4, 3) [000275] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+24] NA REG NA IN00a9: str x8, [fp,#48] // [V39 PInvokeFrame+0x18] Generating: N356 ( 1, 1) [000277] ------------ t277 = LABEL long REG x8 New Basic Block BB04 [0003] created. IN00aa: adr x8, (LARGEADR)[L_M42597_BB04] /--* t277 long Generating: N358 ( 2, 2) [000276] D----------- * STORE_LCL_FLD long V39 PInvokeFrame [+48] NA REG NA IN00ab: str x8, [fp,#72] // [V39 PInvokeFrame+0x30] Generating: N360 ( 3, 2) [000278] ------------ t278 = LCL_VAR long V38 FramesRoot x8 REG x8 IN00ac: ldr x8, [fp,#104] // [V38 FramesRoot] /--* t278 long Generating: N362 ( 4, 3) [000280] -c---------- t280 = * LEA(b+12) long REG NA Generating: N364 ( 1, 2) [000279] -c---------- t279 = CNS_INT byte 0 REG NA /--* t280 long +--* t279 byte Generating: N366 ( 6, 6) [000281] ------------ * STOREIND byte REG NA IN00ad: strb wzr, [x8,#12] Generating: N368 (???,???) [000282] ------------ START_PREEMPTGC void REG NA New Basic Block BB05 [0004] created. L_M42597_BB05: G_M42597_IG03: ; offs=000234H, funclet=00, bbWeight=1 Label: IG04, GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Generating: N370 ( 3, 2) [000177] ------------ t177 = LCL_VAR long V37 tmp2 x8 REG x8 IN00ae: ldr x8, [fp,#112] // [V37 tmp2] Generating: N372 (???,???) [000273] ------------ PINVOKE_PROLOG void REG NA /--* t265 int arg0 in x0 +--* t266 int arg1 in x1 +--* t267 int arg2 in x2 +--* t268 int arg3 in x3 +--* t269 int arg4 in x4 +--* t270 int arg5 in x5 +--* t271 int arg6 in x6 +--* t272 int arg7 in x7 +--* t177 long calli tgt Generating: N374 ( 98, 55) [000178] --CXG------- * CALL ind unman popargs void REG NA New Basic Block BB06 [0005] created. L_M42597_BB06: G_M42597_IG04: ; offs=0002B8H, funclet=00, bbWeight=1 Label: IG05, GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Call: GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN00af: blr x8 L_M42597_BB04: G_M42597_IG05: ; offs=0002BCH, funclet=00, bbWeight=1 Generating: N376 ( 3, 2) [000283] ------------ t283 = LCL_VAR long V38 FramesRoot x0 REG x0 IN00b0: ldr x0, [fp,#104] // [V38 FramesRoot] /--* t283 long Generating: N378 ( 4, 3) [000285] -c---------- t285 = * LEA(b+12) long REG NA Generating: N380 ( 1, 2) [000284] ------------ t284 = CNS_INT byte 1 REG x1 IN00b1: mov w1, #1 /--* t285 long +--* t284 byte Generating: N382 ( 6, 6) [000286] ------------ * STOREIND byte REG NA IN00b2: strb w1, [x0,#12] Generating: N384 ( 3, 12) [000287] H----------- t287 = CNS_INT(h) long 0x1021dd928 ftn REG x0 IN00b3: movz x0, #0xd928 IN00b4: movk x0, #541 LSL #16 IN00b5: movk x0, #1 LSL #32 /--* t287 long Generating: N386 ( 6, 14) [000288] ------------ t288 = * IND int REG x0 IN00b6: ldr w0, [x0] /--* t288 int Generating: N388 ( 7, 15) [000289] ------------ * RETURNTRAP int REG NA IN00b7: cmp w0, #0 New Basic Block BB07 [0006] created. IN00b8: beq (LARGEJMP)L_M42597_BB07 Call: GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN00b9: bl CORINFO_HELP_STOP_FOR_GC L_M42597_BB07: G_M42597_IG06: ; offs=0002C0H, funclet=00, bbWeight=1 Label: IG07, GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Generating: N390 ( 1, 1) [000179] ------------ NO_OP void REG NA IN00ba: nop Generating: N392 ( 1, 1) [000180] ------------ NO_OP void REG NA IN00bb: nop Generating: N394 ( 1, 1) [000181] ------------ NO_OP void REG NA IN00bc: nop Generating: N396 ( 1, 1) [000182] ------------ NO_OP void REG NA IN00bd: nop Generating: N398 ( 1, 1) [000183] ------------ NO_OP void REG NA IN00be: nop Generating: N400 ( 1, 1) [000184] ------------ NO_OP void REG NA IN00bf: nop Generating: N402 ( 1, 1) [000185] ------------ NO_OP void REG NA IN00c0: nop Generating: N404 ( 1, 1) [000186] ------------ NO_OP void REG NA IN00c1: nop Generating: N406 ( 1, 1) [000187] ------------ NO_OP void REG NA IN00c2: nop Generating: N408 ( 1, 1) [000188] ------------ NO_OP void REG NA IN00c3: nop Generating: N410 ( 1, 1) [000189] ------------ NO_OP void REG NA IN00c4: nop Generating: N412 ( 1, 1) [000190] ------------ NO_OP void REG NA IN00c5: nop Generating: N414 ( 1, 1) [000191] ------------ NO_OP void REG NA IN00c6: nop Generating: N416 ( 1, 1) [000192] ------------ NO_OP void REG NA IN00c7: nop Generating: N418 ( 1, 1) [000193] ------------ NO_OP void REG NA IN00c8: nop Generating: N420 ( 1, 1) [000194] ------------ NO_OP void REG NA IN00c9: nop Generating: N422 ( 1, 1) [000195] ------------ NO_OP void REG NA IN00ca: nop Generating: N424 ( 1, 1) [000196] ------------ NO_OP void REG NA IN00cb: nop Generating: N426 ( 1, 1) [000197] ------------ NO_OP void REG NA IN00cc: nop Generating: N428 ( 1, 1) [000198] ------------ NO_OP void REG NA IN00cd: nop Generating: N430 ( 1, 1) [000199] ------------ NO_OP void REG NA IN00ce: nop Generating: N432 ( 1, 1) [000200] ------------ NO_OP void REG NA IN00cf: nop Generating: N434 ( 1, 1) [000201] ------------ NO_OP void REG NA IN00d0: nop Generating: N436 ( 1, 1) [000202] ------------ NO_OP void REG NA IN00d1: nop Generating: N438 ( 1, 1) [000203] ------------ NO_OP void REG NA IN00d2: nop Generating: N440 ( 1, 1) [000204] ------------ NO_OP void REG NA IN00d3: nop Generating: N442 ( 1, 1) [000205] ------------ NO_OP void REG NA IN00d4: nop Generating: N444 ( 1, 1) [000206] ------------ NO_OP void REG NA IN00d5: nop Generating: N446 ( 1, 1) [000207] ------------ NO_OP void REG NA IN00d6: nop Generating: N448 ( 1, 1) [000208] ------------ NO_OP void REG NA IN00d7: nop Generating: N450 ( 1, 1) [000209] ------------ NO_OP void REG NA IN00d8: nop Generating: N452 ( 1, 1) [000210] ------------ NO_OP void REG NA IN00d9: nop Generating: N454 ( 1, 1) [000211] ------------ NO_OP void REG NA IN00da: nop Generating: N456 ( 1, 1) [000212] ------------ NO_OP void REG NA IN00db: nop IN00dc: b L_M42597_BB03 =============== Generating BB03 [???..???) (return), preds={BB02} succs={} flags=0x00000004.40020050: keep internal target hascall LIR BB03 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: {} Live regs: (unchanged) 0000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M42597_BB03: G_M42597_IG07: ; offs=0002ECH, funclet=00, bbWeight=1 Label: IG08, GCvars= {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Generating: N460 ( 3, 2) [000290] ------------ t290 = LCL_VAR long V38 FramesRoot x0 REG x0 IN00dd: ldr x0, [fp,#104] // [V38 FramesRoot] /--* t290 long Generating: N462 ( 4, 3) [000291] -c---------- t291 = * LEA(b+16) long REG NA Generating: N464 ( 3, 4) [000292] ------------ t292 = LCL_FLD byref V39 PInvokeFrame [+16] x1 REG x1 IN00de: ldr x1, [fp,#40] // [V39 PInvokeFrame+0x10] Byref regs: 0000 {} => 0002 {x1} /--* t291 long +--* t292 byref Generating: N466 ( 8, 8) [000293] ------------ * STOREIND long REG NA Byref regs: 0002 {x1} => 0000 {} IN00df: str x1, [x0,#16] Generating: N468 ( 0, 0) [000214] ------------ RETURN void REG NA Reserving epilog IG for block BB03 G_M42597_IG08: ; offs=000378H, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M42597_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG G_M42597_IG02: ; offs=000000H, size=0234H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG03: ; offs=000234H, size=0084H, extend G_M42597_IG04: ; offs=0002B8H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG05: ; offs=0002BCH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG06: ; offs=0002C0H, size=002CH, extend G_M42597_IG07: ; offs=0002ECH, size=008CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG08: ; offs=000378H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG09: ; epilog placeholder, next placeholder=, BB03 [0002], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars= {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} Liveness not changing: {} # compCycleEstimate = 401, compSizeEstimate = 306 ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) ; Final local variable assignments ; ; V00 arg0 [V00 ] ( 1, 1 ) bool -> [fp+0xE4] ; V01 arg1 [V01 ] ( 1, 1 ) bool -> [fp+0xE0] ; V02 arg2 [V02 ] ( 1, 1 ) bool -> [fp+0xDC] ; V03 arg3 [V03 ] ( 1, 1 ) bool -> [fp+0xD8] ; V04 arg4 [V04 ] ( 1, 1 ) bool -> [fp+0xD4] ; V05 arg5 [V05 ] ( 1, 1 ) bool -> [fp+0xD0] ; V06 arg6 [V06 ] ( 1, 1 ) bool -> [fp+0xCC] ; V07 arg7 [V07 ] ( 1, 1 ) bool -> [fp+0xC8] ; V08 arg8 [V08 ] ( 1, 1 ) bool -> [fp+0x138] ; V09 arg9 [V09 ] ( 1, 1 ) bool -> [fp+0x139] ; V10 arg10 [V10 ] ( 1, 1 ) bool -> [fp+0x13A] ; V11 arg11 [V11 ] ( 1, 1 ) bool -> [fp+0x13B] ; V12 arg12 [V12 ] ( 1, 1 ) bool -> [fp+0x13C] ; V13 arg13 [V13 ] ( 1, 1 ) bool -> [fp+0x13D] ; V14 arg14 [V14 ] ( 1, 1 ) bool -> [fp+0x13E] ; V15 arg15 [V15 ] ( 1, 1 ) bool -> [fp+0x13F] ; V16 arg16 [V16 ] ( 1, 1 ) long -> [fp+0x140] ; V17 loc0 [V17 ] ( 1, 1 ) int -> [fp+0xC4] ; V18 loc1 [V18 ] ( 1, 1 ) int -> [fp+0xC0] ; V19 loc2 [V19 ] ( 1, 1 ) int -> [fp+0xBC] ; V20 loc3 [V20 ] ( 1, 1 ) int -> [fp+0xB8] ; V21 loc4 [V21 ] ( 1, 1 ) int -> [fp+0xB4] ; V22 loc5 [V22 ] ( 1, 1 ) int -> [fp+0xB0] ; V23 loc6 [V23 ] ( 1, 1 ) int -> [fp+0xAC] ; V24 loc7 [V24 ] ( 1, 1 ) int -> [fp+0xA8] ; V25 loc8 [V25 ] ( 1, 1 ) int -> [fp+0xA4] ; V26 loc9 [V26 ] ( 1, 1 ) int -> [fp+0xA0] ; V27 loc10 [V27 ] ( 1, 1 ) int -> [fp+0x9C] ; V28 loc11 [V28 ] ( 1, 1 ) int -> [fp+0x98] ; V29 loc12 [V29 ] ( 1, 1 ) int -> [fp+0x94] ; V30 loc13 [V30 ] ( 1, 1 ) int -> [fp+0x90] ; V31 loc14 [V31 ] ( 1, 1 ) int -> [fp+0x8C] ; V32 loc15 [V32 ] ( 1, 1 ) int -> [fp+0x88] ; V33 loc16 [V33 ] ( 1, 1 ) int -> [fp+0x84] ; V34 loc17 [V34 ] ( 1, 1 ) long -> [fp+0x78] ; V35 OutArgs [V35 ] ( 1, 1 ) lclBlk (40) [sp+0x00] "OutgoingArgSpace" ; V36 tmp1 [V36 ] ( 1, 1 ) long -> [fp+0x60] do-not-enreg[X] addr-exposed "stub argument" ; V37 tmp2 [V37 ] ( 1, 1 ) long -> [fp+0x70] "impImportIndirectCall" ; V38 FramesRoot [V38 ] ( 1, 1 ) long -> [fp+0x68] "Pinvoke FrameListRoot" ; V39 PInvokeFrame [V39 ] ( 1, 1 ) blk (72) [fp+0x18] do-not-enreg[X] addr-exposed "Pinvoke FrameVar" ; ; Lcl frame size = 256 *************** Before prolog / epilog generation G_M42597_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG G_M42597_IG02: ; offs=000000H, size=0234H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG03: ; offs=000234H, size=0084H, extend G_M42597_IG04: ; offs=0002B8H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG05: ; offs=0002BCH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG06: ; offs=0002C0H, size=002CH, extend G_M42597_IG07: ; offs=0002ECH, size=008CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG08: ; offs=000378H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG09: ; epilog placeholder, next placeholder=, BB03 [0002], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars= {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} *************** In genFnProlog() __prolog: Save float regs: [] Save int regs: [x19-x28 fp lr] Frame type 2 (save FP/LR at bottom). #outsz=40; #framesz=352; LclFrameSize=256 IN00e0: sub sp, sp, #352 IN00e1: stp fp, lr, [sp,#40] offset=272, calleeSaveSPDelta=0 IN00e2: stp x19, x20, [sp,#272] IN00e3: stp x21, x22, [sp,#288] IN00e4: stp x23, x24, [sp,#304] IN00e5: stp x25, x26, [sp,#320] IN00e6: stp x27, x28, [sp,#336] offsetSpToSavedFp=40 IN00e7: add fp, sp, #40 IN00e8: str x12, [fp,#96] // [V36 tmp1] *************** In genFnPrologCalleeRegArgs() for int regs IN00e9: str w0, [fp,#228] // [V00 arg0] IN00ea: str w1, [fp,#224] // [V01 arg1] IN00eb: str w2, [fp,#220] // [V02 arg2] IN00ec: str w3, [fp,#216] // [V03 arg3] IN00ed: str w4, [fp,#212] // [V04 arg4] IN00ee: str w5, [fp,#208] // [V05 arg5] IN00ef: str w6, [fp,#204] // [V06 arg6] IN00f0: str w7, [fp,#200] // [V07 arg7] *************** In genEnregisterIncomingStackArgs() G_M42597_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur= {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {} Frame type 2 (save FP/LR at bottom). #outsz=40; #framesz=352; localloc? false calleeSaveSPOffset=272, calleeSaveSPDelta=0 IN00f1: ldp x27, x28, [sp,#336] IN00f2: ldp x25, x26, [sp,#320] IN00f3: ldp x23, x24, [sp,#304] IN00f4: ldp x21, x22, [sp,#288] IN00f5: ldp x19, x20, [sp,#272] IN00f6: ldp fp, lr, [sp,#40] IN00f7: add sp, sp, #352 IN00f8: ret lr G_M42597_IG09: ; offs=000384H, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M42597_IG01: ; func=00, offs=000000H, size=0044H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG G_M42597_IG02: ; offs=000044H, size=0234H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG03: ; offs=000278H, size=0084H, extend G_M42597_IG04: ; offs=0002FCH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG05: ; offs=000300H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG06: ; offs=000304H, size=002CH, extend G_M42597_IG07: ; offs=000330H, size=008CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG08: ; offs=0003BCH, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref G_M42597_IG09: ; offs=0003C8H, size=0020H, epilog, nogc, extend *************** In emitJumpDistBind() Binding: IN00aa: adr x8, (LARGEADR)[L_M42597_BB04] Binding L_M42597_BB04 to G_M42597_IG06 Estimate of fwd jump [00722210/170]: 02E8 -> 0304 = 001C Shrinking jump [00722210/170] Adjusted offset of BB04 from 02FC to 02F8 Adjusted offset of BB05 from 0300 to 02FC Adjusted offset of BB06 from 0304 to 0300 Binding: IN00b8: beq (LARGEJMP)L_M42597_BB07 Binding L_M42597_BB07 to G_M42597_IG07 Estimate of fwd jump [00722918/184]: 0320 -> 032C = 000C Shrinking jump [00722918/184] Adjusted offset of BB07 from 0330 to 0328 Binding: IN00dc: b L_M42597_BB03 Binding L_M42597_BB03 to G_M42597_IG08 Adjusted offset of BB08 from 03BC to 03B4 Adjusted offset of BB09 from 03C8 to 03C0 Total shrinkage = 8, min extra jump size = 4294967295 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x3E0 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x14) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M42597_IG01: ; func=00, offs=000000H, size=0044H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN00e0: 000000 D10583FF sub sp, sp, #352 IN00e1: 000004 A902FBFD stp fp, lr, [sp,#40] IN00e2: 000008 A91153F3 stp x19, x20, [sp,#272] IN00e3: 00000C A9125BF5 stp x21, x22, [sp,#288] IN00e4: 000010 A91363F7 stp x23, x24, [sp,#304] IN00e5: 000014 A9146BF9 stp x25, x26, [sp,#320] IN00e6: 000018 A91573FB stp x27, x28, [sp,#336] IN00e7: 00001C 9100A3FD add fp, sp, #40 IN00e8: 000020 F90033AC str x12, [fp,#96] // [V36 tmp1] IN00e9: 000024 B900E7A0 str w0, [fp,#228] // [V00 arg0] IN00ea: 000028 B900E3A1 str w1, [fp,#224] // [V01 arg1] IN00eb: 00002C B900DFA2 str w2, [fp,#220] // [V02 arg2] IN00ec: 000030 B900DBA3 str w3, [fp,#216] // [V03 arg3] IN00ed: 000034 B900D7A4 str w4, [fp,#212] // [V04 arg4] IN00ee: 000038 B900D3A5 str w5, [fp,#208] // [V05 arg5] IN00ef: 00003C B900CFA6 str w6, [fp,#204] // [V06 arg6] IN00f0: 000040 B900CBA7 str w7, [fp,#200] // [V07 arg7] ;; bbWeight=1 PerfScore 16.00 G_M42597_IG02: ; func=00, offs=000044H, size=0234H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN0001: 000044 910083A0 add x0, fp, #32 IN0002: 000048 AA0C03E1 mov x1, x12 IN0003: 00004C 97E39B13 bl CORINFO_HELP_INIT_PINVOKE_FRAME IN0004: 000050 F90037A0 str x0, [fp,#104] // [V38 FramesRoot] IN0005: 000054 910003E0 mov x0, sp IN0006: 000058 F90023A0 str x0, [fp,#64] // [V39 PInvokeFrame+0x28] IN0007: 00005C AA1D03E0 mov x0, fp IN0008: 000060 F9002BA0 str x0, [fp,#80] // [V39 PInvokeFrame+0x38] IN0009: 000064 F94037A0 ldr x0, [fp,#104] // [V38 FramesRoot] IN000a: 000068 910083A1 add x1, fp, #32 // [V39 PInvokeFrame+0x08] ; byrRegs +[x1] IN000b: 00006C F9000801 str x1, [x0,#16] IN000c: 000070 52800000 mov w0, #0 IN000d: 000074 B900C7A0 str w0, [fp,#196] // [V17 loc0] IN000e: 000078 D503201F nop IN000f: 00007C B940E7A0 ldr w0, [fp,#228] // [V00 arg0] IN0010: 000080 53001C00 uxtb w0, w0 IN0011: 000084 7100001F cmp w0, #0 IN0012: 000088 9A9F07E0 cset x0, ne IN0013: 00008C B900C3A0 str w0, [fp,#192] // [V18 loc1] IN0014: 000090 D503201F nop IN0015: 000094 D503201F nop IN0016: 000098 B940E3A0 ldr w0, [fp,#224] // [V01 arg1] IN0017: 00009C 53001C00 uxtb w0, w0 IN0018: 0000A0 7100001F cmp w0, #0 IN0019: 0000A4 9A9F07E0 cset x0, ne IN001a: 0000A8 B900BFA0 str w0, [fp,#188] // [V19 loc2] IN001b: 0000AC D503201F nop IN001c: 0000B0 D503201F nop IN001d: 0000B4 B940DFA0 ldr w0, [fp,#220] // [V02 arg2] IN001e: 0000B8 53001C00 uxtb w0, w0 IN001f: 0000BC 7100001F cmp w0, #0 IN0020: 0000C0 9A9F07E0 cset x0, ne IN0021: 0000C4 B900BBA0 str w0, [fp,#184] // [V20 loc3] IN0022: 0000C8 D503201F nop IN0023: 0000CC D503201F nop IN0024: 0000D0 B940DBA0 ldr w0, [fp,#216] // [V03 arg3] IN0025: 0000D4 53001C00 uxtb w0, w0 IN0026: 0000D8 7100001F cmp w0, #0 IN0027: 0000DC 9A9F07E0 cset x0, ne IN0028: 0000E0 B900B7A0 str w0, [fp,#180] // [V21 loc4] IN0029: 0000E4 D503201F nop IN002a: 0000E8 D503201F nop IN002b: 0000EC B940D7A0 ldr w0, [fp,#212] // [V04 arg4] IN002c: 0000F0 53001C00 uxtb w0, w0 IN002d: 0000F4 7100001F cmp w0, #0 IN002e: 0000F8 9A9F07E0 cset x0, ne IN002f: 0000FC B900B3A0 str w0, [fp,#176] // [V22 loc5] IN0030: 000100 D503201F nop IN0031: 000104 D503201F nop IN0032: 000108 B940D3A0 ldr w0, [fp,#208] // [V05 arg5] IN0033: 00010C 53001C00 uxtb w0, w0 IN0034: 000110 7100001F cmp w0, #0 IN0035: 000114 9A9F07E0 cset x0, ne IN0036: 000118 B900AFA0 str w0, [fp,#172] // [V23 loc6] IN0037: 00011C D503201F nop IN0038: 000120 D503201F nop IN0039: 000124 B940CFA0 ldr w0, [fp,#204] // [V06 arg6] IN003a: 000128 53001C00 uxtb w0, w0 IN003b: 00012C 7100001F cmp w0, #0 IN003c: 000130 9A9F07E0 cset x0, ne IN003d: 000134 B900ABA0 str w0, [fp,#168] // [V24 loc7] IN003e: 000138 D503201F nop IN003f: 00013C D503201F nop IN0040: 000140 B940CBA0 ldr w0, [fp,#200] // [V07 arg7] IN0041: 000144 53001C00 uxtb w0, w0 IN0042: 000148 7100001F cmp w0, #0 IN0043: 00014C 9A9F07E0 cset x0, ne IN0044: 000150 B900A7A0 str w0, [fp,#164] // [V25 loc8] IN0045: 000154 D503201F nop IN0046: 000158 D503201F nop IN0047: 00015C B9413BA0 ldr w0, [fp,#312] // [V08 arg8] IN0048: 000160 53001C00 uxtb w0, w0 IN0049: 000164 7100001F cmp w0, #0 IN004a: 000168 9A9F07E0 cset x0, ne IN004b: 00016C B900A3A0 str w0, [fp,#160] // [V26 loc9] IN004c: 000170 D503201F nop IN004d: 000174 D503201F nop IN004e: 000178 D2802731 mov xip1, #313 IN004f: 00017C B8716BA0 ldr w0, [fp, xip1] // [V09 arg9] IN0050: 000180 53001C00 uxtb w0, w0 IN0051: 000184 7100001F cmp w0, #0 IN0052: 000188 9A9F07E0 cset x0, ne IN0053: 00018C B9009FA0 str w0, [fp,#156] // [V27 loc10] IN0054: 000190 D503201F nop IN0055: 000194 D503201F nop IN0056: 000198 D2802751 mov xip1, #314 IN0057: 00019C B8716BA0 ldr w0, [fp, xip1] // [V10 arg10] IN0058: 0001A0 53001C00 uxtb w0, w0 IN0059: 0001A4 7100001F cmp w0, #0 IN005a: 0001A8 9A9F07E0 cset x0, ne IN005b: 0001AC B9009BA0 str w0, [fp,#152] // [V28 loc11] IN005c: 0001B0 D503201F nop IN005d: 0001B4 D503201F nop IN005e: 0001B8 D2802771 mov xip1, #315 IN005f: 0001BC B8716BA0 ldr w0, [fp, xip1] // [V11 arg11] IN0060: 0001C0 53001C00 uxtb w0, w0 IN0061: 0001C4 7100001F cmp w0, #0 IN0062: 0001C8 9A9F07E0 cset x0, ne IN0063: 0001CC B90097A0 str w0, [fp,#148] // [V29 loc12] IN0064: 0001D0 D503201F nop IN0065: 0001D4 D503201F nop IN0066: 0001D8 B9413FA0 ldr w0, [fp,#316] // [V12 arg12] IN0067: 0001DC 53001C00 uxtb w0, w0 IN0068: 0001E0 7100001F cmp w0, #0 IN0069: 0001E4 9A9F07E0 cset x0, ne IN006a: 0001E8 B90093A0 str w0, [fp,#144] // [V30 loc13] IN006b: 0001EC D503201F nop IN006c: 0001F0 D503201F nop IN006d: 0001F4 D28027B1 mov xip1, #317 IN006e: 0001F8 B8716BA0 ldr w0, [fp, xip1] // [V13 arg13] IN006f: 0001FC 53001C00 uxtb w0, w0 IN0070: 000200 7100001F cmp w0, #0 IN0071: 000204 9A9F07E0 cset x0, ne IN0072: 000208 B9008FA0 str w0, [fp,#140] // [V31 loc14] IN0073: 00020C D503201F nop IN0074: 000210 D503201F nop IN0075: 000214 D28027D1 mov xip1, #318 IN0076: 000218 B8716BA0 ldr w0, [fp, xip1] // [V14 arg14] IN0077: 00021C 53001C00 uxtb w0, w0 IN0078: 000220 7100001F cmp w0, #0 IN0079: 000224 9A9F07E0 cset x0, ne IN007a: 000228 B9008BA0 str w0, [fp,#136] // [V32 loc15] IN007b: 00022C D503201F nop IN007c: 000230 D503201F nop IN007d: 000234 D28027F1 mov xip1, #319 IN007e: 000238 B8716BA0 ldr w0, [fp, xip1] // [V15 arg15] IN007f: 00023C 53001C00 uxtb w0, w0 IN0080: 000240 7100001F cmp w0, #0 IN0081: 000244 9A9F07E0 cset x0, ne IN0082: 000248 B90087A0 str w0, [fp,#132] // [V33 loc16] IN0083: 00024C D503201F nop IN0084: 000250 D503201F nop IN0085: 000254 F940A3A0 ldr x0, [fp,#320] // [V16 arg16] IN0086: 000258 F9003FA0 str x0, [fp,#120] // [V34 loc17] IN0087: 00025C D503201F nop IN0088: 000260 F94033A0 ldr x0, [fp,#96] // [V36 tmp1] IN0089: 000264 52800901 mov w1, #72 ; byrRegs -[x1] IN008a: 000268 93407C21 sxtw x1, w1 IN008b: 00026C F8616800 ldr x0, [x0, x1] IN008c: 000270 F9400000 ldr x0, [x0] IN008d: 000274 F9003BA0 str x0, [fp,#112] // [V37 tmp2] ;; bbWeight=1 PerfScore 116.00 G_M42597_IG03: ; func=00, offs=000278H, size=0080H, isz, extend IN008e: 000278 B940A3A0 ldr w0, [fp,#160] // [V26 loc9] IN008f: 00027C B90003E0 str w0, [sp] // [V35 OutArgs] IN0090: 000280 B9409FA0 ldr w0, [fp,#156] // [V27 loc10] IN0091: 000284 B90007E0 str w0, [sp,#4] // [V35 OutArgs+0x04] IN0092: 000288 B9409BA0 ldr w0, [fp,#152] // [V28 loc11] IN0093: 00028C B9000BE0 str w0, [sp,#8] // [V35 OutArgs+0x08] IN0094: 000290 B94097A0 ldr w0, [fp,#148] // [V29 loc12] IN0095: 000294 B9000FE0 str w0, [sp,#12] // [V35 OutArgs+0x0c] IN0096: 000298 B94093A0 ldr w0, [fp,#144] // [V30 loc13] IN0097: 00029C B90013E0 str w0, [sp,#16] // [V35 OutArgs+0x10] IN0098: 0002A0 B9408FA0 ldr w0, [fp,#140] // [V31 loc14] IN0099: 0002A4 B90017E0 str w0, [sp,#20] // [V35 OutArgs+0x14] IN009a: 0002A8 B9408BA0 ldr w0, [fp,#136] // [V32 loc15] IN009b: 0002AC B9001BE0 str w0, [sp,#24] // [V35 OutArgs+0x18] IN009c: 0002B0 B94087A0 ldr w0, [fp,#132] // [V33 loc16] IN009d: 0002B4 B9001FE0 str w0, [sp,#28] // [V35 OutArgs+0x1c] IN009e: 0002B8 F9403FA0 ldr x0, [fp,#120] // [V34 loc17] IN009f: 0002BC F90013E0 str x0, [sp,#32] // [V35 OutArgs+0x20] IN00a0: 0002C0 B940C3A0 ldr w0, [fp,#192] // [V18 loc1] IN00a1: 0002C4 B940BFA1 ldr w1, [fp,#188] // [V19 loc2] IN00a2: 0002C8 B940BBA2 ldr w2, [fp,#184] // [V20 loc3] IN00a3: 0002CC B940B7A3 ldr w3, [fp,#180] // [V21 loc4] IN00a4: 0002D0 B940B3A4 ldr w4, [fp,#176] // [V22 loc5] IN00a5: 0002D4 B940AFA5 ldr w5, [fp,#172] // [V23 loc6] IN00a6: 0002D8 B940ABA6 ldr w6, [fp,#168] // [V24 loc7] IN00a7: 0002DC B940A7A7 ldr w7, [fp,#164] // [V25 loc8] IN00a8: 0002E0 F94033A8 ldr x8, [fp,#96] // [V36 tmp1] IN00a9: 0002E4 F9001BA8 str x8, [fp,#48] // [V39 PInvokeFrame+0x18] IN00aa: 0002E8 100000C8 adr x8, [G_M42597_IG06] IN00ab: 0002EC F90027A8 str x8, [fp,#72] // [V39 PInvokeFrame+0x30] IN00ac: 0002F0 F94037A8 ldr x8, [fp,#104] // [V38 FramesRoot] IN00ad: 0002F4 3900311F strb wzr, [x8,#12] ;; bbWeight=1 PerfScore 50.50 G_M42597_IG04: ; func=00, offs=0002F8H, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00ae: 0002F8 F9403BA8 ldr x8, [fp,#112] // [V37 tmp2] ;; bbWeight=1 PerfScore 2.00 G_M42597_IG05: ; func=00, offs=0002FCH, size=0004H, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00af: 0002FC D63F0100 blr x8 ; gcr arg pop 0 ;; bbWeight=1 PerfScore 1.00 G_M42597_IG06: ; func=00, offs=000300H, size=0028H, isz, extend IN00b0: 000300 F94037A0 ldr x0, [fp,#104] // [V38 FramesRoot] IN00b1: 000304 52800021 mov w1, #1 IN00b2: 000308 39003001 strb w1, [x0,#12] IN00b3: 00030C D29B2500 movz x0, #0xd928 IN00b4: 000310 F2A043A0 movk x0, #541 LSL #16 IN00b5: 000314 F2C00020 movk x0, #1 LSL #32 IN00b6: 000318 B9400000 ldr w0, [x0] IN00b7: 00031C 7100001F cmp w0, #0 IN00b8: 000320 54000040 beq G_M42597_IG07 IN00b9: 000324 97E39A61 bl CORINFO_HELP_STOP_FOR_GC ; gcr arg pop 0 ;; bbWeight=1 PerfScore 10.50 G_M42597_IG07: ; func=00, offs=000328H, size=008CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00ba: 000328 D503201F nop IN00bb: 00032C D503201F nop IN00bc: 000330 D503201F nop IN00bd: 000334 D503201F nop IN00be: 000338 D503201F nop IN00bf: 00033C D503201F nop IN00c0: 000340 D503201F nop IN00c1: 000344 D503201F nop IN00c2: 000348 D503201F nop IN00c3: 00034C D503201F nop IN00c4: 000350 D503201F nop IN00c5: 000354 D503201F nop IN00c6: 000358 D503201F nop IN00c7: 00035C D503201F nop IN00c8: 000360 D503201F nop IN00c9: 000364 D503201F nop IN00ca: 000368 D503201F nop IN00cb: 00036C D503201F nop IN00cc: 000370 D503201F nop IN00cd: 000374 D503201F nop IN00ce: 000378 D503201F nop IN00cf: 00037C D503201F nop IN00d0: 000380 D503201F nop IN00d1: 000384 D503201F nop IN00d2: 000388 D503201F nop IN00d3: 00038C D503201F nop IN00d4: 000390 D503201F nop IN00d5: 000394 D503201F nop IN00d6: 000398 D503201F nop IN00d7: 00039C D503201F nop IN00d8: 0003A0 D503201F nop IN00d9: 0003A4 D503201F nop IN00da: 0003A8 D503201F nop IN00db: 0003AC D503201F nop IN00dc: 0003B0 14000001 b G_M42597_IG08 ;; bbWeight=1 PerfScore 18.00 G_M42597_IG08: ; func=00, offs=0003B4H, size=000CH, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00dd: 0003B4 F94037A0 ldr x0, [fp,#104] // [V38 FramesRoot] IN00de: 0003B8 F94017A1 ldr x1, [fp,#40] // [V39 PInvokeFrame+0x10] ; byrRegs +[x1] IN00df: 0003BC F9000801 str x1, [x0,#16] ;; bbWeight=1 PerfScore 5.00 G_M42597_IG09: ; func=00, offs=0003C0H, size=0020H, epilog, nogc, extend IN00f1: 0003C0 A95573FB ldp x27, x28, [sp,#336] IN00f2: 0003C4 A9546BF9 ldp x25, x26, [sp,#320] IN00f3: 0003C8 A95363F7 ldp x23, x24, [sp,#304] IN00f4: 0003CC A9525BF5 ldp x21, x22, [sp,#288] IN00f5: 0003D0 A95153F3 ldp x19, x20, [sp,#272] IN00f6: 0003D4 A942FBFD ldp fp, lr, [sp,#40] IN00f7: 0003D8 910583FF add sp, sp, #352 IN00f8: 0003DC D65F03C0 ret lr ;; bbWeight=1 PerfScore 7.50Allocated method code size = 992 , actual size = 992 ; Total bytes of code 992, prolog size 68, PerfScore 325.70, instruction count 248 (MethodHash=7798599a) for method ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) ; ============================================================ *************** After end code gen, before unwindEmit() G_M42597_IG01: ; func=00, offs=000000H, size=0044H, bbWeight=1 PerfScore 16.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN00e0: 000000 sub sp, sp, #352 IN00e1: 000004 stp fp, lr, [sp,#40] IN00e2: 000008 stp x19, x20, [sp,#272] IN00e3: 00000C stp x21, x22, [sp,#288] IN00e4: 000010 stp x23, x24, [sp,#304] IN00e5: 000014 stp x25, x26, [sp,#320] IN00e6: 000018 stp x27, x28, [sp,#336] IN00e7: 00001C add fp, sp, #40 IN00e8: 000020 str x12, [fp,#96] // [V36 tmp1] IN00e9: 000024 str w0, [fp,#228] // [V00 arg0] IN00ea: 000028 str w1, [fp,#224] // [V01 arg1] IN00eb: 00002C str w2, [fp,#220] // [V02 arg2] IN00ec: 000030 str w3, [fp,#216] // [V03 arg3] IN00ed: 000034 str w4, [fp,#212] // [V04 arg4] IN00ee: 000038 str w5, [fp,#208] // [V05 arg5] IN00ef: 00003C str w6, [fp,#204] // [V06 arg6] IN00f0: 000040 str w7, [fp,#200] // [V07 arg7] G_M42597_IG02: ; offs=000044H, size=0234H, bbWeight=1 PerfScore 116.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN0001: 000044 add x0, fp, #32 IN0002: 000048 mov x1, x12 IN0003: 00004C bl CORINFO_HELP_INIT_PINVOKE_FRAME IN0004: 000050 str x0, [fp,#104] // [V38 FramesRoot] IN0005: 000054 mov x0, sp IN0006: 000058 str x0, [fp,#64] // [V39 PInvokeFrame+0x28] IN0007: 00005C mov x0, fp IN0008: 000060 str x0, [fp,#80] // [V39 PInvokeFrame+0x38] IN0009: 000064 ldr x0, [fp,#104] // [V38 FramesRoot] IN000a: 000068 add x1, fp, #32 // [V39 PInvokeFrame+0x08] IN000b: 00006C str x1, [x0,#16] IN000c: 000070 mov w0, #0 IN000d: 000074 str w0, [fp,#196] // [V17 loc0] IN000e: 000078 nop IN000f: 00007C ldr w0, [fp,#228] // [V00 arg0] IN0010: 000080 uxtb w0, w0 IN0011: 000084 cmp w0, #0 IN0012: 000088 cset x0, ne IN0013: 00008C str w0, [fp,#192] // [V18 loc1] IN0014: 000090 nop IN0015: 000094 nop IN0016: 000098 ldr w0, [fp,#224] // [V01 arg1] IN0017: 00009C uxtb w0, w0 IN0018: 0000A0 cmp w0, #0 IN0019: 0000A4 cset x0, ne IN001a: 0000A8 str w0, [fp,#188] // [V19 loc2] IN001b: 0000AC nop IN001c: 0000B0 nop IN001d: 0000B4 ldr w0, [fp,#220] // [V02 arg2] IN001e: 0000B8 uxtb w0, w0 IN001f: 0000BC cmp w0, #0 IN0020: 0000C0 cset x0, ne IN0021: 0000C4 str w0, [fp,#184] // [V20 loc3] IN0022: 0000C8 nop IN0023: 0000CC nop IN0024: 0000D0 ldr w0, [fp,#216] // [V03 arg3] IN0025: 0000D4 uxtb w0, w0 IN0026: 0000D8 cmp w0, #0 IN0027: 0000DC cset x0, ne IN0028: 0000E0 str w0, [fp,#180] // [V21 loc4] IN0029: 0000E4 nop IN002a: 0000E8 nop IN002b: 0000EC ldr w0, [fp,#212] // [V04 arg4] IN002c: 0000F0 uxtb w0, w0 IN002d: 0000F4 cmp w0, #0 IN002e: 0000F8 cset x0, ne IN002f: 0000FC str w0, [fp,#176] // [V22 loc5] IN0030: 000100 nop IN0031: 000104 nop IN0032: 000108 ldr w0, [fp,#208] // [V05 arg5] IN0033: 00010C uxtb w0, w0 IN0034: 000110 cmp w0, #0 IN0035: 000114 cset x0, ne IN0036: 000118 str w0, [fp,#172] // [V23 loc6] IN0037: 00011C nop IN0038: 000120 nop IN0039: 000124 ldr w0, [fp,#204] // [V06 arg6] IN003a: 000128 uxtb w0, w0 IN003b: 00012C cmp w0, #0 IN003c: 000130 cset x0, ne IN003d: 000134 str w0, [fp,#168] // [V24 loc7] IN003e: 000138 nop IN003f: 00013C nop IN0040: 000140 ldr w0, [fp,#200] // [V07 arg7] IN0041: 000144 uxtb w0, w0 IN0042: 000148 cmp w0, #0 IN0043: 00014C cset x0, ne IN0044: 000150 str w0, [fp,#164] // [V25 loc8] IN0045: 000154 nop IN0046: 000158 nop IN0047: 00015C ldr w0, [fp,#312] // [V08 arg8] IN0048: 000160 uxtb w0, w0 IN0049: 000164 cmp w0, #0 IN004a: 000168 cset x0, ne IN004b: 00016C str w0, [fp,#160] // [V26 loc9] IN004c: 000170 nop IN004d: 000174 nop IN004e: 000178 mov xip1, #313 IN004f: 00017C ldr w0, [fp, xip1] // [V09 arg9] IN0050: 000180 uxtb w0, w0 IN0051: 000184 cmp w0, #0 IN0052: 000188 cset x0, ne IN0053: 00018C str w0, [fp,#156] // [V27 loc10] IN0054: 000190 nop IN0055: 000194 nop IN0056: 000198 mov xip1, #314 IN0057: 00019C ldr w0, [fp, xip1] // [V10 arg10] IN0058: 0001A0 uxtb w0, w0 IN0059: 0001A4 cmp w0, #0 IN005a: 0001A8 cset x0, ne IN005b: 0001AC str w0, [fp,#152] // [V28 loc11] IN005c: 0001B0 nop IN005d: 0001B4 nop IN005e: 0001B8 mov xip1, #315 IN005f: 0001BC ldr w0, [fp, xip1] // [V11 arg11] IN0060: 0001C0 uxtb w0, w0 IN0061: 0001C4 cmp w0, #0 IN0062: 0001C8 cset x0, ne IN0063: 0001CC str w0, [fp,#148] // [V29 loc12] IN0064: 0001D0 nop IN0065: 0001D4 nop IN0066: 0001D8 ldr w0, [fp,#316] // [V12 arg12] IN0067: 0001DC uxtb w0, w0 IN0068: 0001E0 cmp w0, #0 IN0069: 0001E4 cset x0, ne IN006a: 0001E8 str w0, [fp,#144] // [V30 loc13] IN006b: 0001EC nop IN006c: 0001F0 nop IN006d: 0001F4 mov xip1, #317 IN006e: 0001F8 ldr w0, [fp, xip1] // [V13 arg13] IN006f: 0001FC uxtb w0, w0 IN0070: 000200 cmp w0, #0 IN0071: 000204 cset x0, ne IN0072: 000208 str w0, [fp,#140] // [V31 loc14] IN0073: 00020C nop IN0074: 000210 nop IN0075: 000214 mov xip1, #318 IN0076: 000218 ldr w0, [fp, xip1] // [V14 arg14] IN0077: 00021C uxtb w0, w0 IN0078: 000220 cmp w0, #0 IN0079: 000224 cset x0, ne IN007a: 000228 str w0, [fp,#136] // [V32 loc15] IN007b: 00022C nop IN007c: 000230 nop IN007d: 000234 mov xip1, #319 IN007e: 000238 ldr w0, [fp, xip1] // [V15 arg15] IN007f: 00023C uxtb w0, w0 IN0080: 000240 cmp w0, #0 IN0081: 000244 cset x0, ne IN0082: 000248 str w0, [fp,#132] // [V33 loc16] IN0083: 00024C nop IN0084: 000250 nop IN0085: 000254 ldr x0, [fp,#320] // [V16 arg16] IN0086: 000258 str x0, [fp,#120] // [V34 loc17] IN0087: 00025C nop IN0088: 000260 ldr x0, [fp,#96] // [V36 tmp1] IN0089: 000264 mov w1, #72 IN008a: 000268 sxtw x1, w1 IN008b: 00026C ldr x0, [x0, x1] IN008c: 000270 ldr x0, [x0] IN008d: 000274 str x0, [fp,#112] // [V37 tmp2] G_M42597_IG03: ; offs=000278H, size=0080H, bbWeight=1 PerfScore 50.50, isz, extend IN008e: 000278 ldr w0, [fp,#160] // [V26 loc9] IN008f: 00027C str w0, [sp] // [V35 OutArgs] IN0090: 000280 ldr w0, [fp,#156] // [V27 loc10] IN0091: 000284 str w0, [sp,#4] // [V35 OutArgs+0x04] IN0092: 000288 ldr w0, [fp,#152] // [V28 loc11] IN0093: 00028C str w0, [sp,#8] // [V35 OutArgs+0x08] IN0094: 000290 ldr w0, [fp,#148] // [V29 loc12] IN0095: 000294 str w0, [sp,#12] // [V35 OutArgs+0x0c] IN0096: 000298 ldr w0, [fp,#144] // [V30 loc13] IN0097: 00029C str w0, [sp,#16] // [V35 OutArgs+0x10] IN0098: 0002A0 ldr w0, [fp,#140] // [V31 loc14] IN0099: 0002A4 str w0, [sp,#20] // [V35 OutArgs+0x14] IN009a: 0002A8 ldr w0, [fp,#136] // [V32 loc15] IN009b: 0002AC str w0, [sp,#24] // [V35 OutArgs+0x18] IN009c: 0002B0 ldr w0, [fp,#132] // [V33 loc16] IN009d: 0002B4 str w0, [sp,#28] // [V35 OutArgs+0x1c] IN009e: 0002B8 ldr x0, [fp,#120] // [V34 loc17] IN009f: 0002BC str x0, [sp,#32] // [V35 OutArgs+0x20] IN00a0: 0002C0 ldr w0, [fp,#192] // [V18 loc1] IN00a1: 0002C4 ldr w1, [fp,#188] // [V19 loc2] IN00a2: 0002C8 ldr w2, [fp,#184] // [V20 loc3] IN00a3: 0002CC ldr w3, [fp,#180] // [V21 loc4] IN00a4: 0002D0 ldr w4, [fp,#176] // [V22 loc5] IN00a5: 0002D4 ldr w5, [fp,#172] // [V23 loc6] IN00a6: 0002D8 ldr w6, [fp,#168] // [V24 loc7] IN00a7: 0002DC ldr w7, [fp,#164] // [V25 loc8] IN00a8: 0002E0 ldr x8, [fp,#96] // [V36 tmp1] IN00a9: 0002E4 str x8, [fp,#48] // [V39 PInvokeFrame+0x18] IN00aa: 0002E8 adr x8, [G_M42597_IG06] IN00ab: 0002EC str x8, [fp,#72] // [V39 PInvokeFrame+0x30] IN00ac: 0002F0 ldr x8, [fp,#104] // [V38 FramesRoot] IN00ad: 0002F4 strb wzr, [x8,#12] G_M42597_IG04: ; offs=0002F8H, size=0004H, bbWeight=1 PerfScore 2.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00ae: 0002F8 ldr x8, [fp,#112] // [V37 tmp2] G_M42597_IG05: ; offs=0002FCH, size=0004H, bbWeight=1 PerfScore 1.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00af: 0002FC blr x8 G_M42597_IG06: ; offs=000300H, size=0028H, bbWeight=1 PerfScore 10.50, isz, extend IN00b0: 000300 ldr x0, [fp,#104] // [V38 FramesRoot] IN00b1: 000304 mov w1, #1 IN00b2: 000308 strb w1, [x0,#12] IN00b3: 00030C movz x0, #0xd928 IN00b4: 000310 movk x0, #541 LSL #16 IN00b5: 000314 movk x0, #1 LSL #32 IN00b6: 000318 ldr w0, [x0] IN00b7: 00031C cmp w0, #0 IN00b8: 000320 beq G_M42597_IG07 IN00b9: 000324 bl CORINFO_HELP_STOP_FOR_GC G_M42597_IG07: ; offs=000328H, size=008CH, bbWeight=1 PerfScore 18.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00ba: 000328 nop IN00bb: 00032C nop IN00bc: 000330 nop IN00bd: 000334 nop IN00be: 000338 nop IN00bf: 00033C nop IN00c0: 000340 nop IN00c1: 000344 nop IN00c2: 000348 nop IN00c3: 00034C nop IN00c4: 000350 nop IN00c5: 000354 nop IN00c6: 000358 nop IN00c7: 00035C nop IN00c8: 000360 nop IN00c9: 000364 nop IN00ca: 000368 nop IN00cb: 00036C nop IN00cc: 000370 nop IN00cd: 000374 nop IN00ce: 000378 nop IN00cf: 00037C nop IN00d0: 000380 nop IN00d1: 000384 nop IN00d2: 000388 nop IN00d3: 00038C nop IN00d4: 000390 nop IN00d5: 000394 nop IN00d6: 000398 nop IN00d7: 00039C nop IN00d8: 0003A0 nop IN00d9: 0003A4 nop IN00da: 0003A8 nop IN00db: 0003AC nop IN00dc: 0003B0 b G_M42597_IG08 G_M42597_IG08: ; offs=0003B4H, size=000CH, bbWeight=1 PerfScore 5.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref IN00dd: 0003B4 ldr x0, [fp,#104] // [V38 FramesRoot] IN00de: 0003B8 ldr x1, [fp,#40] // [V39 PInvokeFrame+0x10] IN00df: 0003BC str x1, [x0,#16] G_M42597_IG09: ; offs=0003C0H, size=0020H, bbWeight=1 PerfScore 7.50, epilog, nogc, extend IN00f1: 0003C0 ldp x27, x28, [sp,#336] IN00f2: 0003C4 ldp x25, x26, [sp,#320] IN00f3: 0003C8 ldp x23, x24, [sp,#304] IN00f4: 0003CC ldp x21, x22, [sp,#288] IN00f5: 0003D0 ldp x19, x20, [sp,#272] IN00f6: 0003D4 ldp fp, lr, [sp,#40] IN00f7: 0003D8 add sp, sp, #352 IN00f8: 0003DC ret lr *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x0003e0 (not in unwind data) Code Words : 3 Epilog Count : 1 E bit : 0 X bit : 0 Vers : 0 Function Length : 248 (0x000f8) Actual length = 992 (0x0003e0) ---- Epilog scopes ---- ---- Scope 0 Epilog Start Offset : 240 (0x000f0) Actual offset = 960 (0x0003c0) Offset from main function begin = 960 (0x0003c0) Epilog Start Index : 2 (0x02) ---- Unwind codes ---- E2 05 add_fp 5 (0x05); add fp, sp, #40 ---- Epilog start at index 2 ---- E6 save_next E6 save_next E6 save_next E6 save_next C8 22 save_regp X#0 Z#34 (0x22); stp x19, x20, [sp, #272] 45 save_fplr #5 (0x05); stp fp, lr, [sp, #40] 16 alloc_s #22 (0x16); sub sp, sp, #352 (0x160) E4 end E4 end allocUnwindInfo(pHotCode=0x0000000281937380, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x3e0, unwindSize=0x14, pUnwindBlock=0x0000000100659592, funKind=0 (main function)) *************** In gcInfoBlockHdrSave() Set code length to 992. Set ReturnKind to Scalar. Set stack base register to fp. Set Outgoing stack arg area size to 40. Register slot id for reg x1 (byref) = 0. Set state of slot 0 at instr offset 0x6c to Live. Set state of slot 0 at instr offset 0x268 to Dead. Set state of slot 0 at instr offset 0x3bc to Live. Set state of slot 0 at instr offset 0x3e0 to Dead. Defining interruptible range: [0x44, 0x3c0). *************** Finishing PHASE Emit GC+EH tables Method code size: 992 Allocations for ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) (MethodHash=7798599a) count: 2117, size: 179554, max = 8960 allocateMemory: 196608, nraUsed: 181976 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 0 | 0.00% ASTNode | 45488 | 25.33% InstDesc | 20224 | 11.26% ImpStack | 456 | 0.25% BasicBlock | 2280 | 1.27% fgArgInfo | 1064 | 0.59% fgArgInfoPtrArr | 152 | 0.08% FlowList | 64 | 0.04% TreeStatementList | 0 | 0.00% SiScope | 0 | 0.00% DominatorMemory | 0 | 0.00% LSRA | 4488 | 2.50% LSRA_Interval | 7920 | 4.41% LSRA_RefPosition | 22680 | 12.63% Reachability | 0 | 0.00% SSA | 0 | 0.00% ValueNumber | 0 | 0.00% LvaTable | 8960 | 4.99% UnwindInfo | 56 | 0.03% hashBv | 120 | 0.07% bitset | 432 | 0.24% FixedBitVect | 40 | 0.02% Generic | 1022 | 0.57% LocalAddressVisitor | 1536 | 0.86% FieldSeqStore | 0 | 0.00% ZeroOffsetFieldMap | 40 | 0.02% ArrayInfoMap | 0 | 0.00% MemoryPhiArg | 0 | 0.00% CSE | 0 | 0.00% GC | 2668 | 1.49% CorTailCallInfo | 0 | 0.00% Inlining | 128 | 0.07% ArrayStack | 0 | 0.00% DebugInfo | 0 | 0.00% DebugOnly | 58152 | 32.39% Codegen | 1416 | 0.79% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 168 | 0.09% RangeCheck | 0 | 0.00% CopyProp | 0 | 0.00% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 0 | 0.00% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 0 | 0.00% ****** DONE compiling ILStubClass:IL_STUB_PInvoke(bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,bool,long) Process 23238 stopped * thread #1, queue = 'com.apple.main-thread', stop reason = EXC_BAD_ACCESS (code=1, address=0x1) frame #0: 0x0000000102d06f54 libGenericsNative.dylib`::GetVector128BOut(e00=true, e01=false, e02=true, e03=false, e04=true, e05=false, e06=true, e07=false, e08=true, e09=false, e10=false, e11=false, e12=false, e13=false, e14=false, e15=false, pValue=0x0000000000000001) at GenericsNative.Vector128B.cpp:84:13 81 #if defined(TARGET_XARCH) 82 _mm_storeu_si128(pValue, value); 83 #else -> 84 *pValue = value; 85 #endif 86 } 87 Target 0: (corerun) stopped. (lldb)