****** START compiling _cpblk:initialize():int (MethodHash=f85ac856)
Generating code for Windows arm64
OPTIONS: Tier-0 compilation (set COMPlus_TieredCompilation=0 to disable)
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000  7f 01 00 00 04    ldsflda      0x4000001
IL_0005  20 aa 00 00 00    ldc.i4       0xAA
IL_000a  1a                ldc.i4.4    
IL_000b  fe 12 02          unaligned.   0x2
IL_000e  fe 18             initblk     
IL_0010  7f 01 00 00 04    ldsflda      0x4000001
IL_0015  1a                ldc.i4.4    
IL_0016  58                add         
IL_0017  20 ff 00 00 00    ldc.i4       0xFF
IL_001c  1a                ldc.i4.4    
IL_001d  fe 12 02          unaligned.   0x2
IL_0020  fe 18             initblk     
IL_0022  7f 01 00 00 04    ldsflda      0x4000001
IL_0027  4a                ldind.i4    
IL_0028  20 aa aa aa aa    ldc.i4       0xAAAAAAAA
IL_002d  fe 01             ceq         
IL_002f  39 15 00 00 00    brfalse      21 (IL_0049)
IL_0034  7f 01 00 00 04    ldsflda      0x4000001
IL_0039  1a                ldc.i4.4    
IL_003a  58                add         
IL_003b  fe 12 02          unaligned.   0x2
IL_003e  4a                ldind.i4    
IL_003f  15                ldc.i4.m1   
IL_0040  fe 01             ceq         
IL_0042  39 02 00 00 00    brfalse      2 (IL_0049)
IL_0047  17                ldc.i4.1    
IL_0048  2a                ret         
IL_0049  16                ldc.i4.0    
IL_004a  2a                ret         

lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
;  V00 OutArgs        lclBlk <na>  "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for _cpblk:initialize():int
getVars() returned cVars = 0, extendOthers = true
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for _cpblk:initialize():int
Jump targets:
  IL_0049
New Basic Block BB01 [0000] created.
BB01 [000..034)
New Basic Block BB02 [0001] created.
BB02 [034..047)
New Basic Block BB03 [0002] created.
BB03 [047..049)
New Basic Block BB04 [0003] created.
BB04 [049..04B)
CLFLG_MINOPT set for method _cpblk:initialize():int
IL Code Size,Instr   75,  26, Basic Block count   4, Local Variable Num,Ref count   1,  0 for method _cpblk:initialize():int
IL Code Size,Instr   75,  26, Basic Block count   4, Local Variable Num,Ref count   1,  0 for method _cpblk:initialize():int
OPTIONS: opts.MinOpts() == true
Basic block list for '_cpblk:initialize():int'

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     
BB02 [0001]  1                             1       [034..047)-> BB04 ( cond )                     
BB03 [0002]  1                             1       [047..049)        (return)                     
BB04 [0003]  2                             1       [049..04B)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     
BB02 [0001]  1                             1       [034..047)-> BB04 ( cond )                     
BB03 [0002]  1                             1       [047..049)        (return)                     
BB04 [0003]  2                             1       [049..04B)        (return)                     
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

------------ BB02 [034..047) -> BB04 (cond), preds={} succs={BB03,BB04}

------------ BB03 [047..049) (return), preds={} succs={}

------------ BB04 [049..04B) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Profile incorporation
BBOPT not set

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation
*************** In impImport() for _cpblk:initialize():int

impImportBlockPending for BB01

Importing BB01 (PC=000) of '_cpblk:initialize():int'
    [ 0]   0 (0x000) ldsflda 04000001
    [ 1]   5 (0x005) ldc.i4 170
    [ 2]  10 (0x00a) ldc.i4.4 4
    [ 3]  11 (0x00b) unaligned. 2initblk

STMT00000 ( 0x000[E-] ... ??? )
               [000005] IA---------                         *  ASG       struct (init)
               [000003] -------N---                         +--*  BLK       struct<4>
               [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----------                         \--*  INIT_VAL  int   
               [000001] -----------                            \--*  CNS_INT   int    170

    [ 0]  16 (0x010) ldsflda 04000001
    [ 1]  21 (0x015) ldc.i4.4 4
    [ 2]  22 (0x016) add
    [ 1]  23 (0x017) ldc.i4 255
    [ 2]  28 (0x01c) ldc.i4.4 4
    [ 3]  29 (0x01d) unaligned. 2initblk

STMT00001 ( 0x010[E-] ... ??? )
               [000014] IA---------                         *  ASG       struct (init)
               [000012] -------N---                         +--*  BLK       struct<4>
               [000009] -----------                         |  \--*  ADD       long  
               [000006] H----------                         |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000008] -----------                         |     \--*  CAST      long <- int
               [000007] -----------                         |        \--*  CNS_INT   int    4
               [000013] -----------                         \--*  INIT_VAL  int   
               [000010] -----------                            \--*  CNS_INT   int    255

    [ 0]  34 (0x022) ldsflda 04000001
    [ 1]  39 (0x027) ldind.i4
    [ 1]  40 (0x028) ldc.i4 -1431655766
    [ 2]  45 (0x02d) ceq
    [ 1]  47 (0x02f) brfalse

STMT00002 ( 0x022[E-] ... ??? )
               [000019] ---XG------                         *  JTRUE     void  
               [000018] ---XG------                         \--*  NE        int   
               [000016] ---XG------                            +--*  IND       int   
               [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----------                            \--*  CNS_INT   int    -0x55555556

impImportBlockPending for BB02

impImportBlockPending for BB04

Importing BB04 (PC=073) of '_cpblk:initialize():int'
    [ 0]  73 (0x049) ldc.i4.0 0
    [ 1]  74 (0x04a) ret

STMT00003 ( 0x049[E-] ... ??? )
               [000021] -----------                         *  RETURN    int   
               [000020] -----------                         \--*  CNS_INT   int    0

Importing BB02 (PC=052) of '_cpblk:initialize():int'
    [ 0]  52 (0x034) ldsflda 04000001
    [ 1]  57 (0x039) ldc.i4.4 4
    [ 2]  58 (0x03a) add
    [ 1]  59 (0x03b) unaligned. 2ldind.i4
    [ 1]  63 (0x03f) ldc.i4.m1 -1
    [ 2]  64 (0x040) ceq
    [ 1]  66 (0x042) brfalse

STMT00004 ( 0x034[E-] ... ??? )
               [000029] ---XG------                         *  JTRUE     void  
               [000028] ---XG------                         \--*  NE        int   
               [000026] U--XG------                            +--*  IND       int   
               [000025] -----------                            |  \--*  ADD       long  
               [000022] H----------                            |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000024] -----------                            |     \--*  CAST      long <- int
               [000023] -----------                            |        \--*  CNS_INT   int    4
               [000027] -----------                            \--*  CNS_INT   int    -1

impImportBlockPending for BB03

impImportBlockPending for BB04

Importing BB03 (PC=071) of '_cpblk:initialize():int'
    [ 0]  71 (0x047) ldc.i4.1 1
    [ 1]  72 (0x048) ret

STMT00005 ( 0x047[E-] ... ??? )
               [000031] -----------                         *  RETURN    int   
               [000030] -----------                         \--*  CNS_INT   int    1

*************** Finishing PHASE Importation
Trees after Importation

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1                             1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1                             1       [047..049)        (return)                     i 
BB04 [0003]  2                             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00F )
               [000005] IA---------                         *  ASG       struct (init)
               [000003] -------N---                         +--*  BLK       struct<4>
               [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----------                         \--*  INIT_VAL  int   
               [000001] -----------                            \--*  CNS_INT   int    170

***** BB01
STMT00001 ( 0x010[E-] ... 0x021 )
               [000014] IA---------                         *  ASG       struct (init)
               [000012] -------N---                         +--*  BLK       struct<4>
               [000009] -----------                         |  \--*  ADD       long  
               [000006] H----------                         |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000008] -----------                         |     \--*  CAST      long <- int
               [000007] -----------                         |        \--*  CNS_INT   int    4
               [000013] -----------                         \--*  INIT_VAL  int   
               [000010] -----------                            \--*  CNS_INT   int    255

***** BB01
STMT00002 ( 0x022[E-] ... 0x02F )
               [000019] ---XG------                         *  JTRUE     void  
               [000018] ---XG------                         \--*  NE        int   
               [000016] ---XG------                            +--*  IND       int   
               [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----------                            \--*  CNS_INT   int    -0x55555556

------------ BB02 [034..047) -> BB04 (cond), preds={} succs={BB03,BB04}

***** BB02
STMT00004 ( 0x034[E-] ... 0x042 )
               [000029] ---XG------                         *  JTRUE     void  
               [000028] ---XG------                         \--*  NE        int   
               [000026] U--XG------                            +--*  IND       int   
               [000025] -----------                            |  \--*  ADD       long  
               [000022] H----------                            |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000024] -----------                            |     \--*  CAST      long <- int
               [000023] -----------                            |        \--*  CNS_INT   int    4
               [000027] -----------                            \--*  CNS_INT   int    -1

------------ BB03 [047..049) (return), preds={} succs={}

***** BB03
STMT00005 ( 0x047[E-] ... 0x048 )
               [000031] -----------                         *  RETURN    int   
               [000030] -----------                         \--*  CNS_INT   int    1

------------ BB04 [049..04B) (return), preds={} succs={}

***** BB04
STMT00003 ( 0x049[E-] ... 0x04A )
               [000021] -----------                         *  RETURN    int   
               [000020] -----------                         \--*  CNS_INT   int    0

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 5, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining
*************** In fgDebugCheckBBlist

*************** Finishing PHASE Morph - Inlining [no changes]

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1                             1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1                             1       [047..049)        (return)                     i 
BB04 [0003]  2                             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Compute preds

Renumbering the basic blocks for fgComputePred

*************** Before renumbering the basic blocks

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd                 weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1                             1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1                             1       [047..049)        (return)                     i 
BB04 [0003]  2                             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** After renumbering the basic blocks
=============== No blocks renumbered!
Setting edge weights for BB01 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38]

*************** Finishing PHASE Compute preds
Trees after Compute preds

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00F )
               [000005] IA---------                         *  ASG       struct (init)
               [000003] -------N---                         +--*  BLK       struct<4>
               [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----------                         \--*  INIT_VAL  int   
               [000001] -----------                            \--*  CNS_INT   int    170

***** BB01
STMT00001 ( 0x010[E-] ... 0x021 )
               [000014] IA---------                         *  ASG       struct (init)
               [000012] -------N---                         +--*  BLK       struct<4>
               [000009] -----------                         |  \--*  ADD       long  
               [000006] H----------                         |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000008] -----------                         |     \--*  CAST      long <- int
               [000007] -----------                         |        \--*  CNS_INT   int    4
               [000013] -----------                         \--*  INIT_VAL  int   
               [000010] -----------                            \--*  CNS_INT   int    255

***** BB01
STMT00002 ( 0x022[E-] ... 0x02F )
               [000019] ---XG------                         *  JTRUE     void  
               [000018] ---XG------                         \--*  NE        int   
               [000016] ---XG------                            +--*  IND       int   
               [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----------                            \--*  CNS_INT   int    -0x55555556

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

***** BB02
STMT00004 ( 0x034[E-] ... 0x042 )
               [000029] ---XG------                         *  JTRUE     void  
               [000028] ---XG------                         \--*  NE        int   
               [000026] U--XG------                            +--*  IND       int   
               [000025] -----------                            |  \--*  ADD       long  
               [000022] H----------                            |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000024] -----------                            |     \--*  CAST      long <- int
               [000023] -----------                            |        \--*  CNS_INT   int    4
               [000027] -----------                            \--*  CNS_INT   int    -1

------------ BB03 [047..049) (return), preds={BB02} succs={}

***** BB03
STMT00005 ( 0x047[E-] ... 0x048 )
               [000031] -----------                         *  RETURN    int   
               [000030] -----------                         \--*  CNS_INT   int    1

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}

***** BB04
STMT00003 ( 0x049[E-] ... 0x04A )
               [000021] -----------                         *  RETURN    int   
               [000020] -----------                         \--*  CNS_INT   int    0

-------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Morph - Promote Structs
  promotion opt flag not enabled

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x00F )
               [000005] IA---------                         *  ASG       struct (init)
               [000003] -------N---                         +--*  BLK       struct<4>
               [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----------                         \--*  INIT_VAL  int   
               [000001] -----------                            \--*  CNS_INT   int    170

LocalAddressVisitor visiting statement:
STMT00001 ( 0x010[E-] ... 0x021 )
               [000014] IA---------                         *  ASG       struct (init)
               [000012] -------N---                         +--*  BLK       struct<4>
               [000009] -----------                         |  \--*  ADD       long  
               [000006] H----------                         |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000008] -----------                         |     \--*  CAST      long <- int
               [000007] -----------                         |        \--*  CNS_INT   int    4
               [000013] -----------                         \--*  INIT_VAL  int   
               [000010] -----------                            \--*  CNS_INT   int    255

LocalAddressVisitor visiting statement:
STMT00002 ( 0x022[E-] ... 0x02F )
               [000019] ---XG------                         *  JTRUE     void  
               [000018] ---XG------                         \--*  NE        int   
               [000016] ---XG------                            +--*  IND       int   
               [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----------                            \--*  CNS_INT   int    -0x55555556

LocalAddressVisitor visiting statement:
STMT00004 ( 0x034[E-] ... 0x042 )
               [000029] ---XG------                         *  JTRUE     void  
               [000028] ---XG------                         \--*  NE        int   
               [000026] U--XG------                            +--*  IND       int   
               [000025] -----------                            |  \--*  ADD       long  
               [000022] H----------                            |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000024] -----------                            |     \--*  CAST      long <- int
               [000023] -----------                            |        \--*  CNS_INT   int    4
               [000027] -----------                            \--*  CNS_INT   int    -1

LocalAddressVisitor visiting statement:
STMT00005 ( 0x047[E-] ... 0x048 )
               [000031] -----------                         *  RETURN    int   
               [000030] -----------                         \--*  CNS_INT   int    1

LocalAddressVisitor visiting statement:
STMT00003 ( 0x049[E-] ... 0x04A )
               [000021] -----------                         *  RETURN    int   
               [000020] -----------                         \--*  CNS_INT   int    0


*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Forward Substitution

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global

*************** In fgMorphBlocks()
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Morphing BB01 of '_cpblk:initialize():int'

fgMorphTree BB01, STMT00000 (before)
               [000005] IA---------                         *  ASG       struct (init)
               [000003] -------N---                         +--*  BLK       struct<4>
               [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----------                         \--*  INIT_VAL  int   
               [000001] -----------                            \--*  CNS_INT   int    170
Notify VM instruction set (AdvSimd) must be supported.
MorphInitBlock:
MorphBlock for dst tree, before:
               [000003] n----+-N---                         *  BLK       struct<4>
               [000000] H----+-----                         \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
MorphBlock after:
               [000003] n----+-N---                         *  BLK       struct<4>
               [000000] H----+-----                         \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
PrepareDst for [000003] have not found a local var.
MorphInitBlock (after):
               [000005] IA---------                         *  ASG       struct (init)
               [000003] n----+-N---                         +--*  BLK       struct<4>
               [000000] H----+-----                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----+-----                         \--*  INIT_VAL  int   
               [000001] -----+-----                            \--*  CNS_INT   int    170

fgMorphTree BB01, STMT00001 (before)
               [000014] IA---------                         *  ASG       struct (init)
               [000012] -------N---                         +--*  BLK       struct<4>
               [000009] -----------                         |  \--*  ADD       long  
               [000006] H----------                         |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000008] -----------                         |     \--*  CAST      long <- int
               [000007] -----------                         |        \--*  CNS_INT   int    4
               [000013] -----------                         \--*  INIT_VAL  int   
               [000010] -----------                            \--*  CNS_INT   int    255
MorphInitBlock:
MorphBlock for dst tree, before:
               [000012] ---X-+-N---                         *  BLK       struct<4>
               [000009] -----+-----                         \--*  ADD       long  
               [000008] -----+-----                            +--*  CAST      long <- int
               [000007] -----+-----                            |  \--*  CNS_INT   int    4
               [000006] H----+-----                            \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
MorphBlock after:
               [000012] ---X-+-N---                         *  BLK       struct<4>
               [000009] -----+-----                         \--*  ADD       long  
               [000008] -----+-----                            +--*  CAST      long <- int
               [000007] -----+-----                            |  \--*  CNS_INT   int    4
               [000006] H----+-----                            \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
PrepareDst for [000012] have not found a local var.
MorphInitBlock (after):
               [000014] IA-X-------                         *  ASG       struct (init)
               [000012] ---X-+-N---                         +--*  BLK       struct<4>
               [000009] -----+-----                         |  \--*  ADD       long  
               [000008] -----+-----                         |     +--*  CAST      long <- int
               [000007] -----+-----                         |     |  \--*  CNS_INT   int    4
               [000006] H----+-----                         |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000013] -----+-----                         \--*  INIT_VAL  int   
               [000010] -----+-----                            \--*  CNS_INT   int    255

fgMorphTree BB01, STMT00001 (after)
               [000014] IA-X-+-----                         *  ASG       struct (init)
               [000012] ---X-+-N---                         +--*  BLK       struct<4>
               [000009] -----+-----                         |  \--*  ADD       long  
               [000008] -----+-----                         |     +--*  CAST      long <- int
               [000007] -----+-----                         |     |  \--*  CNS_INT   int    4
               [000006] H----+-----                         |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000013] -----+-----                         \--*  INIT_VAL  int   
               [000010] -----+-----                            \--*  CNS_INT   int    255

fgMorphTree BB01, STMT00002 (before)
               [000019] ---XG------                         *  JTRUE     void  
               [000018] ---XG------                         \--*  NE        int   
               [000016] ---XG------                            +--*  IND       int   
               [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----------                            \--*  CNS_INT   int    -0x55555556

Morphing BB02 of '_cpblk:initialize():int'

fgMorphTree BB02, STMT00004 (before)
               [000029] ---XG------                         *  JTRUE     void  
               [000028] ---XG------                         \--*  NE        int   
               [000026] U--XG------                            +--*  IND       int   
               [000025] -----------                            |  \--*  ADD       long  
               [000022] H----------                            |     +--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000024] -----------                            |     \--*  CAST      long <- int
               [000023] -----------                            |        \--*  CNS_INT   int    4
               [000027] -----------                            \--*  CNS_INT   int    -1

fgMorphTree BB02, STMT00004 (after)
               [000029] ---XG+-----                         *  JTRUE     void  
               [000028] J--XG+-N---                         \--*  NE        int   
               [000026] U--XG+-----                            +--*  IND       int   
               [000025] -----+-----                            |  \--*  ADD       long  
               [000024] -----+-----                            |     +--*  CAST      long <- int
               [000023] -----+-----                            |     |  \--*  CNS_INT   int    4
               [000022] H----+-----                            |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000027] -----+-----                            \--*  CNS_INT   int    -1

Morphing BB03 of '_cpblk:initialize():int'

fgMorphTree BB03, STMT00005 (before)
               [000031] -----------                         *  RETURN    int   
               [000030] -----------                         \--*  CNS_INT   int    1

Morphing BB04 of '_cpblk:initialize():int'

fgMorphTree BB04, STMT00003 (before)
               [000021] -----------                         *  RETURN    int   
               [000020] -----------                         \--*  CNS_INT   int    0

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00F )
               [000005] IA---+-----                         *  ASG       struct (init)
               [000003] n----+-N---                         +--*  BLK       struct<4>
               [000000] H----+-----                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000004] -----+-----                         \--*  INIT_VAL  int   
               [000001] -----+-----                            \--*  CNS_INT   int    170

***** BB01
STMT00001 ( 0x010[E-] ... 0x021 )
               [000014] IA-X-+-----                         *  ASG       struct (init)
               [000012] ---X-+-N---                         +--*  BLK       struct<4>
               [000009] -----+-----                         |  \--*  ADD       long  
               [000008] -----+-----                         |     +--*  CAST      long <- int
               [000007] -----+-----                         |     |  \--*  CNS_INT   int    4
               [000006] H----+-----                         |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000013] -----+-----                         \--*  INIT_VAL  int   
               [000010] -----+-----                            \--*  CNS_INT   int    255

***** BB01
STMT00002 ( 0x022[E-] ... 0x02F )
               [000019] ----G+-----                         *  JTRUE     void  
               [000018] J---G+-N---                         \--*  NE        int   
               [000016] n---G+-----                            +--*  IND       int   
               [000015] H----+-----                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000017] -----+-----                            \--*  CNS_INT   int    -0x55555556

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

***** BB02
STMT00004 ( 0x034[E-] ... 0x042 )
               [000029] ---XG+-----                         *  JTRUE     void  
               [000028] J--XG+-N---                         \--*  NE        int   
               [000026] U--XG+-----                            +--*  IND       int   
               [000025] -----+-----                            |  \--*  ADD       long  
               [000024] -----+-----                            |     +--*  CAST      long <- int
               [000023] -----+-----                            |     |  \--*  CNS_INT   int    4
               [000022] H----+-----                            |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
               [000027] -----+-----                            \--*  CNS_INT   int    -1

------------ BB03 [047..049) (return), preds={BB02} succs={}

***** BB03
STMT00005 ( 0x047[E-] ... 0x048 )
               [000031] -----+-----                         *  RETURN    int   
               [000030] -----+-----                         \--*  CNS_INT   int    1

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}

***** BB04
STMT00003 ( 0x049[E-] ... 0x04A )
               [000021] -----+-----                         *  RETURN    int   
               [000020] -----+-----                         \--*  CNS_INT   int    0

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute edge weights (1, false)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

 -- no profile data, so using default called count
 -- not optimizing or no profile data, so not computing edge weights

*************** Finishing PHASE Compute edge weights (1, false) [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00F )
     (  9, 18) [000005] IA------R--                         *  ASG       struct (init)
     (  6, 14) [000003] n------N---                         +--*  BLK       struct<4>
     (  3, 12) [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
     (  2,  3) [000004] -----------                         \--*  INIT_VAL  int   
     (  1,  2) [000001] -----------                            \--*  CNS_INT   int    170

***** BB01
STMT00001 ( 0x010[E-] ... 0x021 )
     ( 12, 23) [000014] IA-X----R--                         *  ASG       struct (init)
     (  9, 19) [000012] ---X---N---                         +--*  BLK       struct<4>
     (  6, 17) [000009] -----------                         |  \--*  ADD       long  
     (  2,  4) [000008] -----------                         |     +--*  CAST      long <- int
     (  1,  2) [000007] -----------                         |     |  \--*  CNS_INT   int    4
     (  3, 12) [000006] H----------                         |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
     (  2,  3) [000013] -----------                         \--*  INIT_VAL  int   
     (  1,  2) [000010] -----------                            \--*  CNS_INT   int    255

***** BB01
STMT00002 ( 0x022[E-] ... 0x02F )
     ( 10, 21) [000019] ----G------                         *  JTRUE     void  
     (  8, 19) [000018] J---G--N---                         \--*  NE        int   
     (  6, 14) [000016] n---G------                            +--*  IND       int   
     (  3, 12) [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
     (  1,  4) [000017] -----------                            \--*  CNS_INT   int    -0x55555556

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

***** BB02
STMT00004 ( 0x034[E-] ... 0x042 )
     ( 12, 23) [000029] ---XG------                         *  JTRUE     void  
     ( 10, 21) [000028] J--XG--N---                         \--*  NE        int   
     (  8, 18) [000026] U--XG------                            +--*  IND       int   
     (  6, 17) [000025] -------N---                            |  \--*  ADD       long  
     (  2,  4) [000024] -----------                            |     +--*  CAST      long <- int
     (  1,  2) [000023] -----------                            |     |  \--*  CNS_INT   int    4
     (  3, 12) [000022] H----------                            |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
     (  1,  2) [000027] -----------                            \--*  CNS_INT   int    -1

------------ BB03 [047..049) (return), preds={BB02} succs={}

***** BB03
STMT00005 ( 0x047[E-] ... 0x048 )
     (  2,  3) [000031] -----------                         *  RETURN    int   
     (  1,  2) [000030] -----------                         \--*  CNS_INT   int    1

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}

***** BB04
STMT00003 ( 0x049[E-] ... 0x04A )
     (  2,  3) [000021] -----------                         *  RETURN    int   
     (  1,  2) [000020] -----------                         \--*  CNS_INT   int    0

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has    8 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}

***** BB01
STMT00000 ( 0x000[E-] ... 0x00F )
N005 (  9, 18) [000005] IA------R--                         *  ASG       struct (init)
N004 (  6, 14) [000003] n------N---                         +--*  BLK       struct<4>
N003 (  3, 12) [000000] H----------                         |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
N002 (  2,  3) [000004] -----------                         \--*  INIT_VAL  int   
N001 (  1,  2) [000001] -----------                            \--*  CNS_INT   int    170

***** BB01
STMT00001 ( 0x010[E-] ... 0x021 )
N008 ( 12, 23) [000014] IA-X----R--                         *  ASG       struct (init)
N007 (  9, 19) [000012] ---X---N---                         +--*  BLK       struct<4>
N006 (  6, 17) [000009] -----------                         |  \--*  ADD       long  
N004 (  2,  4) [000008] -----------                         |     +--*  CAST      long <- int
N003 (  1,  2) [000007] -----------                         |     |  \--*  CNS_INT   int    4
N005 (  3, 12) [000006] H----------                         |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
N002 (  2,  3) [000013] -----------                         \--*  INIT_VAL  int   
N001 (  1,  2) [000010] -----------                            \--*  CNS_INT   int    255

***** BB01
STMT00002 ( 0x022[E-] ... 0x02F )
N005 ( 10, 21) [000019] ----G------                         *  JTRUE     void  
N004 (  8, 19) [000018] J---G--N---                         \--*  NE        int   
N002 (  6, 14) [000016] n---G------                            +--*  IND       int   
N001 (  3, 12) [000015] H----------                            |  \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
N003 (  1,  4) [000017] -----------                            \--*  CNS_INT   int    -0x55555556

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}

***** BB02
STMT00004 ( 0x034[E-] ... 0x042 )
N008 ( 12, 23) [000029] ---XG------                         *  JTRUE     void  
N007 ( 10, 21) [000028] J--XG--N---                         \--*  NE        int   
N005 (  8, 18) [000026] U--XG------                            +--*  IND       int   
N004 (  6, 17) [000025] -------N---                            |  \--*  ADD       long  
N002 (  2,  4) [000024] -----------                            |     +--*  CAST      long <- int
N001 (  1,  2) [000023] -----------                            |     |  \--*  CNS_INT   int    4
N003 (  3, 12) [000022] H----------                            |     \--*  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
N006 (  1,  2) [000027] -----------                            \--*  CNS_INT   int    -1

------------ BB03 [047..049) (return), preds={BB02} succs={}

***** BB03
STMT00005 ( 0x047[E-] ... 0x048 )
N002 (  2,  3) [000031] -----------                         *  RETURN    int   
N001 (  1,  2) [000030] -----------                         \--*  CNS_INT   int    1

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}

***** BB04
STMT00003 ( 0x049[E-] ... 0x04A )
N002 (  2,  3) [000021] -----------                         *  RETURN    int   
N001 (  1,  2) [000020] -----------                         \--*  CNS_INT   int    0

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR
Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y):
N001 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    170
                                                            /--*  t1     int    
N002 (  2,  3) [000004] -----------                    t4 = *  INIT_VAL  int   
N003 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N004 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init)

Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y):
N001 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    255
                                                            /--*  t10    int    
N002 (  2,  3) [000013] -----------                   t13 = *  INIT_VAL  int   
N003 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4
                                                            /--*  t7     int    
N004 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int
N005 (  3, 12) [000006] H----------                    t6 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t8     long   
                                                            +--*  t6     long   
N006 (  6, 17) [000009] -----------                    t9 = *  ADD       long  
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N007 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init)


*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
               [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    170
                                                            /--*  t1     int    
N002 (  2,  3) [000004] -----------                    t4 = *  INIT_VAL  int   
N003 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N004 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init)
               [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-]
N001 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    255
                                                            /--*  t10    int    
N002 (  2,  3) [000013] -----------                   t13 = *  INIT_VAL  int   
N003 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4
                                                            /--*  t7     int    
N004 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int
N005 (  3, 12) [000006] H----------                    t6 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t8     long   
                                                            +--*  t6     long   
N006 (  6, 17) [000009] -----------                    t9 = *  ADD       long  
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N007 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init)
               [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-]
N001 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t15    long   
N002 (  6, 14) [000016] n---G------                   t16 = *  IND       int   
N003 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556
                                                            /--*  t16    int    
                                                            +--*  t17    int    
N004 (  8, 19) [000018] J---G--N---                   t18 = *  NE        int   
                                                            /--*  t18    int    
N005 ( 10, 21) [000019] ----G------                         *  JTRUE     void  

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
               [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-]
N001 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4
                                                            /--*  t23    int    
N002 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int
N003 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t24    long   
                                                            +--*  t22    long   
N004 (  6, 17) [000025] -------N---                   t25 = *  ADD       long  
                                                            /--*  t25    long   
N005 (  8, 18) [000026] U--XG------                   t26 = *  IND       int   
N006 (  1,  2) [000027] -----------                   t27 =    CNS_INT   int    -1
                                                            /--*  t26    int    
                                                            +--*  t27    int    
N007 ( 10, 21) [000028] J--XG--N---                   t28 = *  NE        int   
                                                            /--*  t28    int    
N008 ( 12, 23) [000029] ---XG------                         *  JTRUE     void  

------------ BB03 [047..049) (return), preds={BB02} succs={}
               [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-]
N001 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1
                                                            /--*  t30    int    
N002 (  2,  3) [000031] -----------                         *  RETURN    int   

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}
               [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-]
N001 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0
                                                            /--*  t20    int    
N002 (  2,  3) [000021] -----------                         *  RETURN    int   

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Do 'simple' lowering

*************** Finishing PHASE Do 'simple' lowering [no changes]

*************** Starting PHASE Lowering nodeinfo
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
LowerCast for: N004 (  2,  4) [000008] -----------                         *  CAST      long <- int

LowerCast for: N002 (  2,  4) [000024] -----------                         *  CAST      long <- int

Addressing mode:
  Base
    N002 (  2,  4) [000024] -----------                         *  CAST      long <- int
  + Index * 1 + 0
    N003 (  3, 12) [000022] H----------                         *  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
New addressing mode node:
  N004 (  6, 17) [000025] -----------                         *  LEA(b+(i*1)+0) long  

lowering GT_RETURN
N002 (  2,  3) [000031] -----------                         *  RETURN    int   
============lowering GT_RETURN
N002 (  2,  3) [000021] -----------                         *  RETURN    int   
============Lower has completed modifying nodes.

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
               [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    0xAAAAAAAA
                                                            /--*  t1     int    
N002 (  2,  3) [000004] -c---------                    t4 = *  INIT_VAL  int   
N003 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N004 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll)
               [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-]
N001 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    0xFFFFFFFF
                                                            /--*  t10    int    
N002 (  2,  3) [000013] -c---------                   t13 = *  INIT_VAL  int   
N003 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4
                                                            /--*  t7     int    
N004 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int
                                                            /--*  t8     long   
N006 (  6, 17) [000009] -c---------                    t9 = *  LEA(b+-789747524) long  
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N007 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll)
               [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-]
N001 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t15    long   
N002 (  6, 14) [000016] n---G------                   t16 = *  IND       int   
N003 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556
                                                            /--*  t16    int    
                                                            +--*  t17    int    
N004 (  8, 19) [000018] J---G--N---                         *  NE        void  
N005 ( 10, 21) [000019] ----G------                         *  JTRUE     void  

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
               [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-]
N001 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4
                                                            /--*  t23    int    
N002 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int
N003 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t24    long   
                                                            +--*  t22    long   
N004 (  6, 17) [000025] -c---------                   t25 = *  LEA(b+(i*1)+0) long  
                                                            /--*  t25    long   
N005 (  8, 18) [000026] U--XG------                   t26 = *  IND       int   
N006 (  1,  2) [000027] -c---------                   t27 =    CNS_INT   int    -1
                                                            /--*  t26    int    
                                                            +--*  t27    int    
N007 ( 10, 21) [000028] J--XG--N---                         *  NE        void  
N008 ( 12, 23) [000029] ---XG------                         *  JTRUE     void  

------------ BB03 [047..049) (return), preds={BB02} succs={}
               [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-]
N001 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1
                                                            /--*  t30    int    
N002 (  2,  3) [000031] -----------                         *  RETURN    int   

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}
               [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-]
N001 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0
                                                            /--*  t20    int    
N002 (  2,  3) [000021] -----------                         *  RETURN    int   

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
;  V00 OutArgs        lclBlk <0>  do-not-enreg[] "OutgoingArgSpace"
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()

*************** In fgRemoveDeadBlocks()
Removing unreachable blocks for fgRemoveDeadBlocks iteration #1
*************** In fgDebugCheckBBlist

*** lvaComputeRefCounts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
               [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    0xAAAAAAAA
                                                            /--*  t1     int    
N002 (  2,  3) [000004] -c---------                    t4 = *  INIT_VAL  int   
N003 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N004 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll)
               [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-]
N001 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    0xFFFFFFFF
                                                            /--*  t10    int    
N002 (  2,  3) [000013] -c---------                   t13 = *  INIT_VAL  int   
N003 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4
                                                            /--*  t7     int    
N004 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int
                                                            /--*  t8     long   
N006 (  6, 17) [000009] -c---------                    t9 = *  LEA(b+-789747524) long  
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N007 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll)
               [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-]
N001 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t15    long   
N002 (  6, 14) [000016] n---G------                   t16 = *  IND       int   
N003 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556
                                                            /--*  t16    int    
                                                            +--*  t17    int    
N004 (  8, 19) [000018] J---G--N---                         *  NE        void  
N005 ( 10, 21) [000019] ----G------                         *  JTRUE     void  

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
               [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-]
N001 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4
                                                            /--*  t23    int    
N002 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int
N003 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA]
                                                            /--*  t24    long   
                                                            +--*  t22    long   
N004 (  6, 17) [000025] -c---------                   t25 = *  LEA(b+(i*1)+0) long  
                                                            /--*  t25    long   
N005 (  8, 18) [000026] U--XG------                   t26 = *  IND       int   
N006 (  1,  2) [000027] -c---------                   t27 =    CNS_INT   int    -1
                                                            /--*  t26    int    
                                                            +--*  t27    int    
N007 ( 10, 21) [000028] J--XG--N---                         *  NE        void  
N008 ( 12, 23) [000029] ---XG------                         *  JTRUE     void  

------------ BB03 [047..049) (return), preds={BB02} succs={}
               [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-]
N001 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1
                                                            /--*  t30    int    
N002 (  2,  3) [000031] -----------                         *  RETURN    int   

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}
               [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-]
N001 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0
                                                            /--*  t20    int    
N002 (  2,  3) [000021] -----------                         *  RETURN    int   

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
 in: {}
out: {}
BB02
use: {}
def: {}
 in: {}
out: {}
BB03
use: {}
def: {}
 in: {}
out: {}
BB04
use: {}
def: {}
 in: {}
out: {}

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
*************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
--- delta bump 136 for FP frame
--- virtual stack offset to actual stack offset delta is 136
-- V00 was 0, now 136

compRsvdRegCheck
  frame size  =    136
  compArgSize =      0
 Returning true (MinOpts)

  Reserved REG_OPT_RSVD (xip1) due to large frame
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
	Succ block: BB02, Criteria: weight, Worklist: [BB02 ]
	Succ block: BB04, Criteria: weight, Worklist: [BB02 BB04 ]
Current block: BB02
	Succ block: BB03, Criteria: bbNum, Worklist: [BB03 BB04 ]
Current block: BB03
Current block: BB04
Final LSRA Block Sequence:
BB01 (  1   ) critical-out
BB02 (  1   ) critical-out
BB03 (  1   )
BB04 (  1   ) critical-in

BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001. t1              =  CNS_INT   0xAAAAAAAA
  N002. t4              =  INIT_VAL ; t1
  N003. t0              =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N004.                    STORE_BLK; t0,t4
  N000.                    IL_OFFSET INLRT @ 0x010[E-]
  N001. t10             =  CNS_INT   0xFFFFFFFF
  N002. t13             =  INIT_VAL ; t10
  N003. t7              =  CNS_INT   4
  N004. t8              =  CAST     ; t7
  N006. t9              =  LEA(b+-789747524); t8
  N007.                    STORE_BLK; t9,t13
  N000.                    IL_OFFSET INLRT @ 0x022[E-]
  N001. t15             =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N002. t16             =  IND      ; t15
  N003. t17             =  CNS_INT   -0x55555556
  N004.                    NE       ; t16,t17
  N005.                    JTRUE    

BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
  N000.                    IL_OFFSET INLRT @ 0x034[E-]
  N001. t23             =  CNS_INT   4
  N002. t24             =  CAST     ; t23
  N003. t22             =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N004. t25             =  LEA(b+(i*1)+0); t24,t22
  N005. t26             =  IND      ; t25
  N006.                    CNS_INT   -1
  N007.                    NE       ; t26
  N008.                    JTRUE    

BB03 [047..049) (return), preds={BB02} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x047[E-]
  N001. t30             =  CNS_INT   1
  N002.                    RETURN   ; t30

BB04 [049..04B) (return), preds={BB01,BB02} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x049[E-]
  N001. t20             =  CNS_INT   0
  N002.                    RETURN   ; t20




buildIntervals second part ========

NEW BLOCK BB01
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N002 (???,???) [000032] -----------                         *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N004 (  1,  2) [000001] -----------                         *  CNS_INT   int    0xAAAAAAAA REG NA
Interval  0: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N004.t1. CNS_INT }
N006 (  2,  3) [000004] -c---------                         *  INIT_VAL  int    REG NA
Contained
DefList: { N004.t1. CNS_INT }
N008 (  3, 12) [000000] H----------                         *  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG NA
Interval  1: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #2   @9   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N004.t1. CNS_INT; N008.t0. CNS_INT }
N010 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
<RefPosition #3   @10  RefTypeUse <Ivl:1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #4   @10  RefTypeUse <Ivl:0> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N012 (???,???) [000033] -----------                         *  IL_OFFSET void   INLRT @ 0x010[E-] REG NA

DefList: {  }
N014 (  1,  2) [000010] -----------                         *  CNS_INT   int    0xFFFFFFFF REG NA
Interval  2: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #5   @15  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N014.t10. CNS_INT }
N016 (  2,  3) [000013] -c---------                         *  INIT_VAL  int    REG NA
Contained
DefList: { N014.t10. CNS_INT }
N018 (  1,  2) [000007] -----------                         *  CNS_INT   int    4 REG NA
Interval  3: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #6   @19  RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N014.t10. CNS_INT; N018.t7. CNS_INT }
N020 (  2,  4) [000008] -----------                         *  CAST      long <- int REG NA
<RefPosition #7   @20  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval  4: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #8   @21  RefTypeDef <Ivl:4> CAST BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N014.t10. CNS_INT; N020.t8. CAST }
N022 (  6, 17) [000009] -c---------                         *  LEA(b+-789747524) long   REG NA
Contained
DefList: { N014.t10. CNS_INT; N020.t8. CAST }
N024 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
Interval  5: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #9   @24  RefTypeDef <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #10  @24  RefTypeUse <Ivl:4> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeUse <Ivl:2> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #12  @24  RefTypeUse <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>

DefList: {  }
N026 (???,???) [000034] -----------                         *  IL_OFFSET void   INLRT @ 0x022[E-] REG NA

DefList: {  }
N028 (  3, 12) [000015] H----------                         *  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG NA
Interval  6: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #13  @29  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N028.t15. CNS_INT }
N030 (  6, 14) [000016] n---G------                         *  IND       int    REG NA
<RefPosition #14  @30  RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval  7: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #15  @31  RefTypeDef <Ivl:7> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N030.t16. IND }
N032 (  1,  4) [000017] -----------                         *  CNS_INT   int    -0x55555556 REG NA
Interval  8: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #16  @33  RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N030.t16. IND; N032.t17. CNS_INT }
N034 (  8, 19) [000018] J---G--N---                         *  NE        void   REG NA
<RefPosition #17  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #18  @34  RefTypeUse <Ivl:8> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N036 ( 10, 21) [000019] ----G------                         *  JTRUE     void   REG NA


NEW BLOCK BB02


Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #19  @38  RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N040 (???,???) [000035] -----------                         *  IL_OFFSET void   INLRT @ 0x034[E-] REG NA

DefList: {  }
N042 (  1,  2) [000023] -----------                         *  CNS_INT   int    4 REG NA
Interval  9: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #20  @43  RefTypeDef <Ivl:9> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N042.t23. CNS_INT }
N044 (  2,  4) [000024] -----------                         *  CAST      long <- int REG NA
<RefPosition #21  @44  RefTypeUse <Ivl:9> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 10: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #22  @45  RefTypeDef <Ivl:10> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N044.t24. CAST }
N046 (  3, 12) [000022] H----------                         *  CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG NA
Interval 11: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #23  @47  RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N044.t24. CAST; N046.t22. CNS_INT }
N048 (  6, 17) [000025] -c---------                         *  LEA(b+(i*1)+0) long   REG NA
Contained
DefList: { N044.t24. CAST; N046.t22. CNS_INT }
N050 (  8, 18) [000026] U--XG------                         *  IND       int    REG NA
<RefPosition #24  @50  RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #25  @50  RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 12: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #26  @51  RefTypeDef <Ivl:12> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N050.t26. IND }
N052 (  1,  2) [000027] -c---------                         *  CNS_INT   int    -1 REG NA
Contained
DefList: { N050.t26. IND }
N054 ( 10, 21) [000028] J--XG--N---                         *  NE        void   REG NA
<RefPosition #27  @54  RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N056 ( 12, 23) [000029] ---XG------                         *  JTRUE     void   REG NA


NEW BLOCK BB03


Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #28  @58  RefTypeBB BB03 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N060 (???,???) [000036] -----------                         *  IL_OFFSET void   INLRT @ 0x047[E-] REG NA

DefList: {  }
N062 (  1,  2) [000030] -----------                         *  CNS_INT   int    1 REG NA
Interval 13: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #29  @63  RefTypeDef <Ivl:13> CNS_INT BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N062.t30. CNS_INT }
N064 (  2,  3) [000031] -----------                         *  RETURN    int    REG NA
<RefPosition #30  @64  RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #31  @64  RefTypeUse <Ivl:13> BB03 regmask=[x0] minReg=1 last fixed wt=100.00>


NEW BLOCK BB04


Setting BB01 as the predecessor for determining incoming variable registers of BB04
<RefPosition #32  @66  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N068 (???,???) [000037] -----------                         *  IL_OFFSET void   INLRT @ 0x049[E-] REG NA

DefList: {  }
N070 (  1,  2) [000020] -----------                         *  CNS_INT   int    0 REG NA
Interval 14: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28]
<RefPosition #33  @71  RefTypeDef <Ivl:14> CNS_INT BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N070.t20. CNS_INT }
N072 (  2,  3) [000021] -----------                         *  RETURN    int    REG NA
<RefPosition #34  @72  RefTypeFixedReg <Reg:x0 > BB04 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #35  @72  RefTypeUse <Ivl:14> BB04 regmask=[x0] minReg=1 last fixed wt=100.00>


Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: int (constant) RefPositions {#1@5 #4@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  1: long (constant) RefPositions {#2@9 #3@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  2: int (constant) RefPositions {#5@15 #11@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  3: int (constant) RefPositions {#6@19 #7@20} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  4: long RefPositions {#8@21 #10@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  5: int (INTERNAL) RefPositions {#9@24 #12@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  6: long (constant) RefPositions {#13@29 #14@30} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  7: int RefPositions {#15@31 #17@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  8: int (constant) RefPositions {#16@33 #18@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  9: int (constant) RefPositions {#20@43 #21@44} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 10: long RefPositions {#22@45 #24@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 11: long (constant) RefPositions {#23@47 #25@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 12: int RefPositions {#26@51 #27@54} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 13: int (constant) RefPositions {#29@63 #31@64} physReg:NA Preferences=[x0]
Interval 14: int (constant) RefPositions {#33@71 #35@72} physReg:NA Preferences=[x0]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #2   @9   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #3   @10  RefTypeUse <Ivl:1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #4   @10  RefTypeUse <Ivl:0> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #5   @15  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #6   @19  RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #7   @20  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #8   @21  RefTypeDef <Ivl:4> CAST BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #9   @24  RefTypeDef <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #10  @24  RefTypeUse <Ivl:4> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeUse <Ivl:2> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #12  @24  RefTypeUse <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #13  @29  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #14  @30  RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #15  @31  RefTypeDef <Ivl:7> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #16  @33  RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #17  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #18  @34  RefTypeUse <Ivl:8> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #19  @38  RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #20  @43  RefTypeDef <Ivl:9> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #21  @44  RefTypeUse <Ivl:9> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #22  @45  RefTypeDef <Ivl:10> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #23  @47  RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #24  @50  RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #25  @50  RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #26  @51  RefTypeDef <Ivl:12> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #27  @54  RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #28  @58  RefTypeBB BB03 regmask=[] minReg=1 wt=100.00>
<RefPosition #29  @63  RefTypeDef <Ivl:13> CNS_INT BB03 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #30  @64  RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #31  @64  RefTypeUse <Ivl:13> BB03 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #32  @66  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #33  @71  RefTypeDef <Ivl:14> CNS_INT BB04 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #34  @72  RefTypeFixedReg <Reg:x0 > BB04 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #35  @72  RefTypeUse <Ivl:14> BB04 regmask=[x0] minReg=1 last fixed wt=100.00>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: 
BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004.                    CNS_INT   0xAAAAAAAA
        Def:<I0>(#1)
  N006.                    INIT_VAL 
  N008.                    CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
        Def:<I1>(#2)
  N010.                    STORE_BLK
                               Use:<I1>(#3) *
                               Use:<I0>(#4) *
  N012.                    IL_OFFSET INLRT @ 0x010[E-]
  N014.                    CNS_INT   0xFFFFFFFF
        Def:<I2>(#5)
  N016.                    INIT_VAL 
  N018.                    CNS_INT   4
        Def:<I3>(#6)
  N020.                    CAST     
                               Use:<I3>(#7) *
        Def:<I4>(#8)
  N022.                    LEA(b+-789747524)
  N024.                    STORE_BLK
        Def:<T5>(#9)
                               Use:<I4>(#10) *
                               Use:<I2>(#11) *
                               Use:<T5>(#12) *
  N026.                    IL_OFFSET INLRT @ 0x022[E-]
  N028.                    CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
        Def:<I6>(#13)
  N030.                    IND      
                               Use:<I6>(#14) *
        Def:<I7>(#15)
  N032.                    CNS_INT   -0x55555556
        Def:<I8>(#16)
  N034.                    NE       
                               Use:<I7>(#17) *
                               Use:<I8>(#18) *
  N036.                    JTRUE    

BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
  N040.                    IL_OFFSET INLRT @ 0x034[E-]
  N042.                    CNS_INT   4
        Def:<I9>(#20)
  N044.                    CAST     
                               Use:<I9>(#21) *
        Def:<I10>(#22)
  N046.                    CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
        Def:<I11>(#23)
  N048.                    LEA(b+(i*1)+0)
  N050.                    IND      
                               Use:<I10>(#24) *
                               Use:<I11>(#25) *
        Def:<I12>(#26)
  N052.                    CNS_INT   -1
  N054.                    NE       
                               Use:<I12>(#27) *
  N056.                    JTRUE    

BB03 [047..049) (return), preds={BB02} succs={}
=====
  N060.                    IL_OFFSET INLRT @ 0x047[E-]
  N062.                    CNS_INT   1
        Def:<I13>(#29)
  N064.                    RETURN   
                               Use:<I13>(#31) Fixed:x0(#30) *

BB04 [049..04B) (return), preds={BB01,BB02} succs={}
=====
  N068.                    IL_OFFSET INLRT @ 0x049[E-]
  N070.                    CNS_INT   0
        Def:<I14>(#33)
  N072.                    RETURN   
                               Use:<I14>(#35) Fixed:x0(#34) *




Linear scan intervals after buildIntervals:
Interval  0: int (constant) RefPositions {#1@5 #4@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  1: long (constant) RefPositions {#2@9 #3@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  2: int (constant) RefPositions {#5@15 #11@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  3: int (constant) RefPositions {#6@19 #7@20} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  4: long RefPositions {#8@21 #10@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  5: int (INTERNAL) RefPositions {#9@24 #12@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  6: long (constant) RefPositions {#13@29 #14@30} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  7: int RefPositions {#15@31 #17@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  8: int (constant) RefPositions {#16@33 #18@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  9: int (constant) RefPositions {#20@43 #21@44} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 10: long RefPositions {#22@45 #24@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 11: long (constant) RefPositions {#23@47 #25@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 12: int RefPositions {#26@51 #27@54} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 13: int (constant) RefPositions {#29@63 #31@64} physReg:NA Preferences=[x0]
Interval 14: int (constant) RefPositions {#33@71 #35@72} physReg:NA Preferences=[x0]

*************** In LinearScan::allocateRegisters()

Linear scan intervals before allocateRegisters:
Interval  0: int (constant) RefPositions {#1@5 #4@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  1: long (constant) RefPositions {#2@9 #3@10} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  2: int (constant) RefPositions {#5@15 #11@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  3: int (constant) RefPositions {#6@19 #7@20} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  4: long RefPositions {#8@21 #10@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  5: int (INTERNAL) RefPositions {#9@24 #12@24} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  6: long (constant) RefPositions {#13@29 #14@30} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  7: int RefPositions {#15@31 #17@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  8: int (constant) RefPositions {#16@33 #18@34} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval  9: int (constant) RefPositions {#20@43 #21@44} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 10: long RefPositions {#22@45 #24@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 11: long (constant) RefPositions {#23@47 #25@50} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 12: int RefPositions {#26@51 #27@54} physReg:NA Preferences=[x0-xip0 x19-x28]
Interval 13: int (constant) RefPositions {#29@63 #31@64} physReg:NA Preferences=[x0]
Interval 14: int (constant) RefPositions {#33@71 #35@72} physReg:NA Preferences=[x0]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #2   @9   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #3   @10  RefTypeUse <Ivl:1> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #4   @10  RefTypeUse <Ivl:0> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #5   @15  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #6   @19  RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #7   @20  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #8   @21  RefTypeDef <Ivl:4> CAST BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #9   @24  RefTypeDef <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #10  @24  RefTypeUse <Ivl:4> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeUse <Ivl:2> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #12  @24  RefTypeUse <Ivl:5 internal> STORE_BLK BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00>
<RefPosition #13  @29  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #14  @30  RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #15  @31  RefTypeDef <Ivl:7> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #16  @33  RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #17  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #18  @34  RefTypeUse <Ivl:8> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #19  @38  RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #20  @43  RefTypeDef <Ivl:9> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #21  @44  RefTypeUse <Ivl:9> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #22  @45  RefTypeDef <Ivl:10> CAST BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #23  @47  RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #24  @50  RefTypeUse <Ivl:10> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #25  @50  RefTypeUse <Ivl:11> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #26  @51  RefTypeDef <Ivl:12> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #27  @54  RefTypeUse <Ivl:12> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #28  @58  RefTypeBB BB03 regmask=[] minReg=1 wt=100.00>
<RefPosition #29  @63  RefTypeDef <Ivl:13> CNS_INT BB03 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #30  @64  RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #31  @64  RefTypeUse <Ivl:13> BB03 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #32  @66  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #33  @71  RefTypeDef <Ivl:14> CNS_INT BB04 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #34  @72  RefTypeFixedReg <Reg:x0 > BB04 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #35  @72  RefTypeUse <Ivl:14> BB04 regmask=[x0] minReg=1 last fixed wt=100.00>


Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.

---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
                                 |    |    |    |    |    |    |    |    |    |    |
 0.#0  BB1 PredBB0               |    |    |    |    |    |    |    |    |    |    |
 5.#1  C0   Def    BSFIT(A) x0   |C0 a|    |    |    |    |    |    |    |    |    |
 9.#2  C1   Def    ORDER(A) x1   |C0 a|C1 a|    |    |    |    |    |    |    |    |
10.#3  C1   Use *  Keep     x1   |C0 a|C1 a|    |    |    |    |    |    |    |    |
10.#4  C0   Use *  Keep     x0   |C0 a|C1 a|    |    |    |    |    |    |    |    |
15.#5  C2   Def    BSFIT(A) x0   |C2 a|C1 i|    |    |    |    |    |    |    |    |
19.#6  C3   Def    ORDER(A) x1   |C2 a|C3 a|    |    |    |    |    |    |    |    |
20.#7  C3   Use *  Keep     x1   |C2 a|C3 a|    |    |    |    |    |    |    |    |
21.#8  I4   Def    ORDER(A) x1   |C2 a|I4 a|    |    |    |    |    |    |    |    |
24.#9  I5   Def    ORDER(A) x2   |C2 a|I4 a|I5 a|    |    |    |    |    |    |    |
24.#10 I4   Use *  Keep     x1   |C2 a|I4 a|I5 a|    |    |    |    |    |    |    |
24.#11 C2   Use *  Keep     x0   |C2 a|I4 a|I5 a|    |    |    |    |    |    |    |
24.#12 I5   Use *  Keep     x2   |C2 a|I4 a|I5 a|    |    |    |    |    |    |    |
29.#13 C6   Def    BSFIT(A) x0   |C6 a|    |    |    |    |    |    |    |    |    |
30.#14 C6   Use *  Keep     x0   |C6 a|    |    |    |    |    |    |    |    |    |
31.#15 I7   Def    BSFIT(A) x0   |I7 a|    |    |    |    |    |    |    |    |    |
33.#16 C8   Def    ORDER(A) x1   |I7 a|C8 a|    |    |    |    |    |    |    |    |
34.#17 I7   Use *  Keep     x0   |I7 a|C8 a|    |    |    |    |    |    |    |    |
34.#18 C8   Use *  Keep     x1   |I7 a|C8 a|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
38.#19 BB2 PredBB1               |    |    |    |    |    |    |    |    |    |    |
43.#20 C9   Def    BSFIT(A) x0   |C9 a|    |    |    |    |    |    |    |    |    |
44.#21 C9   Use *  Keep     x0   |C9 a|    |    |    |    |    |    |    |    |    |
45.#22 I10  Def    BSFIT(A) x0   |I10a|    |    |    |    |    |    |    |    |    |
47.#23 C11  Def    ORDER(A) x1   |I10a|C11a|    |    |    |    |    |    |    |    |
50.#24 I10  Use *  Keep     x0   |I10a|C11a|    |    |    |    |    |    |    |    |
50.#25 C11  Use *  Keep     x1   |I10a|C11a|    |    |    |    |    |    |    |    |
51.#26 I12  Def    BSFIT(A) x0   |I12a|C11i|    |    |    |    |    |    |    |    |
54.#27 I12  Use *  Keep     x0   |I12a|C11i|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
58.#28 BB3 PredBB2               |    |    |    |    |    |    |    |    |    |    |
63.#29 C13  Def    Alloc    x0   |C13a|    |    |    |    |    |    |    |    |    |
64.#30 x0   Fixd   Keep     x0   |C13a|    |    |    |    |    |    |    |    |    |
64.#31 C13  Use *  Keep     x0   |C13a|    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
66.#32 BB4 PredBB1               |    |    |    |    |    |    |    |    |    |    |
71.#33 C14  Def    Alloc    x0   |C14a|    |    |    |    |    |    |    |    |    |
72.#34 x0   Fixd   Keep     x0   |C14a|    |    |    |    |    |    |    |    |    |
72.#35 C14  Use *  Keep     x0   |C14i|    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #2   @9   RefTypeDef <Ivl:1> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #3   @10  RefTypeUse <Ivl:1> BB01 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #4   @10  RefTypeUse <Ivl:0> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #5   @15  RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #6   @19  RefTypeDef <Ivl:3> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #7   @20  RefTypeUse <Ivl:3> BB01 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #8   @21  RefTypeDef <Ivl:4> CAST BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #9   @24  RefTypeDef <Ivl:5 internal> STORE_BLK BB01 regmask=[x2] minReg=1 wt=400.00>
<RefPosition #10  @24  RefTypeUse <Ivl:4> BB01 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #11  @24  RefTypeUse <Ivl:2> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #12  @24  RefTypeUse <Ivl:5 internal> STORE_BLK BB01 regmask=[x2] minReg=1 last wt=400.00>
<RefPosition #13  @29  RefTypeDef <Ivl:6> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #14  @30  RefTypeUse <Ivl:6> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #15  @31  RefTypeDef <Ivl:7> IND BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #16  @33  RefTypeDef <Ivl:8> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #17  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #18  @34  RefTypeUse <Ivl:8> BB01 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #19  @38  RefTypeBB BB02 regmask=[] minReg=1 wt=100.00>
<RefPosition #20  @43  RefTypeDef <Ivl:9> CNS_INT BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #21  @44  RefTypeUse <Ivl:9> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #22  @45  RefTypeDef <Ivl:10> CAST BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #23  @47  RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #24  @50  RefTypeUse <Ivl:10> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #25  @50  RefTypeUse <Ivl:11> BB02 regmask=[x1] minReg=1 last wt=100.00>
<RefPosition #26  @51  RefTypeDef <Ivl:12> IND BB02 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #27  @54  RefTypeUse <Ivl:12> BB02 regmask=[x0] minReg=1 last wt=100.00>
<RefPosition #28  @58  RefTypeBB BB03 regmask=[] minReg=1 wt=100.00>
<RefPosition #29  @63  RefTypeDef <Ivl:13> CNS_INT BB03 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #30  @64  RefTypeFixedReg <Reg:x0 > BB03 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #31  @64  RefTypeUse <Ivl:13> BB03 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #32  @66  RefTypeBB BB04 regmask=[] minReg=1 wt=100.00>
<RefPosition #33  @71  RefTypeDef <Ivl:14> CNS_INT BB04 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #34  @72  RefTypeFixedReg <Reg:x0 > BB04 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #35  @72  RefTypeUse <Ivl:14> BB04 regmask=[x0] minReg=1 last fixed wt=100.00>
Active intervals at end of allocation:

Trees after linear scan register allocator (LSRA)

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
N002 (???,???) [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N004 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    0xAAAAAAAA REG x0
                                                            /--*  t1     int    
N006 (  2,  3) [000004] -c---------                    t4 = *  INIT_VAL  int    REG NA
N008 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N010 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
N012 (???,???) [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-] REG NA
N014 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    0xFFFFFFFF REG x0
                                                            /--*  t10    int    
N016 (  2,  3) [000013] -c---------                   t13 = *  INIT_VAL  int    REG NA
N018 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4 REG x1
                                                            /--*  t7     int    
N020 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int REG x1
                                                            /--*  t8     long   
N022 (  6, 17) [000009] -c---------                    t9 = *  LEA(b+-789747524) long   REG NA
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N024 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
N026 (???,???) [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-] REG NA
N028 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x0
                                                            /--*  t15    long   
N030 (  6, 14) [000016] n---G------                   t16 = *  IND       int    REG x0
N032 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556 REG x1
                                                            /--*  t16    int    
                                                            +--*  t17    int    
N034 (  8, 19) [000018] J---G--N---                         *  NE        void   REG NA
N036 ( 10, 21) [000019] ----G------                         *  JTRUE     void   REG NA

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N040 (???,???) [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-] REG NA
N042 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4 REG x0
                                                            /--*  t23    int    
N044 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int REG x0
N046 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
                                                            /--*  t24    long   
                                                            +--*  t22    long   
N048 (  6, 17) [000025] -c---------                   t25 = *  LEA(b+(i*1)+0) long   REG NA
                                                            /--*  t25    long   
N050 (  8, 18) [000026] U--XG------                   t26 = *  IND       int    REG x0
N052 (  1,  2) [000027] -c---------                   t27 =    CNS_INT   int    -1 REG NA
                                                            /--*  t26    int    
                                                            +--*  t27    int    
N054 ( 10, 21) [000028] J--XG--N---                         *  NE        void   REG NA
N056 ( 12, 23) [000029] ---XG------                         *  JTRUE     void   REG NA

------------ BB03 [047..049) (return), preds={BB02} succs={}
N060 (???,???) [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-] REG NA
N062 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1 REG x0
                                                            /--*  t30    int    
N064 (  2,  3) [000031] -----------                         *  RETURN    int    REG NA

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}
N068 (???,???) [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-] REG NA
N070 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0 REG x0
                                                            /--*  t20    int    
N072 (  2,  3) [000021] -----------                         *  RETURN    int    REG NA

-------------------------------------------------------------------------------------------------------------------

Final allocation
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
 0.#0  BB1 PredBB0               |    |    |    |    |    |    |    |    |    |    |
 5.#1  C0   Def    Alloc    x0   |C0 a|    |    |    |    |    |    |    |    |    |
 9.#2  C1   Def    Alloc    x1   |C0 a|C1 a|    |    |    |    |    |    |    |    |
10.#3  C1   Use *  Keep     x1   |C0 a|C1 i|    |    |    |    |    |    |    |    |
10.#4  C0   Use *  Keep     x0   |C0 i|    |    |    |    |    |    |    |    |    |
15.#5  C2   Def    Alloc    x0   |C2 a|    |    |    |    |    |    |    |    |    |
19.#6  C3   Def    Alloc    x1   |C2 a|C3 a|    |    |    |    |    |    |    |    |
20.#7  C3   Use *  Keep     x1   |C2 a|C3 i|    |    |    |    |    |    |    |    |
21.#8  I4   Def    Alloc    x1   |C2 a|I4 a|    |    |    |    |    |    |    |    |
24.#9  I5   Def    Alloc    x2   |C2 a|I4 a|I5 a|    |    |    |    |    |    |    |
24.#10 I4   Use *  Keep     x1   |C2 a|I4 i|I5 a|    |    |    |    |    |    |    |
24.#11 C2   Use *  Keep     x0   |C2 i|    |I5 a|    |    |    |    |    |    |    |
24.#12 I5   Use *  Keep     x2   |    |    |I5 i|    |    |    |    |    |    |    |
29.#13 C6   Def    Alloc    x0   |C6 a|    |    |    |    |    |    |    |    |    |
30.#14 C6   Use *  Keep     x0   |C6 i|    |    |    |    |    |    |    |    |    |
31.#15 I7   Def    Alloc    x0   |I7 a|    |    |    |    |    |    |    |    |    |
33.#16 C8   Def    Alloc    x1   |I7 a|C8 a|    |    |    |    |    |    |    |    |
34.#17 I7   Use *  Keep     x0   |I7 i|C8 a|    |    |    |    |    |    |    |    |
34.#18 C8   Use *  Keep     x1   |    |C8 i|    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
38.#19 BB2 PredBB1               |    |    |    |    |    |    |    |    |    |    |
43.#20 C9   Def    Alloc    x0   |C9 a|    |    |    |    |    |    |    |    |    |
44.#21 C9   Use *  Keep     x0   |C9 i|    |    |    |    |    |    |    |    |    |
45.#22 I10  Def    Alloc    x0   |I10a|    |    |    |    |    |    |    |    |    |
47.#23 C11  Def    Alloc    x1   |I10a|C11a|    |    |    |    |    |    |    |    |
50.#24 I10  Use *  Keep     x0   |I10i|C11a|    |    |    |    |    |    |    |    |
50.#25 C11  Use *  Keep     x1   |    |C11i|    |    |    |    |    |    |    |    |
51.#26 I12  Def    Alloc    x0   |I12a|    |    |    |    |    |    |    |    |    |
54.#27 I12  Use *  Keep     x0   |I12i|    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
58.#28 BB3 PredBB2               |    |    |    |    |    |    |    |    |    |    |
63.#29 C13  Def    Alloc    x0   |C13a|    |    |    |    |    |    |    |    |    |
64.#30 x0   Fixd   Keep     x0   |C13a|    |    |    |    |    |    |    |    |    |
64.#31 C13  Use *  Keep     x0   |C13i|    |    |    |    |    |    |    |    |    |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |
---------------------------------+----+----+----+----+----+----+----+----+----+----+
66.#32 BB4 PredBB1               |    |    |    |    |    |    |    |    |    |    |
71.#33 C14  Def    Alloc    x0   |C14a|    |    |    |    |    |    |    |    |    |
72.#34 x0   Fixd   Keep     x0   |C14a|    |    |    |    |    |    |    |    |    |
72.#35 C14  Use *  Keep     x0   |C14i|    |    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  0
Total Reg Cand Vars: 0
Total number of Intervals: 14
Total number of RefPositions: 35
Total Number of spill temps created: 0
..........
BB01 [  100.00]: BEST_FIT = 4, REG_ORDER = 5
BB02 [  100.00]: BEST_FIT = 3, REG_ORDER = 1
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total BEST_FIT [#11] : 7   Weighted: 700.000000
Total REG_ORDER [#13] : 6   Weighted: 600.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: 
BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004. x0              =  CNS_INT   0xAAAAAAAA
  N006. STK             =  INIT_VAL ; x0
  N008. x1              =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N010.                    STORE_BLK; x1,STK
  N012.                    IL_OFFSET INLRT @ 0x010[E-]
  N014. x0              =  CNS_INT   0xFFFFFFFF
  N016. STK             =  INIT_VAL ; x0
  N018. x1              =  CNS_INT   4
  N020. x1              =  CAST     ; x1
  N022. STK             =  LEA(b+-789747524); x1
  N024.                    STORE_BLK; STK,STK
  N026.                    IL_OFFSET INLRT @ 0x022[E-]
  N028. x0              =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N030. x0              =  IND      ; x0
  N032. x1              =  CNS_INT   -0x55555556
  N034.                    NE       ; x0,x1
  N036.                    JTRUE    

BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
  N040.                    IL_OFFSET INLRT @ 0x034[E-]
  N042. x0              =  CNS_INT   4
  N044. x0              =  CAST     ; x0
  N046. x1              =  CNS_INT(h) 0x7ffcd0ed68bc static Fseq[DATA]
  N048. STK             =  LEA(b+(i*1)+0); x0,x1
  N050. x0              =  IND      ; STK
  N052.                    CNS_INT   -1
  N054.                    NE       ; x0
  N056.                    JTRUE    

BB03 [047..049) (return), preds={BB02} succs={}
=====
  N060.                    IL_OFFSET INLRT @ 0x047[E-]
  N062. x0              =  CNS_INT   1
  N064.                    RETURN   ; x0

BB04 [049..04B) (return), preds={BB01,BB02} succs={}
=====
  N068.                    IL_OFFSET INLRT @ 0x049[E-]
  N070. x0              =  CNS_INT   0
  N072.                    RETURN   ; x0




*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04}
N002 (???,???) [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N004 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    0xAAAAAAAA REG x0
                                                            /--*  t1     int    
N006 (  2,  3) [000004] -c---------                    t4 = *  INIT_VAL  int    REG NA
N008 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
                                                            /--*  t0     long   
                                                            +--*  t4     int    
N010 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
N012 (???,???) [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-] REG NA
N014 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    0xFFFFFFFF REG x0
                                                            /--*  t10    int    
N016 (  2,  3) [000013] -c---------                   t13 = *  INIT_VAL  int    REG NA
N018 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4 REG x1
                                                            /--*  t7     int    
N020 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int REG x1
                                                            /--*  t8     long   
N022 (  6, 17) [000009] -c---------                    t9 = *  LEA(b+-789747524) long   REG NA
                                                            /--*  t9     long   
                                                            +--*  t13    int    
N024 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
N026 (???,???) [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-] REG NA
N028 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x0
                                                            /--*  t15    long   
N030 (  6, 14) [000016] n---G------                   t16 = *  IND       int    REG x0
N032 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556 REG x1
                                                            /--*  t16    int    
                                                            +--*  t17    int    
N034 (  8, 19) [000018] J---G--N---                         *  NE        void   REG NA
N036 ( 10, 21) [000019] ----G------                         *  JTRUE     void   REG NA

------------ BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N040 (???,???) [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-] REG NA
N042 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4 REG x0
                                                            /--*  t23    int    
N044 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int REG x0
N046 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
                                                            /--*  t24    long   
                                                            +--*  t22    long   
N048 (  6, 17) [000025] -c---------                   t25 = *  LEA(b+(i*1)+0) long   REG NA
                                                            /--*  t25    long   
N050 (  8, 18) [000026] U--XG------                   t26 = *  IND       int    REG x0
N052 (  1,  2) [000027] -c---------                   t27 =    CNS_INT   int    -1 REG NA
                                                            /--*  t26    int    
                                                            +--*  t27    int    
N054 ( 10, 21) [000028] J--XG--N---                         *  NE        void   REG NA
N056 ( 12, 23) [000029] ---XG------                         *  JTRUE     void   REG NA

------------ BB03 [047..049) (return), preds={BB02} succs={}
N060 (???,???) [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-] REG NA
N062 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1 REG x0
                                                            /--*  t30    int    
N064 (  2,  3) [000031] -----------                         *  RETURN    int    REG NA

------------ BB04 [049..04B) (return), preds={BB01,BB02} succs={}
N068 (???,???) [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-] REG NA
N070 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0 REG x0
                                                            /--*  t20    int    
N072 (  2,  3) [000021] -----------                         *  RETURN    int    REG NA

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckLoopTable: loop table not valid

*************** Starting PHASE Place 'align' instructions

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i LIR 
-----------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [x0-x2]
Callee-saved registers pushed: 2 [fp lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
--- delta bump 16 for FP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   do-not-enreg[] "OutgoingArgSpace"
;
; Lcl frame size = 0
Mark labels for codegen
  BB01 : first block
  BB04 : branch target
  BB04 : branch target
*************** After genMarkLabelsForCodegen()

-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight    lp [IL range]     [jump]      [EH region]         [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1       [000..034)-> BB04 ( cond )                     i label LIR 
BB02 [0001]  1       BB01                  1       [034..047)-> BB04 ( cond )                     i LIR 
BB03 [0002]  1       BB02                  1       [047..049)        (return)                     i LIR 
BB04 [0003]  2       BB01,BB02             1       [049..04B)        (return)                     i label LIR 
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [000..034) -> BB04 (cond), preds={} succs={BB02,BB04} flags=0x00000000.20010020: i label LIR 
BB01 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M14249_BB01:
Mapped BB01 to G_M14249_IG02
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Added IP mapping: 0x0000 STACK_EMPTY (G_M14249_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000032] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N004 (  1,  2) [000001] -----------                    t1 =    CNS_INT   int    0xAAAAAAAA REG x0
IN0001:                           mov     w0, #0xAAAAAAAA
                                                                        /--*  t1     int    
Generating: N006 (  2,  3) [000004] -c---------                    t4 = *  INIT_VAL  int    REG NA
Generating: N008 (  3, 12) [000000] H----------                    t0 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
IN0002:                           movz    x1, #0x68BC      // data for _cpblk:DATA
IN0003:                           movk    x1, #0xD0ED LSL #16
IN0004:                           movk    x1, #0x7FFC LSL #32
                                                                        /--*  t0     long   
                                                                        +--*  t4     int    
Generating: N010 (  6, 14) [000003] nA---------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
IN0005:                           str     w0, [x1]
Added IP mapping: 0x0010 STACK_EMPTY (G_M14249_IG02,ins#5,ofs#20)
Generating: N012 (???,???) [000033] -----------                            IL_OFFSET void   INLRT @ 0x010[E-] REG NA
Generating: N014 (  1,  2) [000010] -----------                   t10 =    CNS_INT   int    0xFFFFFFFF REG x0
IN0006:                           movn    w0, #0
                                                                        /--*  t10    int    
Generating: N016 (  2,  3) [000013] -c---------                   t13 = *  INIT_VAL  int    REG NA
Generating: N018 (  1,  2) [000007] -----------                    t7 =    CNS_INT   int    4 REG x1
IN0007:                           mov     w1, #4
                                                                        /--*  t7     int    
Generating: N020 (  2,  4) [000008] -----------                    t8 = *  CAST      long <- int REG x1
IN0008:                           sxtw    x1, w1
                                                                        /--*  t8     long   
Generating: N022 (  6, 17) [000009] -c---------                    t9 = *  LEA(b+-789747524) long   REG NA
                                                                        /--*  t9     long   
                                                                        +--*  t13    int    
Generating: N024 (  9, 19) [000012] -A-X-------                         *  STORE_BLK struct<4> (init) (Unroll) REG NA
IN0009:                           movz    x2, #0x9744
IN000a:                           movk    x2, #0x2F12 LSL #16
IN000b:                           sub     x2, x1, x2
IN000c:                           str     w0, [x2]
Added IP mapping: 0x0022 STACK_EMPTY (G_M14249_IG02,ins#12,ofs#48)
Generating: N026 (???,???) [000034] -----------                            IL_OFFSET void   INLRT @ 0x022[E-] REG NA
Generating: N028 (  3, 12) [000015] H----------                   t15 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x0
IN000d:                           movz    x0, #0x68BC      // data for _cpblk:DATA
IN000e:                           movk    x0, #0xD0ED LSL #16
IN000f:                           movk    x0, #0x7FFC LSL #32
                                                                        /--*  t15    long   
Generating: N030 (  6, 14) [000016] n---G------                   t16 = *  IND       int    REG x0
IN0010:                           ldr     w0, [x0]
Generating: N032 (  1,  4) [000017] -----------                   t17 =    CNS_INT   int    -0x55555556 REG x1
IN0011:                           mov     w1, #0xAAAAAAAA
                                                                        /--*  t16    int    
                                                                        +--*  t17    int    
Generating: N034 (  8, 19) [000018] J---G--N---                         *  NE        void   REG NA
IN0012:                           cmp     w0, w1
Generating: N036 ( 10, 21) [000019] ----G------                         *  JTRUE     void   REG NA
IN0013:                           bne     (LARGEJMP)L_M14249_BB04

Variable Live Range History Dump for BB01
..None..

=============== Generating BB02 [034..047) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.20000020: i LIR 
BB02 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M14249_BB02:
Added IP mapping: 0x0034 STACK_EMPTY (G_M14249_IG02,ins#19,ofs#80) label
Generating: N040 (???,???) [000035] -----------                            IL_OFFSET void   INLRT @ 0x034[E-] REG NA
Generating: N042 (  1,  2) [000023] -----------                   t23 =    CNS_INT   int    4 REG x0
IN0014:                           mov     w0, #4
                                                                        /--*  t23    int    
Generating: N044 (  2,  4) [000024] -----------                   t24 = *  CAST      long <- int REG x0
IN0015:                           sxtw    x0, w0
Generating: N046 (  3, 12) [000022] H----------                   t22 =    CNS_INT(h) long   0x7ffcd0ed68bc static Fseq[DATA] REG x1
IN0016:                           movz    x1, #0x68BC      // data for _cpblk:DATA
IN0017:                           movk    x1, #0xD0ED LSL #16
IN0018:                           movk    x1, #0x7FFC LSL #32
                                                                        /--*  t24    long   
                                                                        +--*  t22    long   
Generating: N048 (  6, 17) [000025] -c---------                   t25 = *  LEA(b+(i*1)+0) long   REG NA
                                                                        /--*  t25    long   
Generating: N050 (  8, 18) [000026] U--XG------                   t26 = *  IND       int    REG x0
IN0019:                           ldr     w0, [x0, x1]
Generating: N052 (  1,  2) [000027] -c---------                   t27 =    CNS_INT   int    -1 REG NA
                                                                        /--*  t26    int    
                                                                        +--*  t27    int    
Generating: N054 ( 10, 21) [000028] J--XG--N---                         *  NE        void   REG NA
IN001a:                           cmn     w0, #1
Generating: N056 ( 12, 23) [000029] ---XG------                         *  JTRUE     void   REG NA
IN001b:                           bne     (LARGEJMP)L_M14249_BB04

Variable Live Range History Dump for BB02
..None..

=============== Generating BB03 [047..049) (return), preds={BB02} succs={} flags=0x00000000.20000020: i LIR 
BB03 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M14249_BB03:
Added IP mapping: 0x0047 STACK_EMPTY (G_M14249_IG02,ins#27,ofs#116) label
Generating: N060 (???,???) [000036] -----------                            IL_OFFSET void   INLRT @ 0x047[E-] REG NA
Generating: N062 (  1,  2) [000030] -----------                   t30 =    CNS_INT   int    1 REG x0
IN001c:                           mov     w0, #1
                                                                        /--*  t30    int    
Generating: N064 (  2,  3) [000031] -----------                         *  RETURN    int    REG NA
Added IP mapping: EPILOG (G_M14249_IG02,ins#28,ofs#120) label
Reserving epilog IG for block BB03

      G_M14249_IG02:        ; offs=000000H, funclet=00, bbWeight=1   , byref
*************** After placeholder IG creation
G_M14249_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M14249_IG02:        ; offs=000000H, size=0078H, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref
G_M14249_IG03:        ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M14249_IG04:        ; offs=000178H, size=0000H, gcrefRegs=0000 {} <-- Current IG

Variable Live Range History Dump for BB03
..None..

=============== Generating BB04 [049..04B) (return), preds={BB01,BB02} succs={} flags=0x00000000.20010020: i label LIR 
BB04 IN (0)={} + ByrefExposed + GcHeap
     OUT(0)={} + ByrefExposed + GcHeap

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M14249_BB04:
Mapped BB04 to G_M14249_IG04
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
Added IP mapping: 0x0049 STACK_EMPTY (G_M14249_IG04,ins#0,ofs#0) label
Generating: N068 (???,???) [000037] -----------                            IL_OFFSET void   INLRT @ 0x049[E-] REG NA
Generating: N070 (  1,  2) [000020] -----------                   t20 =    CNS_INT   int    0 REG x0
IN001d:                           mov     w0, wzr
                                                                        /--*  t20    int    
Generating: N072 (  2,  3) [000021] -----------                         *  RETURN    int    REG NA
Added IP mapping: EPILOG (G_M14249_IG04,ins#1,ofs#4) label
Reserving epilog IG for block BB04

      G_M14249_IG04:        ; offs=000178H, funclet=00, bbWeight=1   , gcvars, byref
*************** After placeholder IG creation
G_M14249_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M14249_IG02:        ; offs=000000H, size=0078H, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref
G_M14249_IG03:        ; epilog placeholder, next placeholder=IG05 , BB03 [0002], epilog, extend <-- First placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M14249_IG04:        ; offs=000178H, size=0004H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], gcvars, byref
G_M14249_IG05:        ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}

Variable Live Range History Dump for BB04
..None..
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =     47, compSizeEstimate =    91 _cpblk:initialize():int
; Final local variable assignments
;
;# V00 OutArgs      [V00    ] (  1,  1   )  lclBlk ( 0) [sp+00H]   do-not-enreg[] "OutgoingArgSpace"
;
; Lcl frame size = 0
*************** Before prolog / epilog generation
G_M14249_IG01:        ; func=00, offs=000000H, size=0000H, gcrefRegs=0000 {} <-- Prolog IG
G_M14249_IG02:        ; offs=000000H, size=0078H, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref
G_M14249_IG03:        ; epilog placeholder, next placeholder=IG05 , BB03 [0002], epilog, extend <-- First placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
G_M14249_IG04:        ; offs=000178H, size=0004H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], gcvars, byref
G_M14249_IG05:        ; epilog placeholder, next placeholder=<END>, BB04 [0003], epilog, extend <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M14249_IG01,ins#0,ofs#0) label

__prolog:
Save float regs: []
Save int   regs: [fp lr]
Frame type 1. #outsz=0; #framesz=16; LclFrameSize=0
IN001e:                           stp     fp, lr, [sp, #-0x10]!
    offset=16, calleeSaveSpDelta=0
    offsetSpToSavedFp=0
IN001f:                           mov     fp, sp
*************** In genEnregisterIncomingStackArgs()


      G_M14249_IG01:        ; offs=000000H, funclet=00, bbWeight=1   , gcvars, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
Frame type 1. #outsz=0; #framesz=16; localloc? false
    calleeSaveSpOffset=16, calleeSaveSpDelta=0
IN0020:                           ldp     fp, lr, [sp], #0x10
IN0021:                           ret     lr

      G_M14249_IG03:        ; offs=000078H, funclet=00, bbWeight=1   , epilog, nogc, extend
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
Frame type 1. #outsz=0; #framesz=16; localloc? false
    calleeSaveSpOffset=16, calleeSaveSpDelta=0
IN0022:                           ldp     fp, lr, [sp], #0x10
IN0023:                           ret     lr

      G_M14249_IG05:        ; offs=00017CH, funclet=00, bbWeight=1   , epilog, nogc, extend
0 prologs, 2 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M14249_IG01:        ; func=00, offs=000000H, size=0008H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref, nogc <-- Prolog IG
G_M14249_IG02:        ; offs=000008H, size=0078H, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref
G_M14249_IG03:        ; offs=000080H, size=0008H, epilog, nogc, extend
G_M14249_IG04:        ; offs=000088H, size=0004H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], gcvars, byref
G_M14249_IG05:        ; offs=00008CH, size=0008H, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
IG02 IN0013 bne[8] -> IG04
IG02 IN001b bne[8] -> IG04
  total jump count: 2
Binding: IN0013:                           bne     (LARGEJMP)L_M14249_BB04
Binding L_M14249_BB04 to G_M14249_IG04
Estimate of fwd jump [55D8FB4C/019]: 0050 -> 0088 = 0038
Shrinking jump [55D8FB4C/019]
Binding: IN001b:                           bne     (LARGEJMP)L_M14249_BB04
Binding L_M14249_BB04 to G_M14249_IG04
Estimate of fwd jump [55D8FC2C/027]: 0070 -> 0084 = 0014
Shrinking jump [55D8FC2C/027]
Adjusted offset of BB03 from 0080 to 0078
Adjusted offset of BB04 from 0088 to 0080
Adjusted offset of BB05 from 008C to 0084
Total shrinkage =   8, min extra jump size = 4294967295

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x8C bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x10)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler


G_M14249_IG01:        ; func=00, offs=000000H, size=0008H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref, nogc <-- Prolog IG
IN001e: 000000  A9BF7BFD          stp     fp, lr, [sp, #-0x10]!
IN001f: 000004  910003FD          mov     fp, sp
						;; size=8 bbWeight=1    PerfScore 1.50
G_M14249_IG02:        ; func=00, offs=000008H, size=0070H, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref, isz
IN0001: 000008  3201F3E0          mov     w0, #0xAAAAAAAA
IN0002: 00000C  D28D1781          movz    x1, #0x68BC      // data for _cpblk:DATA
IN0003: 000010  F2BA1DA1          movk    x1, #0xD0ED LSL #16
IN0004: 000014  F2CFFF81          movk    x1, #0x7FFC LSL #32
IN0005: 000018  B9000020          str     w0, [x1]
IN0006: 00001C  12800000          movn    w0, #0
IN0007: 000020  52800081          mov     w1, #4
IN0008: 000024  93407C21          sxtw    x1, w1
IN0009: 000028  D292E882          movz    x2, #0x9744
IN000a: 00002C  F2A5E242          movk    x2, #0x2F12 LSL #16
IN000b: 000030  CB020022          sub     x2, x1, x2
IN000c: 000034  B9000040          str     w0, [x2]
IN000d: 000038  D28D1780          movz    x0, #0x68BC      // data for _cpblk:DATA
IN000e: 00003C  F2BA1DA0          movk    x0, #0xD0ED LSL #16
IN000f: 000040  F2CFFF80          movk    x0, #0x7FFC LSL #32
IN0010: 000044  B9400000          ldr     w0, [x0]
IN0011: 000048  3201F3E1          mov     w1, #0xAAAAAAAA
IN0012: 00004C  6B01001F          cmp     w0, w1
IN0013: 000050  54000181          bne     G_M14249_IG04
IN0014: 000054  52800080          mov     w0, #4
IN0015: 000058  93407C00          sxtw    x0, w0
IN0016: 00005C  D28D1781          movz    x1, #0x68BC      // data for _cpblk:DATA
IN0017: 000060  F2BA1DA1          movk    x1, #0xD0ED LSL #16
IN0018: 000064  F2CFFF81          movk    x1, #0x7FFC LSL #32
IN0019: 000068  B8616800          ldr     w0, [x0, x1]
IN001a: 00006C  3100041F          cmn     w0, #1
IN001b: 000070  54000081          bne     G_M14249_IG04
IN001c: 000074  52800020          mov     w0, #1
						;; size=112 bbWeight=1    PerfScore 21.00
G_M14249_IG03:        ; func=00, offs=000078H, size=0008H, epilog, nogc, extend
IN0020: 000078  A8C17BFD          ldp     fp, lr, [sp], #0x10
IN0021: 00007C  D65F03C0          ret     lr
						;; size=8 bbWeight=1    PerfScore 2.00
G_M14249_IG04:        ; func=00, offs=000080H, size=0004H, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], gcvars, byref
IN001d: 000080  2A1F03E0          mov     w0, wzr
						;; size=4 bbWeight=1    PerfScore 0.50
G_M14249_IG05:        ; func=00, offs=000084H, size=0008H, epilog, nogc, extend
IN0022: 000084  A8C17BFD          ldp     fp, lr, [sp], #0x10
IN0023: 000088  D65F03C0          ret     lr
						;; size=8 bbWeight=1    PerfScore 2.00Allocated method code size =  140 , actual size =  140, unused size =    0

; Total bytes of code 140, prolog size 8, PerfScore 41.00, instruction count 35, allocated bytes for code 140 (MethodHash=f85ac856) for method _cpblk:initialize():int
; ============================================================

*************** After end code gen, before unwindEmit()
G_M14249_IG01:        ; func=00, offs=000000H, size=0008H, bbWeight=1    PerfScore 1.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, gcvars, byref, nogc <-- Prolog IG

IN001e: 000000                    stp     fp, lr, [sp, #-0x10]!
IN001f: 000004                    mov     fp, sp

G_M14249_IG02:        ; offs=000008H, size=0070H, bbWeight=1    PerfScore 21.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], BB02 [0001], BB03 [0002], byref, isz

IN0001: 000008                    mov     w0, #0xAAAAAAAA
IN0002: 00000C                    movz    x1, #0x68BC      // data for _cpblk:DATA
IN0003: 000010                    movk    x1, #0xD0ED LSL #16
IN0004: 000014                    movk    x1, #0x7FFC LSL #32
IN0005: 000018                    str     w0, [x1]
IN0006: 00001C                    movn    w0, #0
IN0007: 000020                    mov     w1, #4
IN0008: 000024                    sxtw    x1, w1
IN0009: 000028                    movz    x2, #0x9744
IN000a: 00002C                    movk    x2, #0x2F12 LSL #16
IN000b: 000030                    sub     x2, x1, x2
IN000c: 000034                    str     w0, [x2]
IN000d: 000038                    movz    x0, #0x68BC      // data for _cpblk:DATA
IN000e: 00003C                    movk    x0, #0xD0ED LSL #16
IN000f: 000040                    movk    x0, #0x7FFC LSL #32
IN0010: 000044                    ldr     w0, [x0]
IN0011: 000048                    mov     w1, #0xAAAAAAAA
IN0012: 00004C                    cmp     w0, w1
IN0013: 000050                    bne     G_M14249_IG04
IN0014: 000054                    mov     w0, #4
IN0015: 000058                    sxtw    x0, w0
IN0016: 00005C                    movz    x1, #0x68BC      // data for _cpblk:DATA
IN0017: 000060                    movk    x1, #0xD0ED LSL #16
IN0018: 000064                    movk    x1, #0x7FFC LSL #32
IN0019: 000068                    ldr     w0, [x0, x1]
IN001a: 00006C                    cmn     w0, #1
IN001b: 000070                    bne     G_M14249_IG04
IN001c: 000074                    mov     w0, #1

G_M14249_IG03:        ; offs=000078H, size=0008H, bbWeight=1    PerfScore 2.00, epilog, nogc, extend

IN0020: 000078                    ldp     fp, lr, [sp], #0x10
IN0021: 00007C                    ret     lr

G_M14249_IG04:        ; offs=000080H, size=0004H, bbWeight=1    PerfScore 0.50, gcVars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB04 [0003], gcvars, byref

IN001d: 000080                    mov     w0, wzr

G_M14249_IG05:        ; offs=000084H, size=0008H, bbWeight=1    PerfScore 2.00, epilog, nogc, extend

IN0022: 000084                    ldp     fp, lr, [sp], #0x10
IN0023: 000088                    ret     lr


*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0x00008c (not in unwind data)
  Code Words        : 1
  Epilog Count      : 2
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 35 (0x00023) Actual length = 140 (0x00008c)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 30 (0x0001e) Actual offset = 120 (0x000078) Offset from main function begin = 120 (0x000078)
  Epilog Start Index         : 1 (0x01)
  ---- Scope 1
  Epilog Start Offset        : 33 (0x00021) Actual offset = 132 (0x000084) Offset from main function begin = 132 (0x000084)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    81          save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]!
    E4          end
    E4          end

allocUnwindInfo(pHotCode=0x00007FFCD0D31780, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x8c, unwindSize=0x10, pUnwindBlock=0x0000024455D8A306, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 9
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000008 ( STACK_EMPTY )
IL offs 0x0010 : 0x0000001C ( STACK_EMPTY )
IL offs 0x0022 : 0x00000038 ( STACK_EMPTY )
IL offs 0x0034 : 0x00000054 ( STACK_EMPTY )
IL offs 0x0047 : 0x00000074 ( STACK_EMPTY )
IL offs EPILOG : 0x00000078 ( STACK_EMPTY )
IL offs 0x0049 : 0x00000080 ( STACK_EMPTY )
IL offs EPILOG : 0x00000084 ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 0
; Variable debug info: 0 live ranges, 0 vars for method _cpblk:initialize():int
VARIABLE LIVE RANGES:
..None..
*************** In gcInfoBlockHdrSave()
Set code length to 140.
Set ReturnKind to Scalar.
Set stack base register to fp.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:

*************** Finishing PHASE Emit GC+EH tables
Method code size: 140

Allocations for _cpblk:initialize():int (MethodHash=f85ac856)
count:        367, size:      40616, max =       5128
allocateMemory:      65536, nraUsed:      43232

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
         AssertionProp |          0 |   0.00%
               ASTNode |       5520 |  13.59%
              InstDesc |       8156 |  20.08%
              ImpStack |        384 |   0.95%
            BasicBlock |       1504 |   3.70%
              CallArgs |          0 |   0.00%
              FlowList |        160 |   0.39%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |          0 |   0.00%
                  LSRA |       6984 |  17.20%
         LSRA_Interval |       1200 |   2.95%
      LSRA_RefPosition |       2592 |   6.38%
          Reachability |        120 |   0.30%
                   SSA |          0 |   0.00%
           ValueNumber |          0 |   0.00%
              LvaTable |       2176 |   5.36%
            UnwindInfo |        136 |   0.33%
                hashBv |        160 |   0.39%
                bitset |        120 |   0.30%
          FixedBitVect |         32 |   0.08%
               Generic |        928 |   2.28%
   LocalAddressVisitor |          0 |   0.00%
         FieldSeqStore |        144 |   0.35%
          MemorySsaMap |          0 |   0.00%
          MemoryPhiArg |          0 |   0.00%
                   CSE |          0 |   0.00%
                    GC |       1248 |   3.07%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        232 |   0.57%
            ArrayStack |          0 |   0.00%
             DebugInfo |        432 |   1.06%
             DebugOnly |       7004 |  17.24%
               Codegen |       1088 |   2.68%
               LoopOpt |         96 |   0.24%
             LoopClone |          0 |   0.00%
             LoopHoist |          0 |   0.00%
               Unknown |         80 |   0.20%
            RangeCheck |          0 |   0.00%
              CopyProp |          0 |   0.00%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |         40 |   0.10%
           ClassLayout |         80 |   0.20%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |          0 |   0.00%
                   Pgo |          0 |   0.00%

****** DONE compiling _cpblk:initialize():int