diff --git a/src/coreclr/jit/fgdiagnostic.cpp b/src/coreclr/jit/fgdiagnostic.cpp
index 146866f961d696..b28794d8cdd067 100644
--- a/src/coreclr/jit/fgdiagnostic.cpp
+++ b/src/coreclr/jit/fgdiagnostic.cpp
@@ -3428,10 +3428,12 @@ void Compiler::fgDebugCheckFlags(GenTree* tree, BasicBlock* block)
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_GetFfrByte:
+ case NI_Sve_GetFfrDouble:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
case NI_Sve_GetFfrInt64:
case NI_Sve_GetFfrSByte:
+ case NI_Sve_GetFfrSingle:
case NI_Sve_GetFfrUInt16:
case NI_Sve_GetFfrUInt32:
case NI_Sve_GetFfrUInt64:
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
index a5f5f9fda75aed..2634ad8e0632c2 100644
--- a/src/coreclr/jit/gentree.cpp
+++ b/src/coreclr/jit/gentree.cpp
@@ -28802,10 +28802,12 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_GatherPrefetch8Bit:
case NI_Sve_GetFfrByte:
+ case NI_Sve_GetFfrDouble:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
case NI_Sve_GetFfrInt64:
case NI_Sve_GetFfrSByte:
+ case NI_Sve_GetFfrSingle:
case NI_Sve_GetFfrUInt16:
case NI_Sve_GetFfrUInt32:
case NI_Sve_GetFfrUInt64:
@@ -29020,10 +29022,12 @@ void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_GetFfrByte:
+ case NI_Sve_GetFfrDouble:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
case NI_Sve_GetFfrInt64:
case NI_Sve_GetFfrSByte:
+ case NI_Sve_GetFfrSingle:
case NI_Sve_GetFfrUInt16:
case NI_Sve_GetFfrUInt32:
case NI_Sve_GetFfrUInt64:
diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h
index 75e9603c8946ea..6fb3f89104ec06 100644
--- a/src/coreclr/jit/hwintrinsiclistarm64sve.h
+++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h
@@ -58,11 +58,11 @@ HARDWARE_INTRINSIC(Sve, Count16BitElements,
HARDWARE_INTRINSIC(Sve, Count32BitElements, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cntw, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(Sve, Count64BitElements, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cntd, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(Sve, Count8BitElements, 0, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cntb, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed)
-HARDWARE_INTRINSIC(Sve, CreateBreakAfterMask, -1, 2, {INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen)
-HARDWARE_INTRINSIC(Sve, CreateBreakAfterPropagateMask, -1, 3, {INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation)
-HARDWARE_INTRINSIC(Sve, CreateBreakBeforeMask, -1, 2, {INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen)
-HARDWARE_INTRINSIC(Sve, CreateBreakBeforePropagateMask, -1, 3, {INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation)
-HARDWARE_INTRINSIC(Sve, CreateBreakPropagateMask, -1, -1, {INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_HasRMWSemantics|HW_Flag_ZeroingMaskedOperation)
+HARDWARE_INTRINSIC(Sve, CreateBreakAfterMask, -1, 2, {INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka, INS_sve_brka}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CreateBreakAfterPropagateMask, -1, 3, {INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa, INS_sve_brkpa}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation)
+HARDWARE_INTRINSIC(Sve, CreateBreakBeforeMask, -1, 2, {INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb, INS_sve_brkb}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, CreateBreakBeforePropagateMask, -1, 3, {INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb, INS_sve_brkpb}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation)
+HARDWARE_INTRINSIC(Sve, CreateBreakPropagateMask, -1, -1, {INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn, INS_sve_brkn}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_HasRMWSemantics|HW_Flag_ZeroingMaskedOperation)
HARDWARE_INTRINSIC(Sve, CreateFalseMaskByte, -1, 0, {INS_invalid, INS_sve_pfalse, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(Sve, CreateFalseMaskDouble, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_pfalse}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(Sve, CreateFalseMaskInt16, -1, 0, {INS_invalid, INS_invalid, INS_sve_pfalse, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
@@ -73,7 +73,7 @@ HARDWARE_INTRINSIC(Sve, CreateFalseMaskSingle,
HARDWARE_INTRINSIC(Sve, CreateFalseMaskUInt16, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_sve_pfalse, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(Sve, CreateFalseMaskUInt32, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_pfalse, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(Sve, CreateFalseMaskUInt64, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_pfalse, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport)
-HARDWARE_INTRINSIC(Sve, CreateMaskForFirstActiveElement, -1, 2, {INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
+HARDWARE_INTRINSIC(Sve, CreateMaskForFirstActiveElement, -1, 2, {INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst, INS_sve_pfirst}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve, CreateMaskForNextActiveElement, -1, 2, {INS_invalid, INS_sve_pnext, INS_invalid, INS_sve_pnext, INS_invalid, INS_sve_pnext, INS_invalid, INS_sve_pnext, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_ReturnsPerElementMask|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve, CreateTrueMaskByte, -1, 1, {INS_invalid, INS_sve_ptrue, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_SpecialImport)
HARDWARE_INTRINSIC(Sve, CreateTrueMaskDouble, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ptrue}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_SpecialImport)
@@ -139,10 +139,12 @@ HARDWARE_INTRINSIC(Sve, GatherVectorWithByteOffsetFirstFaulting,
HARDWARE_INTRINSIC(Sve, GatherVectorWithByteOffsets, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ld1w, INS_sve_ld1w, INS_sve_ld1d, INS_sve_ld1d, INS_sve_ld1w, INS_sve_ld1d}, HW_Category_MemoryLoad, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ZeroingMaskedOperation)
HARDWARE_INTRINSIC(Sve, GetActiveElementCount, -1, 2, {INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp, INS_sve_cntp}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_ExplicitMaskedOperation)
HARDWARE_INTRINSIC(Sve, GetFfrByte, -1, 0, {INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
+HARDWARE_INTRINSIC(Sve, GetFfrDouble, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrInt16, -1, 0, {INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrInt32, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrInt64, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrSByte, -1, 0, {INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
+HARDWARE_INTRINSIC(Sve, GetFfrSingle, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrUInt16, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrUInt32, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, GetFfrUInt64, -1, 0, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_rdffr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ReturnsPerElementMask|HW_Flag_SpecialSideEffect_Other)
@@ -269,7 +271,7 @@ HARDWARE_INTRINSIC(Sve, Scatter32BitWithByteOffsetsNarrowing,
HARDWARE_INTRINSIC(Sve, Scatter8BitNarrowing, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_st1b, INS_sve_st1b, INS_sve_st1b, INS_sve_st1b, INS_invalid, INS_invalid}, HW_Category_MemoryStore, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, Scatter8BitWithByteOffsetsNarrowing, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_st1b, INS_sve_st1b, INS_sve_st1b, INS_sve_st1b, INS_invalid, INS_invalid}, HW_Category_MemoryStore, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, ScatterWithByteOffsets, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_st1w, INS_sve_st1w, INS_sve_st1d, INS_sve_st1d, INS_sve_st1w, INS_sve_st1d}, HW_Category_MemoryStore, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation)
-HARDWARE_INTRINSIC(Sve, SetFfr, -1, 1, {INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialSideEffect_Other|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, SetFfr, -1, 1, {INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr, INS_sve_wrffr}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialSideEffect_Other|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, ShiftLeftLogical, -1, -1, {INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_sve_lsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve, ShiftRightArithmetic, -1, -1, {INS_sve_asr, INS_invalid, INS_sve_asr, INS_invalid, INS_sve_asr, INS_invalid, INS_sve_asr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve, ShiftRightArithmeticForDivide, -1, -1, {INS_sve_asrd, INS_invalid, INS_sve_asrd, INS_invalid, INS_sve_asrd, INS_invalid, INS_sve_asrd, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_HasImmediateOperand)
@@ -286,9 +288,9 @@ HARDWARE_INTRINSIC(Sve, StoreNarrowing,
HARDWARE_INTRINSIC(Sve, StoreNonTemporal, -1, 3, {INS_sve_stnt1b, INS_sve_stnt1b, INS_sve_stnt1h, INS_sve_stnt1h, INS_sve_stnt1w, INS_sve_stnt1w, INS_sve_stnt1d, INS_sve_stnt1d, INS_sve_stnt1w, INS_sve_stnt1d}, HW_Category_MemoryStore, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_ExplicitMaskedOperation|HW_Flag_SpecialCodeGen|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, Subtract, -1, 2, {INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_sub, INS_sve_fsub, INS_sve_fsub}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, SubtractSaturate, -1, 2, {INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
-HARDWARE_INTRINSIC(Sve, TestAnyTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
-HARDWARE_INTRINSIC(Sve, TestFirstTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
-HARDWARE_INTRINSIC(Sve, TestLastTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, TestAnyTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, TestFirstTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
+HARDWARE_INTRINSIC(Sve, TestLastTrue, -1, 2, {INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest, INS_sve_ptest}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, TransposeEven, -1, 2, {INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1, INS_sve_trn1}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasAllMaskVariant)
HARDWARE_INTRINSIC(Sve, TransposeOdd, -1, 2, {INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2, INS_sve_trn2}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasAllMaskVariant)
HARDWARE_INTRINSIC(Sve, TrigonometricMultiplyAddCoefficient, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_ftmad, INS_sve_ftmad}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SpecialCodeGen)
diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp
index c8f677347601cc..602cf4f2b4624f 100644
--- a/src/coreclr/jit/lowerarmarch.cpp
+++ b/src/coreclr/jit/lowerarmarch.cpp
@@ -1875,10 +1875,12 @@ GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node)
}
case NI_Sve_GetFfrByte:
+ case NI_Sve_GetFfrDouble:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
case NI_Sve_GetFfrInt64:
case NI_Sve_GetFfrSByte:
+ case NI_Sve_GetFfrSingle:
case NI_Sve_GetFfrUInt16:
case NI_Sve_GetFfrUInt32:
case NI_Sve_GetFfrUInt64:
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
index f37e70545e9dcf..819b72cec57008 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
@@ -2086,6 +2086,12 @@ internal Arm64() { }
// Break after first true condition
+ ///
+ /// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKA Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
/// BRKA Presult.B, Pg/Z, Pop.B
@@ -2134,9 +2140,21 @@ internal Arm64() { }
///
public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKA Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
// Break after first true condition, propagating from previous partition
+ ///
+ /// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
@@ -2185,9 +2203,21 @@ internal Arm64() { }
///
public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
// Break before first true condition
+ ///
+ /// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKB Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
/// BRKB Presult.B, Pg/Z, Pop.B
@@ -2236,9 +2266,21 @@ internal Arm64() { }
///
public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKB Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
// Break before first true condition, propagating from previous partition
+ ///
+ /// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
@@ -2287,9 +2329,21 @@ internal Arm64() { }
///
public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) { throw new PlatformNotSupportedException(); }
+
// Propagate break to next partition
+ ///
+ /// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
+ ///
+ public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
@@ -2338,6 +2392,12 @@ internal Arm64() { }
///
public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
+ ///
+ public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
// Set all predicate elements to false
@@ -2431,6 +2491,12 @@ internal Arm64() { }
// Set the first active predicate element to true
+ ///
+ /// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
+ /// PFIRST Ptied.B, Pg, Ptied.B
+ ///
+ public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
/// PFIRST Ptied.B, Pg, Ptied.B
@@ -2479,6 +2545,12 @@ internal Arm64() { }
///
public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
+ /// PFIRST Ptied.B, Pg, Ptied.B
+ ///
+ public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) { throw new PlatformNotSupportedException(); }
+
// Find next active predicate
@@ -5341,6 +5413,12 @@ internal Arm64() { }
///
public static Vector GetFfrByte() { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svrdffr()
+ /// RDFFR Presult.B
+ ///
+ public static Vector GetFfrDouble() { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svrdffr()
/// RDFFR Presult.B
@@ -5365,6 +5443,12 @@ internal Arm64() { }
///
public static Vector GetFfrSByte() { throw new PlatformNotSupportedException(); }
+ ///
+ /// svbool_t svrdffr()
+ /// RDFFR Presult.B
+ ///
+ public static Vector GetFfrSingle() { throw new PlatformNotSupportedException(); }
+
///
/// svbool_t svrdffr()
/// RDFFR Presult.B
@@ -9154,6 +9238,12 @@ internal Arm64() { }
// Write to the first-fault register
+ ///
+ /// void svwrffr(svbool_t op)
+ /// WRFFR Pop.B
+ ///
+ public static void SetFfr(Vector value) { throw new PlatformNotSupportedException(); }
+
///
/// void svwrffr(svbool_t op)
/// WRFFR Pop.B
@@ -9202,6 +9292,12 @@ internal Arm64() { }
///
public static void SetFfr(Vector value) { throw new PlatformNotSupportedException(); }
+ ///
+ /// void svwrffr(svbool_t op)
+ /// WRFFR Pop.B
+ ///
+ public static void SetFfr(Vector value) { throw new PlatformNotSupportedException(); }
+
// Logical shift left
@@ -10169,6 +10265,12 @@ internal Arm64() { }
// Test whether any active element is true
+ ///
+ /// bool svptest_any(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestAnyTrue(Vector mask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
///
/// bool svptest_any(svbool_t pg, svbool_t op)
/// PTEST
@@ -10217,9 +10319,21 @@ internal Arm64() { }
///
public static bool TestAnyTrue(Vector mask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// bool svptest_any(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestAnyTrue(Vector mask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
// Test whether the first active element is true
+ ///
+ /// bool svptest_first(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestFirstTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
///
/// bool svptest_first(svbool_t pg, svbool_t op)
/// PTEST
@@ -10268,9 +10382,21 @@ internal Arm64() { }
///
public static bool TestFirstTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// bool svptest_first(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestFirstTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
// Test whether the last active element is true
+ ///
+ /// bool svptest_last(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestLastTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
///
/// bool svptest_last(svbool_t pg, svbool_t op)
/// PTEST
@@ -10319,6 +10445,12 @@ internal Arm64() { }
///
public static bool TestLastTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+ ///
+ /// bool svptest_last(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestLastTrue(Vector leftMask, Vector rightMask) { throw new PlatformNotSupportedException(); }
+
// Interleave even elements from two inputs
diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
index bd752b482cd150..69d4375549fd7d 100644
--- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
+++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
@@ -2083,6 +2083,12 @@ internal Arm64() { }
// Break after first true condition
+ ///
+ /// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKA Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) => CreateBreakAfterMask(totalMask, fromMask);
+
///
/// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
/// BRKA Presult.B, Pg/Z, Pop.B
@@ -2131,9 +2137,21 @@ internal Arm64() { }
///
public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) => CreateBreakAfterMask(totalMask, fromMask);
+ ///
+ /// svbool_t svbrka[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKA Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakAfterMask(Vector totalMask, Vector fromMask) => CreateBreakAfterMask(totalMask, fromMask);
+
// Break after first true condition, propagating from previous partition
+ ///
+ /// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) => CreateBreakAfterPropagateMask(mask, left, right);
+
///
/// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
@@ -2182,9 +2200,21 @@ internal Arm64() { }
///
public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) => CreateBreakAfterPropagateMask(mask, left, right);
+ ///
+ /// svbool_t svbrkpa[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPA Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakAfterPropagateMask(Vector mask, Vector left, Vector right) => CreateBreakAfterPropagateMask(mask, left, right);
+
// Break before first true condition
+ ///
+ /// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKB Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) => CreateBreakBeforeMask(totalMask, fromMask);
+
///
/// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
/// BRKB Presult.B, Pg/Z, Pop.B
@@ -2233,9 +2263,21 @@ internal Arm64() { }
///
public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) => CreateBreakBeforeMask(totalMask, fromMask);
+ ///
+ /// svbool_t svbrkb[_b]_z(svbool_t pg, svbool_t op)
+ /// BRKB Presult.B, Pg/Z, Pop.B
+ ///
+ public static Vector CreateBreakBeforeMask(Vector totalMask, Vector fromMask) => CreateBreakBeforeMask(totalMask, fromMask);
+
// Break before first true condition, propagating from previous partition
+ ///
+ /// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) => CreateBreakBeforePropagateMask(mask, left, right);
+
///
/// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
@@ -2284,9 +2326,21 @@ internal Arm64() { }
///
public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) => CreateBreakBeforePropagateMask(mask, left, right);
+ ///
+ /// svbool_t svbrkpb[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKPB Presult.B, Pg/Z, Pop1.B, Pop2.B
+ ///
+ public static Vector CreateBreakBeforePropagateMask(Vector mask, Vector left, Vector right) => CreateBreakBeforePropagateMask(mask, left, right);
+
// Propagate break to next partition
+ ///
+ /// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
+ ///
+ public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) => CreateBreakPropagateMask(totalMask, fromMask);
+
///
/// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
@@ -2335,6 +2389,12 @@ internal Arm64() { }
///
public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) => CreateBreakPropagateMask(totalMask, fromMask);
+ ///
+ /// svbool_t svbrkn[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
+ /// BRKN Ptied2.B, Pg/Z, Pop1.B, Ptied2.B
+ ///
+ public static Vector CreateBreakPropagateMask(Vector totalMask, Vector fromMask) => CreateBreakPropagateMask(totalMask, fromMask);
+
// Set all predicate elements to false
@@ -2428,6 +2488,12 @@ internal Arm64() { }
// Set the first active predicate element to true
+ ///
+ /// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
+ /// PFIRST Ptied.B, Pg, Ptied.B
+ ///
+ public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) => CreateMaskForFirstActiveElement(totalMask, fromMask);
+
///
/// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
/// PFIRST Ptied.B, Pg, Ptied.B
@@ -2476,6 +2542,12 @@ internal Arm64() { }
///
public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) => CreateMaskForFirstActiveElement(totalMask, fromMask);
+ ///
+ /// svbool_t svpfirst[_b](svbool_t pg, svbool_t op)
+ /// PFIRST Ptied.B, Pg, Ptied.B
+ ///
+ public static Vector CreateMaskForFirstActiveElement(Vector totalMask, Vector fromMask) => CreateMaskForFirstActiveElement(totalMask, fromMask);
+
// Find next active predicate
@@ -5338,6 +5410,12 @@ internal Arm64() { }
///
public static Vector GetFfrByte() => GetFfrByte();
+ ///
+ /// svbool_t svrdffr()
+ /// RDFFR Presult.B
+ ///
+ public static Vector GetFfrDouble() => GetFfrDouble();
+
///
/// svbool_t svrdffr()
/// RDFFR Presult.B
@@ -5362,6 +5440,12 @@ internal Arm64() { }
///
public static Vector GetFfrSByte() => GetFfrSByte();
+ ///
+ /// svbool_t svrdffr()
+ /// RDFFR Presult.B
+ ///
+ public static Vector GetFfrSingle() => GetFfrSingle();
+
///
/// svbool_t svrdffr()
/// RDFFR Presult.B
@@ -9145,6 +9229,12 @@ internal Arm64() { }
// Write to the first-fault register
+ ///
+ /// void svwrffr(svbool_t op)
+ /// WRFFR Pop.B
+ ///
+ public static void SetFfr(Vector value) => SetFfr(value);
+
///
/// void svwrffr(svbool_t op)
/// WRFFR Pop.B
@@ -9193,6 +9283,12 @@ internal Arm64() { }
///
public static void SetFfr(Vector value) => SetFfr(value);
+ ///
+ /// void svwrffr(svbool_t op)
+ /// WRFFR Pop.B
+ ///
+ public static void SetFfr(Vector value) => SetFfr(value);
+
// Logical shift left
@@ -10160,6 +10256,12 @@ internal Arm64() { }
// Test whether any active element is true
+ ///
+ /// bool svptest_any(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestAnyTrue(Vector mask, Vector rightMask) => TestAnyTrue(mask, rightMask);
+
///
/// bool svptest_any(svbool_t pg, svbool_t op)
/// PTEST
@@ -10208,9 +10310,21 @@ internal Arm64() { }
///
public static bool TestAnyTrue(Vector mask, Vector rightMask) => TestAnyTrue(mask, rightMask);
+ ///
+ /// bool svptest_any(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestAnyTrue(Vector mask, Vector rightMask) => TestAnyTrue(mask, rightMask);
+
// Test whether the first active element is true
+ ///
+ /// bool svptest_first(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestFirstTrue(Vector leftMask, Vector rightMask) => TestFirstTrue(leftMask, rightMask);
+
///
/// bool svptest_first(svbool_t pg, svbool_t op)
/// PTEST
@@ -10259,9 +10373,21 @@ internal Arm64() { }
///
public static bool TestFirstTrue(Vector leftMask, Vector rightMask) => TestFirstTrue(leftMask, rightMask);
+ ///
+ /// bool svptest_first(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestFirstTrue(Vector leftMask, Vector rightMask) => TestFirstTrue(leftMask, rightMask);
+
// Test whether the last active element is true
+ ///
+ /// bool svptest_last(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestLastTrue(Vector leftMask, Vector rightMask) => TestLastTrue(leftMask, rightMask);
+
///
/// bool svptest_last(svbool_t pg, svbool_t op)
/// PTEST
@@ -10310,6 +10436,12 @@ internal Arm64() { }
///
public static bool TestLastTrue(Vector leftMask, Vector rightMask) => TestLastTrue(leftMask, rightMask);
+ ///
+ /// bool svptest_last(svbool_t pg, svbool_t op)
+ /// PTEST
+ ///
+ public static bool TestLastTrue(Vector leftMask, Vector rightMask) => TestLastTrue(leftMask, rightMask);
+
// Interleave even elements from two inputs
diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
index 479501776f2a19..b52aa5f58fc4f6 100644
--- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
+++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs
@@ -4876,6 +4876,7 @@ internal Arm64() { }
public static ulong Count32BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; }
public static ulong Count64BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; }
public static ulong Count8BitElements([ConstantExpected] SveMaskPattern pattern = SveMaskPattern.All) { throw null; }
+ public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
@@ -4884,6 +4885,8 @@ internal Arm64() { }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateBreakAfterMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
@@ -4892,6 +4895,8 @@ internal Arm64() { }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
+ public static System.Numerics.Vector CreateBreakAfterPropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
+ public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
@@ -4900,6 +4905,8 @@ internal Arm64() { }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateBreakBeforeMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
@@ -4908,6 +4915,8 @@ internal Arm64() { }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
+ public static System.Numerics.Vector CreateBreakBeforePropagateMask(System.Numerics.Vector mask, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; }
+ public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
@@ -4916,6 +4925,7 @@ internal Arm64() { }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateBreakPropagateMask(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateFalseMaskByte() { throw null; }
public static System.Numerics.Vector CreateFalseMaskDouble() { throw null; }
public static System.Numerics.Vector CreateFalseMaskInt16() { throw null; }
@@ -4926,6 +4936,7 @@ internal Arm64() { }
public static System.Numerics.Vector CreateFalseMaskUInt16() { throw null; }
public static System.Numerics.Vector CreateFalseMaskUInt32() { throw null; }
public static System.Numerics.Vector CreateFalseMaskUInt64() { throw null; }
+ public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
@@ -4934,6 +4945,7 @@ internal Arm64() { }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector totalMask, System.Numerics.Vector fromMask) { throw null; }
+ public static System.Numerics.Vector CreateMaskForFirstActiveElement(System.Numerics.Vector