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Expose cross-platform helpers for Vector64, Vector128, and Vector256 #53450

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merged 22 commits into from
Sep 30, 2021
Merged

Expose cross-platform helpers for Vector64, Vector128, and Vector256 #53450

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df33419
Refactoring Vector<T> to be alphabetically ordered and reduce duplica…
tannergooding May 22, 2021
bcf2bbd
Adding a debug view to System.Numerics.Vector<T>
tannergooding May 22, 2021
7ed4a28
Do some basic code cleanup and refactoring of Vector64/128/256
tannergooding May 22, 2021
b577114
Updating Vector64/128/256 to expose cross platform helper methods
tannergooding May 23, 2021
4cdec92
Adding templated tests for Vector64
tannergooding May 23, 2021
2f9ce11
Regenerating templated tests for Vector64
tannergooding May 23, 2021
4940fcf
Adding templated tests for Vector128
tannergooding May 23, 2021
ac9c477
Regenerating templated tests for Vector128
tannergooding May 23, 2021
557128e
Adding templated tests for Vector256
tannergooding May 23, 2021
81a012e
Regenerating templated tests for Vector256
tannergooding May 23, 2021
3245883
Fix getSIMDStructFromField to account for accessing the private ulong…
tannergooding May 24, 2021
37c521e
Ensure helper intrinsics don't insert on importation
tannergooding May 24, 2021
6cddb02
Minor cleanup of impBaseIntrinsic for x86/x64
tannergooding May 25, 2021
8c28873
Intrinsify the Vector64/128/256 methods
tannergooding May 26, 2021
1b665fc
Make the internal helper named IsTypeSupported to not conflict with m…
tannergooding May 30, 2021
f917ea6
Ensure we lie about the type for TYP_SIMD32 bitwise ops when only AVX…
tannergooding May 31, 2021
10dfe0c
Use gtNewSimdZeroNode rather than gtNewSIMDVectorZero
tannergooding Jun 1, 2021
6d34d27
Applying formatting patch
tannergooding Jun 1, 2021
57ce0a9
Apply suggestions from code review
tannergooding Jun 29, 2021
f2529d7
Apply suggestions from code review
tannergooding Jun 30, 2021
54610f9
Split HardwareIntrinsic tests into 3 groups
tannergooding Jun 30, 2021
fc5c5bc
Update src/coreclr/vm/class.cpp
tannergooding Sep 30, 2021
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198 changes: 145 additions & 53 deletions src/coreclr/jit/compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3122,65 +3122,53 @@ class Compiler
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize);
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, CorInfoType simdBaseJitType, unsigned simdSize);
unsigned simdSize,
bool isSimdAsHWIntrinsic = false);
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
GenTree* op1,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic = false);
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
GenTree* op1,
GenTree* op2,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize);
unsigned simdSize,
bool isSimdAsHWIntrinsic = false);
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize);
unsigned simdSize,
bool isSimdAsHWIntrinsic = false);
GenTreeHWIntrinsic* gtNewSimdHWIntrinsicNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
GenTree* op4,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize);

GenTreeHWIntrinsic* gtNewSimdCreateBroadcastNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTreeHWIntrinsic* gtNewSimdGetElementNode(var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTreeHWIntrinsic* gtNewSimdWithElementNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);
unsigned simdSize,
bool isSimdAsHWIntrinsic = false);

GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdBaseJitType,
unsigned simdSize)
{
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, hwIntrinsicID, simdBaseJitType, simdSize);
node->gtFlags |= GTF_SIMDASHW_OP;
return node;
bool isSimdAsHWIntrinsic = true;
return gtNewSimdHWIntrinsicNode(type, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
}

GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(
var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, CorInfoType simdBaseJitType, unsigned simdSize)
{
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, op1, hwIntrinsicID, simdBaseJitType, simdSize);
node->gtFlags |= GTF_SIMDASHW_OP;
return node;
bool isSimdAsHWIntrinsic = true;
return gtNewSimdHWIntrinsicNode(type, op1, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
}

GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
Expand All @@ -3190,9 +3178,8 @@ class Compiler
CorInfoType simdBaseJitType,
unsigned simdSize)
{
GenTreeHWIntrinsic* node = gtNewSimdHWIntrinsicNode(type, op1, op2, hwIntrinsicID, simdBaseJitType, simdSize);
node->gtFlags |= GTF_SIMDASHW_OP;
return node;
bool isSimdAsHWIntrinsic = true;
return gtNewSimdHWIntrinsicNode(type, op1, op2, hwIntrinsicID, simdBaseJitType, simdSize, isSimdAsHWIntrinsic);
}

GenTreeHWIntrinsic* gtNewSimdAsHWIntrinsicNode(var_types type,
Expand All @@ -3203,12 +3190,114 @@ class Compiler
CorInfoType simdBaseJitType,
unsigned simdSize)
{
GenTreeHWIntrinsic* node =
gtNewSimdHWIntrinsicNode(type, op1, op2, op3, hwIntrinsicID, simdBaseJitType, simdSize);
node->gtFlags |= GTF_SIMDASHW_OP;
return node;
bool isSimdAsHWIntrinsic = true;
return gtNewSimdHWIntrinsicNode(type, op1, op2, op3, hwIntrinsicID, simdBaseJitType, simdSize,
isSimdAsHWIntrinsic);
}

GenTree* gtNewSimdAbsNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdBinOpNode(genTreeOps op,
var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCeilNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCmpOpNode(genTreeOps op,
var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCmpOpAllNode(genTreeOps op,
var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCmpOpAnyNode(genTreeOps op,
var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCndSelNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdCreateBroadcastNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdDotProdNode(var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdFloorNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdGetElementNode(var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdMaxNode(var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdMinNode(var_types type,
GenTree* op1,
GenTree* op2,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdSqrtNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize, bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdUnOpNode(genTreeOps op,
var_types type,
GenTree* op1,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdWithElementNode(var_types type,
GenTree* op1,
GenTree* op2,
GenTree* op3,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTree* gtNewSimdZeroNode(var_types type,
CorInfoType simdBaseJitType,
unsigned simdSize,
bool isSimdAsHWIntrinsic);

GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID);
GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types type,
GenTree* op1,
Expand Down Expand Up @@ -4316,14 +4405,6 @@ class Compiler
unsigned simdSize,
GenTree* newobjThis);

GenTree* impSimdAsHWIntrinsicCndSel(CORINFO_CLASS_HANDLE clsHnd,
var_types retType,
CorInfoType simdBaseJitType,
unsigned simdSize,
GenTree* op1,
GenTree* op2,
GenTree* op3);

GenTree* impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_CLASS_HANDLE clsHnd,
CORINFO_METHOD_HANDLE method,
Expand Down Expand Up @@ -4353,14 +4434,6 @@ class Compiler
GenTree* impSSE2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
GenTree* impAvxOrAvx2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);
GenTree* impBMI1OrBMI2Intrinsic(NamedIntrinsic intrinsic, CORINFO_METHOD_HANDLE method, CORINFO_SIG_INFO* sig);

GenTree* impSimdAsHWIntrinsicRelOp(NamedIntrinsic intrinsic,
CORINFO_CLASS_HANDLE clsHnd,
var_types retType,
CorInfoType simdBaseJitType,
unsigned simdSize,
GenTree* op1,
GenTree* op2);
#endif // TARGET_XARCH
#endif // FEATURE_HW_INTRINSICS
GenTree* impArrayAccessIntrinsic(CORINFO_CLASS_HANDLE clsHnd,
Expand Down Expand Up @@ -8547,6 +8620,25 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#endif
}

#if defined(DEBUG)
bool IsBaselineSimdIsaSupportedDebugOnly()
{
#ifdef FEATURE_SIMD
#if defined(TARGET_XARCH)
CORINFO_InstructionSet minimumIsa = InstructionSet_SSE2;
#elif defined(TARGET_ARM64)
CORINFO_InstructionSet minimumIsa = InstructionSet_AdvSimd;
#else
#error Unsupported platform
#endif // !TARGET_XARCH && !TARGET_ARM64

return compIsaSupportedDebugOnly(minimumIsa) && JitConfig.EnableHWIntrinsic();
#else
return false;
#endif // FEATURE_SIMD
}
#endif // DEBUG

// Get highest available level for SIMD codegen
SIMDLevel getSIMDSupportLevel()
{
Expand Down
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