diff --git a/README.md b/README.md
index 29d53dc..26bdead 100644
--- a/README.md
+++ b/README.md
@@ -19,7 +19,7 @@ Design](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf).
 
 The simulation testcases available use [Icarus Verilog](http://iverilog.icarus.com) and [SVUT](https://github.com/dpretet/svut) tool to run the tests.
 
-The FIFO is fully functional and used in many successful project
+The FIFO is fully functional and used in many successful projects.
 
 # Usage
 
diff --git a/rtl/async_fifo.v b/rtl/async_fifo.v
index 3dd0833..5657a82 100644
--- a/rtl/async_fifo.v
+++ b/rtl/async_fifo.v
@@ -7,11 +7,16 @@
 module async_fifo
 
     #(
+        // Data width
         parameter DSIZE = 8,
+        // Address width
         parameter ASIZE = 4,
+        // Almost full thresold
         parameter AWFULLSIZE = 1,
+        // Almost empty thresold
         parameter AREMPTYSIZE = 1,
-        parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
+        // First word fall-through without latency
+        parameter FALLTHROUGH = "TRUE"
     )(
         input  wire             wclk,
         input  wire             wrst_n,
diff --git a/sim/Makefile b/sim/Makefile
index 772e649..0ca8877 100755
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -1,12 +1,12 @@
 test:
-	@svutRun -f files.f
+	@svutRun -f files.f -define "AFULL=1;AEMPTY=1"
+	@svutRun -f files.f -define "AFULL=3;AEMPTY=2"
 
 test-dry-run:
 	@svutRun -f files.f -dry-run
 
 gui:
 	@svutRun -f files.f -gui
-    :qa
 
 clean:
 	@-rm -f *.vcd
diff --git a/sim/async_fifo_unit_test.sv b/sim/async_fifo_unit_test.sv
index c9a2252..6f94feb 100644
--- a/sim/async_fifo_unit_test.sv
+++ b/sim/async_fifo_unit_test.sv
@@ -5,12 +5,26 @@ module async_fifo_unit_test;
 
     `SVUT_SETUP
 
-    integer i;
+    `ifndef AEMPTY
+    `define AEMPTY 1
+    `endif
+
+    `ifndef AFULL
+    `define AFULL 1
+    `endif
+
+    `ifndef FALLTHROUGH
+    `define FALLTHROUGH "TRUE"
+    `endif
 
     parameter DSIZE = 32;
     parameter ASIZE = 4;
-    parameter AREMPTYSIZE = 1;
-    parameter AWFULLSIZE = 1;
+    parameter AREMPTYSIZE = `AEMPTY;
+    parameter AWFULLSIZE = `AFULL;
+    parameter FALLTHROUGH = `FALLTHROUGH;
+    parameter MAX_TRAFFIC = 10;
+
+    integer timeout;
 
     reg              wclk;
     reg              wrst_n;
@@ -26,26 +40,27 @@ module async_fifo_unit_test;
     wire             arempty;
 
     async_fifo
-	#(
-		DSIZE,
-		ASIZE,
-        AWFULLSIZE,
-        AREMPTYSIZE
+    #(
+        .DSIZE        (DSIZE),
+        .ASIZE        (ASIZE),
+        .AWFULLSIZE   (AWFULLSIZE),
+        .AREMPTYSIZE  (AREMPTYSIZE),
+        .FALLTHROUGH  (FALLTHROUGH)
     )
     dut
     (
-		wclk,
-		wrst_n,
-		winc,
-		wdata,
-		wfull,
-		awfull,
-		rclk,
-		rrst_n,
-		rinc,
-		rdata,
-		rempty,
-		arempty
+        wclk,
+        wrst_n,
+        winc,
+        wdata,
+        wfull,
+        awfull,
+        rclk,
+        rrst_n,
+        rinc,
+        rdata,
+        rempty,
+        arempty
     );
 
     // An example to create a clock
@@ -55,13 +70,10 @@ module async_fifo_unit_test;
     always #3 rclk <= ~rclk;
 
     // An example to dump data for visualization
-`ifdef USE_VLOG_TB_UTILS
-   vlog_tb_utils vtu();
-`else
     initial begin
+        $dumpfile("async_fifo_unit_test.vcd");
         $dumpvars(0, async_fifo_unit_test);
     end
-`endif
 
     task setup(msg="Setup testcase");
     begin
@@ -75,6 +87,7 @@ module async_fifo_unit_test;
         wrst_n = 1;
         rrst_n = 1;
         #50;
+        timeout = 0;
         @(posedge wclk);
 
     end
@@ -88,14 +101,14 @@ module async_fifo_unit_test;
 
     `TEST_SUITE("ASYNCFIFO")
 
-    `UNIT_TEST("IDLE")
+    `UNIT_TEST("TEST_IDLE")
 
         `FAIL_IF(wfull);
         `FAIL_IF(!rempty);
 
     `UNIT_TEST_END
 
-    `UNIT_TEST("SINGLE_WRITE_THEN_READ")
+    `UNIT_TEST("TEST_SINGLE_WRITE_THEN_READ")
 
         @(posedge wclk)
 
@@ -117,9 +130,9 @@ module async_fifo_unit_test;
 
     `UNIT_TEST_END
 
-    `UNIT_TEST("MULTIPLE_WRITE_AND_READ")
+    `UNIT_TEST("TEST_MULTIPLE_WRITE_THEN_READ")
 
-        for (i=0; i<10; i=i+1) begin
+        for (int i=0; i<10; i=i+1) begin
             @(negedge wclk);
             winc = 1;
             wdata = i;
@@ -132,7 +145,7 @@ module async_fifo_unit_test;
         @(posedge rclk);
 
         rinc = 1;
-        for (i=0; i<10; i=i+1) begin
+        for (int i=0; i<10; i=i+1) begin
             @(posedge rclk);
             `FAIL_IF_NOT_EQUAL(rdata, i);
         end
@@ -143,7 +156,7 @@ module async_fifo_unit_test;
 
         winc = 1;
 
-        for (i=0; i<2**ASIZE; i=i+1) begin
+        for (int i=0; i<2**ASIZE; i=i+1) begin
             @(negedge wclk)
             wdata = i;
         end
@@ -160,7 +173,7 @@ module async_fifo_unit_test;
 
         `FAIL_IF_NOT_EQUAL(rempty, 1);
 
-        for (i=0; i<2**ASIZE; i=i+1) begin
+        for (int i=0; i<2**ASIZE; i=i+1) begin
             @(posedge wclk)
             winc = 1;
             wdata = i;
@@ -170,25 +183,12 @@ module async_fifo_unit_test;
 
     `UNIT_TEST_END
 
-    `UNIT_TEST("TEST_SIMPLE_ALMOST_EMPTY_FLAG")
+    `UNIT_TEST("TEST_ALMOST_EMPTY_FLAG")
 
         `FAIL_IF_NOT_EQUAL(arempty, 0);
 
-        @(posedge wclk)
         winc = 1;
-        wdata = i;
-        @(posedge wclk);
-        winc = 0;
-
-        #100;
-        `FAIL_IF_NOT_EQUAL(arempty, 1);
-
-    `UNIT_TEST_END
-
-    `UNIT_TEST("TEST_SIMPLE_ALMOST_FULL_FLAG")
-
-        winc = 1;
-        for (i=0; i<2**ASIZE; i=i+1) begin
+        for (int i=0; i<AREMPTYSIZE; i=i+1) begin
 
             @(negedge wclk)
             wdata = i;
@@ -198,15 +198,15 @@ module async_fifo_unit_test;
         @(negedge wclk);
         winc = 0;
 
-        @(posedge wclk)
-        `FAIL_IF_NOT_EQUAL(wfull, 1);
+        #100;
+        `FAIL_IF_NOT_EQUAL(arempty, 1);
 
     `UNIT_TEST_END
 
-    `UNIT_TEST("TEST_CONSECUTIVE_ALMOST_EMPTY_FULL")
+    `UNIT_TEST("TEST_ALMOST_FULL_FLAG")
 
         winc = 1;
-        for (i=0; i<2**ASIZE; i=i+1) begin
+        for (int i=0; i<2**ASIZE-AWFULLSIZE; i=i+1) begin
 
             @(negedge wclk)
             wdata = i;
@@ -217,9 +217,52 @@ module async_fifo_unit_test;
         winc = 0;
 
         @(posedge wclk)
-        `FAIL_IF_NOT_EQUAL(wfull, 1);
+        `FAIL_IF_NOT_EQUAL(awfull, 1);
 
     `UNIT_TEST_END
+
+    `UNIT_TEST("TEST_CONCURRENT_WRITE_READ")
+
+        fork
+        // Concurrent accesses
+        begin
+            fork
+            // Write source
+            begin
+                winc = 1;
+                for (int i=0; i<MAX_TRAFFIC; i=i+1) begin
+                    while (wfull)
+                        @(negedge wclk);
+                    @(negedge wclk);
+                    wdata = i;
+                end
+                winc = 0;
+            end
+            // Read sink
+            begin
+                for (int i=0; i<MAX_TRAFFIC; i=i+1) begin
+                    while (rempty)
+                        @(posedge rclk);
+                    rinc = 1;
+                    @(negedge rclk);
+                    `FAIL_IF_NOT_EQUAL(rdata, i);
+                end
+                rinc = 0;
+            end
+            join
+        end
+        // Timeout management
+        begin
+            while (timeout<10000) begin
+                timeout = timeout + 1;
+                @(posedge rclk);
+            end
+            `ERROR("Reached timeout!");
+        end
+        join_any
+
+    `UNIT_TEST_END
+
     `TEST_SUITE_END
 
 endmodule
diff --git a/sim/wave.gtkw b/sim/wave.gtkw
index 0ac4dee..1328282 100644
--- a/sim/wave.gtkw
+++ b/sim/wave.gtkw
@@ -1,39 +1,55 @@
 [*]
-[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Fri Sep 11 15:40:43 2020
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Sat Mar 30 09:48:17 2024
 [*]
-[dumpfile] "/Users/damien/workspace/hdl/meduram/deps/async_fifo/sim/test/dump.vcd"
-[dumpfile_mtime] "Fri Sep 11 12:31:34 2020"
-[dumpfile_size] 33471
-[savefile] "/Users/damien/workspace/hdl/meduram/deps/async_fifo/sim/test/wave.gtkw"
-[timestart] 0
-[size] 1280 730
-[pos] 148 -1
-*-17.372753 414900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[dumpfile] "/Users/damien/workspace/hdl/async_fifo/sim/async_fifo_unit_test.vcd"
+[dumpfile_mtime] "Sat Mar 30 09:47:41 2024"
+[dumpfile_size] 35394
+[savefile] "wave.gtkw"
+[timestart] 2131420
+[size] 1440 784
+[pos] -1 -1
+*-13.015144 2119510 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] async_fifo_unit_test.
 [treeopen] async_fifo_unit_test.dut.
-[sst_width] 196
-[signals_width] 332
+[sst_width] 253
+[signals_width] 150
 [sst_expanded] 1
-[sst_vpaned_height] 285
+[sst_vpaned_height] 357
 @200
 -TB
+@420
+async_fifo_unit_test.svut_nb_test
 @28
+[color] 7
 async_fifo_unit_test.dut.wclk
+[color] 7
 async_fifo_unit_test.dut.wrst_n
+[color] 7
 async_fifo_unit_test.dut.winc
 @22
+[color] 7
 async_fifo_unit_test.wdata[31:0]
 @28
+[color] 7
 async_fifo_unit_test.dut.wfull
+[color] 7
 async_fifo_unit_test.dut.awfull
+@29
+[color] 2
 async_fifo_unit_test.dut.rclk
+@28
+[color] 2
 async_fifo_unit_test.dut.rrst_n
+[color] 2
 async_fifo_unit_test.dut.rinc
 @22
+[color] 2
 async_fifo_unit_test.rdata[31:0]
 @28
+[color] 2
 async_fifo_unit_test.dut.rempty
+[color] 2
 async_fifo_unit_test.dut.arempty
 @200
 -DUT
@@ -50,9 +66,7 @@ async_fifo_unit_test.dut.wq2_rptr[4:0]
 @22
 async_fifo_unit_test.dut.fifomem.waddr[3:0]
 async_fifo_unit_test.dut.fifomem.wdata[31:0]
-@23
 async_fifo_unit_test.dut.fifomem.raddr[3:0]
-@22
 async_fifo_unit_test.dut.fifomem.rdata[31:0]
 @200
 -RD PTR EMPTY