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add xcelium support #452

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Feb 26, 2024
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4 changes: 4 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
@@ -158,6 +158,10 @@ vcs-sim:
vcs-ams-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## xcelium simulation
xcelium-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --tool=xcelium $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## Generates the build output for helloworld application
## Uses verilator to simulate the HW model and run the FW
## UART Dumping in uart0.log to show recollected results
11 changes: 11 additions & 0 deletions core-v-mini-mcu.core
Original file line number Diff line number Diff line change
@@ -313,20 +313,26 @@ targets:
- tool_modelsim? (pre_patch_modelsim_Makefile)
- tool_vcs? (cfile_uartdpi)
- tool_vcs? (pre_build_remote_bitbang)
- tool_xcelium? (pre_build_remote_bitbang)
- tool_xcelium? (pre_build_uartdpi)
- tool_verilator? (tb-verilator)
- tool_modelsim? (tb-sv)
- tool_vcs? (tb-sv)
- tool_xcelium? (tb-sv)
- "!integrated_heep? (x_heep_system)"
toplevel:
- tool_modelsim? (tb_top)
- tool_vcs? (tb_top)
- tool_xcelium? (tb_top)
- tool_verilator? (testharness)
hooks:
pre_build:
- tool_modelsim? (pre_build_uartdpi)
- tool_modelsim? (pre_build_remote_bitbang)
- tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
- ams_sim? (pre_patch_vcs_ams_Makefile)
- tool_xcelium? (pre_build_uartdpi)
- tool_xcelium? (pre_build_remote_bitbang)
parameters:
- COREV_PULP
- FPU
@@ -364,6 +370,11 @@ targets:
- -LDFLAGS "-pthread -lutil"
- +lint=TFIPC-L
- -V
xcelium:
xrun_options:
- -vtimescale 1ns/10ps
- -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.so
- -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs.so
verilator:
mode: cc
verilator_options:
4 changes: 2 additions & 2 deletions hw/ip/i2s/rtl/i2s_core.sv
Original file line number Diff line number Diff line change
@@ -7,8 +7,8 @@
// Description: I2s core logic

module i2s_core #(
parameter MaxWordWidth,
parameter ClkDividerWidth
parameter MaxWordWidth = 32,
parameter ClkDividerWidth = 8
) (
input logic clk_i,
input logic rst_ni,
2 changes: 1 addition & 1 deletion hw/ip/i2s/rtl/i2s_ws_gen.sv
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@
// by Antonio Pullini (pullinia@iis.ee.ethz.ch)

module i2s_ws_gen #(
parameter MaxWordWidth,
parameter MaxWordWidth = 32,
localparam int unsigned CounterWidth = $clog2(MaxWordWidth)
) (
input logic sck_i,
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
diff --git a/src/clk_mux_glitch_free.sv b/src/clk_mux_glitch_free.sv
index e0eb5cd..5193742 100644
--- a/src/clk_mux_glitch_free.sv
+++ b/src/clk_mux_glitch_free.sv
@@ -191,7 +191,7 @@ endmodule

// Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
module clk_or_tree #(
- parameter int unsigned NUM_INPUTS
+ parameter int unsigned NUM_INPUTS = 1
) (
input logic [NUM_INPUTS-1:0] clks_i,
output logic clk_o
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v
index 88582b3..55342b5 100644
--- a/picosoc/spiflash.v
+++ b/picosoc/spiflash.v
@@ -109,7 +109,7 @@ module spiflash (

initial begin
for (i=0;i<=16*1024*1024;i=i+1)
- memory[i] = '0;
+ memory[i] = 8'h00;
result = $value$plusargs("firmware=%s", firmware_file);
if (!result)
firmware_file = "firmware.hex";

Original file line number Diff line number Diff line change
@@ -191,7 +191,7 @@ endmodule

// Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
module clk_or_tree #(
parameter int unsigned NUM_INPUTS
parameter int unsigned NUM_INPUTS = 1
) (
input logic [NUM_INPUTS-1:0] clks_i,
output logic clk_o
2 changes: 1 addition & 1 deletion hw/vendor/yosyshq_picorv32/picosoc/spiflash.v
Original file line number Diff line number Diff line change
@@ -109,7 +109,7 @@ module spiflash (

initial begin
for (i=0;i<=16*1024*1024;i=i+1)
memory[i] = '0;
memory[i] = 8'h00;
result = $value$plusargs("firmware=%s", firmware_file);
if (!result)
firmware_file = "firmware.hex";
2 changes: 1 addition & 1 deletion tb/tb_util.svh.tpl
Original file line number Diff line number Diff line change
@@ -96,7 +96,7 @@ endtask

% for bank in range(ram_numbanks):
task tb_writetoSram${bank};
input integer addr;
input int addr;
input [7:0] val3;
input [7:0] val2;
input [7:0] val1;
4 changes: 4 additions & 0 deletions x-heep-tb-utils.core
Original file line number Diff line number Diff line change
@@ -79,13 +79,17 @@ targets:
- tool_verilator? (uartdpi)
- tool_modelsim? (systemverilog_only_uart)
- tool_vcs? (systemverilog_only_uart)
- tool_xcelium? (systemverilog_only_uart)
- tool_verilator? (files_verilator_waiver)
- tool_verilator? (remote_bitbang_dpi)
- tool_modelsim? (systemverilog_only_simjtag)
- tool_vcs? (systemverilog_only_simjtag)
- tool_xcelium? (systemverilog_only_simjtag)
- tool_modelsim? (cypress_flash)
- tool_vcs? (cypress_flash)
- tool_xcelium? (cypress_flash)
toplevel:
- tool_modelsim? (tb_top)
- tool_vcs? (tb_top)
- tool_xcelium? (tb_top)
- tool_verilator? (testharness)