adc_cal: riscv: Add changelog entry for ADC calibration

esp-rs · Jun 7, 2023 · 062884e · 062884e
1 parent 1484b71
commit 062884e
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -37,6 +37,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fix Async GPIO not disabling interupts on chips with multiple banks (#572)
 - Add unified field-based efuse access
 - Add `timer_interrupt` example in ESP32-H2 and refactor `clk_src` configuration (#576)
+- Add ADC calibration implementation for a riscv chips (#555)
 
 ### Changed
 

diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs
@@ -17,14 +17,14 @@ use crate::{
 
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 mod cal_basic;
-#[cfg(esp32c3)]
+#[cfg(any(esp32c3, esp32c6))]
 mod cal_curve;
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 mod cal_line;
 
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 pub use cal_basic::AdcCalBasic;
-#[cfg(esp32c3)]
+#[cfg(any(esp32c3, esp32c6))]
 pub use cal_curve::{AdcCalCurve, AdcHasCurveCal};
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 pub use cal_line::{AdcCalLine, AdcHasLineCal};
@@ -540,6 +540,7 @@ where
     }
 }
 
+#[cfg(any(esp32c2, esp32c3, esp32c6))]
 impl AdcCalEfuse for ADC1 {
     fn get_init_code(atten: Attenuation) -> Option<u16> {
         Efuse::get_rtc_calib_init_code(1, atten)