From 062884e301d3ad79718977416cfd8d3a99050e4a Mon Sep 17 00:00:00 2001
From: K <kayo@illumium.org>
Date: Fri, 2 Jun 2023 11:14:01 +0500
Subject: [PATCH] adc_cal: riscv: Add changelog entry for ADC calibration

---
 CHANGELOG.md                           | 1 +
 esp-hal-common/src/analog/adc/riscv.rs | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index a06e88be42f..4142202926a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -37,6 +37,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fix Async GPIO not disabling interupts on chips with multiple banks (#572)
 - Add unified field-based efuse access
 - Add `timer_interrupt` example in ESP32-H2 and refactor `clk_src` configuration (#576)
+- Add ADC calibration implementation for a riscv chips (#555)
 
 ### Changed
 
diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs
index 2fb9904aa3a..07f0e5275b8 100644
--- a/esp-hal-common/src/analog/adc/riscv.rs
+++ b/esp-hal-common/src/analog/adc/riscv.rs
@@ -17,14 +17,14 @@ use crate::{
 
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 mod cal_basic;
-#[cfg(esp32c3)]
+#[cfg(any(esp32c3, esp32c6))]
 mod cal_curve;
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 mod cal_line;
 
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 pub use cal_basic::AdcCalBasic;
-#[cfg(esp32c3)]
+#[cfg(any(esp32c3, esp32c6))]
 pub use cal_curve::{AdcCalCurve, AdcHasCurveCal};
 #[cfg(any(esp32c2, esp32c3, esp32c6))]
 pub use cal_line::{AdcCalLine, AdcHasLineCal};
@@ -540,6 +540,7 @@ where
     }
 }
 
+#[cfg(any(esp32c2, esp32c3, esp32c6))]
 impl AdcCalEfuse for ADC1 {
     fn get_init_code(atten: Attenuation) -> Option<u16> {
         Efuse::get_rtc_calib_init_code(1, atten)