From 4c0900b4f7d5a46e8eae0de3773bcf2ab061d508 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 14:55:37 +0200 Subject: [PATCH 1/9] Re-enable delay tests on S2 and C2 --- hil-test/tests/delay.rs | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/hil-test/tests/delay.rs b/hil-test/tests/delay.rs index b00c1c130d6..dfc835e17a6 100644 --- a/hil-test/tests/delay.rs +++ b/hil-test/tests/delay.rs @@ -1,7 +1,6 @@ //! Delay Test -// esp32c2 is disabled currently as it fails -//% CHIPS: esp32 esp32c3 esp32c6 esp32s3 +//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32s2 esp32s3 #![no_std] #![no_main] @@ -44,7 +43,11 @@ mod tests { let t2 = esp_hal::time::current_time(); assert!(t2 > t1); - assert!((t2 - t1).to_nanos() >= 600_000_000u64); + assert!( + (t2 - t1).to_nanos() >= 600_000_000u64, + "diff: {:?}", + (t2 - t1).to_nanos() + ); } #[test] @@ -55,7 +58,11 @@ mod tests { let t2 = esp_hal::time::current_time(); assert!(t2 > t1); - assert!((t2 - t1).to_millis() >= 700u64); + assert!( + (t2 - t1).to_millis() >= 700u64, + "diff: {:?}", + (t2 - t1).to_millis() + ); } #[test] @@ -66,7 +73,11 @@ mod tests { let t2 = esp_hal::time::current_time(); assert!(t2 > t1); - assert!((t2 - t1).to_micros() >= 1_500_000u64); + assert!( + (t2 - t1).to_micros() >= 1_500_000u64, + "diff: {:?}", + (t2 - t1).to_micros() + ); } #[test] @@ -77,6 +88,10 @@ mod tests { let t2 = esp_hal::time::current_time(); assert!(t2 > t1); - assert!((t2 - t1).to_millis() >= 3000u64); + assert!( + (t2 - t1).to_millis() >= 3000u64, + "diff: {:?}", + (t2 - t1).to_millis() + ); } } From 46c8f54b1b28aca233245ef2b4b10a9a0f7a7a9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 16:59:51 +0200 Subject: [PATCH 2/9] Systimer: use fn instead of constant to retrieve tick freq --- esp-hal/src/time.rs | 2 +- esp-hal/src/timer/systimer.rs | 20 +++++++++++++------- examples/src/bin/systimer.rs | 4 ++-- hil-test/tests/systimer.rs | 4 ++-- 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/esp-hal/src/time.rs b/esp-hal/src/time.rs index ba05a694ec1..24fe8aff314 100644 --- a/esp-hal/src/time.rs +++ b/esp-hal/src/time.rs @@ -50,7 +50,7 @@ pub fn current_time() -> fugit::Instant { let ticks = crate::timer::systimer::SystemTimer::now(); ( ticks, - (crate::timer::systimer::SystemTimer::TICKS_PER_SECOND / 1_000_000), + (crate::timer::systimer::SystemTimer::ticks_per_second() / 1_000_000), ) }; diff --git a/esp-hal/src/timer/systimer.rs b/esp-hal/src/timer/systimer.rs index 60745c4118b..daf7e19a29a 100644 --- a/esp-hal/src/timer/systimer.rs +++ b/esp-hal/src/timer/systimer.rs @@ -112,17 +112,23 @@ impl<'d> SystemTimer<'d> { if #[cfg(esp32s2)] { /// Bitmask to be applied to the raw register value. pub const BIT_MASK: u64 = u64::MAX; - /// The ticks per second the underlying peripheral uses. - pub const TICKS_PER_SECOND: u64 = 80_000_000; // Bitmask to be applied to the raw period register value. const PERIOD_MASK: u64 = 0x1FFF_FFFF; + + /// Returns the tick frequency of the underlying timer unit. + pub fn ticks_per_second() -> u64 { + 80_000_000 + } } else { /// Bitmask to be applied to the raw register value. pub const BIT_MASK: u64 = 0xF_FFFF_FFFF_FFFF; - /// The ticks per second the underlying peripheral uses. - pub const TICKS_PER_SECOND: u64 = 16_000_000; // Bitmask to be applied to the raw period register value. const PERIOD_MASK: u64 = 0x3FF_FFFF; + + /// Returns the tick frequency of the underlying timer unit. + pub fn ticks_per_second() -> u64 { + 16_000_000 + } } } @@ -810,7 +816,7 @@ where } let us = period.ticks(); - let ticks = us * (SystemTimer::TICKS_PER_SECOND / 1_000_000) as u32; + let ticks = us * (SystemTimer::ticks_per_second() / 1_000_000) as u32; self.comparator.set_mode(ComparatorMode::Period); self.comparator.set_period(ticks); @@ -879,7 +885,7 @@ where } }; - let us = ticks / (SystemTimer::TICKS_PER_SECOND / 1_000_000); + let us = ticks / (SystemTimer::ticks_per_second() / 1_000_000); Instant::::from_ticks(us) } @@ -888,7 +894,7 @@ where let mode = self.comparator.get_mode(); let us = value.ticks(); - let ticks = us * (SystemTimer::TICKS_PER_SECOND / 1_000_000); + let ticks = us * (SystemTimer::ticks_per_second() / 1_000_000); if matches!(mode, ComparatorMode::Period) { // Period mode diff --git a/examples/src/bin/systimer.rs b/examples/src/bin/systimer.rs index 15e479d8d32..cdbf345a96b 100644 --- a/examples/src/bin/systimer.rs +++ b/examples/src/bin/systimer.rs @@ -74,11 +74,11 @@ fn main() -> ! { alarm0.enable_interrupt(true); alarm1.set_interrupt_handler(systimer_target1); - alarm1.set_target(SystemTimer::now() + (SystemTimer::TICKS_PER_SECOND * 2)); + alarm1.set_target(SystemTimer::now() + (SystemTimer::ticks_per_second() * 2)); alarm1.enable_interrupt(true); alarm2.set_interrupt_handler(systimer_target2); - alarm2.set_target(SystemTimer::now() + (SystemTimer::TICKS_PER_SECOND * 3)); + alarm2.set_target(SystemTimer::now() + (SystemTimer::ticks_per_second() * 3)); alarm2.enable_interrupt(true); ALARM0.borrow_ref_mut(cs).replace(alarm0); diff --git a/hil-test/tests/systimer.rs b/hil-test/tests/systimer.rs index 9e3fe53dc94..e8360539d85 100644 --- a/hil-test/tests/systimer.rs +++ b/hil-test/tests/systimer.rs @@ -137,7 +137,7 @@ mod tests { critical_section::with(|cs| { alarm0.set_interrupt_handler(pass_test_if_called); - alarm0.set_target(SystemTimer::now() + SystemTimer::TICKS_PER_SECOND / 10); + alarm0.set_target(SystemTimer::now() + SystemTimer::ticks_per_second() / 10); alarm0.enable_interrupt(true); ALARM_TARGET.borrow_ref_mut(cs).replace(alarm0); @@ -157,7 +157,7 @@ mod tests { critical_section::with(|cs| { alarm0.set_interrupt_handler(target_fail_test_if_called_twice); - alarm0.set_target(SystemTimer::now() + SystemTimer::TICKS_PER_SECOND / 10); + alarm0.set_target(SystemTimer::now() + SystemTimer::ticks_per_second() / 10); alarm0.enable_interrupt(true); let alarm1 = alarm1.into_periodic(); From 7c40826d4d3ede09b19fc4c698369ffb96509241 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 17:07:04 +0200 Subject: [PATCH 3/9] Reformulate delay using current_time --- esp-hal/src/delay.rs | 107 +++++++++++++------------------------------ 1 file changed, 33 insertions(+), 74 deletions(-) diff --git a/esp-hal/src/delay.rs b/esp-hal/src/delay.rs index 2febb2202e3..f1d07ba6578 100644 --- a/esp-hal/src/delay.rs +++ b/esp-hal/src/delay.rs @@ -30,17 +30,16 @@ //! [DelayUs]: embedded_hal_02::blocking::delay::DelayUs //! [embedded-hal]: https://docs.rs/embedded-hal/1.0.0/embedded_hal/delay/index.html -use fugit::HertzU64; pub use fugit::MicrosDurationU64; +use crate::clock::Clocks; + /// Delay driver /// /// Uses the `SYSTIMER` peripheral internally for RISC-V devices, and the /// built-in Xtensa timer for Xtensa devices. #[derive(Clone, Copy)] -pub struct Delay { - freq: HertzU64, -} +pub struct Delay; impl Delay { /// Delay for the specified number of milliseconds @@ -80,83 +79,43 @@ impl embedded_hal::delay::DelayNs for Delay { } } -#[cfg(riscv)] -mod implementation { - use super::*; - use crate::{clock::Clocks, timer::systimer::SystemTimer}; - - impl Delay { - /// Create a new `Delay` instance - pub fn new(clocks: &Clocks<'_>) -> Self { - // The counters and comparators are driven using `XTAL_CLK`. - // The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz. - // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle. - Self { - #[cfg(not(esp32h2))] - freq: HertzU64::MHz(clocks.xtal_clock.to_MHz() as u64 * 10 / 25), - #[cfg(esp32h2)] - // esp32h2 TRM, section 11.2 Clock Source Selection - freq: HertzU64::MHz(clocks.xtal_clock.to_MHz() as u64 * 10 / 20), - } - } - - /// Delay for the specified time - pub fn delay(&self, time: MicrosDurationU64) { - let t0 = SystemTimer::now(); - let rate: HertzU64 = MicrosDurationU64::from_ticks(1).into_rate(); - let clocks = time.ticks() * (self.freq / rate); - - while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {} - } +impl Delay { + /// Creates a new `Delay` instance. + pub fn new(_clocks: &Clocks<'_>) -> Self { + // The counters and comparators are driven using `XTAL_CLK`. + // The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz. + // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle. + Self {} + } - /// Delay for the specified number of microseconds - pub fn delay_micros(&self, us: u32) { - let t0 = SystemTimer::now(); - let clocks = us as u64 * (self.freq / HertzU64::MHz(1)); + /// Delay for the specified time + pub fn delay(&self, delay: MicrosDurationU64) { + let start = crate::time::current_time(); - while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {} - } + while elapsed_since(start) < delay {} + } - /// Delay for the specified number of nanoseconds - pub fn delay_nanos(&self, ns: u32) { - let t0 = SystemTimer::now(); - let clocks = ns as u64 * (self.freq / HertzU64::MHz(1)) / 1000; + /// Delay for the specified number of microseconds + pub fn delay_micros(&self, us: u32) { + let delay = MicrosDurationU64::micros(us as u64); + self.delay(delay); + } - while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {} - } + /// Delay for the specified number of nanoseconds + pub fn delay_nanos(&self, ns: u32) { + let delay = MicrosDurationU64::nanos(ns as u64); + self.delay(delay); } } -#[cfg(xtensa)] -mod implementation { - use super::*; - use crate::clock::Clocks; - - impl Delay { - /// Create a new `Delay` instance - pub fn new(clocks: &Clocks<'_>) -> Self { - Self { - freq: clocks.cpu_clock.into(), - } - } - - /// Delay for the specified time - pub fn delay(&self, time: MicrosDurationU64) { - let rate: HertzU64 = MicrosDurationU64::from_ticks(1).into_rate(); - let clocks = time.ticks() * (self.freq / rate); - xtensa_lx::timer::delay(clocks as u32); - } +fn elapsed_since(start: fugit::Instant) -> MicrosDurationU64 { + let now = crate::time::current_time(); - /// Delay for the specified number of microseconds - pub fn delay_micros(&self, us: u32) { - let clocks = us as u64 * (self.freq / HertzU64::MHz(1)); - xtensa_lx::timer::delay(clocks as u32); - } - - /// Delay for the specified number of nanoseconds - pub fn delay_nanos(&self, ns: u32) { - let clocks = ns as u64 * (self.freq / HertzU64::MHz(1)) / 1000; - xtensa_lx::timer::delay(clocks as u32); - } + if start.ticks() <= now.ticks() { + now - start + } else { + // current_time specifies at least 7 happy years, let's ignore this issue for + // now. + panic!("Time has wrapped around, which we currently don't handle"); } } From 7e5b55d9894765a5b19dc88ec5ce3b3565c81787 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 17:56:22 +0200 Subject: [PATCH 4/9] Take actual XTAL into account --- esp-hal/CHANGELOG.md | 1 + esp-hal/src/clock/mod.rs | 24 ++++++++++++++++++++++++ esp-hal/src/delay.rs | 27 +++++++++++---------------- esp-hal/src/timer/systimer.rs | 27 +++++++++++++++++++-------- hil-test/tests/delay.rs | 5 +++-- 5 files changed, 58 insertions(+), 26 deletions(-) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index 1faae3aef65..8f9a05689a9 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -287,6 +287,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Auto detect crystal frequency based on `RtcClock::estimate_xtal_frequency()` (#1165) - ESP32-S3: Configure 32k ICACHE (#1169) - Lift the minimal buffer size requirement for I2S (#1189) +- Replaced `SystemTimer::TICKS_PER_SEC` with `SystemTimer::ticks_per_sec()` (#?) ### Removed diff --git a/esp-hal/src/clock/mod.rs b/esp-hal/src/clock/mod.rs index eec20041cb1..902a96b4ce3 100644 --- a/esp-hal/src/clock/mod.rs +++ b/esp-hal/src/clock/mod.rs @@ -71,6 +71,8 @@ //! ``` use fugit::HertzU32; +#[cfg(any(esp32, esp32c2))] +use portable_atomic::{AtomicU32, Ordering}; #[cfg(any(esp32, esp32c2))] use crate::rtc_cntl::RtcClock; @@ -333,6 +335,24 @@ pub struct RawClocks { pub pll_96m_clock: HertzU32, } +cfg_if::cfg_if! { + if #[cfg(any(esp32, esp32c2))] { + static XTAL_FREQ_MHZ: AtomicU32 = AtomicU32::new(40); + + pub(crate) fn xtal_freq_mhz() -> u32 { + XTAL_FREQ_MHZ.load(Ordering::Relaxed) + } + } else if #[cfg(esp32h2)] { + pub(crate) fn xtal_freq_mhz() -> u32 { + 32 + } + } else if #[cfg(not(esp32s2))]{ + pub(crate) fn xtal_freq_mhz() -> u32 { + 40 + } + } +} + /// Used to configure the frequencies of the clocks present in the chip. /// /// After setting all frequencies, call the freeze function to apply the @@ -362,6 +382,7 @@ impl<'d> ClockControl<'d> { } else { 26 }; + XTAL_FREQ_MHZ.store(xtal_freq, Ordering::Relaxed); ClockControl { _private: clock_control.into_ref(), @@ -385,6 +406,7 @@ impl<'d> ClockControl<'d> { } else { XtalClock::RtcXtalFreq26M }; + XTAL_FREQ_MHZ.store(xtal_freq.mhz(), Ordering::Relaxed); let pll_freq = match cpu_clock_speed { CpuClock::Clock80MHz => PllClock::Pll320MHz, @@ -429,6 +451,7 @@ impl<'d> ClockControl<'d> { } else { 26 }; + XTAL_FREQ_MHZ.store(xtal_freq, Ordering::Relaxed); ClockControl { _private: clock_control.into_ref(), @@ -452,6 +475,7 @@ impl<'d> ClockControl<'d> { } else { XtalClock::RtcXtalFreq26M }; + XTAL_FREQ_MHZ.store(xtal_freq.mhz(), Ordering::Relaxed); let pll_freq = PllClock::Pll480MHz; diff --git a/esp-hal/src/delay.rs b/esp-hal/src/delay.rs index f1d07ba6578..f0dec8ecb08 100644 --- a/esp-hal/src/delay.rs +++ b/esp-hal/src/delay.rs @@ -39,16 +39,8 @@ use crate::clock::Clocks; /// Uses the `SYSTIMER` peripheral internally for RISC-V devices, and the /// built-in Xtensa timer for Xtensa devices. #[derive(Clone, Copy)] -pub struct Delay; - -impl Delay { - /// Delay for the specified number of milliseconds - pub fn delay_millis(&self, ms: u32) { - for _ in 0..ms { - self.delay_micros(1000); - } - } -} +#[non_exhaustive] +pub struct Delay {} #[cfg(feature = "embedded-hal-02")] impl embedded_hal_02::blocking::delay::DelayMs for Delay @@ -56,9 +48,7 @@ where T: Into, { fn delay_ms(&mut self, ms: T) { - for _ in 0..ms.into() { - self.delay_micros(1000); - } + self.delay_millis(ms.into()); } } @@ -81,10 +71,8 @@ impl embedded_hal::delay::DelayNs for Delay { impl Delay { /// Creates a new `Delay` instance. + // Do not remove the argument, it makes sure that the clocks are initialized. pub fn new(_clocks: &Clocks<'_>) -> Self { - // The counters and comparators are driven using `XTAL_CLK`. - // The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz. - // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle. Self {} } @@ -95,6 +83,13 @@ impl Delay { while elapsed_since(start) < delay {} } + /// Delay for the specified number of milliseconds + pub fn delay_millis(&self, ms: u32) { + for _ in 0..ms { + self.delay_micros(1000); + } + } + /// Delay for the specified number of microseconds pub fn delay_micros(&self, us: u32) { let delay = MicrosDurationU64::micros(us as u64); diff --git a/esp-hal/src/timer/systimer.rs b/esp-hal/src/timer/systimer.rs index daf7e19a29a..ed7969e1a86 100644 --- a/esp-hal/src/timer/systimer.rs +++ b/esp-hal/src/timer/systimer.rs @@ -114,20 +114,31 @@ impl<'d> SystemTimer<'d> { pub const BIT_MASK: u64 = u64::MAX; // Bitmask to be applied to the raw period register value. const PERIOD_MASK: u64 = 0x1FFF_FFFF; - - /// Returns the tick frequency of the underlying timer unit. - pub fn ticks_per_second() -> u64 { - 80_000_000 - } } else { /// Bitmask to be applied to the raw register value. pub const BIT_MASK: u64 = 0xF_FFFF_FFFF_FFFF; // Bitmask to be applied to the raw period register value. const PERIOD_MASK: u64 = 0x3FF_FFFF; + } + } - /// Returns the tick frequency of the underlying timer unit. - pub fn ticks_per_second() -> u64 { - 16_000_000 + /// Returns the tick frequency of the underlying timer unit. + pub fn ticks_per_second() -> u64 { + cfg_if::cfg_if! { + if #[cfg(esp32s2)] { + 80_000_000 + } else if #[cfg(esp32h2)] { + // The counters and comparators are driven using `XTAL_CLK`. + // The average clock frequency is fXTAL_CLK/2, which is 16 MHz. + // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle. + const MULTIPLIER: u64 = 10_000_000 / 20; + crate::clock::xtal_freq_mhz() as u64 * MULTIPLIER + } else { + // The counters and comparators are driven using `XTAL_CLK`. + // The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz. + // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle. + const MULTIPLIER: u64 = 10_000_000 / 25; + crate::clock::xtal_freq_mhz() as u64 * MULTIPLIER } } } diff --git a/hil-test/tests/delay.rs b/hil-test/tests/delay.rs index dfc835e17a6..159a7da6841 100644 --- a/hil-test/tests/delay.rs +++ b/hil-test/tests/delay.rs @@ -1,6 +1,7 @@ //! Delay Test //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32s2 esp32s3 +//% FEATURES: defmt #![no_std] #![no_main] @@ -36,7 +37,7 @@ mod tests { } #[test] - #[timeout(1)] + #[timeout(2)] fn delay_ns(mut ctx: Context) { let t1 = esp_hal::time::current_time(); ctx.delay.delay_ns(600_000_000); @@ -51,7 +52,7 @@ mod tests { } #[test] - #[timeout(1)] + #[timeout(2)] fn delay_700millis(ctx: Context) { let t1 = esp_hal::time::current_time(); ctx.delay.delay_millis(700); From 9f4e20bcd11bc6cf4eb51a2e361fbfa6b8e9ce3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 18:05:57 +0200 Subject: [PATCH 5/9] Re-enable tests --- hil-test/tests/embassy_timers_executors.rs | 3 +-- hil-test/tests/get_time.rs | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/hil-test/tests/embassy_timers_executors.rs b/hil-test/tests/embassy_timers_executors.rs index 92d0a8a3871..966a41d6461 100644 --- a/hil-test/tests/embassy_timers_executors.rs +++ b/hil-test/tests/embassy_timers_executors.rs @@ -1,7 +1,6 @@ //! Embassy timer and executor Test -// esp32c2 is disabled currently as it fails -//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s3 +//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 #![no_std] #![no_main] diff --git a/hil-test/tests/get_time.rs b/hil-test/tests/get_time.rs index c3cdfeee902..72b065ced05 100644 --- a/hil-test/tests/get_time.rs +++ b/hil-test/tests/get_time.rs @@ -1,7 +1,6 @@ //! current_time Test -// esp32c2 is disabled currently as it fails -//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 +//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 #![no_std] #![no_main] From 2bca74189d11a832c79d5151052c33ae6f26cdf4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 18:08:29 +0200 Subject: [PATCH 6/9] Fix changelog --- esp-hal/CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index 8f9a05689a9..61c074ebf64 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -287,7 +287,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Auto detect crystal frequency based on `RtcClock::estimate_xtal_frequency()` (#1165) - ESP32-S3: Configure 32k ICACHE (#1169) - Lift the minimal buffer size requirement for I2S (#1189) -- Replaced `SystemTimer::TICKS_PER_SEC` with `SystemTimer::ticks_per_sec()` (#?) +- Replaced `SystemTimer::TICKS_PER_SEC` with `SystemTimer::ticks_per_sec()` (#1981) ### Removed From 7b6932ced6f96fd9d8b24fae8ca312d5b3fa4e4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 18:09:21 +0200 Subject: [PATCH 7/9] Disable defmt --- hil-test/tests/delay.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/hil-test/tests/delay.rs b/hil-test/tests/delay.rs index 159a7da6841..96e7adcfb32 100644 --- a/hil-test/tests/delay.rs +++ b/hil-test/tests/delay.rs @@ -1,7 +1,6 @@ //! Delay Test //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32s2 esp32s3 -//% FEATURES: defmt #![no_std] #![no_main] From df6900ac7e313fe1d48c2b3c4beaac28a2c49520 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 18:21:07 +0200 Subject: [PATCH 8/9] Remove unused esp32 code --- esp-hal/src/clock/mod.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/esp-hal/src/clock/mod.rs b/esp-hal/src/clock/mod.rs index 902a96b4ce3..67b68dfebc9 100644 --- a/esp-hal/src/clock/mod.rs +++ b/esp-hal/src/clock/mod.rs @@ -71,7 +71,7 @@ //! ``` use fugit::HertzU32; -#[cfg(any(esp32, esp32c2))] +#[cfg(esp32c2)] use portable_atomic::{AtomicU32, Ordering}; #[cfg(any(esp32, esp32c2))] @@ -336,7 +336,7 @@ pub struct RawClocks { } cfg_if::cfg_if! { - if #[cfg(any(esp32, esp32c2))] { + if #[cfg(esp32c2)] { static XTAL_FREQ_MHZ: AtomicU32 = AtomicU32::new(40); pub(crate) fn xtal_freq_mhz() -> u32 { @@ -346,7 +346,9 @@ cfg_if::cfg_if! { pub(crate) fn xtal_freq_mhz() -> u32 { 32 } - } else if #[cfg(not(esp32s2))]{ + } else if #[cfg(any(esp32, esp32s2))] { + // Function would be unused + } else { pub(crate) fn xtal_freq_mhz() -> u32 { 40 } @@ -382,7 +384,6 @@ impl<'d> ClockControl<'d> { } else { 26 }; - XTAL_FREQ_MHZ.store(xtal_freq, Ordering::Relaxed); ClockControl { _private: clock_control.into_ref(), @@ -406,7 +407,6 @@ impl<'d> ClockControl<'d> { } else { XtalClock::RtcXtalFreq26M }; - XTAL_FREQ_MHZ.store(xtal_freq.mhz(), Ordering::Relaxed); let pll_freq = match cpu_clock_speed { CpuClock::Clock80MHz => PllClock::Pll320MHz, From d02ad969e84e658cf62ffab0359c45af9cf5ce8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 21 Aug 2024 18:30:29 +0200 Subject: [PATCH 9/9] Update esp-hal/src/delay.rs Co-authored-by: Jesse Braham --- esp-hal/src/delay.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp-hal/src/delay.rs b/esp-hal/src/delay.rs index f0dec8ecb08..842d7bcbf28 100644 --- a/esp-hal/src/delay.rs +++ b/esp-hal/src/delay.rs @@ -40,7 +40,7 @@ use crate::clock::Clocks; /// built-in Xtensa timer for Xtensa devices. #[derive(Clone, Copy)] #[non_exhaustive] -pub struct Delay {} +pub struct Delay; #[cfg(feature = "embedded-hal-02")] impl embedded_hal_02::blocking::delay::DelayMs for Delay