From 7f899b1f8f66cb37255977017464446899d49508 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Mon, 5 Feb 2024 10:43:41 -0800 Subject: [PATCH 1/2] Remove `esp8266` package --- esp8266/.cargo/config.toml | 5 - esp8266/Cargo.toml | 38 - esp8266/README.md | 30 - esp8266/build.rs | 17 - esp8266/device.x | 1 - esp8266/rust-toolchain.toml | 2 - esp8266/src/dport.rs | 71 - esp8266/src/dport/dport_ctl.rs | 66 - esp8266/src/dport/edge_int_enable.rs | 101 - esp8266/src/dport/ioswap.rs | 159 - esp8266/src/dport/spi_cache.rs | 165 - esp8266/src/dport/spi_cache_target.rs | 79 - esp8266/src/dport/spi_interrupt_type.rs | 52 - esp8266/src/efuse.rs | 47 - esp8266/src/efuse/efuse_data0.rs | 63 - esp8266/src/efuse/efuse_data1.rs | 63 - esp8266/src/efuse/efuse_data2.rs | 63 - esp8266/src/efuse/efuse_data3.rs | 63 - esp8266/src/generic.rs | 522 -- esp8266/src/generic/raw.rs | 93 - esp8266/src/gpio.rs | 297 - esp8266/src/gpio/gpio_enable.rs | 85 - esp8266/src/gpio/gpio_enable_w1tc.rs | 42 - esp8266/src/gpio/gpio_enable_w1ts.rs | 42 - esp8266/src/gpio/gpio_in.rs | 85 - esp8266/src/gpio/gpio_out.rs | 85 - esp8266/src/gpio/gpio_out_w1tc.rs | 42 - esp8266/src/gpio/gpio_out_w1ts.rs | 42 - esp8266/src/gpio/gpio_pin0.rs | 328 - esp8266/src/gpio/gpio_pin1.rs | 328 - esp8266/src/gpio/gpio_pin10.rs | 328 - esp8266/src/gpio/gpio_pin11.rs | 328 - esp8266/src/gpio/gpio_pin12.rs | 328 - esp8266/src/gpio/gpio_pin13.rs | 328 - esp8266/src/gpio/gpio_pin14.rs | 328 - esp8266/src/gpio/gpio_pin15.rs | 328 - esp8266/src/gpio/gpio_pin2.rs | 328 - esp8266/src/gpio/gpio_pin3.rs | 328 - esp8266/src/gpio/gpio_pin4.rs | 328 - esp8266/src/gpio/gpio_pin5.rs | 328 - esp8266/src/gpio/gpio_pin6.rs | 328 - esp8266/src/gpio/gpio_pin7.rs | 328 - esp8266/src/gpio/gpio_pin8.rs | 328 - esp8266/src/gpio/gpio_pin9.rs | 328 - esp8266/src/gpio/gpio_rtc_calib_sync.rs | 85 - esp8266/src/gpio/gpio_rtc_calib_value.rs | 104 - esp8266/src/gpio/gpio_sigma_delta.rs | 104 - esp8266/src/gpio/gpio_status.rs | 66 - esp8266/src/gpio/gpio_status_w1tc.rs | 44 - esp8266/src/gpio/gpio_status_w1ts.rs | 44 - esp8266/src/i2s.rs | 117 - esp8266/src/i2s/i2s_fifo_conf.rs | 142 - esp8266/src/i2s/i2sconf.rs | 332 - esp8266/src/i2s/i2sconf_sigle_data.rs | 66 - esp8266/src/i2s/i2sint_clr.rs | 161 - esp8266/src/i2s/i2sint_ena.rs | 165 - esp8266/src/i2s/i2sint_raw.rs | 165 - esp8266/src/i2s/i2sint_st.rs | 161 - esp8266/src/i2s/i2srxeof_num.rs | 66 - esp8266/src/i2s/i2srxfifo.rs | 63 - esp8266/src/i2s/i2stiming.rs | 294 - esp8266/src/i2s/i2stxfifo.rs | 63 - esp8266/src/io_mux.rs | 177 - esp8266/src/io_mux/io_mux_conf.rs | 85 - esp8266/src/io_mux/io_mux_gpio0.rs | 155 - esp8266/src/io_mux/io_mux_gpio2.rs | 155 - esp8266/src/io_mux/io_mux_gpio4.rs | 155 - esp8266/src/io_mux/io_mux_gpio5.rs | 155 - esp8266/src/io_mux/io_mux_mtck.rs | 155 - esp8266/src/io_mux/io_mux_mtdi.rs | 155 - esp8266/src/io_mux/io_mux_mtdo.rs | 155 - esp8266/src/io_mux/io_mux_mtms.rs | 155 - esp8266/src/io_mux/io_mux_sd_clk.rs | 155 - esp8266/src/io_mux/io_mux_sd_cmd.rs | 155 - esp8266/src/io_mux/io_mux_sd_data0.rs | 155 - esp8266/src/io_mux/io_mux_sd_data1.rs | 155 - esp8266/src/io_mux/io_mux_sd_data2.rs | 155 - esp8266/src/io_mux/io_mux_sd_data3.rs | 155 - esp8266/src/io_mux/io_mux_u0rxd.rs | 155 - esp8266/src/io_mux/io_mux_u0txd.rs | 155 - esp8266/src/lib.rs | 840 --- esp8266/src/rng.rs | 17 - esp8266/src/rng/rng.rs | 25 - esp8266/src/rtc.rs | 83 - esp8266/src/rtc/pad_xpd_dcdc_conf.rs | 44 - esp8266/src/rtc/rtc_gpio_conf.rs | 44 - esp8266/src/rtc/rtc_gpio_enable.rs | 44 - esp8266/src/rtc/rtc_gpio_in_data.rs | 44 - esp8266/src/rtc/rtc_gpio_out.rs | 44 - esp8266/src/rtc/rtc_state1.rs | 63 - esp8266/src/rtc/rtc_store0.rs | 63 - esp8266/src/rtccntl.rs | 18 - esp8266/src/rtccntl/pll.rs | 127 - esp8266/src/slc.rs | 328 - esp8266/src/slc/slc_ahb_test.rs | 85 - esp8266/src/slc/slc_bridge_conf.rs | 123 - esp8266/src/slc/slc_conf0.rs | 253 - esp8266/src/slc/slc_conf1.rs | 63 - esp8266/src/slc/slc_date.rs | 63 - esp8266/src/slc/slc_id.rs | 63 - esp8266/src/slc/slc_int_clr.rs | 465 -- esp8266/src/slc/slc_int_ena.rs | 465 -- esp8266/src/slc/slc_int_raw.rs | 465 -- esp8266/src/slc/slc_int_status.rs | 465 -- esp8266/src/slc/slc_intvec_tohost.rs | 66 - esp8266/src/slc/slc_rx_dscr_conf.rs | 85 - esp8266/src/slc/slc_rx_eof_bfr_des_addr.rs | 63 - esp8266/src/slc/slc_rx_eof_des_addr.rs | 63 - esp8266/src/slc/slc_rx_fifo_push.rs | 85 - esp8266/src/slc/slc_rx_link.rs | 142 - esp8266/src/slc/slc_rx_status.rs | 82 - esp8266/src/slc/slc_rxlink_dscr.rs | 63 - esp8266/src/slc/slc_rxlink_dscr_bf0.rs | 63 - esp8266/src/slc/slc_rxlink_dscr_bf1.rs | 63 - esp8266/src/slc/slc_sdio_st.rs | 117 - esp8266/src/slc/slc_state0.rs | 63 - esp8266/src/slc/slc_state1.rs | 63 - esp8266/src/slc/slc_token0.rs | 139 - esp8266/src/slc/slc_token1.rs | 139 - esp8266/src/slc/slc_tx_eof_des_addr.rs | 63 - esp8266/src/slc/slc_tx_fifo_pop.rs | 85 - esp8266/src/slc/slc_tx_link.rs | 142 - esp8266/src/slc/slc_tx_status.rs | 82 - esp8266/src/slc/slc_txlink_dscr.rs | 63 - esp8266/src/slc/slc_txlink_dscr_bf0.rs | 63 - esp8266/src/slc/slc_txlink_dscr_bf1.rs | 63 - esp8266/src/spi0.rs | 368 -- esp8266/src/spi0/spi_addr.rs | 98 - esp8266/src/spi0/spi_clock.rs | 142 - esp8266/src/spi0/spi_cmd.rs | 280 - esp8266/src/spi0/spi_ctrl.rs | 295 - esp8266/src/spi0/spi_ctrl1.rs | 95 - esp8266/src/spi0/spi_ctrl2.rs | 161 - esp8266/src/spi0/spi_ext0.rs | 95 - esp8266/src/spi0/spi_ext1.rs | 101 - esp8266/src/spi0/spi_ext2.rs | 63 - esp8266/src/spi0/spi_ext3.rs | 66 - esp8266/src/spi0/spi_pin.rs | 114 - esp8266/src/spi0/spi_rd_status.rs | 66 - esp8266/src/spi0/spi_slave.rs | 356 -- esp8266/src/spi0/spi_slave1.rs | 237 - esp8266/src/spi0/spi_slave2.rs | 123 - esp8266/src/spi0/spi_slave3.rs | 123 - esp8266/src/spi0/spi_user.rs | 456 -- esp8266/src/spi0/spi_user1.rs | 123 - esp8266/src/spi0/spi_user2.rs | 85 - esp8266/src/spi0/spi_w0.rs | 63 - esp8266/src/spi0/spi_w1.rs | 63 - esp8266/src/spi0/spi_w10.rs | 63 - esp8266/src/spi0/spi_w11.rs | 63 - esp8266/src/spi0/spi_w12.rs | 63 - esp8266/src/spi0/spi_w13.rs | 63 - esp8266/src/spi0/spi_w14.rs | 63 - esp8266/src/spi0/spi_w15.rs | 63 - esp8266/src/spi0/spi_w2.rs | 63 - esp8266/src/spi0/spi_w3.rs | 63 - esp8266/src/spi0/spi_w4.rs | 63 - esp8266/src/spi0/spi_w5.rs | 63 - esp8266/src/spi0/spi_w6.rs | 63 - esp8266/src/spi0/spi_w7.rs | 63 - esp8266/src/spi0/spi_w8.rs | 63 - esp8266/src/spi0/spi_w9.rs | 63 - esp8266/src/spi0/spi_wr_status.rs | 66 - esp8266/src/spi1.rs | 368 -- esp8266/src/spi1/spi_addr.rs | 98 - esp8266/src/spi1/spi_clock.rs | 142 - esp8266/src/spi1/spi_cmd.rs | 280 - esp8266/src/spi1/spi_ctrl.rs | 295 - esp8266/src/spi1/spi_ctrl1.rs | 95 - esp8266/src/spi1/spi_ctrl2.rs | 161 - esp8266/src/spi1/spi_ext0.rs | 95 - esp8266/src/spi1/spi_ext1.rs | 101 - esp8266/src/spi1/spi_ext2.rs | 63 - esp8266/src/spi1/spi_ext3.rs | 66 - esp8266/src/spi1/spi_pin.rs | 114 - esp8266/src/spi1/spi_rd_status.rs | 66 - esp8266/src/spi1/spi_slave.rs | 356 -- esp8266/src/spi1/spi_slave1.rs | 237 - esp8266/src/spi1/spi_slave2.rs | 123 - esp8266/src/spi1/spi_slave3.rs | 123 - esp8266/src/spi1/spi_user.rs | 456 -- esp8266/src/spi1/spi_user1.rs | 123 - esp8266/src/spi1/spi_user2.rs | 85 - esp8266/src/spi1/spi_w0.rs | 63 - esp8266/src/spi1/spi_w1.rs | 63 - esp8266/src/spi1/spi_w10.rs | 63 - esp8266/src/spi1/spi_w11.rs | 63 - esp8266/src/spi1/spi_w12.rs | 63 - esp8266/src/spi1/spi_w13.rs | 63 - esp8266/src/spi1/spi_w14.rs | 63 - esp8266/src/spi1/spi_w15.rs | 63 - esp8266/src/spi1/spi_w2.rs | 63 - esp8266/src/spi1/spi_w3.rs | 63 - esp8266/src/spi1/spi_w4.rs | 63 - esp8266/src/spi1/spi_w5.rs | 63 - esp8266/src/spi1/spi_w6.rs | 63 - esp8266/src/spi1/spi_w7.rs | 63 - esp8266/src/spi1/spi_w8.rs | 63 - esp8266/src/spi1/spi_w9.rs | 63 - esp8266/src/spi1/spi_wr_status.rs | 66 - esp8266/src/timer.rs | 98 - esp8266/src/timer/frc1_count.rs | 36 - esp8266/src/timer/frc1_ctrl.rs | 261 - esp8266/src/timer/frc1_int.rs | 66 - esp8266/src/timer/frc1_load.rs | 66 - esp8266/src/timer/frc2_alarm.rs | 63 - esp8266/src/timer/frc2_count.rs | 36 - esp8266/src/timer/frc2_ctrl.rs | 261 - esp8266/src/timer/frc2_int.rs | 66 - esp8266/src/timer/frc2_load.rs | 66 - esp8266/src/uart0.rs | 158 - esp8266/src/uart0/uart_autobaud.rs | 82 - esp8266/src/uart0/uart_clkdiv.rs | 66 - esp8266/src/uart0/uart_conf0.rs | 343 -- esp8266/src/uart0/uart_conf1.rs | 155 - esp8266/src/uart0/uart_date.rs | 63 - esp8266/src/uart0/uart_fifo.rs | 77 - esp8266/src/uart0/uart_highpulse.rs | 39 - esp8266/src/uart0/uart_id.rs | 63 - esp8266/src/uart0/uart_int_clr.rs | 106 - esp8266/src/uart0/uart_int_ena.rs | 218 - esp8266/src/uart0/uart_int_raw.rs | 127 - esp8266/src/uart0/uart_int_st.rs | 127 - esp8266/src/uart0/uart_lowpulse.rs | 39 - esp8266/src/uart0/uart_rxd_cnt.rs | 39 - esp8266/src/uart0/uart_status.rs | 92 - esp8266/src/uart1.rs | 158 - esp8266/src/uart1/uart_autobaud.rs | 82 - esp8266/src/uart1/uart_clkdiv.rs | 66 - esp8266/src/uart1/uart_conf0.rs | 343 -- esp8266/src/uart1/uart_conf1.rs | 155 - esp8266/src/uart1/uart_date.rs | 63 - esp8266/src/uart1/uart_fifo.rs | 77 - esp8266/src/uart1/uart_highpulse.rs | 39 - esp8266/src/uart1/uart_id.rs | 63 - esp8266/src/uart1/uart_int_clr.rs | 106 - esp8266/src/uart1/uart_int_ena.rs | 218 - esp8266/src/uart1/uart_int_raw.rs | 127 - esp8266/src/uart1/uart_int_st.rs | 127 - esp8266/src/uart1/uart_lowpulse.rs | 39 - esp8266/src/uart1/uart_rxd_cnt.rs | 39 - esp8266/src/uart1/uart_status.rs | 92 - esp8266/src/wdt.rs | 77 - esp8266/src/wdt/count.rs | 44 - esp8266/src/wdt/reset_stage.rs | 44 - esp8266/src/wdt/stage.rs | 44 - esp8266/src/wdt/wdt_ctl.rs | 165 - esp8266/src/wdt/wdt_op.rs | 63 - esp8266/src/wdt/wdt_op_nd.rs | 63 - esp8266/src/wdt/wdt_rst.rs | 63 - esp8266/svd/esp8266.base.svd | 6446 -------------------- esp8266/svd/patches/_dport.yaml | 114 - esp8266/svd/patches/_gpio.yaml | 15 - esp8266/svd/patches/_io_mux.yaml | 23 - esp8266/svd/patches/_misc.yaml | 103 - esp8266/svd/patches/_rtc.yaml | 33 - esp8266/svd/patches/_spi.yaml | 213 - esp8266/svd/patches/_timer.yaml | 30 - esp8266/svd/patches/_uart.yaml | 7 - esp8266/svd/patches/esp8266.yaml | 11 - 260 files changed, 40010 deletions(-) delete mode 100644 esp8266/.cargo/config.toml delete mode 100644 esp8266/Cargo.toml delete mode 100644 esp8266/README.md delete mode 100644 esp8266/build.rs delete mode 100644 esp8266/device.x delete mode 100644 esp8266/rust-toolchain.toml delete mode 100644 esp8266/src/dport.rs delete mode 100644 esp8266/src/dport/dport_ctl.rs delete mode 100644 esp8266/src/dport/edge_int_enable.rs delete mode 100644 esp8266/src/dport/ioswap.rs delete mode 100644 esp8266/src/dport/spi_cache.rs delete mode 100644 esp8266/src/dport/spi_cache_target.rs delete mode 100644 esp8266/src/dport/spi_interrupt_type.rs delete mode 100644 esp8266/src/efuse.rs delete mode 100644 esp8266/src/efuse/efuse_data0.rs delete mode 100644 esp8266/src/efuse/efuse_data1.rs delete mode 100644 esp8266/src/efuse/efuse_data2.rs delete mode 100644 esp8266/src/efuse/efuse_data3.rs delete mode 100644 esp8266/src/generic.rs delete mode 100644 esp8266/src/generic/raw.rs delete mode 100644 esp8266/src/gpio.rs delete mode 100644 esp8266/src/gpio/gpio_enable.rs delete mode 100644 esp8266/src/gpio/gpio_enable_w1tc.rs delete mode 100644 esp8266/src/gpio/gpio_enable_w1ts.rs delete mode 100644 esp8266/src/gpio/gpio_in.rs delete mode 100644 esp8266/src/gpio/gpio_out.rs delete mode 100644 esp8266/src/gpio/gpio_out_w1tc.rs delete mode 100644 esp8266/src/gpio/gpio_out_w1ts.rs delete mode 100644 esp8266/src/gpio/gpio_pin0.rs delete mode 100644 esp8266/src/gpio/gpio_pin1.rs delete mode 100644 esp8266/src/gpio/gpio_pin10.rs delete mode 100644 esp8266/src/gpio/gpio_pin11.rs delete mode 100644 esp8266/src/gpio/gpio_pin12.rs delete mode 100644 esp8266/src/gpio/gpio_pin13.rs delete mode 100644 esp8266/src/gpio/gpio_pin14.rs delete mode 100644 esp8266/src/gpio/gpio_pin15.rs delete mode 100644 esp8266/src/gpio/gpio_pin2.rs delete mode 100644 esp8266/src/gpio/gpio_pin3.rs delete mode 100644 esp8266/src/gpio/gpio_pin4.rs delete mode 100644 esp8266/src/gpio/gpio_pin5.rs delete mode 100644 esp8266/src/gpio/gpio_pin6.rs delete mode 100644 esp8266/src/gpio/gpio_pin7.rs delete mode 100644 esp8266/src/gpio/gpio_pin8.rs delete mode 100644 esp8266/src/gpio/gpio_pin9.rs delete mode 100644 esp8266/src/gpio/gpio_rtc_calib_sync.rs delete mode 100644 esp8266/src/gpio/gpio_rtc_calib_value.rs delete mode 100644 esp8266/src/gpio/gpio_sigma_delta.rs delete mode 100644 esp8266/src/gpio/gpio_status.rs delete mode 100644 esp8266/src/gpio/gpio_status_w1tc.rs delete mode 100644 esp8266/src/gpio/gpio_status_w1ts.rs delete mode 100644 esp8266/src/i2s.rs delete mode 100644 esp8266/src/i2s/i2s_fifo_conf.rs delete mode 100644 esp8266/src/i2s/i2sconf.rs delete mode 100644 esp8266/src/i2s/i2sconf_sigle_data.rs delete mode 100644 esp8266/src/i2s/i2sint_clr.rs delete mode 100644 esp8266/src/i2s/i2sint_ena.rs delete mode 100644 esp8266/src/i2s/i2sint_raw.rs delete mode 100644 esp8266/src/i2s/i2sint_st.rs delete mode 100644 esp8266/src/i2s/i2srxeof_num.rs delete mode 100644 esp8266/src/i2s/i2srxfifo.rs delete mode 100644 esp8266/src/i2s/i2stiming.rs delete mode 100644 esp8266/src/i2s/i2stxfifo.rs delete mode 100644 esp8266/src/io_mux.rs delete mode 100644 esp8266/src/io_mux/io_mux_conf.rs delete mode 100644 esp8266/src/io_mux/io_mux_gpio0.rs delete mode 100644 esp8266/src/io_mux/io_mux_gpio2.rs delete mode 100644 esp8266/src/io_mux/io_mux_gpio4.rs delete mode 100644 esp8266/src/io_mux/io_mux_gpio5.rs delete mode 100644 esp8266/src/io_mux/io_mux_mtck.rs delete mode 100644 esp8266/src/io_mux/io_mux_mtdi.rs delete mode 100644 esp8266/src/io_mux/io_mux_mtdo.rs delete mode 100644 esp8266/src/io_mux/io_mux_mtms.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_clk.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_cmd.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_data0.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_data1.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_data2.rs delete mode 100644 esp8266/src/io_mux/io_mux_sd_data3.rs delete mode 100644 esp8266/src/io_mux/io_mux_u0rxd.rs delete mode 100644 esp8266/src/io_mux/io_mux_u0txd.rs delete mode 100644 esp8266/src/lib.rs delete mode 100644 esp8266/src/rng.rs delete mode 100644 esp8266/src/rng/rng.rs delete mode 100644 esp8266/src/rtc.rs delete mode 100644 esp8266/src/rtc/pad_xpd_dcdc_conf.rs delete mode 100644 esp8266/src/rtc/rtc_gpio_conf.rs delete mode 100644 esp8266/src/rtc/rtc_gpio_enable.rs delete mode 100644 esp8266/src/rtc/rtc_gpio_in_data.rs delete mode 100644 esp8266/src/rtc/rtc_gpio_out.rs delete mode 100644 esp8266/src/rtc/rtc_state1.rs delete mode 100644 esp8266/src/rtc/rtc_store0.rs delete mode 100644 esp8266/src/rtccntl.rs delete mode 100644 esp8266/src/rtccntl/pll.rs delete mode 100644 esp8266/src/slc.rs delete mode 100644 esp8266/src/slc/slc_ahb_test.rs delete mode 100644 esp8266/src/slc/slc_bridge_conf.rs delete mode 100644 esp8266/src/slc/slc_conf0.rs delete mode 100644 esp8266/src/slc/slc_conf1.rs delete mode 100644 esp8266/src/slc/slc_date.rs delete mode 100644 esp8266/src/slc/slc_id.rs delete mode 100644 esp8266/src/slc/slc_int_clr.rs delete mode 100644 esp8266/src/slc/slc_int_ena.rs delete mode 100644 esp8266/src/slc/slc_int_raw.rs delete mode 100644 esp8266/src/slc/slc_int_status.rs delete mode 100644 esp8266/src/slc/slc_intvec_tohost.rs delete mode 100644 esp8266/src/slc/slc_rx_dscr_conf.rs delete mode 100644 esp8266/src/slc/slc_rx_eof_bfr_des_addr.rs delete mode 100644 esp8266/src/slc/slc_rx_eof_des_addr.rs delete mode 100644 esp8266/src/slc/slc_rx_fifo_push.rs delete mode 100644 esp8266/src/slc/slc_rx_link.rs delete mode 100644 esp8266/src/slc/slc_rx_status.rs delete mode 100644 esp8266/src/slc/slc_rxlink_dscr.rs delete mode 100644 esp8266/src/slc/slc_rxlink_dscr_bf0.rs delete mode 100644 esp8266/src/slc/slc_rxlink_dscr_bf1.rs delete mode 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"hardware-support", - "no-std", -] -include = [ - "src/**", - "build.rs", - "device.x", -] - -[lib] -bench = false -test = false - -[dependencies] -critical-section = { version = "1.1.1", optional = true } -vcell = "0.1.3" -xtensa-lx = "0.8.0" - -[features] -default = ["xtensa-lx/esp8266"] -rt = [] -impl-register-debug = [] diff --git a/esp8266/README.md b/esp8266/README.md deleted file mode 100644 index f5b4d29e26..0000000000 --- a/esp8266/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# esp8266 - -[![Crates.io](https://img.shields.io/crates/v/esp8266?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp8266) -[![docs.rs](https://img.shields.io/docsrs/esp8266?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp8266) -![Crates.io](https://img.shields.io/crates/l/esp8266?labelColor=1C2C2E&style=flat-square) -[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org) - -A **P**eripheral **A**ccess **C**rate (**PAC**) for the **esp8266** from Espressif. See the [svd2rust] repository for more information on how to use this crate. - -If you find any problems with the included SVD file please open an issue in the [espressif/svd] repository so that the fixes can be applied upstream. - -[svd2rust]: https://github.com/rust-embedded/svd2rust -[espressif/svd]: https://github.com/espressif/svd - -## [Documentation](https://docs.rs/esp8266) - -## License - -Licensed under either of: - -- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) -- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT) - -at your option. - -### Contribution - -Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in -the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without -any additional terms or conditions. diff --git a/esp8266/build.rs b/esp8266/build.rs deleted file mode 100644 index d0781acdb6..0000000000 --- a/esp8266/build.rs +++ /dev/null @@ -1,17 +0,0 @@ -#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; -fn main() { - if env::var_os("CARGO_FEATURE_RT").is_some() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - File::create(out.join("device.x")) - .unwrap() - .write_all(include_bytes!("device.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=device.x"); - } - println!("cargo:rerun-if-changed=build.rs"); -} diff --git a/esp8266/device.x b/esp8266/device.x deleted file mode 100644 index 8b13789179..0000000000 --- a/esp8266/device.x +++ /dev/null @@ -1 +0,0 @@ - diff --git a/esp8266/rust-toolchain.toml b/esp8266/rust-toolchain.toml deleted file mode 100644 index a2f5ab508d..0000000000 --- a/esp8266/rust-toolchain.toml +++ /dev/null @@ -1,2 +0,0 @@ -[toolchain] -channel = "esp" diff --git a/esp8266/src/dport.rs b/esp8266/src/dport.rs deleted file mode 100644 index 7adb818527..0000000000 --- a/esp8266/src/dport.rs +++ /dev/null @@ -1,71 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - _reserved0: [u8; 0x04], - edge_int_enable: EDGE_INT_ENABLE, - _reserved1: [u8; 0x04], - spi_cache: SPI_CACHE, - _reserved2: [u8; 0x04], - dport_ctl: DPORT_CTL, - _reserved3: [u8; 0x08], - spi_interrupt_type: SPI_INTERRUPT_TYPE, - spi_cache_target: SPI_CACHE_TARGET, - ioswap: IOSWAP, -} -impl RegisterBlock { - #[doc = "0x04 - EDGE_INT_ENABLE"] - #[inline(always)] - pub const fn edge_int_enable(&self) -> &EDGE_INT_ENABLE { - &self.edge_int_enable - } - #[doc = "0x0c - Controls SPI memory-mapped caching"] - #[inline(always)] - pub const fn spi_cache(&self) -> &SPI_CACHE { - &self.spi_cache - } - #[doc = "0x14 - DPORT_CTL"] - #[inline(always)] - pub const fn dport_ctl(&self) -> &DPORT_CTL { - &self.dport_ctl - } - #[doc = "0x20 - SPI interrupt type register"] - #[inline(always)] - pub const fn spi_interrupt_type(&self) -> &SPI_INTERRUPT_TYPE { - &self.spi_interrupt_type - } - #[doc = "0x24 - Control where the cache is mapped (unconfirmed)"] - #[inline(always)] - pub const fn spi_cache_target(&self) -> &SPI_CACHE_TARGET { - &self.spi_cache_target - } - #[doc = "0x28 - IO Swap register"] - #[inline(always)] - pub const fn ioswap(&self) -> &IOSWAP { - &self.ioswap - } -} -#[doc = "EDGE_INT_ENABLE (rw) register accessor: EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_int_enable`] module"] -pub type EDGE_INT_ENABLE = crate::Reg; -#[doc = "EDGE_INT_ENABLE"] -pub mod edge_int_enable; -#[doc = "DPORT_CTL (rw) register accessor: DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dport_ctl`] module"] -pub type DPORT_CTL = crate::Reg; -#[doc = "DPORT_CTL"] -pub mod dport_ctl; -#[doc = "IOSWAP (rw) register accessor: IO Swap register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioswap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioswap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioswap`] module"] -pub type IOSWAP = crate::Reg; -#[doc = "IO Swap register"] -pub mod ioswap; -#[doc = "SPI_CACHE (rw) register accessor: Controls SPI memory-mapped caching\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache`] module"] -pub type SPI_CACHE = crate::Reg; -#[doc = "Controls SPI memory-mapped caching"] -pub mod spi_cache; -#[doc = "SPI_INTERRUPT_TYPE (r) register accessor: SPI interrupt type register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_interrupt_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_interrupt_type`] module"] -pub type SPI_INTERRUPT_TYPE = crate::Reg; -#[doc = "SPI interrupt type register"] -pub mod spi_interrupt_type; -#[doc = "SPI_CACHE_TARGET (rw) register accessor: Control where the cache is mapped (unconfirmed)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache_target::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache_target::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache_target`] module"] -pub type SPI_CACHE_TARGET = crate::Reg; -#[doc = "Control where the cache is mapped (unconfirmed)"] -pub mod spi_cache_target; diff --git a/esp8266/src/dport/dport_ctl.rs b/esp8266/src/dport/dport_ctl.rs deleted file mode 100644 index af3a6dbfb2..0000000000 --- a/esp8266/src/dport/dport_ctl.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `DPORT_CTL` reader"] -pub type R = crate::R; -#[doc = "Register `DPORT_CTL` writer"] -pub type W = crate::W; -#[doc = "Field `DPORT_CTL_DOUBLE_CLK` reader - "] -pub type DPORT_CTL_DOUBLE_CLK_R = crate::BitReader; -#[doc = "Field `DPORT_CTL_DOUBLE_CLK` writer - "] -pub type DPORT_CTL_DOUBLE_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn dport_ctl_double_clk(&self) -> DPORT_CTL_DOUBLE_CLK_R { - DPORT_CTL_DOUBLE_CLK_R::new((self.bits & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DPORT_CTL") - .field( - "dport_ctl_double_clk", - &format_args!("{}", self.dport_ctl_double_clk().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn dport_ctl_double_clk(&mut self) -> DPORT_CTL_DOUBLE_CLK_W { - DPORT_CTL_DOUBLE_CLK_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct DPORT_CTL_SPEC; -impl crate::RegisterSpec for DPORT_CTL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`dport_ctl::R`](R) reader structure"] -impl crate::Readable for DPORT_CTL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`dport_ctl::W`](W) writer structure"] -impl crate::Writable for DPORT_CTL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets DPORT_CTL to value 0"] -impl crate::Resettable for DPORT_CTL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/dport/edge_int_enable.rs b/esp8266/src/dport/edge_int_enable.rs deleted file mode 100644 index 45c3fef33d..0000000000 --- a/esp8266/src/dport/edge_int_enable.rs +++ /dev/null @@ -1,101 +0,0 @@ -#[doc = "Register `EDGE_INT_ENABLE` reader"] -pub type R = crate::R; -#[doc = "Register `EDGE_INT_ENABLE` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `wdt_edge_int_enable` reader - Enable the watchdog timer edge interrupt"] -pub type WDT_EDGE_INT_ENABLE_R = crate::BitReader; -#[doc = "Field `wdt_edge_int_enable` writer - Enable the watchdog timer edge interrupt"] -pub type WDT_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `timer1_edge_int_enable` reader - Enable the timer1 edge interrupt"] -pub type TIMER1_EDGE_INT_ENABLE_R = crate::BitReader; -#[doc = "Field `timer1_edge_int_enable` writer - Enable the timer1 edge interrupt"] -pub type TIMER1_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - Enable the watchdog timer edge interrupt"] - #[inline(always)] - pub fn wdt_edge_int_enable(&self) -> WDT_EDGE_INT_ENABLE_R { - WDT_EDGE_INT_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Enable the timer1 edge interrupt"] - #[inline(always)] - pub fn timer1_edge_int_enable(&self) -> TIMER1_EDGE_INT_ENABLE_R { - TIMER1_EDGE_INT_ENABLE_R::new(((self.bits >> 1) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EDGE_INT_ENABLE") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "wdt_edge_int_enable", - &format_args!("{}", self.wdt_edge_int_enable().bit()), - ) - .field( - "timer1_edge_int_enable", - &format_args!("{}", self.timer1_edge_int_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - Enable the watchdog timer edge interrupt"] - #[inline(always)] - #[must_use] - pub fn wdt_edge_int_enable(&mut self) -> WDT_EDGE_INT_ENABLE_W { - WDT_EDGE_INT_ENABLE_W::new(self, 0) - } - #[doc = "Bit 1 - Enable the timer1 edge interrupt"] - #[inline(always)] - #[must_use] - pub fn timer1_edge_int_enable(&mut self) -> TIMER1_EDGE_INT_ENABLE_W { - TIMER1_EDGE_INT_ENABLE_W::new(self, 1) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EDGE_INT_ENABLE_SPEC; -impl crate::RegisterSpec for EDGE_INT_ENABLE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`edge_int_enable::R`](R) reader structure"] -impl crate::Readable for EDGE_INT_ENABLE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`edge_int_enable::W`](W) writer structure"] -impl crate::Writable for EDGE_INT_ENABLE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets EDGE_INT_ENABLE to value 0"] -impl crate::Resettable for EDGE_INT_ENABLE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/dport/ioswap.rs b/esp8266/src/dport/ioswap.rs deleted file mode 100644 index 4514619ce2..0000000000 --- a/esp8266/src/dport/ioswap.rs +++ /dev/null @@ -1,159 +0,0 @@ -#[doc = "Register `IOSWAP` reader"] -pub type R = crate::R; -#[doc = "Register `IOSWAP` writer"] -pub type W = crate::W; -#[doc = "Field `uart` reader - Swap UART"] -pub type UART_R = crate::BitReader; -#[doc = "Field `uart` writer - Swap UART"] -pub type UART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi` reader - Swap SPI"] -pub type SPI_R = crate::BitReader; -#[doc = "Field `spi` writer - Swap SPI"] -pub type SPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart0` reader - Swap UART0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)"] -pub type UART0_R = crate::BitReader; -#[doc = "Field `uart0` writer - Swap UART0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)"] -pub type UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart1` reader - Swap UART1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)"] -pub type UART1_R = crate::BitReader; -#[doc = "Field `uart1` writer - Swap UART1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)"] -pub type UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `hspi` reader - Set HSPI with higher priority"] -pub type HSPI_R = crate::BitReader; -#[doc = "Field `hspi` writer - Set HSPI with higher priority"] -pub type HSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `double_hspi` reader - Set two SPI masters on HSPI"] -pub type DOUBLE_HSPI_R = crate::BitReader; -#[doc = "Field `double_hspi` writer - Set two SPI masters on HSPI"] -pub type DOUBLE_HSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `double_cspi` reader - Set two SPI masters on CSPI"] -pub type DOUBLE_CSPI_R = crate::BitReader; -#[doc = "Field `double_cspi` writer - Set two SPI masters on CSPI"] -pub type DOUBLE_CSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Swap UART"] - #[inline(always)] - pub fn uart(&self) -> UART_R { - UART_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Swap SPI"] - #[inline(always)] - pub fn spi(&self) -> SPI_R { - SPI_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Swap UART0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)"] - #[inline(always)] - pub fn uart0(&self) -> UART0_R { - UART0_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - Swap UART1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)"] - #[inline(always)] - pub fn uart1(&self) -> UART1_R { - UART1_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 5 - Set HSPI with higher priority"] - #[inline(always)] - pub fn hspi(&self) -> HSPI_R { - HSPI_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Set two SPI masters on HSPI"] - #[inline(always)] - pub fn double_hspi(&self) -> DOUBLE_HSPI_R { - DOUBLE_HSPI_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Set two SPI masters on CSPI"] - #[inline(always)] - pub fn double_cspi(&self) -> DOUBLE_CSPI_R { - DOUBLE_CSPI_R::new(((self.bits >> 7) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IOSWAP") - .field("uart", &format_args!("{}", self.uart().bit())) - .field("spi", &format_args!("{}", self.spi().bit())) - .field("uart0", &format_args!("{}", self.uart0().bit())) - .field("uart1", &format_args!("{}", self.uart1().bit())) - .field("hspi", &format_args!("{}", self.hspi().bit())) - .field("double_hspi", &format_args!("{}", self.double_hspi().bit())) - .field("double_cspi", &format_args!("{}", self.double_cspi().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Swap UART"] - #[inline(always)] - #[must_use] - pub fn uart(&mut self) -> UART_W { - UART_W::new(self, 0) - } - #[doc = "Bit 1 - Swap SPI"] - #[inline(always)] - #[must_use] - pub fn spi(&mut self) -> SPI_W { - SPI_W::new(self, 1) - } - #[doc = "Bit 2 - Swap UART0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)"] - #[inline(always)] - #[must_use] - pub fn uart0(&mut self) -> UART0_W { - UART0_W::new(self, 2) - } - #[doc = "Bit 3 - Swap UART1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)"] - #[inline(always)] - #[must_use] - pub fn uart1(&mut self) -> UART1_W { - UART1_W::new(self, 3) - } - #[doc = "Bit 5 - Set HSPI with higher priority"] - #[inline(always)] - #[must_use] - pub fn hspi(&mut self) -> HSPI_W { - HSPI_W::new(self, 5) - } - #[doc = "Bit 6 - Set two SPI masters on HSPI"] - #[inline(always)] - #[must_use] - pub fn double_hspi(&mut self) -> DOUBLE_HSPI_W { - DOUBLE_HSPI_W::new(self, 6) - } - #[doc = "Bit 7 - Set two SPI masters on CSPI"] - #[inline(always)] - #[must_use] - pub fn double_cspi(&mut self) -> DOUBLE_CSPI_W { - DOUBLE_CSPI_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO Swap register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioswap::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioswap::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IOSWAP_SPEC; -impl crate::RegisterSpec for IOSWAP_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`ioswap::R`](R) reader structure"] -impl crate::Readable for IOSWAP_SPEC {} -#[doc = "`write(|w| ..)` method takes [`ioswap::W`](W) writer structure"] -impl crate::Writable for IOSWAP_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IOSWAP to value 0"] -impl crate::Resettable for IOSWAP_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/dport/spi_cache.rs b/esp8266/src/dport/spi_cache.rs deleted file mode 100644 index e7e3c1b87f..0000000000 --- a/esp8266/src/dport/spi_cache.rs +++ /dev/null @@ -1,165 +0,0 @@ -#[doc = "Register `SPI_CACHE` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CACHE` writer"] -pub type W = crate::W; -#[doc = "Field `cache_flush_start` reader - Flush cache"] -pub type CACHE_FLUSH_START_R = crate::BitReader; -#[doc = "Field `cache_flush_start` writer - Flush cache"] -pub type CACHE_FLUSH_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cache_empty` reader - Cache is empty"] -pub type CACHE_EMPTY_R = crate::BitReader; -#[doc = "Field `cache_empty` writer - Cache is empty"] -pub type CACHE_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cache_enable` reader - Cache enable"] -pub type CACHE_ENABLE_R = crate::BitReader; -#[doc = "Field `cache_enable` writer - Cache enable"] -pub type CACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busy` reader - SPI busy"] -pub type BUSY_R = crate::BitReader; -#[doc = "Field `busy` writer - SPI busy"] -pub type BUSY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `block` reader - Flash memory block to map, in 2mb blocks"] -pub type BLOCK_R = crate::FieldReader; -#[doc = "Field `block` writer - Flash memory block to map, in 2mb blocks"] -pub type BLOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `offset` reader - Offset within block to map, in megabytes"] -pub type OFFSET_R = crate::FieldReader; -#[doc = "Field `offset` writer - Offset within block to map, in megabytes"] -pub type OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `target` reader - Controls where the spi flash is mapped (unconfirmed)"] -pub type TARGET_R = crate::BitReader; -#[doc = "Field `target` writer - Controls where the spi flash is mapped (unconfirmed)"] -pub type TARGET_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Flush cache"] - #[inline(always)] - pub fn cache_flush_start(&self) -> CACHE_FLUSH_START_R { - CACHE_FLUSH_START_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Cache is empty"] - #[inline(always)] - pub fn cache_empty(&self) -> CACHE_EMPTY_R { - CACHE_EMPTY_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 8 - Cache enable"] - #[inline(always)] - pub fn cache_enable(&self) -> CACHE_ENABLE_R { - CACHE_ENABLE_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - SPI busy"] - #[inline(always)] - pub fn busy(&self) -> BUSY_R { - BUSY_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 16:18 - Flash memory block to map, in 2mb blocks"] - #[inline(always)] - pub fn block(&self) -> BLOCK_R { - BLOCK_R::new(((self.bits >> 16) & 7) as u8) - } - #[doc = "Bits 24:25 - Offset within block to map, in megabytes"] - #[inline(always)] - pub fn offset(&self) -> OFFSET_R { - OFFSET_R::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bit 26 - Controls where the spi flash is mapped (unconfirmed)"] - #[inline(always)] - pub fn target(&self) -> TARGET_R { - TARGET_R::new(((self.bits >> 26) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CACHE") - .field( - "cache_flush_start", - &format_args!("{}", self.cache_flush_start().bit()), - ) - .field("cache_empty", &format_args!("{}", self.cache_empty().bit())) - .field( - "cache_enable", - &format_args!("{}", self.cache_enable().bit()), - ) - .field("busy", &format_args!("{}", self.busy().bit())) - .field("block", &format_args!("{}", self.block().bits())) - .field("offset", &format_args!("{}", self.offset().bits())) - .field("target", &format_args!("{}", self.target().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Flush cache"] - #[inline(always)] - #[must_use] - pub fn cache_flush_start(&mut self) -> CACHE_FLUSH_START_W { - CACHE_FLUSH_START_W::new(self, 0) - } - #[doc = "Bit 1 - Cache is empty"] - #[inline(always)] - #[must_use] - pub fn cache_empty(&mut self) -> CACHE_EMPTY_W { - CACHE_EMPTY_W::new(self, 1) - } - #[doc = "Bit 8 - Cache enable"] - #[inline(always)] - #[must_use] - pub fn cache_enable(&mut self) -> CACHE_ENABLE_W { - CACHE_ENABLE_W::new(self, 8) - } - #[doc = "Bit 9 - SPI busy"] - #[inline(always)] - #[must_use] - pub fn busy(&mut self) -> BUSY_W { - BUSY_W::new(self, 9) - } - #[doc = "Bits 16:18 - Flash memory block to map, in 2mb blocks"] - #[inline(always)] - #[must_use] - pub fn block(&mut self) -> BLOCK_W { - BLOCK_W::new(self, 16) - } - #[doc = "Bits 24:25 - Offset within block to map, in megabytes"] - #[inline(always)] - #[must_use] - pub fn offset(&mut self) -> OFFSET_W { - OFFSET_W::new(self, 24) - } - #[doc = "Bit 26 - Controls where the spi flash is mapped (unconfirmed)"] - #[inline(always)] - #[must_use] - pub fn target(&mut self) -> TARGET_W { - TARGET_W::new(self, 26) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Controls SPI memory-mapped caching\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CACHE_SPEC; -impl crate::RegisterSpec for SPI_CACHE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_cache::R`](R) reader structure"] -impl crate::Readable for SPI_CACHE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_cache::W`](W) writer structure"] -impl crate::Writable for SPI_CACHE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CACHE to value 0"] -impl crate::Resettable for SPI_CACHE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/dport/spi_cache_target.rs b/esp8266/src/dport/spi_cache_target.rs deleted file mode 100644 index d3c1550796..0000000000 --- a/esp8266/src/dport/spi_cache_target.rs +++ /dev/null @@ -1,79 +0,0 @@ -#[doc = "Register `SPI_CACHE_TARGET` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CACHE_TARGET` writer"] -pub type W = crate::W; -#[doc = "Field `target1` reader - "] -pub type TARGET1_R = crate::BitReader; -#[doc = "Field `target1` writer - "] -pub type TARGET1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `target2` reader - "] -pub type TARGET2_R = crate::BitReader; -#[doc = "Field `target2` writer - "] -pub type TARGET2_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 3"] - #[inline(always)] - pub fn target1(&self) -> TARGET1_R { - TARGET1_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn target2(&self) -> TARGET2_R { - TARGET2_R::new(((self.bits >> 4) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CACHE_TARGET") - .field("target1", &format_args!("{}", self.target1().bit())) - .field("target2", &format_args!("{}", self.target2().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn target1(&mut self) -> TARGET1_W { - TARGET1_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn target2(&mut self) -> TARGET2_W { - TARGET2_W::new(self, 4) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Control where the cache is mapped (unconfirmed)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache_target::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache_target::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CACHE_TARGET_SPEC; -impl crate::RegisterSpec for SPI_CACHE_TARGET_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_cache_target::R`](R) reader structure"] -impl crate::Readable for SPI_CACHE_TARGET_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_cache_target::W`](W) writer structure"] -impl crate::Writable for SPI_CACHE_TARGET_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CACHE_TARGET to value 0"] -impl crate::Resettable for SPI_CACHE_TARGET_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/dport/spi_interrupt_type.rs b/esp8266/src/dport/spi_interrupt_type.rs deleted file mode 100644 index 3e35888706..0000000000 --- a/esp8266/src/dport/spi_interrupt_type.rs +++ /dev/null @@ -1,52 +0,0 @@ -#[doc = "Register `SPI_INTERRUPT_TYPE` reader"] -pub type R = crate::R; -#[doc = "Field `spi0` reader - SPI0 interrupt"] -pub type SPI0_R = crate::BitReader; -#[doc = "Field `spi1` reader - SPI1 interrupt"] -pub type SPI1_R = crate::BitReader; -#[doc = "Field `i2s` reader - I2S interrupt"] -pub type I2S_R = crate::BitReader; -impl R { - #[doc = "Bit 4 - SPI0 interrupt"] - #[inline(always)] - pub fn spi0(&self) -> SPI0_R { - SPI0_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 7 - SPI1 interrupt"] - #[inline(always)] - pub fn spi1(&self) -> SPI1_R { - SPI1_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 9 - I2S interrupt"] - #[inline(always)] - pub fn i2s(&self) -> I2S_R { - I2S_R::new(((self.bits >> 9) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_INTERRUPT_TYPE") - .field("spi0", &format_args!("{}", self.spi0().bit())) - .field("spi1", &format_args!("{}", self.spi1().bit())) - .field("i2s", &format_args!("{}", self.i2s().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "SPI interrupt type register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_interrupt_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_INTERRUPT_TYPE_SPEC; -impl crate::RegisterSpec for SPI_INTERRUPT_TYPE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_interrupt_type::R`](R) reader structure"] -impl crate::Readable for SPI_INTERRUPT_TYPE_SPEC {} -#[doc = "`reset()` method sets SPI_INTERRUPT_TYPE to value 0"] -impl crate::Resettable for SPI_INTERRUPT_TYPE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/efuse.rs b/esp8266/src/efuse.rs deleted file mode 100644 index a8b85e1771..0000000000 --- a/esp8266/src/efuse.rs +++ /dev/null @@ -1,47 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - efuse_data0: EFUSE_DATA0, - efuse_data1: EFUSE_DATA1, - efuse_data2: EFUSE_DATA2, - efuse_data3: EFUSE_DATA3, -} -impl RegisterBlock { - #[doc = "0x00 - EFUSE_DATA0"] - #[inline(always)] - pub const fn efuse_data0(&self) -> &EFUSE_DATA0 { - &self.efuse_data0 - } - #[doc = "0x04 - EFUSE_DATA1"] - #[inline(always)] - pub const fn efuse_data1(&self) -> &EFUSE_DATA1 { - &self.efuse_data1 - } - #[doc = "0x08 - EFUSE_DATA2"] - #[inline(always)] - pub const fn efuse_data2(&self) -> &EFUSE_DATA2 { - &self.efuse_data2 - } - #[doc = "0x0c - EFUSE_DATA3"] - #[inline(always)] - pub const fn efuse_data3(&self) -> &EFUSE_DATA3 { - &self.efuse_data3 - } -} -#[doc = "EFUSE_DATA0 (rw) register accessor: EFUSE_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_data0`] module"] -pub type EFUSE_DATA0 = crate::Reg; -#[doc = "EFUSE_DATA0"] -pub mod efuse_data0; -#[doc = "EFUSE_DATA1 (rw) register accessor: EFUSE_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_data1`] module"] -pub type EFUSE_DATA1 = crate::Reg; -#[doc = "EFUSE_DATA1"] -pub mod efuse_data1; -#[doc = "EFUSE_DATA2 (rw) register accessor: EFUSE_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_data2`] module"] -pub type EFUSE_DATA2 = crate::Reg; -#[doc = "EFUSE_DATA2"] -pub mod efuse_data2; -#[doc = "EFUSE_DATA3 (rw) register accessor: EFUSE_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@efuse_data3`] module"] -pub type EFUSE_DATA3 = crate::Reg; -#[doc = "EFUSE_DATA3"] -pub mod efuse_data3; diff --git a/esp8266/src/efuse/efuse_data0.rs b/esp8266/src/efuse/efuse_data0.rs deleted file mode 100644 index f78a5bdcdd..0000000000 --- a/esp8266/src/efuse/efuse_data0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `EFUSE_DATA0` reader"] -pub type R = crate::R; -#[doc = "Register `EFUSE_DATA0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EFUSE_DATA0") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "EFUSE_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EFUSE_DATA0_SPEC; -impl crate::RegisterSpec for EFUSE_DATA0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`efuse_data0::R`](R) reader structure"] -impl crate::Readable for EFUSE_DATA0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`efuse_data0::W`](W) writer structure"] -impl crate::Writable for EFUSE_DATA0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets EFUSE_DATA0 to value 0"] -impl crate::Resettable for EFUSE_DATA0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/efuse/efuse_data1.rs b/esp8266/src/efuse/efuse_data1.rs deleted file mode 100644 index ac505a6740..0000000000 --- a/esp8266/src/efuse/efuse_data1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `EFUSE_DATA1` reader"] -pub type R = crate::R; -#[doc = "Register `EFUSE_DATA1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EFUSE_DATA1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "EFUSE_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EFUSE_DATA1_SPEC; -impl crate::RegisterSpec for EFUSE_DATA1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`efuse_data1::R`](R) reader structure"] -impl crate::Readable for EFUSE_DATA1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`efuse_data1::W`](W) writer structure"] -impl crate::Writable for EFUSE_DATA1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets EFUSE_DATA1 to value 0"] -impl crate::Resettable for EFUSE_DATA1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/efuse/efuse_data2.rs b/esp8266/src/efuse/efuse_data2.rs deleted file mode 100644 index cfd3ce011c..0000000000 --- a/esp8266/src/efuse/efuse_data2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `EFUSE_DATA2` reader"] -pub type R = crate::R; -#[doc = "Register `EFUSE_DATA2` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EFUSE_DATA2") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "EFUSE_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EFUSE_DATA2_SPEC; -impl crate::RegisterSpec for EFUSE_DATA2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`efuse_data2::R`](R) reader structure"] -impl crate::Readable for EFUSE_DATA2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`efuse_data2::W`](W) writer structure"] -impl crate::Writable for EFUSE_DATA2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets EFUSE_DATA2 to value 0"] -impl crate::Resettable for EFUSE_DATA2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/efuse/efuse_data3.rs b/esp8266/src/efuse/efuse_data3.rs deleted file mode 100644 index 1f8c083f56..0000000000 --- a/esp8266/src/efuse/efuse_data3.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `EFUSE_DATA3` reader"] -pub type R = crate::R; -#[doc = "Register `EFUSE_DATA3` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EFUSE_DATA3") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "EFUSE_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efuse_data3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`efuse_data3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct EFUSE_DATA3_SPEC; -impl crate::RegisterSpec for EFUSE_DATA3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`efuse_data3::R`](R) reader structure"] -impl crate::Readable for EFUSE_DATA3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`efuse_data3::W`](W) writer structure"] -impl crate::Writable for EFUSE_DATA3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets EFUSE_DATA3 to value 0"] -impl crate::Resettable for EFUSE_DATA3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/generic.rs b/esp8266/src/generic.rs deleted file mode 100644 index 59c8e74749..0000000000 --- a/esp8266/src/generic.rs +++ /dev/null @@ -1,522 +0,0 @@ -use core::marker; -#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] -pub trait RawReg: - Copy - + Default - + From - + core::ops::BitOr - + core::ops::BitAnd - + core::ops::BitOrAssign - + core::ops::BitAndAssign - + core::ops::Not - + core::ops::Shl -{ - #[doc = " Mask for bits of width `WI`"] - fn mask() -> Self; - #[doc = " Mask for bits of width 1"] - fn one() -> Self; -} -macro_rules! raw_reg { - ($ U : ty , $ size : literal , $ mask : ident) => { - impl RawReg for $U { - #[inline(always)] - fn mask() -> Self { - $mask::() - } - #[inline(always)] - fn one() -> Self { - 1 - } - } - const fn $mask() -> $U { - <$U>::MAX >> ($size - WI) - } - impl FieldSpec for $U { - type Ux = $U; - } - }; -} -raw_reg!(u8, 8, mask_u8); -raw_reg!(u16, 16, mask_u16); -raw_reg!(u32, 32, mask_u32); -raw_reg!(u64, 64, mask_u64); -#[doc = " Raw register type"] -pub trait RegisterSpec { - #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] - type Ux: RawReg; -} -#[doc = " Raw field type"] -pub trait FieldSpec: Sized { - #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] - type Ux: Copy + PartialEq + From; -} -#[doc = " Trait implemented by readable registers to enable the `read` method."] -#[doc = ""] -#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec {} -#[doc = " Trait implemented by writeable registers."] -#[doc = ""] -#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] -#[doc = ""] -#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] -pub trait Writable: RegisterSpec { - #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; - #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; -} -#[doc = " Reset value of the register."] -#[doc = ""] -#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] -#[doc = " register by using the `reset` method."] -pub trait Resettable: RegisterSpec { - #[doc = " Reset value of the register."] - const RESET_VALUE: Self::Ux; - #[doc = " Reset value of the register."] - #[inline(always)] - fn reset_value() -> Self::Ux { - Self::RESET_VALUE - } -} -#[doc = " This structure provides volatile access to registers."] -#[repr(transparent)] -pub struct Reg { - register: vcell::VolatileCell, - _marker: marker::PhantomData, -} -unsafe impl Send for Reg where REG::Ux: Send {} -impl Reg { - #[doc = " Returns the underlying memory address of register."] - #[doc = ""] - #[doc = " ```ignore"] - #[doc = " let reg_ptr = periph.reg.as_ptr();"] - #[doc = " ```"] - #[inline(always)] - pub fn as_ptr(&self) -> *mut REG::Ux { - self.register.as_ptr() - } -} -impl Reg { - #[doc = " Reads the contents of a `Readable` register."] - #[doc = ""] - #[doc = " You can read the raw contents of a register by using `bits`:"] - #[doc = " ```ignore"] - #[doc = " let bits = periph.reg.read().bits();"] - #[doc = " ```"] - #[doc = " or get the content of a particular field of a register:"] - #[doc = " ```ignore"] - #[doc = " let reader = periph.reg.read();"] - #[doc = " let bits = reader.field1().bits();"] - #[doc = " let flag = reader.field2().bit_is_set();"] - #[doc = " ```"] - #[inline(always)] - pub fn read(&self) -> R { - R { - bits: self.register.get(), - _reg: marker::PhantomData, - } - } -} -impl Reg { - #[doc = " Writes the reset value to `Writable` register."] - #[doc = ""] - #[doc = " Resets the register to its initial state."] - #[inline(always)] - pub fn reset(&self) { - self.register.set(REG::RESET_VALUE) - } - #[doc = " Writes bits to a `Writable` register."] - #[doc = ""] - #[doc = " You can write raw bits into a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] - #[doc = " ```"] - #[doc = " or write only the fields you need:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " In the latter case, other fields will be set to their reset value."] - #[inline(always)] - pub fn write(&self, f: F) - where - F: FnOnce(&mut W) -> &mut W, - { - self.register.set( - f(&mut W { - bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }) - .bits, - ); - } -} -impl Reg { - #[doc = " Writes 0 to a `Writable` register."] - #[doc = ""] - #[doc = " Similar to `write`, but unused bits will contain 0."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Unsafe to use with registers which don't allow to write 0."] - #[inline(always)] - pub unsafe fn write_with_zero(&self, f: F) - where - F: FnOnce(&mut W) -> &mut W, - { - self.register.set( - f(&mut W { - bits: REG::Ux::default(), - _reg: marker::PhantomData, - }) - .bits, - ); - } -} -impl Reg { - #[doc = " Modifies the contents of the register by reading and then writing it."] - #[doc = ""] - #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] - #[doc = " r.bits() | 3"] - #[doc = " ) });"] - #[doc = " ```"] - #[doc = " or"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " Other fields will have the value they had before the call to `modify`."] - #[inline(always)] - pub fn modify(&self, f: F) - where - for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, - { - let bits = self.register.get(); - self.register.set( - f( - &R { - bits, - _reg: marker::PhantomData, - }, - &mut W { - bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }, - ) - .bits, - ); - } -} -#[doc(hidden)] -pub mod raw; -#[doc = " Register reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] -#[doc = " method."] -pub type R = raw::R; -impl R { - #[doc = " Reads raw bits from register."] - #[inline(always)] - pub const fn bits(&self) -> REG::Ux { - self.bits - } -} -impl PartialEq for R -where - REG::Ux: PartialEq, - FI: Copy, - REG::Ux: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(®::Ux::from(*other)) - } -} -#[doc = " Register writer."] -#[doc = ""] -#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub type W = raw::W; -#[doc = " Field reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of fields."] -pub type FieldReader = raw::FieldReader; -#[doc = " Bit-wise field reader"] -pub type BitReader = raw::BitReader; -impl FieldReader { - #[doc = " Reads raw bits from field."] - #[inline(always)] - pub const fn bits(&self) -> FI::Ux { - self.bits - } -} -impl PartialEq for FieldReader -where - FI: FieldSpec + Copy, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&FI::Ux::from(*other)) - } -} -impl PartialEq for BitReader -where - FI: Copy, - bool: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&bool::from(*other)) - } -} -impl BitReader { - #[doc = " Value of the field as raw bits."] - #[inline(always)] - pub const fn bit(&self) -> bool { - self.bits - } - #[doc = " Returns `true` if the bit is clear (0)."] - #[inline(always)] - pub const fn bit_is_clear(&self) -> bool { - !self.bit() - } - #[doc = " Returns `true` if the bit is set (1)."] - #[inline(always)] - pub const fn bit_is_set(&self) -> bool { - self.bit() - } -} -#[doc(hidden)] -pub struct Safe; -#[doc(hidden)] -pub struct Unsafe; -#[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; -#[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>; -impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Field width"] - pub const WIDTH: u8 = WI; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - WI - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Field width"] - pub const WIDTH: u8 = WI; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - WI - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bits(FI::Ux::from(variant)) - } -} -macro_rules! bit_proxy { - ($ writer : ident , $ mwv : ident) => { - #[doc(hidden)] - pub struct $mwv; - #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; - impl<'a, REG, FI> $writer<'a, REG, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { - #[doc = " Field width"] - pub const WIDTH: u8 = 1; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - Self::WIDTH - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } - #[doc = " Writes bit to the field"] - #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bit(bool::from(variant)) - } - } - }; -} -bit_proxy!(BitWriter, BitM); -bit_proxy!(BitWriter1S, Bit1S); -bit_proxy!(BitWriter0C, Bit0C); -bit_proxy!(BitWriter1C, Bit1C); -bit_proxy!(BitWriter0S, Bit0S); -bit_proxy!(BitWriter1T, Bit1T); -bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, FI> BitWriter<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Clears the field bit by passing one"] - #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Sets the field bit by passing zero"] - #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing one"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing zero"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} diff --git a/esp8266/src/generic/raw.rs b/esp8266/src/generic/raw.rs deleted file mode 100644 index 81f5779524..0000000000 --- a/esp8266/src/generic/raw.rs +++ /dev/null @@ -1,93 +0,0 @@ -use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; -pub struct R { - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct FieldReader -where - FI: FieldSpec, -{ - pub(crate) bits: FI::Ux, - _reg: marker::PhantomData, -} -impl FieldReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: FI::Ux) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -pub struct BitReader { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, Safety)>, -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} -pub struct BitWriter<'a, REG, FI = bool, M = BitM> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} diff --git a/esp8266/src/gpio.rs b/esp8266/src/gpio.rs deleted file mode 100644 index e74fb60f4c..0000000000 --- a/esp8266/src/gpio.rs +++ /dev/null @@ -1,297 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - gpio_out: GPIO_OUT, - gpio_out_w1ts: GPIO_OUT_W1TS, - gpio_out_w1tc: GPIO_OUT_W1TC, - gpio_enable: GPIO_ENABLE, - gpio_enable_w1ts: GPIO_ENABLE_W1TS, - gpio_enable_w1tc: GPIO_ENABLE_W1TC, - gpio_in: GPIO_IN, - gpio_status: GPIO_STATUS, - gpio_status_w1ts: GPIO_STATUS_W1TS, - gpio_status_w1tc: GPIO_STATUS_W1TC, - gpio_pin0: GPIO_PIN0, - gpio_pin1: GPIO_PIN1, - gpio_pin2: GPIO_PIN2, - gpio_pin3: GPIO_PIN3, - gpio_pin4: GPIO_PIN4, - gpio_pin5: GPIO_PIN5, - gpio_pin6: GPIO_PIN6, - gpio_pin7: GPIO_PIN7, - gpio_pin8: GPIO_PIN8, - gpio_pin9: GPIO_PIN9, - gpio_pin10: GPIO_PIN10, - gpio_pin11: GPIO_PIN11, - gpio_pin12: GPIO_PIN12, - gpio_pin13: GPIO_PIN13, - gpio_pin14: GPIO_PIN14, - gpio_pin15: GPIO_PIN15, - gpio_sigma_delta: GPIO_SIGMA_DELTA, - gpio_rtc_calib_sync: GPIO_RTC_CALIB_SYNC, - gpio_rtc_calib_value: GPIO_RTC_CALIB_VALUE, -} -impl RegisterBlock { - #[doc = "0x00 - BT-Coexist Selection register"] - #[inline(always)] - pub const fn gpio_out(&self) -> &GPIO_OUT { - &self.gpio_out - } - #[doc = "0x04 - GPIO_OUT_W1TS"] - #[inline(always)] - pub const fn gpio_out_w1ts(&self) -> &GPIO_OUT_W1TS { - &self.gpio_out_w1ts - } - #[doc = "0x08 - GPIO_OUT_W1TC"] - #[inline(always)] - pub const fn gpio_out_w1tc(&self) -> &GPIO_OUT_W1TC { - &self.gpio_out_w1tc - } - #[doc = "0x0c - GPIO_ENABLE"] - #[inline(always)] - pub const fn gpio_enable(&self) -> &GPIO_ENABLE { - &self.gpio_enable - } - #[doc = "0x10 - GPIO_ENABLE_W1TS"] - #[inline(always)] - pub const fn gpio_enable_w1ts(&self) -> &GPIO_ENABLE_W1TS { - &self.gpio_enable_w1ts - } - #[doc = "0x14 - GPIO_ENABLE_W1TC"] - #[inline(always)] - pub const fn gpio_enable_w1tc(&self) -> &GPIO_ENABLE_W1TC { - &self.gpio_enable_w1tc - } - #[doc = "0x18 - The values of the strapping pins."] - #[inline(always)] - pub const fn gpio_in(&self) -> &GPIO_IN { - &self.gpio_in - } - #[doc = "0x1c - GPIO_STATUS"] - #[inline(always)] - pub const fn gpio_status(&self) -> &GPIO_STATUS { - &self.gpio_status - } - #[doc = "0x20 - GPIO_STATUS_W1TS"] - #[inline(always)] - pub const fn gpio_status_w1ts(&self) -> &GPIO_STATUS_W1TS { - &self.gpio_status_w1ts - } - #[doc = "0x24 - GPIO_STATUS_W1TC"] - #[inline(always)] - pub const fn gpio_status_w1tc(&self) -> &GPIO_STATUS_W1TC { - &self.gpio_status_w1tc - } - #[doc = "0x28 - GPIO_PIN0"] - #[inline(always)] - pub const fn gpio_pin0(&self) -> &GPIO_PIN0 { - &self.gpio_pin0 - } - #[doc = "0x2c - GPIO_PIN1"] - #[inline(always)] - pub const fn gpio_pin1(&self) -> &GPIO_PIN1 { - &self.gpio_pin1 - } - #[doc = "0x30 - GPIO_PIN2"] - #[inline(always)] - pub const fn gpio_pin2(&self) -> &GPIO_PIN2 { - &self.gpio_pin2 - } - #[doc = "0x34 - GPIO_PIN3"] - #[inline(always)] - pub const fn gpio_pin3(&self) -> &GPIO_PIN3 { - &self.gpio_pin3 - } - #[doc = "0x38 - GPIO_PIN4"] - #[inline(always)] - pub const fn gpio_pin4(&self) -> &GPIO_PIN4 { - &self.gpio_pin4 - } - #[doc = "0x3c - GPIO_PIN5"] - #[inline(always)] - pub const fn gpio_pin5(&self) -> &GPIO_PIN5 { - &self.gpio_pin5 - } - #[doc = "0x40 - GPIO_PIN6"] - #[inline(always)] - pub const fn gpio_pin6(&self) -> &GPIO_PIN6 { - &self.gpio_pin6 - } - #[doc = "0x44 - GPIO_PIN7"] - #[inline(always)] - pub const fn gpio_pin7(&self) -> &GPIO_PIN7 { - &self.gpio_pin7 - } - #[doc = "0x48 - GPIO_PIN8"] - #[inline(always)] - pub const fn gpio_pin8(&self) -> &GPIO_PIN8 { - &self.gpio_pin8 - } - #[doc = "0x4c - GPIO_PIN9"] - #[inline(always)] - pub const fn gpio_pin9(&self) -> &GPIO_PIN9 { - &self.gpio_pin9 - } - #[doc = "0x50 - GPIO_PIN10"] - #[inline(always)] - pub const fn gpio_pin10(&self) -> &GPIO_PIN10 { - &self.gpio_pin10 - } - #[doc = "0x54 - GPIO_PIN11"] - #[inline(always)] - pub const fn gpio_pin11(&self) -> &GPIO_PIN11 { - &self.gpio_pin11 - } - #[doc = "0x58 - GPIO_PIN12"] - #[inline(always)] - pub const fn gpio_pin12(&self) -> &GPIO_PIN12 { - &self.gpio_pin12 - } - #[doc = "0x5c - GPIO_PIN13"] - #[inline(always)] - pub const fn gpio_pin13(&self) -> &GPIO_PIN13 { - &self.gpio_pin13 - } - #[doc = "0x60 - GPIO_PIN14"] - #[inline(always)] - pub const fn gpio_pin14(&self) -> &GPIO_PIN14 { - &self.gpio_pin14 - } - #[doc = "0x64 - GPIO_PIN15"] - #[inline(always)] - pub const fn gpio_pin15(&self) -> &GPIO_PIN15 { - &self.gpio_pin15 - } - #[doc = "0x68 - GPIO_SIGMA_DELTA"] - #[inline(always)] - pub const fn gpio_sigma_delta(&self) -> &GPIO_SIGMA_DELTA { - &self.gpio_sigma_delta - } - #[doc = "0x6c - Positvie edge of this bit will trigger the RTC-clock-calibration process."] - #[inline(always)] - pub const fn gpio_rtc_calib_sync(&self) -> &GPIO_RTC_CALIB_SYNC { - &self.gpio_rtc_calib_sync - } - #[doc = "0x70 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] - #[inline(always)] - pub const fn gpio_rtc_calib_value(&self) -> &GPIO_RTC_CALIB_VALUE { - &self.gpio_rtc_calib_value - } -} -#[doc = "GPIO_OUT (rw) register accessor: BT-Coexist Selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_out`] module"] -pub type GPIO_OUT = crate::Reg; -#[doc = "BT-Coexist Selection register"] -pub mod gpio_out; -#[doc = "GPIO_OUT_W1TS (w) register accessor: GPIO_OUT_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_out_w1ts`] module"] -pub type GPIO_OUT_W1TS = crate::Reg; -#[doc = "GPIO_OUT_W1TS"] -pub mod gpio_out_w1ts; -#[doc = "GPIO_OUT_W1TC (w) register accessor: GPIO_OUT_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_out_w1tc`] module"] -pub type GPIO_OUT_W1TC = crate::Reg; -#[doc = "GPIO_OUT_W1TC"] -pub mod gpio_out_w1tc; -#[doc = "GPIO_ENABLE (rw) register accessor: GPIO_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_enable`] module"] -pub type GPIO_ENABLE = crate::Reg; -#[doc = "GPIO_ENABLE"] -pub mod gpio_enable; -#[doc = "GPIO_ENABLE_W1TS (w) register accessor: GPIO_ENABLE_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_enable_w1ts`] module"] -pub type GPIO_ENABLE_W1TS = crate::Reg; -#[doc = "GPIO_ENABLE_W1TS"] -pub mod gpio_enable_w1ts; -#[doc = "GPIO_ENABLE_W1TC (w) register accessor: GPIO_ENABLE_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_enable_w1tc`] module"] -pub type GPIO_ENABLE_W1TC = crate::Reg; -#[doc = "GPIO_ENABLE_W1TC"] -pub mod gpio_enable_w1tc; -#[doc = "GPIO_IN (rw) register accessor: The values of the strapping pins.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_in`] module"] -pub type GPIO_IN = crate::Reg; -#[doc = "The values of the strapping pins."] -pub mod gpio_in; -#[doc = "GPIO_STATUS (rw) register accessor: GPIO_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_status`] module"] -pub type GPIO_STATUS = crate::Reg; -#[doc = "GPIO_STATUS"] -pub mod gpio_status; -#[doc = "GPIO_STATUS_W1TS (w) register accessor: GPIO_STATUS_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_status_w1ts`] module"] -pub type GPIO_STATUS_W1TS = crate::Reg; -#[doc = "GPIO_STATUS_W1TS"] -pub mod gpio_status_w1ts; -#[doc = "GPIO_STATUS_W1TC (w) register accessor: GPIO_STATUS_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_status_w1tc`] module"] -pub type GPIO_STATUS_W1TC = crate::Reg; -#[doc = "GPIO_STATUS_W1TC"] -pub mod gpio_status_w1tc; -#[doc = "GPIO_PIN0 (rw) register accessor: GPIO_PIN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin0`] module"] -pub type GPIO_PIN0 = crate::Reg; -#[doc = "GPIO_PIN0"] -pub mod gpio_pin0; -#[doc = "GPIO_PIN1 (rw) register accessor: GPIO_PIN1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin1`] module"] -pub type GPIO_PIN1 = crate::Reg; -#[doc = "GPIO_PIN1"] -pub mod gpio_pin1; -#[doc = "GPIO_PIN2 (rw) register accessor: GPIO_PIN2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin2`] module"] -pub type GPIO_PIN2 = crate::Reg; -#[doc = "GPIO_PIN2"] -pub mod gpio_pin2; -#[doc = "GPIO_PIN3 (rw) register accessor: GPIO_PIN3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin3`] module"] -pub type GPIO_PIN3 = crate::Reg; -#[doc = "GPIO_PIN3"] -pub mod gpio_pin3; -#[doc = "GPIO_PIN4 (rw) register accessor: GPIO_PIN4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin4`] module"] -pub type GPIO_PIN4 = crate::Reg; -#[doc = "GPIO_PIN4"] -pub mod gpio_pin4; -#[doc = "GPIO_PIN5 (rw) register accessor: GPIO_PIN5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin5`] module"] -pub type GPIO_PIN5 = crate::Reg; -#[doc = "GPIO_PIN5"] -pub mod gpio_pin5; -#[doc = "GPIO_PIN6 (rw) register accessor: GPIO_PIN6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin6`] module"] -pub type GPIO_PIN6 = crate::Reg; -#[doc = "GPIO_PIN6"] -pub mod gpio_pin6; -#[doc = "GPIO_PIN7 (rw) register accessor: GPIO_PIN7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin7`] module"] -pub type GPIO_PIN7 = crate::Reg; -#[doc = "GPIO_PIN7"] -pub mod gpio_pin7; -#[doc = "GPIO_PIN8 (rw) register accessor: GPIO_PIN8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin8`] module"] -pub type GPIO_PIN8 = crate::Reg; -#[doc = "GPIO_PIN8"] -pub mod gpio_pin8; -#[doc = "GPIO_PIN9 (rw) register accessor: GPIO_PIN9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin9`] module"] -pub type GPIO_PIN9 = crate::Reg; -#[doc = "GPIO_PIN9"] -pub mod gpio_pin9; -#[doc = "GPIO_PIN10 (rw) register accessor: GPIO_PIN10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin10`] module"] -pub type GPIO_PIN10 = crate::Reg; -#[doc = "GPIO_PIN10"] -pub mod gpio_pin10; -#[doc = "GPIO_PIN11 (rw) register accessor: GPIO_PIN11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin11`] module"] -pub type GPIO_PIN11 = crate::Reg; -#[doc = "GPIO_PIN11"] -pub mod gpio_pin11; -#[doc = "GPIO_PIN12 (rw) register accessor: GPIO_PIN12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin12`] module"] -pub type GPIO_PIN12 = crate::Reg; -#[doc = "GPIO_PIN12"] -pub mod gpio_pin12; -#[doc = "GPIO_PIN13 (rw) register accessor: GPIO_PIN13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin13`] module"] -pub type GPIO_PIN13 = crate::Reg; -#[doc = "GPIO_PIN13"] -pub mod gpio_pin13; -#[doc = "GPIO_PIN14 (rw) register accessor: GPIO_PIN14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin14`] module"] -pub type GPIO_PIN14 = crate::Reg; -#[doc = "GPIO_PIN14"] -pub mod gpio_pin14; -#[doc = "GPIO_PIN15 (rw) register accessor: GPIO_PIN15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pin15`] module"] -pub type GPIO_PIN15 = crate::Reg; -#[doc = "GPIO_PIN15"] -pub mod gpio_pin15; -#[doc = "GPIO_SIGMA_DELTA (rw) register accessor: GPIO_SIGMA_DELTA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_sigma_delta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_sigma_delta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sigma_delta`] module"] -pub type GPIO_SIGMA_DELTA = crate::Reg; -#[doc = "GPIO_SIGMA_DELTA"] -pub mod gpio_sigma_delta; -#[doc = "GPIO_RTC_CALIB_SYNC (rw) register accessor: Positvie edge of this bit will trigger the RTC-clock-calibration process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_rtc_calib_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_rtc_calib_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_rtc_calib_sync`] module"] -pub type GPIO_RTC_CALIB_SYNC = crate::Reg; -#[doc = "Positvie edge of this bit will trigger the RTC-clock-calibration process."] -pub mod gpio_rtc_calib_sync; -#[doc = "GPIO_RTC_CALIB_VALUE (rw) register accessor: 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_rtc_calib_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_rtc_calib_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_rtc_calib_value`] module"] -pub type GPIO_RTC_CALIB_VALUE = crate::Reg; -#[doc = "0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] -pub mod gpio_rtc_calib_value; diff --git a/esp8266/src/gpio/gpio_enable.rs b/esp8266/src/gpio/gpio_enable.rs deleted file mode 100644 index fb79821c79..0000000000 --- a/esp8266/src/gpio/gpio_enable.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `GPIO_ENABLE` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_ENABLE` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_ENABLE_DATA` reader - The output enable register."] -pub type GPIO_ENABLE_DATA_R = crate::FieldReader; -#[doc = "Field `GPIO_ENABLE_DATA` writer - The output enable register."] -pub type GPIO_ENABLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `GPIO_SDIO_SEL` reader - SDIO-dis selection register"] -pub type GPIO_SDIO_SEL_R = crate::FieldReader; -#[doc = "Field `GPIO_SDIO_SEL` writer - SDIO-dis selection register"] -pub type GPIO_SDIO_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:15 - The output enable register."] - #[inline(always)] - pub fn gpio_enable_data(&self) -> GPIO_ENABLE_DATA_R { - GPIO_ENABLE_DATA_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:21 - SDIO-dis selection register"] - #[inline(always)] - pub fn gpio_sdio_sel(&self) -> GPIO_SDIO_SEL_R { - GPIO_SDIO_SEL_R::new(((self.bits >> 16) & 0x3f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_ENABLE") - .field( - "gpio_sdio_sel", - &format_args!("{}", self.gpio_sdio_sel().bits()), - ) - .field( - "gpio_enable_data", - &format_args!("{}", self.gpio_enable_data().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - The output enable register."] - #[inline(always)] - #[must_use] - pub fn gpio_enable_data(&mut self) -> GPIO_ENABLE_DATA_W { - GPIO_ENABLE_DATA_W::new(self, 0) - } - #[doc = "Bits 16:21 - SDIO-dis selection register"] - #[inline(always)] - #[must_use] - pub fn gpio_sdio_sel(&mut self) -> GPIO_SDIO_SEL_W { - GPIO_SDIO_SEL_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_ENABLE_SPEC; -impl crate::RegisterSpec for GPIO_ENABLE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_enable::R`](R) reader structure"] -impl crate::Readable for GPIO_ENABLE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_enable::W`](W) writer structure"] -impl crate::Writable for GPIO_ENABLE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_ENABLE to value 0"] -impl crate::Resettable for GPIO_ENABLE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_enable_w1tc.rs b/esp8266/src/gpio/gpio_enable_w1tc.rs deleted file mode 100644 index 4e2370404c..0000000000 --- a/esp8266/src/gpio/gpio_enable_w1tc.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `GPIO_ENABLE_W1TC` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_ENABLE_DATA_W1TC` writer - Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA"] -pub type GPIO_ENABLE_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_enable_data_w1tc(&mut self) -> GPIO_ENABLE_DATA_W1TC_W { - GPIO_ENABLE_DATA_W1TC_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_ENABLE_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_ENABLE_W1TC_SPEC; -impl crate::RegisterSpec for GPIO_ENABLE_W1TC_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_enable_w1tc::W`](W) writer structure"] -impl crate::Writable for GPIO_ENABLE_W1TC_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_ENABLE_W1TC to value 0"] -impl crate::Resettable for GPIO_ENABLE_W1TC_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_enable_w1ts.rs b/esp8266/src/gpio/gpio_enable_w1ts.rs deleted file mode 100644 index fc64630141..0000000000 --- a/esp8266/src/gpio/gpio_enable_w1ts.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `GPIO_ENABLE_W1TS` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_ENABLE_DATA_W1TS` writer - Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA"] -pub type GPIO_ENABLE_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_enable_data_w1ts(&mut self) -> GPIO_ENABLE_DATA_W1TS_W { - GPIO_ENABLE_DATA_W1TS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_ENABLE_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_ENABLE_W1TS_SPEC; -impl crate::RegisterSpec for GPIO_ENABLE_W1TS_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_enable_w1ts::W`](W) writer structure"] -impl crate::Writable for GPIO_ENABLE_W1TS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_ENABLE_W1TS to value 0"] -impl crate::Resettable for GPIO_ENABLE_W1TS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_in.rs b/esp8266/src/gpio/gpio_in.rs deleted file mode 100644 index 6e74e1b410..0000000000 --- a/esp8266/src/gpio/gpio_in.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `GPIO_IN` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_IN` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_IN_DATA` reader - The values of the GPIO pins when the GPIO pin is set as input."] -pub type GPIO_IN_DATA_R = crate::FieldReader; -#[doc = "Field `GPIO_IN_DATA` writer - The values of the GPIO pins when the GPIO pin is set as input."] -pub type GPIO_IN_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `GPIO_STRAPPING` reader - The values of the strapping pins."] -pub type GPIO_STRAPPING_R = crate::FieldReader; -#[doc = "Field `GPIO_STRAPPING` writer - The values of the strapping pins."] -pub type GPIO_STRAPPING_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - The values of the GPIO pins when the GPIO pin is set as input."] - #[inline(always)] - pub fn gpio_in_data(&self) -> GPIO_IN_DATA_R { - GPIO_IN_DATA_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - The values of the strapping pins."] - #[inline(always)] - pub fn gpio_strapping(&self) -> GPIO_STRAPPING_R { - GPIO_STRAPPING_R::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_IN") - .field( - "gpio_strapping", - &format_args!("{}", self.gpio_strapping().bits()), - ) - .field( - "gpio_in_data", - &format_args!("{}", self.gpio_in_data().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - The values of the GPIO pins when the GPIO pin is set as input."] - #[inline(always)] - #[must_use] - pub fn gpio_in_data(&mut self) -> GPIO_IN_DATA_W { - GPIO_IN_DATA_W::new(self, 0) - } - #[doc = "Bits 16:31 - The values of the strapping pins."] - #[inline(always)] - #[must_use] - pub fn gpio_strapping(&mut self) -> GPIO_STRAPPING_W { - GPIO_STRAPPING_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The values of the strapping pins.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_IN_SPEC; -impl crate::RegisterSpec for GPIO_IN_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_in::R`](R) reader structure"] -impl crate::Readable for GPIO_IN_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_in::W`](W) writer structure"] -impl crate::Writable for GPIO_IN_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_IN to value 0"] -impl crate::Resettable for GPIO_IN_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_out.rs b/esp8266/src/gpio/gpio_out.rs deleted file mode 100644 index aef5d463e6..0000000000 --- a/esp8266/src/gpio/gpio_out.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `GPIO_OUT` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_OUT` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_OUT_DATA` reader - The output value when the GPIO pin is set as output."] -pub type GPIO_OUT_DATA_R = crate::FieldReader; -#[doc = "Field `GPIO_OUT_DATA` writer - The output value when the GPIO pin is set as output."] -pub type GPIO_OUT_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `GPIO_BT_SEL` reader - BT-Coexist Selection register"] -pub type GPIO_BT_SEL_R = crate::FieldReader; -#[doc = "Field `GPIO_BT_SEL` writer - BT-Coexist Selection register"] -pub type GPIO_BT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - The output value when the GPIO pin is set as output."] - #[inline(always)] - pub fn gpio_out_data(&self) -> GPIO_OUT_DATA_R { - GPIO_OUT_DATA_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:31 - BT-Coexist Selection register"] - #[inline(always)] - pub fn gpio_bt_sel(&self) -> GPIO_BT_SEL_R { - GPIO_BT_SEL_R::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_OUT") - .field( - "gpio_bt_sel", - &format_args!("{}", self.gpio_bt_sel().bits()), - ) - .field( - "gpio_out_data", - &format_args!("{}", self.gpio_out_data().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - The output value when the GPIO pin is set as output."] - #[inline(always)] - #[must_use] - pub fn gpio_out_data(&mut self) -> GPIO_OUT_DATA_W { - GPIO_OUT_DATA_W::new(self, 0) - } - #[doc = "Bits 16:31 - BT-Coexist Selection register"] - #[inline(always)] - #[must_use] - pub fn gpio_bt_sel(&mut self) -> GPIO_BT_SEL_W { - GPIO_BT_SEL_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "BT-Coexist Selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_OUT_SPEC; -impl crate::RegisterSpec for GPIO_OUT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_out::R`](R) reader structure"] -impl crate::Readable for GPIO_OUT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_out::W`](W) writer structure"] -impl crate::Writable for GPIO_OUT_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_OUT to value 0"] -impl crate::Resettable for GPIO_OUT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_out_w1tc.rs b/esp8266/src/gpio/gpio_out_w1tc.rs deleted file mode 100644 index c3e85c0c09..0000000000 --- a/esp8266/src/gpio/gpio_out_w1tc.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `GPIO_OUT_W1TC` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_OUT_DATA_W1TC` writer - Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA"] -pub type GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_out_data_w1tc(&mut self) -> GPIO_OUT_DATA_W1TC_W { - GPIO_OUT_DATA_W1TC_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_OUT_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_OUT_W1TC_SPEC; -impl crate::RegisterSpec for GPIO_OUT_W1TC_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_out_w1tc::W`](W) writer structure"] -impl crate::Writable for GPIO_OUT_W1TC_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_OUT_W1TC to value 0"] -impl crate::Resettable for GPIO_OUT_W1TC_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_out_w1ts.rs b/esp8266/src/gpio/gpio_out_w1ts.rs deleted file mode 100644 index d2a6f8b357..0000000000 --- a/esp8266/src/gpio/gpio_out_w1ts.rs +++ /dev/null @@ -1,42 +0,0 @@ -#[doc = "Register `GPIO_OUT_W1TS` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_OUT_DATA_W1TS` writer - Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA"] -pub type GPIO_OUT_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_out_data_w1ts(&mut self) -> GPIO_OUT_DATA_W1TS_W { - GPIO_OUT_DATA_W1TS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_OUT_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_OUT_W1TS_SPEC; -impl crate::RegisterSpec for GPIO_OUT_W1TS_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_out_w1ts::W`](W) writer structure"] -impl crate::Writable for GPIO_OUT_W1TS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_OUT_W1TS to value 0"] -impl crate::Resettable for GPIO_OUT_W1TS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin0.rs b/esp8266/src/gpio/gpio_pin0.rs deleted file mode 100644 index ac75e9e382..0000000000 --- a/esp8266/src/gpio/gpio_pin0.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN0` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN0` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN0_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN0_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN0_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN0_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN0_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN0_SOURCE_A { - match self.bits { - false => GPIO_PIN0_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN0_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN0_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN0_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN0_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN0_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN0_SOURCE_A>; -impl<'a, REG> GPIO_PIN0_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN0_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN0_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN0_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN0_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN0_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN0_DRIVER_A { - match self.bits { - false => GPIO_PIN0_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN0_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN0_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN0_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN0_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN0_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN0_DRIVER_A>; -impl<'a, REG> GPIO_PIN0_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN0_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN0_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN0_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN0_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN0_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN0_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN0_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN0_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN0_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN0_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN0_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN0_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN0_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN0_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN0_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN0_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN0_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN0_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN0_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN0_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN0_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN0_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin0_source(&self) -> GPIO_PIN0_SOURCE_R { - GPIO_PIN0_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin0_driver(&self) -> GPIO_PIN0_DRIVER_R { - GPIO_PIN0_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin0_int_type(&self) -> GPIO_PIN0_INT_TYPE_R { - GPIO_PIN0_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin0_wakeup_enable(&self) -> GPIO_PIN0_WAKEUP_ENABLE_R { - GPIO_PIN0_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN0") - .field( - "gpio_pin0_wakeup_enable", - &format_args!("{}", self.gpio_pin0_wakeup_enable().bit()), - ) - .field( - "gpio_pin0_int_type", - &format_args!("{}", self.gpio_pin0_int_type().bits()), - ) - .field( - "gpio_pin0_driver", - &format_args!("{}", self.gpio_pin0_driver().bit()), - ) - .field( - "gpio_pin0_source", - &format_args!("{}", self.gpio_pin0_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin0_source(&mut self) -> GPIO_PIN0_SOURCE_W { - GPIO_PIN0_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin0_driver(&mut self) -> GPIO_PIN0_DRIVER_W { - GPIO_PIN0_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin0_int_type(&mut self) -> GPIO_PIN0_INT_TYPE_W { - GPIO_PIN0_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin0_wakeup_enable(&mut self) -> GPIO_PIN0_WAKEUP_ENABLE_W { - GPIO_PIN0_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN0_SPEC; -impl crate::RegisterSpec for GPIO_PIN0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin0::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin0::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN0 to value 0"] -impl crate::Resettable for GPIO_PIN0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin1.rs b/esp8266/src/gpio/gpio_pin1.rs deleted file mode 100644 index e7886d2510..0000000000 --- a/esp8266/src/gpio/gpio_pin1.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN1` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN1` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN1_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN1_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN1_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN1_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN1_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN1_SOURCE_A { - match self.bits { - false => GPIO_PIN1_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN1_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN1_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN1_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN1_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN1_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN1_SOURCE_A>; -impl<'a, REG> GPIO_PIN1_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN1_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN1_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN1_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN1_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN1_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN1_DRIVER_A { - match self.bits { - false => GPIO_PIN1_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN1_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN1_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN1_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN1_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN1_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN1_DRIVER_A>; -impl<'a, REG> GPIO_PIN1_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN1_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN1_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN1_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN1_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN1_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN1_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN1_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN1_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN1_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN1_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN1_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN1_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN1_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN1_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN1_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN1_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN1_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN1_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN1_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN1_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN1_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN1_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin1_source(&self) -> GPIO_PIN1_SOURCE_R { - GPIO_PIN1_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin1_driver(&self) -> GPIO_PIN1_DRIVER_R { - GPIO_PIN1_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin1_int_type(&self) -> GPIO_PIN1_INT_TYPE_R { - GPIO_PIN1_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin1_wakeup_enable(&self) -> GPIO_PIN1_WAKEUP_ENABLE_R { - GPIO_PIN1_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN1") - .field( - "gpio_pin1_wakeup_enable", - &format_args!("{}", self.gpio_pin1_wakeup_enable().bit()), - ) - .field( - "gpio_pin1_int_type", - &format_args!("{}", self.gpio_pin1_int_type().bits()), - ) - .field( - "gpio_pin1_driver", - &format_args!("{}", self.gpio_pin1_driver().bit()), - ) - .field( - "gpio_pin1_source", - &format_args!("{}", self.gpio_pin1_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin1_source(&mut self) -> GPIO_PIN1_SOURCE_W { - GPIO_PIN1_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin1_driver(&mut self) -> GPIO_PIN1_DRIVER_W { - GPIO_PIN1_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin1_int_type(&mut self) -> GPIO_PIN1_INT_TYPE_W { - GPIO_PIN1_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin1_wakeup_enable(&mut self) -> GPIO_PIN1_WAKEUP_ENABLE_W { - GPIO_PIN1_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN1_SPEC; -impl crate::RegisterSpec for GPIO_PIN1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin1::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin1::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN1 to value 0"] -impl crate::Resettable for GPIO_PIN1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin10.rs b/esp8266/src/gpio/gpio_pin10.rs deleted file mode 100644 index e986230f0b..0000000000 --- a/esp8266/src/gpio/gpio_pin10.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN10` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN10` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN10_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN10_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN10_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN10_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN10_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN10_SOURCE_A { - match self.bits { - false => GPIO_PIN10_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN10_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN10_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN10_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN10_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN10_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN10_SOURCE_A>; -impl<'a, REG> GPIO_PIN10_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN10_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN10_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN10_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN10_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN10_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN10_DRIVER_A { - match self.bits { - false => GPIO_PIN10_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN10_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN10_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN10_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN10_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN10_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN10_DRIVER_A>; -impl<'a, REG> GPIO_PIN10_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN10_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN10_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN10_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN10_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN10_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN10_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN10_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN10_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN10_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN10_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN10_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN10_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN10_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN10_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN10_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN10_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN10_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN10_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN10_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN10_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN10_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN10_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin10_source(&self) -> GPIO_PIN10_SOURCE_R { - GPIO_PIN10_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin10_driver(&self) -> GPIO_PIN10_DRIVER_R { - GPIO_PIN10_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin10_int_type(&self) -> GPIO_PIN10_INT_TYPE_R { - GPIO_PIN10_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin10_wakeup_enable(&self) -> GPIO_PIN10_WAKEUP_ENABLE_R { - GPIO_PIN10_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN10") - .field( - "gpio_pin10_wakeup_enable", - &format_args!("{}", self.gpio_pin10_wakeup_enable().bit()), - ) - .field( - "gpio_pin10_int_type", - &format_args!("{}", self.gpio_pin10_int_type().bits()), - ) - .field( - "gpio_pin10_driver", - &format_args!("{}", self.gpio_pin10_driver().bit()), - ) - .field( - "gpio_pin10_source", - &format_args!("{}", self.gpio_pin10_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin10_source(&mut self) -> GPIO_PIN10_SOURCE_W { - GPIO_PIN10_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin10_driver(&mut self) -> GPIO_PIN10_DRIVER_W { - GPIO_PIN10_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin10_int_type(&mut self) -> GPIO_PIN10_INT_TYPE_W { - GPIO_PIN10_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin10_wakeup_enable(&mut self) -> GPIO_PIN10_WAKEUP_ENABLE_W { - GPIO_PIN10_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN10_SPEC; -impl crate::RegisterSpec for GPIO_PIN10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin10::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin10::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN10_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN10 to value 0"] -impl crate::Resettable for GPIO_PIN10_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin11.rs b/esp8266/src/gpio/gpio_pin11.rs deleted file mode 100644 index 5feb3a00a0..0000000000 --- a/esp8266/src/gpio/gpio_pin11.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN11` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN11` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN11_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN11_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN11_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN11_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN11_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN11_SOURCE_A { - match self.bits { - false => GPIO_PIN11_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN11_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN11_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN11_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN11_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN11_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN11_SOURCE_A>; -impl<'a, REG> GPIO_PIN11_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN11_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN11_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN11_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN11_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN11_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN11_DRIVER_A { - match self.bits { - false => GPIO_PIN11_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN11_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN11_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN11_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN11_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN11_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN11_DRIVER_A>; -impl<'a, REG> GPIO_PIN11_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN11_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN11_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN11_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN11_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN11_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN11_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN11_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN11_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN11_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN11_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN11_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN11_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN11_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN11_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN11_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN11_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN11_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN11_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN11_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN11_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN11_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN11_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin11_source(&self) -> GPIO_PIN11_SOURCE_R { - GPIO_PIN11_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin11_driver(&self) -> GPIO_PIN11_DRIVER_R { - GPIO_PIN11_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin11_int_type(&self) -> GPIO_PIN11_INT_TYPE_R { - GPIO_PIN11_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin11_wakeup_enable(&self) -> GPIO_PIN11_WAKEUP_ENABLE_R { - GPIO_PIN11_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN11") - .field( - "gpio_pin11_wakeup_enable", - &format_args!("{}", self.gpio_pin11_wakeup_enable().bit()), - ) - .field( - "gpio_pin11_int_type", - &format_args!("{}", self.gpio_pin11_int_type().bits()), - ) - .field( - "gpio_pin11_driver", - &format_args!("{}", self.gpio_pin11_driver().bit()), - ) - .field( - "gpio_pin11_source", - &format_args!("{}", self.gpio_pin11_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin11_source(&mut self) -> GPIO_PIN11_SOURCE_W { - GPIO_PIN11_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin11_driver(&mut self) -> GPIO_PIN11_DRIVER_W { - GPIO_PIN11_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin11_int_type(&mut self) -> GPIO_PIN11_INT_TYPE_W { - GPIO_PIN11_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin11_wakeup_enable(&mut self) -> GPIO_PIN11_WAKEUP_ENABLE_W { - GPIO_PIN11_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN11_SPEC; -impl crate::RegisterSpec for GPIO_PIN11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin11::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin11::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN11_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN11 to value 0"] -impl crate::Resettable for GPIO_PIN11_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin12.rs b/esp8266/src/gpio/gpio_pin12.rs deleted file mode 100644 index fe5fa43163..0000000000 --- a/esp8266/src/gpio/gpio_pin12.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN12` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN12` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN12_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN12_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN12_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN12_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN12_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN12_SOURCE_A { - match self.bits { - false => GPIO_PIN12_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN12_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN12_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN12_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN12_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN12_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN12_SOURCE_A>; -impl<'a, REG> GPIO_PIN12_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN12_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN12_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN12_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN12_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN12_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN12_DRIVER_A { - match self.bits { - false => GPIO_PIN12_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN12_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN12_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN12_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN12_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN12_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN12_DRIVER_A>; -impl<'a, REG> GPIO_PIN12_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN12_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN12_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN12_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN12_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN12_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN12_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN12_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN12_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN12_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN12_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN12_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN12_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN12_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN12_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN12_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN12_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN12_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN12_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN12_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN12_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN12_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN12_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin12_source(&self) -> GPIO_PIN12_SOURCE_R { - GPIO_PIN12_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin12_driver(&self) -> GPIO_PIN12_DRIVER_R { - GPIO_PIN12_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin12_int_type(&self) -> GPIO_PIN12_INT_TYPE_R { - GPIO_PIN12_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin12_wakeup_enable(&self) -> GPIO_PIN12_WAKEUP_ENABLE_R { - GPIO_PIN12_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN12") - .field( - "gpio_pin12_wakeup_enable", - &format_args!("{}", self.gpio_pin12_wakeup_enable().bit()), - ) - .field( - "gpio_pin12_int_type", - &format_args!("{}", self.gpio_pin12_int_type().bits()), - ) - .field( - "gpio_pin12_driver", - &format_args!("{}", self.gpio_pin12_driver().bit()), - ) - .field( - "gpio_pin12_source", - &format_args!("{}", self.gpio_pin12_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin12_source(&mut self) -> GPIO_PIN12_SOURCE_W { - GPIO_PIN12_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin12_driver(&mut self) -> GPIO_PIN12_DRIVER_W { - GPIO_PIN12_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin12_int_type(&mut self) -> GPIO_PIN12_INT_TYPE_W { - GPIO_PIN12_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin12_wakeup_enable(&mut self) -> GPIO_PIN12_WAKEUP_ENABLE_W { - GPIO_PIN12_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN12_SPEC; -impl crate::RegisterSpec for GPIO_PIN12_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin12::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN12_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin12::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN12_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN12 to value 0"] -impl crate::Resettable for GPIO_PIN12_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin13.rs b/esp8266/src/gpio/gpio_pin13.rs deleted file mode 100644 index db1cfc8c27..0000000000 --- a/esp8266/src/gpio/gpio_pin13.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN13` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN13` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN13_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN13_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN13_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN13_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN13_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN13_SOURCE_A { - match self.bits { - false => GPIO_PIN13_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN13_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN13_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN13_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN13_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN13_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN13_SOURCE_A>; -impl<'a, REG> GPIO_PIN13_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN13_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN13_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN13_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN13_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN13_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN13_DRIVER_A { - match self.bits { - false => GPIO_PIN13_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN13_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN13_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN13_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN13_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN13_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN13_DRIVER_A>; -impl<'a, REG> GPIO_PIN13_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN13_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN13_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN13_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN13_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN13_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN13_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN13_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN13_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN13_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN13_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN13_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN13_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN13_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN13_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN13_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN13_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN13_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN13_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN13_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN13_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN13_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN13_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin13_source(&self) -> GPIO_PIN13_SOURCE_R { - GPIO_PIN13_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin13_driver(&self) -> GPIO_PIN13_DRIVER_R { - GPIO_PIN13_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin13_int_type(&self) -> GPIO_PIN13_INT_TYPE_R { - GPIO_PIN13_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin13_wakeup_enable(&self) -> GPIO_PIN13_WAKEUP_ENABLE_R { - GPIO_PIN13_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN13") - .field( - "gpio_pin13_wakeup_enable", - &format_args!("{}", self.gpio_pin13_wakeup_enable().bit()), - ) - .field( - "gpio_pin13_int_type", - &format_args!("{}", self.gpio_pin13_int_type().bits()), - ) - .field( - "gpio_pin13_driver", - &format_args!("{}", self.gpio_pin13_driver().bit()), - ) - .field( - "gpio_pin13_source", - &format_args!("{}", self.gpio_pin13_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin13_source(&mut self) -> GPIO_PIN13_SOURCE_W { - GPIO_PIN13_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin13_driver(&mut self) -> GPIO_PIN13_DRIVER_W { - GPIO_PIN13_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin13_int_type(&mut self) -> GPIO_PIN13_INT_TYPE_W { - GPIO_PIN13_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin13_wakeup_enable(&mut self) -> GPIO_PIN13_WAKEUP_ENABLE_W { - GPIO_PIN13_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN13_SPEC; -impl crate::RegisterSpec for GPIO_PIN13_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin13::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN13_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin13::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN13_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN13 to value 0"] -impl crate::Resettable for GPIO_PIN13_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin14.rs b/esp8266/src/gpio/gpio_pin14.rs deleted file mode 100644 index 517e3e60e3..0000000000 --- a/esp8266/src/gpio/gpio_pin14.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN14` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN14` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN14_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN14_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN14_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN14_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN14_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN14_SOURCE_A { - match self.bits { - false => GPIO_PIN14_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN14_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN14_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN14_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN14_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN14_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN14_SOURCE_A>; -impl<'a, REG> GPIO_PIN14_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN14_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN14_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN14_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN14_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN14_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN14_DRIVER_A { - match self.bits { - false => GPIO_PIN14_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN14_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN14_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN14_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN14_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN14_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN14_DRIVER_A>; -impl<'a, REG> GPIO_PIN14_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN14_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN14_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN14_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN14_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN14_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN14_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN14_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN14_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN14_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN14_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN14_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN14_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN14_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN14_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN14_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN14_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN14_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN14_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN14_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN14_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN14_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN14_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin14_source(&self) -> GPIO_PIN14_SOURCE_R { - GPIO_PIN14_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin14_driver(&self) -> GPIO_PIN14_DRIVER_R { - GPIO_PIN14_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin14_int_type(&self) -> GPIO_PIN14_INT_TYPE_R { - GPIO_PIN14_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin14_wakeup_enable(&self) -> GPIO_PIN14_WAKEUP_ENABLE_R { - GPIO_PIN14_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN14") - .field( - "gpio_pin14_wakeup_enable", - &format_args!("{}", self.gpio_pin14_wakeup_enable().bit()), - ) - .field( - "gpio_pin14_int_type", - &format_args!("{}", self.gpio_pin14_int_type().bits()), - ) - .field( - "gpio_pin14_driver", - &format_args!("{}", self.gpio_pin14_driver().bit()), - ) - .field( - "gpio_pin14_source", - &format_args!("{}", self.gpio_pin14_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin14_source(&mut self) -> GPIO_PIN14_SOURCE_W { - GPIO_PIN14_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin14_driver(&mut self) -> GPIO_PIN14_DRIVER_W { - GPIO_PIN14_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin14_int_type(&mut self) -> GPIO_PIN14_INT_TYPE_W { - GPIO_PIN14_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin14_wakeup_enable(&mut self) -> GPIO_PIN14_WAKEUP_ENABLE_W { - GPIO_PIN14_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN14_SPEC; -impl crate::RegisterSpec for GPIO_PIN14_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin14::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN14_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin14::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN14_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN14 to value 0"] -impl crate::Resettable for GPIO_PIN14_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin15.rs b/esp8266/src/gpio/gpio_pin15.rs deleted file mode 100644 index efc33c4433..0000000000 --- a/esp8266/src/gpio/gpio_pin15.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN15` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN15` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN15_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN15_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN15_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN15_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN15_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN15_SOURCE_A { - match self.bits { - false => GPIO_PIN15_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN15_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN15_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN15_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN15_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN15_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN15_SOURCE_A>; -impl<'a, REG> GPIO_PIN15_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN15_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN15_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN15_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN15_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN15_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN15_DRIVER_A { - match self.bits { - false => GPIO_PIN15_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN15_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN15_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN15_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN15_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN15_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN15_DRIVER_A>; -impl<'a, REG> GPIO_PIN15_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN15_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN15_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN15_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN15_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN15_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN15_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN15_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN15_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN15_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN15_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN15_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN15_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN15_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN15_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN15_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN15_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN15_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN15_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN15_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN15_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN15_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN15_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin15_source(&self) -> GPIO_PIN15_SOURCE_R { - GPIO_PIN15_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin15_driver(&self) -> GPIO_PIN15_DRIVER_R { - GPIO_PIN15_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin15_int_type(&self) -> GPIO_PIN15_INT_TYPE_R { - GPIO_PIN15_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin15_wakeup_enable(&self) -> GPIO_PIN15_WAKEUP_ENABLE_R { - GPIO_PIN15_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN15") - .field( - "gpio_pin15_wakeup_enable", - &format_args!("{}", self.gpio_pin15_wakeup_enable().bit()), - ) - .field( - "gpio_pin15_int_type", - &format_args!("{}", self.gpio_pin15_int_type().bits()), - ) - .field( - "gpio_pin15_driver", - &format_args!("{}", self.gpio_pin15_driver().bit()), - ) - .field( - "gpio_pin15_source", - &format_args!("{}", self.gpio_pin15_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin15_source(&mut self) -> GPIO_PIN15_SOURCE_W { - GPIO_PIN15_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin15_driver(&mut self) -> GPIO_PIN15_DRIVER_W { - GPIO_PIN15_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin15_int_type(&mut self) -> GPIO_PIN15_INT_TYPE_W { - GPIO_PIN15_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin15_wakeup_enable(&mut self) -> GPIO_PIN15_WAKEUP_ENABLE_W { - GPIO_PIN15_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN15_SPEC; -impl crate::RegisterSpec for GPIO_PIN15_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin15::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN15_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin15::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN15_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN15 to value 0"] -impl crate::Resettable for GPIO_PIN15_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin2.rs b/esp8266/src/gpio/gpio_pin2.rs deleted file mode 100644 index 1c95f006bf..0000000000 --- a/esp8266/src/gpio/gpio_pin2.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN2` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN2` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN2_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN2_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN2_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN2_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN2_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN2_SOURCE_A { - match self.bits { - false => GPIO_PIN2_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN2_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN2_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN2_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN2_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN2_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN2_SOURCE_A>; -impl<'a, REG> GPIO_PIN2_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN2_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN2_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN2_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN2_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN2_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN2_DRIVER_A { - match self.bits { - false => GPIO_PIN2_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN2_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN2_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN2_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN2_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN2_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN2_DRIVER_A>; -impl<'a, REG> GPIO_PIN2_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN2_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN2_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN2_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN2_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN2_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN2_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN2_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN2_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN2_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN2_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN2_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN2_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN2_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN2_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN2_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN2_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN2_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN2_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN2_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN2_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN2_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN2_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin2_source(&self) -> GPIO_PIN2_SOURCE_R { - GPIO_PIN2_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin2_driver(&self) -> GPIO_PIN2_DRIVER_R { - GPIO_PIN2_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin2_int_type(&self) -> GPIO_PIN2_INT_TYPE_R { - GPIO_PIN2_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin2_wakeup_enable(&self) -> GPIO_PIN2_WAKEUP_ENABLE_R { - GPIO_PIN2_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN2") - .field( - "gpio_pin2_wakeup_enable", - &format_args!("{}", self.gpio_pin2_wakeup_enable().bit()), - ) - .field( - "gpio_pin2_int_type", - &format_args!("{}", self.gpio_pin2_int_type().bits()), - ) - .field( - "gpio_pin2_driver", - &format_args!("{}", self.gpio_pin2_driver().bit()), - ) - .field( - "gpio_pin2_source", - &format_args!("{}", self.gpio_pin2_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin2_source(&mut self) -> GPIO_PIN2_SOURCE_W { - GPIO_PIN2_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin2_driver(&mut self) -> GPIO_PIN2_DRIVER_W { - GPIO_PIN2_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin2_int_type(&mut self) -> GPIO_PIN2_INT_TYPE_W { - GPIO_PIN2_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin2_wakeup_enable(&mut self) -> GPIO_PIN2_WAKEUP_ENABLE_W { - GPIO_PIN2_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN2_SPEC; -impl crate::RegisterSpec for GPIO_PIN2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin2::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin2::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN2 to value 0"] -impl crate::Resettable for GPIO_PIN2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin3.rs b/esp8266/src/gpio/gpio_pin3.rs deleted file mode 100644 index b06b9b128b..0000000000 --- a/esp8266/src/gpio/gpio_pin3.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN3` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN3` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN3_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN3_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN3_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN3_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN3_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN3_SOURCE_A { - match self.bits { - false => GPIO_PIN3_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN3_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN3_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN3_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN3_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN3_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN3_SOURCE_A>; -impl<'a, REG> GPIO_PIN3_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN3_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN3_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN3_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN3_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN3_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN3_DRIVER_A { - match self.bits { - false => GPIO_PIN3_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN3_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN3_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN3_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN3_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN3_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN3_DRIVER_A>; -impl<'a, REG> GPIO_PIN3_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN3_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN3_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN3_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN3_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN3_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN3_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN3_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN3_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN3_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN3_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN3_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN3_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN3_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN3_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN3_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN3_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN3_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN3_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN3_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN3_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN3_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN3_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin3_source(&self) -> GPIO_PIN3_SOURCE_R { - GPIO_PIN3_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin3_driver(&self) -> GPIO_PIN3_DRIVER_R { - GPIO_PIN3_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin3_int_type(&self) -> GPIO_PIN3_INT_TYPE_R { - GPIO_PIN3_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin3_wakeup_enable(&self) -> GPIO_PIN3_WAKEUP_ENABLE_R { - GPIO_PIN3_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN3") - .field( - "gpio_pin3_wakeup_enable", - &format_args!("{}", self.gpio_pin3_wakeup_enable().bit()), - ) - .field( - "gpio_pin3_int_type", - &format_args!("{}", self.gpio_pin3_int_type().bits()), - ) - .field( - "gpio_pin3_driver", - &format_args!("{}", self.gpio_pin3_driver().bit()), - ) - .field( - "gpio_pin3_source", - &format_args!("{}", self.gpio_pin3_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin3_source(&mut self) -> GPIO_PIN3_SOURCE_W { - GPIO_PIN3_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin3_driver(&mut self) -> GPIO_PIN3_DRIVER_W { - GPIO_PIN3_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin3_int_type(&mut self) -> GPIO_PIN3_INT_TYPE_W { - GPIO_PIN3_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin3_wakeup_enable(&mut self) -> GPIO_PIN3_WAKEUP_ENABLE_W { - GPIO_PIN3_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN3_SPEC; -impl crate::RegisterSpec for GPIO_PIN3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin3::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin3::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN3 to value 0"] -impl crate::Resettable for GPIO_PIN3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin4.rs b/esp8266/src/gpio/gpio_pin4.rs deleted file mode 100644 index 0b94997635..0000000000 --- a/esp8266/src/gpio/gpio_pin4.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN4` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN4` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN4_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN4_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN4_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN4_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN4_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN4_SOURCE_A { - match self.bits { - false => GPIO_PIN4_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN4_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN4_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN4_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN4_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN4_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN4_SOURCE_A>; -impl<'a, REG> GPIO_PIN4_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN4_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN4_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN4_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN4_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN4_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN4_DRIVER_A { - match self.bits { - false => GPIO_PIN4_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN4_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN4_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN4_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN4_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN4_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN4_DRIVER_A>; -impl<'a, REG> GPIO_PIN4_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN4_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN4_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN4_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN4_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN4_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN4_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN4_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN4_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN4_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN4_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN4_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN4_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN4_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN4_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN4_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN4_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN4_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN4_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN4_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN4_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN4_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN4_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin4_source(&self) -> GPIO_PIN4_SOURCE_R { - GPIO_PIN4_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin4_driver(&self) -> GPIO_PIN4_DRIVER_R { - GPIO_PIN4_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin4_int_type(&self) -> GPIO_PIN4_INT_TYPE_R { - GPIO_PIN4_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin4_wakeup_enable(&self) -> GPIO_PIN4_WAKEUP_ENABLE_R { - GPIO_PIN4_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN4") - .field( - "gpio_pin4_wakeup_enable", - &format_args!("{}", self.gpio_pin4_wakeup_enable().bit()), - ) - .field( - "gpio_pin4_int_type", - &format_args!("{}", self.gpio_pin4_int_type().bits()), - ) - .field( - "gpio_pin4_driver", - &format_args!("{}", self.gpio_pin4_driver().bit()), - ) - .field( - "gpio_pin4_source", - &format_args!("{}", self.gpio_pin4_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin4_source(&mut self) -> GPIO_PIN4_SOURCE_W { - GPIO_PIN4_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin4_driver(&mut self) -> GPIO_PIN4_DRIVER_W { - GPIO_PIN4_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin4_int_type(&mut self) -> GPIO_PIN4_INT_TYPE_W { - GPIO_PIN4_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin4_wakeup_enable(&mut self) -> GPIO_PIN4_WAKEUP_ENABLE_W { - GPIO_PIN4_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN4_SPEC; -impl crate::RegisterSpec for GPIO_PIN4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin4::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin4::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN4 to value 0"] -impl crate::Resettable for GPIO_PIN4_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin5.rs b/esp8266/src/gpio/gpio_pin5.rs deleted file mode 100644 index a1b9ebfe93..0000000000 --- a/esp8266/src/gpio/gpio_pin5.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN5` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN5` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN5_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN5_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN5_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN5_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN5_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN5_SOURCE_A { - match self.bits { - false => GPIO_PIN5_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN5_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN5_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN5_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN5_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN5_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN5_SOURCE_A>; -impl<'a, REG> GPIO_PIN5_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN5_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN5_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN5_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN5_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN5_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN5_DRIVER_A { - match self.bits { - false => GPIO_PIN5_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN5_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN5_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN5_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN5_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN5_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN5_DRIVER_A>; -impl<'a, REG> GPIO_PIN5_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN5_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN5_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN5_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN5_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN5_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN5_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN5_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN5_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN5_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN5_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN5_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN5_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN5_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN5_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN5_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN5_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN5_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN5_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN5_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN5_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN5_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN5_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin5_source(&self) -> GPIO_PIN5_SOURCE_R { - GPIO_PIN5_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin5_driver(&self) -> GPIO_PIN5_DRIVER_R { - GPIO_PIN5_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin5_int_type(&self) -> GPIO_PIN5_INT_TYPE_R { - GPIO_PIN5_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin5_wakeup_enable(&self) -> GPIO_PIN5_WAKEUP_ENABLE_R { - GPIO_PIN5_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN5") - .field( - "gpio_pin5_wakeup_enable", - &format_args!("{}", self.gpio_pin5_wakeup_enable().bit()), - ) - .field( - "gpio_pin5_int_type", - &format_args!("{}", self.gpio_pin5_int_type().bits()), - ) - .field( - "gpio_pin5_driver", - &format_args!("{}", self.gpio_pin5_driver().bit()), - ) - .field( - "gpio_pin5_source", - &format_args!("{}", self.gpio_pin5_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin5_source(&mut self) -> GPIO_PIN5_SOURCE_W { - GPIO_PIN5_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin5_driver(&mut self) -> GPIO_PIN5_DRIVER_W { - GPIO_PIN5_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin5_int_type(&mut self) -> GPIO_PIN5_INT_TYPE_W { - GPIO_PIN5_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin5_wakeup_enable(&mut self) -> GPIO_PIN5_WAKEUP_ENABLE_W { - GPIO_PIN5_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN5_SPEC; -impl crate::RegisterSpec for GPIO_PIN5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin5::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin5::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN5 to value 0"] -impl crate::Resettable for GPIO_PIN5_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin6.rs b/esp8266/src/gpio/gpio_pin6.rs deleted file mode 100644 index f2d01e6bbe..0000000000 --- a/esp8266/src/gpio/gpio_pin6.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN6` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN6` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN6_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN6_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN6_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN6_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN6_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN6_SOURCE_A { - match self.bits { - false => GPIO_PIN6_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN6_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN6_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN6_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN6_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN6_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN6_SOURCE_A>; -impl<'a, REG> GPIO_PIN6_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN6_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN6_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN6_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN6_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN6_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN6_DRIVER_A { - match self.bits { - false => GPIO_PIN6_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN6_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN6_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN6_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN6_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN6_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN6_DRIVER_A>; -impl<'a, REG> GPIO_PIN6_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN6_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN6_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN6_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN6_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN6_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN6_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN6_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN6_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN6_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN6_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN6_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN6_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN6_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN6_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN6_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN6_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN6_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN6_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN6_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN6_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN6_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN6_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin6_source(&self) -> GPIO_PIN6_SOURCE_R { - GPIO_PIN6_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin6_driver(&self) -> GPIO_PIN6_DRIVER_R { - GPIO_PIN6_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin6_int_type(&self) -> GPIO_PIN6_INT_TYPE_R { - GPIO_PIN6_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin6_wakeup_enable(&self) -> GPIO_PIN6_WAKEUP_ENABLE_R { - GPIO_PIN6_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN6") - .field( - "gpio_pin6_wakeup_enable", - &format_args!("{}", self.gpio_pin6_wakeup_enable().bit()), - ) - .field( - "gpio_pin6_int_type", - &format_args!("{}", self.gpio_pin6_int_type().bits()), - ) - .field( - "gpio_pin6_driver", - &format_args!("{}", self.gpio_pin6_driver().bit()), - ) - .field( - "gpio_pin6_source", - &format_args!("{}", self.gpio_pin6_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin6_source(&mut self) -> GPIO_PIN6_SOURCE_W { - GPIO_PIN6_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin6_driver(&mut self) -> GPIO_PIN6_DRIVER_W { - GPIO_PIN6_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin6_int_type(&mut self) -> GPIO_PIN6_INT_TYPE_W { - GPIO_PIN6_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin6_wakeup_enable(&mut self) -> GPIO_PIN6_WAKEUP_ENABLE_W { - GPIO_PIN6_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN6_SPEC; -impl crate::RegisterSpec for GPIO_PIN6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin6::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin6::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN6_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN6 to value 0"] -impl crate::Resettable for GPIO_PIN6_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin7.rs b/esp8266/src/gpio/gpio_pin7.rs deleted file mode 100644 index 8ff9f0f399..0000000000 --- a/esp8266/src/gpio/gpio_pin7.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN7` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN7` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN7_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN7_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN7_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN7_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN7_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN7_SOURCE_A { - match self.bits { - false => GPIO_PIN7_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN7_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN7_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN7_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN7_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN7_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN7_SOURCE_A>; -impl<'a, REG> GPIO_PIN7_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN7_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN7_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN7_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN7_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN7_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN7_DRIVER_A { - match self.bits { - false => GPIO_PIN7_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN7_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN7_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN7_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN7_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN7_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN7_DRIVER_A>; -impl<'a, REG> GPIO_PIN7_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN7_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN7_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN7_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN7_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN7_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN7_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN7_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN7_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN7_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN7_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN7_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN7_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN7_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN7_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN7_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN7_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN7_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN7_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN7_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN7_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN7_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN7_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin7_source(&self) -> GPIO_PIN7_SOURCE_R { - GPIO_PIN7_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin7_driver(&self) -> GPIO_PIN7_DRIVER_R { - GPIO_PIN7_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin7_int_type(&self) -> GPIO_PIN7_INT_TYPE_R { - GPIO_PIN7_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin7_wakeup_enable(&self) -> GPIO_PIN7_WAKEUP_ENABLE_R { - GPIO_PIN7_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN7") - .field( - "gpio_pin7_wakeup_enable", - &format_args!("{}", self.gpio_pin7_wakeup_enable().bit()), - ) - .field( - "gpio_pin7_int_type", - &format_args!("{}", self.gpio_pin7_int_type().bits()), - ) - .field( - "gpio_pin7_driver", - &format_args!("{}", self.gpio_pin7_driver().bit()), - ) - .field( - "gpio_pin7_source", - &format_args!("{}", self.gpio_pin7_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin7_source(&mut self) -> GPIO_PIN7_SOURCE_W { - GPIO_PIN7_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin7_driver(&mut self) -> GPIO_PIN7_DRIVER_W { - GPIO_PIN7_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin7_int_type(&mut self) -> GPIO_PIN7_INT_TYPE_W { - GPIO_PIN7_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin7_wakeup_enable(&mut self) -> GPIO_PIN7_WAKEUP_ENABLE_W { - GPIO_PIN7_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN7_SPEC; -impl crate::RegisterSpec for GPIO_PIN7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin7::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin7::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN7_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN7 to value 0"] -impl crate::Resettable for GPIO_PIN7_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin8.rs b/esp8266/src/gpio/gpio_pin8.rs deleted file mode 100644 index 56f3d738f7..0000000000 --- a/esp8266/src/gpio/gpio_pin8.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN8` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN8` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN8_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN8_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN8_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN8_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN8_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN8_SOURCE_A { - match self.bits { - false => GPIO_PIN8_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN8_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN8_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN8_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN8_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN8_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN8_SOURCE_A>; -impl<'a, REG> GPIO_PIN8_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN8_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN8_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN8_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN8_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN8_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN8_DRIVER_A { - match self.bits { - false => GPIO_PIN8_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN8_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN8_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN8_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN8_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN8_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN8_DRIVER_A>; -impl<'a, REG> GPIO_PIN8_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN8_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN8_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN8_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN8_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN8_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN8_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN8_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN8_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN8_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN8_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN8_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN8_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN8_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN8_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN8_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN8_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN8_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN8_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN8_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN8_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN8_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN8_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin8_source(&self) -> GPIO_PIN8_SOURCE_R { - GPIO_PIN8_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin8_driver(&self) -> GPIO_PIN8_DRIVER_R { - GPIO_PIN8_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin8_int_type(&self) -> GPIO_PIN8_INT_TYPE_R { - GPIO_PIN8_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin8_wakeup_enable(&self) -> GPIO_PIN8_WAKEUP_ENABLE_R { - GPIO_PIN8_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN8") - .field( - "gpio_pin8_wakeup_enable", - &format_args!("{}", self.gpio_pin8_wakeup_enable().bit()), - ) - .field( - "gpio_pin8_int_type", - &format_args!("{}", self.gpio_pin8_int_type().bits()), - ) - .field( - "gpio_pin8_driver", - &format_args!("{}", self.gpio_pin8_driver().bit()), - ) - .field( - "gpio_pin8_source", - &format_args!("{}", self.gpio_pin8_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin8_source(&mut self) -> GPIO_PIN8_SOURCE_W { - GPIO_PIN8_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin8_driver(&mut self) -> GPIO_PIN8_DRIVER_W { - GPIO_PIN8_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin8_int_type(&mut self) -> GPIO_PIN8_INT_TYPE_W { - GPIO_PIN8_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin8_wakeup_enable(&mut self) -> GPIO_PIN8_WAKEUP_ENABLE_W { - GPIO_PIN8_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN8_SPEC; -impl crate::RegisterSpec for GPIO_PIN8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin8::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin8::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN8_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN8 to value 0"] -impl crate::Resettable for GPIO_PIN8_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_pin9.rs b/esp8266/src/gpio/gpio_pin9.rs deleted file mode 100644 index a5bafaef51..0000000000 --- a/esp8266/src/gpio/gpio_pin9.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = "Register `GPIO_PIN9` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_PIN9` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_PIN9_SOURCE` reader - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN9_SOURCE_R = crate::BitReader; -#[doc = "1: sigma-delta; 0: GPIO_DATA\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN9_SOURCE_A { - #[doc = "0: sigma-delta"] - SIGMA_DELTA = 0, - #[doc = "1: gpio data"] - GPIO_DATA = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN9_SOURCE_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN9_SOURCE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN9_SOURCE_A { - match self.bits { - false => GPIO_PIN9_SOURCE_A::SIGMA_DELTA, - true => GPIO_PIN9_SOURCE_A::GPIO_DATA, - } - } - #[doc = "sigma-delta"] - #[inline(always)] - pub fn is_sigma_delta(&self) -> bool { - *self == GPIO_PIN9_SOURCE_A::SIGMA_DELTA - } - #[doc = "gpio data"] - #[inline(always)] - pub fn is_gpio_data(&self) -> bool { - *self == GPIO_PIN9_SOURCE_A::GPIO_DATA - } -} -#[doc = "Field `GPIO_PIN9_SOURCE` writer - 1: sigma-delta; 0: GPIO_DATA"] -pub type GPIO_PIN9_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN9_SOURCE_A>; -impl<'a, REG> GPIO_PIN9_SOURCE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "sigma-delta"] - #[inline(always)] - pub fn sigma_delta(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_SOURCE_A::SIGMA_DELTA) - } - #[doc = "gpio data"] - #[inline(always)] - pub fn gpio_data(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_SOURCE_A::GPIO_DATA) - } -} -#[doc = "Field `GPIO_PIN9_DRIVER` reader - 1: open drain; 0: normal"] -pub type GPIO_PIN9_DRIVER_R = crate::BitReader; -#[doc = "1: open drain; 0: normal\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum GPIO_PIN9_DRIVER_A { - #[doc = "0: open drain"] - OPEN_DRAIN = 0, - #[doc = "1: normal"] - NORMAL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: GPIO_PIN9_DRIVER_A) -> Self { - variant as u8 != 0 - } -} -impl GPIO_PIN9_DRIVER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> GPIO_PIN9_DRIVER_A { - match self.bits { - false => GPIO_PIN9_DRIVER_A::OPEN_DRAIN, - true => GPIO_PIN9_DRIVER_A::NORMAL, - } - } - #[doc = "open drain"] - #[inline(always)] - pub fn is_open_drain(&self) -> bool { - *self == GPIO_PIN9_DRIVER_A::OPEN_DRAIN - } - #[doc = "normal"] - #[inline(always)] - pub fn is_normal(&self) -> bool { - *self == GPIO_PIN9_DRIVER_A::NORMAL - } -} -#[doc = "Field `GPIO_PIN9_DRIVER` writer - 1: open drain; 0: normal"] -pub type GPIO_PIN9_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG, GPIO_PIN9_DRIVER_A>; -impl<'a, REG> GPIO_PIN9_DRIVER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "open drain"] - #[inline(always)] - pub fn open_drain(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_DRIVER_A::OPEN_DRAIN) - } - #[doc = "normal"] - #[inline(always)] - pub fn normal(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_DRIVER_A::NORMAL) - } -} -#[doc = "Field `GPIO_PIN9_INT_TYPE` reader - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN9_INT_TYPE_R = crate::FieldReader; -#[doc = "0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum GPIO_PIN9_INT_TYPE_A { - #[doc = "0: interrupt is disabled"] - DISABLED = 0, - #[doc = "1: interrupt is triggered on the positive edge"] - POSITIVE_EDGE = 1, - #[doc = "2: interrupt is triggered on the negative edge"] - NEGATIVE_EDGE = 2, - #[doc = "3: interrupt is triggered on both edges"] - BOTH_EDGES = 3, - #[doc = "4: interrupt is triggered on the low level"] - LOW_LEVEL = 4, - #[doc = "5: interrupt is triggered on the high level"] - HIGH_LEVEL = 5, -} -impl From for u8 { - #[inline(always)] - fn from(variant: GPIO_PIN9_INT_TYPE_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for GPIO_PIN9_INT_TYPE_A { - type Ux = u8; -} -impl GPIO_PIN9_INT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(GPIO_PIN9_INT_TYPE_A::DISABLED), - 1 => Some(GPIO_PIN9_INT_TYPE_A::POSITIVE_EDGE), - 2 => Some(GPIO_PIN9_INT_TYPE_A::NEGATIVE_EDGE), - 3 => Some(GPIO_PIN9_INT_TYPE_A::BOTH_EDGES), - 4 => Some(GPIO_PIN9_INT_TYPE_A::LOW_LEVEL), - 5 => Some(GPIO_PIN9_INT_TYPE_A::HIGH_LEVEL), - _ => None, - } - } - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::DISABLED - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn is_positive_edge(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::POSITIVE_EDGE - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn is_negative_edge(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::NEGATIVE_EDGE - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn is_both_edges(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::BOTH_EDGES - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn is_low_level(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::LOW_LEVEL - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn is_high_level(&self) -> bool { - *self == GPIO_PIN9_INT_TYPE_A::HIGH_LEVEL - } -} -#[doc = "Field `GPIO_PIN9_INT_TYPE` writer - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] -pub type GPIO_PIN9_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, GPIO_PIN9_INT_TYPE_A>; -impl<'a, REG> GPIO_PIN9_INT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "interrupt is disabled"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::DISABLED) - } - #[doc = "interrupt is triggered on the positive edge"] - #[inline(always)] - pub fn positive_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::POSITIVE_EDGE) - } - #[doc = "interrupt is triggered on the negative edge"] - #[inline(always)] - pub fn negative_edge(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::NEGATIVE_EDGE) - } - #[doc = "interrupt is triggered on both edges"] - #[inline(always)] - pub fn both_edges(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::BOTH_EDGES) - } - #[doc = "interrupt is triggered on the low level"] - #[inline(always)] - pub fn low_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::LOW_LEVEL) - } - #[doc = "interrupt is triggered on the high level"] - #[inline(always)] - pub fn high_level(self) -> &'a mut crate::W { - self.variant(GPIO_PIN9_INT_TYPE_A::HIGH_LEVEL) - } -} -#[doc = "Field `GPIO_PIN9_WAKEUP_ENABLE` reader - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN9_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN9_WAKEUP_ENABLE` writer - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] -pub type GPIO_PIN9_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - pub fn gpio_pin9_source(&self) -> GPIO_PIN9_SOURCE_R { - GPIO_PIN9_SOURCE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - pub fn gpio_pin9_driver(&self) -> GPIO_PIN9_DRIVER_R { - GPIO_PIN9_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - pub fn gpio_pin9_int_type(&self) -> GPIO_PIN9_INT_TYPE_R { - GPIO_PIN9_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - pub fn gpio_pin9_wakeup_enable(&self) -> GPIO_PIN9_WAKEUP_ENABLE_R { - GPIO_PIN9_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_PIN9") - .field( - "gpio_pin9_wakeup_enable", - &format_args!("{}", self.gpio_pin9_wakeup_enable().bit()), - ) - .field( - "gpio_pin9_int_type", - &format_args!("{}", self.gpio_pin9_int_type().bits()), - ) - .field( - "gpio_pin9_driver", - &format_args!("{}", self.gpio_pin9_driver().bit()), - ) - .field( - "gpio_pin9_source", - &format_args!("{}", self.gpio_pin9_source().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: sigma-delta; 0: GPIO_DATA"] - #[inline(always)] - #[must_use] - pub fn gpio_pin9_source(&mut self) -> GPIO_PIN9_SOURCE_W { - GPIO_PIN9_SOURCE_W::new(self, 0) - } - #[doc = "Bit 2 - 1: open drain; 0: normal"] - #[inline(always)] - #[must_use] - pub fn gpio_pin9_driver(&mut self) -> GPIO_PIN9_DRIVER_W { - GPIO_PIN9_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level"] - #[inline(always)] - #[must_use] - pub fn gpio_pin9_int_type(&mut self) -> GPIO_PIN9_INT_TYPE_W { - GPIO_PIN9_INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5"] - #[inline(always)] - #[must_use] - pub fn gpio_pin9_wakeup_enable(&mut self) -> GPIO_PIN9_WAKEUP_ENABLE_W { - GPIO_PIN9_WAKEUP_ENABLE_W::new(self, 10) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_PIN9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pin9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pin9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_PIN9_SPEC; -impl crate::RegisterSpec for GPIO_PIN9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_pin9::R`](R) reader structure"] -impl crate::Readable for GPIO_PIN9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_pin9::W`](W) writer structure"] -impl crate::Writable for GPIO_PIN9_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_PIN9 to value 0"] -impl crate::Resettable for GPIO_PIN9_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_rtc_calib_sync.rs b/esp8266/src/gpio/gpio_rtc_calib_sync.rs deleted file mode 100644 index 71e6383025..0000000000 --- a/esp8266/src/gpio/gpio_rtc_calib_sync.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `GPIO_RTC_CALIB_SYNC` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_RTC_CALIB_SYNC` writer"] -pub type W = crate::W; -#[doc = "Field `RTC_PERIOD_NUM` reader - The cycle number of RTC-clock during RTC-clock-calibration"] -pub type RTC_PERIOD_NUM_R = crate::FieldReader; -#[doc = "Field `RTC_PERIOD_NUM` writer - The cycle number of RTC-clock during RTC-clock-calibration"] -pub type RTC_PERIOD_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `RTC_CALIB_START` reader - Positvie edge of this bit will trigger the RTC-clock-calibration process."] -pub type RTC_CALIB_START_R = crate::BitReader; -#[doc = "Field `RTC_CALIB_START` writer - Positvie edge of this bit will trigger the RTC-clock-calibration process."] -pub type RTC_CALIB_START_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:9 - The cycle number of RTC-clock during RTC-clock-calibration"] - #[inline(always)] - pub fn rtc_period_num(&self) -> RTC_PERIOD_NUM_R { - RTC_PERIOD_NUM_R::new((self.bits & 0x03ff) as u16) - } - #[doc = "Bit 31 - Positvie edge of this bit will trigger the RTC-clock-calibration process."] - #[inline(always)] - pub fn rtc_calib_start(&self) -> RTC_CALIB_START_R { - RTC_CALIB_START_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_RTC_CALIB_SYNC") - .field( - "rtc_calib_start", - &format_args!("{}", self.rtc_calib_start().bit()), - ) - .field( - "rtc_period_num", - &format_args!("{}", self.rtc_period_num().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:9 - The cycle number of RTC-clock during RTC-clock-calibration"] - #[inline(always)] - #[must_use] - pub fn rtc_period_num(&mut self) -> RTC_PERIOD_NUM_W { - RTC_PERIOD_NUM_W::new(self, 0) - } - #[doc = "Bit 31 - Positvie edge of this bit will trigger the RTC-clock-calibration process."] - #[inline(always)] - #[must_use] - pub fn rtc_calib_start(&mut self) -> RTC_CALIB_START_W { - RTC_CALIB_START_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Positvie edge of this bit will trigger the RTC-clock-calibration process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_rtc_calib_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_rtc_calib_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_RTC_CALIB_SYNC_SPEC; -impl crate::RegisterSpec for GPIO_RTC_CALIB_SYNC_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_rtc_calib_sync::R`](R) reader structure"] -impl crate::Readable for GPIO_RTC_CALIB_SYNC_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_rtc_calib_sync::W`](W) writer structure"] -impl crate::Writable for GPIO_RTC_CALIB_SYNC_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_RTC_CALIB_SYNC to value 0"] -impl crate::Resettable for GPIO_RTC_CALIB_SYNC_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_rtc_calib_value.rs b/esp8266/src/gpio/gpio_rtc_calib_value.rs deleted file mode 100644 index e04c5cb283..0000000000 --- a/esp8266/src/gpio/gpio_rtc_calib_value.rs +++ /dev/null @@ -1,104 +0,0 @@ -#[doc = "Register `GPIO_RTC_CALIB_VALUE` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_RTC_CALIB_VALUE` writer"] -pub type W = crate::W; -#[doc = "Field `RTC_CALIB_VALUE` reader - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock"] -pub type RTC_CALIB_VALUE_R = crate::FieldReader; -#[doc = "Field `RTC_CALIB_VALUE` writer - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock"] -pub type RTC_CALIB_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -#[doc = "Field `RTC_CALIB_RDY_REAL` reader - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] -pub type RTC_CALIB_RDY_REAL_R = crate::BitReader; -#[doc = "Field `RTC_CALIB_RDY_REAL` writer - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] -pub type RTC_CALIB_RDY_REAL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RTC_CALIB_RDY` reader - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] -pub type RTC_CALIB_RDY_R = crate::BitReader; -#[doc = "Field `RTC_CALIB_RDY` writer - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] -pub type RTC_CALIB_RDY_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:19 - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock"] - #[inline(always)] - pub fn rtc_calib_value(&self) -> RTC_CALIB_VALUE_R { - RTC_CALIB_VALUE_R::new(self.bits & 0x000f_ffff) - } - #[doc = "Bit 30 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] - #[inline(always)] - pub fn rtc_calib_rdy_real(&self) -> RTC_CALIB_RDY_REAL_R { - RTC_CALIB_RDY_REAL_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] - #[inline(always)] - pub fn rtc_calib_rdy(&self) -> RTC_CALIB_RDY_R { - RTC_CALIB_RDY_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_RTC_CALIB_VALUE") - .field( - "rtc_calib_rdy", - &format_args!("{}", self.rtc_calib_rdy().bit()), - ) - .field( - "rtc_calib_rdy_real", - &format_args!("{}", self.rtc_calib_rdy_real().bit()), - ) - .field( - "rtc_calib_value", - &format_args!("{}", self.rtc_calib_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:19 - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock"] - #[inline(always)] - #[must_use] - pub fn rtc_calib_value(&mut self) -> RTC_CALIB_VALUE_W { - RTC_CALIB_VALUE_W::new(self, 0) - } - #[doc = "Bit 30 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] - #[inline(always)] - #[must_use] - pub fn rtc_calib_rdy_real(&mut self) -> RTC_CALIB_RDY_REAL_W { - RTC_CALIB_RDY_REAL_W::new(self, 30) - } - #[doc = "Bit 31 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done"] - #[inline(always)] - #[must_use] - pub fn rtc_calib_rdy(&mut self) -> RTC_CALIB_RDY_W { - RTC_CALIB_RDY_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "0: during RTC-clock-calibration; 1: RTC-clock-calibration is done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_rtc_calib_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_rtc_calib_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_RTC_CALIB_VALUE_SPEC; -impl crate::RegisterSpec for GPIO_RTC_CALIB_VALUE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_rtc_calib_value::R`](R) reader structure"] -impl crate::Readable for GPIO_RTC_CALIB_VALUE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_rtc_calib_value::W`](W) writer structure"] -impl crate::Writable for GPIO_RTC_CALIB_VALUE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_RTC_CALIB_VALUE to value 0"] -impl crate::Resettable for GPIO_RTC_CALIB_VALUE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_sigma_delta.rs b/esp8266/src/gpio/gpio_sigma_delta.rs deleted file mode 100644 index 843b355f3a..0000000000 --- a/esp8266/src/gpio/gpio_sigma_delta.rs +++ /dev/null @@ -1,104 +0,0 @@ -#[doc = "Register `GPIO_SIGMA_DELTA` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_SIGMA_DELTA` writer"] -pub type W = crate::W; -#[doc = "Field `SIGMA_DELTA_TARGET` reader - target level of the sigma-delta. It is a signed byte."] -pub type SIGMA_DELTA_TARGET_R = crate::FieldReader; -#[doc = "Field `SIGMA_DELTA_TARGET` writer - target level of the sigma-delta. It is a signed byte."] -pub type SIGMA_DELTA_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `SIGMA_DELTA_PRESCALAR` reader - Clock pre-divider for sigma-delta."] -pub type SIGMA_DELTA_PRESCALAR_R = crate::FieldReader; -#[doc = "Field `SIGMA_DELTA_PRESCALAR` writer - Clock pre-divider for sigma-delta."] -pub type SIGMA_DELTA_PRESCALAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `SIGMA_DELTA_ENABLE` reader - 1: enable sigma-delta; 0: disable"] -pub type SIGMA_DELTA_ENABLE_R = crate::BitReader; -#[doc = "Field `SIGMA_DELTA_ENABLE` writer - 1: enable sigma-delta; 0: disable"] -pub type SIGMA_DELTA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:7 - target level of the sigma-delta. It is a signed byte."] - #[inline(always)] - pub fn sigma_delta_target(&self) -> SIGMA_DELTA_TARGET_R { - SIGMA_DELTA_TARGET_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Clock pre-divider for sigma-delta."] - #[inline(always)] - pub fn sigma_delta_prescalar(&self) -> SIGMA_DELTA_PRESCALAR_R { - SIGMA_DELTA_PRESCALAR_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bit 16 - 1: enable sigma-delta; 0: disable"] - #[inline(always)] - pub fn sigma_delta_enable(&self) -> SIGMA_DELTA_ENABLE_R { - SIGMA_DELTA_ENABLE_R::new(((self.bits >> 16) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_SIGMA_DELTA") - .field( - "sigma_delta_enable", - &format_args!("{}", self.sigma_delta_enable().bit()), - ) - .field( - "sigma_delta_prescalar", - &format_args!("{}", self.sigma_delta_prescalar().bits()), - ) - .field( - "sigma_delta_target", - &format_args!("{}", self.sigma_delta_target().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - target level of the sigma-delta. It is a signed byte."] - #[inline(always)] - #[must_use] - pub fn sigma_delta_target(&mut self) -> SIGMA_DELTA_TARGET_W { - SIGMA_DELTA_TARGET_W::new(self, 0) - } - #[doc = "Bits 8:15 - Clock pre-divider for sigma-delta."] - #[inline(always)] - #[must_use] - pub fn sigma_delta_prescalar(&mut self) -> SIGMA_DELTA_PRESCALAR_W { - SIGMA_DELTA_PRESCALAR_W::new(self, 8) - } - #[doc = "Bit 16 - 1: enable sigma-delta; 0: disable"] - #[inline(always)] - #[must_use] - pub fn sigma_delta_enable(&mut self) -> SIGMA_DELTA_ENABLE_W { - SIGMA_DELTA_ENABLE_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_SIGMA_DELTA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_sigma_delta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_sigma_delta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_SIGMA_DELTA_SPEC; -impl crate::RegisterSpec for GPIO_SIGMA_DELTA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_sigma_delta::R`](R) reader structure"] -impl crate::Readable for GPIO_SIGMA_DELTA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_sigma_delta::W`](W) writer structure"] -impl crate::Writable for GPIO_SIGMA_DELTA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_SIGMA_DELTA to value 0"] -impl crate::Resettable for GPIO_SIGMA_DELTA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_status.rs b/esp8266/src/gpio/gpio_status.rs deleted file mode 100644 index 5cf61f1f72..0000000000 --- a/esp8266/src/gpio/gpio_status.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `GPIO_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `GPIO_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_STATUS_INTERRUPT` reader - Interrupt enable register."] -pub type GPIO_STATUS_INTERRUPT_R = crate::FieldReader; -#[doc = "Field `GPIO_STATUS_INTERRUPT` writer - Interrupt enable register."] -pub type GPIO_STATUS_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Interrupt enable register."] - #[inline(always)] - pub fn gpio_status_interrupt(&self) -> GPIO_STATUS_INTERRUPT_R { - GPIO_STATUS_INTERRUPT_R::new((self.bits & 0xffff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO_STATUS") - .field( - "gpio_status_interrupt", - &format_args!("{}", self.gpio_status_interrupt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - Interrupt enable register."] - #[inline(always)] - #[must_use] - pub fn gpio_status_interrupt(&mut self) -> GPIO_STATUS_INTERRUPT_W { - GPIO_STATUS_INTERRUPT_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_STATUS_SPEC; -impl crate::RegisterSpec for GPIO_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] -impl crate::Readable for GPIO_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`gpio_status::W`](W) writer structure"] -impl crate::Writable for GPIO_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_STATUS to value 0"] -impl crate::Resettable for GPIO_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_status_w1tc.rs b/esp8266/src/gpio/gpio_status_w1tc.rs deleted file mode 100644 index 6ad89e8029..0000000000 --- a/esp8266/src/gpio/gpio_status_w1tc.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `GPIO_STATUS_W1TC` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_STATUS_INTERRUPT_W1TC` writer - Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT"] -pub type GPIO_STATUS_INTERRUPT_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT"] - #[inline(always)] - #[must_use] - pub fn gpio_status_interrupt_w1tc( - &mut self, - ) -> GPIO_STATUS_INTERRUPT_W1TC_W { - GPIO_STATUS_INTERRUPT_W1TC_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_STATUS_W1TC\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_STATUS_W1TC_SPEC; -impl crate::RegisterSpec for GPIO_STATUS_W1TC_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_status_w1tc::W`](W) writer structure"] -impl crate::Writable for GPIO_STATUS_W1TC_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_STATUS_W1TC to value 0"] -impl crate::Resettable for GPIO_STATUS_W1TC_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/gpio/gpio_status_w1ts.rs b/esp8266/src/gpio/gpio_status_w1ts.rs deleted file mode 100644 index b1f2b8a1e2..0000000000 --- a/esp8266/src/gpio/gpio_status_w1ts.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `GPIO_STATUS_W1TS` writer"] -pub type W = crate::W; -#[doc = "Field `GPIO_STATUS_INTERRUPT_W1TS` writer - Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT"] -pub type GPIO_STATUS_INTERRUPT_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bits 0:15 - Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT"] - #[inline(always)] - #[must_use] - pub fn gpio_status_interrupt_w1ts( - &mut self, - ) -> GPIO_STATUS_INTERRUPT_W1TS_W { - GPIO_STATUS_INTERRUPT_W1TS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "GPIO_STATUS_W1TS\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct GPIO_STATUS_W1TS_SPEC; -impl crate::RegisterSpec for GPIO_STATUS_W1TS_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`gpio_status_w1ts::W`](W) writer structure"] -impl crate::Writable for GPIO_STATUS_W1TS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets GPIO_STATUS_W1TS to value 0"] -impl crate::Resettable for GPIO_STATUS_W1TS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s.rs b/esp8266/src/i2s.rs deleted file mode 100644 index 484b189503..0000000000 --- a/esp8266/src/i2s.rs +++ /dev/null @@ -1,117 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - i2stxfifo: I2STXFIFO, - i2srxfifo: I2SRXFIFO, - i2sconf: I2SCONF, - i2sint_raw: I2SINT_RAW, - i2sint_st: I2SINT_ST, - i2sint_ena: I2SINT_ENA, - i2sint_clr: I2SINT_CLR, - i2stiming: I2STIMING, - i2s_fifo_conf: I2S_FIFO_CONF, - i2srxeof_num: I2SRXEOF_NUM, - i2sconf_sigle_data: I2SCONF_SIGLE_DATA, -} -impl RegisterBlock { - #[doc = "0x00 - I2STXFIFO"] - #[inline(always)] - pub const fn i2stxfifo(&self) -> &I2STXFIFO { - &self.i2stxfifo - } - #[doc = "0x04 - I2SRXFIFO"] - #[inline(always)] - pub const fn i2srxfifo(&self) -> &I2SRXFIFO { - &self.i2srxfifo - } - #[doc = "0x08 - I2SCONF"] - #[inline(always)] - pub const fn i2sconf(&self) -> &I2SCONF { - &self.i2sconf - } - #[doc = "0x0c - I2SINT_RAW"] - #[inline(always)] - pub const fn i2sint_raw(&self) -> &I2SINT_RAW { - &self.i2sint_raw - } - #[doc = "0x10 - I2SINT_ST"] - #[inline(always)] - pub const fn i2sint_st(&self) -> &I2SINT_ST { - &self.i2sint_st - } - #[doc = "0x14 - I2SINT_ENA"] - #[inline(always)] - pub const fn i2sint_ena(&self) -> &I2SINT_ENA { - &self.i2sint_ena - } - #[doc = "0x18 - I2SINT_CLR"] - #[inline(always)] - pub const fn i2sint_clr(&self) -> &I2SINT_CLR { - &self.i2sint_clr - } - #[doc = "0x1c - I2STIMING"] - #[inline(always)] - pub const fn i2stiming(&self) -> &I2STIMING { - &self.i2stiming - } - #[doc = "0x20 - I2S_FIFO_CONF"] - #[inline(always)] - pub const fn i2s_fifo_conf(&self) -> &I2S_FIFO_CONF { - &self.i2s_fifo_conf - } - #[doc = "0x24 - I2SRXEOF_NUM"] - #[inline(always)] - pub const fn i2srxeof_num(&self) -> &I2SRXEOF_NUM { - &self.i2srxeof_num - } - #[doc = "0x28 - I2SCONF_SIGLE_DATA"] - #[inline(always)] - pub const fn i2sconf_sigle_data(&self) -> &I2SCONF_SIGLE_DATA { - &self.i2sconf_sigle_data - } -} -#[doc = "I2STXFIFO (rw) register accessor: I2STXFIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2stxfifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2stxfifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2stxfifo`] module"] -pub type I2STXFIFO = crate::Reg; -#[doc = "I2STXFIFO"] -pub mod i2stxfifo; -#[doc = "I2SRXFIFO (rw) register accessor: I2SRXFIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2srxfifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2srxfifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2srxfifo`] module"] -pub type I2SRXFIFO = crate::Reg; -#[doc = "I2SRXFIFO"] -pub mod i2srxfifo; -#[doc = "I2SCONF (rw) register accessor: I2SCONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sconf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sconf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sconf`] module"] -pub type I2SCONF = crate::Reg; -#[doc = "I2SCONF"] -pub mod i2sconf; -#[doc = "I2SINT_RAW (rw) register accessor: I2SINT_RAW\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sint_raw`] module"] -pub type I2SINT_RAW = crate::Reg; -#[doc = "I2SINT_RAW"] -pub mod i2sint_raw; -#[doc = "I2SINT_ST (rw) register accessor: I2SINT_ST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sint_st`] module"] -pub type I2SINT_ST = crate::Reg; -#[doc = "I2SINT_ST"] -pub mod i2sint_st; -#[doc = "I2SINT_ENA (rw) register accessor: I2SINT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sint_ena`] module"] -pub type I2SINT_ENA = crate::Reg; -#[doc = "I2SINT_ENA"] -pub mod i2sint_ena; -#[doc = "I2SINT_CLR (rw) register accessor: I2SINT_CLR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sint_clr`] module"] -pub type I2SINT_CLR = crate::Reg; -#[doc = "I2SINT_CLR"] -pub mod i2sint_clr; -#[doc = "I2STIMING (rw) register accessor: I2STIMING\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2stiming::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2stiming::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2stiming`] module"] -pub type I2STIMING = crate::Reg; -#[doc = "I2STIMING"] -pub mod i2stiming; -#[doc = "I2S_FIFO_CONF (rw) register accessor: I2S_FIFO_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_fifo_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_fifo_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_fifo_conf`] module"] -pub type I2S_FIFO_CONF = crate::Reg; -#[doc = "I2S_FIFO_CONF"] -pub mod i2s_fifo_conf; -#[doc = "I2SRXEOF_NUM (rw) register accessor: I2SRXEOF_NUM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2srxeof_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2srxeof_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2srxeof_num`] module"] -pub type I2SRXEOF_NUM = crate::Reg; -#[doc = "I2SRXEOF_NUM"] -pub mod i2srxeof_num; -#[doc = "I2SCONF_SIGLE_DATA (rw) register accessor: I2SCONF_SIGLE_DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sconf_sigle_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sconf_sigle_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2sconf_sigle_data`] module"] -pub type I2SCONF_SIGLE_DATA = crate::Reg; -#[doc = "I2SCONF_SIGLE_DATA"] -pub mod i2sconf_sigle_data; diff --git a/esp8266/src/i2s/i2s_fifo_conf.rs b/esp8266/src/i2s/i2s_fifo_conf.rs deleted file mode 100644 index 7015f9a17c..0000000000 --- a/esp8266/src/i2s/i2s_fifo_conf.rs +++ /dev/null @@ -1,142 +0,0 @@ -#[doc = "Register `I2S_FIFO_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `I2S_FIFO_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_RX_DATA_NUM` reader - "] -pub type I2S_I2S_RX_DATA_NUM_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_RX_DATA_NUM` writer - "] -pub type I2S_I2S_RX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `I2S_I2S_TX_DATA_NUM` reader - "] -pub type I2S_I2S_TX_DATA_NUM_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_TX_DATA_NUM` writer - "] -pub type I2S_I2S_TX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `I2S_I2S_DSCR_EN` reader - "] -pub type I2S_I2S_DSCR_EN_R = crate::BitReader; -#[doc = "Field `I2S_I2S_DSCR_EN` writer - "] -pub type I2S_I2S_DSCR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_FIFO_MOD` reader - "] -pub type I2S_I2S_TX_FIFO_MOD_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_TX_FIFO_MOD` writer - "] -pub type I2S_I2S_TX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `I2S_I2S_RX_FIFO_MOD` reader - "] -pub type I2S_I2S_RX_FIFO_MOD_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_RX_FIFO_MOD` writer - "] -pub type I2S_I2S_RX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:5"] - #[inline(always)] - pub fn i2s_i2s_rx_data_num(&self) -> I2S_I2S_RX_DATA_NUM_R { - I2S_I2S_RX_DATA_NUM_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11"] - #[inline(always)] - pub fn i2s_i2s_tx_data_num(&self) -> I2S_I2S_TX_DATA_NUM_R { - I2S_I2S_TX_DATA_NUM_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn i2s_i2s_dscr_en(&self) -> I2S_I2S_DSCR_EN_R { - I2S_I2S_DSCR_EN_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bits 13:15"] - #[inline(always)] - pub fn i2s_i2s_tx_fifo_mod(&self) -> I2S_I2S_TX_FIFO_MOD_R { - I2S_I2S_TX_FIFO_MOD_R::new(((self.bits >> 13) & 7) as u8) - } - #[doc = "Bits 16:18"] - #[inline(always)] - pub fn i2s_i2s_rx_fifo_mod(&self) -> I2S_I2S_RX_FIFO_MOD_R { - I2S_I2S_RX_FIFO_MOD_R::new(((self.bits >> 16) & 7) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2S_FIFO_CONF") - .field( - "i2s_i2s_rx_fifo_mod", - &format_args!("{}", self.i2s_i2s_rx_fifo_mod().bits()), - ) - .field( - "i2s_i2s_tx_fifo_mod", - &format_args!("{}", self.i2s_i2s_tx_fifo_mod().bits()), - ) - .field( - "i2s_i2s_dscr_en", - &format_args!("{}", self.i2s_i2s_dscr_en().bit()), - ) - .field( - "i2s_i2s_tx_data_num", - &format_args!("{}", self.i2s_i2s_tx_data_num().bits()), - ) - .field( - "i2s_i2s_rx_data_num", - &format_args!("{}", self.i2s_i2s_rx_data_num().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:5"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_data_num(&mut self) -> I2S_I2S_RX_DATA_NUM_W { - I2S_I2S_RX_DATA_NUM_W::new(self, 0) - } - #[doc = "Bits 6:11"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_data_num(&mut self) -> I2S_I2S_TX_DATA_NUM_W { - I2S_I2S_TX_DATA_NUM_W::new(self, 6) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_dscr_en(&mut self) -> I2S_I2S_DSCR_EN_W { - I2S_I2S_DSCR_EN_W::new(self, 12) - } - #[doc = "Bits 13:15"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_fifo_mod(&mut self) -> I2S_I2S_TX_FIFO_MOD_W { - I2S_I2S_TX_FIFO_MOD_W::new(self, 13) - } - #[doc = "Bits 16:18"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_fifo_mod(&mut self) -> I2S_I2S_RX_FIFO_MOD_W { - I2S_I2S_RX_FIFO_MOD_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2S_FIFO_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_fifo_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_fifo_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2S_FIFO_CONF_SPEC; -impl crate::RegisterSpec for I2S_FIFO_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2s_fifo_conf::R`](R) reader structure"] -impl crate::Readable for I2S_FIFO_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2s_fifo_conf::W`](W) writer structure"] -impl crate::Writable for I2S_FIFO_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2S_FIFO_CONF to value 0"] -impl crate::Resettable for I2S_FIFO_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sconf.rs b/esp8266/src/i2s/i2sconf.rs deleted file mode 100644 index 61aca90807..0000000000 --- a/esp8266/src/i2s/i2sconf.rs +++ /dev/null @@ -1,332 +0,0 @@ -#[doc = "Register `I2SCONF` reader"] -pub type R = crate::R; -#[doc = "Register `I2SCONF` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_TX_RESET` reader - "] -pub type I2S_I2S_TX_RESET_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_RESET` writer - "] -pub type I2S_I2S_TX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_RESET` reader - "] -pub type I2S_I2S_RX_RESET_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_RESET` writer - "] -pub type I2S_I2S_RX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_FIFO_RESET` reader - "] -pub type I2S_I2S_TX_FIFO_RESET_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_FIFO_RESET` writer - "] -pub type I2S_I2S_TX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_FIFO_RESET` reader - "] -pub type I2S_I2S_RX_FIFO_RESET_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_FIFO_RESET` writer - "] -pub type I2S_I2S_RX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_TRANS_SLAVE_MOD` reader - "] -pub type I2S_TRANS_SLAVE_MOD_R = crate::BitReader; -#[doc = "Field `I2S_TRANS_SLAVE_MOD` writer - "] -pub type I2S_TRANS_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_RECE_SLAVE_MOD` reader - "] -pub type I2S_RECE_SLAVE_MOD_R = crate::BitReader; -#[doc = "Field `I2S_RECE_SLAVE_MOD` writer - "] -pub type I2S_RECE_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_RIGHT_FIRST` reader - "] -pub type I2S_RIGHT_FIRST_R = crate::BitReader; -#[doc = "Field `I2S_RIGHT_FIRST` writer - "] -pub type I2S_RIGHT_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_MSB_RIGHT` reader - "] -pub type I2S_MSB_RIGHT_R = crate::BitReader; -#[doc = "Field `I2S_MSB_RIGHT` writer - "] -pub type I2S_MSB_RIGHT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_START` reader - "] -pub type I2S_I2S_TX_START_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_START` writer - "] -pub type I2S_I2S_TX_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_START` reader - "] -pub type I2S_I2S_RX_START_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_START` writer - "] -pub type I2S_I2S_RX_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_TRANS_MSB_SHIFT` reader - "] -pub type I2S_TRANS_MSB_SHIFT_R = crate::BitReader; -#[doc = "Field `I2S_TRANS_MSB_SHIFT` writer - "] -pub type I2S_TRANS_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_RECE_MSB_SHIFT` reader - "] -pub type I2S_RECE_MSB_SHIFT_R = crate::BitReader; -#[doc = "Field `I2S_RECE_MSB_SHIFT` writer - "] -pub type I2S_RECE_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_BITS_MOD` reader - "] -pub type I2S_BITS_MOD_R = crate::FieldReader; -#[doc = "Field `I2S_BITS_MOD` writer - "] -pub type I2S_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `I2S_CLKM_DIV_NUM` reader - "] -pub type I2S_CLKM_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `I2S_CLKM_DIV_NUM` writer - "] -pub type I2S_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `I2S_BCK_DIV_NUM` reader - "] -pub type I2S_BCK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `I2S_BCK_DIV_NUM` writer - "] -pub type I2S_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn i2s_i2s_tx_reset(&self) -> I2S_I2S_TX_RESET_R { - I2S_I2S_TX_RESET_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn i2s_i2s_rx_reset(&self) -> I2S_I2S_RX_RESET_R { - I2S_I2S_RX_RESET_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn i2s_i2s_tx_fifo_reset(&self) -> I2S_I2S_TX_FIFO_RESET_R { - I2S_I2S_TX_FIFO_RESET_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn i2s_i2s_rx_fifo_reset(&self) -> I2S_I2S_RX_FIFO_RESET_R { - I2S_I2S_RX_FIFO_RESET_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn i2s_trans_slave_mod(&self) -> I2S_TRANS_SLAVE_MOD_R { - I2S_TRANS_SLAVE_MOD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn i2s_rece_slave_mod(&self) -> I2S_RECE_SLAVE_MOD_R { - I2S_RECE_SLAVE_MOD_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn i2s_right_first(&self) -> I2S_RIGHT_FIRST_R { - I2S_RIGHT_FIRST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn i2s_msb_right(&self) -> I2S_MSB_RIGHT_R { - I2S_MSB_RIGHT_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn i2s_i2s_tx_start(&self) -> I2S_I2S_TX_START_R { - I2S_I2S_TX_START_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn i2s_i2s_rx_start(&self) -> I2S_I2S_RX_START_R { - I2S_I2S_RX_START_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10"] - #[inline(always)] - pub fn i2s_trans_msb_shift(&self) -> I2S_TRANS_MSB_SHIFT_R { - I2S_TRANS_MSB_SHIFT_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11"] - #[inline(always)] - pub fn i2s_rece_msb_shift(&self) -> I2S_RECE_MSB_SHIFT_R { - I2S_RECE_MSB_SHIFT_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bits 12:15"] - #[inline(always)] - pub fn i2s_bits_mod(&self) -> I2S_BITS_MOD_R { - I2S_BITS_MOD_R::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:21"] - #[inline(always)] - pub fn i2s_clkm_div_num(&self) -> I2S_CLKM_DIV_NUM_R { - I2S_CLKM_DIV_NUM_R::new(((self.bits >> 16) & 0x3f) as u8) - } - #[doc = "Bits 22:27"] - #[inline(always)] - pub fn i2s_bck_div_num(&self) -> I2S_BCK_DIV_NUM_R { - I2S_BCK_DIV_NUM_R::new(((self.bits >> 22) & 0x3f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SCONF") - .field( - "i2s_bck_div_num", - &format_args!("{}", self.i2s_bck_div_num().bits()), - ) - .field( - "i2s_clkm_div_num", - &format_args!("{}", self.i2s_clkm_div_num().bits()), - ) - .field( - "i2s_bits_mod", - &format_args!("{}", self.i2s_bits_mod().bits()), - ) - .field( - "i2s_rece_msb_shift", - &format_args!("{}", self.i2s_rece_msb_shift().bit()), - ) - .field( - "i2s_trans_msb_shift", - &format_args!("{}", self.i2s_trans_msb_shift().bit()), - ) - .field( - "i2s_i2s_rx_start", - &format_args!("{}", self.i2s_i2s_rx_start().bit()), - ) - .field( - "i2s_i2s_tx_start", - &format_args!("{}", self.i2s_i2s_tx_start().bit()), - ) - .field( - "i2s_msb_right", - &format_args!("{}", self.i2s_msb_right().bit()), - ) - .field( - "i2s_right_first", - &format_args!("{}", self.i2s_right_first().bit()), - ) - .field( - "i2s_rece_slave_mod", - &format_args!("{}", self.i2s_rece_slave_mod().bit()), - ) - .field( - "i2s_trans_slave_mod", - &format_args!("{}", self.i2s_trans_slave_mod().bit()), - ) - .field( - "i2s_i2s_rx_fifo_reset", - &format_args!("{}", self.i2s_i2s_rx_fifo_reset().bit()), - ) - .field( - "i2s_i2s_tx_fifo_reset", - &format_args!("{}", self.i2s_i2s_tx_fifo_reset().bit()), - ) - .field( - "i2s_i2s_rx_reset", - &format_args!("{}", self.i2s_i2s_rx_reset().bit()), - ) - .field( - "i2s_i2s_tx_reset", - &format_args!("{}", self.i2s_i2s_tx_reset().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_reset(&mut self) -> I2S_I2S_TX_RESET_W { - I2S_I2S_TX_RESET_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_reset(&mut self) -> I2S_I2S_RX_RESET_W { - I2S_I2S_RX_RESET_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_fifo_reset(&mut self) -> I2S_I2S_TX_FIFO_RESET_W { - I2S_I2S_TX_FIFO_RESET_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_fifo_reset(&mut self) -> I2S_I2S_RX_FIFO_RESET_W { - I2S_I2S_RX_FIFO_RESET_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_slave_mod(&mut self) -> I2S_TRANS_SLAVE_MOD_W { - I2S_TRANS_SLAVE_MOD_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_slave_mod(&mut self) -> I2S_RECE_SLAVE_MOD_W { - I2S_RECE_SLAVE_MOD_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn i2s_right_first(&mut self) -> I2S_RIGHT_FIRST_W { - I2S_RIGHT_FIRST_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn i2s_msb_right(&mut self) -> I2S_MSB_RIGHT_W { - I2S_MSB_RIGHT_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_start(&mut self) -> I2S_I2S_TX_START_W { - I2S_I2S_TX_START_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_start(&mut self) -> I2S_I2S_RX_START_W { - I2S_I2S_RX_START_W::new(self, 9) - } - #[doc = "Bit 10"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_msb_shift(&mut self) -> I2S_TRANS_MSB_SHIFT_W { - I2S_TRANS_MSB_SHIFT_W::new(self, 10) - } - #[doc = "Bit 11"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_msb_shift(&mut self) -> I2S_RECE_MSB_SHIFT_W { - I2S_RECE_MSB_SHIFT_W::new(self, 11) - } - #[doc = "Bits 12:15"] - #[inline(always)] - #[must_use] - pub fn i2s_bits_mod(&mut self) -> I2S_BITS_MOD_W { - I2S_BITS_MOD_W::new(self, 12) - } - #[doc = "Bits 16:21"] - #[inline(always)] - #[must_use] - pub fn i2s_clkm_div_num(&mut self) -> I2S_CLKM_DIV_NUM_W { - I2S_CLKM_DIV_NUM_W::new(self, 16) - } - #[doc = "Bits 22:27"] - #[inline(always)] - #[must_use] - pub fn i2s_bck_div_num(&mut self) -> I2S_BCK_DIV_NUM_W { - I2S_BCK_DIV_NUM_W::new(self, 22) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SCONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sconf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sconf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SCONF_SPEC; -impl crate::RegisterSpec for I2SCONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sconf::R`](R) reader structure"] -impl crate::Readable for I2SCONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sconf::W`](W) writer structure"] -impl crate::Writable for I2SCONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SCONF to value 0"] -impl crate::Resettable for I2SCONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sconf_sigle_data.rs b/esp8266/src/i2s/i2sconf_sigle_data.rs deleted file mode 100644 index 3d5b7d0e50..0000000000 --- a/esp8266/src/i2s/i2sconf_sigle_data.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `I2SCONF_SIGLE_DATA` reader"] -pub type R = crate::R; -#[doc = "Register `I2SCONF_SIGLE_DATA` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_SIGLE_DATA` reader - "] -pub type I2S_I2S_SIGLE_DATA_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_SIGLE_DATA` writer - "] -pub type I2S_I2S_SIGLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn i2s_i2s_sigle_data(&self) -> I2S_I2S_SIGLE_DATA_R { - I2S_I2S_SIGLE_DATA_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SCONF_SIGLE_DATA") - .field( - "i2s_i2s_sigle_data", - &format_args!("{}", self.i2s_i2s_sigle_data().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_sigle_data(&mut self) -> I2S_I2S_SIGLE_DATA_W { - I2S_I2S_SIGLE_DATA_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SCONF_SIGLE_DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sconf_sigle_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sconf_sigle_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SCONF_SIGLE_DATA_SPEC; -impl crate::RegisterSpec for I2SCONF_SIGLE_DATA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sconf_sigle_data::R`](R) reader structure"] -impl crate::Readable for I2SCONF_SIGLE_DATA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sconf_sigle_data::W`](W) writer structure"] -impl crate::Writable for I2SCONF_SIGLE_DATA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SCONF_SIGLE_DATA to value 0"] -impl crate::Resettable for I2SCONF_SIGLE_DATA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sint_clr.rs b/esp8266/src/i2s/i2sint_clr.rs deleted file mode 100644 index 92f83476e7..0000000000 --- a/esp8266/src/i2s/i2sint_clr.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `I2SINT_CLR` reader"] -pub type R = crate::R; -#[doc = "Register `I2SINT_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_TAKE_DATA_INT_CLR` reader - "] -pub type I2S_I2S_TAKE_DATA_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TAKE_DATA_INT_CLR` writer - "] -pub type I2S_I2S_TAKE_DATA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_PUT_DATA_INT_CLR` reader - "] -pub type I2S_I2S_PUT_DATA_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_PUT_DATA_INT_CLR` writer - "] -pub type I2S_I2S_PUT_DATA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_CLR` reader - "] -pub type I2S_I2S_RX_WFULL_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_CLR` writer - "] -pub type I2S_I2S_RX_WFULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_CLR` reader - "] -pub type I2S_I2S_RX_REMPTY_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_CLR` writer - "] -pub type I2S_I2S_RX_REMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_CLR` reader - "] -pub type I2S_I2S_TX_WFULL_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_CLR` writer - "] -pub type I2S_I2S_TX_WFULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_CLR` reader - "] -pub type I2S_I2S_TX_REMPTY_INT_CLR_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_CLR` writer - "] -pub type I2S_I2S_TX_REMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn i2s_i2s_take_data_int_clr(&self) -> I2S_I2S_TAKE_DATA_INT_CLR_R { - I2S_I2S_TAKE_DATA_INT_CLR_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn i2s_i2s_put_data_int_clr(&self) -> I2S_I2S_PUT_DATA_INT_CLR_R { - I2S_I2S_PUT_DATA_INT_CLR_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn i2s_i2s_rx_wfull_int_clr(&self) -> I2S_I2S_RX_WFULL_INT_CLR_R { - I2S_I2S_RX_WFULL_INT_CLR_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn i2s_i2s_rx_rempty_int_clr(&self) -> I2S_I2S_RX_REMPTY_INT_CLR_R { - I2S_I2S_RX_REMPTY_INT_CLR_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn i2s_i2s_tx_wfull_int_clr(&self) -> I2S_I2S_TX_WFULL_INT_CLR_R { - I2S_I2S_TX_WFULL_INT_CLR_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn i2s_i2s_tx_rempty_int_clr(&self) -> I2S_I2S_TX_REMPTY_INT_CLR_R { - I2S_I2S_TX_REMPTY_INT_CLR_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SINT_CLR") - .field( - "i2s_i2s_tx_rempty_int_clr", - &format_args!("{}", self.i2s_i2s_tx_rempty_int_clr().bit()), - ) - .field( - "i2s_i2s_tx_wfull_int_clr", - &format_args!("{}", self.i2s_i2s_tx_wfull_int_clr().bit()), - ) - .field( - "i2s_i2s_rx_rempty_int_clr", - &format_args!("{}", self.i2s_i2s_rx_rempty_int_clr().bit()), - ) - .field( - "i2s_i2s_rx_wfull_int_clr", - &format_args!("{}", self.i2s_i2s_rx_wfull_int_clr().bit()), - ) - .field( - "i2s_i2s_put_data_int_clr", - &format_args!("{}", self.i2s_i2s_put_data_int_clr().bit()), - ) - .field( - "i2s_i2s_take_data_int_clr", - &format_args!("{}", self.i2s_i2s_take_data_int_clr().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_take_data_int_clr(&mut self) -> I2S_I2S_TAKE_DATA_INT_CLR_W { - I2S_I2S_TAKE_DATA_INT_CLR_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_put_data_int_clr(&mut self) -> I2S_I2S_PUT_DATA_INT_CLR_W { - I2S_I2S_PUT_DATA_INT_CLR_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_wfull_int_clr(&mut self) -> I2S_I2S_RX_WFULL_INT_CLR_W { - I2S_I2S_RX_WFULL_INT_CLR_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_rempty_int_clr(&mut self) -> I2S_I2S_RX_REMPTY_INT_CLR_W { - I2S_I2S_RX_REMPTY_INT_CLR_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_wfull_int_clr(&mut self) -> I2S_I2S_TX_WFULL_INT_CLR_W { - I2S_I2S_TX_WFULL_INT_CLR_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_rempty_int_clr(&mut self) -> I2S_I2S_TX_REMPTY_INT_CLR_W { - I2S_I2S_TX_REMPTY_INT_CLR_W::new(self, 5) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SINT_CLR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SINT_CLR_SPEC; -impl crate::RegisterSpec for I2SINT_CLR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sint_clr::R`](R) reader structure"] -impl crate::Readable for I2SINT_CLR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sint_clr::W`](W) writer structure"] -impl crate::Writable for I2SINT_CLR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SINT_CLR to value 0"] -impl crate::Resettable for I2SINT_CLR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sint_ena.rs b/esp8266/src/i2s/i2sint_ena.rs deleted file mode 100644 index f46c13aac0..0000000000 --- a/esp8266/src/i2s/i2sint_ena.rs +++ /dev/null @@ -1,165 +0,0 @@ -#[doc = "Register `I2SINT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `I2SINT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_ENA` reader - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_ENA` writer - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_ENA` reader - "] -pub type I2S_I2S_TX_PUT_DATA_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_ENA` writer - "] -pub type I2S_I2S_TX_PUT_DATA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_ENA` reader - "] -pub type I2S_I2S_RX_WFULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_ENA` writer - "] -pub type I2S_I2S_RX_WFULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_ENA` reader - "] -pub type I2S_I2S_RX_REMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_ENA` writer - "] -pub type I2S_I2S_RX_REMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_ENA` reader - "] -pub type I2S_I2S_TX_WFULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_ENA` writer - "] -pub type I2S_I2S_TX_WFULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_ENA` reader - "] -pub type I2S_I2S_TX_REMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_ENA` writer - "] -pub type I2S_I2S_TX_REMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn i2s_i2s_rx_take_data_int_ena(&self) -> I2S_I2S_RX_TAKE_DATA_INT_ENA_R { - I2S_I2S_RX_TAKE_DATA_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn i2s_i2s_tx_put_data_int_ena(&self) -> I2S_I2S_TX_PUT_DATA_INT_ENA_R { - I2S_I2S_TX_PUT_DATA_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn i2s_i2s_rx_wfull_int_ena(&self) -> I2S_I2S_RX_WFULL_INT_ENA_R { - I2S_I2S_RX_WFULL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn i2s_i2s_rx_rempty_int_ena(&self) -> I2S_I2S_RX_REMPTY_INT_ENA_R { - I2S_I2S_RX_REMPTY_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn i2s_i2s_tx_wfull_int_ena(&self) -> I2S_I2S_TX_WFULL_INT_ENA_R { - I2S_I2S_TX_WFULL_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn i2s_i2s_tx_rempty_int_ena(&self) -> I2S_I2S_TX_REMPTY_INT_ENA_R { - I2S_I2S_TX_REMPTY_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SINT_ENA") - .field( - "i2s_i2s_tx_rempty_int_ena", - &format_args!("{}", self.i2s_i2s_tx_rempty_int_ena().bit()), - ) - .field( - "i2s_i2s_tx_wfull_int_ena", - &format_args!("{}", self.i2s_i2s_tx_wfull_int_ena().bit()), - ) - .field( - "i2s_i2s_rx_rempty_int_ena", - &format_args!("{}", self.i2s_i2s_rx_rempty_int_ena().bit()), - ) - .field( - "i2s_i2s_rx_wfull_int_ena", - &format_args!("{}", self.i2s_i2s_rx_wfull_int_ena().bit()), - ) - .field( - "i2s_i2s_tx_put_data_int_ena", - &format_args!("{}", self.i2s_i2s_tx_put_data_int_ena().bit()), - ) - .field( - "i2s_i2s_rx_take_data_int_ena", - &format_args!("{}", self.i2s_i2s_rx_take_data_int_ena().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_take_data_int_ena( - &mut self, - ) -> I2S_I2S_RX_TAKE_DATA_INT_ENA_W { - I2S_I2S_RX_TAKE_DATA_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_put_data_int_ena( - &mut self, - ) -> I2S_I2S_TX_PUT_DATA_INT_ENA_W { - I2S_I2S_TX_PUT_DATA_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_wfull_int_ena(&mut self) -> I2S_I2S_RX_WFULL_INT_ENA_W { - I2S_I2S_RX_WFULL_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_rempty_int_ena(&mut self) -> I2S_I2S_RX_REMPTY_INT_ENA_W { - I2S_I2S_RX_REMPTY_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_wfull_int_ena(&mut self) -> I2S_I2S_TX_WFULL_INT_ENA_W { - I2S_I2S_TX_WFULL_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_rempty_int_ena(&mut self) -> I2S_I2S_TX_REMPTY_INT_ENA_W { - I2S_I2S_TX_REMPTY_INT_ENA_W::new(self, 5) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SINT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SINT_ENA_SPEC; -impl crate::RegisterSpec for I2SINT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sint_ena::R`](R) reader structure"] -impl crate::Readable for I2SINT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sint_ena::W`](W) writer structure"] -impl crate::Writable for I2SINT_ENA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SINT_ENA to value 0"] -impl crate::Resettable for I2SINT_ENA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sint_raw.rs b/esp8266/src/i2s/i2sint_raw.rs deleted file mode 100644 index dd83d6a84e..0000000000 --- a/esp8266/src/i2s/i2sint_raw.rs +++ /dev/null @@ -1,165 +0,0 @@ -#[doc = "Register `I2SINT_RAW` reader"] -pub type R = crate::R; -#[doc = "Register `I2SINT_RAW` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_RAW` reader - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_RAW` writer - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_RAW` reader - "] -pub type I2S_I2S_TX_PUT_DATA_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_RAW` writer - "] -pub type I2S_I2S_TX_PUT_DATA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_RAW` reader - "] -pub type I2S_I2S_RX_WFULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_RAW` writer - "] -pub type I2S_I2S_RX_WFULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_RAW` reader - "] -pub type I2S_I2S_RX_REMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_RAW` writer - "] -pub type I2S_I2S_RX_REMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_RAW` reader - "] -pub type I2S_I2S_TX_WFULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_RAW` writer - "] -pub type I2S_I2S_TX_WFULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_RAW` reader - "] -pub type I2S_I2S_TX_REMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_RAW` writer - "] -pub type I2S_I2S_TX_REMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn i2s_i2s_rx_take_data_int_raw(&self) -> I2S_I2S_RX_TAKE_DATA_INT_RAW_R { - I2S_I2S_RX_TAKE_DATA_INT_RAW_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn i2s_i2s_tx_put_data_int_raw(&self) -> I2S_I2S_TX_PUT_DATA_INT_RAW_R { - I2S_I2S_TX_PUT_DATA_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn i2s_i2s_rx_wfull_int_raw(&self) -> I2S_I2S_RX_WFULL_INT_RAW_R { - I2S_I2S_RX_WFULL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn i2s_i2s_rx_rempty_int_raw(&self) -> I2S_I2S_RX_REMPTY_INT_RAW_R { - I2S_I2S_RX_REMPTY_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn i2s_i2s_tx_wfull_int_raw(&self) -> I2S_I2S_TX_WFULL_INT_RAW_R { - I2S_I2S_TX_WFULL_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn i2s_i2s_tx_rempty_int_raw(&self) -> I2S_I2S_TX_REMPTY_INT_RAW_R { - I2S_I2S_TX_REMPTY_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SINT_RAW") - .field( - "i2s_i2s_tx_rempty_int_raw", - &format_args!("{}", self.i2s_i2s_tx_rempty_int_raw().bit()), - ) - .field( - "i2s_i2s_tx_wfull_int_raw", - &format_args!("{}", self.i2s_i2s_tx_wfull_int_raw().bit()), - ) - .field( - "i2s_i2s_rx_rempty_int_raw", - &format_args!("{}", self.i2s_i2s_rx_rempty_int_raw().bit()), - ) - .field( - "i2s_i2s_rx_wfull_int_raw", - &format_args!("{}", self.i2s_i2s_rx_wfull_int_raw().bit()), - ) - .field( - "i2s_i2s_tx_put_data_int_raw", - &format_args!("{}", self.i2s_i2s_tx_put_data_int_raw().bit()), - ) - .field( - "i2s_i2s_rx_take_data_int_raw", - &format_args!("{}", self.i2s_i2s_rx_take_data_int_raw().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_take_data_int_raw( - &mut self, - ) -> I2S_I2S_RX_TAKE_DATA_INT_RAW_W { - I2S_I2S_RX_TAKE_DATA_INT_RAW_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_put_data_int_raw( - &mut self, - ) -> I2S_I2S_TX_PUT_DATA_INT_RAW_W { - I2S_I2S_TX_PUT_DATA_INT_RAW_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_wfull_int_raw(&mut self) -> I2S_I2S_RX_WFULL_INT_RAW_W { - I2S_I2S_RX_WFULL_INT_RAW_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_rempty_int_raw(&mut self) -> I2S_I2S_RX_REMPTY_INT_RAW_W { - I2S_I2S_RX_REMPTY_INT_RAW_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_wfull_int_raw(&mut self) -> I2S_I2S_TX_WFULL_INT_RAW_W { - I2S_I2S_TX_WFULL_INT_RAW_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_rempty_int_raw(&mut self) -> I2S_I2S_TX_REMPTY_INT_RAW_W { - I2S_I2S_TX_REMPTY_INT_RAW_W::new(self, 5) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SINT_RAW\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SINT_RAW_SPEC; -impl crate::RegisterSpec for I2SINT_RAW_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sint_raw::R`](R) reader structure"] -impl crate::Readable for I2SINT_RAW_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sint_raw::W`](W) writer structure"] -impl crate::Writable for I2SINT_RAW_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SINT_RAW to value 0"] -impl crate::Resettable for I2SINT_RAW_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2sint_st.rs b/esp8266/src/i2s/i2sint_st.rs deleted file mode 100644 index 3e826f7b19..0000000000 --- a/esp8266/src/i2s/i2sint_st.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `I2SINT_ST` reader"] -pub type R = crate::R; -#[doc = "Register `I2SINT_ST` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_ST` reader - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_TAKE_DATA_INT_ST` writer - "] -pub type I2S_I2S_RX_TAKE_DATA_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_ST` reader - "] -pub type I2S_I2S_TX_PUT_DATA_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_PUT_DATA_INT_ST` writer - "] -pub type I2S_I2S_TX_PUT_DATA_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_ST` reader - "] -pub type I2S_I2S_RX_WFULL_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_WFULL_INT_ST` writer - "] -pub type I2S_I2S_RX_WFULL_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_ST` reader - "] -pub type I2S_I2S_RX_REMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_RX_REMPTY_INT_ST` writer - "] -pub type I2S_I2S_RX_REMPTY_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_ST` reader - "] -pub type I2S_I2S_TX_WFULL_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_WFULL_INT_ST` writer - "] -pub type I2S_I2S_TX_WFULL_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_ST` reader - "] -pub type I2S_I2S_TX_REMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `I2S_I2S_TX_REMPTY_INT_ST` writer - "] -pub type I2S_I2S_TX_REMPTY_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn i2s_i2s_rx_take_data_int_st(&self) -> I2S_I2S_RX_TAKE_DATA_INT_ST_R { - I2S_I2S_RX_TAKE_DATA_INT_ST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn i2s_i2s_tx_put_data_int_st(&self) -> I2S_I2S_TX_PUT_DATA_INT_ST_R { - I2S_I2S_TX_PUT_DATA_INT_ST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn i2s_i2s_rx_wfull_int_st(&self) -> I2S_I2S_RX_WFULL_INT_ST_R { - I2S_I2S_RX_WFULL_INT_ST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn i2s_i2s_rx_rempty_int_st(&self) -> I2S_I2S_RX_REMPTY_INT_ST_R { - I2S_I2S_RX_REMPTY_INT_ST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn i2s_i2s_tx_wfull_int_st(&self) -> I2S_I2S_TX_WFULL_INT_ST_R { - I2S_I2S_TX_WFULL_INT_ST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn i2s_i2s_tx_rempty_int_st(&self) -> I2S_I2S_TX_REMPTY_INT_ST_R { - I2S_I2S_TX_REMPTY_INT_ST_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SINT_ST") - .field( - "i2s_i2s_tx_rempty_int_st", - &format_args!("{}", self.i2s_i2s_tx_rempty_int_st().bit()), - ) - .field( - "i2s_i2s_tx_wfull_int_st", - &format_args!("{}", self.i2s_i2s_tx_wfull_int_st().bit()), - ) - .field( - "i2s_i2s_rx_rempty_int_st", - &format_args!("{}", self.i2s_i2s_rx_rempty_int_st().bit()), - ) - .field( - "i2s_i2s_rx_wfull_int_st", - &format_args!("{}", self.i2s_i2s_rx_wfull_int_st().bit()), - ) - .field( - "i2s_i2s_tx_put_data_int_st", - &format_args!("{}", self.i2s_i2s_tx_put_data_int_st().bit()), - ) - .field( - "i2s_i2s_rx_take_data_int_st", - &format_args!("{}", self.i2s_i2s_rx_take_data_int_st().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_take_data_int_st(&mut self) -> I2S_I2S_RX_TAKE_DATA_INT_ST_W { - I2S_I2S_RX_TAKE_DATA_INT_ST_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_put_data_int_st(&mut self) -> I2S_I2S_TX_PUT_DATA_INT_ST_W { - I2S_I2S_TX_PUT_DATA_INT_ST_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_wfull_int_st(&mut self) -> I2S_I2S_RX_WFULL_INT_ST_W { - I2S_I2S_RX_WFULL_INT_ST_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_rempty_int_st(&mut self) -> I2S_I2S_RX_REMPTY_INT_ST_W { - I2S_I2S_RX_REMPTY_INT_ST_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_wfull_int_st(&mut self) -> I2S_I2S_TX_WFULL_INT_ST_W { - I2S_I2S_TX_WFULL_INT_ST_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_tx_rempty_int_st(&mut self) -> I2S_I2S_TX_REMPTY_INT_ST_W { - I2S_I2S_TX_REMPTY_INT_ST_W::new(self, 5) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SINT_ST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2sint_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2sint_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SINT_ST_SPEC; -impl crate::RegisterSpec for I2SINT_ST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2sint_st::R`](R) reader structure"] -impl crate::Readable for I2SINT_ST_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2sint_st::W`](W) writer structure"] -impl crate::Writable for I2SINT_ST_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SINT_ST to value 0"] -impl crate::Resettable for I2SINT_ST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2srxeof_num.rs b/esp8266/src/i2s/i2srxeof_num.rs deleted file mode 100644 index 2db8e1e5ae..0000000000 --- a/esp8266/src/i2s/i2srxeof_num.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `I2SRXEOF_NUM` reader"] -pub type R = crate::R; -#[doc = "Register `I2SRXEOF_NUM` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_I2S_RX_EOF_NUM` reader - "] -pub type I2S_I2S_RX_EOF_NUM_R = crate::FieldReader; -#[doc = "Field `I2S_I2S_RX_EOF_NUM` writer - "] -pub type I2S_I2S_RX_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn i2s_i2s_rx_eof_num(&self) -> I2S_I2S_RX_EOF_NUM_R { - I2S_I2S_RX_EOF_NUM_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SRXEOF_NUM") - .field( - "i2s_i2s_rx_eof_num", - &format_args!("{}", self.i2s_i2s_rx_eof_num().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn i2s_i2s_rx_eof_num(&mut self) -> I2S_I2S_RX_EOF_NUM_W { - I2S_I2S_RX_EOF_NUM_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SRXEOF_NUM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2srxeof_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2srxeof_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SRXEOF_NUM_SPEC; -impl crate::RegisterSpec for I2SRXEOF_NUM_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2srxeof_num::R`](R) reader structure"] -impl crate::Readable for I2SRXEOF_NUM_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2srxeof_num::W`](W) writer structure"] -impl crate::Writable for I2SRXEOF_NUM_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SRXEOF_NUM to value 0"] -impl crate::Resettable for I2SRXEOF_NUM_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2srxfifo.rs b/esp8266/src/i2s/i2srxfifo.rs deleted file mode 100644 index 7c912017d2..0000000000 --- a/esp8266/src/i2s/i2srxfifo.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `I2SRXFIFO` reader"] -pub type R = crate::R; -#[doc = "Register `I2SRXFIFO` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2SRXFIFO") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2SRXFIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2srxfifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2srxfifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2SRXFIFO_SPEC; -impl crate::RegisterSpec for I2SRXFIFO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2srxfifo::R`](R) reader structure"] -impl crate::Readable for I2SRXFIFO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2srxfifo::W`](W) writer structure"] -impl crate::Writable for I2SRXFIFO_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2SRXFIFO to value 0"] -impl crate::Resettable for I2SRXFIFO_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2stiming.rs b/esp8266/src/i2s/i2stiming.rs deleted file mode 100644 index 60296f0429..0000000000 --- a/esp8266/src/i2s/i2stiming.rs +++ /dev/null @@ -1,294 +0,0 @@ -#[doc = "Register `I2STIMING` reader"] -pub type R = crate::R; -#[doc = "Register `I2STIMING` writer"] -pub type W = crate::W; -#[doc = "Field `I2S_TRANS_BCK_IN_DELAY` reader - "] -pub type I2S_TRANS_BCK_IN_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_TRANS_BCK_IN_DELAY` writer - "] -pub type I2S_TRANS_BCK_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_TRANS_WS_IN_DELAY` reader - "] -pub type I2S_TRANS_WS_IN_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_TRANS_WS_IN_DELAY` writer - "] -pub type I2S_TRANS_WS_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_RECE_BCK_IN_DELAY` reader - "] -pub type I2S_RECE_BCK_IN_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_RECE_BCK_IN_DELAY` writer - "] -pub type I2S_RECE_BCK_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_RECE_WS_IN_DELAY` reader - "] -pub type I2S_RECE_WS_IN_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_RECE_WS_IN_DELAY` writer - "] -pub type I2S_RECE_WS_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_RECE_SD_IN_DELAY` reader - "] -pub type I2S_RECE_SD_IN_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_RECE_SD_IN_DELAY` writer - "] -pub type I2S_RECE_SD_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_TRANS_BCK_OUT_DELAY` reader - "] -pub type I2S_TRANS_BCK_OUT_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_TRANS_BCK_OUT_DELAY` writer - "] -pub type I2S_TRANS_BCK_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_TRANS_WS_OUT_DELAY` reader - "] -pub type I2S_TRANS_WS_OUT_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_TRANS_WS_OUT_DELAY` writer - "] -pub type I2S_TRANS_WS_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_TRANS_SD_OUT_DELAY` reader - "] -pub type I2S_TRANS_SD_OUT_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_TRANS_SD_OUT_DELAY` writer - "] -pub type I2S_TRANS_SD_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_RECE_WS_OUT_DELAY` reader - "] -pub type I2S_RECE_WS_OUT_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_RECE_WS_OUT_DELAY` writer - "] -pub type I2S_RECE_WS_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_RECE_BCK_OUT_DELAY` reader - "] -pub type I2S_RECE_BCK_OUT_DELAY_R = crate::FieldReader; -#[doc = "Field `I2S_RECE_BCK_OUT_DELAY` writer - "] -pub type I2S_RECE_BCK_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `I2S_TRANS_DSYNC_SW` reader - "] -pub type I2S_TRANS_DSYNC_SW_R = crate::BitReader; -#[doc = "Field `I2S_TRANS_DSYNC_SW` writer - "] -pub type I2S_TRANS_DSYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_RECE_DSYNC_SW` reader - "] -pub type I2S_RECE_DSYNC_SW_R = crate::BitReader; -#[doc = "Field `I2S_RECE_DSYNC_SW` writer - "] -pub type I2S_RECE_DSYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `I2S_TRANS_BCK_IN_INV` reader - "] -pub type I2S_TRANS_BCK_IN_INV_R = crate::BitReader; -#[doc = "Field `I2S_TRANS_BCK_IN_INV` writer - "] -pub type I2S_TRANS_BCK_IN_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:1"] - #[inline(always)] - pub fn i2s_trans_bck_in_delay(&self) -> I2S_TRANS_BCK_IN_DELAY_R { - I2S_TRANS_BCK_IN_DELAY_R::new((self.bits & 3) as u8) - } - #[doc = "Bits 2:3"] - #[inline(always)] - pub fn i2s_trans_ws_in_delay(&self) -> I2S_TRANS_WS_IN_DELAY_R { - I2S_TRANS_WS_IN_DELAY_R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5"] - #[inline(always)] - pub fn i2s_rece_bck_in_delay(&self) -> I2S_RECE_BCK_IN_DELAY_R { - I2S_RECE_BCK_IN_DELAY_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bits 6:7"] - #[inline(always)] - pub fn i2s_rece_ws_in_delay(&self) -> I2S_RECE_WS_IN_DELAY_R { - I2S_RECE_WS_IN_DELAY_R::new(((self.bits >> 6) & 3) as u8) - } - #[doc = "Bits 8:9"] - #[inline(always)] - pub fn i2s_rece_sd_in_delay(&self) -> I2S_RECE_SD_IN_DELAY_R { - I2S_RECE_SD_IN_DELAY_R::new(((self.bits >> 8) & 3) as u8) - } - #[doc = "Bits 10:11"] - #[inline(always)] - pub fn i2s_trans_bck_out_delay(&self) -> I2S_TRANS_BCK_OUT_DELAY_R { - I2S_TRANS_BCK_OUT_DELAY_R::new(((self.bits >> 10) & 3) as u8) - } - #[doc = "Bits 12:13"] - #[inline(always)] - pub fn i2s_trans_ws_out_delay(&self) -> I2S_TRANS_WS_OUT_DELAY_R { - I2S_TRANS_WS_OUT_DELAY_R::new(((self.bits >> 12) & 3) as u8) - } - #[doc = "Bits 14:15"] - #[inline(always)] - pub fn i2s_trans_sd_out_delay(&self) -> I2S_TRANS_SD_OUT_DELAY_R { - I2S_TRANS_SD_OUT_DELAY_R::new(((self.bits >> 14) & 3) as u8) - } - #[doc = "Bits 16:17"] - #[inline(always)] - pub fn i2s_rece_ws_out_delay(&self) -> I2S_RECE_WS_OUT_DELAY_R { - I2S_RECE_WS_OUT_DELAY_R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:19"] - #[inline(always)] - pub fn i2s_rece_bck_out_delay(&self) -> I2S_RECE_BCK_OUT_DELAY_R { - I2S_RECE_BCK_OUT_DELAY_R::new(((self.bits >> 18) & 3) as u8) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn i2s_trans_dsync_sw(&self) -> I2S_TRANS_DSYNC_SW_R { - I2S_TRANS_DSYNC_SW_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn i2s_rece_dsync_sw(&self) -> I2S_RECE_DSYNC_SW_R { - I2S_RECE_DSYNC_SW_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22"] - #[inline(always)] - pub fn i2s_trans_bck_in_inv(&self) -> I2S_TRANS_BCK_IN_INV_R { - I2S_TRANS_BCK_IN_INV_R::new(((self.bits >> 22) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2STIMING") - .field( - "i2s_trans_bck_in_inv", - &format_args!("{}", self.i2s_trans_bck_in_inv().bit()), - ) - .field( - "i2s_rece_dsync_sw", - &format_args!("{}", self.i2s_rece_dsync_sw().bit()), - ) - .field( - "i2s_trans_dsync_sw", - &format_args!("{}", self.i2s_trans_dsync_sw().bit()), - ) - .field( - "i2s_rece_bck_out_delay", - &format_args!("{}", self.i2s_rece_bck_out_delay().bits()), - ) - .field( - "i2s_rece_ws_out_delay", - &format_args!("{}", self.i2s_rece_ws_out_delay().bits()), - ) - .field( - "i2s_trans_sd_out_delay", - &format_args!("{}", self.i2s_trans_sd_out_delay().bits()), - ) - .field( - "i2s_trans_ws_out_delay", - &format_args!("{}", self.i2s_trans_ws_out_delay().bits()), - ) - .field( - "i2s_trans_bck_out_delay", - &format_args!("{}", self.i2s_trans_bck_out_delay().bits()), - ) - .field( - "i2s_rece_sd_in_delay", - &format_args!("{}", self.i2s_rece_sd_in_delay().bits()), - ) - .field( - "i2s_rece_ws_in_delay", - &format_args!("{}", self.i2s_rece_ws_in_delay().bits()), - ) - .field( - "i2s_rece_bck_in_delay", - &format_args!("{}", self.i2s_rece_bck_in_delay().bits()), - ) - .field( - "i2s_trans_ws_in_delay", - &format_args!("{}", self.i2s_trans_ws_in_delay().bits()), - ) - .field( - "i2s_trans_bck_in_delay", - &format_args!("{}", self.i2s_trans_bck_in_delay().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:1"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_bck_in_delay(&mut self) -> I2S_TRANS_BCK_IN_DELAY_W { - I2S_TRANS_BCK_IN_DELAY_W::new(self, 0) - } - #[doc = "Bits 2:3"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_ws_in_delay(&mut self) -> I2S_TRANS_WS_IN_DELAY_W { - I2S_TRANS_WS_IN_DELAY_W::new(self, 2) - } - #[doc = "Bits 4:5"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_bck_in_delay(&mut self) -> I2S_RECE_BCK_IN_DELAY_W { - I2S_RECE_BCK_IN_DELAY_W::new(self, 4) - } - #[doc = "Bits 6:7"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_ws_in_delay(&mut self) -> I2S_RECE_WS_IN_DELAY_W { - I2S_RECE_WS_IN_DELAY_W::new(self, 6) - } - #[doc = "Bits 8:9"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_sd_in_delay(&mut self) -> I2S_RECE_SD_IN_DELAY_W { - I2S_RECE_SD_IN_DELAY_W::new(self, 8) - } - #[doc = "Bits 10:11"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_bck_out_delay(&mut self) -> I2S_TRANS_BCK_OUT_DELAY_W { - I2S_TRANS_BCK_OUT_DELAY_W::new(self, 10) - } - #[doc = "Bits 12:13"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_ws_out_delay(&mut self) -> I2S_TRANS_WS_OUT_DELAY_W { - I2S_TRANS_WS_OUT_DELAY_W::new(self, 12) - } - #[doc = "Bits 14:15"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_sd_out_delay(&mut self) -> I2S_TRANS_SD_OUT_DELAY_W { - I2S_TRANS_SD_OUT_DELAY_W::new(self, 14) - } - #[doc = "Bits 16:17"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_ws_out_delay(&mut self) -> I2S_RECE_WS_OUT_DELAY_W { - I2S_RECE_WS_OUT_DELAY_W::new(self, 16) - } - #[doc = "Bits 18:19"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_bck_out_delay(&mut self) -> I2S_RECE_BCK_OUT_DELAY_W { - I2S_RECE_BCK_OUT_DELAY_W::new(self, 18) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_dsync_sw(&mut self) -> I2S_TRANS_DSYNC_SW_W { - I2S_TRANS_DSYNC_SW_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn i2s_rece_dsync_sw(&mut self) -> I2S_RECE_DSYNC_SW_W { - I2S_RECE_DSYNC_SW_W::new(self, 21) - } - #[doc = "Bit 22"] - #[inline(always)] - #[must_use] - pub fn i2s_trans_bck_in_inv(&mut self) -> I2S_TRANS_BCK_IN_INV_W { - I2S_TRANS_BCK_IN_INV_W::new(self, 22) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2STIMING\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2stiming::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2stiming::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2STIMING_SPEC; -impl crate::RegisterSpec for I2STIMING_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2stiming::R`](R) reader structure"] -impl crate::Readable for I2STIMING_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2stiming::W`](W) writer structure"] -impl crate::Writable for I2STIMING_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2STIMING to value 0"] -impl crate::Resettable for I2STIMING_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/i2s/i2stxfifo.rs b/esp8266/src/i2s/i2stxfifo.rs deleted file mode 100644 index d908a0067c..0000000000 --- a/esp8266/src/i2s/i2stxfifo.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `I2STXFIFO` reader"] -pub type R = crate::R; -#[doc = "Register `I2STXFIFO` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2STXFIFO") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "I2STXFIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2stxfifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2stxfifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct I2STXFIFO_SPEC; -impl crate::RegisterSpec for I2STXFIFO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`i2stxfifo::R`](R) reader structure"] -impl crate::Readable for I2STXFIFO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`i2stxfifo::W`](W) writer structure"] -impl crate::Writable for I2STXFIFO_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets I2STXFIFO to value 0"] -impl crate::Resettable for I2STXFIFO_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux.rs b/esp8266/src/io_mux.rs deleted file mode 100644 index 8e33956b10..0000000000 --- a/esp8266/src/io_mux.rs +++ /dev/null @@ -1,177 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - io_mux_conf: IO_MUX_CONF, - io_mux_mtdi: IO_MUX_MTDI, - io_mux_mtck: IO_MUX_MTCK, - io_mux_mtms: IO_MUX_MTMS, - io_mux_mtdo: IO_MUX_MTDO, - io_mux_u0rxd: IO_MUX_U0RXD, - io_mux_u0txd: IO_MUX_U0TXD, - io_mux_sd_clk: IO_MUX_SD_CLK, - io_mux_sd_data0: IO_MUX_SD_DATA0, - io_mux_sd_data1: IO_MUX_SD_DATA1, - io_mux_sd_data2: IO_MUX_SD_DATA2, - io_mux_sd_data3: IO_MUX_SD_DATA3, - io_mux_sd_cmd: IO_MUX_SD_CMD, - io_mux_gpio0: IO_MUX_GPIO0, - io_mux_gpio2: IO_MUX_GPIO2, - io_mux_gpio4: IO_MUX_GPIO4, - io_mux_gpio5: IO_MUX_GPIO5, -} -impl RegisterBlock { - #[doc = "0x00 - IO_MUX_CONF"] - #[inline(always)] - pub const fn io_mux_conf(&self) -> &IO_MUX_CONF { - &self.io_mux_conf - } - #[doc = "0x04 - IO_MUX_MTDI"] - #[inline(always)] - pub const fn io_mux_mtdi(&self) -> &IO_MUX_MTDI { - &self.io_mux_mtdi - } - #[doc = "0x08 - IO_MUX_MTCK"] - #[inline(always)] - pub const fn io_mux_mtck(&self) -> &IO_MUX_MTCK { - &self.io_mux_mtck - } - #[doc = "0x0c - IO_MUX_MTMS"] - #[inline(always)] - pub const fn io_mux_mtms(&self) -> &IO_MUX_MTMS { - &self.io_mux_mtms - } - #[doc = "0x10 - IO_MUX_MTDO"] - #[inline(always)] - pub const fn io_mux_mtdo(&self) -> &IO_MUX_MTDO { - &self.io_mux_mtdo - } - #[doc = "0x14 - IO_MUX_U0RXD"] - #[inline(always)] - pub const fn io_mux_u0rxd(&self) -> &IO_MUX_U0RXD { - &self.io_mux_u0rxd - } - #[doc = "0x18 - IO_MUX_U0TXD"] - #[inline(always)] - pub const fn io_mux_u0txd(&self) -> &IO_MUX_U0TXD { - &self.io_mux_u0txd - } - #[doc = "0x1c - IO_MUX_SD_CLK"] - #[inline(always)] - pub const fn io_mux_sd_clk(&self) -> &IO_MUX_SD_CLK { - &self.io_mux_sd_clk - } - #[doc = "0x20 - IO_MUX_SD_DATA0"] - #[inline(always)] - pub const fn io_mux_sd_data0(&self) -> &IO_MUX_SD_DATA0 { - &self.io_mux_sd_data0 - } - #[doc = "0x24 - IO_MUX_SD_DATA1"] - #[inline(always)] - pub const fn io_mux_sd_data1(&self) -> &IO_MUX_SD_DATA1 { - &self.io_mux_sd_data1 - } - #[doc = "0x28 - IO_MUX_SD_DATA2"] - #[inline(always)] - pub const fn io_mux_sd_data2(&self) -> &IO_MUX_SD_DATA2 { - &self.io_mux_sd_data2 - } - #[doc = "0x2c - IO_MUX_SD_DATA3"] - #[inline(always)] - pub const fn io_mux_sd_data3(&self) -> &IO_MUX_SD_DATA3 { - &self.io_mux_sd_data3 - } - #[doc = "0x30 - IO_MUX_SD_CMD"] - #[inline(always)] - pub const fn io_mux_sd_cmd(&self) -> &IO_MUX_SD_CMD { - &self.io_mux_sd_cmd - } - #[doc = "0x34 - IO_MUX_GPIO0"] - #[inline(always)] - pub const fn io_mux_gpio0(&self) -> &IO_MUX_GPIO0 { - &self.io_mux_gpio0 - } - #[doc = "0x38 - IO_MUX_GPIO2"] - #[inline(always)] - pub const fn io_mux_gpio2(&self) -> &IO_MUX_GPIO2 { - &self.io_mux_gpio2 - } - #[doc = "0x3c - IO_MUX_GPIO4"] - #[inline(always)] - pub const fn io_mux_gpio4(&self) -> &IO_MUX_GPIO4 { - &self.io_mux_gpio4 - } - #[doc = "0x40 - IO_MUX_GPIO5"] - #[inline(always)] - pub const fn io_mux_gpio5(&self) -> &IO_MUX_GPIO5 { - &self.io_mux_gpio5 - } -} -#[doc = "IO_MUX_CONF (rw) register accessor: IO_MUX_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_conf`] module"] -pub type IO_MUX_CONF = crate::Reg; -#[doc = "IO_MUX_CONF"] -pub mod io_mux_conf; -#[doc = "IO_MUX_MTDI (rw) register accessor: IO_MUX_MTDI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtdi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtdi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_mtdi`] module"] -pub type IO_MUX_MTDI = crate::Reg; -#[doc = "IO_MUX_MTDI"] -pub mod io_mux_mtdi; -#[doc = "IO_MUX_MTCK (rw) register accessor: IO_MUX_MTCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtck::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_mtck`] module"] -pub type IO_MUX_MTCK = crate::Reg; -#[doc = "IO_MUX_MTCK"] -pub mod io_mux_mtck; -#[doc = "IO_MUX_MTMS (rw) register accessor: IO_MUX_MTMS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtms::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtms::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_mtms`] module"] -pub type IO_MUX_MTMS = crate::Reg; -#[doc = "IO_MUX_MTMS"] -pub mod io_mux_mtms; -#[doc = "IO_MUX_MTDO (rw) register accessor: IO_MUX_MTDO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtdo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtdo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_mtdo`] module"] -pub type IO_MUX_MTDO = crate::Reg; -#[doc = "IO_MUX_MTDO"] -pub mod io_mux_mtdo; -#[doc = "IO_MUX_U0RXD (rw) register accessor: IO_MUX_U0RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_u0rxd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_u0rxd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_u0rxd`] module"] -pub type IO_MUX_U0RXD = crate::Reg; -#[doc = "IO_MUX_U0RXD"] -pub mod io_mux_u0rxd; -#[doc = "IO_MUX_U0TXD (rw) register accessor: IO_MUX_U0TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_u0txd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_u0txd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_u0txd`] module"] -pub type IO_MUX_U0TXD = crate::Reg; -#[doc = "IO_MUX_U0TXD"] -pub mod io_mux_u0txd; -#[doc = "IO_MUX_SD_CLK (rw) register accessor: IO_MUX_SD_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_clk`] module"] -pub type IO_MUX_SD_CLK = crate::Reg; -#[doc = "IO_MUX_SD_CLK"] -pub mod io_mux_sd_clk; -#[doc = "IO_MUX_SD_DATA0 (rw) register accessor: IO_MUX_SD_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_data0`] module"] -pub type IO_MUX_SD_DATA0 = crate::Reg; -#[doc = "IO_MUX_SD_DATA0"] -pub mod io_mux_sd_data0; -#[doc = "IO_MUX_SD_DATA1 (rw) register accessor: IO_MUX_SD_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_data1`] module"] -pub type IO_MUX_SD_DATA1 = crate::Reg; -#[doc = "IO_MUX_SD_DATA1"] -pub mod io_mux_sd_data1; -#[doc = "IO_MUX_SD_DATA2 (rw) register accessor: IO_MUX_SD_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_data2`] module"] -pub type IO_MUX_SD_DATA2 = crate::Reg; -#[doc = "IO_MUX_SD_DATA2"] -pub mod io_mux_sd_data2; -#[doc = "IO_MUX_SD_DATA3 (rw) register accessor: IO_MUX_SD_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_data3`] module"] -pub type IO_MUX_SD_DATA3 = crate::Reg; -#[doc = "IO_MUX_SD_DATA3"] -pub mod io_mux_sd_data3; -#[doc = "IO_MUX_SD_CMD (rw) register accessor: IO_MUX_SD_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_sd_cmd`] module"] -pub type IO_MUX_SD_CMD = crate::Reg; -#[doc = "IO_MUX_SD_CMD"] -pub mod io_mux_sd_cmd; -#[doc = "IO_MUX_GPIO0 (rw) register accessor: IO_MUX_GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_gpio0`] module"] -pub type IO_MUX_GPIO0 = crate::Reg; -#[doc = "IO_MUX_GPIO0"] -pub mod io_mux_gpio0; -#[doc = "IO_MUX_GPIO2 (rw) register accessor: IO_MUX_GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_gpio2`] module"] -pub type IO_MUX_GPIO2 = crate::Reg; -#[doc = "IO_MUX_GPIO2"] -pub mod io_mux_gpio2; -#[doc = "IO_MUX_GPIO4 (rw) register accessor: IO_MUX_GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_gpio4`] module"] -pub type IO_MUX_GPIO4 = crate::Reg; -#[doc = "IO_MUX_GPIO4"] -pub mod io_mux_gpio4; -#[doc = "IO_MUX_GPIO5 (rw) register accessor: IO_MUX_GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io_mux_gpio5`] module"] -pub type IO_MUX_GPIO5 = crate::Reg; -#[doc = "IO_MUX_GPIO5"] -pub mod io_mux_gpio5; diff --git a/esp8266/src/io_mux/io_mux_conf.rs b/esp8266/src/io_mux/io_mux_conf.rs deleted file mode 100644 index ea1dadc7c9..0000000000 --- a/esp8266/src/io_mux/io_mux_conf.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `IO_MUX_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `SPI0_CLK_EQU_SYS_CLK` reader - "] -pub type SPI0_CLK_EQU_SYS_CLK_R = crate::BitReader; -#[doc = "Field `SPI0_CLK_EQU_SYS_CLK` writer - "] -pub type SPI0_CLK_EQU_SYS_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SPI1_CLK_EQU_SYS_CLK` reader - "] -pub type SPI1_CLK_EQU_SYS_CLK_R = crate::BitReader; -#[doc = "Field `SPI1_CLK_EQU_SYS_CLK` writer - "] -pub type SPI1_CLK_EQU_SYS_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 8"] - #[inline(always)] - pub fn spi0_clk_equ_sys_clk(&self) -> SPI0_CLK_EQU_SYS_CLK_R { - SPI0_CLK_EQU_SYS_CLK_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn spi1_clk_equ_sys_clk(&self) -> SPI1_CLK_EQU_SYS_CLK_R { - SPI1_CLK_EQU_SYS_CLK_R::new(((self.bits >> 9) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_CONF") - .field( - "spi0_clk_equ_sys_clk", - &format_args!("{}", self.spi0_clk_equ_sys_clk().bit()), - ) - .field( - "spi1_clk_equ_sys_clk", - &format_args!("{}", self.spi1_clk_equ_sys_clk().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn spi0_clk_equ_sys_clk(&mut self) -> SPI0_CLK_EQU_SYS_CLK_W { - SPI0_CLK_EQU_SYS_CLK_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn spi1_clk_equ_sys_clk(&mut self) -> SPI1_CLK_EQU_SYS_CLK_W { - SPI1_CLK_EQU_SYS_CLK_W::new(self, 9) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_CONF_SPEC; -impl crate::RegisterSpec for IO_MUX_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_conf::R`](R) reader structure"] -impl crate::Readable for IO_MUX_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_conf::W`](W) writer structure"] -impl crate::Writable for IO_MUX_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_CONF to value 0"] -impl crate::Resettable for IO_MUX_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_gpio0.rs b/esp8266/src/io_mux/io_mux_gpio0.rs deleted file mode 100644 index 75146e7bb0..0000000000 --- a/esp8266/src/io_mux/io_mux_gpio0.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_GPIO0` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_GPIO0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_GPIO0") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_GPIO0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_GPIO0_SPEC; -impl crate::RegisterSpec for IO_MUX_GPIO0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_gpio0::R`](R) reader structure"] -impl crate::Readable for IO_MUX_GPIO0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_gpio0::W`](W) writer structure"] -impl crate::Writable for IO_MUX_GPIO0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_GPIO0 to value 0"] -impl crate::Resettable for IO_MUX_GPIO0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_gpio2.rs b/esp8266/src/io_mux/io_mux_gpio2.rs deleted file mode 100644 index 90bef01ca5..0000000000 --- a/esp8266/src/io_mux/io_mux_gpio2.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_GPIO2` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_GPIO2` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_GPIO2") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_GPIO2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_GPIO2_SPEC; -impl crate::RegisterSpec for IO_MUX_GPIO2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_gpio2::R`](R) reader structure"] -impl crate::Readable for IO_MUX_GPIO2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_gpio2::W`](W) writer structure"] -impl crate::Writable for IO_MUX_GPIO2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_GPIO2 to value 0"] -impl crate::Resettable for IO_MUX_GPIO2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_gpio4.rs b/esp8266/src/io_mux/io_mux_gpio4.rs deleted file mode 100644 index ea3446f308..0000000000 --- a/esp8266/src/io_mux/io_mux_gpio4.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_GPIO4` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_GPIO4` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_GPIO4") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_GPIO4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_GPIO4_SPEC; -impl crate::RegisterSpec for IO_MUX_GPIO4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_gpio4::R`](R) reader structure"] -impl crate::Readable for IO_MUX_GPIO4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_gpio4::W`](W) writer structure"] -impl crate::Writable for IO_MUX_GPIO4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_GPIO4 to value 0"] -impl crate::Resettable for IO_MUX_GPIO4_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_gpio5.rs b/esp8266/src/io_mux/io_mux_gpio5.rs deleted file mode 100644 index 27a19641ea..0000000000 --- a/esp8266/src/io_mux/io_mux_gpio5.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_GPIO5` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_GPIO5` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_GPIO5") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_GPIO5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_gpio5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_gpio5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_GPIO5_SPEC; -impl crate::RegisterSpec for IO_MUX_GPIO5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_gpio5::R`](R) reader structure"] -impl crate::Readable for IO_MUX_GPIO5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_gpio5::W`](W) writer structure"] -impl crate::Writable for IO_MUX_GPIO5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_GPIO5 to value 0"] -impl crate::Resettable for IO_MUX_GPIO5_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_mtck.rs b/esp8266/src/io_mux/io_mux_mtck.rs deleted file mode 100644 index 97f56918ba..0000000000 --- a/esp8266/src/io_mux/io_mux_mtck.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_MTCK` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_MTCK` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_MTCK") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_MTCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtck::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtck::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_MTCK_SPEC; -impl crate::RegisterSpec for IO_MUX_MTCK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_mtck::R`](R) reader structure"] -impl crate::Readable for IO_MUX_MTCK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_mtck::W`](W) writer structure"] -impl crate::Writable for IO_MUX_MTCK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_MTCK to value 0"] -impl crate::Resettable for IO_MUX_MTCK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_mtdi.rs b/esp8266/src/io_mux/io_mux_mtdi.rs deleted file mode 100644 index 66957e8d29..0000000000 --- a/esp8266/src/io_mux/io_mux_mtdi.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_MTDI` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_MTDI` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_MTDI") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_MTDI\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtdi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtdi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_MTDI_SPEC; -impl crate::RegisterSpec for IO_MUX_MTDI_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_mtdi::R`](R) reader structure"] -impl crate::Readable for IO_MUX_MTDI_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_mtdi::W`](W) writer structure"] -impl crate::Writable for IO_MUX_MTDI_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_MTDI to value 0"] -impl crate::Resettable for IO_MUX_MTDI_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_mtdo.rs b/esp8266/src/io_mux/io_mux_mtdo.rs deleted file mode 100644 index 6c9602697e..0000000000 --- a/esp8266/src/io_mux/io_mux_mtdo.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_MTDO` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_MTDO` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_MTDO") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_MTDO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtdo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtdo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_MTDO_SPEC; -impl crate::RegisterSpec for IO_MUX_MTDO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_mtdo::R`](R) reader structure"] -impl crate::Readable for IO_MUX_MTDO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_mtdo::W`](W) writer structure"] -impl crate::Writable for IO_MUX_MTDO_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_MTDO to value 0"] -impl crate::Resettable for IO_MUX_MTDO_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_mtms.rs b/esp8266/src/io_mux/io_mux_mtms.rs deleted file mode 100644 index 83a5e64a5c..0000000000 --- a/esp8266/src/io_mux/io_mux_mtms.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_MTMS` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_MTMS` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_MTMS") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_MTMS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_mtms::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_mtms::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_MTMS_SPEC; -impl crate::RegisterSpec for IO_MUX_MTMS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_mtms::R`](R) reader structure"] -impl crate::Readable for IO_MUX_MTMS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_mtms::W`](W) writer structure"] -impl crate::Writable for IO_MUX_MTMS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_MTMS to value 0"] -impl crate::Resettable for IO_MUX_MTMS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_clk.rs b/esp8266/src/io_mux/io_mux_sd_clk.rs deleted file mode 100644 index c8df19993c..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_clk.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_CLK` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_CLK` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_CLK") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_CLK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_CLK_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_CLK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_clk::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_CLK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_clk::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_CLK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_CLK to value 0"] -impl crate::Resettable for IO_MUX_SD_CLK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_cmd.rs b/esp8266/src/io_mux/io_mux_sd_cmd.rs deleted file mode 100644 index 162e7036b7..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_cmd.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_CMD` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_CMD` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_CMD") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_CMD_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_CMD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_cmd::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_CMD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_cmd::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_CMD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_CMD to value 0"] -impl crate::Resettable for IO_MUX_SD_CMD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_data0.rs b/esp8266/src/io_mux/io_mux_sd_data0.rs deleted file mode 100644 index 3187a4fbbc..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_data0.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_DATA0` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_DATA0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_DATA0") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_DATA0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_DATA0_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_DATA0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_data0::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_DATA0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_data0::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_DATA0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_DATA0 to value 0"] -impl crate::Resettable for IO_MUX_SD_DATA0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_data1.rs b/esp8266/src/io_mux/io_mux_sd_data1.rs deleted file mode 100644 index 6052f30343..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_data1.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_DATA1` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_DATA1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_DATA1") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_DATA1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_DATA1_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_DATA1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_data1::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_DATA1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_data1::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_DATA1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_DATA1 to value 0"] -impl crate::Resettable for IO_MUX_SD_DATA1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_data2.rs b/esp8266/src/io_mux/io_mux_sd_data2.rs deleted file mode 100644 index 07f5029be7..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_data2.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_DATA2` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_DATA2` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_DATA2") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_DATA2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_DATA2_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_DATA2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_data2::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_DATA2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_data2::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_DATA2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_DATA2 to value 0"] -impl crate::Resettable for IO_MUX_SD_DATA2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_sd_data3.rs b/esp8266/src/io_mux/io_mux_sd_data3.rs deleted file mode 100644 index 7149b2b186..0000000000 --- a/esp8266/src/io_mux/io_mux_sd_data3.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_SD_DATA3` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_SD_DATA3` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_SD_DATA3") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_SD_DATA3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_sd_data3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_sd_data3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_SD_DATA3_SPEC; -impl crate::RegisterSpec for IO_MUX_SD_DATA3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_sd_data3::R`](R) reader structure"] -impl crate::Readable for IO_MUX_SD_DATA3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_sd_data3::W`](W) writer structure"] -impl crate::Writable for IO_MUX_SD_DATA3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_SD_DATA3 to value 0"] -impl crate::Resettable for IO_MUX_SD_DATA3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_u0rxd.rs b/esp8266/src/io_mux/io_mux_u0rxd.rs deleted file mode 100644 index 4181398621..0000000000 --- a/esp8266/src/io_mux/io_mux_u0rxd.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_U0RXD` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_U0RXD` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_U0RXD") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_U0RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_u0rxd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_u0rxd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_U0RXD_SPEC; -impl crate::RegisterSpec for IO_MUX_U0RXD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_u0rxd::R`](R) reader structure"] -impl crate::Readable for IO_MUX_U0RXD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_u0rxd::W`](W) writer structure"] -impl crate::Writable for IO_MUX_U0RXD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_U0RXD to value 0"] -impl crate::Resettable for IO_MUX_U0RXD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/io_mux/io_mux_u0txd.rs b/esp8266/src/io_mux/io_mux_u0txd.rs deleted file mode 100644 index 50a3aa7525..0000000000 --- a/esp8266/src/io_mux/io_mux_u0txd.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `IO_MUX_U0TXD` reader"] -pub type R = crate::R; -#[doc = "Register `IO_MUX_U0TXD` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `SLEEP_ENABLE` reader - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_R = crate::BitReader; -#[doc = "Field `SLEEP_ENABLE` writer - configures output enable during sleep mode"] -pub type SLEEP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEP_PULLUP` reader - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_R = crate::BitReader; -#[doc = "Field `SLEEP_PULLUP` writer - configures pull up during sleep mode"] -pub type SLEEP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` reader - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_R = crate::FieldReader; -#[doc = "Field `FUNCTION_SELECT_LOW_BITS` writer - configures IO_MUX function, bottom 2 bits"] -pub type FUNCTION_SELECT_LOW_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `PULLUP` reader - configures pull up"] -pub type PULLUP_R = crate::BitReader; -#[doc = "Field `PULLUP` writer - configures pull up"] -pub type PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` reader - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_R = crate::BitReader; -#[doc = "Field `FUNCTION_SELECT_HIGH_BIT` writer - configures IO_MUX function, upper bit"] -pub type FUNCTION_SELECT_HIGH_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - pub fn sleep_enable(&self) -> SLEEP_ENABLE_R { - SLEEP_ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - pub fn sleep_pullup(&self) -> SLEEP_PULLUP_R { - SLEEP_PULLUP_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - pub fn function_select_low_bits(&self) -> FUNCTION_SELECT_LOW_BITS_R { - FUNCTION_SELECT_LOW_BITS_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - pub fn pullup(&self) -> PULLUP_R { - PULLUP_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - pub fn function_select_high_bit(&self) -> FUNCTION_SELECT_HIGH_BIT_R { - FUNCTION_SELECT_HIGH_BIT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX_U0TXD") - .field("register", &format_args!("{}", self.register().bits())) - .field( - "function_select_low_bits", - &format_args!("{}", self.function_select_low_bits().bits()), - ) - .field( - "function_select_high_bit", - &format_args!("{}", self.function_select_high_bit().bit()), - ) - .field("pullup", &format_args!("{}", self.pullup().bit())) - .field( - "sleep_pullup", - &format_args!("{}", self.sleep_pullup().bit()), - ) - .field( - "sleep_enable", - &format_args!("{}", self.sleep_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - configures output enable during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_enable(&mut self) -> SLEEP_ENABLE_W { - SLEEP_ENABLE_W::new(self, 0) - } - #[doc = "Bit 3 - configures pull up during sleep mode"] - #[inline(always)] - #[must_use] - pub fn sleep_pullup(&mut self) -> SLEEP_PULLUP_W { - SLEEP_PULLUP_W::new(self, 3) - } - #[doc = "Bits 4:5 - configures IO_MUX function, bottom 2 bits"] - #[inline(always)] - #[must_use] - pub fn function_select_low_bits(&mut self) -> FUNCTION_SELECT_LOW_BITS_W { - FUNCTION_SELECT_LOW_BITS_W::new(self, 4) - } - #[doc = "Bit 7 - configures pull up"] - #[inline(always)] - #[must_use] - pub fn pullup(&mut self) -> PULLUP_W { - PULLUP_W::new(self, 7) - } - #[doc = "Bit 8 - configures IO_MUX function, upper bit"] - #[inline(always)] - #[must_use] - pub fn function_select_high_bit(&mut self) -> FUNCTION_SELECT_HIGH_BIT_W { - FUNCTION_SELECT_HIGH_BIT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "IO_MUX_U0TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io_mux_u0txd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io_mux_u0txd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IO_MUX_U0TXD_SPEC; -impl crate::RegisterSpec for IO_MUX_U0TXD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`io_mux_u0txd::R`](R) reader structure"] -impl crate::Readable for IO_MUX_U0TXD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`io_mux_u0txd::W`](W) writer structure"] -impl crate::Writable for IO_MUX_U0TXD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets IO_MUX_U0TXD to value 0"] -impl crate::Resettable for IO_MUX_U0TXD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/lib.rs b/esp8266/src/lib.rs deleted file mode 100644 index 3ad9d6a571..0000000000 --- a/esp8266/src/lib.rs +++ /dev/null @@ -1,840 +0,0 @@ -#![doc = "Peripheral access API for ESP8266 microcontrollers (generated using svd2rust v0.31.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![allow(non_camel_case_types)] -#![allow(non_snake_case)] -#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] -#![no_std] -use core::marker::PhantomData; -use core::ops::Deref; -#[doc = r"Number available in the NVIC for configuring priority"] -pub const NVIC_PRIO_BITS: u8 = 3; -#[allow(unused_imports)] -use generic::*; -#[doc = r"Common register and bit access and modify traits"] -pub mod generic; -#[cfg(feature = "rt")] -extern "C" {} -#[doc(hidden)] -#[repr(C)] -pub union Vector { - pub _handler: unsafe extern "C" fn(), - _reserved: u32, -} -#[cfg(feature = "rt")] -#[doc(hidden)] -pub static __INTERRUPTS: [Vector; 0] = []; -#[doc = r"Enumeration of all the interrupts."] -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub enum Interrupt {} -unsafe impl xtensa_lx::interrupt::InterruptNumber for Interrupt { - #[inline(always)] - fn number(self) -> u16 { - match self {} - } -} -#[doc = r" TryFromInterruptError"] -#[derive(Debug, Copy, Clone)] -pub struct TryFromInterruptError(()); -impl Interrupt { - #[doc = r" Attempt to convert a given value into an `Interrupt`"] - #[inline] - pub fn try_from(value: u16) -> Result { - match value { - _ => Err(TryFromInterruptError(())), - } - } -} -#[doc = "DPORT"] -pub struct DPORT { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for DPORT {} -impl DPORT { - #[doc = r"Pointer to the register block"] - pub const PTR: *const dport::RegisterBlock = 0x3ff0_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const dport::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for DPORT { - type Target = dport::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for DPORT { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DPORT").finish() - } -} -#[doc = "DPORT"] -pub mod dport; -#[doc = "EFUSE"] -pub struct EFUSE { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for EFUSE {} -impl EFUSE { - #[doc = r"Pointer to the register block"] - pub const PTR: *const efuse::RegisterBlock = 0x3ff0_0050 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const efuse::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for EFUSE { - type Target = efuse::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for EFUSE { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EFUSE").finish() - } -} -#[doc = "EFUSE"] -pub mod efuse; -#[doc = "GPIO"] -pub struct GPIO { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for GPIO {} -impl GPIO { - #[doc = r"Pointer to the register block"] - pub const PTR: *const gpio::RegisterBlock = 0x6000_0300 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const gpio::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for GPIO { - type Target = gpio::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for GPIO { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GPIO").finish() - } -} -#[doc = "GPIO"] -pub mod gpio; -#[doc = "I2S"] -pub struct I2S { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for I2S {} -impl I2S { - #[doc = r"Pointer to the register block"] - pub const PTR: *const i2s::RegisterBlock = 0x6000_0e00 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const i2s::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for I2S { - type Target = i2s::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for I2S { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2S").finish() - } -} -#[doc = "I2S"] -pub mod i2s; -#[doc = "IO_MUX"] -pub struct IO_MUX { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for IO_MUX {} -impl IO_MUX { - #[doc = r"Pointer to the register block"] - pub const PTR: *const io_mux::RegisterBlock = 0x6000_0800 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const io_mux::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for IO_MUX { - type Target = io_mux::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for IO_MUX { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_MUX").finish() - } -} -#[doc = "IO_MUX"] -pub mod io_mux; -#[doc = "RTC"] -pub struct RTC { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for RTC {} -impl RTC { - #[doc = r"Pointer to the register block"] - pub const PTR: *const rtc::RegisterBlock = 0x6000_0700 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const rtc::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for RTC { - type Target = rtc::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for RTC { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RTC").finish() - } -} -#[doc = "RTC"] -pub mod rtc; -#[doc = "SLC"] -pub struct SLC { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SLC {} -impl SLC { - #[doc = r"Pointer to the register block"] - pub const PTR: *const slc::RegisterBlock = 0x6000_0b00 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const slc::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SLC { - type Target = slc::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SLC { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC").finish() - } -} -#[doc = "SLC"] -pub mod slc; -#[doc = "SPI0"] -pub struct SPI0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SPI0 {} -impl SPI0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const spi0::RegisterBlock = 0x6000_0200 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const spi0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SPI0 { - type Target = spi0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SPI0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI0").finish() - } -} -#[doc = "SPI0"] -pub mod spi0; -#[doc = "SPI1"] -pub struct SPI1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SPI1 {} -impl SPI1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const spi1::RegisterBlock = 0x6000_0100 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const spi1::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SPI1 { - type Target = spi1::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SPI1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI1").finish() - } -} -#[doc = "SPI1"] -pub mod spi1; -#[doc = "TIMER"] -pub struct TIMER { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TIMER {} -impl TIMER { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer::RegisterBlock = 0x6000_0600 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TIMER { - type Target = timer::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TIMER { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TIMER").finish() - } -} -#[doc = "TIMER"] -pub mod timer; -#[doc = "UART0"] -pub struct UART0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for UART0 {} -impl UART0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const uart0::RegisterBlock = 0x6000_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const uart0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for UART0 { - type Target = uart0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for UART0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0").finish() - } -} -#[doc = "UART0"] -pub mod uart0; -#[doc = "UART1"] -pub struct UART1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for UART1 {} -impl UART1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const uart1::RegisterBlock = 0x6000_0f00 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const uart1::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for UART1 { - type Target = uart1::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for UART1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1").finish() - } -} -#[doc = "UART1"] -pub mod uart1; -#[doc = "WDT"] -pub struct WDT { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for WDT {} -impl WDT { - #[doc = r"Pointer to the register block"] - pub const PTR: *const wdt::RegisterBlock = 0x6000_0900 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const wdt::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for WDT { - type Target = wdt::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for WDT { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WDT").finish() - } -} -#[doc = "WDT"] -pub mod wdt; -#[doc = "RNG register"] -pub struct RNG { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for RNG {} -impl RNG { - #[doc = r"Pointer to the register block"] - pub const PTR: *const rng::RegisterBlock = 0x3ff2_0e44 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const rng::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for RNG { - type Target = rng::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for RNG { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RNG").finish() - } -} -#[doc = "RNG register"] -pub mod rng; -#[doc = "Internal I2C registers"] -pub struct RTCCNTL { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for RTCCNTL {} -impl RTCCNTL { - #[doc = r"Pointer to the register block"] - pub const PTR: *const rtccntl::RegisterBlock = 0x6000_0d00 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const rtccntl::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for RTCCNTL { - type Target = rtccntl::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for RTCCNTL { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RTCCNTL").finish() - } -} -#[doc = "Internal I2C registers"] -pub mod rtccntl; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; -#[doc = r" All the peripherals."] -#[allow(non_snake_case)] -pub struct Peripherals { - #[doc = "DPORT"] - pub DPORT: DPORT, - #[doc = "EFUSE"] - pub EFUSE: EFUSE, - #[doc = "GPIO"] - pub GPIO: GPIO, - #[doc = "I2S"] - pub I2S: I2S, - #[doc = "IO_MUX"] - pub IO_MUX: IO_MUX, - #[doc = "RTC"] - pub RTC: RTC, - #[doc = "SLC"] - pub SLC: SLC, - #[doc = "SPI0"] - pub SPI0: SPI0, - #[doc = "SPI1"] - pub SPI1: SPI1, - #[doc = "TIMER"] - pub TIMER: TIMER, - #[doc = "UART0"] - pub UART0: UART0, - #[doc = "UART1"] - pub UART1: UART1, - #[doc = "WDT"] - pub WDT: WDT, - #[doc = "RNG"] - pub RNG: RNG, - #[doc = "RTCCNTL"] - pub RTCCNTL: RTCCNTL, -} -impl Peripherals { - #[doc = r" Returns all the peripherals *once*."] - #[cfg(feature = "critical-section")] - #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; - } - Some(unsafe { Peripherals::steal() }) - }) - } - #[doc = r" Unchecked version of `Peripherals::take`."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Each of the returned peripherals must be used at most once."] - #[inline] - pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; - Peripherals { - DPORT: DPORT { - _marker: PhantomData, - }, - EFUSE: EFUSE { - _marker: PhantomData, - }, - GPIO: GPIO { - _marker: PhantomData, - }, - I2S: I2S { - _marker: PhantomData, - }, - IO_MUX: IO_MUX { - _marker: PhantomData, - }, - RTC: RTC { - _marker: PhantomData, - }, - SLC: SLC { - _marker: PhantomData, - }, - SPI0: SPI0 { - _marker: PhantomData, - }, - SPI1: SPI1 { - _marker: PhantomData, - }, - TIMER: TIMER { - _marker: PhantomData, - }, - UART0: UART0 { - _marker: PhantomData, - }, - UART1: UART1 { - _marker: PhantomData, - }, - WDT: WDT { - _marker: PhantomData, - }, - RNG: RNG { - _marker: PhantomData, - }, - RTCCNTL: RTCCNTL { - _marker: PhantomData, - }, - } - } -} diff --git a/esp8266/src/rng.rs b/esp8266/src/rng.rs deleted file mode 100644 index 879228ab15..0000000000 --- a/esp8266/src/rng.rs +++ /dev/null @@ -1,17 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - rng: RNG, -} -impl RegisterBlock { - #[doc = "0x00 - RNG register"] - #[inline(always)] - pub const fn rng(&self) -> &RNG { - &self.rng - } -} -#[doc = "rng (r) register accessor: RNG register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng`] module"] -pub type RNG = crate::Reg; -#[doc = "RNG register"] -pub mod rng; diff --git a/esp8266/src/rng/rng.rs b/esp8266/src/rng/rng.rs deleted file mode 100644 index 127b1150d4..0000000000 --- a/esp8266/src/rng/rng.rs +++ /dev/null @@ -1,25 +0,0 @@ -#[doc = "Register `rng` reader"] -pub type R = crate::R; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "RNG register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RNG_SPEC; -impl crate::RegisterSpec for RNG_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rng::R`](R) reader structure"] -impl crate::Readable for RNG_SPEC {} -#[doc = "`reset()` method sets rng to value 0"] -impl crate::Resettable for RNG_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc.rs b/esp8266/src/rtc.rs deleted file mode 100644 index d22ae0bd94..0000000000 --- a/esp8266/src/rtc.rs +++ /dev/null @@ -1,83 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - _reserved0: [u8; 0x14], - rtc_state1: RTC_STATE1, - _reserved1: [u8; 0x18], - rtc_store0: RTC_STORE0, - _reserved2: [u8; 0x34], - rtc_gpio_out: RTC_GPIO_OUT, - _reserved3: [u8; 0x08], - rtc_gpio_enable: RTC_GPIO_ENABLE, - _reserved4: [u8; 0x14], - rtc_gpio_in_data: RTC_GPIO_IN_DATA, - rtc_gpio_conf: RTC_GPIO_CONF, - _reserved6: [u8; 0x0c], - pad_xpd_dcdc_conf: PAD_XPD_DCDC_CONF, -} -impl RegisterBlock { - #[doc = "0x14 - RTC_STATE1"] - #[inline(always)] - pub const fn rtc_state1(&self) -> &RTC_STATE1 { - &self.rtc_state1 - } - #[doc = "0x30 - RTC_STORE0"] - #[inline(always)] - pub const fn rtc_store0(&self) -> &RTC_STORE0 { - &self.rtc_store0 - } - #[doc = "0x68 - RTC_GPIO_OUT"] - #[inline(always)] - pub const fn rtc_gpio_out(&self) -> &RTC_GPIO_OUT { - &self.rtc_gpio_out - } - #[doc = "0x74 - RTC_GPIO_ENABLE"] - #[inline(always)] - pub const fn rtc_gpio_enable(&self) -> &RTC_GPIO_ENABLE { - &self.rtc_gpio_enable - } - #[doc = "0x8c - RTC_GPIO_IN_DATA"] - #[inline(always)] - pub const fn rtc_gpio_in_data(&self) -> &RTC_GPIO_IN_DATA { - &self.rtc_gpio_in_data - } - #[doc = "0x90 - RTC_GPIO_CONF"] - #[inline(always)] - pub const fn rtc_gpio_conf(&self) -> &RTC_GPIO_CONF { - &self.rtc_gpio_conf - } - #[doc = "0xa0 - PAD_XPD_DCDC_CONF"] - #[inline(always)] - pub const fn pad_xpd_dcdc_conf(&self) -> &PAD_XPD_DCDC_CONF { - &self.pad_xpd_dcdc_conf - } -} -#[doc = "RTC_STORE0 (rw) register accessor: RTC_STORE0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_store0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_store0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_store0`] module"] -pub type RTC_STORE0 = crate::Reg; -#[doc = "RTC_STORE0"] -pub mod rtc_store0; -#[doc = "RTC_STATE1 (rw) register accessor: RTC_STATE1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_state1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_state1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_state1`] module"] -pub type RTC_STATE1 = crate::Reg; -#[doc = "RTC_STATE1"] -pub mod rtc_state1; -#[doc = "PAD_XPD_DCDC_CONF (rw) register accessor: PAD_XPD_DCDC_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_xpd_dcdc_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_xpd_dcdc_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_xpd_dcdc_conf`] module"] -pub type PAD_XPD_DCDC_CONF = crate::Reg; -#[doc = "PAD_XPD_DCDC_CONF"] -pub mod pad_xpd_dcdc_conf; -#[doc = "RTC_GPIO_CONF (rw) register accessor: RTC_GPIO_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_gpio_conf`] module"] -pub type RTC_GPIO_CONF = crate::Reg; -#[doc = "RTC_GPIO_CONF"] -pub mod rtc_gpio_conf; -#[doc = "RTC_GPIO_ENABLE (rw) register accessor: RTC_GPIO_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_gpio_enable`] module"] -pub type RTC_GPIO_ENABLE = crate::Reg; -#[doc = "RTC_GPIO_ENABLE"] -pub mod rtc_gpio_enable; -#[doc = "RTC_GPIO_IN_DATA (rw) register accessor: RTC_GPIO_IN_DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_in_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_in_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_gpio_in_data`] module"] -pub type RTC_GPIO_IN_DATA = crate::Reg; -#[doc = "RTC_GPIO_IN_DATA"] -pub mod rtc_gpio_in_data; -#[doc = "RTC_GPIO_OUT (rw) register accessor: RTC_GPIO_OUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_gpio_out`] module"] -pub type RTC_GPIO_OUT = crate::Reg; -#[doc = "RTC_GPIO_OUT"] -pub mod rtc_gpio_out; diff --git a/esp8266/src/rtc/pad_xpd_dcdc_conf.rs b/esp8266/src/rtc/pad_xpd_dcdc_conf.rs deleted file mode 100644 index e503d30917..0000000000 --- a/esp8266/src/rtc/pad_xpd_dcdc_conf.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `PAD_XPD_DCDC_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `PAD_XPD_DCDC_CONF` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "PAD_XPD_DCDC_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_xpd_dcdc_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_xpd_dcdc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PAD_XPD_DCDC_CONF_SPEC; -impl crate::RegisterSpec for PAD_XPD_DCDC_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pad_xpd_dcdc_conf::R`](R) reader structure"] -impl crate::Readable for PAD_XPD_DCDC_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pad_xpd_dcdc_conf::W`](W) writer structure"] -impl crate::Writable for PAD_XPD_DCDC_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets PAD_XPD_DCDC_CONF to value 0"] -impl crate::Resettable for PAD_XPD_DCDC_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_gpio_conf.rs b/esp8266/src/rtc/rtc_gpio_conf.rs deleted file mode 100644 index 0889e0eeda..0000000000 --- a/esp8266/src/rtc/rtc_gpio_conf.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `RTC_GPIO_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_GPIO_CONF` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_GPIO_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_GPIO_CONF_SPEC; -impl crate::RegisterSpec for RTC_GPIO_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_gpio_conf::R`](R) reader structure"] -impl crate::Readable for RTC_GPIO_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_gpio_conf::W`](W) writer structure"] -impl crate::Writable for RTC_GPIO_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_GPIO_CONF to value 0"] -impl crate::Resettable for RTC_GPIO_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_gpio_enable.rs b/esp8266/src/rtc/rtc_gpio_enable.rs deleted file mode 100644 index 741311e83a..0000000000 --- a/esp8266/src/rtc/rtc_gpio_enable.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `RTC_GPIO_ENABLE` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_GPIO_ENABLE` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_GPIO_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_GPIO_ENABLE_SPEC; -impl crate::RegisterSpec for RTC_GPIO_ENABLE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_gpio_enable::R`](R) reader structure"] -impl crate::Readable for RTC_GPIO_ENABLE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable::W`](W) writer structure"] -impl crate::Writable for RTC_GPIO_ENABLE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_GPIO_ENABLE to value 0"] -impl crate::Resettable for RTC_GPIO_ENABLE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_gpio_in_data.rs b/esp8266/src/rtc/rtc_gpio_in_data.rs deleted file mode 100644 index b0a3d3353c..0000000000 --- a/esp8266/src/rtc/rtc_gpio_in_data.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `RTC_GPIO_IN_DATA` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_GPIO_IN_DATA` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_GPIO_IN_DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_in_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_in_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_GPIO_IN_DATA_SPEC; -impl crate::RegisterSpec for RTC_GPIO_IN_DATA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_gpio_in_data::R`](R) reader structure"] -impl crate::Readable for RTC_GPIO_IN_DATA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_gpio_in_data::W`](W) writer structure"] -impl crate::Writable for RTC_GPIO_IN_DATA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_GPIO_IN_DATA to value 0"] -impl crate::Resettable for RTC_GPIO_IN_DATA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_gpio_out.rs b/esp8266/src/rtc/rtc_gpio_out.rs deleted file mode 100644 index 329f753776..0000000000 --- a/esp8266/src/rtc/rtc_gpio_out.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `RTC_GPIO_OUT` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_GPIO_OUT` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_GPIO_OUT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_GPIO_OUT_SPEC; -impl crate::RegisterSpec for RTC_GPIO_OUT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_gpio_out::R`](R) reader structure"] -impl crate::Readable for RTC_GPIO_OUT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out::W`](W) writer structure"] -impl crate::Writable for RTC_GPIO_OUT_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_GPIO_OUT to value 0"] -impl crate::Resettable for RTC_GPIO_OUT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_state1.rs b/esp8266/src/rtc/rtc_state1.rs deleted file mode 100644 index 9fc9a6b4b5..0000000000 --- a/esp8266/src/rtc/rtc_state1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `RTC_STATE1` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_STATE1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RTC_STATE1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_STATE1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_state1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_state1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_STATE1_SPEC; -impl crate::RegisterSpec for RTC_STATE1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_state1::R`](R) reader structure"] -impl crate::Readable for RTC_STATE1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_state1::W`](W) writer structure"] -impl crate::Writable for RTC_STATE1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_STATE1 to value 0"] -impl crate::Resettable for RTC_STATE1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtc/rtc_store0.rs b/esp8266/src/rtc/rtc_store0.rs deleted file mode 100644 index ad90dc7c0e..0000000000 --- a/esp8266/src/rtc/rtc_store0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `RTC_STORE0` reader"] -pub type R = crate::R; -#[doc = "Register `RTC_STORE0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RTC_STORE0") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "RTC_STORE0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_store0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_store0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RTC_STORE0_SPEC; -impl crate::RegisterSpec for RTC_STORE0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`rtc_store0::R`](R) reader structure"] -impl crate::Readable for RTC_STORE0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`rtc_store0::W`](W) writer structure"] -impl crate::Writable for RTC_STORE0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets RTC_STORE0 to value 0"] -impl crate::Resettable for RTC_STORE0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/rtccntl.rs b/esp8266/src/rtccntl.rs deleted file mode 100644 index b851ad2766..0000000000 --- a/esp8266/src/rtccntl.rs +++ /dev/null @@ -1,18 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - _reserved0: [u8; 0x10], - pll: PLL, -} -impl RegisterBlock { - #[doc = "0x10 - PLL I2C Register"] - #[inline(always)] - pub const fn pll(&self) -> &PLL { - &self.pll - } -} -#[doc = "PLL (rw) register accessor: PLL I2C Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll`] module"] -pub type PLL = crate::Reg; -#[doc = "PLL I2C Register"] -pub mod pll; diff --git a/esp8266/src/rtccntl/pll.rs b/esp8266/src/rtccntl/pll.rs deleted file mode 100644 index f61a6d5035..0000000000 --- a/esp8266/src/rtccntl/pll.rs +++ /dev/null @@ -1,127 +0,0 @@ -#[doc = "Register `PLL` reader"] -pub type R = crate::R; -#[doc = "Register `PLL` writer"] -pub type W = crate::W; -#[doc = "Field `BLOCK` reader - Block"] -pub type BLOCK_R = crate::FieldReader; -#[doc = "Field `BLOCK` writer - Block"] -pub type BLOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `ADDR` reader - Address"] -pub type ADDR_R = crate::FieldReader; -#[doc = "Field `ADDR` writer - Address"] -pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `DATA` reader - Data"] -pub type DATA_R = crate::FieldReader; -#[doc = "Field `DATA` writer - Data"] -pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `WRITE` reader - Write"] -pub type WRITE_R = crate::BitReader; -#[doc = "Field `WRITE` writer - Write"] -pub type WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUSY` reader - Ready"] -pub type BUSY_R = crate::BitReader; -#[doc = "Field `BUSY` writer - Ready"] -pub type BUSY_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:7 - Block"] - #[inline(always)] - pub fn block(&self) -> BLOCK_R { - BLOCK_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - Address"] - #[inline(always)] - pub fn addr(&self) -> ADDR_R { - ADDR_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - Data"] - #[inline(always)] - pub fn data(&self) -> DATA_R { - DATA_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bit 24 - Write"] - #[inline(always)] - pub fn write(&self) -> WRITE_R { - WRITE_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - Ready"] - #[inline(always)] - pub fn busy(&self) -> BUSY_R { - BUSY_R::new(((self.bits >> 25) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PLL") - .field("block", &format_args!("{}", self.block().bits())) - .field("addr", &format_args!("{}", self.addr().bits())) - .field("data", &format_args!("{}", self.data().bits())) - .field("write", &format_args!("{}", self.write().bit())) - .field("busy", &format_args!("{}", self.busy().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - Block"] - #[inline(always)] - #[must_use] - pub fn block(&mut self) -> BLOCK_W { - BLOCK_W::new(self, 0) - } - #[doc = "Bits 8:15 - Address"] - #[inline(always)] - #[must_use] - pub fn addr(&mut self) -> ADDR_W { - ADDR_W::new(self, 8) - } - #[doc = "Bits 16:23 - Data"] - #[inline(always)] - #[must_use] - pub fn data(&mut self) -> DATA_W { - DATA_W::new(self, 16) - } - #[doc = "Bit 24 - Write"] - #[inline(always)] - #[must_use] - pub fn write(&mut self) -> WRITE_W { - WRITE_W::new(self, 24) - } - #[doc = "Bit 25 - Ready"] - #[inline(always)] - #[must_use] - pub fn busy(&mut self) -> BUSY_W { - BUSY_W::new(self, 25) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "PLL I2C Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PLL_SPEC; -impl crate::RegisterSpec for PLL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pll::R`](R) reader structure"] -impl crate::Readable for PLL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pll::W`](W) writer structure"] -impl crate::Writable for PLL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets PLL to value 0"] -impl crate::Resettable for PLL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc.rs b/esp8266/src/slc.rs deleted file mode 100644 index a2d5729aad..0000000000 --- a/esp8266/src/slc.rs +++ /dev/null @@ -1,328 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - slc_conf0: SLC_CONF0, - slc_int_raw: SLC_INT_RAW, - slc_int_status: SLC_INT_STATUS, - slc_int_ena: SLC_INT_ENA, - slc_int_clr: SLC_INT_CLR, - slc_rx_status: SLC_RX_STATUS, - slc_rx_fifo_push: SLC_RX_FIFO_PUSH, - slc_tx_status: SLC_TX_STATUS, - slc_tx_fifo_pop: SLC_TX_FIFO_POP, - slc_rx_link: SLC_RX_LINK, - slc_tx_link: SLC_TX_LINK, - slc_intvec_tohost: SLC_INTVEC_TOHOST, - slc_token0: SLC_TOKEN0, - slc_token1: SLC_TOKEN1, - slc_conf1: SLC_CONF1, - slc_state0: SLC_STATE0, - slc_state1: SLC_STATE1, - slc_bridge_conf: SLC_BRIDGE_CONF, - slc_rx_eof_des_addr: SLC_RX_EOF_DES_ADDR, - slc_tx_eof_des_addr: SLC_TX_EOF_DES_ADDR, - slc_rx_eof_bfr_des_addr: SLC_RX_EOF_BFR_DES_ADDR, - slc_ahb_test: SLC_AHB_TEST, - slc_sdio_st: SLC_SDIO_ST, - slc_rx_dscr_conf: SLC_RX_DSCR_CONF, - slc_txlink_dscr: SLC_TXLINK_DSCR, - slc_txlink_dscr_bf0: SLC_TXLINK_DSCR_BF0, - slc_txlink_dscr_bf1: SLC_TXLINK_DSCR_BF1, - slc_rxlink_dscr: SLC_RXLINK_DSCR, - slc_rxlink_dscr_bf0: SLC_RXLINK_DSCR_BF0, - slc_rxlink_dscr_bf1: SLC_RXLINK_DSCR_BF1, - slc_date: SLC_DATE, - slc_id: SLC_ID, -} -impl RegisterBlock { - #[doc = "0x00 - SLC_CONF0"] - #[inline(always)] - pub const fn slc_conf0(&self) -> &SLC_CONF0 { - &self.slc_conf0 - } - #[doc = "0x04 - SLC_INT_RAW"] - #[inline(always)] - pub const fn slc_int_raw(&self) -> &SLC_INT_RAW { - &self.slc_int_raw - } - #[doc = "0x08 - SLC_INT_STATUS"] - #[inline(always)] - pub const fn slc_int_status(&self) -> &SLC_INT_STATUS { - &self.slc_int_status - } - #[doc = "0x0c - SLC_INT_ENA"] - #[inline(always)] - pub const fn slc_int_ena(&self) -> &SLC_INT_ENA { - &self.slc_int_ena - } - #[doc = "0x10 - SLC_INT_CLR"] - #[inline(always)] - pub const fn slc_int_clr(&self) -> &SLC_INT_CLR { - &self.slc_int_clr - } - #[doc = "0x14 - SLC_RX_STATUS"] - #[inline(always)] - pub const fn slc_rx_status(&self) -> &SLC_RX_STATUS { - &self.slc_rx_status - } - #[doc = "0x18 - SLC_RX_FIFO_PUSH"] - #[inline(always)] - pub const fn slc_rx_fifo_push(&self) -> &SLC_RX_FIFO_PUSH { - &self.slc_rx_fifo_push - } - #[doc = "0x1c - SLC_TX_STATUS"] - #[inline(always)] - pub const fn slc_tx_status(&self) -> &SLC_TX_STATUS { - &self.slc_tx_status - } - #[doc = "0x20 - SLC_TX_FIFO_POP"] - #[inline(always)] - pub const fn slc_tx_fifo_pop(&self) -> &SLC_TX_FIFO_POP { - &self.slc_tx_fifo_pop - } - #[doc = "0x24 - SLC_RX_LINK"] - #[inline(always)] - pub const fn slc_rx_link(&self) -> &SLC_RX_LINK { - &self.slc_rx_link - } - #[doc = "0x28 - SLC_TX_LINK"] - #[inline(always)] - pub const fn slc_tx_link(&self) -> &SLC_TX_LINK { - &self.slc_tx_link - } - #[doc = "0x2c - SLC_INTVEC_TOHOST"] - #[inline(always)] - pub const fn slc_intvec_tohost(&self) -> &SLC_INTVEC_TOHOST { - &self.slc_intvec_tohost - } - #[doc = "0x30 - SLC_TOKEN0"] - #[inline(always)] - pub const fn slc_token0(&self) -> &SLC_TOKEN0 { - &self.slc_token0 - } - #[doc = "0x34 - SLC_TOKEN1"] - #[inline(always)] - pub const fn slc_token1(&self) -> &SLC_TOKEN1 { - &self.slc_token1 - } - #[doc = "0x38 - SLC_CONF1"] - #[inline(always)] - pub const fn slc_conf1(&self) -> &SLC_CONF1 { - &self.slc_conf1 - } - #[doc = "0x3c - SLC_STATE0"] - #[inline(always)] - pub const fn slc_state0(&self) -> &SLC_STATE0 { - &self.slc_state0 - } - #[doc = "0x40 - SLC_STATE1"] - #[inline(always)] - pub const fn slc_state1(&self) -> &SLC_STATE1 { - &self.slc_state1 - } - #[doc = "0x44 - SLC_BRIDGE_CONF"] - #[inline(always)] - pub const fn slc_bridge_conf(&self) -> &SLC_BRIDGE_CONF { - &self.slc_bridge_conf - } - #[doc = "0x48 - SLC_RX_EOF_DES_ADDR"] - #[inline(always)] - pub const fn slc_rx_eof_des_addr(&self) -> &SLC_RX_EOF_DES_ADDR { - &self.slc_rx_eof_des_addr - } - #[doc = "0x4c - SLC_TX_EOF_DES_ADDR"] - #[inline(always)] - pub const fn slc_tx_eof_des_addr(&self) -> &SLC_TX_EOF_DES_ADDR { - &self.slc_tx_eof_des_addr - } - #[doc = "0x50 - SLC_RX_EOF_BFR_DES_ADDR"] - #[inline(always)] - pub const fn slc_rx_eof_bfr_des_addr(&self) -> &SLC_RX_EOF_BFR_DES_ADDR { - &self.slc_rx_eof_bfr_des_addr - } - #[doc = "0x54 - SLC_AHB_TEST"] - #[inline(always)] - pub const fn slc_ahb_test(&self) -> &SLC_AHB_TEST { - &self.slc_ahb_test - } - #[doc = "0x58 - SLC_SDIO_ST"] - #[inline(always)] - pub const fn slc_sdio_st(&self) -> &SLC_SDIO_ST { - &self.slc_sdio_st - } - #[doc = "0x5c - SLC_RX_DSCR_CONF"] - #[inline(always)] - pub const fn slc_rx_dscr_conf(&self) -> &SLC_RX_DSCR_CONF { - &self.slc_rx_dscr_conf - } - #[doc = "0x60 - SLC_TXLINK_DSCR"] - #[inline(always)] - pub const fn slc_txlink_dscr(&self) -> &SLC_TXLINK_DSCR { - &self.slc_txlink_dscr - } - #[doc = "0x64 - SLC_TXLINK_DSCR_BF0"] - #[inline(always)] - pub const fn slc_txlink_dscr_bf0(&self) -> &SLC_TXLINK_DSCR_BF0 { - &self.slc_txlink_dscr_bf0 - } - #[doc = "0x68 - SLC_TXLINK_DSCR_BF1"] - #[inline(always)] - pub const fn slc_txlink_dscr_bf1(&self) -> &SLC_TXLINK_DSCR_BF1 { - &self.slc_txlink_dscr_bf1 - } - #[doc = "0x6c - SLC_RXLINK_DSCR"] - #[inline(always)] - pub const fn slc_rxlink_dscr(&self) -> &SLC_RXLINK_DSCR { - &self.slc_rxlink_dscr - } - #[doc = "0x70 - SLC_RXLINK_DSCR_BF0"] - #[inline(always)] - pub const fn slc_rxlink_dscr_bf0(&self) -> &SLC_RXLINK_DSCR_BF0 { - &self.slc_rxlink_dscr_bf0 - } - #[doc = "0x74 - SLC_RXLINK_DSCR_BF1"] - #[inline(always)] - pub const fn slc_rxlink_dscr_bf1(&self) -> &SLC_RXLINK_DSCR_BF1 { - &self.slc_rxlink_dscr_bf1 - } - #[doc = "0x78 - SLC_DATE"] - #[inline(always)] - pub const fn slc_date(&self) -> &SLC_DATE { - &self.slc_date - } - #[doc = "0x7c - SLC_ID"] - #[inline(always)] - pub const fn slc_id(&self) -> &SLC_ID { - &self.slc_id - } -} -#[doc = "SLC_CONF0 (rw) register accessor: SLC_CONF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_conf0`] module"] -pub type SLC_CONF0 = crate::Reg; -#[doc = "SLC_CONF0"] -pub mod slc_conf0; -#[doc = "SLC_INT_RAW (rw) register accessor: SLC_INT_RAW\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_int_raw`] module"] -pub type SLC_INT_RAW = crate::Reg; -#[doc = "SLC_INT_RAW"] -pub mod slc_int_raw; -#[doc = "SLC_INT_STATUS (rw) register accessor: SLC_INT_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_int_status`] module"] -pub type SLC_INT_STATUS = crate::Reg; -#[doc = "SLC_INT_STATUS"] -pub mod slc_int_status; -#[doc = "SLC_INT_ENA (rw) register accessor: SLC_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_int_ena`] module"] -pub type SLC_INT_ENA = crate::Reg; -#[doc = "SLC_INT_ENA"] -pub mod slc_int_ena; -#[doc = "SLC_INT_CLR (rw) register accessor: SLC_INT_CLR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_int_clr`] module"] -pub type SLC_INT_CLR = crate::Reg; -#[doc = "SLC_INT_CLR"] -pub mod slc_int_clr; -#[doc = "SLC_RX_STATUS (rw) register accessor: SLC_RX_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_status`] module"] -pub type SLC_RX_STATUS = crate::Reg; -#[doc = "SLC_RX_STATUS"] -pub mod slc_rx_status; -#[doc = "SLC_RX_FIFO_PUSH (rw) register accessor: SLC_RX_FIFO_PUSH\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_fifo_push::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_fifo_push::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_fifo_push`] module"] -pub type SLC_RX_FIFO_PUSH = crate::Reg; -#[doc = "SLC_RX_FIFO_PUSH"] -pub mod slc_rx_fifo_push; -#[doc = "SLC_TX_STATUS (rw) register accessor: SLC_TX_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_tx_status`] module"] -pub type SLC_TX_STATUS = crate::Reg; -#[doc = "SLC_TX_STATUS"] -pub mod slc_tx_status; -#[doc = "SLC_TX_FIFO_POP (rw) register accessor: SLC_TX_FIFO_POP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_fifo_pop::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_fifo_pop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_tx_fifo_pop`] module"] -pub type SLC_TX_FIFO_POP = crate::Reg; -#[doc = "SLC_TX_FIFO_POP"] -pub mod slc_tx_fifo_pop; -#[doc = "SLC_RX_LINK (rw) register accessor: SLC_RX_LINK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_link::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_link::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_link`] module"] -pub type SLC_RX_LINK = crate::Reg; -#[doc = "SLC_RX_LINK"] -pub mod slc_rx_link; -#[doc = "SLC_TX_LINK (rw) register accessor: SLC_TX_LINK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_link::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_link::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_tx_link`] module"] -pub type SLC_TX_LINK = crate::Reg; -#[doc = "SLC_TX_LINK"] -pub mod slc_tx_link; -#[doc = "SLC_INTVEC_TOHOST (rw) register accessor: SLC_INTVEC_TOHOST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_intvec_tohost::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_intvec_tohost::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_intvec_tohost`] module"] -pub type SLC_INTVEC_TOHOST = crate::Reg; -#[doc = "SLC_INTVEC_TOHOST"] -pub mod slc_intvec_tohost; -#[doc = "SLC_TOKEN0 (rw) register accessor: SLC_TOKEN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_token0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_token0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_token0`] module"] -pub type SLC_TOKEN0 = crate::Reg; -#[doc = "SLC_TOKEN0"] -pub mod slc_token0; -#[doc = "SLC_TOKEN1 (rw) register accessor: SLC_TOKEN1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_token1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_token1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_token1`] module"] -pub type SLC_TOKEN1 = crate::Reg; -#[doc = "SLC_TOKEN1"] -pub mod slc_token1; -#[doc = "SLC_CONF1 (rw) register accessor: SLC_CONF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_conf1`] module"] -pub type SLC_CONF1 = crate::Reg; -#[doc = "SLC_CONF1"] -pub mod slc_conf1; -#[doc = "SLC_STATE0 (rw) register accessor: SLC_STATE0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_state0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_state0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_state0`] module"] -pub type SLC_STATE0 = crate::Reg; -#[doc = "SLC_STATE0"] -pub mod slc_state0; -#[doc = "SLC_STATE1 (rw) register accessor: SLC_STATE1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_state1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_state1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_state1`] module"] -pub type SLC_STATE1 = crate::Reg; -#[doc = "SLC_STATE1"] -pub mod slc_state1; -#[doc = "SLC_BRIDGE_CONF (rw) register accessor: SLC_BRIDGE_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_bridge_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_bridge_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_bridge_conf`] module"] -pub type SLC_BRIDGE_CONF = crate::Reg; -#[doc = "SLC_BRIDGE_CONF"] -pub mod slc_bridge_conf; -#[doc = "SLC_RX_EOF_DES_ADDR (rw) register accessor: SLC_RX_EOF_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_eof_des_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_eof_des_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_eof_des_addr`] module"] -pub type SLC_RX_EOF_DES_ADDR = crate::Reg; -#[doc = "SLC_RX_EOF_DES_ADDR"] -pub mod slc_rx_eof_des_addr; -#[doc = "SLC_TX_EOF_DES_ADDR (rw) register accessor: SLC_TX_EOF_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_eof_des_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_eof_des_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_tx_eof_des_addr`] module"] -pub type SLC_TX_EOF_DES_ADDR = crate::Reg; -#[doc = "SLC_TX_EOF_DES_ADDR"] -pub mod slc_tx_eof_des_addr; -#[doc = "SLC_RX_EOF_BFR_DES_ADDR (rw) register accessor: SLC_RX_EOF_BFR_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_eof_bfr_des_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_eof_bfr_des_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_eof_bfr_des_addr`] module"] -pub type SLC_RX_EOF_BFR_DES_ADDR = - crate::Reg; -#[doc = "SLC_RX_EOF_BFR_DES_ADDR"] -pub mod slc_rx_eof_bfr_des_addr; -#[doc = "SLC_AHB_TEST (rw) register accessor: SLC_AHB_TEST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_ahb_test::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_ahb_test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_ahb_test`] module"] -pub type SLC_AHB_TEST = crate::Reg; -#[doc = "SLC_AHB_TEST"] -pub mod slc_ahb_test; -#[doc = "SLC_SDIO_ST (rw) register accessor: SLC_SDIO_ST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_sdio_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_sdio_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_sdio_st`] module"] -pub type SLC_SDIO_ST = crate::Reg; -#[doc = "SLC_SDIO_ST"] -pub mod slc_sdio_st; -#[doc = "SLC_RX_DSCR_CONF (rw) register accessor: SLC_RX_DSCR_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_dscr_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_dscr_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_dscr_conf`] module"] -pub type SLC_RX_DSCR_CONF = crate::Reg; -#[doc = "SLC_RX_DSCR_CONF"] -pub mod slc_rx_dscr_conf; -#[doc = "SLC_TXLINK_DSCR (rw) register accessor: SLC_TXLINK_DSCR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_txlink_dscr`] module"] -pub type SLC_TXLINK_DSCR = crate::Reg; -#[doc = "SLC_TXLINK_DSCR"] -pub mod slc_txlink_dscr; -#[doc = "SLC_TXLINK_DSCR_BF0 (rw) register accessor: SLC_TXLINK_DSCR_BF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr_bf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr_bf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_txlink_dscr_bf0`] module"] -pub type SLC_TXLINK_DSCR_BF0 = crate::Reg; -#[doc = "SLC_TXLINK_DSCR_BF0"] -pub mod slc_txlink_dscr_bf0; -#[doc = "SLC_TXLINK_DSCR_BF1 (rw) register accessor: SLC_TXLINK_DSCR_BF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr_bf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr_bf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_txlink_dscr_bf1`] module"] -pub type SLC_TXLINK_DSCR_BF1 = crate::Reg; -#[doc = "SLC_TXLINK_DSCR_BF1"] -pub mod slc_txlink_dscr_bf1; -#[doc = "SLC_RXLINK_DSCR (rw) register accessor: SLC_RXLINK_DSCR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rxlink_dscr`] module"] -pub type SLC_RXLINK_DSCR = crate::Reg; -#[doc = "SLC_RXLINK_DSCR"] -pub mod slc_rxlink_dscr; -#[doc = "SLC_RXLINK_DSCR_BF0 (rw) register accessor: SLC_RXLINK_DSCR_BF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr_bf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr_bf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rxlink_dscr_bf0`] module"] -pub type SLC_RXLINK_DSCR_BF0 = crate::Reg; -#[doc = "SLC_RXLINK_DSCR_BF0"] -pub mod slc_rxlink_dscr_bf0; -#[doc = "SLC_RXLINK_DSCR_BF1 (rw) register accessor: SLC_RXLINK_DSCR_BF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr_bf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr_bf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rxlink_dscr_bf1`] module"] -pub type SLC_RXLINK_DSCR_BF1 = crate::Reg; -#[doc = "SLC_RXLINK_DSCR_BF1"] -pub mod slc_rxlink_dscr_bf1; -#[doc = "SLC_DATE (rw) register accessor: SLC_DATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_date`] module"] -pub type SLC_DATE = crate::Reg; -#[doc = "SLC_DATE"] -pub mod slc_date; -#[doc = "SLC_ID (rw) register accessor: SLC_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_id`] module"] -pub type SLC_ID = crate::Reg; -#[doc = "SLC_ID"] -pub mod slc_id; diff --git a/esp8266/src/slc/slc_ahb_test.rs b/esp8266/src/slc/slc_ahb_test.rs deleted file mode 100644 index 5421fc7ac9..0000000000 --- a/esp8266/src/slc/slc_ahb_test.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SLC_AHB_TEST` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_AHB_TEST` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_AHB_TESTMODE` reader - "] -pub type SLC_AHB_TESTMODE_R = crate::FieldReader; -#[doc = "Field `SLC_AHB_TESTMODE` writer - "] -pub type SLC_AHB_TESTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `SLC_AHB_TESTADDR` reader - "] -pub type SLC_AHB_TESTADDR_R = crate::FieldReader; -#[doc = "Field `SLC_AHB_TESTADDR` writer - "] -pub type SLC_AHB_TESTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:2"] - #[inline(always)] - pub fn slc_ahb_testmode(&self) -> SLC_AHB_TESTMODE_R { - SLC_AHB_TESTMODE_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 4:5"] - #[inline(always)] - pub fn slc_ahb_testaddr(&self) -> SLC_AHB_TESTADDR_R { - SLC_AHB_TESTADDR_R::new(((self.bits >> 4) & 3) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_AHB_TEST") - .field( - "slc_ahb_testaddr", - &format_args!("{}", self.slc_ahb_testaddr().bits()), - ) - .field( - "slc_ahb_testmode", - &format_args!("{}", self.slc_ahb_testmode().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:2"] - #[inline(always)] - #[must_use] - pub fn slc_ahb_testmode(&mut self) -> SLC_AHB_TESTMODE_W { - SLC_AHB_TESTMODE_W::new(self, 0) - } - #[doc = "Bits 4:5"] - #[inline(always)] - #[must_use] - pub fn slc_ahb_testaddr(&mut self) -> SLC_AHB_TESTADDR_W { - SLC_AHB_TESTADDR_W::new(self, 4) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_AHB_TEST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_ahb_test::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_ahb_test::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_AHB_TEST_SPEC; -impl crate::RegisterSpec for SLC_AHB_TEST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_ahb_test::R`](R) reader structure"] -impl crate::Readable for SLC_AHB_TEST_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_ahb_test::W`](W) writer structure"] -impl crate::Writable for SLC_AHB_TEST_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_AHB_TEST to value 0"] -impl crate::Resettable for SLC_AHB_TEST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_bridge_conf.rs b/esp8266/src/slc/slc_bridge_conf.rs deleted file mode 100644 index b76d807ea1..0000000000 --- a/esp8266/src/slc/slc_bridge_conf.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SLC_BRIDGE_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_BRIDGE_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TXEOF_ENA` reader - "] -pub type SLC_TXEOF_ENA_R = crate::FieldReader; -#[doc = "Field `SLC_TXEOF_ENA` writer - "] -pub type SLC_TXEOF_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `SLC_FIFO_MAP_ENA` reader - "] -pub type SLC_FIFO_MAP_ENA_R = crate::FieldReader; -#[doc = "Field `SLC_FIFO_MAP_ENA` writer - "] -pub type SLC_FIFO_MAP_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `SLC_TX_DUMMY_MODE` reader - "] -pub type SLC_TX_DUMMY_MODE_R = crate::BitReader; -#[doc = "Field `SLC_TX_DUMMY_MODE` writer - "] -pub type SLC_TX_DUMMY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_PUSH_IDLE_NUM` reader - "] -pub type SLC_TX_PUSH_IDLE_NUM_R = crate::FieldReader; -#[doc = "Field `SLC_TX_PUSH_IDLE_NUM` writer - "] -pub type SLC_TX_PUSH_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:5"] - #[inline(always)] - pub fn slc_txeof_ena(&self) -> SLC_TXEOF_ENA_R { - SLC_TXEOF_ENA_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 8:11"] - #[inline(always)] - pub fn slc_fifo_map_ena(&self) -> SLC_FIFO_MAP_ENA_R { - SLC_FIFO_MAP_ENA_R::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_tx_dummy_mode(&self) -> SLC_TX_DUMMY_MODE_R { - SLC_TX_DUMMY_MODE_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bits 16:31"] - #[inline(always)] - pub fn slc_tx_push_idle_num(&self) -> SLC_TX_PUSH_IDLE_NUM_R { - SLC_TX_PUSH_IDLE_NUM_R::new(((self.bits >> 16) & 0xffff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_BRIDGE_CONF") - .field( - "slc_tx_push_idle_num", - &format_args!("{}", self.slc_tx_push_idle_num().bits()), - ) - .field( - "slc_tx_dummy_mode", - &format_args!("{}", self.slc_tx_dummy_mode().bit()), - ) - .field( - "slc_fifo_map_ena", - &format_args!("{}", self.slc_fifo_map_ena().bits()), - ) - .field( - "slc_txeof_ena", - &format_args!("{}", self.slc_txeof_ena().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:5"] - #[inline(always)] - #[must_use] - pub fn slc_txeof_ena(&mut self) -> SLC_TXEOF_ENA_W { - SLC_TXEOF_ENA_W::new(self, 0) - } - #[doc = "Bits 8:11"] - #[inline(always)] - #[must_use] - pub fn slc_fifo_map_ena(&mut self) -> SLC_FIFO_MAP_ENA_W { - SLC_FIFO_MAP_ENA_W::new(self, 8) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dummy_mode(&mut self) -> SLC_TX_DUMMY_MODE_W { - SLC_TX_DUMMY_MODE_W::new(self, 12) - } - #[doc = "Bits 16:31"] - #[inline(always)] - #[must_use] - pub fn slc_tx_push_idle_num(&mut self) -> SLC_TX_PUSH_IDLE_NUM_W { - SLC_TX_PUSH_IDLE_NUM_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_BRIDGE_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_bridge_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_bridge_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_BRIDGE_CONF_SPEC; -impl crate::RegisterSpec for SLC_BRIDGE_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_bridge_conf::R`](R) reader structure"] -impl crate::Readable for SLC_BRIDGE_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_bridge_conf::W`](W) writer structure"] -impl crate::Writable for SLC_BRIDGE_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_BRIDGE_CONF to value 0"] -impl crate::Resettable for SLC_BRIDGE_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_conf0.rs b/esp8266/src/slc/slc_conf0.rs deleted file mode 100644 index 739fd14c29..0000000000 --- a/esp8266/src/slc/slc_conf0.rs +++ /dev/null @@ -1,253 +0,0 @@ -#[doc = "Register `SLC_CONF0` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_CONF0` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TXLINK_RST` reader - "] -pub type SLC_TXLINK_RST_R = crate::BitReader; -#[doc = "Field `SLC_TXLINK_RST` writer - "] -pub type SLC_TXLINK_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RXLINK_RST` reader - "] -pub type SLC_RXLINK_RST_R = crate::BitReader; -#[doc = "Field `SLC_RXLINK_RST` writer - "] -pub type SLC_RXLINK_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_AHBM_FIFO_RST` reader - "] -pub type SLC_AHBM_FIFO_RST_R = crate::BitReader; -#[doc = "Field `SLC_AHBM_FIFO_RST` writer - "] -pub type SLC_AHBM_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_AHBM_RST` reader - "] -pub type SLC_AHBM_RST_R = crate::BitReader; -#[doc = "Field `SLC_AHBM_RST` writer - "] -pub type SLC_AHBM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_LOOP_TEST` reader - "] -pub type SLC_TX_LOOP_TEST_R = crate::BitReader; -#[doc = "Field `SLC_TX_LOOP_TEST` writer - "] -pub type SLC_TX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_LOOP_TEST` reader - "] -pub type SLC_RX_LOOP_TEST_R = crate::BitReader; -#[doc = "Field `SLC_RX_LOOP_TEST` writer - "] -pub type SLC_RX_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_AUTO_WRBACK` reader - "] -pub type SLC_RX_AUTO_WRBACK_R = crate::BitReader; -#[doc = "Field `SLC_RX_AUTO_WRBACK` writer - "] -pub type SLC_RX_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_NO_RESTART_CLR` reader - "] -pub type SLC_RX_NO_RESTART_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_NO_RESTART_CLR` writer - "] -pub type SLC_RX_NO_RESTART_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_DSCR_BURST_EN` reader - "] -pub type SLC_DSCR_BURST_EN_R = crate::BitReader; -#[doc = "Field `SLC_DSCR_BURST_EN` writer - "] -pub type SLC_DSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_DATA_BURST_EN` reader - "] -pub type SLC_DATA_BURST_EN_R = crate::BitReader; -#[doc = "Field `SLC_DATA_BURST_EN` writer - "] -pub type SLC_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_MODE` reader - "] -pub type SLC_MODE_R = crate::FieldReader; -#[doc = "Field `SLC_MODE` writer - "] -pub type SLC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_txlink_rst(&self) -> SLC_TXLINK_RST_R { - SLC_TXLINK_RST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_rxlink_rst(&self) -> SLC_RXLINK_RST_R { - SLC_RXLINK_RST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn slc_ahbm_fifo_rst(&self) -> SLC_AHBM_FIFO_RST_R { - SLC_AHBM_FIFO_RST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn slc_ahbm_rst(&self) -> SLC_AHBM_RST_R { - SLC_AHBM_RST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn slc_tx_loop_test(&self) -> SLC_TX_LOOP_TEST_R { - SLC_TX_LOOP_TEST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn slc_rx_loop_test(&self) -> SLC_RX_LOOP_TEST_R { - SLC_RX_LOOP_TEST_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn slc_rx_auto_wrback(&self) -> SLC_RX_AUTO_WRBACK_R { - SLC_RX_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn slc_rx_no_restart_clr(&self) -> SLC_RX_NO_RESTART_CLR_R { - SLC_RX_NO_RESTART_CLR_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_dscr_burst_en(&self) -> SLC_DSCR_BURST_EN_R { - SLC_DSCR_BURST_EN_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_data_burst_en(&self) -> SLC_DATA_BURST_EN_R { - SLC_DATA_BURST_EN_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 12:13"] - #[inline(always)] - pub fn slc_mode(&self) -> SLC_MODE_R { - SLC_MODE_R::new(((self.bits >> 12) & 3) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_CONF0") - .field("slc_mode", &format_args!("{}", self.slc_mode().bits())) - .field( - "slc_data_burst_en", - &format_args!("{}", self.slc_data_burst_en().bit()), - ) - .field( - "slc_dscr_burst_en", - &format_args!("{}", self.slc_dscr_burst_en().bit()), - ) - .field( - "slc_rx_no_restart_clr", - &format_args!("{}", self.slc_rx_no_restart_clr().bit()), - ) - .field( - "slc_rx_auto_wrback", - &format_args!("{}", self.slc_rx_auto_wrback().bit()), - ) - .field( - "slc_rx_loop_test", - &format_args!("{}", self.slc_rx_loop_test().bit()), - ) - .field( - "slc_tx_loop_test", - &format_args!("{}", self.slc_tx_loop_test().bit()), - ) - .field( - "slc_ahbm_rst", - &format_args!("{}", self.slc_ahbm_rst().bit()), - ) - .field( - "slc_ahbm_fifo_rst", - &format_args!("{}", self.slc_ahbm_fifo_rst().bit()), - ) - .field( - "slc_rxlink_rst", - &format_args!("{}", self.slc_rxlink_rst().bit()), - ) - .field( - "slc_txlink_rst", - &format_args!("{}", self.slc_txlink_rst().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_rst(&mut self) -> SLC_TXLINK_RST_W { - SLC_TXLINK_RST_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_rst(&mut self) -> SLC_RXLINK_RST_W { - SLC_RXLINK_RST_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn slc_ahbm_fifo_rst(&mut self) -> SLC_AHBM_FIFO_RST_W { - SLC_AHBM_FIFO_RST_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn slc_ahbm_rst(&mut self) -> SLC_AHBM_RST_W { - SLC_AHBM_RST_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn slc_tx_loop_test(&mut self) -> SLC_TX_LOOP_TEST_W { - SLC_TX_LOOP_TEST_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn slc_rx_loop_test(&mut self) -> SLC_RX_LOOP_TEST_W { - SLC_RX_LOOP_TEST_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn slc_rx_auto_wrback(&mut self) -> SLC_RX_AUTO_WRBACK_W { - SLC_RX_AUTO_WRBACK_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn slc_rx_no_restart_clr(&mut self) -> SLC_RX_NO_RESTART_CLR_W { - SLC_RX_NO_RESTART_CLR_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_dscr_burst_en(&mut self) -> SLC_DSCR_BURST_EN_W { - SLC_DSCR_BURST_EN_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_data_burst_en(&mut self) -> SLC_DATA_BURST_EN_W { - SLC_DATA_BURST_EN_W::new(self, 9) - } - #[doc = "Bits 12:13"] - #[inline(always)] - #[must_use] - pub fn slc_mode(&mut self) -> SLC_MODE_W { - SLC_MODE_W::new(self, 12) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_CONF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_CONF0_SPEC; -impl crate::RegisterSpec for SLC_CONF0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_conf0::R`](R) reader structure"] -impl crate::Readable for SLC_CONF0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_conf0::W`](W) writer structure"] -impl crate::Writable for SLC_CONF0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_CONF0 to value 0"] -impl crate::Resettable for SLC_CONF0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_conf1.rs b/esp8266/src/slc/slc_conf1.rs deleted file mode 100644 index 8331bab423..0000000000 --- a/esp8266/src/slc/slc_conf1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_CONF1` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_CONF1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_CONF1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_CONF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_CONF1_SPEC; -impl crate::RegisterSpec for SLC_CONF1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_conf1::R`](R) reader structure"] -impl crate::Readable for SLC_CONF1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_conf1::W`](W) writer structure"] -impl crate::Writable for SLC_CONF1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_CONF1 to value 0"] -impl crate::Resettable for SLC_CONF1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_date.rs b/esp8266/src/slc/slc_date.rs deleted file mode 100644 index df05dd1f9a..0000000000 --- a/esp8266/src/slc/slc_date.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_DATE` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_DATE` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_DATE") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_DATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_DATE_SPEC; -impl crate::RegisterSpec for SLC_DATE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_date::R`](R) reader structure"] -impl crate::Readable for SLC_DATE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_date::W`](W) writer structure"] -impl crate::Writable for SLC_DATE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_DATE to value 0"] -impl crate::Resettable for SLC_DATE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_id.rs b/esp8266/src/slc/slc_id.rs deleted file mode 100644 index 71b949090d..0000000000 --- a/esp8266/src/slc/slc_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_ID` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_ID` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_ID") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_ID_SPEC; -impl crate::RegisterSpec for SLC_ID_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_id::R`](R) reader structure"] -impl crate::Readable for SLC_ID_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_id::W`](W) writer structure"] -impl crate::Writable for SLC_ID_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_ID to value 0"] -impl crate::Resettable for SLC_ID_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_int_clr.rs b/esp8266/src/slc/slc_int_clr.rs deleted file mode 100644 index e8882e211f..0000000000 --- a/esp8266/src/slc/slc_int_clr.rs +++ /dev/null @@ -1,465 +0,0 @@ -#[doc = "Register `SLC_INT_CLR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_INT_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_FRHOST_BIT0_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT0_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT0_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT1_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT1_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT1_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT2_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT2_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT2_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT3_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT3_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT3_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT4_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT4_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT4_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT5_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT5_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT5_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT6_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT6_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT6_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT6_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT7_INT_CLR` reader - "] -pub type SLC_FRHOST_BIT7_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT7_INT_CLR` writer - "] -pub type SLC_FRHOST_BIT7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_START_INT_CLR` reader - "] -pub type SLC_RX_START_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_START_INT_CLR` writer - "] -pub type SLC_RX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_START_INT_CLR` reader - "] -pub type SLC_TX_START_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_START_INT_CLR` writer - "] -pub type SLC_TX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_UDF_INT_CLR` reader - "] -pub type SLC_RX_UDF_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_UDF_INT_CLR` writer - "] -pub type SLC_RX_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_OVF_INT_CLR` reader - "] -pub type SLC_TX_OVF_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_OVF_INT_CLR` writer - "] -pub type SLC_TX_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_CLR` reader - "] -pub type SLC_TOKEN0_1TO0_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_CLR` writer - "] -pub type SLC_TOKEN0_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_CLR` reader - "] -pub type SLC_TOKEN1_1TO0_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_CLR` writer - "] -pub type SLC_TOKEN1_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DONE_INT_CLR` reader - "] -pub type SLC_TX_DONE_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_DONE_INT_CLR` writer - "] -pub type SLC_TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_EOF_INT_CLR` reader - "] -pub type SLC_TX_EOF_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_EOF_INT_CLR` writer - "] -pub type SLC_TX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DONE_INT_CLR` reader - "] -pub type SLC_RX_DONE_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_DONE_INT_CLR` writer - "] -pub type SLC_RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_EOF_INT_CLR` reader - "] -pub type SLC_RX_EOF_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_EOF_INT_CLR` writer - "] -pub type SLC_RX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOHOST_INT_CLR` reader - "] -pub type SLC_TOHOST_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TOHOST_INT_CLR` writer - "] -pub type SLC_TOHOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_CLR` reader - "] -pub type SLC_TX_DSCR_ERR_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_CLR` writer - "] -pub type SLC_TX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_CLR` reader - "] -pub type SLC_RX_DSCR_ERR_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_CLR` writer - "] -pub type SLC_RX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_CLR` reader - "] -pub type SLC_TX_DSCR_EMPTY_INT_CLR_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_CLR` writer - "] -pub type SLC_TX_DSCR_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_frhost_bit0_int_clr(&self) -> SLC_FRHOST_BIT0_INT_CLR_R { - SLC_FRHOST_BIT0_INT_CLR_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_frhost_bit1_int_clr(&self) -> SLC_FRHOST_BIT1_INT_CLR_R { - SLC_FRHOST_BIT1_INT_CLR_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn slc_frhost_bit2_int_clr(&self) -> SLC_FRHOST_BIT2_INT_CLR_R { - SLC_FRHOST_BIT2_INT_CLR_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn slc_frhost_bit3_int_clr(&self) -> SLC_FRHOST_BIT3_INT_CLR_R { - SLC_FRHOST_BIT3_INT_CLR_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn slc_frhost_bit4_int_clr(&self) -> SLC_FRHOST_BIT4_INT_CLR_R { - SLC_FRHOST_BIT4_INT_CLR_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn slc_frhost_bit5_int_clr(&self) -> SLC_FRHOST_BIT5_INT_CLR_R { - SLC_FRHOST_BIT5_INT_CLR_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn slc_frhost_bit6_int_clr(&self) -> SLC_FRHOST_BIT6_INT_CLR_R { - SLC_FRHOST_BIT6_INT_CLR_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn slc_frhost_bit7_int_clr(&self) -> SLC_FRHOST_BIT7_INT_CLR_R { - SLC_FRHOST_BIT7_INT_CLR_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_rx_start_int_clr(&self) -> SLC_RX_START_INT_CLR_R { - SLC_RX_START_INT_CLR_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_tx_start_int_clr(&self) -> SLC_TX_START_INT_CLR_R { - SLC_TX_START_INT_CLR_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10"] - #[inline(always)] - pub fn slc_rx_udf_int_clr(&self) -> SLC_RX_UDF_INT_CLR_R { - SLC_RX_UDF_INT_CLR_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11"] - #[inline(always)] - pub fn slc_tx_ovf_int_clr(&self) -> SLC_TX_OVF_INT_CLR_R { - SLC_TX_OVF_INT_CLR_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token0_1to0_int_clr(&self) -> SLC_TOKEN0_1TO0_INT_CLR_R { - SLC_TOKEN0_1TO0_INT_CLR_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token1_1to0_int_clr(&self) -> SLC_TOKEN1_1TO0_INT_CLR_R { - SLC_TOKEN1_1TO0_INT_CLR_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_tx_done_int_clr(&self) -> SLC_TX_DONE_INT_CLR_R { - SLC_TX_DONE_INT_CLR_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15"] - #[inline(always)] - pub fn slc_tx_eof_int_clr(&self) -> SLC_TX_EOF_INT_CLR_R { - SLC_TX_EOF_INT_CLR_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_rx_done_int_clr(&self) -> SLC_RX_DONE_INT_CLR_R { - SLC_RX_DONE_INT_CLR_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17"] - #[inline(always)] - pub fn slc_rx_eof_int_clr(&self) -> SLC_RX_EOF_INT_CLR_R { - SLC_RX_EOF_INT_CLR_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18"] - #[inline(always)] - pub fn slc_tohost_int_clr(&self) -> SLC_TOHOST_INT_CLR_R { - SLC_TOHOST_INT_CLR_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn slc_tx_dscr_err_int_clr(&self) -> SLC_TX_DSCR_ERR_INT_CLR_R { - SLC_TX_DSCR_ERR_INT_CLR_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn slc_rx_dscr_err_int_clr(&self) -> SLC_RX_DSCR_ERR_INT_CLR_R { - SLC_RX_DSCR_ERR_INT_CLR_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn slc_tx_dscr_empty_int_clr(&self) -> SLC_TX_DSCR_EMPTY_INT_CLR_R { - SLC_TX_DSCR_EMPTY_INT_CLR_R::new(((self.bits >> 21) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_INT_CLR") - .field( - "slc_tx_dscr_empty_int_clr", - &format_args!("{}", self.slc_tx_dscr_empty_int_clr().bit()), - ) - .field( - "slc_rx_dscr_err_int_clr", - &format_args!("{}", self.slc_rx_dscr_err_int_clr().bit()), - ) - .field( - "slc_tx_dscr_err_int_clr", - &format_args!("{}", self.slc_tx_dscr_err_int_clr().bit()), - ) - .field( - "slc_tohost_int_clr", - &format_args!("{}", self.slc_tohost_int_clr().bit()), - ) - .field( - "slc_rx_eof_int_clr", - &format_args!("{}", self.slc_rx_eof_int_clr().bit()), - ) - .field( - "slc_rx_done_int_clr", - &format_args!("{}", self.slc_rx_done_int_clr().bit()), - ) - .field( - "slc_tx_eof_int_clr", - &format_args!("{}", self.slc_tx_eof_int_clr().bit()), - ) - .field( - "slc_tx_done_int_clr", - &format_args!("{}", self.slc_tx_done_int_clr().bit()), - ) - .field( - "slc_token1_1to0_int_clr", - &format_args!("{}", self.slc_token1_1to0_int_clr().bit()), - ) - .field( - "slc_token0_1to0_int_clr", - &format_args!("{}", self.slc_token0_1to0_int_clr().bit()), - ) - .field( - "slc_tx_ovf_int_clr", - &format_args!("{}", self.slc_tx_ovf_int_clr().bit()), - ) - .field( - "slc_rx_udf_int_clr", - &format_args!("{}", self.slc_rx_udf_int_clr().bit()), - ) - .field( - "slc_tx_start_int_clr", - &format_args!("{}", self.slc_tx_start_int_clr().bit()), - ) - .field( - "slc_rx_start_int_clr", - &format_args!("{}", self.slc_rx_start_int_clr().bit()), - ) - .field( - "slc_frhost_bit7_int_clr", - &format_args!("{}", self.slc_frhost_bit7_int_clr().bit()), - ) - .field( - "slc_frhost_bit6_int_clr", - &format_args!("{}", self.slc_frhost_bit6_int_clr().bit()), - ) - .field( - "slc_frhost_bit5_int_clr", - &format_args!("{}", self.slc_frhost_bit5_int_clr().bit()), - ) - .field( - "slc_frhost_bit4_int_clr", - &format_args!("{}", self.slc_frhost_bit4_int_clr().bit()), - ) - .field( - "slc_frhost_bit3_int_clr", - &format_args!("{}", self.slc_frhost_bit3_int_clr().bit()), - ) - .field( - "slc_frhost_bit2_int_clr", - &format_args!("{}", self.slc_frhost_bit2_int_clr().bit()), - ) - .field( - "slc_frhost_bit1_int_clr", - &format_args!("{}", self.slc_frhost_bit1_int_clr().bit()), - ) - .field( - "slc_frhost_bit0_int_clr", - &format_args!("{}", self.slc_frhost_bit0_int_clr().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit0_int_clr(&mut self) -> SLC_FRHOST_BIT0_INT_CLR_W { - SLC_FRHOST_BIT0_INT_CLR_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit1_int_clr(&mut self) -> SLC_FRHOST_BIT1_INT_CLR_W { - SLC_FRHOST_BIT1_INT_CLR_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit2_int_clr(&mut self) -> SLC_FRHOST_BIT2_INT_CLR_W { - SLC_FRHOST_BIT2_INT_CLR_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit3_int_clr(&mut self) -> SLC_FRHOST_BIT3_INT_CLR_W { - SLC_FRHOST_BIT3_INT_CLR_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit4_int_clr(&mut self) -> SLC_FRHOST_BIT4_INT_CLR_W { - SLC_FRHOST_BIT4_INT_CLR_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit5_int_clr(&mut self) -> SLC_FRHOST_BIT5_INT_CLR_W { - SLC_FRHOST_BIT5_INT_CLR_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit6_int_clr(&mut self) -> SLC_FRHOST_BIT6_INT_CLR_W { - SLC_FRHOST_BIT6_INT_CLR_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit7_int_clr(&mut self) -> SLC_FRHOST_BIT7_INT_CLR_W { - SLC_FRHOST_BIT7_INT_CLR_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_rx_start_int_clr(&mut self) -> SLC_RX_START_INT_CLR_W { - SLC_RX_START_INT_CLR_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_tx_start_int_clr(&mut self) -> SLC_TX_START_INT_CLR_W { - SLC_TX_START_INT_CLR_W::new(self, 9) - } - #[doc = "Bit 10"] - #[inline(always)] - #[must_use] - pub fn slc_rx_udf_int_clr(&mut self) -> SLC_RX_UDF_INT_CLR_W { - SLC_RX_UDF_INT_CLR_W::new(self, 10) - } - #[doc = "Bit 11"] - #[inline(always)] - #[must_use] - pub fn slc_tx_ovf_int_clr(&mut self) -> SLC_TX_OVF_INT_CLR_W { - SLC_TX_OVF_INT_CLR_W::new(self, 11) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token0_1to0_int_clr(&mut self) -> SLC_TOKEN0_1TO0_INT_CLR_W { - SLC_TOKEN0_1TO0_INT_CLR_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token1_1to0_int_clr(&mut self) -> SLC_TOKEN1_1TO0_INT_CLR_W { - SLC_TOKEN1_1TO0_INT_CLR_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_tx_done_int_clr(&mut self) -> SLC_TX_DONE_INT_CLR_W { - SLC_TX_DONE_INT_CLR_W::new(self, 14) - } - #[doc = "Bit 15"] - #[inline(always)] - #[must_use] - pub fn slc_tx_eof_int_clr(&mut self) -> SLC_TX_EOF_INT_CLR_W { - SLC_TX_EOF_INT_CLR_W::new(self, 15) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_rx_done_int_clr(&mut self) -> SLC_RX_DONE_INT_CLR_W { - SLC_RX_DONE_INT_CLR_W::new(self, 16) - } - #[doc = "Bit 17"] - #[inline(always)] - #[must_use] - pub fn slc_rx_eof_int_clr(&mut self) -> SLC_RX_EOF_INT_CLR_W { - SLC_RX_EOF_INT_CLR_W::new(self, 17) - } - #[doc = "Bit 18"] - #[inline(always)] - #[must_use] - pub fn slc_tohost_int_clr(&mut self) -> SLC_TOHOST_INT_CLR_W { - SLC_TOHOST_INT_CLR_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_err_int_clr(&mut self) -> SLC_TX_DSCR_ERR_INT_CLR_W { - SLC_TX_DSCR_ERR_INT_CLR_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn slc_rx_dscr_err_int_clr(&mut self) -> SLC_RX_DSCR_ERR_INT_CLR_W { - SLC_RX_DSCR_ERR_INT_CLR_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_empty_int_clr(&mut self) -> SLC_TX_DSCR_EMPTY_INT_CLR_W { - SLC_TX_DSCR_EMPTY_INT_CLR_W::new(self, 21) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_INT_CLR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_INT_CLR_SPEC; -impl crate::RegisterSpec for SLC_INT_CLR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_int_clr::R`](R) reader structure"] -impl crate::Readable for SLC_INT_CLR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_int_clr::W`](W) writer structure"] -impl crate::Writable for SLC_INT_CLR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_INT_CLR to value 0"] -impl crate::Resettable for SLC_INT_CLR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_int_ena.rs b/esp8266/src/slc/slc_int_ena.rs deleted file mode 100644 index ed40c34fa9..0000000000 --- a/esp8266/src/slc/slc_int_ena.rs +++ /dev/null @@ -1,465 +0,0 @@ -#[doc = "Register `SLC_INT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_INT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_FRHOST_BIT0_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT0_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT0_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT1_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT1_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT1_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT2_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT2_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT2_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT3_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT3_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT3_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT4_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT4_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT4_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT5_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT5_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT5_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT6_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT6_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT6_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT6_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT7_INT_ENA` reader - "] -pub type SLC_FRHOST_BIT7_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT7_INT_ENA` writer - "] -pub type SLC_FRHOST_BIT7_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_START_INT_ENA` reader - "] -pub type SLC_RX_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_RX_START_INT_ENA` writer - "] -pub type SLC_RX_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_START_INT_ENA` reader - "] -pub type SLC_TX_START_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_START_INT_ENA` writer - "] -pub type SLC_TX_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_UDF_INT_ENA` reader - "] -pub type SLC_RX_UDF_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_RX_UDF_INT_ENA` writer - "] -pub type SLC_RX_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_OVF_INT_ENA` reader - "] -pub type SLC_TX_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_OVF_INT_ENA` writer - "] -pub type SLC_TX_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_ENA` reader - "] -pub type SLC_TOKEN0_1TO0_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_ENA` writer - "] -pub type SLC_TOKEN0_1TO0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_ENA` reader - "] -pub type SLC_TOKEN1_1TO0_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_ENA` writer - "] -pub type SLC_TOKEN1_1TO0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DONE_INT_ENA` reader - "] -pub type SLC_TX_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_DONE_INT_ENA` writer - "] -pub type SLC_TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_EOF_INT_ENA` reader - "] -pub type SLC_TX_EOF_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_EOF_INT_ENA` writer - "] -pub type SLC_TX_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DONE_INT_ENA` reader - "] -pub type SLC_RX_DONE_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_RX_DONE_INT_ENA` writer - "] -pub type SLC_RX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_EOF_INT_ENA` reader - "] -pub type SLC_RX_EOF_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_RX_EOF_INT_ENA` writer - "] -pub type SLC_RX_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOHOST_INT_ENA` reader - "] -pub type SLC_TOHOST_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TOHOST_INT_ENA` writer - "] -pub type SLC_TOHOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_ENA` reader - "] -pub type SLC_TX_DSCR_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_ENA` writer - "] -pub type SLC_TX_DSCR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_ENA` reader - "] -pub type SLC_RX_DSCR_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_ENA` writer - "] -pub type SLC_RX_DSCR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_ENA` reader - "] -pub type SLC_TX_DSCR_EMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_ENA` writer - "] -pub type SLC_TX_DSCR_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_frhost_bit0_int_ena(&self) -> SLC_FRHOST_BIT0_INT_ENA_R { - SLC_FRHOST_BIT0_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_frhost_bit1_int_ena(&self) -> SLC_FRHOST_BIT1_INT_ENA_R { - SLC_FRHOST_BIT1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn slc_frhost_bit2_int_ena(&self) -> SLC_FRHOST_BIT2_INT_ENA_R { - SLC_FRHOST_BIT2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn slc_frhost_bit3_int_ena(&self) -> SLC_FRHOST_BIT3_INT_ENA_R { - SLC_FRHOST_BIT3_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn slc_frhost_bit4_int_ena(&self) -> SLC_FRHOST_BIT4_INT_ENA_R { - SLC_FRHOST_BIT4_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn slc_frhost_bit5_int_ena(&self) -> SLC_FRHOST_BIT5_INT_ENA_R { - SLC_FRHOST_BIT5_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn slc_frhost_bit6_int_ena(&self) -> SLC_FRHOST_BIT6_INT_ENA_R { - SLC_FRHOST_BIT6_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn slc_frhost_bit7_int_ena(&self) -> SLC_FRHOST_BIT7_INT_ENA_R { - SLC_FRHOST_BIT7_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_rx_start_int_ena(&self) -> SLC_RX_START_INT_ENA_R { - SLC_RX_START_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_tx_start_int_ena(&self) -> SLC_TX_START_INT_ENA_R { - SLC_TX_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10"] - #[inline(always)] - pub fn slc_rx_udf_int_ena(&self) -> SLC_RX_UDF_INT_ENA_R { - SLC_RX_UDF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11"] - #[inline(always)] - pub fn slc_tx_ovf_int_ena(&self) -> SLC_TX_OVF_INT_ENA_R { - SLC_TX_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token0_1to0_int_ena(&self) -> SLC_TOKEN0_1TO0_INT_ENA_R { - SLC_TOKEN0_1TO0_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token1_1to0_int_ena(&self) -> SLC_TOKEN1_1TO0_INT_ENA_R { - SLC_TOKEN1_1TO0_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_tx_done_int_ena(&self) -> SLC_TX_DONE_INT_ENA_R { - SLC_TX_DONE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15"] - #[inline(always)] - pub fn slc_tx_eof_int_ena(&self) -> SLC_TX_EOF_INT_ENA_R { - SLC_TX_EOF_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_rx_done_int_ena(&self) -> SLC_RX_DONE_INT_ENA_R { - SLC_RX_DONE_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17"] - #[inline(always)] - pub fn slc_rx_eof_int_ena(&self) -> SLC_RX_EOF_INT_ENA_R { - SLC_RX_EOF_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18"] - #[inline(always)] - pub fn slc_tohost_int_ena(&self) -> SLC_TOHOST_INT_ENA_R { - SLC_TOHOST_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn slc_tx_dscr_err_int_ena(&self) -> SLC_TX_DSCR_ERR_INT_ENA_R { - SLC_TX_DSCR_ERR_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn slc_rx_dscr_err_int_ena(&self) -> SLC_RX_DSCR_ERR_INT_ENA_R { - SLC_RX_DSCR_ERR_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn slc_tx_dscr_empty_int_ena(&self) -> SLC_TX_DSCR_EMPTY_INT_ENA_R { - SLC_TX_DSCR_EMPTY_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_INT_ENA") - .field( - "slc_tx_dscr_empty_int_ena", - &format_args!("{}", self.slc_tx_dscr_empty_int_ena().bit()), - ) - .field( - "slc_rx_dscr_err_int_ena", - &format_args!("{}", self.slc_rx_dscr_err_int_ena().bit()), - ) - .field( - "slc_tx_dscr_err_int_ena", - &format_args!("{}", self.slc_tx_dscr_err_int_ena().bit()), - ) - .field( - "slc_tohost_int_ena", - &format_args!("{}", self.slc_tohost_int_ena().bit()), - ) - .field( - "slc_rx_eof_int_ena", - &format_args!("{}", self.slc_rx_eof_int_ena().bit()), - ) - .field( - "slc_rx_done_int_ena", - &format_args!("{}", self.slc_rx_done_int_ena().bit()), - ) - .field( - "slc_tx_eof_int_ena", - &format_args!("{}", self.slc_tx_eof_int_ena().bit()), - ) - .field( - "slc_tx_done_int_ena", - &format_args!("{}", self.slc_tx_done_int_ena().bit()), - ) - .field( - "slc_token1_1to0_int_ena", - &format_args!("{}", self.slc_token1_1to0_int_ena().bit()), - ) - .field( - "slc_token0_1to0_int_ena", - &format_args!("{}", self.slc_token0_1to0_int_ena().bit()), - ) - .field( - "slc_tx_ovf_int_ena", - &format_args!("{}", self.slc_tx_ovf_int_ena().bit()), - ) - .field( - "slc_rx_udf_int_ena", - &format_args!("{}", self.slc_rx_udf_int_ena().bit()), - ) - .field( - "slc_tx_start_int_ena", - &format_args!("{}", self.slc_tx_start_int_ena().bit()), - ) - .field( - "slc_rx_start_int_ena", - &format_args!("{}", self.slc_rx_start_int_ena().bit()), - ) - .field( - "slc_frhost_bit7_int_ena", - &format_args!("{}", self.slc_frhost_bit7_int_ena().bit()), - ) - .field( - "slc_frhost_bit6_int_ena", - &format_args!("{}", self.slc_frhost_bit6_int_ena().bit()), - ) - .field( - "slc_frhost_bit5_int_ena", - &format_args!("{}", self.slc_frhost_bit5_int_ena().bit()), - ) - .field( - "slc_frhost_bit4_int_ena", - &format_args!("{}", self.slc_frhost_bit4_int_ena().bit()), - ) - .field( - "slc_frhost_bit3_int_ena", - &format_args!("{}", self.slc_frhost_bit3_int_ena().bit()), - ) - .field( - "slc_frhost_bit2_int_ena", - &format_args!("{}", self.slc_frhost_bit2_int_ena().bit()), - ) - .field( - "slc_frhost_bit1_int_ena", - &format_args!("{}", self.slc_frhost_bit1_int_ena().bit()), - ) - .field( - "slc_frhost_bit0_int_ena", - &format_args!("{}", self.slc_frhost_bit0_int_ena().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit0_int_ena(&mut self) -> SLC_FRHOST_BIT0_INT_ENA_W { - SLC_FRHOST_BIT0_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit1_int_ena(&mut self) -> SLC_FRHOST_BIT1_INT_ENA_W { - SLC_FRHOST_BIT1_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit2_int_ena(&mut self) -> SLC_FRHOST_BIT2_INT_ENA_W { - SLC_FRHOST_BIT2_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit3_int_ena(&mut self) -> SLC_FRHOST_BIT3_INT_ENA_W { - SLC_FRHOST_BIT3_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit4_int_ena(&mut self) -> SLC_FRHOST_BIT4_INT_ENA_W { - SLC_FRHOST_BIT4_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit5_int_ena(&mut self) -> SLC_FRHOST_BIT5_INT_ENA_W { - SLC_FRHOST_BIT5_INT_ENA_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit6_int_ena(&mut self) -> SLC_FRHOST_BIT6_INT_ENA_W { - SLC_FRHOST_BIT6_INT_ENA_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit7_int_ena(&mut self) -> SLC_FRHOST_BIT7_INT_ENA_W { - SLC_FRHOST_BIT7_INT_ENA_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_rx_start_int_ena(&mut self) -> SLC_RX_START_INT_ENA_W { - SLC_RX_START_INT_ENA_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_tx_start_int_ena(&mut self) -> SLC_TX_START_INT_ENA_W { - SLC_TX_START_INT_ENA_W::new(self, 9) - } - #[doc = "Bit 10"] - #[inline(always)] - #[must_use] - pub fn slc_rx_udf_int_ena(&mut self) -> SLC_RX_UDF_INT_ENA_W { - SLC_RX_UDF_INT_ENA_W::new(self, 10) - } - #[doc = "Bit 11"] - #[inline(always)] - #[must_use] - pub fn slc_tx_ovf_int_ena(&mut self) -> SLC_TX_OVF_INT_ENA_W { - SLC_TX_OVF_INT_ENA_W::new(self, 11) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token0_1to0_int_ena(&mut self) -> SLC_TOKEN0_1TO0_INT_ENA_W { - SLC_TOKEN0_1TO0_INT_ENA_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token1_1to0_int_ena(&mut self) -> SLC_TOKEN1_1TO0_INT_ENA_W { - SLC_TOKEN1_1TO0_INT_ENA_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_tx_done_int_ena(&mut self) -> SLC_TX_DONE_INT_ENA_W { - SLC_TX_DONE_INT_ENA_W::new(self, 14) - } - #[doc = "Bit 15"] - #[inline(always)] - #[must_use] - pub fn slc_tx_eof_int_ena(&mut self) -> SLC_TX_EOF_INT_ENA_W { - SLC_TX_EOF_INT_ENA_W::new(self, 15) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_rx_done_int_ena(&mut self) -> SLC_RX_DONE_INT_ENA_W { - SLC_RX_DONE_INT_ENA_W::new(self, 16) - } - #[doc = "Bit 17"] - #[inline(always)] - #[must_use] - pub fn slc_rx_eof_int_ena(&mut self) -> SLC_RX_EOF_INT_ENA_W { - SLC_RX_EOF_INT_ENA_W::new(self, 17) - } - #[doc = "Bit 18"] - #[inline(always)] - #[must_use] - pub fn slc_tohost_int_ena(&mut self) -> SLC_TOHOST_INT_ENA_W { - SLC_TOHOST_INT_ENA_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_err_int_ena(&mut self) -> SLC_TX_DSCR_ERR_INT_ENA_W { - SLC_TX_DSCR_ERR_INT_ENA_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn slc_rx_dscr_err_int_ena(&mut self) -> SLC_RX_DSCR_ERR_INT_ENA_W { - SLC_RX_DSCR_ERR_INT_ENA_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_empty_int_ena(&mut self) -> SLC_TX_DSCR_EMPTY_INT_ENA_W { - SLC_TX_DSCR_EMPTY_INT_ENA_W::new(self, 21) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_INT_ENA_SPEC; -impl crate::RegisterSpec for SLC_INT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_int_ena::R`](R) reader structure"] -impl crate::Readable for SLC_INT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_int_ena::W`](W) writer structure"] -impl crate::Writable for SLC_INT_ENA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_INT_ENA to value 0"] -impl crate::Resettable for SLC_INT_ENA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_int_raw.rs b/esp8266/src/slc/slc_int_raw.rs deleted file mode 100644 index a97a39d673..0000000000 --- a/esp8266/src/slc/slc_int_raw.rs +++ /dev/null @@ -1,465 +0,0 @@ -#[doc = "Register `SLC_INT_RAW` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_INT_RAW` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_FRHOST_BIT0_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT0_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT0_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT1_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT1_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT1_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT2_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT2_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT2_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT3_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT3_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT3_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT4_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT4_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT4_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT5_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT5_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT5_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT6_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT6_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT6_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT6_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT7_INT_RAW` reader - "] -pub type SLC_FRHOST_BIT7_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT7_INT_RAW` writer - "] -pub type SLC_FRHOST_BIT7_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_START_INT_RAW` reader - "] -pub type SLC_RX_START_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_RX_START_INT_RAW` writer - "] -pub type SLC_RX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_START_INT_RAW` reader - "] -pub type SLC_TX_START_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_START_INT_RAW` writer - "] -pub type SLC_TX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_UDF_INT_RAW` reader - "] -pub type SLC_RX_UDF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_RX_UDF_INT_RAW` writer - "] -pub type SLC_RX_UDF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_OVF_INT_RAW` reader - "] -pub type SLC_TX_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_OVF_INT_RAW` writer - "] -pub type SLC_TX_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_RAW` reader - "] -pub type SLC_TOKEN0_1TO0_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_RAW` writer - "] -pub type SLC_TOKEN0_1TO0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_RAW` reader - "] -pub type SLC_TOKEN1_1TO0_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_RAW` writer - "] -pub type SLC_TOKEN1_1TO0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DONE_INT_RAW` reader - "] -pub type SLC_TX_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_DONE_INT_RAW` writer - "] -pub type SLC_TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_EOF_INT_RAW` reader - "] -pub type SLC_TX_EOF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_EOF_INT_RAW` writer - "] -pub type SLC_TX_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DONE_INT_RAW` reader - "] -pub type SLC_RX_DONE_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_RX_DONE_INT_RAW` writer - "] -pub type SLC_RX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_EOF_INT_RAW` reader - "] -pub type SLC_RX_EOF_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_RX_EOF_INT_RAW` writer - "] -pub type SLC_RX_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOHOST_INT_RAW` reader - "] -pub type SLC_TOHOST_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TOHOST_INT_RAW` writer - "] -pub type SLC_TOHOST_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_RAW` reader - "] -pub type SLC_TX_DSCR_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_RAW` writer - "] -pub type SLC_TX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_RAW` reader - "] -pub type SLC_RX_DSCR_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_RAW` writer - "] -pub type SLC_RX_DSCR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_RAW` reader - "] -pub type SLC_TX_DSCR_EMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_RAW` writer - "] -pub type SLC_TX_DSCR_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_frhost_bit0_int_raw(&self) -> SLC_FRHOST_BIT0_INT_RAW_R { - SLC_FRHOST_BIT0_INT_RAW_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_frhost_bit1_int_raw(&self) -> SLC_FRHOST_BIT1_INT_RAW_R { - SLC_FRHOST_BIT1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn slc_frhost_bit2_int_raw(&self) -> SLC_FRHOST_BIT2_INT_RAW_R { - SLC_FRHOST_BIT2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn slc_frhost_bit3_int_raw(&self) -> SLC_FRHOST_BIT3_INT_RAW_R { - SLC_FRHOST_BIT3_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn slc_frhost_bit4_int_raw(&self) -> SLC_FRHOST_BIT4_INT_RAW_R { - SLC_FRHOST_BIT4_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn slc_frhost_bit5_int_raw(&self) -> SLC_FRHOST_BIT5_INT_RAW_R { - SLC_FRHOST_BIT5_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn slc_frhost_bit6_int_raw(&self) -> SLC_FRHOST_BIT6_INT_RAW_R { - SLC_FRHOST_BIT6_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn slc_frhost_bit7_int_raw(&self) -> SLC_FRHOST_BIT7_INT_RAW_R { - SLC_FRHOST_BIT7_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_rx_start_int_raw(&self) -> SLC_RX_START_INT_RAW_R { - SLC_RX_START_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_tx_start_int_raw(&self) -> SLC_TX_START_INT_RAW_R { - SLC_TX_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10"] - #[inline(always)] - pub fn slc_rx_udf_int_raw(&self) -> SLC_RX_UDF_INT_RAW_R { - SLC_RX_UDF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11"] - #[inline(always)] - pub fn slc_tx_ovf_int_raw(&self) -> SLC_TX_OVF_INT_RAW_R { - SLC_TX_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token0_1to0_int_raw(&self) -> SLC_TOKEN0_1TO0_INT_RAW_R { - SLC_TOKEN0_1TO0_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token1_1to0_int_raw(&self) -> SLC_TOKEN1_1TO0_INT_RAW_R { - SLC_TOKEN1_1TO0_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_tx_done_int_raw(&self) -> SLC_TX_DONE_INT_RAW_R { - SLC_TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15"] - #[inline(always)] - pub fn slc_tx_eof_int_raw(&self) -> SLC_TX_EOF_INT_RAW_R { - SLC_TX_EOF_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_rx_done_int_raw(&self) -> SLC_RX_DONE_INT_RAW_R { - SLC_RX_DONE_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17"] - #[inline(always)] - pub fn slc_rx_eof_int_raw(&self) -> SLC_RX_EOF_INT_RAW_R { - SLC_RX_EOF_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18"] - #[inline(always)] - pub fn slc_tohost_int_raw(&self) -> SLC_TOHOST_INT_RAW_R { - SLC_TOHOST_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn slc_tx_dscr_err_int_raw(&self) -> SLC_TX_DSCR_ERR_INT_RAW_R { - SLC_TX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn slc_rx_dscr_err_int_raw(&self) -> SLC_RX_DSCR_ERR_INT_RAW_R { - SLC_RX_DSCR_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn slc_tx_dscr_empty_int_raw(&self) -> SLC_TX_DSCR_EMPTY_INT_RAW_R { - SLC_TX_DSCR_EMPTY_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_INT_RAW") - .field( - "slc_tx_dscr_empty_int_raw", - &format_args!("{}", self.slc_tx_dscr_empty_int_raw().bit()), - ) - .field( - "slc_rx_dscr_err_int_raw", - &format_args!("{}", self.slc_rx_dscr_err_int_raw().bit()), - ) - .field( - "slc_tx_dscr_err_int_raw", - &format_args!("{}", self.slc_tx_dscr_err_int_raw().bit()), - ) - .field( - "slc_tohost_int_raw", - &format_args!("{}", self.slc_tohost_int_raw().bit()), - ) - .field( - "slc_rx_eof_int_raw", - &format_args!("{}", self.slc_rx_eof_int_raw().bit()), - ) - .field( - "slc_rx_done_int_raw", - &format_args!("{}", self.slc_rx_done_int_raw().bit()), - ) - .field( - "slc_tx_eof_int_raw", - &format_args!("{}", self.slc_tx_eof_int_raw().bit()), - ) - .field( - "slc_tx_done_int_raw", - &format_args!("{}", self.slc_tx_done_int_raw().bit()), - ) - .field( - "slc_token1_1to0_int_raw", - &format_args!("{}", self.slc_token1_1to0_int_raw().bit()), - ) - .field( - "slc_token0_1to0_int_raw", - &format_args!("{}", self.slc_token0_1to0_int_raw().bit()), - ) - .field( - "slc_tx_ovf_int_raw", - &format_args!("{}", self.slc_tx_ovf_int_raw().bit()), - ) - .field( - "slc_rx_udf_int_raw", - &format_args!("{}", self.slc_rx_udf_int_raw().bit()), - ) - .field( - "slc_tx_start_int_raw", - &format_args!("{}", self.slc_tx_start_int_raw().bit()), - ) - .field( - "slc_rx_start_int_raw", - &format_args!("{}", self.slc_rx_start_int_raw().bit()), - ) - .field( - "slc_frhost_bit7_int_raw", - &format_args!("{}", self.slc_frhost_bit7_int_raw().bit()), - ) - .field( - "slc_frhost_bit6_int_raw", - &format_args!("{}", self.slc_frhost_bit6_int_raw().bit()), - ) - .field( - "slc_frhost_bit5_int_raw", - &format_args!("{}", self.slc_frhost_bit5_int_raw().bit()), - ) - .field( - "slc_frhost_bit4_int_raw", - &format_args!("{}", self.slc_frhost_bit4_int_raw().bit()), - ) - .field( - "slc_frhost_bit3_int_raw", - &format_args!("{}", self.slc_frhost_bit3_int_raw().bit()), - ) - .field( - "slc_frhost_bit2_int_raw", - &format_args!("{}", self.slc_frhost_bit2_int_raw().bit()), - ) - .field( - "slc_frhost_bit1_int_raw", - &format_args!("{}", self.slc_frhost_bit1_int_raw().bit()), - ) - .field( - "slc_frhost_bit0_int_raw", - &format_args!("{}", self.slc_frhost_bit0_int_raw().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit0_int_raw(&mut self) -> SLC_FRHOST_BIT0_INT_RAW_W { - SLC_FRHOST_BIT0_INT_RAW_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit1_int_raw(&mut self) -> SLC_FRHOST_BIT1_INT_RAW_W { - SLC_FRHOST_BIT1_INT_RAW_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit2_int_raw(&mut self) -> SLC_FRHOST_BIT2_INT_RAW_W { - SLC_FRHOST_BIT2_INT_RAW_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit3_int_raw(&mut self) -> SLC_FRHOST_BIT3_INT_RAW_W { - SLC_FRHOST_BIT3_INT_RAW_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit4_int_raw(&mut self) -> SLC_FRHOST_BIT4_INT_RAW_W { - SLC_FRHOST_BIT4_INT_RAW_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit5_int_raw(&mut self) -> SLC_FRHOST_BIT5_INT_RAW_W { - SLC_FRHOST_BIT5_INT_RAW_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit6_int_raw(&mut self) -> SLC_FRHOST_BIT6_INT_RAW_W { - SLC_FRHOST_BIT6_INT_RAW_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit7_int_raw(&mut self) -> SLC_FRHOST_BIT7_INT_RAW_W { - SLC_FRHOST_BIT7_INT_RAW_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_rx_start_int_raw(&mut self) -> SLC_RX_START_INT_RAW_W { - SLC_RX_START_INT_RAW_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_tx_start_int_raw(&mut self) -> SLC_TX_START_INT_RAW_W { - SLC_TX_START_INT_RAW_W::new(self, 9) - } - #[doc = "Bit 10"] - #[inline(always)] - #[must_use] - pub fn slc_rx_udf_int_raw(&mut self) -> SLC_RX_UDF_INT_RAW_W { - SLC_RX_UDF_INT_RAW_W::new(self, 10) - } - #[doc = "Bit 11"] - #[inline(always)] - #[must_use] - pub fn slc_tx_ovf_int_raw(&mut self) -> SLC_TX_OVF_INT_RAW_W { - SLC_TX_OVF_INT_RAW_W::new(self, 11) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token0_1to0_int_raw(&mut self) -> SLC_TOKEN0_1TO0_INT_RAW_W { - SLC_TOKEN0_1TO0_INT_RAW_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token1_1to0_int_raw(&mut self) -> SLC_TOKEN1_1TO0_INT_RAW_W { - SLC_TOKEN1_1TO0_INT_RAW_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_tx_done_int_raw(&mut self) -> SLC_TX_DONE_INT_RAW_W { - SLC_TX_DONE_INT_RAW_W::new(self, 14) - } - #[doc = "Bit 15"] - #[inline(always)] - #[must_use] - pub fn slc_tx_eof_int_raw(&mut self) -> SLC_TX_EOF_INT_RAW_W { - SLC_TX_EOF_INT_RAW_W::new(self, 15) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_rx_done_int_raw(&mut self) -> SLC_RX_DONE_INT_RAW_W { - SLC_RX_DONE_INT_RAW_W::new(self, 16) - } - #[doc = "Bit 17"] - #[inline(always)] - #[must_use] - pub fn slc_rx_eof_int_raw(&mut self) -> SLC_RX_EOF_INT_RAW_W { - SLC_RX_EOF_INT_RAW_W::new(self, 17) - } - #[doc = "Bit 18"] - #[inline(always)] - #[must_use] - pub fn slc_tohost_int_raw(&mut self) -> SLC_TOHOST_INT_RAW_W { - SLC_TOHOST_INT_RAW_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_err_int_raw(&mut self) -> SLC_TX_DSCR_ERR_INT_RAW_W { - SLC_TX_DSCR_ERR_INT_RAW_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn slc_rx_dscr_err_int_raw(&mut self) -> SLC_RX_DSCR_ERR_INT_RAW_W { - SLC_RX_DSCR_ERR_INT_RAW_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_empty_int_raw(&mut self) -> SLC_TX_DSCR_EMPTY_INT_RAW_W { - SLC_TX_DSCR_EMPTY_INT_RAW_W::new(self, 21) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_INT_RAW\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_INT_RAW_SPEC; -impl crate::RegisterSpec for SLC_INT_RAW_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_int_raw::R`](R) reader structure"] -impl crate::Readable for SLC_INT_RAW_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_int_raw::W`](W) writer structure"] -impl crate::Writable for SLC_INT_RAW_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_INT_RAW to value 0"] -impl crate::Resettable for SLC_INT_RAW_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_int_status.rs b/esp8266/src/slc/slc_int_status.rs deleted file mode 100644 index 02218d45ac..0000000000 --- a/esp8266/src/slc/slc_int_status.rs +++ /dev/null @@ -1,465 +0,0 @@ -#[doc = "Register `SLC_INT_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_INT_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_FRHOST_BIT0_INT_ST` reader - "] -pub type SLC_FRHOST_BIT0_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT0_INT_ST` writer - "] -pub type SLC_FRHOST_BIT0_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT1_INT_ST` reader - "] -pub type SLC_FRHOST_BIT1_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT1_INT_ST` writer - "] -pub type SLC_FRHOST_BIT1_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT2_INT_ST` reader - "] -pub type SLC_FRHOST_BIT2_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT2_INT_ST` writer - "] -pub type SLC_FRHOST_BIT2_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT3_INT_ST` reader - "] -pub type SLC_FRHOST_BIT3_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT3_INT_ST` writer - "] -pub type SLC_FRHOST_BIT3_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT4_INT_ST` reader - "] -pub type SLC_FRHOST_BIT4_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT4_INT_ST` writer - "] -pub type SLC_FRHOST_BIT4_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT5_INT_ST` reader - "] -pub type SLC_FRHOST_BIT5_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT5_INT_ST` writer - "] -pub type SLC_FRHOST_BIT5_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT6_INT_ST` reader - "] -pub type SLC_FRHOST_BIT6_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT6_INT_ST` writer - "] -pub type SLC_FRHOST_BIT6_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_FRHOST_BIT7_INT_ST` reader - "] -pub type SLC_FRHOST_BIT7_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_FRHOST_BIT7_INT_ST` writer - "] -pub type SLC_FRHOST_BIT7_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_START_INT_ST` reader - "] -pub type SLC_RX_START_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_RX_START_INT_ST` writer - "] -pub type SLC_RX_START_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_START_INT_ST` reader - "] -pub type SLC_TX_START_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_START_INT_ST` writer - "] -pub type SLC_TX_START_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_UDF_INT_ST` reader - "] -pub type SLC_RX_UDF_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_RX_UDF_INT_ST` writer - "] -pub type SLC_RX_UDF_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_OVF_INT_ST` reader - "] -pub type SLC_TX_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_OVF_INT_ST` writer - "] -pub type SLC_TX_OVF_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_ST` reader - "] -pub type SLC_TOKEN0_1TO0_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_1TO0_INT_ST` writer - "] -pub type SLC_TOKEN0_1TO0_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_ST` reader - "] -pub type SLC_TOKEN1_1TO0_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_1TO0_INT_ST` writer - "] -pub type SLC_TOKEN1_1TO0_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DONE_INT_ST` reader - "] -pub type SLC_TX_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_DONE_INT_ST` writer - "] -pub type SLC_TX_DONE_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_EOF_INT_ST` reader - "] -pub type SLC_TX_EOF_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_EOF_INT_ST` writer - "] -pub type SLC_TX_EOF_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DONE_INT_ST` reader - "] -pub type SLC_RX_DONE_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_RX_DONE_INT_ST` writer - "] -pub type SLC_RX_DONE_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_EOF_INT_ST` reader - "] -pub type SLC_RX_EOF_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_RX_EOF_INT_ST` writer - "] -pub type SLC_RX_EOF_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOHOST_INT_ST` reader - "] -pub type SLC_TOHOST_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TOHOST_INT_ST` writer - "] -pub type SLC_TOHOST_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_ST` reader - "] -pub type SLC_TX_DSCR_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_ERR_INT_ST` writer - "] -pub type SLC_TX_DSCR_ERR_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_ST` reader - "] -pub type SLC_RX_DSCR_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_RX_DSCR_ERR_INT_ST` writer - "] -pub type SLC_RX_DSCR_ERR_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_ST` reader - "] -pub type SLC_TX_DSCR_EMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `SLC_TX_DSCR_EMPTY_INT_ST` writer - "] -pub type SLC_TX_DSCR_EMPTY_INT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_frhost_bit0_int_st(&self) -> SLC_FRHOST_BIT0_INT_ST_R { - SLC_FRHOST_BIT0_INT_ST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_frhost_bit1_int_st(&self) -> SLC_FRHOST_BIT1_INT_ST_R { - SLC_FRHOST_BIT1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn slc_frhost_bit2_int_st(&self) -> SLC_FRHOST_BIT2_INT_ST_R { - SLC_FRHOST_BIT2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn slc_frhost_bit3_int_st(&self) -> SLC_FRHOST_BIT3_INT_ST_R { - SLC_FRHOST_BIT3_INT_ST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn slc_frhost_bit4_int_st(&self) -> SLC_FRHOST_BIT4_INT_ST_R { - SLC_FRHOST_BIT4_INT_ST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn slc_frhost_bit5_int_st(&self) -> SLC_FRHOST_BIT5_INT_ST_R { - SLC_FRHOST_BIT5_INT_ST_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6"] - #[inline(always)] - pub fn slc_frhost_bit6_int_st(&self) -> SLC_FRHOST_BIT6_INT_ST_R { - SLC_FRHOST_BIT6_INT_ST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7"] - #[inline(always)] - pub fn slc_frhost_bit7_int_st(&self) -> SLC_FRHOST_BIT7_INT_ST_R { - SLC_FRHOST_BIT7_INT_ST_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_rx_start_int_st(&self) -> SLC_RX_START_INT_ST_R { - SLC_RX_START_INT_ST_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_tx_start_int_st(&self) -> SLC_TX_START_INT_ST_R { - SLC_TX_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10"] - #[inline(always)] - pub fn slc_rx_udf_int_st(&self) -> SLC_RX_UDF_INT_ST_R { - SLC_RX_UDF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11"] - #[inline(always)] - pub fn slc_tx_ovf_int_st(&self) -> SLC_TX_OVF_INT_ST_R { - SLC_TX_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token0_1to0_int_st(&self) -> SLC_TOKEN0_1TO0_INT_ST_R { - SLC_TOKEN0_1TO0_INT_ST_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token1_1to0_int_st(&self) -> SLC_TOKEN1_1TO0_INT_ST_R { - SLC_TOKEN1_1TO0_INT_ST_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_tx_done_int_st(&self) -> SLC_TX_DONE_INT_ST_R { - SLC_TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15"] - #[inline(always)] - pub fn slc_tx_eof_int_st(&self) -> SLC_TX_EOF_INT_ST_R { - SLC_TX_EOF_INT_ST_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_rx_done_int_st(&self) -> SLC_RX_DONE_INT_ST_R { - SLC_RX_DONE_INT_ST_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17"] - #[inline(always)] - pub fn slc_rx_eof_int_st(&self) -> SLC_RX_EOF_INT_ST_R { - SLC_RX_EOF_INT_ST_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18"] - #[inline(always)] - pub fn slc_tohost_int_st(&self) -> SLC_TOHOST_INT_ST_R { - SLC_TOHOST_INT_ST_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn slc_tx_dscr_err_int_st(&self) -> SLC_TX_DSCR_ERR_INT_ST_R { - SLC_TX_DSCR_ERR_INT_ST_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn slc_rx_dscr_err_int_st(&self) -> SLC_RX_DSCR_ERR_INT_ST_R { - SLC_RX_DSCR_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn slc_tx_dscr_empty_int_st(&self) -> SLC_TX_DSCR_EMPTY_INT_ST_R { - SLC_TX_DSCR_EMPTY_INT_ST_R::new(((self.bits >> 21) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_INT_STATUS") - .field( - "slc_tx_dscr_empty_int_st", - &format_args!("{}", self.slc_tx_dscr_empty_int_st().bit()), - ) - .field( - "slc_rx_dscr_err_int_st", - &format_args!("{}", self.slc_rx_dscr_err_int_st().bit()), - ) - .field( - "slc_tx_dscr_err_int_st", - &format_args!("{}", self.slc_tx_dscr_err_int_st().bit()), - ) - .field( - "slc_tohost_int_st", - &format_args!("{}", self.slc_tohost_int_st().bit()), - ) - .field( - "slc_rx_eof_int_st", - &format_args!("{}", self.slc_rx_eof_int_st().bit()), - ) - .field( - "slc_rx_done_int_st", - &format_args!("{}", self.slc_rx_done_int_st().bit()), - ) - .field( - "slc_tx_eof_int_st", - &format_args!("{}", self.slc_tx_eof_int_st().bit()), - ) - .field( - "slc_tx_done_int_st", - &format_args!("{}", self.slc_tx_done_int_st().bit()), - ) - .field( - "slc_token1_1to0_int_st", - &format_args!("{}", self.slc_token1_1to0_int_st().bit()), - ) - .field( - "slc_token0_1to0_int_st", - &format_args!("{}", self.slc_token0_1to0_int_st().bit()), - ) - .field( - "slc_tx_ovf_int_st", - &format_args!("{}", self.slc_tx_ovf_int_st().bit()), - ) - .field( - "slc_rx_udf_int_st", - &format_args!("{}", self.slc_rx_udf_int_st().bit()), - ) - .field( - "slc_tx_start_int_st", - &format_args!("{}", self.slc_tx_start_int_st().bit()), - ) - .field( - "slc_rx_start_int_st", - &format_args!("{}", self.slc_rx_start_int_st().bit()), - ) - .field( - "slc_frhost_bit7_int_st", - &format_args!("{}", self.slc_frhost_bit7_int_st().bit()), - ) - .field( - "slc_frhost_bit6_int_st", - &format_args!("{}", self.slc_frhost_bit6_int_st().bit()), - ) - .field( - "slc_frhost_bit5_int_st", - &format_args!("{}", self.slc_frhost_bit5_int_st().bit()), - ) - .field( - "slc_frhost_bit4_int_st", - &format_args!("{}", self.slc_frhost_bit4_int_st().bit()), - ) - .field( - "slc_frhost_bit3_int_st", - &format_args!("{}", self.slc_frhost_bit3_int_st().bit()), - ) - .field( - "slc_frhost_bit2_int_st", - &format_args!("{}", self.slc_frhost_bit2_int_st().bit()), - ) - .field( - "slc_frhost_bit1_int_st", - &format_args!("{}", self.slc_frhost_bit1_int_st().bit()), - ) - .field( - "slc_frhost_bit0_int_st", - &format_args!("{}", self.slc_frhost_bit0_int_st().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit0_int_st(&mut self) -> SLC_FRHOST_BIT0_INT_ST_W { - SLC_FRHOST_BIT0_INT_ST_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit1_int_st(&mut self) -> SLC_FRHOST_BIT1_INT_ST_W { - SLC_FRHOST_BIT1_INT_ST_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit2_int_st(&mut self) -> SLC_FRHOST_BIT2_INT_ST_W { - SLC_FRHOST_BIT2_INT_ST_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit3_int_st(&mut self) -> SLC_FRHOST_BIT3_INT_ST_W { - SLC_FRHOST_BIT3_INT_ST_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit4_int_st(&mut self) -> SLC_FRHOST_BIT4_INT_ST_W { - SLC_FRHOST_BIT4_INT_ST_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit5_int_st(&mut self) -> SLC_FRHOST_BIT5_INT_ST_W { - SLC_FRHOST_BIT5_INT_ST_W::new(self, 5) - } - #[doc = "Bit 6"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit6_int_st(&mut self) -> SLC_FRHOST_BIT6_INT_ST_W { - SLC_FRHOST_BIT6_INT_ST_W::new(self, 6) - } - #[doc = "Bit 7"] - #[inline(always)] - #[must_use] - pub fn slc_frhost_bit7_int_st(&mut self) -> SLC_FRHOST_BIT7_INT_ST_W { - SLC_FRHOST_BIT7_INT_ST_W::new(self, 7) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_rx_start_int_st(&mut self) -> SLC_RX_START_INT_ST_W { - SLC_RX_START_INT_ST_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_tx_start_int_st(&mut self) -> SLC_TX_START_INT_ST_W { - SLC_TX_START_INT_ST_W::new(self, 9) - } - #[doc = "Bit 10"] - #[inline(always)] - #[must_use] - pub fn slc_rx_udf_int_st(&mut self) -> SLC_RX_UDF_INT_ST_W { - SLC_RX_UDF_INT_ST_W::new(self, 10) - } - #[doc = "Bit 11"] - #[inline(always)] - #[must_use] - pub fn slc_tx_ovf_int_st(&mut self) -> SLC_TX_OVF_INT_ST_W { - SLC_TX_OVF_INT_ST_W::new(self, 11) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token0_1to0_int_st(&mut self) -> SLC_TOKEN0_1TO0_INT_ST_W { - SLC_TOKEN0_1TO0_INT_ST_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token1_1to0_int_st(&mut self) -> SLC_TOKEN1_1TO0_INT_ST_W { - SLC_TOKEN1_1TO0_INT_ST_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_tx_done_int_st(&mut self) -> SLC_TX_DONE_INT_ST_W { - SLC_TX_DONE_INT_ST_W::new(self, 14) - } - #[doc = "Bit 15"] - #[inline(always)] - #[must_use] - pub fn slc_tx_eof_int_st(&mut self) -> SLC_TX_EOF_INT_ST_W { - SLC_TX_EOF_INT_ST_W::new(self, 15) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_rx_done_int_st(&mut self) -> SLC_RX_DONE_INT_ST_W { - SLC_RX_DONE_INT_ST_W::new(self, 16) - } - #[doc = "Bit 17"] - #[inline(always)] - #[must_use] - pub fn slc_rx_eof_int_st(&mut self) -> SLC_RX_EOF_INT_ST_W { - SLC_RX_EOF_INT_ST_W::new(self, 17) - } - #[doc = "Bit 18"] - #[inline(always)] - #[must_use] - pub fn slc_tohost_int_st(&mut self) -> SLC_TOHOST_INT_ST_W { - SLC_TOHOST_INT_ST_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_err_int_st(&mut self) -> SLC_TX_DSCR_ERR_INT_ST_W { - SLC_TX_DSCR_ERR_INT_ST_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn slc_rx_dscr_err_int_st(&mut self) -> SLC_RX_DSCR_ERR_INT_ST_W { - SLC_RX_DSCR_ERR_INT_ST_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn slc_tx_dscr_empty_int_st(&mut self) -> SLC_TX_DSCR_EMPTY_INT_ST_W { - SLC_TX_DSCR_EMPTY_INT_ST_W::new(self, 21) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_INT_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_int_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_int_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_INT_STATUS_SPEC; -impl crate::RegisterSpec for SLC_INT_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_int_status::R`](R) reader structure"] -impl crate::Readable for SLC_INT_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_int_status::W`](W) writer structure"] -impl crate::Writable for SLC_INT_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_INT_STATUS to value 0"] -impl crate::Resettable for SLC_INT_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_intvec_tohost.rs b/esp8266/src/slc/slc_intvec_tohost.rs deleted file mode 100644 index d3f8297775..0000000000 --- a/esp8266/src/slc/slc_intvec_tohost.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SLC_INTVEC_TOHOST` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_INTVEC_TOHOST` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TOHOST_INTVEC` reader - "] -pub type SLC_TOHOST_INTVEC_R = crate::FieldReader; -#[doc = "Field `SLC_TOHOST_INTVEC` writer - "] -pub type SLC_TOHOST_INTVEC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7"] - #[inline(always)] - pub fn slc_tohost_intvec(&self) -> SLC_TOHOST_INTVEC_R { - SLC_TOHOST_INTVEC_R::new((self.bits & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_INTVEC_TOHOST") - .field( - "slc_tohost_intvec", - &format_args!("{}", self.slc_tohost_intvec().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7"] - #[inline(always)] - #[must_use] - pub fn slc_tohost_intvec(&mut self) -> SLC_TOHOST_INTVEC_W { - SLC_TOHOST_INTVEC_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_INTVEC_TOHOST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_intvec_tohost::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_intvec_tohost::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_INTVEC_TOHOST_SPEC; -impl crate::RegisterSpec for SLC_INTVEC_TOHOST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_intvec_tohost::R`](R) reader structure"] -impl crate::Readable for SLC_INTVEC_TOHOST_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_intvec_tohost::W`](W) writer structure"] -impl crate::Writable for SLC_INTVEC_TOHOST_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_INTVEC_TOHOST to value 0"] -impl crate::Resettable for SLC_INTVEC_TOHOST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_dscr_conf.rs b/esp8266/src/slc/slc_rx_dscr_conf.rs deleted file mode 100644 index 483d3abcfe..0000000000 --- a/esp8266/src/slc/slc_rx_dscr_conf.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SLC_RX_DSCR_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_DSCR_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TOKEN_NO_REPLACE` reader - "] -pub type SLC_TOKEN_NO_REPLACE_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN_NO_REPLACE` writer - "] -pub type SLC_TOKEN_NO_REPLACE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_INFOR_NO_REPLACE` reader - "] -pub type SLC_INFOR_NO_REPLACE_R = crate::BitReader; -#[doc = "Field `SLC_INFOR_NO_REPLACE` writer - "] -pub type SLC_INFOR_NO_REPLACE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_token_no_replace(&self) -> SLC_TOKEN_NO_REPLACE_R { - SLC_TOKEN_NO_REPLACE_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9"] - #[inline(always)] - pub fn slc_infor_no_replace(&self) -> SLC_INFOR_NO_REPLACE_R { - SLC_INFOR_NO_REPLACE_R::new(((self.bits >> 9) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_DSCR_CONF") - .field( - "slc_infor_no_replace", - &format_args!("{}", self.slc_infor_no_replace().bit()), - ) - .field( - "slc_token_no_replace", - &format_args!("{}", self.slc_token_no_replace().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_token_no_replace(&mut self) -> SLC_TOKEN_NO_REPLACE_W { - SLC_TOKEN_NO_REPLACE_W::new(self, 8) - } - #[doc = "Bit 9"] - #[inline(always)] - #[must_use] - pub fn slc_infor_no_replace(&mut self) -> SLC_INFOR_NO_REPLACE_W { - SLC_INFOR_NO_REPLACE_W::new(self, 9) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_DSCR_CONF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_dscr_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_dscr_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_DSCR_CONF_SPEC; -impl crate::RegisterSpec for SLC_RX_DSCR_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_dscr_conf::R`](R) reader structure"] -impl crate::Readable for SLC_RX_DSCR_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_dscr_conf::W`](W) writer structure"] -impl crate::Writable for SLC_RX_DSCR_CONF_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_DSCR_CONF to value 0"] -impl crate::Resettable for SLC_RX_DSCR_CONF_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_eof_bfr_des_addr.rs b/esp8266/src/slc/slc_rx_eof_bfr_des_addr.rs deleted file mode 100644 index ff88c51fad..0000000000 --- a/esp8266/src/slc/slc_rx_eof_bfr_des_addr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_RX_EOF_BFR_DES_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_EOF_BFR_DES_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_EOF_BFR_DES_ADDR") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_EOF_BFR_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_eof_bfr_des_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_eof_bfr_des_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_EOF_BFR_DES_ADDR_SPEC; -impl crate::RegisterSpec for SLC_RX_EOF_BFR_DES_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_eof_bfr_des_addr::R`](R) reader structure"] -impl crate::Readable for SLC_RX_EOF_BFR_DES_ADDR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_eof_bfr_des_addr::W`](W) writer structure"] -impl crate::Writable for SLC_RX_EOF_BFR_DES_ADDR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_EOF_BFR_DES_ADDR to value 0"] -impl crate::Resettable for SLC_RX_EOF_BFR_DES_ADDR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_eof_des_addr.rs b/esp8266/src/slc/slc_rx_eof_des_addr.rs deleted file mode 100644 index 5aae236c33..0000000000 --- a/esp8266/src/slc/slc_rx_eof_des_addr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_RX_EOF_DES_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_EOF_DES_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_EOF_DES_ADDR") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_EOF_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_eof_des_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_eof_des_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_EOF_DES_ADDR_SPEC; -impl crate::RegisterSpec for SLC_RX_EOF_DES_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_eof_des_addr::R`](R) reader structure"] -impl crate::Readable for SLC_RX_EOF_DES_ADDR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_eof_des_addr::W`](W) writer structure"] -impl crate::Writable for SLC_RX_EOF_DES_ADDR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_EOF_DES_ADDR to value 0"] -impl crate::Resettable for SLC_RX_EOF_DES_ADDR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_fifo_push.rs b/esp8266/src/slc/slc_rx_fifo_push.rs deleted file mode 100644 index 650cc53188..0000000000 --- a/esp8266/src/slc/slc_rx_fifo_push.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SLC_RX_FIFO_PUSH` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_FIFO_PUSH` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_RXFIFO_WDATA` reader - "] -pub type SLC_RXFIFO_WDATA_R = crate::FieldReader; -#[doc = "Field `SLC_RXFIFO_WDATA` writer - "] -pub type SLC_RXFIFO_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `SLC_RXFIFO_PUSH` reader - "] -pub type SLC_RXFIFO_PUSH_R = crate::BitReader; -#[doc = "Field `SLC_RXFIFO_PUSH` writer - "] -pub type SLC_RXFIFO_PUSH_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:8"] - #[inline(always)] - pub fn slc_rxfifo_wdata(&self) -> SLC_RXFIFO_WDATA_R { - SLC_RXFIFO_WDATA_R::new((self.bits & 0x01ff) as u16) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_rxfifo_push(&self) -> SLC_RXFIFO_PUSH_R { - SLC_RXFIFO_PUSH_R::new(((self.bits >> 16) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_FIFO_PUSH") - .field( - "slc_rxfifo_push", - &format_args!("{}", self.slc_rxfifo_push().bit()), - ) - .field( - "slc_rxfifo_wdata", - &format_args!("{}", self.slc_rxfifo_wdata().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:8"] - #[inline(always)] - #[must_use] - pub fn slc_rxfifo_wdata(&mut self) -> SLC_RXFIFO_WDATA_W { - SLC_RXFIFO_WDATA_W::new(self, 0) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_rxfifo_push(&mut self) -> SLC_RXFIFO_PUSH_W { - SLC_RXFIFO_PUSH_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_FIFO_PUSH\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_fifo_push::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_fifo_push::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_FIFO_PUSH_SPEC; -impl crate::RegisterSpec for SLC_RX_FIFO_PUSH_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_fifo_push::R`](R) reader structure"] -impl crate::Readable for SLC_RX_FIFO_PUSH_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_fifo_push::W`](W) writer structure"] -impl crate::Writable for SLC_RX_FIFO_PUSH_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_FIFO_PUSH to value 0"] -impl crate::Resettable for SLC_RX_FIFO_PUSH_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_link.rs b/esp8266/src/slc/slc_rx_link.rs deleted file mode 100644 index 25b89b2d12..0000000000 --- a/esp8266/src/slc/slc_rx_link.rs +++ /dev/null @@ -1,142 +0,0 @@ -#[doc = "Register `SLC_RX_LINK` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_LINK` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_RXLINK_ADDR` reader - "] -pub type SLC_RXLINK_ADDR_R = crate::FieldReader; -#[doc = "Field `SLC_RXLINK_ADDR` writer - "] -pub type SLC_RXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -#[doc = "Field `SLC_RXLINK_STOP` reader - "] -pub type SLC_RXLINK_STOP_R = crate::BitReader; -#[doc = "Field `SLC_RXLINK_STOP` writer - "] -pub type SLC_RXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RXLINK_START` reader - "] -pub type SLC_RXLINK_START_R = crate::BitReader; -#[doc = "Field `SLC_RXLINK_START` writer - "] -pub type SLC_RXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RXLINK_RESTART` reader - "] -pub type SLC_RXLINK_RESTART_R = crate::BitReader; -#[doc = "Field `SLC_RXLINK_RESTART` writer - "] -pub type SLC_RXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RXLINK_PARK` reader - "] -pub type SLC_RXLINK_PARK_R = crate::BitReader; -#[doc = "Field `SLC_RXLINK_PARK` writer - "] -pub type SLC_RXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:19"] - #[inline(always)] - pub fn slc_rxlink_addr(&self) -> SLC_RXLINK_ADDR_R { - SLC_RXLINK_ADDR_R::new(self.bits & 0x000f_ffff) - } - #[doc = "Bit 28"] - #[inline(always)] - pub fn slc_rxlink_stop(&self) -> SLC_RXLINK_STOP_R { - SLC_RXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29"] - #[inline(always)] - pub fn slc_rxlink_start(&self) -> SLC_RXLINK_START_R { - SLC_RXLINK_START_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30"] - #[inline(always)] - pub fn slc_rxlink_restart(&self) -> SLC_RXLINK_RESTART_R { - SLC_RXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn slc_rxlink_park(&self) -> SLC_RXLINK_PARK_R { - SLC_RXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_LINK") - .field( - "slc_rxlink_park", - &format_args!("{}", self.slc_rxlink_park().bit()), - ) - .field( - "slc_rxlink_restart", - &format_args!("{}", self.slc_rxlink_restart().bit()), - ) - .field( - "slc_rxlink_start", - &format_args!("{}", self.slc_rxlink_start().bit()), - ) - .field( - "slc_rxlink_stop", - &format_args!("{}", self.slc_rxlink_stop().bit()), - ) - .field( - "slc_rxlink_addr", - &format_args!("{}", self.slc_rxlink_addr().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:19"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_addr(&mut self) -> SLC_RXLINK_ADDR_W { - SLC_RXLINK_ADDR_W::new(self, 0) - } - #[doc = "Bit 28"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_stop(&mut self) -> SLC_RXLINK_STOP_W { - SLC_RXLINK_STOP_W::new(self, 28) - } - #[doc = "Bit 29"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_start(&mut self) -> SLC_RXLINK_START_W { - SLC_RXLINK_START_W::new(self, 29) - } - #[doc = "Bit 30"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_restart(&mut self) -> SLC_RXLINK_RESTART_W { - SLC_RXLINK_RESTART_W::new(self, 30) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn slc_rxlink_park(&mut self) -> SLC_RXLINK_PARK_W { - SLC_RXLINK_PARK_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_LINK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_link::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_link::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_LINK_SPEC; -impl crate::RegisterSpec for SLC_RX_LINK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_link::R`](R) reader structure"] -impl crate::Readable for SLC_RX_LINK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_link::W`](W) writer structure"] -impl crate::Writable for SLC_RX_LINK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_LINK to value 0"] -impl crate::Resettable for SLC_RX_LINK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rx_status.rs b/esp8266/src/slc/slc_rx_status.rs deleted file mode 100644 index d6e532dcbe..0000000000 --- a/esp8266/src/slc/slc_rx_status.rs +++ /dev/null @@ -1,82 +0,0 @@ -#[doc = "Register `SLC_RX_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RX_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_RX_FULL` reader - "] -pub type SLC_RX_FULL_R = crate::BitReader; -#[doc = "Field `SLC_RX_FULL` writer - "] -pub type SLC_RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_RX_EMPTY` reader - "] -pub type SLC_RX_EMPTY_R = crate::BitReader; -#[doc = "Field `SLC_RX_EMPTY` writer - "] -pub type SLC_RX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_rx_full(&self) -> SLC_RX_FULL_R { - SLC_RX_FULL_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_rx_empty(&self) -> SLC_RX_EMPTY_R { - SLC_RX_EMPTY_R::new(((self.bits >> 1) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RX_STATUS") - .field( - "slc_rx_empty", - &format_args!("{}", self.slc_rx_empty().bit()), - ) - .field("slc_rx_full", &format_args!("{}", self.slc_rx_full().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_rx_full(&mut self) -> SLC_RX_FULL_W { - SLC_RX_FULL_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_rx_empty(&mut self) -> SLC_RX_EMPTY_W { - SLC_RX_EMPTY_W::new(self, 1) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RX_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rx_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rx_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RX_STATUS_SPEC; -impl crate::RegisterSpec for SLC_RX_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rx_status::R`](R) reader structure"] -impl crate::Readable for SLC_RX_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rx_status::W`](W) writer structure"] -impl crate::Writable for SLC_RX_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RX_STATUS to value 0"] -impl crate::Resettable for SLC_RX_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rxlink_dscr.rs b/esp8266/src/slc/slc_rxlink_dscr.rs deleted file mode 100644 index dc72d7ee69..0000000000 --- a/esp8266/src/slc/slc_rxlink_dscr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_RXLINK_DSCR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RXLINK_DSCR` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RXLINK_DSCR") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RXLINK_DSCR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RXLINK_DSCR_SPEC; -impl crate::RegisterSpec for SLC_RXLINK_DSCR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rxlink_dscr::R`](R) reader structure"] -impl crate::Readable for SLC_RXLINK_DSCR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rxlink_dscr::W`](W) writer structure"] -impl crate::Writable for SLC_RXLINK_DSCR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RXLINK_DSCR to value 0"] -impl crate::Resettable for SLC_RXLINK_DSCR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rxlink_dscr_bf0.rs b/esp8266/src/slc/slc_rxlink_dscr_bf0.rs deleted file mode 100644 index 569e6ed198..0000000000 --- a/esp8266/src/slc/slc_rxlink_dscr_bf0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_RXLINK_DSCR_BF0` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RXLINK_DSCR_BF0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RXLINK_DSCR_BF0") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RXLINK_DSCR_BF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr_bf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr_bf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RXLINK_DSCR_BF0_SPEC; -impl crate::RegisterSpec for SLC_RXLINK_DSCR_BF0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rxlink_dscr_bf0::R`](R) reader structure"] -impl crate::Readable for SLC_RXLINK_DSCR_BF0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rxlink_dscr_bf0::W`](W) writer structure"] -impl crate::Writable for SLC_RXLINK_DSCR_BF0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RXLINK_DSCR_BF0 to value 0"] -impl crate::Resettable for SLC_RXLINK_DSCR_BF0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_rxlink_dscr_bf1.rs b/esp8266/src/slc/slc_rxlink_dscr_bf1.rs deleted file mode 100644 index 31501f7b26..0000000000 --- a/esp8266/src/slc/slc_rxlink_dscr_bf1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_RXLINK_DSCR_BF1` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_RXLINK_DSCR_BF1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_RXLINK_DSCR_BF1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_RXLINK_DSCR_BF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_rxlink_dscr_bf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_rxlink_dscr_bf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_RXLINK_DSCR_BF1_SPEC; -impl crate::RegisterSpec for SLC_RXLINK_DSCR_BF1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_rxlink_dscr_bf1::R`](R) reader structure"] -impl crate::Readable for SLC_RXLINK_DSCR_BF1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_rxlink_dscr_bf1::W`](W) writer structure"] -impl crate::Writable for SLC_RXLINK_DSCR_BF1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_RXLINK_DSCR_BF1 to value 0"] -impl crate::Resettable for SLC_RXLINK_DSCR_BF1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_sdio_st.rs b/esp8266/src/slc/slc_sdio_st.rs deleted file mode 100644 index 3d8cd756f7..0000000000 --- a/esp8266/src/slc/slc_sdio_st.rs +++ /dev/null @@ -1,117 +0,0 @@ -#[doc = "Register `SLC_SDIO_ST` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_SDIO_ST` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_CMD_ST` reader - "] -pub type SLC_CMD_ST_R = crate::FieldReader; -#[doc = "Field `SLC_CMD_ST` writer - "] -pub type SLC_CMD_ST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `SLC_FUNC_ST` reader - "] -pub type SLC_FUNC_ST_R = crate::FieldReader; -#[doc = "Field `SLC_FUNC_ST` writer - "] -pub type SLC_FUNC_ST_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `SLC_SDIO_WAKEUP` reader - "] -pub type SLC_SDIO_WAKEUP_R = crate::BitReader; -#[doc = "Field `SLC_SDIO_WAKEUP` writer - "] -pub type SLC_SDIO_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_BUS_ST` reader - "] -pub type SLC_BUS_ST_R = crate::FieldReader; -#[doc = "Field `SLC_BUS_ST` writer - "] -pub type SLC_BUS_ST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2"] - #[inline(always)] - pub fn slc_cmd_st(&self) -> SLC_CMD_ST_R { - SLC_CMD_ST_R::new((self.bits & 7) as u8) - } - #[doc = "Bits 4:7"] - #[inline(always)] - pub fn slc_func_st(&self) -> SLC_FUNC_ST_R { - SLC_FUNC_ST_R::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bit 8"] - #[inline(always)] - pub fn slc_sdio_wakeup(&self) -> SLC_SDIO_WAKEUP_R { - SLC_SDIO_WAKEUP_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bits 12:14"] - #[inline(always)] - pub fn slc_bus_st(&self) -> SLC_BUS_ST_R { - SLC_BUS_ST_R::new(((self.bits >> 12) & 7) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_SDIO_ST") - .field("slc_bus_st", &format_args!("{}", self.slc_bus_st().bits())) - .field( - "slc_sdio_wakeup", - &format_args!("{}", self.slc_sdio_wakeup().bit()), - ) - .field( - "slc_func_st", - &format_args!("{}", self.slc_func_st().bits()), - ) - .field("slc_cmd_st", &format_args!("{}", self.slc_cmd_st().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:2"] - #[inline(always)] - #[must_use] - pub fn slc_cmd_st(&mut self) -> SLC_CMD_ST_W { - SLC_CMD_ST_W::new(self, 0) - } - #[doc = "Bits 4:7"] - #[inline(always)] - #[must_use] - pub fn slc_func_st(&mut self) -> SLC_FUNC_ST_W { - SLC_FUNC_ST_W::new(self, 4) - } - #[doc = "Bit 8"] - #[inline(always)] - #[must_use] - pub fn slc_sdio_wakeup(&mut self) -> SLC_SDIO_WAKEUP_W { - SLC_SDIO_WAKEUP_W::new(self, 8) - } - #[doc = "Bits 12:14"] - #[inline(always)] - #[must_use] - pub fn slc_bus_st(&mut self) -> SLC_BUS_ST_W { - SLC_BUS_ST_W::new(self, 12) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_SDIO_ST\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_sdio_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_sdio_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_SDIO_ST_SPEC; -impl crate::RegisterSpec for SLC_SDIO_ST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_sdio_st::R`](R) reader structure"] -impl crate::Readable for SLC_SDIO_ST_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_sdio_st::W`](W) writer structure"] -impl crate::Writable for SLC_SDIO_ST_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_SDIO_ST to value 0"] -impl crate::Resettable for SLC_SDIO_ST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_state0.rs b/esp8266/src/slc/slc_state0.rs deleted file mode 100644 index c8aae6507a..0000000000 --- a/esp8266/src/slc/slc_state0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_STATE0` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_STATE0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_STATE0") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_STATE0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_state0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_state0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_STATE0_SPEC; -impl crate::RegisterSpec for SLC_STATE0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_state0::R`](R) reader structure"] -impl crate::Readable for SLC_STATE0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_state0::W`](W) writer structure"] -impl crate::Writable for SLC_STATE0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_STATE0 to value 0"] -impl crate::Resettable for SLC_STATE0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_state1.rs b/esp8266/src/slc/slc_state1.rs deleted file mode 100644 index d471105be1..0000000000 --- a/esp8266/src/slc/slc_state1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_STATE1` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_STATE1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_STATE1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_STATE1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_state1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_state1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_STATE1_SPEC; -impl crate::RegisterSpec for SLC_STATE1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_state1::R`](R) reader structure"] -impl crate::Readable for SLC_STATE1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_state1::W`](W) writer structure"] -impl crate::Writable for SLC_STATE1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_STATE1 to value 0"] -impl crate::Resettable for SLC_STATE1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_token0.rs b/esp8266/src/slc/slc_token0.rs deleted file mode 100644 index 0904c8de7c..0000000000 --- a/esp8266/src/slc/slc_token0.rs +++ /dev/null @@ -1,139 +0,0 @@ -#[doc = "Register `SLC_TOKEN0` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TOKEN0` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TOKEN0_LOCAL_WDATA` reader - "] -pub type SLC_TOKEN0_LOCAL_WDATA_R = crate::FieldReader; -#[doc = "Field `SLC_TOKEN0_LOCAL_WDATA` writer - "] -pub type SLC_TOKEN0_LOCAL_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `SLC_TOKEN0_LOCAL_WR` reader - "] -pub type SLC_TOKEN0_LOCAL_WR_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_LOCAL_WR` writer - "] -pub type SLC_TOKEN0_LOCAL_WR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_LOCAL_INC` reader - "] -pub type SLC_TOKEN0_LOCAL_INC_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_LOCAL_INC` writer - "] -pub type SLC_TOKEN0_LOCAL_INC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0_LOCAL_INC_MORE` reader - "] -pub type SLC_TOKEN0_LOCAL_INC_MORE_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN0_LOCAL_INC_MORE` writer - "] -pub type SLC_TOKEN0_LOCAL_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN0` reader - "] -pub type SLC_TOKEN0_R = crate::FieldReader; -#[doc = "Field `SLC_TOKEN0` writer - "] -pub type SLC_TOKEN0_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn slc_token0_local_wdata(&self) -> SLC_TOKEN0_LOCAL_WDATA_R { - SLC_TOKEN0_LOCAL_WDATA_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token0_local_wr(&self) -> SLC_TOKEN0_LOCAL_WR_R { - SLC_TOKEN0_LOCAL_WR_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token0_local_inc(&self) -> SLC_TOKEN0_LOCAL_INC_R { - SLC_TOKEN0_LOCAL_INC_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_token0_local_inc_more(&self) -> SLC_TOKEN0_LOCAL_INC_MORE_R { - SLC_TOKEN0_LOCAL_INC_MORE_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bits 16:27"] - #[inline(always)] - pub fn slc_token0(&self) -> SLC_TOKEN0_R { - SLC_TOKEN0_R::new(((self.bits >> 16) & 0x0fff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TOKEN0") - .field("slc_token0", &format_args!("{}", self.slc_token0().bits())) - .field( - "slc_token0_local_inc_more", - &format_args!("{}", self.slc_token0_local_inc_more().bit()), - ) - .field( - "slc_token0_local_inc", - &format_args!("{}", self.slc_token0_local_inc().bit()), - ) - .field( - "slc_token0_local_wr", - &format_args!("{}", self.slc_token0_local_wr().bit()), - ) - .field( - "slc_token0_local_wdata", - &format_args!("{}", self.slc_token0_local_wdata().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn slc_token0_local_wdata(&mut self) -> SLC_TOKEN0_LOCAL_WDATA_W { - SLC_TOKEN0_LOCAL_WDATA_W::new(self, 0) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token0_local_wr(&mut self) -> SLC_TOKEN0_LOCAL_WR_W { - SLC_TOKEN0_LOCAL_WR_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token0_local_inc(&mut self) -> SLC_TOKEN0_LOCAL_INC_W { - SLC_TOKEN0_LOCAL_INC_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_token0_local_inc_more(&mut self) -> SLC_TOKEN0_LOCAL_INC_MORE_W { - SLC_TOKEN0_LOCAL_INC_MORE_W::new(self, 14) - } - #[doc = "Bits 16:27"] - #[inline(always)] - #[must_use] - pub fn slc_token0(&mut self) -> SLC_TOKEN0_W { - SLC_TOKEN0_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TOKEN0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_token0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_token0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TOKEN0_SPEC; -impl crate::RegisterSpec for SLC_TOKEN0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_token0::R`](R) reader structure"] -impl crate::Readable for SLC_TOKEN0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_token0::W`](W) writer structure"] -impl crate::Writable for SLC_TOKEN0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TOKEN0 to value 0"] -impl crate::Resettable for SLC_TOKEN0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_token1.rs b/esp8266/src/slc/slc_token1.rs deleted file mode 100644 index 041a706465..0000000000 --- a/esp8266/src/slc/slc_token1.rs +++ /dev/null @@ -1,139 +0,0 @@ -#[doc = "Register `SLC_TOKEN1` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TOKEN1` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TOKEN1_LOCAL_WDATA` reader - "] -pub type SLC_TOKEN1_LOCAL_WDATA_R = crate::FieldReader; -#[doc = "Field `SLC_TOKEN1_LOCAL_WDATA` writer - "] -pub type SLC_TOKEN1_LOCAL_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `SLC_TOKEN1_LOCAL_WR` reader - "] -pub type SLC_TOKEN1_LOCAL_WR_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_LOCAL_WR` writer - "] -pub type SLC_TOKEN1_LOCAL_WR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_LOCAL_INC` reader - "] -pub type SLC_TOKEN1_LOCAL_INC_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_LOCAL_INC` writer - "] -pub type SLC_TOKEN1_LOCAL_INC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1_LOCAL_INC_MORE` reader - "] -pub type SLC_TOKEN1_LOCAL_INC_MORE_R = crate::BitReader; -#[doc = "Field `SLC_TOKEN1_LOCAL_INC_MORE` writer - "] -pub type SLC_TOKEN1_LOCAL_INC_MORE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TOKEN1` reader - "] -pub type SLC_TOKEN1_R = crate::FieldReader; -#[doc = "Field `SLC_TOKEN1` writer - "] -pub type SLC_TOKEN1_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn slc_token1_local_wdata(&self) -> SLC_TOKEN1_LOCAL_WDATA_R { - SLC_TOKEN1_LOCAL_WDATA_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bit 12"] - #[inline(always)] - pub fn slc_token1_local_wr(&self) -> SLC_TOKEN1_LOCAL_WR_R { - SLC_TOKEN1_LOCAL_WR_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13"] - #[inline(always)] - pub fn slc_token1_local_inc(&self) -> SLC_TOKEN1_LOCAL_INC_R { - SLC_TOKEN1_LOCAL_INC_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14"] - #[inline(always)] - pub fn slc_token1_local_inc_more(&self) -> SLC_TOKEN1_LOCAL_INC_MORE_R { - SLC_TOKEN1_LOCAL_INC_MORE_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bits 16:27"] - #[inline(always)] - pub fn slc_token1(&self) -> SLC_TOKEN1_R { - SLC_TOKEN1_R::new(((self.bits >> 16) & 0x0fff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TOKEN1") - .field("slc_token1", &format_args!("{}", self.slc_token1().bits())) - .field( - "slc_token1_local_inc_more", - &format_args!("{}", self.slc_token1_local_inc_more().bit()), - ) - .field( - "slc_token1_local_inc", - &format_args!("{}", self.slc_token1_local_inc().bit()), - ) - .field( - "slc_token1_local_wr", - &format_args!("{}", self.slc_token1_local_wr().bit()), - ) - .field( - "slc_token1_local_wdata", - &format_args!("{}", self.slc_token1_local_wdata().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn slc_token1_local_wdata(&mut self) -> SLC_TOKEN1_LOCAL_WDATA_W { - SLC_TOKEN1_LOCAL_WDATA_W::new(self, 0) - } - #[doc = "Bit 12"] - #[inline(always)] - #[must_use] - pub fn slc_token1_local_wr(&mut self) -> SLC_TOKEN1_LOCAL_WR_W { - SLC_TOKEN1_LOCAL_WR_W::new(self, 12) - } - #[doc = "Bit 13"] - #[inline(always)] - #[must_use] - pub fn slc_token1_local_inc(&mut self) -> SLC_TOKEN1_LOCAL_INC_W { - SLC_TOKEN1_LOCAL_INC_W::new(self, 13) - } - #[doc = "Bit 14"] - #[inline(always)] - #[must_use] - pub fn slc_token1_local_inc_more(&mut self) -> SLC_TOKEN1_LOCAL_INC_MORE_W { - SLC_TOKEN1_LOCAL_INC_MORE_W::new(self, 14) - } - #[doc = "Bits 16:27"] - #[inline(always)] - #[must_use] - pub fn slc_token1(&mut self) -> SLC_TOKEN1_W { - SLC_TOKEN1_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TOKEN1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_token1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_token1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TOKEN1_SPEC; -impl crate::RegisterSpec for SLC_TOKEN1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_token1::R`](R) reader structure"] -impl crate::Readable for SLC_TOKEN1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_token1::W`](W) writer structure"] -impl crate::Writable for SLC_TOKEN1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TOKEN1 to value 0"] -impl crate::Resettable for SLC_TOKEN1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_tx_eof_des_addr.rs b/esp8266/src/slc/slc_tx_eof_des_addr.rs deleted file mode 100644 index 18d77d5db0..0000000000 --- a/esp8266/src/slc/slc_tx_eof_des_addr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_TX_EOF_DES_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TX_EOF_DES_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TX_EOF_DES_ADDR") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TX_EOF_DES_ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_eof_des_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_eof_des_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TX_EOF_DES_ADDR_SPEC; -impl crate::RegisterSpec for SLC_TX_EOF_DES_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_tx_eof_des_addr::R`](R) reader structure"] -impl crate::Readable for SLC_TX_EOF_DES_ADDR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_tx_eof_des_addr::W`](W) writer structure"] -impl crate::Writable for SLC_TX_EOF_DES_ADDR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TX_EOF_DES_ADDR to value 0"] -impl crate::Resettable for SLC_TX_EOF_DES_ADDR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_tx_fifo_pop.rs b/esp8266/src/slc/slc_tx_fifo_pop.rs deleted file mode 100644 index 902107b3ae..0000000000 --- a/esp8266/src/slc/slc_tx_fifo_pop.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SLC_TX_FIFO_POP` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TX_FIFO_POP` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TXFIFO_RDATA` reader - "] -pub type SLC_TXFIFO_RDATA_R = crate::FieldReader; -#[doc = "Field `SLC_TXFIFO_RDATA` writer - "] -pub type SLC_TXFIFO_RDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; -#[doc = "Field `SLC_TXFIFO_POP` reader - "] -pub type SLC_TXFIFO_POP_R = crate::BitReader; -#[doc = "Field `SLC_TXFIFO_POP` writer - "] -pub type SLC_TXFIFO_POP_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:10"] - #[inline(always)] - pub fn slc_txfifo_rdata(&self) -> SLC_TXFIFO_RDATA_R { - SLC_TXFIFO_RDATA_R::new((self.bits & 0x07ff) as u16) - } - #[doc = "Bit 16"] - #[inline(always)] - pub fn slc_txfifo_pop(&self) -> SLC_TXFIFO_POP_R { - SLC_TXFIFO_POP_R::new(((self.bits >> 16) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TX_FIFO_POP") - .field( - "slc_txfifo_pop", - &format_args!("{}", self.slc_txfifo_pop().bit()), - ) - .field( - "slc_txfifo_rdata", - &format_args!("{}", self.slc_txfifo_rdata().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:10"] - #[inline(always)] - #[must_use] - pub fn slc_txfifo_rdata(&mut self) -> SLC_TXFIFO_RDATA_W { - SLC_TXFIFO_RDATA_W::new(self, 0) - } - #[doc = "Bit 16"] - #[inline(always)] - #[must_use] - pub fn slc_txfifo_pop(&mut self) -> SLC_TXFIFO_POP_W { - SLC_TXFIFO_POP_W::new(self, 16) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TX_FIFO_POP\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_fifo_pop::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_fifo_pop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TX_FIFO_POP_SPEC; -impl crate::RegisterSpec for SLC_TX_FIFO_POP_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_tx_fifo_pop::R`](R) reader structure"] -impl crate::Readable for SLC_TX_FIFO_POP_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_tx_fifo_pop::W`](W) writer structure"] -impl crate::Writable for SLC_TX_FIFO_POP_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TX_FIFO_POP to value 0"] -impl crate::Resettable for SLC_TX_FIFO_POP_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_tx_link.rs b/esp8266/src/slc/slc_tx_link.rs deleted file mode 100644 index 61968ba406..0000000000 --- a/esp8266/src/slc/slc_tx_link.rs +++ /dev/null @@ -1,142 +0,0 @@ -#[doc = "Register `SLC_TX_LINK` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TX_LINK` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TXLINK_ADDR` reader - "] -pub type SLC_TXLINK_ADDR_R = crate::FieldReader; -#[doc = "Field `SLC_TXLINK_ADDR` writer - "] -pub type SLC_TXLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -#[doc = "Field `SLC_TXLINK_STOP` reader - "] -pub type SLC_TXLINK_STOP_R = crate::BitReader; -#[doc = "Field `SLC_TXLINK_STOP` writer - "] -pub type SLC_TXLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TXLINK_START` reader - "] -pub type SLC_TXLINK_START_R = crate::BitReader; -#[doc = "Field `SLC_TXLINK_START` writer - "] -pub type SLC_TXLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TXLINK_RESTART` reader - "] -pub type SLC_TXLINK_RESTART_R = crate::BitReader; -#[doc = "Field `SLC_TXLINK_RESTART` writer - "] -pub type SLC_TXLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TXLINK_PARK` reader - "] -pub type SLC_TXLINK_PARK_R = crate::BitReader; -#[doc = "Field `SLC_TXLINK_PARK` writer - "] -pub type SLC_TXLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:19"] - #[inline(always)] - pub fn slc_txlink_addr(&self) -> SLC_TXLINK_ADDR_R { - SLC_TXLINK_ADDR_R::new(self.bits & 0x000f_ffff) - } - #[doc = "Bit 28"] - #[inline(always)] - pub fn slc_txlink_stop(&self) -> SLC_TXLINK_STOP_R { - SLC_TXLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29"] - #[inline(always)] - pub fn slc_txlink_start(&self) -> SLC_TXLINK_START_R { - SLC_TXLINK_START_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30"] - #[inline(always)] - pub fn slc_txlink_restart(&self) -> SLC_TXLINK_RESTART_R { - SLC_TXLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn slc_txlink_park(&self) -> SLC_TXLINK_PARK_R { - SLC_TXLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TX_LINK") - .field( - "slc_txlink_park", - &format_args!("{}", self.slc_txlink_park().bit()), - ) - .field( - "slc_txlink_restart", - &format_args!("{}", self.slc_txlink_restart().bit()), - ) - .field( - "slc_txlink_start", - &format_args!("{}", self.slc_txlink_start().bit()), - ) - .field( - "slc_txlink_stop", - &format_args!("{}", self.slc_txlink_stop().bit()), - ) - .field( - "slc_txlink_addr", - &format_args!("{}", self.slc_txlink_addr().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:19"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_addr(&mut self) -> SLC_TXLINK_ADDR_W { - SLC_TXLINK_ADDR_W::new(self, 0) - } - #[doc = "Bit 28"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_stop(&mut self) -> SLC_TXLINK_STOP_W { - SLC_TXLINK_STOP_W::new(self, 28) - } - #[doc = "Bit 29"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_start(&mut self) -> SLC_TXLINK_START_W { - SLC_TXLINK_START_W::new(self, 29) - } - #[doc = "Bit 30"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_restart(&mut self) -> SLC_TXLINK_RESTART_W { - SLC_TXLINK_RESTART_W::new(self, 30) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn slc_txlink_park(&mut self) -> SLC_TXLINK_PARK_W { - SLC_TXLINK_PARK_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TX_LINK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_link::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_link::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TX_LINK_SPEC; -impl crate::RegisterSpec for SLC_TX_LINK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_tx_link::R`](R) reader structure"] -impl crate::Readable for SLC_TX_LINK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_tx_link::W`](W) writer structure"] -impl crate::Writable for SLC_TX_LINK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TX_LINK to value 0"] -impl crate::Resettable for SLC_TX_LINK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_tx_status.rs b/esp8266/src/slc/slc_tx_status.rs deleted file mode 100644 index b6e89b8785..0000000000 --- a/esp8266/src/slc/slc_tx_status.rs +++ /dev/null @@ -1,82 +0,0 @@ -#[doc = "Register `SLC_TX_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TX_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `SLC_TX_FULL` reader - "] -pub type SLC_TX_FULL_R = crate::BitReader; -#[doc = "Field `SLC_TX_FULL` writer - "] -pub type SLC_TX_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLC_TX_EMPTY` reader - "] -pub type SLC_TX_EMPTY_R = crate::BitReader; -#[doc = "Field `SLC_TX_EMPTY` writer - "] -pub type SLC_TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0"] - #[inline(always)] - pub fn slc_tx_full(&self) -> SLC_TX_FULL_R { - SLC_TX_FULL_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1"] - #[inline(always)] - pub fn slc_tx_empty(&self) -> SLC_TX_EMPTY_R { - SLC_TX_EMPTY_R::new(((self.bits >> 1) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TX_STATUS") - .field( - "slc_tx_empty", - &format_args!("{}", self.slc_tx_empty().bit()), - ) - .field("slc_tx_full", &format_args!("{}", self.slc_tx_full().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0"] - #[inline(always)] - #[must_use] - pub fn slc_tx_full(&mut self) -> SLC_TX_FULL_W { - SLC_TX_FULL_W::new(self, 0) - } - #[doc = "Bit 1"] - #[inline(always)] - #[must_use] - pub fn slc_tx_empty(&mut self) -> SLC_TX_EMPTY_W { - SLC_TX_EMPTY_W::new(self, 1) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TX_STATUS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_tx_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_tx_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TX_STATUS_SPEC; -impl crate::RegisterSpec for SLC_TX_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_tx_status::R`](R) reader structure"] -impl crate::Readable for SLC_TX_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_tx_status::W`](W) writer structure"] -impl crate::Writable for SLC_TX_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TX_STATUS to value 0"] -impl crate::Resettable for SLC_TX_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_txlink_dscr.rs b/esp8266/src/slc/slc_txlink_dscr.rs deleted file mode 100644 index 730b09d5d6..0000000000 --- a/esp8266/src/slc/slc_txlink_dscr.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_TXLINK_DSCR` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TXLINK_DSCR` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TXLINK_DSCR") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TXLINK_DSCR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TXLINK_DSCR_SPEC; -impl crate::RegisterSpec for SLC_TXLINK_DSCR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_txlink_dscr::R`](R) reader structure"] -impl crate::Readable for SLC_TXLINK_DSCR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_txlink_dscr::W`](W) writer structure"] -impl crate::Writable for SLC_TXLINK_DSCR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TXLINK_DSCR to value 0"] -impl crate::Resettable for SLC_TXLINK_DSCR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_txlink_dscr_bf0.rs b/esp8266/src/slc/slc_txlink_dscr_bf0.rs deleted file mode 100644 index 57bc1effe7..0000000000 --- a/esp8266/src/slc/slc_txlink_dscr_bf0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_TXLINK_DSCR_BF0` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TXLINK_DSCR_BF0` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TXLINK_DSCR_BF0") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TXLINK_DSCR_BF0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr_bf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr_bf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TXLINK_DSCR_BF0_SPEC; -impl crate::RegisterSpec for SLC_TXLINK_DSCR_BF0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_txlink_dscr_bf0::R`](R) reader structure"] -impl crate::Readable for SLC_TXLINK_DSCR_BF0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_txlink_dscr_bf0::W`](W) writer structure"] -impl crate::Writable for SLC_TXLINK_DSCR_BF0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TXLINK_DSCR_BF0 to value 0"] -impl crate::Resettable for SLC_TXLINK_DSCR_BF0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/slc/slc_txlink_dscr_bf1.rs b/esp8266/src/slc/slc_txlink_dscr_bf1.rs deleted file mode 100644 index 17ef8edbdc..0000000000 --- a/esp8266/src/slc/slc_txlink_dscr_bf1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SLC_TXLINK_DSCR_BF1` reader"] -pub type R = crate::R; -#[doc = "Register `SLC_TXLINK_DSCR_BF1` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SLC_TXLINK_DSCR_BF1") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SLC_TXLINK_DSCR_BF1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_txlink_dscr_bf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slc_txlink_dscr_bf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SLC_TXLINK_DSCR_BF1_SPEC; -impl crate::RegisterSpec for SLC_TXLINK_DSCR_BF1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`slc_txlink_dscr_bf1::R`](R) reader structure"] -impl crate::Readable for SLC_TXLINK_DSCR_BF1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`slc_txlink_dscr_bf1::W`](W) writer structure"] -impl crate::Writable for SLC_TXLINK_DSCR_BF1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SLC_TXLINK_DSCR_BF1 to value 0"] -impl crate::Resettable for SLC_TXLINK_DSCR_BF1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0.rs b/esp8266/src/spi0.rs deleted file mode 100644 index 9be6b79f62..0000000000 --- a/esp8266/src/spi0.rs +++ /dev/null @@ -1,368 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - spi_cmd: SPI_CMD, - spi_addr: SPI_ADDR, - spi_ctrl: SPI_CTRL, - spi_ctrl1: SPI_CTRL1, - spi_rd_status: SPI_RD_STATUS, - spi_ctrl2: SPI_CTRL2, - spi_clock: SPI_CLOCK, - spi_user: SPI_USER, - spi_user1: SPI_USER1, - spi_user2: SPI_USER2, - spi_wr_status: SPI_WR_STATUS, - spi_pin: SPI_PIN, - spi_slave: SPI_SLAVE, - spi_slave1: SPI_SLAVE1, - spi_slave2: SPI_SLAVE2, - spi_slave3: SPI_SLAVE3, - spi_w0: SPI_W0, - spi_w1: SPI_W1, - spi_w2: SPI_W2, - spi_w3: SPI_W3, - spi_w4: SPI_W4, - spi_w5: SPI_W5, - spi_w6: SPI_W6, - spi_w7: SPI_W7, - spi_w8: SPI_W8, - spi_w9: SPI_W9, - spi_w10: SPI_W10, - spi_w11: SPI_W11, - spi_w12: SPI_W12, - spi_w13: SPI_W13, - spi_w14: SPI_W14, - spi_w15: SPI_W15, - _reserved32: [u8; 0x70], - spi_ext0: SPI_EXT0, - spi_ext1: SPI_EXT1, - spi_ext2: SPI_EXT2, - spi_ext3: SPI_EXT3, -} -impl RegisterBlock { - #[doc = "0x00 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - pub const fn spi_cmd(&self) -> &SPI_CMD { - &self.spi_cmd - } - #[doc = "0x04 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - pub const fn spi_addr(&self) -> &SPI_ADDR { - &self.spi_addr - } - #[doc = "0x08 - SPI_CTRL"] - #[inline(always)] - pub const fn spi_ctrl(&self) -> &SPI_CTRL { - &self.spi_ctrl - } - #[doc = "0x0c - "] - #[inline(always)] - pub const fn spi_ctrl1(&self) -> &SPI_CTRL1 { - &self.spi_ctrl1 - } - #[doc = "0x10 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - pub const fn spi_rd_status(&self) -> &SPI_RD_STATUS { - &self.spi_rd_status - } - #[doc = "0x14 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - pub const fn spi_ctrl2(&self) -> &SPI_CTRL2 { - &self.spi_ctrl2 - } - #[doc = "0x18 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - pub const fn spi_clock(&self) -> &SPI_CLOCK { - &self.spi_clock - } - #[doc = "0x1c - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - pub const fn spi_user(&self) -> &SPI_USER { - &self.spi_user - } - #[doc = "0x20 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_user1(&self) -> &SPI_USER1 { - &self.spi_user1 - } - #[doc = "0x24 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_user2(&self) -> &SPI_USER2 { - &self.spi_user2 - } - #[doc = "0x28 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - pub const fn spi_wr_status(&self) -> &SPI_WR_STATUS { - &self.spi_wr_status - } - #[doc = "0x2c - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - pub const fn spi_pin(&self) -> &SPI_PIN { - &self.spi_pin - } - #[doc = "0x30 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - pub const fn spi_slave(&self) -> &SPI_SLAVE { - &self.spi_slave - } - #[doc = "0x34 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_slave1(&self) -> &SPI_SLAVE1 { - &self.spi_slave1 - } - #[doc = "0x38 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub const fn spi_slave2(&self) -> &SPI_SLAVE2 { - &self.spi_slave2 - } - #[doc = "0x3c - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - pub const fn spi_slave3(&self) -> &SPI_SLAVE3 { - &self.spi_slave3 - } - #[doc = "0x40 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - pub const fn spi_w0(&self) -> &SPI_W0 { - &self.spi_w0 - } - #[doc = "0x44 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - pub const fn spi_w1(&self) -> &SPI_W1 { - &self.spi_w1 - } - #[doc = "0x48 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - pub const fn spi_w2(&self) -> &SPI_W2 { - &self.spi_w2 - } - #[doc = "0x4c - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - pub const fn spi_w3(&self) -> &SPI_W3 { - &self.spi_w3 - } - #[doc = "0x50 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - pub const fn spi_w4(&self) -> &SPI_W4 { - &self.spi_w4 - } - #[doc = "0x54 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - pub const fn spi_w5(&self) -> &SPI_W5 { - &self.spi_w5 - } - #[doc = "0x58 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - pub const fn spi_w6(&self) -> &SPI_W6 { - &self.spi_w6 - } - #[doc = "0x5c - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - pub const fn spi_w7(&self) -> &SPI_W7 { - &self.spi_w7 - } - #[doc = "0x60 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - pub const fn spi_w8(&self) -> &SPI_W8 { - &self.spi_w8 - } - #[doc = "0x64 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - pub const fn spi_w9(&self) -> &SPI_W9 { - &self.spi_w9 - } - #[doc = "0x68 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - pub const fn spi_w10(&self) -> &SPI_W10 { - &self.spi_w10 - } - #[doc = "0x6c - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - pub const fn spi_w11(&self) -> &SPI_W11 { - &self.spi_w11 - } - #[doc = "0x70 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - pub const fn spi_w12(&self) -> &SPI_W12 { - &self.spi_w12 - } - #[doc = "0x74 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - pub const fn spi_w13(&self) -> &SPI_W13 { - &self.spi_w13 - } - #[doc = "0x78 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - pub const fn spi_w14(&self) -> &SPI_W14 { - &self.spi_w14 - } - #[doc = "0x7c - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - pub const fn spi_w15(&self) -> &SPI_W15 { - &self.spi_w15 - } - #[doc = "0xf0 - "] - #[inline(always)] - pub const fn spi_ext0(&self) -> &SPI_EXT0 { - &self.spi_ext0 - } - #[doc = "0xf4 - "] - #[inline(always)] - pub const fn spi_ext1(&self) -> &SPI_EXT1 { - &self.spi_ext1 - } - #[doc = "0xf8 - "] - #[inline(always)] - pub const fn spi_ext2(&self) -> &SPI_EXT2 { - &self.spi_ext2 - } - #[doc = "0xfc - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - pub const fn spi_ext3(&self) -> &SPI_EXT3 { - &self.spi_ext3 - } -} -#[doc = "SPI_CMD (rw) register accessor: In the master mode, it is the start bit of a single operation. Self-clear by hardware\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cmd`] module"] -pub type SPI_CMD = crate::Reg; -#[doc = "In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub mod spi_cmd; -#[doc = "SPI_ADDR (rw) register accessor: In the master mode, it is the value of address in \"address\" phase.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_addr`] module"] -pub type SPI_ADDR = crate::Reg; -#[doc = "In the master mode, it is the value of address in \"address\" phase."] -pub mod spi_addr; -#[doc = "SPI_CTRL (rw) register accessor: SPI_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl`] module"] -pub type SPI_CTRL = crate::Reg; -#[doc = "SPI_CTRL"] -pub mod spi_ctrl; -#[doc = "SPI_RD_STATUS (rw) register accessor: In the slave mode, this register are the status register for the master to read out.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rd_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rd_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rd_status`] module"] -pub type SPI_RD_STATUS = crate::Reg; -#[doc = "In the slave mode, this register are the status register for the master to read out."] -pub mod spi_rd_status; -#[doc = "SPI_CTRL2 (rw) register accessor: spi_cs signal is delayed by 80MHz clock cycles\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl2`] module"] -pub type SPI_CTRL2 = crate::Reg; -#[doc = "spi_cs signal is delayed by 80MHz clock cycles"] -pub mod spi_ctrl2; -#[doc = "SPI_CLOCK (rw) register accessor: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clock`] module"] -pub type SPI_CLOCK = crate::Reg; -#[doc = "In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub mod spi_clock; -#[doc = "SPI_USER (rw) register accessor: This bit enable the \"command\" phase of an operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user`] module"] -pub type SPI_USER = crate::Reg; -#[doc = "This bit enable the \"command\" phase of an operation."] -pub mod spi_user; -#[doc = "SPI_USER1 (rw) register accessor: The length in bits of \"address\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user1`] module"] -pub type SPI_USER1 = crate::Reg; -#[doc = "The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub mod spi_user1; -#[doc = "SPI_USER2 (rw) register accessor: The length in bits of \"command\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user2`] module"] -pub type SPI_USER2 = crate::Reg; -#[doc = "The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub mod spi_user2; -#[doc = "SPI_WR_STATUS (rw) register accessor: In the slave mode, this register are the status register for the master to write into.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_wr_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_wr_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wr_status`] module"] -pub type SPI_WR_STATUS = crate::Reg; -#[doc = "In the slave mode, this register are the status register for the master to write into."] -pub mod spi_wr_status; -#[doc = "SPI_PIN (rw) register accessor: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_pin::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_pin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_pin`] module"] -pub type SPI_PIN = crate::Reg; -#[doc = "1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub mod spi_pin; -#[doc = "SPI_SLAVE (rw) register accessor: It is the synchronous reset signal of the module. This bit is self-cleared by hardware.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave`] module"] -pub type SPI_SLAVE = crate::Reg; -#[doc = "It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub mod spi_slave; -#[doc = "SPI_SLAVE1 (rw) register accessor: In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave1`] module"] -pub type SPI_SLAVE1 = crate::Reg; -#[doc = "In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub mod spi_slave1; -#[doc = "SPI_SLAVE2 (rw) register accessor: In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave2`] module"] -pub type SPI_SLAVE2 = crate::Reg; -#[doc = "In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub mod spi_slave2; -#[doc = "SPI_SLAVE3 (rw) register accessor: In slave mode, it is the value of \"write-status\" command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave3`] module"] -pub type SPI_SLAVE3 = crate::Reg; -#[doc = "In slave mode, it is the value of \"write-status\" command"] -pub mod spi_slave3; -#[doc = "SPI_EXT3 (rw) register accessor: This register is for two SPI masters to share the same cs, clock and data signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext3`] module"] -pub type SPI_EXT3 = crate::Reg; -#[doc = "This register is for two SPI masters to share the same cs, clock and data signals."] -pub mod spi_ext3; -#[doc = "SPI_W0 (rw) register accessor: the data inside the buffer of the SPI module, word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w0`] module"] -pub type SPI_W0 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 0"] -pub mod spi_w0; -#[doc = "SPI_W1 (rw) register accessor: the data inside the buffer of the SPI module, word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w1`] module"] -pub type SPI_W1 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 1"] -pub mod spi_w1; -#[doc = "SPI_W2 (rw) register accessor: the data inside the buffer of the SPI module, word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w2`] module"] -pub type SPI_W2 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 2"] -pub mod spi_w2; -#[doc = "SPI_W3 (rw) register accessor: the data inside the buffer of the SPI module, word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w3`] module"] -pub type SPI_W3 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 3"] -pub mod spi_w3; -#[doc = "SPI_W4 (rw) register accessor: the data inside the buffer of the SPI module, word 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w4`] module"] -pub type SPI_W4 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 4"] -pub mod spi_w4; -#[doc = "SPI_W5 (rw) register accessor: the data inside the buffer of the SPI module, word 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w5`] module"] -pub type SPI_W5 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 5"] -pub mod spi_w5; -#[doc = "SPI_W6 (rw) register accessor: the data inside the buffer of the SPI module, word 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w6`] module"] -pub type SPI_W6 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 6"] -pub mod spi_w6; -#[doc = "SPI_W7 (rw) register accessor: the data inside the buffer of the SPI module, word 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w7`] module"] -pub type SPI_W7 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 7"] -pub mod spi_w7; -#[doc = "SPI_W8 (rw) register accessor: the data inside the buffer of the SPI module, word 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w8`] module"] -pub type SPI_W8 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 8"] -pub mod spi_w8; -#[doc = "SPI_W9 (rw) register accessor: the data inside the buffer of the SPI module, word 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w9`] module"] -pub type SPI_W9 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 9"] -pub mod spi_w9; -#[doc = "SPI_W10 (rw) register accessor: the data inside the buffer of the SPI module, word 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w10`] module"] -pub type SPI_W10 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 10"] -pub mod spi_w10; -#[doc = "SPI_W11 (rw) register accessor: the data inside the buffer of the SPI module, word 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w11`] module"] -pub type SPI_W11 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 11"] -pub mod spi_w11; -#[doc = "SPI_W12 (rw) register accessor: the data inside the buffer of the SPI module, word 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w12`] module"] -pub type SPI_W12 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 12"] -pub mod spi_w12; -#[doc = "SPI_W13 (rw) register accessor: the data inside the buffer of the SPI module, word 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w13`] module"] -pub type SPI_W13 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 13"] -pub mod spi_w13; -#[doc = "SPI_W14 (rw) register accessor: the data inside the buffer of the SPI module, word 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w14`] module"] -pub type SPI_W14 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 14"] -pub mod spi_w14; -#[doc = "SPI_W15 (rw) register accessor: the data inside the buffer of the SPI module, word 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w15`] module"] -pub type SPI_W15 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 15"] -pub mod spi_w15; -#[doc = "SPI_CTRL1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl1`] module"] -pub type SPI_CTRL1 = crate::Reg; -#[doc = ""] -pub mod spi_ctrl1; -#[doc = "SPI_EXT0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext0`] module"] -pub type SPI_EXT0 = crate::Reg; -#[doc = ""] -pub mod spi_ext0; -#[doc = "SPI_EXT1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext1`] module"] -pub type SPI_EXT1 = crate::Reg; -#[doc = ""] -pub mod spi_ext1; -#[doc = "SPI_EXT2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext2`] module"] -pub type SPI_EXT2 = crate::Reg; -#[doc = ""] -pub mod spi_ext2; diff --git a/esp8266/src/spi0/spi_addr.rs b/esp8266/src/spi0/spi_addr.rs deleted file mode 100644 index 799938b12c..0000000000 --- a/esp8266/src/spi0/spi_addr.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `SPI_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `iodata_start_addr` reader - In the master mode, it is the value of address in \"address\" phase."] -pub type IODATA_START_ADDR_R = crate::FieldReader; -#[doc = "Field `iodata_start_addr` writer - In the master mode, it is the value of address in \"address\" phase."] -pub type IODATA_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `address` reader - "] -pub type ADDRESS_R = crate::FieldReader; -#[doc = "Field `address` writer - "] -pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -#[doc = "Field `size` reader - "] -pub type SIZE_R = crate::FieldReader; -#[doc = "Field `size` writer - "] -pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - pub fn iodata_start_addr(&self) -> IODATA_START_ADDR_R { - IODATA_START_ADDR_R::new(self.bits) - } - #[doc = "Bits 0:23"] - #[inline(always)] - pub fn address(&self) -> ADDRESS_R { - ADDRESS_R::new(self.bits & 0x00ff_ffff) - } - #[doc = "Bits 24:31"] - #[inline(always)] - pub fn size(&self) -> SIZE_R { - SIZE_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_ADDR") - .field( - "iodata_start_addr", - &format_args!("{}", self.iodata_start_addr().bits()), - ) - .field("address", &format_args!("{}", self.address().bits())) - .field("size", &format_args!("{}", self.size().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - #[must_use] - pub fn iodata_start_addr(&mut self) -> IODATA_START_ADDR_W { - IODATA_START_ADDR_W::new(self, 0) - } - #[doc = "Bits 0:23"] - #[inline(always)] - #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self, 0) - } - #[doc = "Bits 24:31"] - #[inline(always)] - #[must_use] - pub fn size(&mut self) -> SIZE_W { - SIZE_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, it is the value of address in \"address\" phase.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_ADDR_SPEC; -impl crate::RegisterSpec for SPI_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_addr::R`](R) reader structure"] -impl crate::Readable for SPI_ADDR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_addr::W`](W) writer structure"] -impl crate::Writable for SPI_ADDR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_ADDR to value 0"] -impl crate::Resettable for SPI_ADDR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_clock.rs b/esp8266/src/spi0/spi_clock.rs deleted file mode 100644 index 1fe6e08bae..0000000000 --- a/esp8266/src/spi0/spi_clock.rs +++ /dev/null @@ -1,142 +0,0 @@ -#[doc = "Register `SPI_CLOCK` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CLOCK` writer"] -pub type W = crate::W; -#[doc = "Field `spi_clkcnt_L` reader - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] -pub type SPI_CLKCNT_L_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_L` writer - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] -pub type SPI_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkcnt_H` reader - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] -pub type SPI_CLKCNT_H_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_H` writer - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] -pub type SPI_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkcnt_N` reader - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] -pub type SPI_CLKCNT_N_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_N` writer - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] -pub type SPI_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkdiv_pre` reader - In the master mode, it is pre-divider of spi_clk."] -pub type SPI_CLKDIV_PRE_R = crate::FieldReader; -#[doc = "Field `spi_clkdiv_pre` writer - In the master mode, it is pre-divider of spi_clk."] -pub type SPI_CLKDIV_PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -#[doc = "Field `spi_clk_equ_sysclk` reader - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub type SPI_CLK_EQU_SYSCLK_R = crate::BitReader; -#[doc = "Field `spi_clk_equ_sysclk` writer - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub type SPI_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] - #[inline(always)] - pub fn spi_clkcnt_l(&self) -> SPI_CLKCNT_L_R { - SPI_CLKCNT_L_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] - #[inline(always)] - pub fn spi_clkcnt_h(&self) -> SPI_CLKCNT_H_R { - SPI_CLKCNT_H_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:17 - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] - #[inline(always)] - pub fn spi_clkcnt_n(&self) -> SPI_CLKCNT_N_R { - SPI_CLKCNT_N_R::new(((self.bits >> 12) & 0x3f) as u8) - } - #[doc = "Bits 18:30 - In the master mode, it is pre-divider of spi_clk."] - #[inline(always)] - pub fn spi_clkdiv_pre(&self) -> SPI_CLKDIV_PRE_R { - SPI_CLKDIV_PRE_R::new(((self.bits >> 18) & 0x1fff) as u16) - } - #[doc = "Bit 31 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - pub fn spi_clk_equ_sysclk(&self) -> SPI_CLK_EQU_SYSCLK_R { - SPI_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CLOCK") - .field( - "spi_clk_equ_sysclk", - &format_args!("{}", self.spi_clk_equ_sysclk().bit()), - ) - .field( - "spi_clkdiv_pre", - &format_args!("{}", self.spi_clkdiv_pre().bits()), - ) - .field( - "spi_clkcnt_n", - &format_args!("{}", self.spi_clkcnt_n().bits()), - ) - .field( - "spi_clkcnt_h", - &format_args!("{}", self.spi_clkcnt_h().bits()), - ) - .field( - "spi_clkcnt_l", - &format_args!("{}", self.spi_clkcnt_l().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:5 - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_l(&mut self) -> SPI_CLKCNT_L_W { - SPI_CLKCNT_L_W::new(self, 0) - } - #[doc = "Bits 6:11 - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_h(&mut self) -> SPI_CLKCNT_H_W { - SPI_CLKCNT_H_W::new(self, 6) - } - #[doc = "Bits 12:17 - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_n(&mut self) -> SPI_CLKCNT_N_W { - SPI_CLKCNT_N_W::new(self, 12) - } - #[doc = "Bits 18:30 - In the master mode, it is pre-divider of spi_clk."] - #[inline(always)] - #[must_use] - pub fn spi_clkdiv_pre(&mut self) -> SPI_CLKDIV_PRE_W { - SPI_CLKDIV_PRE_W::new(self, 18) - } - #[doc = "Bit 31 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - #[must_use] - pub fn spi_clk_equ_sysclk(&mut self) -> SPI_CLK_EQU_SYSCLK_W { - SPI_CLK_EQU_SYSCLK_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CLOCK_SPEC; -impl crate::RegisterSpec for SPI_CLOCK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_clock::R`](R) reader structure"] -impl crate::Readable for SPI_CLOCK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_clock::W`](W) writer structure"] -impl crate::Writable for SPI_CLOCK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CLOCK to value 0"] -impl crate::Resettable for SPI_CLOCK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_cmd.rs b/esp8266/src/spi0/spi_cmd.rs deleted file mode 100644 index 80c59b0e14..0000000000 --- a/esp8266/src/spi0/spi_cmd.rs +++ /dev/null @@ -1,280 +0,0 @@ -#[doc = "Register `SPI_CMD` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CMD` writer"] -pub type W = crate::W; -#[doc = "Field `spi_usr` reader - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub type SPI_USR_R = crate::BitReader; -#[doc = "Field `spi_usr` writer - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub type SPI_USR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_hpm` reader - "] -pub type SPI_HPM_R = crate::BitReader; -#[doc = "Field `spi_hpm` writer - "] -pub type SPI_HPM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_res` reader - "] -pub type SPI_RES_R = crate::BitReader; -#[doc = "Field `spi_res` writer - "] -pub type SPI_RES_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dp` reader - "] -pub type SPI_DP_R = crate::BitReader; -#[doc = "Field `spi_dp` writer - "] -pub type SPI_DP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ce` reader - "] -pub type SPI_CE_R = crate::BitReader; -#[doc = "Field `spi_ce` writer - "] -pub type SPI_CE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_be` reader - "] -pub type SPI_BE_R = crate::BitReader; -#[doc = "Field `spi_be` writer - "] -pub type SPI_BE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_se` reader - "] -pub type SPI_SE_R = crate::BitReader; -#[doc = "Field `spi_se` writer - "] -pub type SPI_SE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_pp` reader - "] -pub type SPI_PP_R = crate::BitReader; -#[doc = "Field `spi_pp` writer - "] -pub type SPI_PP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_sr` reader - "] -pub type SPI_WRITE_SR_R = crate::BitReader; -#[doc = "Field `spi_write_sr` writer - "] -pub type SPI_WRITE_SR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read_sr` reader - "] -pub type SPI_READ_SR_R = crate::BitReader; -#[doc = "Field `spi_read_sr` writer - "] -pub type SPI_READ_SR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read_id` reader - "] -pub type SPI_READ_ID_R = crate::BitReader; -#[doc = "Field `spi_read_id` writer - "] -pub type SPI_READ_ID_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_disable` reader - "] -pub type SPI_WRITE_DISABLE_R = crate::BitReader; -#[doc = "Field `spi_write_disable` writer - "] -pub type SPI_WRITE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_enable` reader - "] -pub type SPI_WRITE_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_write_enable` writer - "] -pub type SPI_WRITE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read` reader - "] -pub type SPI_READ_R = crate::BitReader; -#[doc = "Field `spi_read` writer - "] -pub type SPI_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 18 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - pub fn spi_usr(&self) -> SPI_USR_R { - SPI_USR_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn spi_hpm(&self) -> SPI_HPM_R { - SPI_HPM_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn spi_res(&self) -> SPI_RES_R { - SPI_RES_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn spi_dp(&self) -> SPI_DP_R { - SPI_DP_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22"] - #[inline(always)] - pub fn spi_ce(&self) -> SPI_CE_R { - SPI_CE_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23"] - #[inline(always)] - pub fn spi_be(&self) -> SPI_BE_R { - SPI_BE_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24"] - #[inline(always)] - pub fn spi_se(&self) -> SPI_SE_R { - SPI_SE_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25"] - #[inline(always)] - pub fn spi_pp(&self) -> SPI_PP_R { - SPI_PP_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26"] - #[inline(always)] - pub fn spi_write_sr(&self) -> SPI_WRITE_SR_R { - SPI_WRITE_SR_R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27"] - #[inline(always)] - pub fn spi_read_sr(&self) -> SPI_READ_SR_R { - SPI_READ_SR_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28"] - #[inline(always)] - pub fn spi_read_id(&self) -> SPI_READ_ID_R { - SPI_READ_ID_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29"] - #[inline(always)] - pub fn spi_write_disable(&self) -> SPI_WRITE_DISABLE_R { - SPI_WRITE_DISABLE_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30"] - #[inline(always)] - pub fn spi_write_enable(&self) -> SPI_WRITE_ENABLE_R { - SPI_WRITE_ENABLE_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn spi_read(&self) -> SPI_READ_R { - SPI_READ_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CMD") - .field("spi_usr", &format_args!("{}", self.spi_usr().bit())) - .field("spi_read", &format_args!("{}", self.spi_read().bit())) - .field( - "spi_write_enable", - &format_args!("{}", self.spi_write_enable().bit()), - ) - .field( - "spi_write_disable", - &format_args!("{}", self.spi_write_disable().bit()), - ) - .field("spi_read_id", &format_args!("{}", self.spi_read_id().bit())) - .field("spi_read_sr", &format_args!("{}", self.spi_read_sr().bit())) - .field( - "spi_write_sr", - &format_args!("{}", self.spi_write_sr().bit()), - ) - .field("spi_pp", &format_args!("{}", self.spi_pp().bit())) - .field("spi_se", &format_args!("{}", self.spi_se().bit())) - .field("spi_be", &format_args!("{}", self.spi_be().bit())) - .field("spi_ce", &format_args!("{}", self.spi_ce().bit())) - .field("spi_dp", &format_args!("{}", self.spi_dp().bit())) - .field("spi_res", &format_args!("{}", self.spi_res().bit())) - .field("spi_hpm", &format_args!("{}", self.spi_hpm().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 18 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - #[must_use] - pub fn spi_usr(&mut self) -> SPI_USR_W { - SPI_USR_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn spi_hpm(&mut self) -> SPI_HPM_W { - SPI_HPM_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn spi_res(&mut self) -> SPI_RES_W { - SPI_RES_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn spi_dp(&mut self) -> SPI_DP_W { - SPI_DP_W::new(self, 21) - } - #[doc = "Bit 22"] - #[inline(always)] - #[must_use] - pub fn spi_ce(&mut self) -> SPI_CE_W { - SPI_CE_W::new(self, 22) - } - #[doc = "Bit 23"] - #[inline(always)] - #[must_use] - pub fn spi_be(&mut self) -> SPI_BE_W { - SPI_BE_W::new(self, 23) - } - #[doc = "Bit 24"] - #[inline(always)] - #[must_use] - pub fn spi_se(&mut self) -> SPI_SE_W { - SPI_SE_W::new(self, 24) - } - #[doc = "Bit 25"] - #[inline(always)] - #[must_use] - pub fn spi_pp(&mut self) -> SPI_PP_W { - SPI_PP_W::new(self, 25) - } - #[doc = "Bit 26"] - #[inline(always)] - #[must_use] - pub fn spi_write_sr(&mut self) -> SPI_WRITE_SR_W { - SPI_WRITE_SR_W::new(self, 26) - } - #[doc = "Bit 27"] - #[inline(always)] - #[must_use] - pub fn spi_read_sr(&mut self) -> SPI_READ_SR_W { - SPI_READ_SR_W::new(self, 27) - } - #[doc = "Bit 28"] - #[inline(always)] - #[must_use] - pub fn spi_read_id(&mut self) -> SPI_READ_ID_W { - SPI_READ_ID_W::new(self, 28) - } - #[doc = "Bit 29"] - #[inline(always)] - #[must_use] - pub fn spi_write_disable(&mut self) -> SPI_WRITE_DISABLE_W { - SPI_WRITE_DISABLE_W::new(self, 29) - } - #[doc = "Bit 30"] - #[inline(always)] - #[must_use] - pub fn spi_write_enable(&mut self) -> SPI_WRITE_ENABLE_W { - SPI_WRITE_ENABLE_W::new(self, 30) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn spi_read(&mut self) -> SPI_READ_W { - SPI_READ_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, it is the start bit of a single operation. Self-clear by hardware\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CMD_SPEC; -impl crate::RegisterSpec for SPI_CMD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_cmd::R`](R) reader structure"] -impl crate::Readable for SPI_CMD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_cmd::W`](W) writer structure"] -impl crate::Writable for SPI_CMD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CMD to value 0"] -impl crate::Resettable for SPI_CMD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ctrl.rs b/esp8266/src/spi0/spi_ctrl.rs deleted file mode 100644 index f55e8560f8..0000000000 --- a/esp8266/src/spi0/spi_ctrl.rs +++ /dev/null @@ -1,295 +0,0 @@ -#[doc = "Register `SPI_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `spi_fastrd_mode` reader - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] -pub type SPI_FASTRD_MODE_R = crate::BitReader; -#[doc = "Field `spi_fastrd_mode` writer - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] -pub type SPI_FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dout_mode` reader - In the read operations, \"read-data\" phase apply 2 signals"] -pub type SPI_DOUT_MODE_R = crate::BitReader; -#[doc = "Field `spi_dout_mode` writer - In the read operations, \"read-data\" phase apply 2 signals"] -pub type SPI_DOUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `res_and_res` reader - 'Res and res'?"] -pub type RES_AND_RES_R = crate::BitReader; -#[doc = "Field `res_and_res` writer - 'Res and res'?"] -pub type RES_AND_RES_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sst_aai` reader - SST_AAI?"] -pub type SST_AAI_R = crate::BitReader; -#[doc = "Field `sst_aai` writer - SST_AAI?"] -pub type SST_AAI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `enable_ahb` reader - Enable AHB"] -pub type ENABLE_AHB_R = crate::BitReader; -#[doc = "Field `enable_ahb` writer - Enable AHB"] -pub type ENABLE_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `hold_mode` reader - Hold mode"] -pub type HOLD_MODE_R = crate::BitReader; -#[doc = "Field `hold_mode` writer - Hold mode"] -pub type HOLD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `share_but` reader - Share bus"] -pub type SHARE_BUT_R = crate::BitReader; -#[doc = "Field `share_but` writer - Share bus"] -pub type SHARE_BUT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_qout_mode` reader - In the read operations, \"read-data\" phase apply 4 signals"] -pub type SPI_QOUT_MODE_R = crate::BitReader; -#[doc = "Field `spi_qout_mode` writer - In the read operations, \"read-data\" phase apply 4 signals"] -pub type SPI_QOUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `wp_reg` reader - Write protect?"] -pub type WP_REG_R = crate::BitReader; -#[doc = "Field `wp_reg` writer - Write protect?"] -pub type WP_REG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `two_byte_status` reader - Enable two byte status"] -pub type TWO_BYTE_STATUS_R = crate::BitReader; -#[doc = "Field `two_byte_status` writer - Enable two byte status"] -pub type TWO_BYTE_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dio_mode` reader - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_DIO_MODE_R = crate::BitReader; -#[doc = "Field `spi_dio_mode` writer - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_DIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_qio_mode` reader - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_QIO_MODE_R = crate::BitReader; -#[doc = "Field `spi_qio_mode` writer - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_QIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_rd_bit_order` reader - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] -pub type SPI_RD_BIT_ORDER_R = crate::BitReader; -#[doc = "Field `spi_rd_bit_order` writer - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] -pub type SPI_RD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_wr_bit_order` reader - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] -pub type SPI_WR_BIT_ORDER_R = crate::BitReader; -#[doc = "Field `spi_wr_bit_order` writer - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] -pub type SPI_WR_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 13 - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] - #[inline(always)] - pub fn spi_fastrd_mode(&self) -> SPI_FASTRD_MODE_R { - SPI_FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - In the read operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_dout_mode(&self) -> SPI_DOUT_MODE_R { - SPI_DOUT_MODE_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - 'Res and res'?"] - #[inline(always)] - pub fn res_and_res(&self) -> RES_AND_RES_R { - RES_AND_RES_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - SST_AAI?"] - #[inline(always)] - pub fn sst_aai(&self) -> SST_AAI_R { - SST_AAI_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Enable AHB"] - #[inline(always)] - pub fn enable_ahb(&self) -> ENABLE_AHB_R { - ENABLE_AHB_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Hold mode"] - #[inline(always)] - pub fn hold_mode(&self) -> HOLD_MODE_R { - HOLD_MODE_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Share bus"] - #[inline(always)] - pub fn share_but(&self) -> SHARE_BUT_R { - SHARE_BUT_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - In the read operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_qout_mode(&self) -> SPI_QOUT_MODE_R { - SPI_QOUT_MODE_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Write protect?"] - #[inline(always)] - pub fn wp_reg(&self) -> WP_REG_R { - WP_REG_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Enable two byte status"] - #[inline(always)] - pub fn two_byte_status(&self) -> TWO_BYTE_STATUS_R { - TWO_BYTE_STATUS_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_dio_mode(&self) -> SPI_DIO_MODE_R { - SPI_DIO_MODE_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_qio_mode(&self) -> SPI_QIO_MODE_R { - SPI_QIO_MODE_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] - #[inline(always)] - pub fn spi_rd_bit_order(&self) -> SPI_RD_BIT_ORDER_R { - SPI_RD_BIT_ORDER_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] - #[inline(always)] - pub fn spi_wr_bit_order(&self) -> SPI_WR_BIT_ORDER_R { - SPI_WR_BIT_ORDER_R::new(((self.bits >> 26) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL") - .field( - "spi_wr_bit_order", - &format_args!("{}", self.spi_wr_bit_order().bit()), - ) - .field( - "spi_rd_bit_order", - &format_args!("{}", self.spi_rd_bit_order().bit()), - ) - .field( - "spi_qio_mode", - &format_args!("{}", self.spi_qio_mode().bit()), - ) - .field( - "spi_dio_mode", - &format_args!("{}", self.spi_dio_mode().bit()), - ) - .field( - "spi_qout_mode", - &format_args!("{}", self.spi_qout_mode().bit()), - ) - .field( - "spi_dout_mode", - &format_args!("{}", self.spi_dout_mode().bit()), - ) - .field( - "spi_fastrd_mode", - &format_args!("{}", self.spi_fastrd_mode().bit()), - ) - .field( - "two_byte_status", - &format_args!("{}", self.two_byte_status().bit()), - ) - .field("wp_reg", &format_args!("{}", self.wp_reg().bit())) - .field("share_but", &format_args!("{}", self.share_but().bit())) - .field("hold_mode", &format_args!("{}", self.hold_mode().bit())) - .field("enable_ahb", &format_args!("{}", self.enable_ahb().bit())) - .field("sst_aai", &format_args!("{}", self.sst_aai().bit())) - .field("res_and_res", &format_args!("{}", self.res_and_res().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 13 - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] - #[inline(always)] - #[must_use] - pub fn spi_fastrd_mode(&mut self) -> SPI_FASTRD_MODE_W { - SPI_FASTRD_MODE_W::new(self, 13) - } - #[doc = "Bit 14 - In the read operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_dout_mode(&mut self) -> SPI_DOUT_MODE_W { - SPI_DOUT_MODE_W::new(self, 14) - } - #[doc = "Bit 15 - 'Res and res'?"] - #[inline(always)] - #[must_use] - pub fn res_and_res(&mut self) -> RES_AND_RES_W { - RES_AND_RES_W::new(self, 15) - } - #[doc = "Bit 16 - SST_AAI?"] - #[inline(always)] - #[must_use] - pub fn sst_aai(&mut self) -> SST_AAI_W { - SST_AAI_W::new(self, 16) - } - #[doc = "Bit 17 - Enable AHB"] - #[inline(always)] - #[must_use] - pub fn enable_ahb(&mut self) -> ENABLE_AHB_W { - ENABLE_AHB_W::new(self, 17) - } - #[doc = "Bit 18 - Hold mode"] - #[inline(always)] - #[must_use] - pub fn hold_mode(&mut self) -> HOLD_MODE_W { - HOLD_MODE_W::new(self, 18) - } - #[doc = "Bit 19 - Share bus"] - #[inline(always)] - #[must_use] - pub fn share_but(&mut self) -> SHARE_BUT_W { - SHARE_BUT_W::new(self, 19) - } - #[doc = "Bit 20 - In the read operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_qout_mode(&mut self) -> SPI_QOUT_MODE_W { - SPI_QOUT_MODE_W::new(self, 20) - } - #[doc = "Bit 21 - Write protect?"] - #[inline(always)] - #[must_use] - pub fn wp_reg(&mut self) -> WP_REG_W { - WP_REG_W::new(self, 21) - } - #[doc = "Bit 22 - Enable two byte status"] - #[inline(always)] - #[must_use] - pub fn two_byte_status(&mut self) -> TWO_BYTE_STATUS_W { - TWO_BYTE_STATUS_W::new(self, 22) - } - #[doc = "Bit 23 - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_dio_mode(&mut self) -> SPI_DIO_MODE_W { - SPI_DIO_MODE_W::new(self, 23) - } - #[doc = "Bit 24 - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_qio_mode(&mut self) -> SPI_QIO_MODE_W { - SPI_QIO_MODE_W::new(self, 24) - } - #[doc = "Bit 25 - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] - #[inline(always)] - #[must_use] - pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W { - SPI_RD_BIT_ORDER_W::new(self, 25) - } - #[doc = "Bit 26 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] - #[inline(always)] - #[must_use] - pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W { - SPI_WR_BIT_ORDER_W::new(self, 26) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SPI_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL_SPEC; -impl crate::RegisterSpec for SPI_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL to value 0"] -impl crate::Resettable for SPI_CTRL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ctrl1.rs b/esp8266/src/spi0/spi_ctrl1.rs deleted file mode 100644 index a910a57e9e..0000000000 --- a/esp8266/src/spi0/spi_ctrl1.rs +++ /dev/null @@ -1,95 +0,0 @@ -#[doc = "Register `SPI_CTRL1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL1` writer"] -pub type W = crate::W; -#[doc = "Field `status` reader - In the slave mode, it is the status for master to read out."] -pub type STATUS_R = crate::FieldReader; -#[doc = "Field `status` writer - In the slave mode, it is the status for master to read out."] -pub type STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `wb_mode` reader - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] -pub type WB_MODE_R = crate::FieldReader; -#[doc = "Field `wb_mode` writer - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] -pub type WB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `status_ext` reader - In the slave mode,it is the status for master to read out."] -pub type STATUS_EXT_R = crate::FieldReader; -#[doc = "Field `status_ext` writer - In the slave mode,it is the status for master to read out."] -pub type STATUS_EXT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."] - #[inline(always)] - pub fn status(&self) -> STATUS_R { - STATUS_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] - #[inline(always)] - pub fn wb_mode(&self) -> WB_MODE_R { - WB_MODE_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In the slave mode,it is the status for master to read out."] - #[inline(always)] - pub fn status_ext(&self) -> STATUS_EXT_R { - STATUS_EXT_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL1") - .field("status", &format_args!("{}", self.status().bits())) - .field("wb_mode", &format_args!("{}", self.wb_mode().bits())) - .field("status_ext", &format_args!("{}", self.status_ext().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."] - #[inline(always)] - #[must_use] - pub fn status(&mut self) -> STATUS_W { - STATUS_W::new(self, 0) - } - #[doc = "Bits 16:23 - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] - #[inline(always)] - #[must_use] - pub fn wb_mode(&mut self) -> WB_MODE_W { - WB_MODE_W::new(self, 16) - } - #[doc = "Bits 24:31 - In the slave mode,it is the status for master to read out."] - #[inline(always)] - #[must_use] - pub fn status_ext(&mut self) -> STATUS_EXT_W { - STATUS_EXT_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL1_SPEC; -impl crate::RegisterSpec for SPI_CTRL1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl1::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl1::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL1 to value 0"] -impl crate::Resettable for SPI_CTRL1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ctrl2.rs b/esp8266/src/spi0/spi_ctrl2.rs deleted file mode 100644 index de0f6e05cc..0000000000 --- a/esp8266/src/spi0/spi_ctrl2.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `SPI_CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL2` writer"] -pub type W = crate::W; -#[doc = "Field `spi_miso_delay_mode` reader - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MISO_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_miso_delay_mode` writer - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MISO_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_miso_delay_num` reader - MISO signals are delayed by 80MHz clock cycles"] -pub type SPI_MISO_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_miso_delay_num` writer - MISO signals are delayed by 80MHz clock cycles"] -pub type SPI_MISO_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `spi_mosi_delay_mode` reader - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MOSI_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_mosi_delay_mode` writer - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MOSI_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_mosi_delay_num` reader - MOSI signals are delayed by 80MHz clock cycles"] -pub type SPI_MOSI_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_mosi_delay_num` writer - MOSI signals are delayed by 80MHz clock cycles"] -pub type SPI_MOSI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `spi_cs_delay_mode` reader - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_CS_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_cs_delay_mode` writer - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_CS_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_cs_delay_num` reader - spi_cs signal is delayed by 80MHz clock cycles"] -pub type SPI_CS_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_cs_delay_num` writer - spi_cs signal is delayed by 80MHz clock cycles"] -pub type SPI_CS_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_miso_delay_mode(&self) -> SPI_MISO_DELAY_MODE_R { - SPI_MISO_DELAY_MODE_R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_miso_delay_num(&self) -> SPI_MISO_DELAY_NUM_R { - SPI_MISO_DELAY_NUM_R::new(((self.bits >> 18) & 7) as u8) - } - #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_mosi_delay_mode(&self) -> SPI_MOSI_DELAY_MODE_R { - SPI_MOSI_DELAY_MODE_R::new(((self.bits >> 21) & 3) as u8) - } - #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_mosi_delay_num(&self) -> SPI_MOSI_DELAY_NUM_R { - SPI_MOSI_DELAY_NUM_R::new(((self.bits >> 23) & 7) as u8) - } - #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_cs_delay_mode(&self) -> SPI_CS_DELAY_MODE_R { - SPI_CS_DELAY_MODE_R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_cs_delay_num(&self) -> SPI_CS_DELAY_NUM_R { - SPI_CS_DELAY_NUM_R::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL2") - .field( - "spi_cs_delay_num", - &format_args!("{}", self.spi_cs_delay_num().bits()), - ) - .field( - "spi_cs_delay_mode", - &format_args!("{}", self.spi_cs_delay_mode().bits()), - ) - .field( - "spi_mosi_delay_num", - &format_args!("{}", self.spi_mosi_delay_num().bits()), - ) - .field( - "spi_mosi_delay_mode", - &format_args!("{}", self.spi_mosi_delay_mode().bits()), - ) - .field( - "spi_miso_delay_num", - &format_args!("{}", self.spi_miso_delay_num().bits()), - ) - .field( - "spi_miso_delay_mode", - &format_args!("{}", self.spi_miso_delay_mode().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_miso_delay_mode(&mut self) -> SPI_MISO_DELAY_MODE_W { - SPI_MISO_DELAY_MODE_W::new(self, 16) - } - #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_miso_delay_num(&mut self) -> SPI_MISO_DELAY_NUM_W { - SPI_MISO_DELAY_NUM_W::new(self, 18) - } - #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_mosi_delay_mode(&mut self) -> SPI_MOSI_DELAY_MODE_W { - SPI_MOSI_DELAY_MODE_W::new(self, 21) - } - #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_mosi_delay_num(&mut self) -> SPI_MOSI_DELAY_NUM_W { - SPI_MOSI_DELAY_NUM_W::new(self, 23) - } - #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_cs_delay_mode(&mut self) -> SPI_CS_DELAY_MODE_W { - SPI_CS_DELAY_MODE_W::new(self, 26) - } - #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_cs_delay_num(&mut self) -> SPI_CS_DELAY_NUM_W { - SPI_CS_DELAY_NUM_W::new(self, 28) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "spi_cs signal is delayed by 80MHz clock cycles\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL2_SPEC; -impl crate::RegisterSpec for SPI_CTRL2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl2::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl2::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL2 to value 0"] -impl crate::Resettable for SPI_CTRL2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ext0.rs b/esp8266/src/spi0/spi_ext0.rs deleted file mode 100644 index ed47678fee..0000000000 --- a/esp8266/src/spi0/spi_ext0.rs +++ /dev/null @@ -1,95 +0,0 @@ -#[doc = "Register `SPI_EXT0` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT0` writer"] -pub type W = crate::W; -#[doc = "Field `pp_time` reader - "] -pub type PP_TIME_R = crate::FieldReader; -#[doc = "Field `pp_time` writer - "] -pub type PP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `pp_shift` reader - "] -pub type PP_SHIFT_R = crate::FieldReader; -#[doc = "Field `pp_shift` writer - "] -pub type PP_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `pp_enable` reader - "] -pub type PP_ENABLE_R = crate::BitReader; -#[doc = "Field `pp_enable` writer - "] -pub type PP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn pp_time(&self) -> PP_TIME_R { - PP_TIME_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:19"] - #[inline(always)] - pub fn pp_shift(&self) -> PP_SHIFT_R { - PP_SHIFT_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn pp_enable(&self) -> PP_ENABLE_R { - PP_ENABLE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT0") - .field("pp_enable", &format_args!("{}", self.pp_enable().bit())) - .field("pp_shift", &format_args!("{}", self.pp_shift().bits())) - .field("pp_time", &format_args!("{}", self.pp_time().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn pp_time(&mut self) -> PP_TIME_W { - PP_TIME_W::new(self, 0) - } - #[doc = "Bits 16:19"] - #[inline(always)] - #[must_use] - pub fn pp_shift(&mut self) -> PP_SHIFT_W { - PP_SHIFT_W::new(self, 16) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn pp_enable(&mut self) -> PP_ENABLE_W { - PP_ENABLE_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT0_SPEC; -impl crate::RegisterSpec for SPI_EXT0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext0::R`](R) reader structure"] -impl crate::Readable for SPI_EXT0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext0::W`](W) writer structure"] -impl crate::Writable for SPI_EXT0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT0 to value 0"] -impl crate::Resettable for SPI_EXT0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ext1.rs b/esp8266/src/spi0/spi_ext1.rs deleted file mode 100644 index 7016f9451a..0000000000 --- a/esp8266/src/spi0/spi_ext1.rs +++ /dev/null @@ -1,101 +0,0 @@ -#[doc = "Register `SPI_EXT1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT1` writer"] -pub type W = crate::W; -#[doc = "Field `erase_time` reader - "] -pub type ERASE_TIME_R = crate::FieldReader; -#[doc = "Field `erase_time` writer - "] -pub type ERASE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `erase_shift` reader - "] -pub type ERASE_SHIFT_R = crate::FieldReader; -#[doc = "Field `erase_shift` writer - "] -pub type ERASE_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `erase_enable` reader - "] -pub type ERASE_ENABLE_R = crate::BitReader; -#[doc = "Field `erase_enable` writer - "] -pub type ERASE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn erase_time(&self) -> ERASE_TIME_R { - ERASE_TIME_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:19"] - #[inline(always)] - pub fn erase_shift(&self) -> ERASE_SHIFT_R { - ERASE_SHIFT_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn erase_enable(&self) -> ERASE_ENABLE_R { - ERASE_ENABLE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT1") - .field( - "erase_enable", - &format_args!("{}", self.erase_enable().bit()), - ) - .field( - "erase_shift", - &format_args!("{}", self.erase_shift().bits()), - ) - .field("erase_time", &format_args!("{}", self.erase_time().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn erase_time(&mut self) -> ERASE_TIME_W { - ERASE_TIME_W::new(self, 0) - } - #[doc = "Bits 16:19"] - #[inline(always)] - #[must_use] - pub fn erase_shift(&mut self) -> ERASE_SHIFT_W { - ERASE_SHIFT_W::new(self, 16) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn erase_enable(&mut self) -> ERASE_ENABLE_W { - ERASE_ENABLE_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT1_SPEC; -impl crate::RegisterSpec for SPI_EXT1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext1::R`](R) reader structure"] -impl crate::Readable for SPI_EXT1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext1::W`](W) writer structure"] -impl crate::Writable for SPI_EXT1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT1 to value 0"] -impl crate::Resettable for SPI_EXT1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ext2.rs b/esp8266/src/spi0/spi_ext2.rs deleted file mode 100644 index c12c0070da..0000000000 --- a/esp8266/src/spi0/spi_ext2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_EXT2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT2` writer"] -pub type W = crate::W; -#[doc = "Field `st` reader - "] -pub type ST_R = crate::FieldReader; -#[doc = "Field `st` writer - "] -pub type ST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2"] - #[inline(always)] - pub fn st(&self) -> ST_R { - ST_R::new((self.bits & 7) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT2") - .field("st", &format_args!("{}", self.st().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:2"] - #[inline(always)] - #[must_use] - pub fn st(&mut self) -> ST_W { - ST_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT2_SPEC; -impl crate::RegisterSpec for SPI_EXT2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext2::R`](R) reader structure"] -impl crate::Readable for SPI_EXT2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext2::W`](W) writer structure"] -impl crate::Writable for SPI_EXT2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT2 to value 0"] -impl crate::Resettable for SPI_EXT2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_ext3.rs b/esp8266/src/spi0/spi_ext3.rs deleted file mode 100644 index bce9543c34..0000000000 --- a/esp8266/src/spi0/spi_ext3.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_EXT3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT3` writer"] -pub type W = crate::W; -#[doc = "Field `reg_int_hold_ena` reader - This register is for two SPI masters to share the same cs, clock and data signals."] -pub type REG_INT_HOLD_ENA_R = crate::FieldReader; -#[doc = "Field `reg_int_hold_ena` writer - This register is for two SPI masters to share the same cs, clock and data signals."] -pub type REG_INT_HOLD_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - pub fn reg_int_hold_ena(&self) -> REG_INT_HOLD_ENA_R { - REG_INT_HOLD_ENA_R::new((self.bits & 3) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT3") - .field( - "reg_int_hold_ena", - &format_args!("{}", self.reg_int_hold_ena().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - #[must_use] - pub fn reg_int_hold_ena(&mut self) -> REG_INT_HOLD_ENA_W { - REG_INT_HOLD_ENA_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "This register is for two SPI masters to share the same cs, clock and data signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT3_SPEC; -impl crate::RegisterSpec for SPI_EXT3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext3::R`](R) reader structure"] -impl crate::Readable for SPI_EXT3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext3::W`](W) writer structure"] -impl crate::Writable for SPI_EXT3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT3 to value 0"] -impl crate::Resettable for SPI_EXT3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_pin.rs b/esp8266/src/spi0/spi_pin.rs deleted file mode 100644 index e36a780898..0000000000 --- a/esp8266/src/spi0/spi_pin.rs +++ /dev/null @@ -1,114 +0,0 @@ -#[doc = "Register `SPI_PIN` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_PIN` writer"] -pub type W = crate::W; -#[doc = "Field `spi_cs0_dis` reader - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] -pub type SPI_CS0_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs0_dis` writer - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] -pub type SPI_CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs1_dis` reader - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] -pub type SPI_CS1_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs1_dis` writer - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] -pub type SPI_CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs2_dis` reader - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub type SPI_CS2_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs2_dis` writer - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub type SPI_CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_idle_edge` reader - In the master mode, 1: high when idle; 0: low when idle"] -pub type SPI_IDLE_EDGE_R = crate::BitReader; -#[doc = "Field `spi_idle_edge` writer - In the master mode, 1: high when idle; 0: low when idle"] -pub type SPI_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] - #[inline(always)] - pub fn spi_cs0_dis(&self) -> SPI_CS0_DIS_R { - SPI_CS0_DIS_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] - #[inline(always)] - pub fn spi_cs1_dis(&self) -> SPI_CS1_DIS_R { - SPI_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - pub fn spi_cs2_dis(&self) -> SPI_CS2_DIS_R { - SPI_CS2_DIS_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"] - #[inline(always)] - pub fn spi_idle_edge(&self) -> SPI_IDLE_EDGE_R { - SPI_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_PIN") - .field("spi_cs2_dis", &format_args!("{}", self.spi_cs2_dis().bit())) - .field("spi_cs1_dis", &format_args!("{}", self.spi_cs1_dis().bit())) - .field("spi_cs0_dis", &format_args!("{}", self.spi_cs0_dis().bit())) - .field( - "spi_idle_edge", - &format_args!("{}", self.spi_idle_edge().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W { - SPI_CS0_DIS_W::new(self, 0) - } - #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W { - SPI_CS1_DIS_W::new(self, 1) - } - #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W { - SPI_CS2_DIS_W::new(self, 2) - } - #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"] - #[inline(always)] - #[must_use] - pub fn spi_idle_edge(&mut self) -> SPI_IDLE_EDGE_W { - SPI_IDLE_EDGE_W::new(self, 29) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "1: disable CS2; 0: spi_cs signal is from/to CS2 pin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_pin::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_pin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_PIN_SPEC; -impl crate::RegisterSpec for SPI_PIN_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_pin::R`](R) reader structure"] -impl crate::Readable for SPI_PIN_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_pin::W`](W) writer structure"] -impl crate::Writable for SPI_PIN_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_PIN to value 0"] -impl crate::Resettable for SPI_PIN_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_rd_status.rs b/esp8266/src/spi0/spi_rd_status.rs deleted file mode 100644 index ad991c8e13..0000000000 --- a/esp8266/src/spi0/spi_rd_status.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_RD_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_RD_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rd_status` reader - In the slave mode, this register are the status register for the master to read out."] -pub type SLV_RD_STATUS_R = crate::FieldReader; -#[doc = "Field `slv_rd_status` writer - In the slave mode, this register are the status register for the master to read out."] -pub type SLV_RD_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - pub fn slv_rd_status(&self) -> SLV_RD_STATUS_R { - SLV_RD_STATUS_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_RD_STATUS") - .field( - "slv_rd_status", - &format_args!("{}", self.slv_rd_status().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - #[must_use] - pub fn slv_rd_status(&mut self) -> SLV_RD_STATUS_W { - SLV_RD_STATUS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, this register are the status register for the master to read out.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rd_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rd_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_RD_STATUS_SPEC; -impl crate::RegisterSpec for SPI_RD_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_rd_status::R`](R) reader structure"] -impl crate::Readable for SPI_RD_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_rd_status::W`](W) writer structure"] -impl crate::Writable for SPI_RD_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_RD_STATUS to value 0"] -impl crate::Resettable for SPI_RD_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_slave.rs b/esp8266/src/spi0/spi_slave.rs deleted file mode 100644 index 4a1763cb6a..0000000000 --- a/esp8266/src/spi0/spi_slave.rs +++ /dev/null @@ -1,356 +0,0 @@ -#[doc = "Register `SPI_SLAVE` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rd_buf_done` reader - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] -pub type SLV_RD_BUF_DONE_R = crate::BitReader; -#[doc = "Field `slv_rd_buf_done` writer - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] -pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_buf_done` reader - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] -pub type SLV_WR_BUF_DONE_R = crate::BitReader; -#[doc = "Field `slv_wr_buf_done` writer - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] -pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_rd_sta_done` reader - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] -pub type SLV_RD_STA_DONE_R = crate::BitReader; -#[doc = "Field `slv_rd_sta_done` writer - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] -pub type SLV_RD_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_sta_done` reader - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] -pub type SLV_WR_STA_DONE_R = crate::BitReader; -#[doc = "Field `slv_wr_sta_done` writer - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] -pub type SLV_WR_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_trans_done` reader - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] -pub type SPI_TRANS_DONE_R = crate::BitReader; -#[doc = "Field `spi_trans_done` writer - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] -pub type SPI_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_int_en` reader - Interrupt enable bits for the below 5 sources"] -pub type SPI_INT_EN_R = crate::FieldReader; -#[doc = "Field `spi_int_en` writer - Interrupt enable bits for the below 5 sources"] -pub type SPI_INT_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `interrupt_rb_enable` reader - Enable buffer read interrupts"] -pub type INTERRUPT_RB_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_rb_enable` writer - Enable buffer read interrupts"] -pub type INTERRUPT_RB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_wb_enable` reader - Enable buffer write interrupts"] -pub type INTERRUPT_WB_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_wb_enable` writer - Enable buffer write interrupts"] -pub type INTERRUPT_WB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_rs_enable` reader - Enable status read interrupts"] -pub type INTERRUPT_RS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_rs_enable` writer - Enable status read interrupts"] -pub type INTERRUPT_RS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_ws_enable` reader - Enable status write interrupts"] -pub type INTERRUPT_WS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_ws_enable` writer - Enable status write interrupts"] -pub type INTERRUPT_WS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_trans_enable` reader - Enable TRANS interrupts"] -pub type INTERRUPT_TRANS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_trans_enable` writer - Enable TRANS interrupts"] -pub type INTERRUPT_TRANS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_trans_cnt` reader - The operations counter in both the master mode and the slave mode."] -pub type SPI_TRANS_CNT_R = crate::FieldReader; -#[doc = "Field `slv_cmd_define` reader - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] -pub type SLV_CMD_DEFINE_R = crate::BitReader; -#[doc = "Field `slv_cmd_define` writer - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] -pub type SLV_CMD_DEFINE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sta_enable` reader - Enable read/write buffer"] -pub type STA_ENABLE_R = crate::BitReader; -#[doc = "Field `sta_enable` writer - Enable read/write buffer"] -pub type STA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_buffer_enable` reader - Enable read/write buffer"] -pub type SPI_BUFFER_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_buffer_enable` writer - Enable read/write buffer"] -pub type SPI_BUFFER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_slave_mode` reader - 1: slave mode, 0: master mode."] -pub type SPI_SLAVE_MODE_R = crate::BitReader; -#[doc = "Field `spi_slave_mode` writer - 1: slave mode, 0: master mode."] -pub type SPI_SLAVE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_sync_reset` reader - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub type SPI_SYNC_RESET_R = crate::BitReader; -#[doc = "Field `spi_sync_reset` writer - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub type SPI_SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] - #[inline(always)] - pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R { - SLV_RD_BUF_DONE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] - #[inline(always)] - pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R { - SLV_WR_BUF_DONE_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] - #[inline(always)] - pub fn slv_rd_sta_done(&self) -> SLV_RD_STA_DONE_R { - SLV_RD_STA_DONE_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] - #[inline(always)] - pub fn slv_wr_sta_done(&self) -> SLV_WR_STA_DONE_R { - SLV_WR_STA_DONE_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] - #[inline(always)] - pub fn spi_trans_done(&self) -> SPI_TRANS_DONE_R { - SPI_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 5:9 - Interrupt enable bits for the below 5 sources"] - #[inline(always)] - pub fn spi_int_en(&self) -> SPI_INT_EN_R { - SPI_INT_EN_R::new(((self.bits >> 5) & 0x1f) as u8) - } - #[doc = "Bit 5 - Enable buffer read interrupts"] - #[inline(always)] - pub fn interrupt_rb_enable(&self) -> INTERRUPT_RB_ENABLE_R { - INTERRUPT_RB_ENABLE_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Enable buffer write interrupts"] - #[inline(always)] - pub fn interrupt_wb_enable(&self) -> INTERRUPT_WB_ENABLE_R { - INTERRUPT_WB_ENABLE_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Enable status read interrupts"] - #[inline(always)] - pub fn interrupt_rs_enable(&self) -> INTERRUPT_RS_ENABLE_R { - INTERRUPT_RS_ENABLE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Enable status write interrupts"] - #[inline(always)] - pub fn interrupt_ws_enable(&self) -> INTERRUPT_WS_ENABLE_R { - INTERRUPT_WS_ENABLE_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Enable TRANS interrupts"] - #[inline(always)] - pub fn interrupt_trans_enable(&self) -> INTERRUPT_TRANS_ENABLE_R { - INTERRUPT_TRANS_ENABLE_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 23:26 - The operations counter in both the master mode and the slave mode."] - #[inline(always)] - pub fn spi_trans_cnt(&self) -> SPI_TRANS_CNT_R { - SPI_TRANS_CNT_R::new(((self.bits >> 23) & 0x0f) as u8) - } - #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] - #[inline(always)] - pub fn slv_cmd_define(&self) -> SLV_CMD_DEFINE_R { - SLV_CMD_DEFINE_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Enable read/write buffer"] - #[inline(always)] - pub fn sta_enable(&self) -> STA_ENABLE_R { - STA_ENABLE_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Enable read/write buffer"] - #[inline(always)] - pub fn spi_buffer_enable(&self) -> SPI_BUFFER_ENABLE_R { - SPI_BUFFER_ENABLE_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - 1: slave mode, 0: master mode."] - #[inline(always)] - pub fn spi_slave_mode(&self) -> SPI_SLAVE_MODE_R { - SPI_SLAVE_MODE_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - pub fn spi_sync_reset(&self) -> SPI_SYNC_RESET_R { - SPI_SYNC_RESET_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE") - .field( - "spi_sync_reset", - &format_args!("{}", self.spi_sync_reset().bit()), - ) - .field( - "spi_slave_mode", - &format_args!("{}", self.spi_slave_mode().bit()), - ) - .field( - "slv_cmd_define", - &format_args!("{}", self.slv_cmd_define().bit()), - ) - .field( - "spi_trans_cnt", - &format_args!("{}", self.spi_trans_cnt().bits()), - ) - .field("spi_int_en", &format_args!("{}", self.spi_int_en().bits())) - .field( - "spi_trans_done", - &format_args!("{}", self.spi_trans_done().bit()), - ) - .field( - "slv_wr_sta_done", - &format_args!("{}", self.slv_wr_sta_done().bit()), - ) - .field( - "slv_rd_sta_done", - &format_args!("{}", self.slv_rd_sta_done().bit()), - ) - .field( - "slv_wr_buf_done", - &format_args!("{}", self.slv_wr_buf_done().bit()), - ) - .field( - "slv_rd_buf_done", - &format_args!("{}", self.slv_rd_buf_done().bit()), - ) - .field( - "spi_buffer_enable", - &format_args!("{}", self.spi_buffer_enable().bit()), - ) - .field("sta_enable", &format_args!("{}", self.sta_enable().bit())) - .field( - "interrupt_trans_enable", - &format_args!("{}", self.interrupt_trans_enable().bit()), - ) - .field( - "interrupt_ws_enable", - &format_args!("{}", self.interrupt_ws_enable().bit()), - ) - .field( - "interrupt_rs_enable", - &format_args!("{}", self.interrupt_rs_enable().bit()), - ) - .field( - "interrupt_wb_enable", - &format_args!("{}", self.interrupt_wb_enable().bit()), - ) - .field( - "interrupt_rb_enable", - &format_args!("{}", self.interrupt_rb_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W { - SLV_RD_BUF_DONE_W::new(self, 0) - } - #[doc = "Bit 1 - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W { - SLV_WR_BUF_DONE_W::new(self, 1) - } - #[doc = "Bit 2 - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_rd_sta_done(&mut self) -> SLV_RD_STA_DONE_W { - SLV_RD_STA_DONE_W::new(self, 2) - } - #[doc = "Bit 3 - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_wr_sta_done(&mut self) -> SLV_WR_STA_DONE_W { - SLV_WR_STA_DONE_W::new(self, 3) - } - #[doc = "Bit 4 - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] - #[inline(always)] - #[must_use] - pub fn spi_trans_done(&mut self) -> SPI_TRANS_DONE_W { - SPI_TRANS_DONE_W::new(self, 4) - } - #[doc = "Bits 5:9 - Interrupt enable bits for the below 5 sources"] - #[inline(always)] - #[must_use] - pub fn spi_int_en(&mut self) -> SPI_INT_EN_W { - SPI_INT_EN_W::new(self, 5) - } - #[doc = "Bit 5 - Enable buffer read interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_rb_enable(&mut self) -> INTERRUPT_RB_ENABLE_W { - INTERRUPT_RB_ENABLE_W::new(self, 5) - } - #[doc = "Bit 6 - Enable buffer write interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_wb_enable(&mut self) -> INTERRUPT_WB_ENABLE_W { - INTERRUPT_WB_ENABLE_W::new(self, 6) - } - #[doc = "Bit 7 - Enable status read interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_rs_enable(&mut self) -> INTERRUPT_RS_ENABLE_W { - INTERRUPT_RS_ENABLE_W::new(self, 7) - } - #[doc = "Bit 8 - Enable status write interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_ws_enable(&mut self) -> INTERRUPT_WS_ENABLE_W { - INTERRUPT_WS_ENABLE_W::new(self, 8) - } - #[doc = "Bit 9 - Enable TRANS interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_trans_enable(&mut self) -> INTERRUPT_TRANS_ENABLE_W { - INTERRUPT_TRANS_ENABLE_W::new(self, 9) - } - #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] - #[inline(always)] - #[must_use] - pub fn slv_cmd_define(&mut self) -> SLV_CMD_DEFINE_W { - SLV_CMD_DEFINE_W::new(self, 27) - } - #[doc = "Bit 28 - Enable read/write buffer"] - #[inline(always)] - #[must_use] - pub fn sta_enable(&mut self) -> STA_ENABLE_W { - STA_ENABLE_W::new(self, 28) - } - #[doc = "Bit 29 - Enable read/write buffer"] - #[inline(always)] - #[must_use] - pub fn spi_buffer_enable(&mut self) -> SPI_BUFFER_ENABLE_W { - SPI_BUFFER_ENABLE_W::new(self, 29) - } - #[doc = "Bit 30 - 1: slave mode, 0: master mode."] - #[inline(always)] - #[must_use] - pub fn spi_slave_mode(&mut self) -> SPI_SLAVE_MODE_W { - SPI_SLAVE_MODE_W::new(self, 30) - } - #[doc = "Bit 31 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - #[must_use] - pub fn spi_sync_reset(&mut self) -> SPI_SYNC_RESET_W { - SPI_SYNC_RESET_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "It is the synchronous reset signal of the module. This bit is self-cleared by hardware.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE_SPEC; -impl crate::RegisterSpec for SPI_SLAVE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE to value 0"] -impl crate::Resettable for SPI_SLAVE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_slave1.rs b/esp8266/src/spi0/spi_slave1.rs deleted file mode 100644 index cd774580b3..0000000000 --- a/esp8266/src/spi0/spi_slave1.rs +++ /dev/null @@ -1,237 +0,0 @@ -#[doc = "Register `SPI_SLAVE1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE1` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdbuf_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] -pub type SLV_RDBUF_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_rdbuf_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] -pub type SLV_RDBUF_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wrbuf_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] -pub type SLV_WRBUF_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_wrbuf_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] -pub type SLV_WRBUF_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_rdsta_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] -pub type SLV_RDSTA_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_rdsta_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] -pub type SLV_RDSTA_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wrsta_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] -pub type SLV_WRSTA_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_wrsta_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] -pub type SLV_WRSTA_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_addr_bitlen` reader - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_WR_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_wr_addr_bitlen` writer - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_WR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `slv_rd_addr_bitlen` reader - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_RD_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_rd_addr_bitlen` writer - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_RD_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `slv_buf_bitlen` reader - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] -pub type SLV_BUF_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_buf_bitlen` writer - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] -pub type SLV_BUF_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `spi_status_read` reader - Enable spi slave status"] -pub type SPI_STATUS_READ_R = crate::BitReader; -#[doc = "Field `spi_status_read` writer - Enable spi slave status"] -pub type SPI_STATUS_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_status_fast_enable` reader - Enable fast spi slave status"] -pub type SPI_STATUS_FAST_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_status_fast_enable` writer - Enable fast spi slave status"] -pub type SPI_STATUS_FAST_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_status_bitlen` reader - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub type SLV_STATUS_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_status_bitlen` writer - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub type SLV_STATUS_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bit 0 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] - #[inline(always)] - pub fn slv_rdbuf_dummy_en(&self) -> SLV_RDBUF_DUMMY_EN_R { - SLV_RDBUF_DUMMY_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] - #[inline(always)] - pub fn slv_wrbuf_dummy_en(&self) -> SLV_WRBUF_DUMMY_EN_R { - SLV_WRBUF_DUMMY_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] - #[inline(always)] - pub fn slv_rdsta_dummy_en(&self) -> SLV_RDSTA_DUMMY_EN_R { - SLV_RDSTA_DUMMY_EN_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] - #[inline(always)] - pub fn slv_wrsta_dummy_en(&self) -> SLV_WRSTA_DUMMY_EN_R { - SLV_WRSTA_DUMMY_EN_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:9 - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - pub fn slv_wr_addr_bitlen(&self) -> SLV_WR_ADDR_BITLEN_R { - SLV_WR_ADDR_BITLEN_R::new(((self.bits >> 4) & 0x3f) as u8) - } - #[doc = "Bits 10:15 - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - pub fn slv_rd_addr_bitlen(&self) -> SLV_RD_ADDR_BITLEN_R { - SLV_RD_ADDR_BITLEN_R::new(((self.bits >> 10) & 0x3f) as u8) - } - #[doc = "Bits 16:24 - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] - #[inline(always)] - pub fn slv_buf_bitlen(&self) -> SLV_BUF_BITLEN_R { - SLV_BUF_BITLEN_R::new(((self.bits >> 16) & 0x01ff) as u16) - } - #[doc = "Bit 25 - Enable spi slave status"] - #[inline(always)] - pub fn spi_status_read(&self) -> SPI_STATUS_READ_R { - SPI_STATUS_READ_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Enable fast spi slave status"] - #[inline(always)] - pub fn spi_status_fast_enable(&self) -> SPI_STATUS_FAST_ENABLE_R { - SPI_STATUS_FAST_ENABLE_R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bits 27:31 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - pub fn slv_status_bitlen(&self) -> SLV_STATUS_BITLEN_R { - SLV_STATUS_BITLEN_R::new(((self.bits >> 27) & 0x1f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE1") - .field( - "slv_status_bitlen", - &format_args!("{}", self.slv_status_bitlen().bits()), - ) - .field( - "slv_buf_bitlen", - &format_args!("{}", self.slv_buf_bitlen().bits()), - ) - .field( - "slv_rd_addr_bitlen", - &format_args!("{}", self.slv_rd_addr_bitlen().bits()), - ) - .field( - "slv_wr_addr_bitlen", - &format_args!("{}", self.slv_wr_addr_bitlen().bits()), - ) - .field( - "slv_wrsta_dummy_en", - &format_args!("{}", self.slv_wrsta_dummy_en().bit()), - ) - .field( - "slv_rdsta_dummy_en", - &format_args!("{}", self.slv_rdsta_dummy_en().bit()), - ) - .field( - "slv_wrbuf_dummy_en", - &format_args!("{}", self.slv_wrbuf_dummy_en().bit()), - ) - .field( - "slv_rdbuf_dummy_en", - &format_args!("{}", self.slv_rdbuf_dummy_en().bit()), - ) - .field( - "spi_status_fast_enable", - &format_args!("{}", self.spi_status_fast_enable().bit()), - ) - .field( - "spi_status_read", - &format_args!("{}", self.spi_status_read().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_dummy_en(&mut self) -> SLV_RDBUF_DUMMY_EN_W { - SLV_RDBUF_DUMMY_EN_W::new(self, 0) - } - #[doc = "Bit 1 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_dummy_en(&mut self) -> SLV_WRBUF_DUMMY_EN_W { - SLV_WRBUF_DUMMY_EN_W::new(self, 1) - } - #[doc = "Bit 2 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_dummy_en(&mut self) -> SLV_RDSTA_DUMMY_EN_W { - SLV_RDSTA_DUMMY_EN_W::new(self, 2) - } - #[doc = "Bit 3 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_dummy_en(&mut self) -> SLV_WRSTA_DUMMY_EN_W { - SLV_WRSTA_DUMMY_EN_W::new(self, 3) - } - #[doc = "Bits 4:9 - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wr_addr_bitlen(&mut self) -> SLV_WR_ADDR_BITLEN_W { - SLV_WR_ADDR_BITLEN_W::new(self, 4) - } - #[doc = "Bits 10:15 - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rd_addr_bitlen(&mut self) -> SLV_RD_ADDR_BITLEN_W { - SLV_RD_ADDR_BITLEN_W::new(self, 10) - } - #[doc = "Bits 16:24 - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_buf_bitlen(&mut self) -> SLV_BUF_BITLEN_W { - SLV_BUF_BITLEN_W::new(self, 16) - } - #[doc = "Bit 25 - Enable spi slave status"] - #[inline(always)] - #[must_use] - pub fn spi_status_read(&mut self) -> SPI_STATUS_READ_W { - SPI_STATUS_READ_W::new(self, 25) - } - #[doc = "Bit 26 - Enable fast spi slave status"] - #[inline(always)] - #[must_use] - pub fn spi_status_fast_enable(&mut self) -> SPI_STATUS_FAST_ENABLE_W { - SPI_STATUS_FAST_ENABLE_W::new(self, 26) - } - #[doc = "Bits 27:31 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_status_bitlen(&mut self) -> SLV_STATUS_BITLEN_W { - SLV_STATUS_BITLEN_W::new(self, 27) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE1_SPEC; -impl crate::RegisterSpec for SPI_SLAVE1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave1::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave1::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE1 to value 0"] -impl crate::Resettable for SPI_SLAVE1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_slave2.rs b/esp8266/src/spi0/spi_slave2.rs deleted file mode 100644 index d93a81e4e1..0000000000 --- a/esp8266/src/spi0/spi_slave2.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_SLAVE2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE2` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdsta_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_RDSTA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_rdsta_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_RDSTA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrsta_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_WRSTA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_wrsta_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_WRSTA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_rdbuf_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_RDBUF_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_rdbuf_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_RDBUF_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrbuf_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_WRBUF_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_wrbuf_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_WRBUF_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_rdsta_dummy_cyclelen(&self) -> SLV_RDSTA_DUMMY_CYCLELEN_R { - SLV_RDSTA_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_wrsta_dummy_cyclelen(&self) -> SLV_WRSTA_DUMMY_CYCLELEN_R { - SLV_WRSTA_DUMMY_CYCLELEN_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_rdbuf_dummy_cyclelen(&self) -> SLV_RDBUF_DUMMY_CYCLELEN_R { - SLV_RDBUF_DUMMY_CYCLELEN_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_wrbuf_dummy_cyclelen(&self) -> SLV_WRBUF_DUMMY_CYCLELEN_R { - SLV_WRBUF_DUMMY_CYCLELEN_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE2") - .field( - "slv_wrbuf_dummy_cyclelen", - &format_args!("{}", self.slv_wrbuf_dummy_cyclelen().bits()), - ) - .field( - "slv_rdbuf_dummy_cyclelen", - &format_args!("{}", self.slv_rdbuf_dummy_cyclelen().bits()), - ) - .field( - "slv_wrsta_dummy_cyclelen", - &format_args!("{}", self.slv_wrsta_dummy_cyclelen().bits()), - ) - .field( - "slv_rdsta_dummy_cyclelen", - &format_args!("{}", self.slv_rdsta_dummy_cyclelen().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_dummy_cyclelen(&mut self) -> SLV_RDSTA_DUMMY_CYCLELEN_W { - SLV_RDSTA_DUMMY_CYCLELEN_W::new(self, 0) - } - #[doc = "Bits 8:15 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_dummy_cyclelen(&mut self) -> SLV_WRSTA_DUMMY_CYCLELEN_W { - SLV_WRSTA_DUMMY_CYCLELEN_W::new(self, 8) - } - #[doc = "Bits 16:23 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_dummy_cyclelen(&mut self) -> SLV_RDBUF_DUMMY_CYCLELEN_W { - SLV_RDBUF_DUMMY_CYCLELEN_W::new(self, 16) - } - #[doc = "Bits 24:31 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_dummy_cyclelen(&mut self) -> SLV_WRBUF_DUMMY_CYCLELEN_W { - SLV_WRBUF_DUMMY_CYCLELEN_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE2_SPEC; -impl crate::RegisterSpec for SPI_SLAVE2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave2::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave2::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE2 to value 0"] -impl crate::Resettable for SPI_SLAVE2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_slave3.rs b/esp8266/src/spi0/spi_slave3.rs deleted file mode 100644 index 5d4df59f0e..0000000000 --- a/esp8266/src/spi0/spi_slave3.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_SLAVE3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE3` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdbuf_cmd_value` reader - In slave mode, it is the value of \"read-buffer\" command"] -pub type SLV_RDBUF_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_rdbuf_cmd_value` writer - In slave mode, it is the value of \"read-buffer\" command"] -pub type SLV_RDBUF_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrbuf_cmd_value` reader - In slave mode, it is the value of \"write-buffer\" command"] -pub type SLV_WRBUF_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_wrbuf_cmd_value` writer - In slave mode, it is the value of \"write-buffer\" command"] -pub type SLV_WRBUF_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_rdsta_cmd_value` reader - In slave mode, it is the value of \"read-status\" command"] -pub type SLV_RDSTA_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_rdsta_cmd_value` writer - In slave mode, it is the value of \"read-status\" command"] -pub type SLV_RDSTA_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrsta_cmd_value` reader - In slave mode, it is the value of \"write-status\" command"] -pub type SLV_WRSTA_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_wrsta_cmd_value` writer - In slave mode, it is the value of \"write-status\" command"] -pub type SLV_WRSTA_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - In slave mode, it is the value of \"read-buffer\" command"] - #[inline(always)] - pub fn slv_rdbuf_cmd_value(&self) -> SLV_RDBUF_CMD_VALUE_R { - SLV_RDBUF_CMD_VALUE_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - In slave mode, it is the value of \"write-buffer\" command"] - #[inline(always)] - pub fn slv_wrbuf_cmd_value(&self) -> SLV_WRBUF_CMD_VALUE_R { - SLV_WRBUF_CMD_VALUE_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - In slave mode, it is the value of \"read-status\" command"] - #[inline(always)] - pub fn slv_rdsta_cmd_value(&self) -> SLV_RDSTA_CMD_VALUE_R { - SLV_RDSTA_CMD_VALUE_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - pub fn slv_wrsta_cmd_value(&self) -> SLV_WRSTA_CMD_VALUE_R { - SLV_WRSTA_CMD_VALUE_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE3") - .field( - "slv_wrsta_cmd_value", - &format_args!("{}", self.slv_wrsta_cmd_value().bits()), - ) - .field( - "slv_rdsta_cmd_value", - &format_args!("{}", self.slv_rdsta_cmd_value().bits()), - ) - .field( - "slv_wrbuf_cmd_value", - &format_args!("{}", self.slv_wrbuf_cmd_value().bits()), - ) - .field( - "slv_rdbuf_cmd_value", - &format_args!("{}", self.slv_rdbuf_cmd_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - In slave mode, it is the value of \"read-buffer\" command"] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_cmd_value(&mut self) -> SLV_RDBUF_CMD_VALUE_W { - SLV_RDBUF_CMD_VALUE_W::new(self, 0) - } - #[doc = "Bits 8:15 - In slave mode, it is the value of \"write-buffer\" command"] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_cmd_value(&mut self) -> SLV_WRBUF_CMD_VALUE_W { - SLV_WRBUF_CMD_VALUE_W::new(self, 8) - } - #[doc = "Bits 16:23 - In slave mode, it is the value of \"read-status\" command"] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_cmd_value(&mut self) -> SLV_RDSTA_CMD_VALUE_W { - SLV_RDSTA_CMD_VALUE_W::new(self, 16) - } - #[doc = "Bits 24:31 - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_cmd_value(&mut self) -> SLV_WRSTA_CMD_VALUE_W { - SLV_WRSTA_CMD_VALUE_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In slave mode, it is the value of \"write-status\" command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE3_SPEC; -impl crate::RegisterSpec for SPI_SLAVE3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave3::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave3::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE3 to value 0"] -impl crate::Resettable for SPI_SLAVE3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_user.rs b/esp8266/src/spi0/spi_user.rs deleted file mode 100644 index 716c499919..0000000000 --- a/esp8266/src/spi0/spi_user.rs +++ /dev/null @@ -1,456 +0,0 @@ -#[doc = "Register `SPI_USER` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER` writer"] -pub type W = crate::W; -#[doc = "Field `spi_duplex` reader - set spi in full duplex mode"] -pub type SPI_DUPLEX_R = crate::BitReader; -#[doc = "Field `spi_duplex` writer - set spi in full duplex mode"] -pub type SPI_DUPLEX_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ahb_user_command_4byte` reader - reserved"] -pub type SPI_AHB_USER_COMMAND_4BYTE_R = crate::BitReader; -#[doc = "Field `spi_ahb_user_command_4byte` writer - reserved"] -pub type SPI_AHB_USER_COMMAND_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_flash_mode` reader - "] -pub type SPI_FLASH_MODE_R = crate::BitReader; -#[doc = "Field `spi_flash_mode` writer - "] -pub type SPI_FLASH_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ahb_user_command` reader - reserved"] -pub type SPI_AHB_USER_COMMAND_R = crate::BitReader; -#[doc = "Field `spi_ahb_user_command` writer - reserved"] -pub type SPI_AHB_USER_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs_hold` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable."] -pub type SPI_CS_HOLD_R = crate::BitReader; -#[doc = "Field `spi_cs_hold` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable."] -pub type SPI_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs_setup` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] -pub type SPI_CS_SETUP_R = crate::BitReader; -#[doc = "Field `spi_cs_setup` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] -pub type SPI_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ck_i_edge` reader - In the slave mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_I_EDGE_R = crate::BitReader; -#[doc = "Field `spi_ck_i_edge` writer - In the slave mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ck_o_edge` reader - In the master mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_O_EDGE_R = crate::BitReader; -#[doc = "Field `spi_ck_o_edge` writer - In the master mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_O_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_rd_byte_order` reader - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] -pub type SPI_RD_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `spi_rd_byte_order` writer - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] -pub type SPI_RD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_wr_byte_order` reader - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] -pub type SPI_WR_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `spi_wr_byte_order` writer - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] -pub type SPI_WR_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_dual` reader - In the write operations, \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DUAL_R = crate::BitReader; -#[doc = "Field `spi_fwrite_dual` writer - In the write operations, \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_quad` reader - In the write operations, \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QUAD_R = crate::BitReader; -#[doc = "Field `spi_fwrite_quad` writer - In the write operations, \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_dio` reader - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DIO_R = crate::BitReader; -#[doc = "Field `spi_fwrite_dio` writer - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_qio` reader - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QIO_R = crate::BitReader; -#[doc = "Field `spi_fwrite_qio` writer - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_sio` reader - 1: mosi and miso signals share the same pin"] -pub type SPI_SIO_R = crate::BitReader; -#[doc = "Field `spi_sio` writer - 1: mosi and miso signals share the same pin"] -pub type SPI_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `reg_usr_miso_highpart` reader - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MISO_HIGHPART_R = crate::BitReader; -#[doc = "Field `reg_usr_miso_highpart` writer - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `reg_usr_mosi_highpart` reader - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MOSI_HIGHPART_R = crate::BitReader; -#[doc = "Field `reg_usr_mosi_highpart` writer - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_mosi` reader - This bit enable the \"write-data\" phase of an operation."] -pub type SPI_USR_MOSI_R = crate::BitReader; -#[doc = "Field `spi_usr_mosi` writer - This bit enable the \"write-data\" phase of an operation."] -pub type SPI_USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_miso` reader - This bit enable the \"read-data\" phase of an operation."] -pub type SPI_USR_MISO_R = crate::BitReader; -#[doc = "Field `spi_usr_miso` writer - This bit enable the \"read-data\" phase of an operation."] -pub type SPI_USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_dummy` reader - This bit enable the \"dummy\" phase of an operation."] -pub type SPI_USR_DUMMY_R = crate::BitReader; -#[doc = "Field `spi_usr_dummy` writer - This bit enable the \"dummy\" phase of an operation."] -pub type SPI_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_addr` reader - This bit enable the \"address\" phase of an operation."] -pub type SPI_USR_ADDR_R = crate::BitReader; -#[doc = "Field `spi_usr_addr` writer - This bit enable the \"address\" phase of an operation."] -pub type SPI_USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_command` reader - This bit enable the \"command\" phase of an operation."] -pub type SPI_USR_COMMAND_R = crate::BitReader; -#[doc = "Field `spi_usr_command` writer - This bit enable the \"command\" phase of an operation."] -pub type SPI_USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - set spi in full duplex mode"] - #[inline(always)] - pub fn spi_duplex(&self) -> SPI_DUPLEX_R { - SPI_DUPLEX_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - reserved"] - #[inline(always)] - pub fn spi_ahb_user_command_4byte(&self) -> SPI_AHB_USER_COMMAND_4BYTE_R { - SPI_AHB_USER_COMMAND_4BYTE_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn spi_flash_mode(&self) -> SPI_FLASH_MODE_R { - SPI_FLASH_MODE_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - reserved"] - #[inline(always)] - pub fn spi_ahb_user_command(&self) -> SPI_AHB_USER_COMMAND_R { - SPI_AHB_USER_COMMAND_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] - #[inline(always)] - pub fn spi_cs_hold(&self) -> SPI_CS_HOLD_R { - SPI_CS_HOLD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] - #[inline(always)] - pub fn spi_cs_setup(&self) -> SPI_CS_SETUP_R { - SPI_CS_SETUP_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - In the slave mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - pub fn spi_ck_i_edge(&self) -> SPI_CK_I_EDGE_R { - SPI_CK_I_EDGE_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - In the master mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - pub fn spi_ck_o_edge(&self) -> SPI_CK_O_EDGE_R { - SPI_CK_O_EDGE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 10 - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] - #[inline(always)] - pub fn spi_rd_byte_order(&self) -> SPI_RD_BYTE_ORDER_R { - SPI_RD_BYTE_ORDER_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] - #[inline(always)] - pub fn spi_wr_byte_order(&self) -> SPI_WR_BYTE_ORDER_R { - SPI_WR_BYTE_ORDER_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - In the write operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_fwrite_dual(&self) -> SPI_FWRITE_DUAL_R { - SPI_FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - In the write operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_fwrite_quad(&self) -> SPI_FWRITE_QUAD_R { - SPI_FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_fwrite_dio(&self) -> SPI_FWRITE_DIO_R { - SPI_FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_fwrite_qio(&self) -> SPI_FWRITE_QIO_R { - SPI_FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - 1: mosi and miso signals share the same pin"] - #[inline(always)] - pub fn spi_sio(&self) -> SPI_SIO_R { - SPI_SIO_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 24 - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - pub fn reg_usr_miso_highpart(&self) -> REG_USR_MISO_HIGHPART_R { - REG_USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - pub fn reg_usr_mosi_highpart(&self) -> REG_USR_MOSI_HIGHPART_R { - REG_USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 27 - This bit enable the \"write-data\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_mosi(&self) -> SPI_USR_MOSI_R { - SPI_USR_MOSI_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - This bit enable the \"read-data\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_miso(&self) -> SPI_USR_MISO_R { - SPI_USR_MISO_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - This bit enable the \"dummy\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_dummy(&self) -> SPI_USR_DUMMY_R { - SPI_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - This bit enable the \"address\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_addr(&self) -> SPI_USR_ADDR_R { - SPI_USR_ADDR_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_command(&self) -> SPI_USR_COMMAND_R { - SPI_USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER") - .field( - "spi_usr_command", - &format_args!("{}", self.spi_usr_command().bit()), - ) - .field( - "spi_usr_addr", - &format_args!("{}", self.spi_usr_addr().bit()), - ) - .field( - "spi_usr_dummy", - &format_args!("{}", self.spi_usr_dummy().bit()), - ) - .field( - "spi_usr_miso", - &format_args!("{}", self.spi_usr_miso().bit()), - ) - .field( - "spi_usr_mosi", - &format_args!("{}", self.spi_usr_mosi().bit()), - ) - .field( - "reg_usr_mosi_highpart", - &format_args!("{}", self.reg_usr_mosi_highpart().bit()), - ) - .field( - "reg_usr_miso_highpart", - &format_args!("{}", self.reg_usr_miso_highpart().bit()), - ) - .field("spi_sio", &format_args!("{}", self.spi_sio().bit())) - .field( - "spi_fwrite_qio", - &format_args!("{}", self.spi_fwrite_qio().bit()), - ) - .field( - "spi_fwrite_dio", - &format_args!("{}", self.spi_fwrite_dio().bit()), - ) - .field( - "spi_fwrite_quad", - &format_args!("{}", self.spi_fwrite_quad().bit()), - ) - .field( - "spi_fwrite_dual", - &format_args!("{}", self.spi_fwrite_dual().bit()), - ) - .field( - "spi_wr_byte_order", - &format_args!("{}", self.spi_wr_byte_order().bit()), - ) - .field( - "spi_rd_byte_order", - &format_args!("{}", self.spi_rd_byte_order().bit()), - ) - .field( - "spi_ck_i_edge", - &format_args!("{}", self.spi_ck_i_edge().bit()), - ) - .field( - "spi_ck_o_edge", - &format_args!("{}", self.spi_ck_o_edge().bit()), - ) - .field( - "spi_cs_setup", - &format_args!("{}", self.spi_cs_setup().bit()), - ) - .field("spi_cs_hold", &format_args!("{}", self.spi_cs_hold().bit())) - .field( - "spi_ahb_user_command", - &format_args!("{}", self.spi_ahb_user_command().bit()), - ) - .field( - "spi_flash_mode", - &format_args!("{}", self.spi_flash_mode().bit()), - ) - .field( - "spi_ahb_user_command_4byte", - &format_args!("{}", self.spi_ahb_user_command_4byte().bit()), - ) - .field("spi_duplex", &format_args!("{}", self.spi_duplex().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - set spi in full duplex mode"] - #[inline(always)] - #[must_use] - pub fn spi_duplex(&mut self) -> SPI_DUPLEX_W { - SPI_DUPLEX_W::new(self, 0) - } - #[doc = "Bit 1 - reserved"] - #[inline(always)] - #[must_use] - pub fn spi_ahb_user_command_4byte(&mut self) -> SPI_AHB_USER_COMMAND_4BYTE_W { - SPI_AHB_USER_COMMAND_4BYTE_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn spi_flash_mode(&mut self) -> SPI_FLASH_MODE_W { - SPI_FLASH_MODE_W::new(self, 2) - } - #[doc = "Bit 3 - reserved"] - #[inline(always)] - #[must_use] - pub fn spi_ahb_user_command(&mut self) -> SPI_AHB_USER_COMMAND_W { - SPI_AHB_USER_COMMAND_W::new(self, 3) - } - #[doc = "Bit 4 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] - #[inline(always)] - #[must_use] - pub fn spi_cs_hold(&mut self) -> SPI_CS_HOLD_W { - SPI_CS_HOLD_W::new(self, 4) - } - #[doc = "Bit 5 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] - #[inline(always)] - #[must_use] - pub fn spi_cs_setup(&mut self) -> SPI_CS_SETUP_W { - SPI_CS_SETUP_W::new(self, 5) - } - #[doc = "Bit 6 - In the slave mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - #[must_use] - pub fn spi_ck_i_edge(&mut self) -> SPI_CK_I_EDGE_W { - SPI_CK_I_EDGE_W::new(self, 6) - } - #[doc = "Bit 7 - In the master mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - #[must_use] - pub fn spi_ck_o_edge(&mut self) -> SPI_CK_O_EDGE_W { - SPI_CK_O_EDGE_W::new(self, 7) - } - #[doc = "Bit 10 - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] - #[inline(always)] - #[must_use] - pub fn spi_rd_byte_order(&mut self) -> SPI_RD_BYTE_ORDER_W { - SPI_RD_BYTE_ORDER_W::new(self, 10) - } - #[doc = "Bit 11 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] - #[inline(always)] - #[must_use] - pub fn spi_wr_byte_order(&mut self) -> SPI_WR_BYTE_ORDER_W { - SPI_WR_BYTE_ORDER_W::new(self, 11) - } - #[doc = "Bit 12 - In the write operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_dual(&mut self) -> SPI_FWRITE_DUAL_W { - SPI_FWRITE_DUAL_W::new(self, 12) - } - #[doc = "Bit 13 - In the write operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_quad(&mut self) -> SPI_FWRITE_QUAD_W { - SPI_FWRITE_QUAD_W::new(self, 13) - } - #[doc = "Bit 14 - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_dio(&mut self) -> SPI_FWRITE_DIO_W { - SPI_FWRITE_DIO_W::new(self, 14) - } - #[doc = "Bit 15 - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_qio(&mut self) -> SPI_FWRITE_QIO_W { - SPI_FWRITE_QIO_W::new(self, 15) - } - #[doc = "Bit 16 - 1: mosi and miso signals share the same pin"] - #[inline(always)] - #[must_use] - pub fn spi_sio(&mut self) -> SPI_SIO_W { - SPI_SIO_W::new(self, 16) - } - #[doc = "Bit 24 - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - #[must_use] - pub fn reg_usr_miso_highpart(&mut self) -> REG_USR_MISO_HIGHPART_W { - REG_USR_MISO_HIGHPART_W::new(self, 24) - } - #[doc = "Bit 25 - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - #[must_use] - pub fn reg_usr_mosi_highpart(&mut self) -> REG_USR_MOSI_HIGHPART_W { - REG_USR_MOSI_HIGHPART_W::new(self, 25) - } - #[doc = "Bit 27 - This bit enable the \"write-data\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_mosi(&mut self) -> SPI_USR_MOSI_W { - SPI_USR_MOSI_W::new(self, 27) - } - #[doc = "Bit 28 - This bit enable the \"read-data\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_miso(&mut self) -> SPI_USR_MISO_W { - SPI_USR_MISO_W::new(self, 28) - } - #[doc = "Bit 29 - This bit enable the \"dummy\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_dummy(&mut self) -> SPI_USR_DUMMY_W { - SPI_USR_DUMMY_W::new(self, 29) - } - #[doc = "Bit 30 - This bit enable the \"address\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_addr(&mut self) -> SPI_USR_ADDR_W { - SPI_USR_ADDR_W::new(self, 30) - } - #[doc = "Bit 31 - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_command(&mut self) -> SPI_USR_COMMAND_W { - SPI_USR_COMMAND_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "This bit enable the \"command\" phase of an operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER_SPEC; -impl crate::RegisterSpec for SPI_USER_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user::R`](R) reader structure"] -impl crate::Readable for SPI_USER_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user::W`](W) writer structure"] -impl crate::Writable for SPI_USER_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER to value 0"] -impl crate::Resettable for SPI_USER_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_user1.rs b/esp8266/src/spi0/spi_user1.rs deleted file mode 100644 index d552093174..0000000000 --- a/esp8266/src/spi0/spi_user1.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_USER1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER1` writer"] -pub type W = crate::W; -#[doc = "Field `reg_usr_dummy_cyclelen` reader - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] -pub type REG_USR_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_dummy_cyclelen` writer - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] -pub type REG_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `reg_usr_miso_bitlen` reader - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MISO_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_miso_bitlen` writer - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MISO_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `reg_usr_mosi_bitlen` reader - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MOSI_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_mosi_bitlen` writer - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MOSI_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `reg_usr_addr_bitlen` reader - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_addr_bitlen` writer - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:7 - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] - #[inline(always)] - pub fn reg_usr_dummy_cyclelen(&self) -> REG_USR_DUMMY_CYCLELEN_R { - REG_USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:16 - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_miso_bitlen(&self) -> REG_USR_MISO_BITLEN_R { - REG_USR_MISO_BITLEN_R::new(((self.bits >> 8) & 0x01ff) as u16) - } - #[doc = "Bits 17:25 - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_mosi_bitlen(&self) -> REG_USR_MOSI_BITLEN_R { - REG_USR_MOSI_BITLEN_R::new(((self.bits >> 17) & 0x01ff) as u16) - } - #[doc = "Bits 26:31 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_addr_bitlen(&self) -> REG_USR_ADDR_BITLEN_R { - REG_USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER1") - .field( - "reg_usr_addr_bitlen", - &format_args!("{}", self.reg_usr_addr_bitlen().bits()), - ) - .field( - "reg_usr_mosi_bitlen", - &format_args!("{}", self.reg_usr_mosi_bitlen().bits()), - ) - .field( - "reg_usr_miso_bitlen", - &format_args!("{}", self.reg_usr_miso_bitlen().bits()), - ) - .field( - "reg_usr_dummy_cyclelen", - &format_args!("{}", self.reg_usr_dummy_cyclelen().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_dummy_cyclelen(&mut self) -> REG_USR_DUMMY_CYCLELEN_W { - REG_USR_DUMMY_CYCLELEN_W::new(self, 0) - } - #[doc = "Bits 8:16 - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_miso_bitlen(&mut self) -> REG_USR_MISO_BITLEN_W { - REG_USR_MISO_BITLEN_W::new(self, 8) - } - #[doc = "Bits 17:25 - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_mosi_bitlen(&mut self) -> REG_USR_MOSI_BITLEN_W { - REG_USR_MOSI_BITLEN_W::new(self, 17) - } - #[doc = "Bits 26:31 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_addr_bitlen(&mut self) -> REG_USR_ADDR_BITLEN_W { - REG_USR_ADDR_BITLEN_W::new(self, 26) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The length in bits of \"address\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER1_SPEC; -impl crate::RegisterSpec for SPI_USER1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user1::R`](R) reader structure"] -impl crate::Readable for SPI_USER1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user1::W`](W) writer structure"] -impl crate::Writable for SPI_USER1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER1 to value 0"] -impl crate::Resettable for SPI_USER1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_user2.rs b/esp8266/src/spi0/spi_user2.rs deleted file mode 100644 index 8b70cf1725..0000000000 --- a/esp8266/src/spi0/spi_user2.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SPI_USER2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER2` writer"] -pub type W = crate::W; -#[doc = "Field `reg_usr_command_value` reader - The value of \"command\" phase"] -pub type REG_USR_COMMAND_VALUE_R = crate::FieldReader; -#[doc = "Field `reg_usr_command_value` writer - The value of \"command\" phase"] -pub type REG_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `reg_usr_command_bitlen` reader - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_COMMAND_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_command_bitlen` writer - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:15 - The value of \"command\" phase"] - #[inline(always)] - pub fn reg_usr_command_value(&self) -> REG_USR_COMMAND_VALUE_R { - REG_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 28:31 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_command_bitlen(&self) -> REG_USR_COMMAND_BITLEN_R { - REG_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER2") - .field( - "reg_usr_command_bitlen", - &format_args!("{}", self.reg_usr_command_bitlen().bits()), - ) - .field( - "reg_usr_command_value", - &format_args!("{}", self.reg_usr_command_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - The value of \"command\" phase"] - #[inline(always)] - #[must_use] - pub fn reg_usr_command_value(&mut self) -> REG_USR_COMMAND_VALUE_W { - REG_USR_COMMAND_VALUE_W::new(self, 0) - } - #[doc = "Bits 28:31 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_command_bitlen(&mut self) -> REG_USR_COMMAND_BITLEN_W { - REG_USR_COMMAND_BITLEN_W::new(self, 28) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The length in bits of \"command\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER2_SPEC; -impl crate::RegisterSpec for SPI_USER2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user2::R`](R) reader structure"] -impl crate::Readable for SPI_USER2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user2::W`](W) writer structure"] -impl crate::Writable for SPI_USER2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER2 to value 0"] -impl crate::Resettable for SPI_USER2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w0.rs b/esp8266/src/spi0/spi_w0.rs deleted file mode 100644 index 75e1624953..0000000000 --- a/esp8266/src/spi0/spi_w0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W0` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W0` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w0` reader - the data inside the buffer of the SPI module, word 0"] -pub type SPI_W0_R = crate::FieldReader; -#[doc = "Field `spi_w0` writer - the data inside the buffer of the SPI module, word 0"] -pub type SPI_W0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - pub fn spi_w0(&self) -> SPI_W0_R { - SPI_W0_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W0") - .field("spi_w0", &format_args!("{}", self.spi_w0().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - #[must_use] - pub fn spi_w0(&mut self) -> SPI_W0_W { - SPI_W0_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W0_SPEC; -impl crate::RegisterSpec for SPI_W0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w0::R`](R) reader structure"] -impl crate::Readable for SPI_W0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w0::W`](W) writer structure"] -impl crate::Writable for SPI_W0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W0 to value 0"] -impl crate::Resettable for SPI_W0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w1.rs b/esp8266/src/spi0/spi_w1.rs deleted file mode 100644 index e6dd0cc9e6..0000000000 --- a/esp8266/src/spi0/spi_w1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W1` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w1` reader - the data inside the buffer of the SPI module, word 1"] -pub type SPI_W1_R = crate::FieldReader; -#[doc = "Field `spi_w1` writer - the data inside the buffer of the SPI module, word 1"] -pub type SPI_W1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - pub fn spi_w1(&self) -> SPI_W1_R { - SPI_W1_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W1") - .field("spi_w1", &format_args!("{}", self.spi_w1().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - #[must_use] - pub fn spi_w1(&mut self) -> SPI_W1_W { - SPI_W1_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W1_SPEC; -impl crate::RegisterSpec for SPI_W1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w1::R`](R) reader structure"] -impl crate::Readable for SPI_W1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w1::W`](W) writer structure"] -impl crate::Writable for SPI_W1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W1 to value 0"] -impl crate::Resettable for SPI_W1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w10.rs b/esp8266/src/spi0/spi_w10.rs deleted file mode 100644 index 2b94029724..0000000000 --- a/esp8266/src/spi0/spi_w10.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W10` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W10` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w10` reader - the data inside the buffer of the SPI module, word 10"] -pub type SPI_W10_R = crate::FieldReader; -#[doc = "Field `spi_w10` writer - the data inside the buffer of the SPI module, word 10"] -pub type SPI_W10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - pub fn spi_w10(&self) -> SPI_W10_R { - SPI_W10_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W10") - .field("spi_w10", &format_args!("{}", self.spi_w10().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - #[must_use] - pub fn spi_w10(&mut self) -> SPI_W10_W { - SPI_W10_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W10_SPEC; -impl crate::RegisterSpec for SPI_W10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w10::R`](R) reader structure"] -impl crate::Readable for SPI_W10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w10::W`](W) writer structure"] -impl crate::Writable for SPI_W10_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W10 to value 0"] -impl crate::Resettable for SPI_W10_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w11.rs b/esp8266/src/spi0/spi_w11.rs deleted file mode 100644 index 90bc965426..0000000000 --- a/esp8266/src/spi0/spi_w11.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W11` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W11` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w11` reader - the data inside the buffer of the SPI module, word 11"] -pub type SPI_W11_R = crate::FieldReader; -#[doc = "Field `spi_w11` writer - the data inside the buffer of the SPI module, word 11"] -pub type SPI_W11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - pub fn spi_w11(&self) -> SPI_W11_R { - SPI_W11_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W11") - .field("spi_w11", &format_args!("{}", self.spi_w11().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - #[must_use] - pub fn spi_w11(&mut self) -> SPI_W11_W { - SPI_W11_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W11_SPEC; -impl crate::RegisterSpec for SPI_W11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w11::R`](R) reader structure"] -impl crate::Readable for SPI_W11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w11::W`](W) writer structure"] -impl crate::Writable for SPI_W11_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W11 to value 0"] -impl crate::Resettable for SPI_W11_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w12.rs b/esp8266/src/spi0/spi_w12.rs deleted file mode 100644 index 27977e4493..0000000000 --- a/esp8266/src/spi0/spi_w12.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W12` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W12` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w12` reader - the data inside the buffer of the SPI module, word 12"] -pub type SPI_W12_R = crate::FieldReader; -#[doc = "Field `spi_w12` writer - the data inside the buffer of the SPI module, word 12"] -pub type SPI_W12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - pub fn spi_w12(&self) -> SPI_W12_R { - SPI_W12_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W12") - .field("spi_w12", &format_args!("{}", self.spi_w12().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - #[must_use] - pub fn spi_w12(&mut self) -> SPI_W12_W { - SPI_W12_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W12_SPEC; -impl crate::RegisterSpec for SPI_W12_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w12::R`](R) reader structure"] -impl crate::Readable for SPI_W12_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w12::W`](W) writer structure"] -impl crate::Writable for SPI_W12_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W12 to value 0"] -impl crate::Resettable for SPI_W12_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w13.rs b/esp8266/src/spi0/spi_w13.rs deleted file mode 100644 index bf8a4462fa..0000000000 --- a/esp8266/src/spi0/spi_w13.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W13` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W13` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w13` reader - the data inside the buffer of the SPI module, word 13"] -pub type SPI_W13_R = crate::FieldReader; -#[doc = "Field `spi_w13` writer - the data inside the buffer of the SPI module, word 13"] -pub type SPI_W13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - pub fn spi_w13(&self) -> SPI_W13_R { - SPI_W13_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W13") - .field("spi_w13", &format_args!("{}", self.spi_w13().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - #[must_use] - pub fn spi_w13(&mut self) -> SPI_W13_W { - SPI_W13_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W13_SPEC; -impl crate::RegisterSpec for SPI_W13_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w13::R`](R) reader structure"] -impl crate::Readable for SPI_W13_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w13::W`](W) writer structure"] -impl crate::Writable for SPI_W13_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W13 to value 0"] -impl crate::Resettable for SPI_W13_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w14.rs b/esp8266/src/spi0/spi_w14.rs deleted file mode 100644 index 47f9865c17..0000000000 --- a/esp8266/src/spi0/spi_w14.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W14` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W14` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w14` reader - the data inside the buffer of the SPI module, word 14"] -pub type SPI_W14_R = crate::FieldReader; -#[doc = "Field `spi_w14` writer - the data inside the buffer of the SPI module, word 14"] -pub type SPI_W14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - pub fn spi_w14(&self) -> SPI_W14_R { - SPI_W14_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W14") - .field("spi_w14", &format_args!("{}", self.spi_w14().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - #[must_use] - pub fn spi_w14(&mut self) -> SPI_W14_W { - SPI_W14_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W14_SPEC; -impl crate::RegisterSpec for SPI_W14_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w14::R`](R) reader structure"] -impl crate::Readable for SPI_W14_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w14::W`](W) writer structure"] -impl crate::Writable for SPI_W14_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W14 to value 0"] -impl crate::Resettable for SPI_W14_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w15.rs b/esp8266/src/spi0/spi_w15.rs deleted file mode 100644 index 9d613f3985..0000000000 --- a/esp8266/src/spi0/spi_w15.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W15` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W15` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w15` reader - the data inside the buffer of the SPI module, word 15"] -pub type SPI_W15_R = crate::FieldReader; -#[doc = "Field `spi_w15` writer - the data inside the buffer of the SPI module, word 15"] -pub type SPI_W15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - pub fn spi_w15(&self) -> SPI_W15_R { - SPI_W15_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W15") - .field("spi_w15", &format_args!("{}", self.spi_w15().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - #[must_use] - pub fn spi_w15(&mut self) -> SPI_W15_W { - SPI_W15_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W15_SPEC; -impl crate::RegisterSpec for SPI_W15_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w15::R`](R) reader structure"] -impl crate::Readable for SPI_W15_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w15::W`](W) writer structure"] -impl crate::Writable for SPI_W15_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W15 to value 0"] -impl crate::Resettable for SPI_W15_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w2.rs b/esp8266/src/spi0/spi_w2.rs deleted file mode 100644 index 142dc225b6..0000000000 --- a/esp8266/src/spi0/spi_w2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W2` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w2` reader - the data inside the buffer of the SPI module, word 2"] -pub type SPI_W2_R = crate::FieldReader; -#[doc = "Field `spi_w2` writer - the data inside the buffer of the SPI module, word 2"] -pub type SPI_W2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - pub fn spi_w2(&self) -> SPI_W2_R { - SPI_W2_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W2") - .field("spi_w2", &format_args!("{}", self.spi_w2().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - #[must_use] - pub fn spi_w2(&mut self) -> SPI_W2_W { - SPI_W2_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W2_SPEC; -impl crate::RegisterSpec for SPI_W2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w2::R`](R) reader structure"] -impl crate::Readable for SPI_W2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w2::W`](W) writer structure"] -impl crate::Writable for SPI_W2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W2 to value 0"] -impl crate::Resettable for SPI_W2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w3.rs b/esp8266/src/spi0/spi_w3.rs deleted file mode 100644 index e6af27f702..0000000000 --- a/esp8266/src/spi0/spi_w3.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W3` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w3` reader - the data inside the buffer of the SPI module, word 3"] -pub type SPI_W3_R = crate::FieldReader; -#[doc = "Field `spi_w3` writer - the data inside the buffer of the SPI module, word 3"] -pub type SPI_W3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - pub fn spi_w3(&self) -> SPI_W3_R { - SPI_W3_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W3") - .field("spi_w3", &format_args!("{}", self.spi_w3().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - #[must_use] - pub fn spi_w3(&mut self) -> SPI_W3_W { - SPI_W3_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W3_SPEC; -impl crate::RegisterSpec for SPI_W3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w3::R`](R) reader structure"] -impl crate::Readable for SPI_W3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w3::W`](W) writer structure"] -impl crate::Writable for SPI_W3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W3 to value 0"] -impl crate::Resettable for SPI_W3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w4.rs b/esp8266/src/spi0/spi_w4.rs deleted file mode 100644 index ad2a4a4c36..0000000000 --- a/esp8266/src/spi0/spi_w4.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W4` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W4` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w4` reader - the data inside the buffer of the SPI module, word 4"] -pub type SPI_W4_R = crate::FieldReader; -#[doc = "Field `spi_w4` writer - the data inside the buffer of the SPI module, word 4"] -pub type SPI_W4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - pub fn spi_w4(&self) -> SPI_W4_R { - SPI_W4_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W4") - .field("spi_w4", &format_args!("{}", self.spi_w4().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - #[must_use] - pub fn spi_w4(&mut self) -> SPI_W4_W { - SPI_W4_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W4_SPEC; -impl crate::RegisterSpec for SPI_W4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w4::R`](R) reader structure"] -impl crate::Readable for SPI_W4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w4::W`](W) writer structure"] -impl crate::Writable for SPI_W4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W4 to value 0"] -impl crate::Resettable for SPI_W4_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w5.rs b/esp8266/src/spi0/spi_w5.rs deleted file mode 100644 index 581a12b6cc..0000000000 --- a/esp8266/src/spi0/spi_w5.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W5` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W5` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w5` reader - the data inside the buffer of the SPI module, word 5"] -pub type SPI_W5_R = crate::FieldReader; -#[doc = "Field `spi_w5` writer - the data inside the buffer of the SPI module, word 5"] -pub type SPI_W5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - pub fn spi_w5(&self) -> SPI_W5_R { - SPI_W5_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W5") - .field("spi_w5", &format_args!("{}", self.spi_w5().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - #[must_use] - pub fn spi_w5(&mut self) -> SPI_W5_W { - SPI_W5_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W5_SPEC; -impl crate::RegisterSpec for SPI_W5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w5::R`](R) reader structure"] -impl crate::Readable for SPI_W5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w5::W`](W) writer structure"] -impl crate::Writable for SPI_W5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W5 to value 0"] -impl crate::Resettable for SPI_W5_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w6.rs b/esp8266/src/spi0/spi_w6.rs deleted file mode 100644 index 9621962619..0000000000 --- a/esp8266/src/spi0/spi_w6.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W6` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W6` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w6` reader - the data inside the buffer of the SPI module, word 6"] -pub type SPI_W6_R = crate::FieldReader; -#[doc = "Field `spi_w6` writer - the data inside the buffer of the SPI module, word 6"] -pub type SPI_W6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - pub fn spi_w6(&self) -> SPI_W6_R { - SPI_W6_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W6") - .field("spi_w6", &format_args!("{}", self.spi_w6().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - #[must_use] - pub fn spi_w6(&mut self) -> SPI_W6_W { - SPI_W6_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W6_SPEC; -impl crate::RegisterSpec for SPI_W6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w6::R`](R) reader structure"] -impl crate::Readable for SPI_W6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w6::W`](W) writer structure"] -impl crate::Writable for SPI_W6_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W6 to value 0"] -impl crate::Resettable for SPI_W6_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w7.rs b/esp8266/src/spi0/spi_w7.rs deleted file mode 100644 index a944063d60..0000000000 --- a/esp8266/src/spi0/spi_w7.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W7` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W7` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w7` reader - the data inside the buffer of the SPI module, word 7"] -pub type SPI_W7_R = crate::FieldReader; -#[doc = "Field `spi_w7` writer - the data inside the buffer of the SPI module, word 7"] -pub type SPI_W7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - pub fn spi_w7(&self) -> SPI_W7_R { - SPI_W7_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W7") - .field("spi_w7", &format_args!("{}", self.spi_w7().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - #[must_use] - pub fn spi_w7(&mut self) -> SPI_W7_W { - SPI_W7_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W7_SPEC; -impl crate::RegisterSpec for SPI_W7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w7::R`](R) reader structure"] -impl crate::Readable for SPI_W7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w7::W`](W) writer structure"] -impl crate::Writable for SPI_W7_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W7 to value 0"] -impl crate::Resettable for SPI_W7_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w8.rs b/esp8266/src/spi0/spi_w8.rs deleted file mode 100644 index a2baeeeaaa..0000000000 --- a/esp8266/src/spi0/spi_w8.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W8` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W8` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w8` reader - the data inside the buffer of the SPI module, word 8"] -pub type SPI_W8_R = crate::FieldReader; -#[doc = "Field `spi_w8` writer - the data inside the buffer of the SPI module, word 8"] -pub type SPI_W8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - pub fn spi_w8(&self) -> SPI_W8_R { - SPI_W8_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W8") - .field("spi_w8", &format_args!("{}", self.spi_w8().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - #[must_use] - pub fn spi_w8(&mut self) -> SPI_W8_W { - SPI_W8_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W8_SPEC; -impl crate::RegisterSpec for SPI_W8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w8::R`](R) reader structure"] -impl crate::Readable for SPI_W8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w8::W`](W) writer structure"] -impl crate::Writable for SPI_W8_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W8 to value 0"] -impl crate::Resettable for SPI_W8_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_w9.rs b/esp8266/src/spi0/spi_w9.rs deleted file mode 100644 index d61d024040..0000000000 --- a/esp8266/src/spi0/spi_w9.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W9` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W9` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w9` reader - the data inside the buffer of the SPI module, word 9"] -pub type SPI_W9_R = crate::FieldReader; -#[doc = "Field `spi_w9` writer - the data inside the buffer of the SPI module, word 9"] -pub type SPI_W9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - pub fn spi_w9(&self) -> SPI_W9_R { - SPI_W9_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W9") - .field("spi_w9", &format_args!("{}", self.spi_w9().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - #[must_use] - pub fn spi_w9(&mut self) -> SPI_W9_W { - SPI_W9_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W9_SPEC; -impl crate::RegisterSpec for SPI_W9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w9::R`](R) reader structure"] -impl crate::Readable for SPI_W9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w9::W`](W) writer structure"] -impl crate::Writable for SPI_W9_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W9 to value 0"] -impl crate::Resettable for SPI_W9_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi0/spi_wr_status.rs b/esp8266/src/spi0/spi_wr_status.rs deleted file mode 100644 index 352c3741d6..0000000000 --- a/esp8266/src/spi0/spi_wr_status.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_WR_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_WR_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `slv_wr_status` reader - In the slave mode, this register are the status register for the master to write into."] -pub type SLV_WR_STATUS_R = crate::FieldReader; -#[doc = "Field `slv_wr_status` writer - In the slave mode, this register are the status register for the master to write into."] -pub type SLV_WR_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - pub fn slv_wr_status(&self) -> SLV_WR_STATUS_R { - SLV_WR_STATUS_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_WR_STATUS") - .field( - "slv_wr_status", - &format_args!("{}", self.slv_wr_status().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - #[must_use] - pub fn slv_wr_status(&mut self) -> SLV_WR_STATUS_W { - SLV_WR_STATUS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, this register are the status register for the master to write into.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_wr_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_wr_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_WR_STATUS_SPEC; -impl crate::RegisterSpec for SPI_WR_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_wr_status::R`](R) reader structure"] -impl crate::Readable for SPI_WR_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_wr_status::W`](W) writer structure"] -impl crate::Writable for SPI_WR_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_WR_STATUS to value 0"] -impl crate::Resettable for SPI_WR_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1.rs b/esp8266/src/spi1.rs deleted file mode 100644 index 9be6b79f62..0000000000 --- a/esp8266/src/spi1.rs +++ /dev/null @@ -1,368 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - spi_cmd: SPI_CMD, - spi_addr: SPI_ADDR, - spi_ctrl: SPI_CTRL, - spi_ctrl1: SPI_CTRL1, - spi_rd_status: SPI_RD_STATUS, - spi_ctrl2: SPI_CTRL2, - spi_clock: SPI_CLOCK, - spi_user: SPI_USER, - spi_user1: SPI_USER1, - spi_user2: SPI_USER2, - spi_wr_status: SPI_WR_STATUS, - spi_pin: SPI_PIN, - spi_slave: SPI_SLAVE, - spi_slave1: SPI_SLAVE1, - spi_slave2: SPI_SLAVE2, - spi_slave3: SPI_SLAVE3, - spi_w0: SPI_W0, - spi_w1: SPI_W1, - spi_w2: SPI_W2, - spi_w3: SPI_W3, - spi_w4: SPI_W4, - spi_w5: SPI_W5, - spi_w6: SPI_W6, - spi_w7: SPI_W7, - spi_w8: SPI_W8, - spi_w9: SPI_W9, - spi_w10: SPI_W10, - spi_w11: SPI_W11, - spi_w12: SPI_W12, - spi_w13: SPI_W13, - spi_w14: SPI_W14, - spi_w15: SPI_W15, - _reserved32: [u8; 0x70], - spi_ext0: SPI_EXT0, - spi_ext1: SPI_EXT1, - spi_ext2: SPI_EXT2, - spi_ext3: SPI_EXT3, -} -impl RegisterBlock { - #[doc = "0x00 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - pub const fn spi_cmd(&self) -> &SPI_CMD { - &self.spi_cmd - } - #[doc = "0x04 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - pub const fn spi_addr(&self) -> &SPI_ADDR { - &self.spi_addr - } - #[doc = "0x08 - SPI_CTRL"] - #[inline(always)] - pub const fn spi_ctrl(&self) -> &SPI_CTRL { - &self.spi_ctrl - } - #[doc = "0x0c - "] - #[inline(always)] - pub const fn spi_ctrl1(&self) -> &SPI_CTRL1 { - &self.spi_ctrl1 - } - #[doc = "0x10 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - pub const fn spi_rd_status(&self) -> &SPI_RD_STATUS { - &self.spi_rd_status - } - #[doc = "0x14 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - pub const fn spi_ctrl2(&self) -> &SPI_CTRL2 { - &self.spi_ctrl2 - } - #[doc = "0x18 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - pub const fn spi_clock(&self) -> &SPI_CLOCK { - &self.spi_clock - } - #[doc = "0x1c - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - pub const fn spi_user(&self) -> &SPI_USER { - &self.spi_user - } - #[doc = "0x20 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_user1(&self) -> &SPI_USER1 { - &self.spi_user1 - } - #[doc = "0x24 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_user2(&self) -> &SPI_USER2 { - &self.spi_user2 - } - #[doc = "0x28 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - pub const fn spi_wr_status(&self) -> &SPI_WR_STATUS { - &self.spi_wr_status - } - #[doc = "0x2c - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - pub const fn spi_pin(&self) -> &SPI_PIN { - &self.spi_pin - } - #[doc = "0x30 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - pub const fn spi_slave(&self) -> &SPI_SLAVE { - &self.spi_slave - } - #[doc = "0x34 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - pub const fn spi_slave1(&self) -> &SPI_SLAVE1 { - &self.spi_slave1 - } - #[doc = "0x38 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub const fn spi_slave2(&self) -> &SPI_SLAVE2 { - &self.spi_slave2 - } - #[doc = "0x3c - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - pub const fn spi_slave3(&self) -> &SPI_SLAVE3 { - &self.spi_slave3 - } - #[doc = "0x40 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - pub const fn spi_w0(&self) -> &SPI_W0 { - &self.spi_w0 - } - #[doc = "0x44 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - pub const fn spi_w1(&self) -> &SPI_W1 { - &self.spi_w1 - } - #[doc = "0x48 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - pub const fn spi_w2(&self) -> &SPI_W2 { - &self.spi_w2 - } - #[doc = "0x4c - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - pub const fn spi_w3(&self) -> &SPI_W3 { - &self.spi_w3 - } - #[doc = "0x50 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - pub const fn spi_w4(&self) -> &SPI_W4 { - &self.spi_w4 - } - #[doc = "0x54 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - pub const fn spi_w5(&self) -> &SPI_W5 { - &self.spi_w5 - } - #[doc = "0x58 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - pub const fn spi_w6(&self) -> &SPI_W6 { - &self.spi_w6 - } - #[doc = "0x5c - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - pub const fn spi_w7(&self) -> &SPI_W7 { - &self.spi_w7 - } - #[doc = "0x60 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - pub const fn spi_w8(&self) -> &SPI_W8 { - &self.spi_w8 - } - #[doc = "0x64 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - pub const fn spi_w9(&self) -> &SPI_W9 { - &self.spi_w9 - } - #[doc = "0x68 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - pub const fn spi_w10(&self) -> &SPI_W10 { - &self.spi_w10 - } - #[doc = "0x6c - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - pub const fn spi_w11(&self) -> &SPI_W11 { - &self.spi_w11 - } - #[doc = "0x70 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - pub const fn spi_w12(&self) -> &SPI_W12 { - &self.spi_w12 - } - #[doc = "0x74 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - pub const fn spi_w13(&self) -> &SPI_W13 { - &self.spi_w13 - } - #[doc = "0x78 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - pub const fn spi_w14(&self) -> &SPI_W14 { - &self.spi_w14 - } - #[doc = "0x7c - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - pub const fn spi_w15(&self) -> &SPI_W15 { - &self.spi_w15 - } - #[doc = "0xf0 - "] - #[inline(always)] - pub const fn spi_ext0(&self) -> &SPI_EXT0 { - &self.spi_ext0 - } - #[doc = "0xf4 - "] - #[inline(always)] - pub const fn spi_ext1(&self) -> &SPI_EXT1 { - &self.spi_ext1 - } - #[doc = "0xf8 - "] - #[inline(always)] - pub const fn spi_ext2(&self) -> &SPI_EXT2 { - &self.spi_ext2 - } - #[doc = "0xfc - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - pub const fn spi_ext3(&self) -> &SPI_EXT3 { - &self.spi_ext3 - } -} -#[doc = "SPI_CMD (rw) register accessor: In the master mode, it is the start bit of a single operation. Self-clear by hardware\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cmd`] module"] -pub type SPI_CMD = crate::Reg; -#[doc = "In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub mod spi_cmd; -#[doc = "SPI_ADDR (rw) register accessor: In the master mode, it is the value of address in \"address\" phase.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_addr`] module"] -pub type SPI_ADDR = crate::Reg; -#[doc = "In the master mode, it is the value of address in \"address\" phase."] -pub mod spi_addr; -#[doc = "SPI_CTRL (rw) register accessor: SPI_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl`] module"] -pub type SPI_CTRL = crate::Reg; -#[doc = "SPI_CTRL"] -pub mod spi_ctrl; -#[doc = "SPI_RD_STATUS (rw) register accessor: In the slave mode, this register are the status register for the master to read out.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rd_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rd_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rd_status`] module"] -pub type SPI_RD_STATUS = crate::Reg; -#[doc = "In the slave mode, this register are the status register for the master to read out."] -pub mod spi_rd_status; -#[doc = "SPI_CTRL2 (rw) register accessor: spi_cs signal is delayed by 80MHz clock cycles\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl2`] module"] -pub type SPI_CTRL2 = crate::Reg; -#[doc = "spi_cs signal is delayed by 80MHz clock cycles"] -pub mod spi_ctrl2; -#[doc = "SPI_CLOCK (rw) register accessor: In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clock`] module"] -pub type SPI_CLOCK = crate::Reg; -#[doc = "In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub mod spi_clock; -#[doc = "SPI_USER (rw) register accessor: This bit enable the \"command\" phase of an operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user`] module"] -pub type SPI_USER = crate::Reg; -#[doc = "This bit enable the \"command\" phase of an operation."] -pub mod spi_user; -#[doc = "SPI_USER1 (rw) register accessor: The length in bits of \"address\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user1`] module"] -pub type SPI_USER1 = crate::Reg; -#[doc = "The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub mod spi_user1; -#[doc = "SPI_USER2 (rw) register accessor: The length in bits of \"command\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user2`] module"] -pub type SPI_USER2 = crate::Reg; -#[doc = "The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub mod spi_user2; -#[doc = "SPI_WR_STATUS (rw) register accessor: In the slave mode, this register are the status register for the master to write into.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_wr_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_wr_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wr_status`] module"] -pub type SPI_WR_STATUS = crate::Reg; -#[doc = "In the slave mode, this register are the status register for the master to write into."] -pub mod spi_wr_status; -#[doc = "SPI_PIN (rw) register accessor: 1: disable CS2; 0: spi_cs signal is from/to CS2 pin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_pin::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_pin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_pin`] module"] -pub type SPI_PIN = crate::Reg; -#[doc = "1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub mod spi_pin; -#[doc = "SPI_SLAVE (rw) register accessor: It is the synchronous reset signal of the module. This bit is self-cleared by hardware.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave`] module"] -pub type SPI_SLAVE = crate::Reg; -#[doc = "It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub mod spi_slave; -#[doc = "SPI_SLAVE1 (rw) register accessor: In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave1`] module"] -pub type SPI_SLAVE1 = crate::Reg; -#[doc = "In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub mod spi_slave1; -#[doc = "SPI_SLAVE2 (rw) register accessor: In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave2`] module"] -pub type SPI_SLAVE2 = crate::Reg; -#[doc = "In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub mod spi_slave2; -#[doc = "SPI_SLAVE3 (rw) register accessor: In slave mode, it is the value of \"write-status\" command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave3`] module"] -pub type SPI_SLAVE3 = crate::Reg; -#[doc = "In slave mode, it is the value of \"write-status\" command"] -pub mod spi_slave3; -#[doc = "SPI_EXT3 (rw) register accessor: This register is for two SPI masters to share the same cs, clock and data signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext3`] module"] -pub type SPI_EXT3 = crate::Reg; -#[doc = "This register is for two SPI masters to share the same cs, clock and data signals."] -pub mod spi_ext3; -#[doc = "SPI_W0 (rw) register accessor: the data inside the buffer of the SPI module, word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w0`] module"] -pub type SPI_W0 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 0"] -pub mod spi_w0; -#[doc = "SPI_W1 (rw) register accessor: the data inside the buffer of the SPI module, word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w1`] module"] -pub type SPI_W1 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 1"] -pub mod spi_w1; -#[doc = "SPI_W2 (rw) register accessor: the data inside the buffer of the SPI module, word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w2`] module"] -pub type SPI_W2 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 2"] -pub mod spi_w2; -#[doc = "SPI_W3 (rw) register accessor: the data inside the buffer of the SPI module, word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w3`] module"] -pub type SPI_W3 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 3"] -pub mod spi_w3; -#[doc = "SPI_W4 (rw) register accessor: the data inside the buffer of the SPI module, word 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w4`] module"] -pub type SPI_W4 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 4"] -pub mod spi_w4; -#[doc = "SPI_W5 (rw) register accessor: the data inside the buffer of the SPI module, word 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w5`] module"] -pub type SPI_W5 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 5"] -pub mod spi_w5; -#[doc = "SPI_W6 (rw) register accessor: the data inside the buffer of the SPI module, word 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w6`] module"] -pub type SPI_W6 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 6"] -pub mod spi_w6; -#[doc = "SPI_W7 (rw) register accessor: the data inside the buffer of the SPI module, word 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w7`] module"] -pub type SPI_W7 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 7"] -pub mod spi_w7; -#[doc = "SPI_W8 (rw) register accessor: the data inside the buffer of the SPI module, word 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w8`] module"] -pub type SPI_W8 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 8"] -pub mod spi_w8; -#[doc = "SPI_W9 (rw) register accessor: the data inside the buffer of the SPI module, word 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w9`] module"] -pub type SPI_W9 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 9"] -pub mod spi_w9; -#[doc = "SPI_W10 (rw) register accessor: the data inside the buffer of the SPI module, word 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w10`] module"] -pub type SPI_W10 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 10"] -pub mod spi_w10; -#[doc = "SPI_W11 (rw) register accessor: the data inside the buffer of the SPI module, word 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w11`] module"] -pub type SPI_W11 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 11"] -pub mod spi_w11; -#[doc = "SPI_W12 (rw) register accessor: the data inside the buffer of the SPI module, word 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w12`] module"] -pub type SPI_W12 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 12"] -pub mod spi_w12; -#[doc = "SPI_W13 (rw) register accessor: the data inside the buffer of the SPI module, word 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w13`] module"] -pub type SPI_W13 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 13"] -pub mod spi_w13; -#[doc = "SPI_W14 (rw) register accessor: the data inside the buffer of the SPI module, word 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w14`] module"] -pub type SPI_W14 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 14"] -pub mod spi_w14; -#[doc = "SPI_W15 (rw) register accessor: the data inside the buffer of the SPI module, word 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w15`] module"] -pub type SPI_W15 = crate::Reg; -#[doc = "the data inside the buffer of the SPI module, word 15"] -pub mod spi_w15; -#[doc = "SPI_CTRL1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl1`] module"] -pub type SPI_CTRL1 = crate::Reg; -#[doc = ""] -pub mod spi_ctrl1; -#[doc = "SPI_EXT0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext0`] module"] -pub type SPI_EXT0 = crate::Reg; -#[doc = ""] -pub mod spi_ext0; -#[doc = "SPI_EXT1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext1`] module"] -pub type SPI_EXT1 = crate::Reg; -#[doc = ""] -pub mod spi_ext1; -#[doc = "SPI_EXT2 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ext2`] module"] -pub type SPI_EXT2 = crate::Reg; -#[doc = ""] -pub mod spi_ext2; diff --git a/esp8266/src/spi1/spi_addr.rs b/esp8266/src/spi1/spi_addr.rs deleted file mode 100644 index 799938b12c..0000000000 --- a/esp8266/src/spi1/spi_addr.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = "Register `SPI_ADDR` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_ADDR` writer"] -pub type W = crate::W; -#[doc = "Field `iodata_start_addr` reader - In the master mode, it is the value of address in \"address\" phase."] -pub type IODATA_START_ADDR_R = crate::FieldReader; -#[doc = "Field `iodata_start_addr` writer - In the master mode, it is the value of address in \"address\" phase."] -pub type IODATA_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `address` reader - "] -pub type ADDRESS_R = crate::FieldReader; -#[doc = "Field `address` writer - "] -pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; -#[doc = "Field `size` reader - "] -pub type SIZE_R = crate::FieldReader; -#[doc = "Field `size` writer - "] -pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - pub fn iodata_start_addr(&self) -> IODATA_START_ADDR_R { - IODATA_START_ADDR_R::new(self.bits) - } - #[doc = "Bits 0:23"] - #[inline(always)] - pub fn address(&self) -> ADDRESS_R { - ADDRESS_R::new(self.bits & 0x00ff_ffff) - } - #[doc = "Bits 24:31"] - #[inline(always)] - pub fn size(&self) -> SIZE_R { - SIZE_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_ADDR") - .field( - "iodata_start_addr", - &format_args!("{}", self.iodata_start_addr().bits()), - ) - .field("address", &format_args!("{}", self.address().bits())) - .field("size", &format_args!("{}", self.size().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."] - #[inline(always)] - #[must_use] - pub fn iodata_start_addr(&mut self) -> IODATA_START_ADDR_W { - IODATA_START_ADDR_W::new(self, 0) - } - #[doc = "Bits 0:23"] - #[inline(always)] - #[must_use] - pub fn address(&mut self) -> ADDRESS_W { - ADDRESS_W::new(self, 0) - } - #[doc = "Bits 24:31"] - #[inline(always)] - #[must_use] - pub fn size(&mut self) -> SIZE_W { - SIZE_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, it is the value of address in \"address\" phase.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_ADDR_SPEC; -impl crate::RegisterSpec for SPI_ADDR_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_addr::R`](R) reader structure"] -impl crate::Readable for SPI_ADDR_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_addr::W`](W) writer structure"] -impl crate::Writable for SPI_ADDR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_ADDR to value 0"] -impl crate::Resettable for SPI_ADDR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_clock.rs b/esp8266/src/spi1/spi_clock.rs deleted file mode 100644 index 1fe6e08bae..0000000000 --- a/esp8266/src/spi1/spi_clock.rs +++ /dev/null @@ -1,142 +0,0 @@ -#[doc = "Register `SPI_CLOCK` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CLOCK` writer"] -pub type W = crate::W; -#[doc = "Field `spi_clkcnt_L` reader - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] -pub type SPI_CLKCNT_L_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_L` writer - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] -pub type SPI_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkcnt_H` reader - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] -pub type SPI_CLKCNT_H_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_H` writer - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] -pub type SPI_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkcnt_N` reader - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] -pub type SPI_CLKCNT_N_R = crate::FieldReader; -#[doc = "Field `spi_clkcnt_N` writer - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] -pub type SPI_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `spi_clkdiv_pre` reader - In the master mode, it is pre-divider of spi_clk."] -pub type SPI_CLKDIV_PRE_R = crate::FieldReader; -#[doc = "Field `spi_clkdiv_pre` writer - In the master mode, it is pre-divider of spi_clk."] -pub type SPI_CLKDIV_PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -#[doc = "Field `spi_clk_equ_sysclk` reader - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub type SPI_CLK_EQU_SYSCLK_R = crate::BitReader; -#[doc = "Field `spi_clk_equ_sysclk` writer - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] -pub type SPI_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] - #[inline(always)] - pub fn spi_clkcnt_l(&self) -> SPI_CLKCNT_L_R { - SPI_CLKCNT_L_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] - #[inline(always)] - pub fn spi_clkcnt_h(&self) -> SPI_CLKCNT_H_R { - SPI_CLKCNT_H_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:17 - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] - #[inline(always)] - pub fn spi_clkcnt_n(&self) -> SPI_CLKCNT_N_R { - SPI_CLKCNT_N_R::new(((self.bits >> 12) & 0x3f) as u8) - } - #[doc = "Bits 18:30 - In the master mode, it is pre-divider of spi_clk."] - #[inline(always)] - pub fn spi_clkdiv_pre(&self) -> SPI_CLKDIV_PRE_R { - SPI_CLKDIV_PRE_R::new(((self.bits >> 18) & 0x1fff) as u16) - } - #[doc = "Bit 31 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - pub fn spi_clk_equ_sysclk(&self) -> SPI_CLK_EQU_SYSCLK_R { - SPI_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CLOCK") - .field( - "spi_clk_equ_sysclk", - &format_args!("{}", self.spi_clk_equ_sysclk().bit()), - ) - .field( - "spi_clkdiv_pre", - &format_args!("{}", self.spi_clkdiv_pre().bits()), - ) - .field( - "spi_clkcnt_n", - &format_args!("{}", self.spi_clkcnt_n().bits()), - ) - .field( - "spi_clkcnt_h", - &format_args!("{}", self.spi_clkcnt_h().bits()), - ) - .field( - "spi_clkcnt_l", - &format_args!("{}", self.spi_clkcnt_l().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:5 - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0."] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_l(&mut self) -> SPI_CLKCNT_L_W { - SPI_CLKCNT_L_W::new(self, 0) - } - #[doc = "Bits 6:11 - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0."] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_h(&mut self) -> SPI_CLKCNT_H_W { - SPI_CLKCNT_H_W::new(self, 6) - } - #[doc = "Bits 12:17 - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)"] - #[inline(always)] - #[must_use] - pub fn spi_clkcnt_n(&mut self) -> SPI_CLKCNT_N_W { - SPI_CLKCNT_N_W::new(self, 12) - } - #[doc = "Bits 18:30 - In the master mode, it is pre-divider of spi_clk."] - #[inline(always)] - #[must_use] - pub fn spi_clkdiv_pre(&mut self) -> SPI_CLKDIV_PRE_W { - SPI_CLKDIV_PRE_W::new(self, 18) - } - #[doc = "Bit 31 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock."] - #[inline(always)] - #[must_use] - pub fn spi_clk_equ_sysclk(&mut self) -> SPI_CLK_EQU_SYSCLK_W { - SPI_CLK_EQU_SYSCLK_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CLOCK_SPEC; -impl crate::RegisterSpec for SPI_CLOCK_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_clock::R`](R) reader structure"] -impl crate::Readable for SPI_CLOCK_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_clock::W`](W) writer structure"] -impl crate::Writable for SPI_CLOCK_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CLOCK to value 0"] -impl crate::Resettable for SPI_CLOCK_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_cmd.rs b/esp8266/src/spi1/spi_cmd.rs deleted file mode 100644 index 80c59b0e14..0000000000 --- a/esp8266/src/spi1/spi_cmd.rs +++ /dev/null @@ -1,280 +0,0 @@ -#[doc = "Register `SPI_CMD` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CMD` writer"] -pub type W = crate::W; -#[doc = "Field `spi_usr` reader - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub type SPI_USR_R = crate::BitReader; -#[doc = "Field `spi_usr` writer - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] -pub type SPI_USR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_hpm` reader - "] -pub type SPI_HPM_R = crate::BitReader; -#[doc = "Field `spi_hpm` writer - "] -pub type SPI_HPM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_res` reader - "] -pub type SPI_RES_R = crate::BitReader; -#[doc = "Field `spi_res` writer - "] -pub type SPI_RES_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dp` reader - "] -pub type SPI_DP_R = crate::BitReader; -#[doc = "Field `spi_dp` writer - "] -pub type SPI_DP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ce` reader - "] -pub type SPI_CE_R = crate::BitReader; -#[doc = "Field `spi_ce` writer - "] -pub type SPI_CE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_be` reader - "] -pub type SPI_BE_R = crate::BitReader; -#[doc = "Field `spi_be` writer - "] -pub type SPI_BE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_se` reader - "] -pub type SPI_SE_R = crate::BitReader; -#[doc = "Field `spi_se` writer - "] -pub type SPI_SE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_pp` reader - "] -pub type SPI_PP_R = crate::BitReader; -#[doc = "Field `spi_pp` writer - "] -pub type SPI_PP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_sr` reader - "] -pub type SPI_WRITE_SR_R = crate::BitReader; -#[doc = "Field `spi_write_sr` writer - "] -pub type SPI_WRITE_SR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read_sr` reader - "] -pub type SPI_READ_SR_R = crate::BitReader; -#[doc = "Field `spi_read_sr` writer - "] -pub type SPI_READ_SR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read_id` reader - "] -pub type SPI_READ_ID_R = crate::BitReader; -#[doc = "Field `spi_read_id` writer - "] -pub type SPI_READ_ID_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_disable` reader - "] -pub type SPI_WRITE_DISABLE_R = crate::BitReader; -#[doc = "Field `spi_write_disable` writer - "] -pub type SPI_WRITE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_write_enable` reader - "] -pub type SPI_WRITE_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_write_enable` writer - "] -pub type SPI_WRITE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_read` reader - "] -pub type SPI_READ_R = crate::BitReader; -#[doc = "Field `spi_read` writer - "] -pub type SPI_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 18 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - pub fn spi_usr(&self) -> SPI_USR_R { - SPI_USR_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19"] - #[inline(always)] - pub fn spi_hpm(&self) -> SPI_HPM_R { - SPI_HPM_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20"] - #[inline(always)] - pub fn spi_res(&self) -> SPI_RES_R { - SPI_RES_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21"] - #[inline(always)] - pub fn spi_dp(&self) -> SPI_DP_R { - SPI_DP_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22"] - #[inline(always)] - pub fn spi_ce(&self) -> SPI_CE_R { - SPI_CE_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23"] - #[inline(always)] - pub fn spi_be(&self) -> SPI_BE_R { - SPI_BE_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24"] - #[inline(always)] - pub fn spi_se(&self) -> SPI_SE_R { - SPI_SE_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25"] - #[inline(always)] - pub fn spi_pp(&self) -> SPI_PP_R { - SPI_PP_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26"] - #[inline(always)] - pub fn spi_write_sr(&self) -> SPI_WRITE_SR_R { - SPI_WRITE_SR_R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bit 27"] - #[inline(always)] - pub fn spi_read_sr(&self) -> SPI_READ_SR_R { - SPI_READ_SR_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28"] - #[inline(always)] - pub fn spi_read_id(&self) -> SPI_READ_ID_R { - SPI_READ_ID_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29"] - #[inline(always)] - pub fn spi_write_disable(&self) -> SPI_WRITE_DISABLE_R { - SPI_WRITE_DISABLE_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30"] - #[inline(always)] - pub fn spi_write_enable(&self) -> SPI_WRITE_ENABLE_R { - SPI_WRITE_ENABLE_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn spi_read(&self) -> SPI_READ_R { - SPI_READ_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CMD") - .field("spi_usr", &format_args!("{}", self.spi_usr().bit())) - .field("spi_read", &format_args!("{}", self.spi_read().bit())) - .field( - "spi_write_enable", - &format_args!("{}", self.spi_write_enable().bit()), - ) - .field( - "spi_write_disable", - &format_args!("{}", self.spi_write_disable().bit()), - ) - .field("spi_read_id", &format_args!("{}", self.spi_read_id().bit())) - .field("spi_read_sr", &format_args!("{}", self.spi_read_sr().bit())) - .field( - "spi_write_sr", - &format_args!("{}", self.spi_write_sr().bit()), - ) - .field("spi_pp", &format_args!("{}", self.spi_pp().bit())) - .field("spi_se", &format_args!("{}", self.spi_se().bit())) - .field("spi_be", &format_args!("{}", self.spi_be().bit())) - .field("spi_ce", &format_args!("{}", self.spi_ce().bit())) - .field("spi_dp", &format_args!("{}", self.spi_dp().bit())) - .field("spi_res", &format_args!("{}", self.spi_res().bit())) - .field("spi_hpm", &format_args!("{}", self.spi_hpm().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 18 - In the master mode, it is the start bit of a single operation. Self-clear by hardware"] - #[inline(always)] - #[must_use] - pub fn spi_usr(&mut self) -> SPI_USR_W { - SPI_USR_W::new(self, 18) - } - #[doc = "Bit 19"] - #[inline(always)] - #[must_use] - pub fn spi_hpm(&mut self) -> SPI_HPM_W { - SPI_HPM_W::new(self, 19) - } - #[doc = "Bit 20"] - #[inline(always)] - #[must_use] - pub fn spi_res(&mut self) -> SPI_RES_W { - SPI_RES_W::new(self, 20) - } - #[doc = "Bit 21"] - #[inline(always)] - #[must_use] - pub fn spi_dp(&mut self) -> SPI_DP_W { - SPI_DP_W::new(self, 21) - } - #[doc = "Bit 22"] - #[inline(always)] - #[must_use] - pub fn spi_ce(&mut self) -> SPI_CE_W { - SPI_CE_W::new(self, 22) - } - #[doc = "Bit 23"] - #[inline(always)] - #[must_use] - pub fn spi_be(&mut self) -> SPI_BE_W { - SPI_BE_W::new(self, 23) - } - #[doc = "Bit 24"] - #[inline(always)] - #[must_use] - pub fn spi_se(&mut self) -> SPI_SE_W { - SPI_SE_W::new(self, 24) - } - #[doc = "Bit 25"] - #[inline(always)] - #[must_use] - pub fn spi_pp(&mut self) -> SPI_PP_W { - SPI_PP_W::new(self, 25) - } - #[doc = "Bit 26"] - #[inline(always)] - #[must_use] - pub fn spi_write_sr(&mut self) -> SPI_WRITE_SR_W { - SPI_WRITE_SR_W::new(self, 26) - } - #[doc = "Bit 27"] - #[inline(always)] - #[must_use] - pub fn spi_read_sr(&mut self) -> SPI_READ_SR_W { - SPI_READ_SR_W::new(self, 27) - } - #[doc = "Bit 28"] - #[inline(always)] - #[must_use] - pub fn spi_read_id(&mut self) -> SPI_READ_ID_W { - SPI_READ_ID_W::new(self, 28) - } - #[doc = "Bit 29"] - #[inline(always)] - #[must_use] - pub fn spi_write_disable(&mut self) -> SPI_WRITE_DISABLE_W { - SPI_WRITE_DISABLE_W::new(self, 29) - } - #[doc = "Bit 30"] - #[inline(always)] - #[must_use] - pub fn spi_write_enable(&mut self) -> SPI_WRITE_ENABLE_W { - SPI_WRITE_ENABLE_W::new(self, 30) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn spi_read(&mut self) -> SPI_READ_W { - SPI_READ_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the master mode, it is the start bit of a single operation. Self-clear by hardware\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CMD_SPEC; -impl crate::RegisterSpec for SPI_CMD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_cmd::R`](R) reader structure"] -impl crate::Readable for SPI_CMD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_cmd::W`](W) writer structure"] -impl crate::Writable for SPI_CMD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CMD to value 0"] -impl crate::Resettable for SPI_CMD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ctrl.rs b/esp8266/src/spi1/spi_ctrl.rs deleted file mode 100644 index f55e8560f8..0000000000 --- a/esp8266/src/spi1/spi_ctrl.rs +++ /dev/null @@ -1,295 +0,0 @@ -#[doc = "Register `SPI_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `spi_fastrd_mode` reader - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] -pub type SPI_FASTRD_MODE_R = crate::BitReader; -#[doc = "Field `spi_fastrd_mode` writer - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] -pub type SPI_FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dout_mode` reader - In the read operations, \"read-data\" phase apply 2 signals"] -pub type SPI_DOUT_MODE_R = crate::BitReader; -#[doc = "Field `spi_dout_mode` writer - In the read operations, \"read-data\" phase apply 2 signals"] -pub type SPI_DOUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `res_and_res` reader - 'Res and res'?"] -pub type RES_AND_RES_R = crate::BitReader; -#[doc = "Field `res_and_res` writer - 'Res and res'?"] -pub type RES_AND_RES_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sst_aai` reader - SST_AAI?"] -pub type SST_AAI_R = crate::BitReader; -#[doc = "Field `sst_aai` writer - SST_AAI?"] -pub type SST_AAI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `enable_ahb` reader - Enable AHB"] -pub type ENABLE_AHB_R = crate::BitReader; -#[doc = "Field `enable_ahb` writer - Enable AHB"] -pub type ENABLE_AHB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `hold_mode` reader - Hold mode"] -pub type HOLD_MODE_R = crate::BitReader; -#[doc = "Field `hold_mode` writer - Hold mode"] -pub type HOLD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `share_but` reader - Share bus"] -pub type SHARE_BUT_R = crate::BitReader; -#[doc = "Field `share_but` writer - Share bus"] -pub type SHARE_BUT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_qout_mode` reader - In the read operations, \"read-data\" phase apply 4 signals"] -pub type SPI_QOUT_MODE_R = crate::BitReader; -#[doc = "Field `spi_qout_mode` writer - In the read operations, \"read-data\" phase apply 4 signals"] -pub type SPI_QOUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `wp_reg` reader - Write protect?"] -pub type WP_REG_R = crate::BitReader; -#[doc = "Field `wp_reg` writer - Write protect?"] -pub type WP_REG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `two_byte_status` reader - Enable two byte status"] -pub type TWO_BYTE_STATUS_R = crate::BitReader; -#[doc = "Field `two_byte_status` writer - Enable two byte status"] -pub type TWO_BYTE_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_dio_mode` reader - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_DIO_MODE_R = crate::BitReader; -#[doc = "Field `spi_dio_mode` writer - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_DIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_qio_mode` reader - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_QIO_MODE_R = crate::BitReader; -#[doc = "Field `spi_qio_mode` writer - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_QIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_rd_bit_order` reader - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] -pub type SPI_RD_BIT_ORDER_R = crate::BitReader; -#[doc = "Field `spi_rd_bit_order` writer - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] -pub type SPI_RD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_wr_bit_order` reader - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] -pub type SPI_WR_BIT_ORDER_R = crate::BitReader; -#[doc = "Field `spi_wr_bit_order` writer - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] -pub type SPI_WR_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 13 - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] - #[inline(always)] - pub fn spi_fastrd_mode(&self) -> SPI_FASTRD_MODE_R { - SPI_FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - In the read operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_dout_mode(&self) -> SPI_DOUT_MODE_R { - SPI_DOUT_MODE_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - 'Res and res'?"] - #[inline(always)] - pub fn res_and_res(&self) -> RES_AND_RES_R { - RES_AND_RES_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - SST_AAI?"] - #[inline(always)] - pub fn sst_aai(&self) -> SST_AAI_R { - SST_AAI_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 17 - Enable AHB"] - #[inline(always)] - pub fn enable_ahb(&self) -> ENABLE_AHB_R { - ENABLE_AHB_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Hold mode"] - #[inline(always)] - pub fn hold_mode(&self) -> HOLD_MODE_R { - HOLD_MODE_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Share bus"] - #[inline(always)] - pub fn share_but(&self) -> SHARE_BUT_R { - SHARE_BUT_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - In the read operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_qout_mode(&self) -> SPI_QOUT_MODE_R { - SPI_QOUT_MODE_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Write protect?"] - #[inline(always)] - pub fn wp_reg(&self) -> WP_REG_R { - WP_REG_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Enable two byte status"] - #[inline(always)] - pub fn two_byte_status(&self) -> TWO_BYTE_STATUS_R { - TWO_BYTE_STATUS_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_dio_mode(&self) -> SPI_DIO_MODE_R { - SPI_DIO_MODE_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_qio_mode(&self) -> SPI_QIO_MODE_R { - SPI_QIO_MODE_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] - #[inline(always)] - pub fn spi_rd_bit_order(&self) -> SPI_RD_BIT_ORDER_R { - SPI_RD_BIT_ORDER_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] - #[inline(always)] - pub fn spi_wr_bit_order(&self) -> SPI_WR_BIT_ORDER_R { - SPI_WR_BIT_ORDER_R::new(((self.bits >> 26) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL") - .field( - "spi_wr_bit_order", - &format_args!("{}", self.spi_wr_bit_order().bit()), - ) - .field( - "spi_rd_bit_order", - &format_args!("{}", self.spi_rd_bit_order().bit()), - ) - .field( - "spi_qio_mode", - &format_args!("{}", self.spi_qio_mode().bit()), - ) - .field( - "spi_dio_mode", - &format_args!("{}", self.spi_dio_mode().bit()), - ) - .field( - "spi_qout_mode", - &format_args!("{}", self.spi_qout_mode().bit()), - ) - .field( - "spi_dout_mode", - &format_args!("{}", self.spi_dout_mode().bit()), - ) - .field( - "spi_fastrd_mode", - &format_args!("{}", self.spi_fastrd_mode().bit()), - ) - .field( - "two_byte_status", - &format_args!("{}", self.two_byte_status().bit()), - ) - .field("wp_reg", &format_args!("{}", self.wp_reg().bit())) - .field("share_but", &format_args!("{}", self.share_but().bit())) - .field("hold_mode", &format_args!("{}", self.hold_mode().bit())) - .field("enable_ahb", &format_args!("{}", self.enable_ahb().bit())) - .field("sst_aai", &format_args!("{}", self.sst_aai().bit())) - .field("res_and_res", &format_args!("{}", self.res_and_res().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 13 - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode"] - #[inline(always)] - #[must_use] - pub fn spi_fastrd_mode(&mut self) -> SPI_FASTRD_MODE_W { - SPI_FASTRD_MODE_W::new(self, 13) - } - #[doc = "Bit 14 - In the read operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_dout_mode(&mut self) -> SPI_DOUT_MODE_W { - SPI_DOUT_MODE_W::new(self, 14) - } - #[doc = "Bit 15 - 'Res and res'?"] - #[inline(always)] - #[must_use] - pub fn res_and_res(&mut self) -> RES_AND_RES_W { - RES_AND_RES_W::new(self, 15) - } - #[doc = "Bit 16 - SST_AAI?"] - #[inline(always)] - #[must_use] - pub fn sst_aai(&mut self) -> SST_AAI_W { - SST_AAI_W::new(self, 16) - } - #[doc = "Bit 17 - Enable AHB"] - #[inline(always)] - #[must_use] - pub fn enable_ahb(&mut self) -> ENABLE_AHB_W { - ENABLE_AHB_W::new(self, 17) - } - #[doc = "Bit 18 - Hold mode"] - #[inline(always)] - #[must_use] - pub fn hold_mode(&mut self) -> HOLD_MODE_W { - HOLD_MODE_W::new(self, 18) - } - #[doc = "Bit 19 - Share bus"] - #[inline(always)] - #[must_use] - pub fn share_but(&mut self) -> SHARE_BUT_W { - SHARE_BUT_W::new(self, 19) - } - #[doc = "Bit 20 - In the read operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_qout_mode(&mut self) -> SPI_QOUT_MODE_W { - SPI_QOUT_MODE_W::new(self, 20) - } - #[doc = "Bit 21 - Write protect?"] - #[inline(always)] - #[must_use] - pub fn wp_reg(&mut self) -> WP_REG_W { - WP_REG_W::new(self, 21) - } - #[doc = "Bit 22 - Enable two byte status"] - #[inline(always)] - #[must_use] - pub fn two_byte_status(&mut self) -> TWO_BYTE_STATUS_W { - TWO_BYTE_STATUS_W::new(self, 22) - } - #[doc = "Bit 23 - In the read operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_dio_mode(&mut self) -> SPI_DIO_MODE_W { - SPI_DIO_MODE_W::new(self, 23) - } - #[doc = "Bit 24 - In the read operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_qio_mode(&mut self) -> SPI_QIO_MODE_W { - SPI_QIO_MODE_W::new(self, 24) - } - #[doc = "Bit 25 - In \"read-data\" (MISO) phase, 1: LSB first; 0: MSB first"] - #[inline(always)] - #[must_use] - pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W { - SPI_RD_BIT_ORDER_W::new(self, 25) - } - #[doc = "Bit 26 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: LSB first; 0: MSB first"] - #[inline(always)] - #[must_use] - pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W { - SPI_WR_BIT_ORDER_W::new(self, 26) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "SPI_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL_SPEC; -impl crate::RegisterSpec for SPI_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL to value 0"] -impl crate::Resettable for SPI_CTRL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ctrl1.rs b/esp8266/src/spi1/spi_ctrl1.rs deleted file mode 100644 index a910a57e9e..0000000000 --- a/esp8266/src/spi1/spi_ctrl1.rs +++ /dev/null @@ -1,95 +0,0 @@ -#[doc = "Register `SPI_CTRL1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL1` writer"] -pub type W = crate::W; -#[doc = "Field `status` reader - In the slave mode, it is the status for master to read out."] -pub type STATUS_R = crate::FieldReader; -#[doc = "Field `status` writer - In the slave mode, it is the status for master to read out."] -pub type STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `wb_mode` reader - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] -pub type WB_MODE_R = crate::FieldReader; -#[doc = "Field `wb_mode` writer - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] -pub type WB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `status_ext` reader - In the slave mode,it is the status for master to read out."] -pub type STATUS_EXT_R = crate::FieldReader; -#[doc = "Field `status_ext` writer - In the slave mode,it is the status for master to read out."] -pub type STATUS_EXT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."] - #[inline(always)] - pub fn status(&self) -> STATUS_R { - STATUS_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 16:23 - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] - #[inline(always)] - pub fn wb_mode(&self) -> WB_MODE_R { - WB_MODE_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In the slave mode,it is the status for master to read out."] - #[inline(always)] - pub fn status_ext(&self) -> STATUS_EXT_R { - STATUS_EXT_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL1") - .field("status", &format_args!("{}", self.status().bits())) - .field("wb_mode", &format_args!("{}", self.wb_mode().bits())) - .field("status_ext", &format_args!("{}", self.status_ext().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."] - #[inline(always)] - #[must_use] - pub fn status(&mut self) -> STATUS_W { - STATUS_W::new(self, 0) - } - #[doc = "Bits 16:23 - Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit."] - #[inline(always)] - #[must_use] - pub fn wb_mode(&mut self) -> WB_MODE_W { - WB_MODE_W::new(self, 16) - } - #[doc = "Bits 24:31 - In the slave mode,it is the status for master to read out."] - #[inline(always)] - #[must_use] - pub fn status_ext(&mut self) -> STATUS_EXT_W { - STATUS_EXT_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL1_SPEC; -impl crate::RegisterSpec for SPI_CTRL1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl1::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl1::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL1 to value 0"] -impl crate::Resettable for SPI_CTRL1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ctrl2.rs b/esp8266/src/spi1/spi_ctrl2.rs deleted file mode 100644 index de0f6e05cc..0000000000 --- a/esp8266/src/spi1/spi_ctrl2.rs +++ /dev/null @@ -1,161 +0,0 @@ -#[doc = "Register `SPI_CTRL2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_CTRL2` writer"] -pub type W = crate::W; -#[doc = "Field `spi_miso_delay_mode` reader - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MISO_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_miso_delay_mode` writer - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MISO_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_miso_delay_num` reader - MISO signals are delayed by 80MHz clock cycles"] -pub type SPI_MISO_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_miso_delay_num` writer - MISO signals are delayed by 80MHz clock cycles"] -pub type SPI_MISO_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `spi_mosi_delay_mode` reader - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MOSI_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_mosi_delay_mode` writer - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_MOSI_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_mosi_delay_num` reader - MOSI signals are delayed by 80MHz clock cycles"] -pub type SPI_MOSI_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_mosi_delay_num` writer - MOSI signals are delayed by 80MHz clock cycles"] -pub type SPI_MOSI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `spi_cs_delay_mode` reader - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_CS_DELAY_MODE_R = crate::FieldReader; -#[doc = "Field `spi_cs_delay_mode` writer - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] -pub type SPI_CS_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `spi_cs_delay_num` reader - spi_cs signal is delayed by 80MHz clock cycles"] -pub type SPI_CS_DELAY_NUM_R = crate::FieldReader; -#[doc = "Field `spi_cs_delay_num` writer - spi_cs signal is delayed by 80MHz clock cycles"] -pub type SPI_CS_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_miso_delay_mode(&self) -> SPI_MISO_DELAY_MODE_R { - SPI_MISO_DELAY_MODE_R::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_miso_delay_num(&self) -> SPI_MISO_DELAY_NUM_R { - SPI_MISO_DELAY_NUM_R::new(((self.bits >> 18) & 7) as u8) - } - #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_mosi_delay_mode(&self) -> SPI_MOSI_DELAY_MODE_R { - SPI_MOSI_DELAY_MODE_R::new(((self.bits >> 21) & 3) as u8) - } - #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_mosi_delay_num(&self) -> SPI_MOSI_DELAY_NUM_R { - SPI_MOSI_DELAY_NUM_R::new(((self.bits >> 23) & 7) as u8) - } - #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - pub fn spi_cs_delay_mode(&self) -> SPI_CS_DELAY_MODE_R { - SPI_CS_DELAY_MODE_R::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - pub fn spi_cs_delay_num(&self) -> SPI_CS_DELAY_NUM_R { - SPI_CS_DELAY_NUM_R::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_CTRL2") - .field( - "spi_cs_delay_num", - &format_args!("{}", self.spi_cs_delay_num().bits()), - ) - .field( - "spi_cs_delay_mode", - &format_args!("{}", self.spi_cs_delay_mode().bits()), - ) - .field( - "spi_mosi_delay_num", - &format_args!("{}", self.spi_mosi_delay_num().bits()), - ) - .field( - "spi_mosi_delay_mode", - &format_args!("{}", self.spi_mosi_delay_mode().bits()), - ) - .field( - "spi_miso_delay_num", - &format_args!("{}", self.spi_miso_delay_num().bits()), - ) - .field( - "spi_miso_delay_mode", - &format_args!("{}", self.spi_miso_delay_mode().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_miso_delay_mode(&mut self) -> SPI_MISO_DELAY_MODE_W { - SPI_MISO_DELAY_MODE_W::new(self, 16) - } - #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_miso_delay_num(&mut self) -> SPI_MISO_DELAY_NUM_W { - SPI_MISO_DELAY_NUM_W::new(self, 18) - } - #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_mosi_delay_mode(&mut self) -> SPI_MOSI_DELAY_MODE_W { - SPI_MOSI_DELAY_MODE_W::new(self, 21) - } - #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_mosi_delay_num(&mut self) -> SPI_MOSI_DELAY_NUM_W { - SPI_MOSI_DELAY_NUM_W::new(self, 23) - } - #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"] - #[inline(always)] - #[must_use] - pub fn spi_cs_delay_mode(&mut self) -> SPI_CS_DELAY_MODE_W { - SPI_CS_DELAY_MODE_W::new(self, 26) - } - #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"] - #[inline(always)] - #[must_use] - pub fn spi_cs_delay_num(&mut self) -> SPI_CS_DELAY_NUM_W { - SPI_CS_DELAY_NUM_W::new(self, 28) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "spi_cs signal is delayed by 80MHz clock cycles\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_CTRL2_SPEC; -impl crate::RegisterSpec for SPI_CTRL2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ctrl2::R`](R) reader structure"] -impl crate::Readable for SPI_CTRL2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ctrl2::W`](W) writer structure"] -impl crate::Writable for SPI_CTRL2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_CTRL2 to value 0"] -impl crate::Resettable for SPI_CTRL2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ext0.rs b/esp8266/src/spi1/spi_ext0.rs deleted file mode 100644 index ed47678fee..0000000000 --- a/esp8266/src/spi1/spi_ext0.rs +++ /dev/null @@ -1,95 +0,0 @@ -#[doc = "Register `SPI_EXT0` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT0` writer"] -pub type W = crate::W; -#[doc = "Field `pp_time` reader - "] -pub type PP_TIME_R = crate::FieldReader; -#[doc = "Field `pp_time` writer - "] -pub type PP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `pp_shift` reader - "] -pub type PP_SHIFT_R = crate::FieldReader; -#[doc = "Field `pp_shift` writer - "] -pub type PP_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `pp_enable` reader - "] -pub type PP_ENABLE_R = crate::BitReader; -#[doc = "Field `pp_enable` writer - "] -pub type PP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn pp_time(&self) -> PP_TIME_R { - PP_TIME_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:19"] - #[inline(always)] - pub fn pp_shift(&self) -> PP_SHIFT_R { - PP_SHIFT_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn pp_enable(&self) -> PP_ENABLE_R { - PP_ENABLE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT0") - .field("pp_enable", &format_args!("{}", self.pp_enable().bit())) - .field("pp_shift", &format_args!("{}", self.pp_shift().bits())) - .field("pp_time", &format_args!("{}", self.pp_time().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn pp_time(&mut self) -> PP_TIME_W { - PP_TIME_W::new(self, 0) - } - #[doc = "Bits 16:19"] - #[inline(always)] - #[must_use] - pub fn pp_shift(&mut self) -> PP_SHIFT_W { - PP_SHIFT_W::new(self, 16) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn pp_enable(&mut self) -> PP_ENABLE_W { - PP_ENABLE_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT0_SPEC; -impl crate::RegisterSpec for SPI_EXT0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext0::R`](R) reader structure"] -impl crate::Readable for SPI_EXT0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext0::W`](W) writer structure"] -impl crate::Writable for SPI_EXT0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT0 to value 0"] -impl crate::Resettable for SPI_EXT0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ext1.rs b/esp8266/src/spi1/spi_ext1.rs deleted file mode 100644 index 7016f9451a..0000000000 --- a/esp8266/src/spi1/spi_ext1.rs +++ /dev/null @@ -1,101 +0,0 @@ -#[doc = "Register `SPI_EXT1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT1` writer"] -pub type W = crate::W; -#[doc = "Field `erase_time` reader - "] -pub type ERASE_TIME_R = crate::FieldReader; -#[doc = "Field `erase_time` writer - "] -pub type ERASE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; -#[doc = "Field `erase_shift` reader - "] -pub type ERASE_SHIFT_R = crate::FieldReader; -#[doc = "Field `erase_shift` writer - "] -pub type ERASE_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `erase_enable` reader - "] -pub type ERASE_ENABLE_R = crate::BitReader; -#[doc = "Field `erase_enable` writer - "] -pub type ERASE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:11"] - #[inline(always)] - pub fn erase_time(&self) -> ERASE_TIME_R { - ERASE_TIME_R::new((self.bits & 0x0fff) as u16) - } - #[doc = "Bits 16:19"] - #[inline(always)] - pub fn erase_shift(&self) -> ERASE_SHIFT_R { - ERASE_SHIFT_R::new(((self.bits >> 16) & 0x0f) as u8) - } - #[doc = "Bit 31"] - #[inline(always)] - pub fn erase_enable(&self) -> ERASE_ENABLE_R { - ERASE_ENABLE_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT1") - .field( - "erase_enable", - &format_args!("{}", self.erase_enable().bit()), - ) - .field( - "erase_shift", - &format_args!("{}", self.erase_shift().bits()), - ) - .field("erase_time", &format_args!("{}", self.erase_time().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:11"] - #[inline(always)] - #[must_use] - pub fn erase_time(&mut self) -> ERASE_TIME_W { - ERASE_TIME_W::new(self, 0) - } - #[doc = "Bits 16:19"] - #[inline(always)] - #[must_use] - pub fn erase_shift(&mut self) -> ERASE_SHIFT_W { - ERASE_SHIFT_W::new(self, 16) - } - #[doc = "Bit 31"] - #[inline(always)] - #[must_use] - pub fn erase_enable(&mut self) -> ERASE_ENABLE_W { - ERASE_ENABLE_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT1_SPEC; -impl crate::RegisterSpec for SPI_EXT1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext1::R`](R) reader structure"] -impl crate::Readable for SPI_EXT1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext1::W`](W) writer structure"] -impl crate::Writable for SPI_EXT1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT1 to value 0"] -impl crate::Resettable for SPI_EXT1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ext2.rs b/esp8266/src/spi1/spi_ext2.rs deleted file mode 100644 index c12c0070da..0000000000 --- a/esp8266/src/spi1/spi_ext2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_EXT2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT2` writer"] -pub type W = crate::W; -#[doc = "Field `st` reader - "] -pub type ST_R = crate::FieldReader; -#[doc = "Field `st` writer - "] -pub type ST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -impl R { - #[doc = "Bits 0:2"] - #[inline(always)] - pub fn st(&self) -> ST_R { - ST_R::new((self.bits & 7) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT2") - .field("st", &format_args!("{}", self.st().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:2"] - #[inline(always)] - #[must_use] - pub fn st(&mut self) -> ST_W { - ST_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT2_SPEC; -impl crate::RegisterSpec for SPI_EXT2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext2::R`](R) reader structure"] -impl crate::Readable for SPI_EXT2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext2::W`](W) writer structure"] -impl crate::Writable for SPI_EXT2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT2 to value 0"] -impl crate::Resettable for SPI_EXT2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_ext3.rs b/esp8266/src/spi1/spi_ext3.rs deleted file mode 100644 index bce9543c34..0000000000 --- a/esp8266/src/spi1/spi_ext3.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_EXT3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_EXT3` writer"] -pub type W = crate::W; -#[doc = "Field `reg_int_hold_ena` reader - This register is for two SPI masters to share the same cs, clock and data signals."] -pub type REG_INT_HOLD_ENA_R = crate::FieldReader; -#[doc = "Field `reg_int_hold_ena` writer - This register is for two SPI masters to share the same cs, clock and data signals."] -pub type REG_INT_HOLD_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -impl R { - #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - pub fn reg_int_hold_ena(&self) -> REG_INT_HOLD_ENA_R { - REG_INT_HOLD_ENA_R::new((self.bits & 3) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_EXT3") - .field( - "reg_int_hold_ena", - &format_args!("{}", self.reg_int_hold_ena().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs, clock and data signals."] - #[inline(always)] - #[must_use] - pub fn reg_int_hold_ena(&mut self) -> REG_INT_HOLD_ENA_W { - REG_INT_HOLD_ENA_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "This register is for two SPI masters to share the same cs, clock and data signals.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ext3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ext3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_EXT3_SPEC; -impl crate::RegisterSpec for SPI_EXT3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_ext3::R`](R) reader structure"] -impl crate::Readable for SPI_EXT3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_ext3::W`](W) writer structure"] -impl crate::Writable for SPI_EXT3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_EXT3 to value 0"] -impl crate::Resettable for SPI_EXT3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_pin.rs b/esp8266/src/spi1/spi_pin.rs deleted file mode 100644 index e36a780898..0000000000 --- a/esp8266/src/spi1/spi_pin.rs +++ /dev/null @@ -1,114 +0,0 @@ -#[doc = "Register `SPI_PIN` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_PIN` writer"] -pub type W = crate::W; -#[doc = "Field `spi_cs0_dis` reader - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] -pub type SPI_CS0_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs0_dis` writer - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] -pub type SPI_CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs1_dis` reader - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] -pub type SPI_CS1_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs1_dis` writer - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] -pub type SPI_CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs2_dis` reader - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub type SPI_CS2_DIS_R = crate::BitReader; -#[doc = "Field `spi_cs2_dis` writer - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] -pub type SPI_CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_idle_edge` reader - In the master mode, 1: high when idle; 0: low when idle"] -pub type SPI_IDLE_EDGE_R = crate::BitReader; -#[doc = "Field `spi_idle_edge` writer - In the master mode, 1: high when idle; 0: low when idle"] -pub type SPI_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] - #[inline(always)] - pub fn spi_cs0_dis(&self) -> SPI_CS0_DIS_R { - SPI_CS0_DIS_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] - #[inline(always)] - pub fn spi_cs1_dis(&self) -> SPI_CS1_DIS_R { - SPI_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - pub fn spi_cs2_dis(&self) -> SPI_CS2_DIS_R { - SPI_CS2_DIS_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"] - #[inline(always)] - pub fn spi_idle_edge(&self) -> SPI_IDLE_EDGE_R { - SPI_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_PIN") - .field("spi_cs2_dis", &format_args!("{}", self.spi_cs2_dis().bit())) - .field("spi_cs1_dis", &format_args!("{}", self.spi_cs1_dis().bit())) - .field("spi_cs0_dis", &format_args!("{}", self.spi_cs0_dis().bit())) - .field( - "spi_idle_edge", - &format_args!("{}", self.spi_idle_edge().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W { - SPI_CS0_DIS_W::new(self, 0) - } - #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W { - SPI_CS1_DIS_W::new(self, 1) - } - #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"] - #[inline(always)] - #[must_use] - pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W { - SPI_CS2_DIS_W::new(self, 2) - } - #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"] - #[inline(always)] - #[must_use] - pub fn spi_idle_edge(&mut self) -> SPI_IDLE_EDGE_W { - SPI_IDLE_EDGE_W::new(self, 29) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "1: disable CS2; 0: spi_cs signal is from/to CS2 pin\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_pin::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_pin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_PIN_SPEC; -impl crate::RegisterSpec for SPI_PIN_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_pin::R`](R) reader structure"] -impl crate::Readable for SPI_PIN_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_pin::W`](W) writer structure"] -impl crate::Writable for SPI_PIN_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_PIN to value 0"] -impl crate::Resettable for SPI_PIN_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_rd_status.rs b/esp8266/src/spi1/spi_rd_status.rs deleted file mode 100644 index ad991c8e13..0000000000 --- a/esp8266/src/spi1/spi_rd_status.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_RD_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_RD_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rd_status` reader - In the slave mode, this register are the status register for the master to read out."] -pub type SLV_RD_STATUS_R = crate::FieldReader; -#[doc = "Field `slv_rd_status` writer - In the slave mode, this register are the status register for the master to read out."] -pub type SLV_RD_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - pub fn slv_rd_status(&self) -> SLV_RD_STATUS_R { - SLV_RD_STATUS_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_RD_STATUS") - .field( - "slv_rd_status", - &format_args!("{}", self.slv_rd_status().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to read out."] - #[inline(always)] - #[must_use] - pub fn slv_rd_status(&mut self) -> SLV_RD_STATUS_W { - SLV_RD_STATUS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, this register are the status register for the master to read out.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_rd_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_rd_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_RD_STATUS_SPEC; -impl crate::RegisterSpec for SPI_RD_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_rd_status::R`](R) reader structure"] -impl crate::Readable for SPI_RD_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_rd_status::W`](W) writer structure"] -impl crate::Writable for SPI_RD_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_RD_STATUS to value 0"] -impl crate::Resettable for SPI_RD_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_slave.rs b/esp8266/src/spi1/spi_slave.rs deleted file mode 100644 index 4a1763cb6a..0000000000 --- a/esp8266/src/spi1/spi_slave.rs +++ /dev/null @@ -1,356 +0,0 @@ -#[doc = "Register `SPI_SLAVE` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rd_buf_done` reader - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] -pub type SLV_RD_BUF_DONE_R = crate::BitReader; -#[doc = "Field `slv_rd_buf_done` writer - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] -pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_buf_done` reader - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] -pub type SLV_WR_BUF_DONE_R = crate::BitReader; -#[doc = "Field `slv_wr_buf_done` writer - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] -pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_rd_sta_done` reader - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] -pub type SLV_RD_STA_DONE_R = crate::BitReader; -#[doc = "Field `slv_rd_sta_done` writer - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] -pub type SLV_RD_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_sta_done` reader - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] -pub type SLV_WR_STA_DONE_R = crate::BitReader; -#[doc = "Field `slv_wr_sta_done` writer - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] -pub type SLV_WR_STA_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_trans_done` reader - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] -pub type SPI_TRANS_DONE_R = crate::BitReader; -#[doc = "Field `spi_trans_done` writer - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] -pub type SPI_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_int_en` reader - Interrupt enable bits for the below 5 sources"] -pub type SPI_INT_EN_R = crate::FieldReader; -#[doc = "Field `spi_int_en` writer - Interrupt enable bits for the below 5 sources"] -pub type SPI_INT_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `interrupt_rb_enable` reader - Enable buffer read interrupts"] -pub type INTERRUPT_RB_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_rb_enable` writer - Enable buffer read interrupts"] -pub type INTERRUPT_RB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_wb_enable` reader - Enable buffer write interrupts"] -pub type INTERRUPT_WB_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_wb_enable` writer - Enable buffer write interrupts"] -pub type INTERRUPT_WB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_rs_enable` reader - Enable status read interrupts"] -pub type INTERRUPT_RS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_rs_enable` writer - Enable status read interrupts"] -pub type INTERRUPT_RS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_ws_enable` reader - Enable status write interrupts"] -pub type INTERRUPT_WS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_ws_enable` writer - Enable status write interrupts"] -pub type INTERRUPT_WS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `interrupt_trans_enable` reader - Enable TRANS interrupts"] -pub type INTERRUPT_TRANS_ENABLE_R = crate::BitReader; -#[doc = "Field `interrupt_trans_enable` writer - Enable TRANS interrupts"] -pub type INTERRUPT_TRANS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_trans_cnt` reader - The operations counter in both the master mode and the slave mode."] -pub type SPI_TRANS_CNT_R = crate::FieldReader; -#[doc = "Field `slv_cmd_define` reader - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] -pub type SLV_CMD_DEFINE_R = crate::BitReader; -#[doc = "Field `slv_cmd_define` writer - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] -pub type SLV_CMD_DEFINE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sta_enable` reader - Enable read/write buffer"] -pub type STA_ENABLE_R = crate::BitReader; -#[doc = "Field `sta_enable` writer - Enable read/write buffer"] -pub type STA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_buffer_enable` reader - Enable read/write buffer"] -pub type SPI_BUFFER_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_buffer_enable` writer - Enable read/write buffer"] -pub type SPI_BUFFER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_slave_mode` reader - 1: slave mode, 0: master mode."] -pub type SPI_SLAVE_MODE_R = crate::BitReader; -#[doc = "Field `spi_slave_mode` writer - 1: slave mode, 0: master mode."] -pub type SPI_SLAVE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_sync_reset` reader - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub type SPI_SYNC_RESET_R = crate::BitReader; -#[doc = "Field `spi_sync_reset` writer - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] -pub type SPI_SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] - #[inline(always)] - pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R { - SLV_RD_BUF_DONE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] - #[inline(always)] - pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R { - SLV_WR_BUF_DONE_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] - #[inline(always)] - pub fn slv_rd_sta_done(&self) -> SLV_RD_STA_DONE_R { - SLV_RD_STA_DONE_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] - #[inline(always)] - pub fn slv_wr_sta_done(&self) -> SLV_WR_STA_DONE_R { - SLV_WR_STA_DONE_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] - #[inline(always)] - pub fn spi_trans_done(&self) -> SPI_TRANS_DONE_R { - SPI_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bits 5:9 - Interrupt enable bits for the below 5 sources"] - #[inline(always)] - pub fn spi_int_en(&self) -> SPI_INT_EN_R { - SPI_INT_EN_R::new(((self.bits >> 5) & 0x1f) as u8) - } - #[doc = "Bit 5 - Enable buffer read interrupts"] - #[inline(always)] - pub fn interrupt_rb_enable(&self) -> INTERRUPT_RB_ENABLE_R { - INTERRUPT_RB_ENABLE_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - Enable buffer write interrupts"] - #[inline(always)] - pub fn interrupt_wb_enable(&self) -> INTERRUPT_WB_ENABLE_R { - INTERRUPT_WB_ENABLE_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Enable status read interrupts"] - #[inline(always)] - pub fn interrupt_rs_enable(&self) -> INTERRUPT_RS_ENABLE_R { - INTERRUPT_RS_ENABLE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - Enable status write interrupts"] - #[inline(always)] - pub fn interrupt_ws_enable(&self) -> INTERRUPT_WS_ENABLE_R { - INTERRUPT_WS_ENABLE_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Enable TRANS interrupts"] - #[inline(always)] - pub fn interrupt_trans_enable(&self) -> INTERRUPT_TRANS_ENABLE_R { - INTERRUPT_TRANS_ENABLE_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bits 23:26 - The operations counter in both the master mode and the slave mode."] - #[inline(always)] - pub fn spi_trans_cnt(&self) -> SPI_TRANS_CNT_R { - SPI_TRANS_CNT_R::new(((self.bits >> 23) & 0x0f) as u8) - } - #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] - #[inline(always)] - pub fn slv_cmd_define(&self) -> SLV_CMD_DEFINE_R { - SLV_CMD_DEFINE_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - Enable read/write buffer"] - #[inline(always)] - pub fn sta_enable(&self) -> STA_ENABLE_R { - STA_ENABLE_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - Enable read/write buffer"] - #[inline(always)] - pub fn spi_buffer_enable(&self) -> SPI_BUFFER_ENABLE_R { - SPI_BUFFER_ENABLE_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - 1: slave mode, 0: master mode."] - #[inline(always)] - pub fn spi_slave_mode(&self) -> SPI_SLAVE_MODE_R { - SPI_SLAVE_MODE_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - pub fn spi_sync_reset(&self) -> SPI_SYNC_RESET_R { - SPI_SYNC_RESET_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE") - .field( - "spi_sync_reset", - &format_args!("{}", self.spi_sync_reset().bit()), - ) - .field( - "spi_slave_mode", - &format_args!("{}", self.spi_slave_mode().bit()), - ) - .field( - "slv_cmd_define", - &format_args!("{}", self.slv_cmd_define().bit()), - ) - .field( - "spi_trans_cnt", - &format_args!("{}", self.spi_trans_cnt().bits()), - ) - .field("spi_int_en", &format_args!("{}", self.spi_int_en().bits())) - .field( - "spi_trans_done", - &format_args!("{}", self.spi_trans_done().bit()), - ) - .field( - "slv_wr_sta_done", - &format_args!("{}", self.slv_wr_sta_done().bit()), - ) - .field( - "slv_rd_sta_done", - &format_args!("{}", self.slv_rd_sta_done().bit()), - ) - .field( - "slv_wr_buf_done", - &format_args!("{}", self.slv_wr_buf_done().bit()), - ) - .field( - "slv_rd_buf_done", - &format_args!("{}", self.slv_rd_buf_done().bit()), - ) - .field( - "spi_buffer_enable", - &format_args!("{}", self.spi_buffer_enable().bit()), - ) - .field("sta_enable", &format_args!("{}", self.sta_enable().bit())) - .field( - "interrupt_trans_enable", - &format_args!("{}", self.interrupt_trans_enable().bit()), - ) - .field( - "interrupt_ws_enable", - &format_args!("{}", self.interrupt_ws_enable().bit()), - ) - .field( - "interrupt_rs_enable", - &format_args!("{}", self.interrupt_rs_enable().bit()), - ) - .field( - "interrupt_wb_enable", - &format_args!("{}", self.interrupt_wb_enable().bit()), - ) - .field( - "interrupt_rb_enable", - &format_args!("{}", self.interrupt_rb_enable().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - The interrupt raw bit for the completement of \"read-buffer\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W { - SLV_RD_BUF_DONE_W::new(self, 0) - } - #[doc = "Bit 1 - The interrupt raw bit for the completement of \"write-buffer\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W { - SLV_WR_BUF_DONE_W::new(self, 1) - } - #[doc = "Bit 2 - The interrupt raw bit for the completement of \"read-status\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_rd_sta_done(&mut self) -> SLV_RD_STA_DONE_W { - SLV_RD_STA_DONE_W::new(self, 2) - } - #[doc = "Bit 3 - The interrupt raw bit for the completement of \"write-status\" operation in the slave mode."] - #[inline(always)] - #[must_use] - pub fn slv_wr_sta_done(&mut self) -> SLV_WR_STA_DONE_W { - SLV_WR_STA_DONE_W::new(self, 3) - } - #[doc = "Bit 4 - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode."] - #[inline(always)] - #[must_use] - pub fn spi_trans_done(&mut self) -> SPI_TRANS_DONE_W { - SPI_TRANS_DONE_W::new(self, 4) - } - #[doc = "Bits 5:9 - Interrupt enable bits for the below 5 sources"] - #[inline(always)] - #[must_use] - pub fn spi_int_en(&mut self) -> SPI_INT_EN_W { - SPI_INT_EN_W::new(self, 5) - } - #[doc = "Bit 5 - Enable buffer read interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_rb_enable(&mut self) -> INTERRUPT_RB_ENABLE_W { - INTERRUPT_RB_ENABLE_W::new(self, 5) - } - #[doc = "Bit 6 - Enable buffer write interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_wb_enable(&mut self) -> INTERRUPT_WB_ENABLE_W { - INTERRUPT_WB_ENABLE_W::new(self, 6) - } - #[doc = "Bit 7 - Enable status read interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_rs_enable(&mut self) -> INTERRUPT_RS_ENABLE_W { - INTERRUPT_RS_ENABLE_W::new(self, 7) - } - #[doc = "Bit 8 - Enable status write interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_ws_enable(&mut self) -> INTERRUPT_WS_ENABLE_W { - INTERRUPT_WS_ENABLE_W::new(self, 8) - } - #[doc = "Bit 9 - Enable TRANS interrupts"] - #[inline(always)] - #[must_use] - pub fn interrupt_trans_enable(&mut self) -> INTERRUPT_TRANS_ENABLE_W { - INTERRUPT_TRANS_ENABLE_W::new(self, 9) - } - #[doc = "Bit 27 - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: \"write-status\"; 4: \"read-status\"; 2: \"write-buffer\" and 3: \"read-buffer\"."] - #[inline(always)] - #[must_use] - pub fn slv_cmd_define(&mut self) -> SLV_CMD_DEFINE_W { - SLV_CMD_DEFINE_W::new(self, 27) - } - #[doc = "Bit 28 - Enable read/write buffer"] - #[inline(always)] - #[must_use] - pub fn sta_enable(&mut self) -> STA_ENABLE_W { - STA_ENABLE_W::new(self, 28) - } - #[doc = "Bit 29 - Enable read/write buffer"] - #[inline(always)] - #[must_use] - pub fn spi_buffer_enable(&mut self) -> SPI_BUFFER_ENABLE_W { - SPI_BUFFER_ENABLE_W::new(self, 29) - } - #[doc = "Bit 30 - 1: slave mode, 0: master mode."] - #[inline(always)] - #[must_use] - pub fn spi_slave_mode(&mut self) -> SPI_SLAVE_MODE_W { - SPI_SLAVE_MODE_W::new(self, 30) - } - #[doc = "Bit 31 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware."] - #[inline(always)] - #[must_use] - pub fn spi_sync_reset(&mut self) -> SPI_SYNC_RESET_W { - SPI_SYNC_RESET_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "It is the synchronous reset signal of the module. This bit is self-cleared by hardware.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE_SPEC; -impl crate::RegisterSpec for SPI_SLAVE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE to value 0"] -impl crate::Resettable for SPI_SLAVE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_slave1.rs b/esp8266/src/spi1/spi_slave1.rs deleted file mode 100644 index cd774580b3..0000000000 --- a/esp8266/src/spi1/spi_slave1.rs +++ /dev/null @@ -1,237 +0,0 @@ -#[doc = "Register `SPI_SLAVE1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE1` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdbuf_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] -pub type SLV_RDBUF_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_rdbuf_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] -pub type SLV_RDBUF_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wrbuf_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] -pub type SLV_WRBUF_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_wrbuf_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] -pub type SLV_WRBUF_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_rdsta_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] -pub type SLV_RDSTA_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_rdsta_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] -pub type SLV_RDSTA_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wrsta_dummy_en` reader - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] -pub type SLV_WRSTA_DUMMY_EN_R = crate::BitReader; -#[doc = "Field `slv_wrsta_dummy_en` writer - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] -pub type SLV_WRSTA_DUMMY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_wr_addr_bitlen` reader - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_WR_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_wr_addr_bitlen` writer - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_WR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `slv_rd_addr_bitlen` reader - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_RD_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_rd_addr_bitlen` writer - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] -pub type SLV_RD_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `slv_buf_bitlen` reader - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] -pub type SLV_BUF_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_buf_bitlen` writer - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] -pub type SLV_BUF_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `spi_status_read` reader - Enable spi slave status"] -pub type SPI_STATUS_READ_R = crate::BitReader; -#[doc = "Field `spi_status_read` writer - Enable spi slave status"] -pub type SPI_STATUS_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_status_fast_enable` reader - Enable fast spi slave status"] -pub type SPI_STATUS_FAST_ENABLE_R = crate::BitReader; -#[doc = "Field `spi_status_fast_enable` writer - Enable fast spi slave status"] -pub type SPI_STATUS_FAST_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `slv_status_bitlen` reader - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub type SLV_STATUS_BITLEN_R = crate::FieldReader; -#[doc = "Field `slv_status_bitlen` writer - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] -pub type SLV_STATUS_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -impl R { - #[doc = "Bit 0 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] - #[inline(always)] - pub fn slv_rdbuf_dummy_en(&self) -> SLV_RDBUF_DUMMY_EN_R { - SLV_RDBUF_DUMMY_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] - #[inline(always)] - pub fn slv_wrbuf_dummy_en(&self) -> SLV_WRBUF_DUMMY_EN_R { - SLV_WRBUF_DUMMY_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] - #[inline(always)] - pub fn slv_rdsta_dummy_en(&self) -> SLV_RDSTA_DUMMY_EN_R { - SLV_RDSTA_DUMMY_EN_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] - #[inline(always)] - pub fn slv_wrsta_dummy_en(&self) -> SLV_WRSTA_DUMMY_EN_R { - SLV_WRSTA_DUMMY_EN_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bits 4:9 - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - pub fn slv_wr_addr_bitlen(&self) -> SLV_WR_ADDR_BITLEN_R { - SLV_WR_ADDR_BITLEN_R::new(((self.bits >> 4) & 0x3f) as u8) - } - #[doc = "Bits 10:15 - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - pub fn slv_rd_addr_bitlen(&self) -> SLV_RD_ADDR_BITLEN_R { - SLV_RD_ADDR_BITLEN_R::new(((self.bits >> 10) & 0x3f) as u8) - } - #[doc = "Bits 16:24 - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] - #[inline(always)] - pub fn slv_buf_bitlen(&self) -> SLV_BUF_BITLEN_R { - SLV_BUF_BITLEN_R::new(((self.bits >> 16) & 0x01ff) as u16) - } - #[doc = "Bit 25 - Enable spi slave status"] - #[inline(always)] - pub fn spi_status_read(&self) -> SPI_STATUS_READ_R { - SPI_STATUS_READ_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 26 - Enable fast spi slave status"] - #[inline(always)] - pub fn spi_status_fast_enable(&self) -> SPI_STATUS_FAST_ENABLE_R { - SPI_STATUS_FAST_ENABLE_R::new(((self.bits >> 26) & 1) != 0) - } - #[doc = "Bits 27:31 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - pub fn slv_status_bitlen(&self) -> SLV_STATUS_BITLEN_R { - SLV_STATUS_BITLEN_R::new(((self.bits >> 27) & 0x1f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE1") - .field( - "slv_status_bitlen", - &format_args!("{}", self.slv_status_bitlen().bits()), - ) - .field( - "slv_buf_bitlen", - &format_args!("{}", self.slv_buf_bitlen().bits()), - ) - .field( - "slv_rd_addr_bitlen", - &format_args!("{}", self.slv_rd_addr_bitlen().bits()), - ) - .field( - "slv_wr_addr_bitlen", - &format_args!("{}", self.slv_wr_addr_bitlen().bits()), - ) - .field( - "slv_wrsta_dummy_en", - &format_args!("{}", self.slv_wrsta_dummy_en().bit()), - ) - .field( - "slv_rdsta_dummy_en", - &format_args!("{}", self.slv_rdsta_dummy_en().bit()), - ) - .field( - "slv_wrbuf_dummy_en", - &format_args!("{}", self.slv_wrbuf_dummy_en().bit()), - ) - .field( - "slv_rdbuf_dummy_en", - &format_args!("{}", self.slv_rdbuf_dummy_en().bit()), - ) - .field( - "spi_status_fast_enable", - &format_args!("{}", self.spi_status_fast_enable().bit()), - ) - .field( - "spi_status_read", - &format_args!("{}", self.spi_status_read().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-buffer\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_dummy_en(&mut self) -> SLV_RDBUF_DUMMY_EN_W { - SLV_RDBUF_DUMMY_EN_W::new(self, 0) - } - #[doc = "Bit 1 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-buffer\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_dummy_en(&mut self) -> SLV_WRBUF_DUMMY_EN_W { - SLV_WRBUF_DUMMY_EN_W::new(self, 1) - } - #[doc = "Bit 2 - In the slave mode, it is the enable bit of \"dummy\" phase for \"read-status\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_dummy_en(&mut self) -> SLV_RDSTA_DUMMY_EN_W { - SLV_RDSTA_DUMMY_EN_W::new(self, 2) - } - #[doc = "Bit 3 - In the slave mode, it is the enable bit of \"dummy\" phase for \"write-status\" operations."] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_dummy_en(&mut self) -> SLV_WRSTA_DUMMY_EN_W { - SLV_WRSTA_DUMMY_EN_W::new(self, 3) - } - #[doc = "Bits 4:9 - In the slave mode, it is the address length in bits for \"write-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wr_addr_bitlen(&mut self) -> SLV_WR_ADDR_BITLEN_W { - SLV_WR_ADDR_BITLEN_W::new(self, 4) - } - #[doc = "Bits 10:15 - In the slave mode, it is the address length in bits for \"read-buffer\" operation. The register value shall be(bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rd_addr_bitlen(&mut self) -> SLV_RD_ADDR_BITLEN_W { - SLV_RD_ADDR_BITLEN_W::new(self, 10) - } - #[doc = "Bits 16:24 - In the slave mode, it is the length in bits for \"write-buffer\" and \"read-buffer\" operations. The register value shallbe (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_buf_bitlen(&mut self) -> SLV_BUF_BITLEN_W { - SLV_BUF_BITLEN_W::new(self, 16) - } - #[doc = "Bit 25 - Enable spi slave status"] - #[inline(always)] - #[must_use] - pub fn spi_status_read(&mut self) -> SPI_STATUS_READ_W { - SPI_STATUS_READ_W::new(self, 25) - } - #[doc = "Bit 26 - Enable fast spi slave status"] - #[inline(always)] - #[must_use] - pub fn spi_status_fast_enable(&mut self) -> SPI_STATUS_FAST_ENABLE_W { - SPI_STATUS_FAST_ENABLE_W::new(self, 26) - } - #[doc = "Bits 27:31 - In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_status_bitlen(&mut self) -> SLV_STATUS_BITLEN_W { - SLV_STATUS_BITLEN_W::new(self, 27) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, it is the length in bits for \"write-status\" and \"read-status\" operations. The register valueshall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE1_SPEC; -impl crate::RegisterSpec for SPI_SLAVE1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave1::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave1::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE1 to value 0"] -impl crate::Resettable for SPI_SLAVE1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_slave2.rs b/esp8266/src/spi1/spi_slave2.rs deleted file mode 100644 index d93a81e4e1..0000000000 --- a/esp8266/src/spi1/spi_slave2.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_SLAVE2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE2` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdsta_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_RDSTA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_rdsta_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_RDSTA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrsta_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_WRSTA_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_wrsta_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] -pub type SLV_WRSTA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_rdbuf_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_RDBUF_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_rdbuf_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_RDBUF_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrbuf_dummy_cyclelen` reader - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_WRBUF_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `slv_wrbuf_dummy_cyclelen` writer - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] -pub type SLV_WRBUF_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_rdsta_dummy_cyclelen(&self) -> SLV_RDSTA_DUMMY_CYCLELEN_R { - SLV_RDSTA_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_wrsta_dummy_cyclelen(&self) -> SLV_WRSTA_DUMMY_CYCLELEN_R { - SLV_WRSTA_DUMMY_CYCLELEN_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_rdbuf_dummy_cyclelen(&self) -> SLV_RDBUF_DUMMY_CYCLELEN_R { - SLV_RDBUF_DUMMY_CYCLELEN_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - pub fn slv_wrbuf_dummy_cyclelen(&self) -> SLV_WRBUF_DUMMY_CYCLELEN_R { - SLV_WRBUF_DUMMY_CYCLELEN_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE2") - .field( - "slv_wrbuf_dummy_cyclelen", - &format_args!("{}", self.slv_wrbuf_dummy_cyclelen().bits()), - ) - .field( - "slv_rdbuf_dummy_cyclelen", - &format_args!("{}", self.slv_rdbuf_dummy_cyclelen().bits()), - ) - .field( - "slv_wrsta_dummy_cyclelen", - &format_args!("{}", self.slv_wrsta_dummy_cyclelen().bits()), - ) - .field( - "slv_rdsta_dummy_cyclelen", - &format_args!("{}", self.slv_rdsta_dummy_cyclelen().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_dummy_cyclelen(&mut self) -> SLV_RDSTA_DUMMY_CYCLELEN_W { - SLV_RDSTA_DUMMY_CYCLELEN_W::new(self, 0) - } - #[doc = "Bits 8:15 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"write-status\" operations. Theregister value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_dummy_cyclelen(&mut self) -> SLV_WRSTA_DUMMY_CYCLELEN_W { - SLV_WRSTA_DUMMY_CYCLELEN_W::new(self, 8) - } - #[doc = "Bits 16:23 - In the slave mode, it is the length in spi_clk cycles of \"dummy\" phase for \"read-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_dummy_cyclelen(&mut self) -> SLV_RDBUF_DUMMY_CYCLELEN_W { - SLV_RDBUF_DUMMY_CYCLELEN_W::new(self, 16) - } - #[doc = "Bits 24:31 - In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_dummy_cyclelen(&mut self) -> SLV_WRBUF_DUMMY_CYCLELEN_W { - SLV_WRBUF_DUMMY_CYCLELEN_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, it is the length in spi_clk cycles \"dummy\" phase for \"write-buffer\" operations. The registervalue shall be (cycle_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE2_SPEC; -impl crate::RegisterSpec for SPI_SLAVE2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave2::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave2::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE2 to value 0"] -impl crate::Resettable for SPI_SLAVE2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_slave3.rs b/esp8266/src/spi1/spi_slave3.rs deleted file mode 100644 index 5d4df59f0e..0000000000 --- a/esp8266/src/spi1/spi_slave3.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_SLAVE3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_SLAVE3` writer"] -pub type W = crate::W; -#[doc = "Field `slv_rdbuf_cmd_value` reader - In slave mode, it is the value of \"read-buffer\" command"] -pub type SLV_RDBUF_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_rdbuf_cmd_value` writer - In slave mode, it is the value of \"read-buffer\" command"] -pub type SLV_RDBUF_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrbuf_cmd_value` reader - In slave mode, it is the value of \"write-buffer\" command"] -pub type SLV_WRBUF_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_wrbuf_cmd_value` writer - In slave mode, it is the value of \"write-buffer\" command"] -pub type SLV_WRBUF_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_rdsta_cmd_value` reader - In slave mode, it is the value of \"read-status\" command"] -pub type SLV_RDSTA_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_rdsta_cmd_value` writer - In slave mode, it is the value of \"read-status\" command"] -pub type SLV_RDSTA_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `slv_wrsta_cmd_value` reader - In slave mode, it is the value of \"write-status\" command"] -pub type SLV_WRSTA_CMD_VALUE_R = crate::FieldReader; -#[doc = "Field `slv_wrsta_cmd_value` writer - In slave mode, it is the value of \"write-status\" command"] -pub type SLV_WRSTA_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - In slave mode, it is the value of \"read-buffer\" command"] - #[inline(always)] - pub fn slv_rdbuf_cmd_value(&self) -> SLV_RDBUF_CMD_VALUE_R { - SLV_RDBUF_CMD_VALUE_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:15 - In slave mode, it is the value of \"write-buffer\" command"] - #[inline(always)] - pub fn slv_wrbuf_cmd_value(&self) -> SLV_WRBUF_CMD_VALUE_R { - SLV_WRBUF_CMD_VALUE_R::new(((self.bits >> 8) & 0xff) as u8) - } - #[doc = "Bits 16:23 - In slave mode, it is the value of \"read-status\" command"] - #[inline(always)] - pub fn slv_rdsta_cmd_value(&self) -> SLV_RDSTA_CMD_VALUE_R { - SLV_RDSTA_CMD_VALUE_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bits 24:31 - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - pub fn slv_wrsta_cmd_value(&self) -> SLV_WRSTA_CMD_VALUE_R { - SLV_WRSTA_CMD_VALUE_R::new(((self.bits >> 24) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_SLAVE3") - .field( - "slv_wrsta_cmd_value", - &format_args!("{}", self.slv_wrsta_cmd_value().bits()), - ) - .field( - "slv_rdsta_cmd_value", - &format_args!("{}", self.slv_rdsta_cmd_value().bits()), - ) - .field( - "slv_wrbuf_cmd_value", - &format_args!("{}", self.slv_wrbuf_cmd_value().bits()), - ) - .field( - "slv_rdbuf_cmd_value", - &format_args!("{}", self.slv_rdbuf_cmd_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - In slave mode, it is the value of \"read-buffer\" command"] - #[inline(always)] - #[must_use] - pub fn slv_rdbuf_cmd_value(&mut self) -> SLV_RDBUF_CMD_VALUE_W { - SLV_RDBUF_CMD_VALUE_W::new(self, 0) - } - #[doc = "Bits 8:15 - In slave mode, it is the value of \"write-buffer\" command"] - #[inline(always)] - #[must_use] - pub fn slv_wrbuf_cmd_value(&mut self) -> SLV_WRBUF_CMD_VALUE_W { - SLV_WRBUF_CMD_VALUE_W::new(self, 8) - } - #[doc = "Bits 16:23 - In slave mode, it is the value of \"read-status\" command"] - #[inline(always)] - #[must_use] - pub fn slv_rdsta_cmd_value(&mut self) -> SLV_RDSTA_CMD_VALUE_W { - SLV_RDSTA_CMD_VALUE_W::new(self, 16) - } - #[doc = "Bits 24:31 - In slave mode, it is the value of \"write-status\" command"] - #[inline(always)] - #[must_use] - pub fn slv_wrsta_cmd_value(&mut self) -> SLV_WRSTA_CMD_VALUE_W { - SLV_WRSTA_CMD_VALUE_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In slave mode, it is the value of \"write-status\" command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_SLAVE3_SPEC; -impl crate::RegisterSpec for SPI_SLAVE3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_slave3::R`](R) reader structure"] -impl crate::Readable for SPI_SLAVE3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_slave3::W`](W) writer structure"] -impl crate::Writable for SPI_SLAVE3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_SLAVE3 to value 0"] -impl crate::Resettable for SPI_SLAVE3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_user.rs b/esp8266/src/spi1/spi_user.rs deleted file mode 100644 index 716c499919..0000000000 --- a/esp8266/src/spi1/spi_user.rs +++ /dev/null @@ -1,456 +0,0 @@ -#[doc = "Register `SPI_USER` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER` writer"] -pub type W = crate::W; -#[doc = "Field `spi_duplex` reader - set spi in full duplex mode"] -pub type SPI_DUPLEX_R = crate::BitReader; -#[doc = "Field `spi_duplex` writer - set spi in full duplex mode"] -pub type SPI_DUPLEX_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ahb_user_command_4byte` reader - reserved"] -pub type SPI_AHB_USER_COMMAND_4BYTE_R = crate::BitReader; -#[doc = "Field `spi_ahb_user_command_4byte` writer - reserved"] -pub type SPI_AHB_USER_COMMAND_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_flash_mode` reader - "] -pub type SPI_FLASH_MODE_R = crate::BitReader; -#[doc = "Field `spi_flash_mode` writer - "] -pub type SPI_FLASH_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ahb_user_command` reader - reserved"] -pub type SPI_AHB_USER_COMMAND_R = crate::BitReader; -#[doc = "Field `spi_ahb_user_command` writer - reserved"] -pub type SPI_AHB_USER_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs_hold` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable."] -pub type SPI_CS_HOLD_R = crate::BitReader; -#[doc = "Field `spi_cs_hold` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable."] -pub type SPI_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_cs_setup` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] -pub type SPI_CS_SETUP_R = crate::BitReader; -#[doc = "Field `spi_cs_setup` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] -pub type SPI_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ck_i_edge` reader - In the slave mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_I_EDGE_R = crate::BitReader; -#[doc = "Field `spi_ck_i_edge` writer - In the slave mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_ck_o_edge` reader - In the master mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_O_EDGE_R = crate::BitReader; -#[doc = "Field `spi_ck_o_edge` writer - In the master mode, 1: rising-edge; 0: falling-edge"] -pub type SPI_CK_O_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_rd_byte_order` reader - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] -pub type SPI_RD_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `spi_rd_byte_order` writer - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] -pub type SPI_RD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_wr_byte_order` reader - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] -pub type SPI_WR_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `spi_wr_byte_order` writer - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] -pub type SPI_WR_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_dual` reader - In the write operations, \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DUAL_R = crate::BitReader; -#[doc = "Field `spi_fwrite_dual` writer - In the write operations, \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_quad` reader - In the write operations, \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QUAD_R = crate::BitReader; -#[doc = "Field `spi_fwrite_quad` writer - In the write operations, \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_dio` reader - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DIO_R = crate::BitReader; -#[doc = "Field `spi_fwrite_dio` writer - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] -pub type SPI_FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_fwrite_qio` reader - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QIO_R = crate::BitReader; -#[doc = "Field `spi_fwrite_qio` writer - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] -pub type SPI_FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_sio` reader - 1: mosi and miso signals share the same pin"] -pub type SPI_SIO_R = crate::BitReader; -#[doc = "Field `spi_sio` writer - 1: mosi and miso signals share the same pin"] -pub type SPI_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `reg_usr_miso_highpart` reader - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MISO_HIGHPART_R = crate::BitReader; -#[doc = "Field `reg_usr_miso_highpart` writer - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `reg_usr_mosi_highpart` reader - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MOSI_HIGHPART_R = crate::BitReader; -#[doc = "Field `reg_usr_mosi_highpart` writer - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] -pub type REG_USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_mosi` reader - This bit enable the \"write-data\" phase of an operation."] -pub type SPI_USR_MOSI_R = crate::BitReader; -#[doc = "Field `spi_usr_mosi` writer - This bit enable the \"write-data\" phase of an operation."] -pub type SPI_USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_miso` reader - This bit enable the \"read-data\" phase of an operation."] -pub type SPI_USR_MISO_R = crate::BitReader; -#[doc = "Field `spi_usr_miso` writer - This bit enable the \"read-data\" phase of an operation."] -pub type SPI_USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_dummy` reader - This bit enable the \"dummy\" phase of an operation."] -pub type SPI_USR_DUMMY_R = crate::BitReader; -#[doc = "Field `spi_usr_dummy` writer - This bit enable the \"dummy\" phase of an operation."] -pub type SPI_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_addr` reader - This bit enable the \"address\" phase of an operation."] -pub type SPI_USR_ADDR_R = crate::BitReader; -#[doc = "Field `spi_usr_addr` writer - This bit enable the \"address\" phase of an operation."] -pub type SPI_USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi_usr_command` reader - This bit enable the \"command\" phase of an operation."] -pub type SPI_USR_COMMAND_R = crate::BitReader; -#[doc = "Field `spi_usr_command` writer - This bit enable the \"command\" phase of an operation."] -pub type SPI_USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - set spi in full duplex mode"] - #[inline(always)] - pub fn spi_duplex(&self) -> SPI_DUPLEX_R { - SPI_DUPLEX_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - reserved"] - #[inline(always)] - pub fn spi_ahb_user_command_4byte(&self) -> SPI_AHB_USER_COMMAND_4BYTE_R { - SPI_AHB_USER_COMMAND_4BYTE_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2"] - #[inline(always)] - pub fn spi_flash_mode(&self) -> SPI_FLASH_MODE_R { - SPI_FLASH_MODE_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - reserved"] - #[inline(always)] - pub fn spi_ahb_user_command(&self) -> SPI_AHB_USER_COMMAND_R { - SPI_AHB_USER_COMMAND_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] - #[inline(always)] - pub fn spi_cs_hold(&self) -> SPI_CS_HOLD_R { - SPI_CS_HOLD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] - #[inline(always)] - pub fn spi_cs_setup(&self) -> SPI_CS_SETUP_R { - SPI_CS_SETUP_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - In the slave mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - pub fn spi_ck_i_edge(&self) -> SPI_CK_I_EDGE_R { - SPI_CK_I_EDGE_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - In the master mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - pub fn spi_ck_o_edge(&self) -> SPI_CK_O_EDGE_R { - SPI_CK_O_EDGE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 10 - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] - #[inline(always)] - pub fn spi_rd_byte_order(&self) -> SPI_RD_BYTE_ORDER_R { - SPI_RD_BYTE_ORDER_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] - #[inline(always)] - pub fn spi_wr_byte_order(&self) -> SPI_WR_BYTE_ORDER_R { - SPI_WR_BYTE_ORDER_R::new(((self.bits >> 11) & 1) != 0) - } - #[doc = "Bit 12 - In the write operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_fwrite_dual(&self) -> SPI_FWRITE_DUAL_R { - SPI_FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - In the write operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_fwrite_quad(&self) -> SPI_FWRITE_QUAD_R { - SPI_FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - pub fn spi_fwrite_dio(&self) -> SPI_FWRITE_DIO_R { - SPI_FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - pub fn spi_fwrite_qio(&self) -> SPI_FWRITE_QIO_R { - SPI_FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 16 - 1: mosi and miso signals share the same pin"] - #[inline(always)] - pub fn spi_sio(&self) -> SPI_SIO_R { - SPI_SIO_R::new(((self.bits >> 16) & 1) != 0) - } - #[doc = "Bit 24 - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - pub fn reg_usr_miso_highpart(&self) -> REG_USR_MISO_HIGHPART_R { - REG_USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0) - } - #[doc = "Bit 25 - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - pub fn reg_usr_mosi_highpart(&self) -> REG_USR_MOSI_HIGHPART_R { - REG_USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0) - } - #[doc = "Bit 27 - This bit enable the \"write-data\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_mosi(&self) -> SPI_USR_MOSI_R { - SPI_USR_MOSI_R::new(((self.bits >> 27) & 1) != 0) - } - #[doc = "Bit 28 - This bit enable the \"read-data\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_miso(&self) -> SPI_USR_MISO_R { - SPI_USR_MISO_R::new(((self.bits >> 28) & 1) != 0) - } - #[doc = "Bit 29 - This bit enable the \"dummy\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_dummy(&self) -> SPI_USR_DUMMY_R { - SPI_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - This bit enable the \"address\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_addr(&self) -> SPI_USR_ADDR_R { - SPI_USR_ADDR_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - pub fn spi_usr_command(&self) -> SPI_USR_COMMAND_R { - SPI_USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER") - .field( - "spi_usr_command", - &format_args!("{}", self.spi_usr_command().bit()), - ) - .field( - "spi_usr_addr", - &format_args!("{}", self.spi_usr_addr().bit()), - ) - .field( - "spi_usr_dummy", - &format_args!("{}", self.spi_usr_dummy().bit()), - ) - .field( - "spi_usr_miso", - &format_args!("{}", self.spi_usr_miso().bit()), - ) - .field( - "spi_usr_mosi", - &format_args!("{}", self.spi_usr_mosi().bit()), - ) - .field( - "reg_usr_mosi_highpart", - &format_args!("{}", self.reg_usr_mosi_highpart().bit()), - ) - .field( - "reg_usr_miso_highpart", - &format_args!("{}", self.reg_usr_miso_highpart().bit()), - ) - .field("spi_sio", &format_args!("{}", self.spi_sio().bit())) - .field( - "spi_fwrite_qio", - &format_args!("{}", self.spi_fwrite_qio().bit()), - ) - .field( - "spi_fwrite_dio", - &format_args!("{}", self.spi_fwrite_dio().bit()), - ) - .field( - "spi_fwrite_quad", - &format_args!("{}", self.spi_fwrite_quad().bit()), - ) - .field( - "spi_fwrite_dual", - &format_args!("{}", self.spi_fwrite_dual().bit()), - ) - .field( - "spi_wr_byte_order", - &format_args!("{}", self.spi_wr_byte_order().bit()), - ) - .field( - "spi_rd_byte_order", - &format_args!("{}", self.spi_rd_byte_order().bit()), - ) - .field( - "spi_ck_i_edge", - &format_args!("{}", self.spi_ck_i_edge().bit()), - ) - .field( - "spi_ck_o_edge", - &format_args!("{}", self.spi_ck_o_edge().bit()), - ) - .field( - "spi_cs_setup", - &format_args!("{}", self.spi_cs_setup().bit()), - ) - .field("spi_cs_hold", &format_args!("{}", self.spi_cs_hold().bit())) - .field( - "spi_ahb_user_command", - &format_args!("{}", self.spi_ahb_user_command().bit()), - ) - .field( - "spi_flash_mode", - &format_args!("{}", self.spi_flash_mode().bit()), - ) - .field( - "spi_ahb_user_command_4byte", - &format_args!("{}", self.spi_ahb_user_command_4byte().bit()), - ) - .field("spi_duplex", &format_args!("{}", self.spi_duplex().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - set spi in full duplex mode"] - #[inline(always)] - #[must_use] - pub fn spi_duplex(&mut self) -> SPI_DUPLEX_W { - SPI_DUPLEX_W::new(self, 0) - } - #[doc = "Bit 1 - reserved"] - #[inline(always)] - #[must_use] - pub fn spi_ahb_user_command_4byte(&mut self) -> SPI_AHB_USER_COMMAND_4BYTE_W { - SPI_AHB_USER_COMMAND_4BYTE_W::new(self, 1) - } - #[doc = "Bit 2"] - #[inline(always)] - #[must_use] - pub fn spi_flash_mode(&mut self) -> SPI_FLASH_MODE_W { - SPI_FLASH_MODE_W::new(self, 2) - } - #[doc = "Bit 3 - reserved"] - #[inline(always)] - #[must_use] - pub fn spi_ahb_user_command(&mut self) -> SPI_AHB_USER_COMMAND_W { - SPI_AHB_USER_COMMAND_W::new(self, 3) - } - #[doc = "Bit 4 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] - #[inline(always)] - #[must_use] - pub fn spi_cs_hold(&mut self) -> SPI_CS_HOLD_W { - SPI_CS_HOLD_W::new(self, 4) - } - #[doc = "Bit 5 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] - #[inline(always)] - #[must_use] - pub fn spi_cs_setup(&mut self) -> SPI_CS_SETUP_W { - SPI_CS_SETUP_W::new(self, 5) - } - #[doc = "Bit 6 - In the slave mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - #[must_use] - pub fn spi_ck_i_edge(&mut self) -> SPI_CK_I_EDGE_W { - SPI_CK_I_EDGE_W::new(self, 6) - } - #[doc = "Bit 7 - In the master mode, 1: rising-edge; 0: falling-edge"] - #[inline(always)] - #[must_use] - pub fn spi_ck_o_edge(&mut self) -> SPI_CK_O_EDGE_W { - SPI_CK_O_EDGE_W::new(self, 7) - } - #[doc = "Bit 10 - In \"read-data\" (MISO) phase, 1: little-endian; 0: big_endian"] - #[inline(always)] - #[must_use] - pub fn spi_rd_byte_order(&mut self) -> SPI_RD_BYTE_ORDER_W { - SPI_RD_BYTE_ORDER_W::new(self, 10) - } - #[doc = "Bit 11 - In \"command\", \"address\", \"write-data\" (MOSI) phases, 1: little-endian; 0: big_endian"] - #[inline(always)] - #[must_use] - pub fn spi_wr_byte_order(&mut self) -> SPI_WR_BYTE_ORDER_W { - SPI_WR_BYTE_ORDER_W::new(self, 11) - } - #[doc = "Bit 12 - In the write operations, \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_dual(&mut self) -> SPI_FWRITE_DUAL_W { - SPI_FWRITE_DUAL_W::new(self, 12) - } - #[doc = "Bit 13 - In the write operations, \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_quad(&mut self) -> SPI_FWRITE_QUAD_W { - SPI_FWRITE_QUAD_W::new(self, 13) - } - #[doc = "Bit 14 - In the write operations, \"address\" phase and \"read-data\" phase apply 2 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_dio(&mut self) -> SPI_FWRITE_DIO_W { - SPI_FWRITE_DIO_W::new(self, 14) - } - #[doc = "Bit 15 - In the write operations, \"address\" phase and \"read-data\" phase apply 4 signals"] - #[inline(always)] - #[must_use] - pub fn spi_fwrite_qio(&mut self) -> SPI_FWRITE_QIO_W { - SPI_FWRITE_QIO_W::new(self, 15) - } - #[doc = "Bit 16 - 1: mosi and miso signals share the same pin"] - #[inline(always)] - #[must_use] - pub fn spi_sio(&mut self) -> SPI_SIO_W { - SPI_SIO_W::new(self, 16) - } - #[doc = "Bit 24 - 1: \"read-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - #[must_use] - pub fn reg_usr_miso_highpart(&mut self) -> REG_USR_MISO_HIGHPART_W { - REG_USR_MISO_HIGHPART_W::new(self, 24) - } - #[doc = "Bit 25 - 1: \"write-data\" phase only access to high-part of the buffer spi_w8~spi_w15"] - #[inline(always)] - #[must_use] - pub fn reg_usr_mosi_highpart(&mut self) -> REG_USR_MOSI_HIGHPART_W { - REG_USR_MOSI_HIGHPART_W::new(self, 25) - } - #[doc = "Bit 27 - This bit enable the \"write-data\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_mosi(&mut self) -> SPI_USR_MOSI_W { - SPI_USR_MOSI_W::new(self, 27) - } - #[doc = "Bit 28 - This bit enable the \"read-data\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_miso(&mut self) -> SPI_USR_MISO_W { - SPI_USR_MISO_W::new(self, 28) - } - #[doc = "Bit 29 - This bit enable the \"dummy\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_dummy(&mut self) -> SPI_USR_DUMMY_W { - SPI_USR_DUMMY_W::new(self, 29) - } - #[doc = "Bit 30 - This bit enable the \"address\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_addr(&mut self) -> SPI_USR_ADDR_W { - SPI_USR_ADDR_W::new(self, 30) - } - #[doc = "Bit 31 - This bit enable the \"command\" phase of an operation."] - #[inline(always)] - #[must_use] - pub fn spi_usr_command(&mut self) -> SPI_USR_COMMAND_W { - SPI_USR_COMMAND_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "This bit enable the \"command\" phase of an operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER_SPEC; -impl crate::RegisterSpec for SPI_USER_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user::R`](R) reader structure"] -impl crate::Readable for SPI_USER_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user::W`](W) writer structure"] -impl crate::Writable for SPI_USER_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER to value 0"] -impl crate::Resettable for SPI_USER_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_user1.rs b/esp8266/src/spi1/spi_user1.rs deleted file mode 100644 index d552093174..0000000000 --- a/esp8266/src/spi1/spi_user1.rs +++ /dev/null @@ -1,123 +0,0 @@ -#[doc = "Register `SPI_USER1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER1` writer"] -pub type W = crate::W; -#[doc = "Field `reg_usr_dummy_cyclelen` reader - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] -pub type REG_USR_DUMMY_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_dummy_cyclelen` writer - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] -pub type REG_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `reg_usr_miso_bitlen` reader - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MISO_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_miso_bitlen` writer - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MISO_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `reg_usr_mosi_bitlen` reader - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MOSI_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_mosi_bitlen` writer - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_MOSI_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; -#[doc = "Field `reg_usr_addr_bitlen` reader - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_ADDR_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_addr_bitlen` writer - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -impl R { - #[doc = "Bits 0:7 - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] - #[inline(always)] - pub fn reg_usr_dummy_cyclelen(&self) -> REG_USR_DUMMY_CYCLELEN_R { - REG_USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 8:16 - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_miso_bitlen(&self) -> REG_USR_MISO_BITLEN_R { - REG_USR_MISO_BITLEN_R::new(((self.bits >> 8) & 0x01ff) as u16) - } - #[doc = "Bits 17:25 - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_mosi_bitlen(&self) -> REG_USR_MOSI_BITLEN_R { - REG_USR_MOSI_BITLEN_R::new(((self.bits >> 17) & 0x01ff) as u16) - } - #[doc = "Bits 26:31 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_addr_bitlen(&self) -> REG_USR_ADDR_BITLEN_R { - REG_USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER1") - .field( - "reg_usr_addr_bitlen", - &format_args!("{}", self.reg_usr_addr_bitlen().bits()), - ) - .field( - "reg_usr_mosi_bitlen", - &format_args!("{}", self.reg_usr_mosi_bitlen().bits()), - ) - .field( - "reg_usr_miso_bitlen", - &format_args!("{}", self.reg_usr_miso_bitlen().bits()), - ) - .field( - "reg_usr_dummy_cyclelen", - &format_args!("{}", self.reg_usr_dummy_cyclelen().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - The length in spi_clk cycles of \"dummy\" phase. The register value shall be (cycle_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_dummy_cyclelen(&mut self) -> REG_USR_DUMMY_CYCLELEN_W { - REG_USR_DUMMY_CYCLELEN_W::new(self, 0) - } - #[doc = "Bits 8:16 - The length in bits of \"read-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_miso_bitlen(&mut self) -> REG_USR_MISO_BITLEN_W { - REG_USR_MISO_BITLEN_W::new(self, 8) - } - #[doc = "Bits 17:25 - The length in bits of \"write-data\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_mosi_bitlen(&mut self) -> REG_USR_MOSI_BITLEN_W { - REG_USR_MOSI_BITLEN_W::new(self, 17) - } - #[doc = "Bits 26:31 - The length in bits of \"address\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_addr_bitlen(&mut self) -> REG_USR_ADDR_BITLEN_W { - REG_USR_ADDR_BITLEN_W::new(self, 26) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The length in bits of \"address\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER1_SPEC; -impl crate::RegisterSpec for SPI_USER1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user1::R`](R) reader structure"] -impl crate::Readable for SPI_USER1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user1::W`](W) writer structure"] -impl crate::Writable for SPI_USER1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER1 to value 0"] -impl crate::Resettable for SPI_USER1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_user2.rs b/esp8266/src/spi1/spi_user2.rs deleted file mode 100644 index 8b70cf1725..0000000000 --- a/esp8266/src/spi1/spi_user2.rs +++ /dev/null @@ -1,85 +0,0 @@ -#[doc = "Register `SPI_USER2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_USER2` writer"] -pub type W = crate::W; -#[doc = "Field `reg_usr_command_value` reader - The value of \"command\" phase"] -pub type REG_USR_COMMAND_VALUE_R = crate::FieldReader; -#[doc = "Field `reg_usr_command_value` writer - The value of \"command\" phase"] -pub type REG_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `reg_usr_command_bitlen` reader - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_COMMAND_BITLEN_R = crate::FieldReader; -#[doc = "Field `reg_usr_command_bitlen` writer - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] -pub type REG_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -impl R { - #[doc = "Bits 0:15 - The value of \"command\" phase"] - #[inline(always)] - pub fn reg_usr_command_value(&self) -> REG_USR_COMMAND_VALUE_R { - REG_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) - } - #[doc = "Bits 28:31 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - pub fn reg_usr_command_bitlen(&self) -> REG_USR_COMMAND_BITLEN_R { - REG_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_USER2") - .field( - "reg_usr_command_bitlen", - &format_args!("{}", self.reg_usr_command_bitlen().bits()), - ) - .field( - "reg_usr_command_value", - &format_args!("{}", self.reg_usr_command_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:15 - The value of \"command\" phase"] - #[inline(always)] - #[must_use] - pub fn reg_usr_command_value(&mut self) -> REG_USR_COMMAND_VALUE_W { - REG_USR_COMMAND_VALUE_W::new(self, 0) - } - #[doc = "Bits 28:31 - The length in bits of \"command\" phase. The register value shall be (bit_num-1)"] - #[inline(always)] - #[must_use] - pub fn reg_usr_command_bitlen(&mut self) -> REG_USR_COMMAND_BITLEN_W { - REG_USR_COMMAND_BITLEN_W::new(self, 28) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The length in bits of \"command\" phase. The register value shall be (bit_num-1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_USER2_SPEC; -impl crate::RegisterSpec for SPI_USER2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_user2::R`](R) reader structure"] -impl crate::Readable for SPI_USER2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_user2::W`](W) writer structure"] -impl crate::Writable for SPI_USER2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_USER2 to value 0"] -impl crate::Resettable for SPI_USER2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w0.rs b/esp8266/src/spi1/spi_w0.rs deleted file mode 100644 index 75e1624953..0000000000 --- a/esp8266/src/spi1/spi_w0.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W0` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W0` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w0` reader - the data inside the buffer of the SPI module, word 0"] -pub type SPI_W0_R = crate::FieldReader; -#[doc = "Field `spi_w0` writer - the data inside the buffer of the SPI module, word 0"] -pub type SPI_W0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - pub fn spi_w0(&self) -> SPI_W0_R { - SPI_W0_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W0") - .field("spi_w0", &format_args!("{}", self.spi_w0().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 0"] - #[inline(always)] - #[must_use] - pub fn spi_w0(&mut self) -> SPI_W0_W { - SPI_W0_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W0_SPEC; -impl crate::RegisterSpec for SPI_W0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w0::R`](R) reader structure"] -impl crate::Readable for SPI_W0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w0::W`](W) writer structure"] -impl crate::Writable for SPI_W0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W0 to value 0"] -impl crate::Resettable for SPI_W0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w1.rs b/esp8266/src/spi1/spi_w1.rs deleted file mode 100644 index e6dd0cc9e6..0000000000 --- a/esp8266/src/spi1/spi_w1.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W1` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W1` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w1` reader - the data inside the buffer of the SPI module, word 1"] -pub type SPI_W1_R = crate::FieldReader; -#[doc = "Field `spi_w1` writer - the data inside the buffer of the SPI module, word 1"] -pub type SPI_W1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - pub fn spi_w1(&self) -> SPI_W1_R { - SPI_W1_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W1") - .field("spi_w1", &format_args!("{}", self.spi_w1().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 1"] - #[inline(always)] - #[must_use] - pub fn spi_w1(&mut self) -> SPI_W1_W { - SPI_W1_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W1_SPEC; -impl crate::RegisterSpec for SPI_W1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w1::R`](R) reader structure"] -impl crate::Readable for SPI_W1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w1::W`](W) writer structure"] -impl crate::Writable for SPI_W1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W1 to value 0"] -impl crate::Resettable for SPI_W1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w10.rs b/esp8266/src/spi1/spi_w10.rs deleted file mode 100644 index 2b94029724..0000000000 --- a/esp8266/src/spi1/spi_w10.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W10` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W10` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w10` reader - the data inside the buffer of the SPI module, word 10"] -pub type SPI_W10_R = crate::FieldReader; -#[doc = "Field `spi_w10` writer - the data inside the buffer of the SPI module, word 10"] -pub type SPI_W10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - pub fn spi_w10(&self) -> SPI_W10_R { - SPI_W10_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W10") - .field("spi_w10", &format_args!("{}", self.spi_w10().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 10"] - #[inline(always)] - #[must_use] - pub fn spi_w10(&mut self) -> SPI_W10_W { - SPI_W10_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W10_SPEC; -impl crate::RegisterSpec for SPI_W10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w10::R`](R) reader structure"] -impl crate::Readable for SPI_W10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w10::W`](W) writer structure"] -impl crate::Writable for SPI_W10_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W10 to value 0"] -impl crate::Resettable for SPI_W10_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w11.rs b/esp8266/src/spi1/spi_w11.rs deleted file mode 100644 index 90bc965426..0000000000 --- a/esp8266/src/spi1/spi_w11.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W11` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W11` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w11` reader - the data inside the buffer of the SPI module, word 11"] -pub type SPI_W11_R = crate::FieldReader; -#[doc = "Field `spi_w11` writer - the data inside the buffer of the SPI module, word 11"] -pub type SPI_W11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - pub fn spi_w11(&self) -> SPI_W11_R { - SPI_W11_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W11") - .field("spi_w11", &format_args!("{}", self.spi_w11().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 11"] - #[inline(always)] - #[must_use] - pub fn spi_w11(&mut self) -> SPI_W11_W { - SPI_W11_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W11_SPEC; -impl crate::RegisterSpec for SPI_W11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w11::R`](R) reader structure"] -impl crate::Readable for SPI_W11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w11::W`](W) writer structure"] -impl crate::Writable for SPI_W11_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W11 to value 0"] -impl crate::Resettable for SPI_W11_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w12.rs b/esp8266/src/spi1/spi_w12.rs deleted file mode 100644 index 27977e4493..0000000000 --- a/esp8266/src/spi1/spi_w12.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W12` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W12` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w12` reader - the data inside the buffer of the SPI module, word 12"] -pub type SPI_W12_R = crate::FieldReader; -#[doc = "Field `spi_w12` writer - the data inside the buffer of the SPI module, word 12"] -pub type SPI_W12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - pub fn spi_w12(&self) -> SPI_W12_R { - SPI_W12_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W12") - .field("spi_w12", &format_args!("{}", self.spi_w12().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 12"] - #[inline(always)] - #[must_use] - pub fn spi_w12(&mut self) -> SPI_W12_W { - SPI_W12_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W12_SPEC; -impl crate::RegisterSpec for SPI_W12_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w12::R`](R) reader structure"] -impl crate::Readable for SPI_W12_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w12::W`](W) writer structure"] -impl crate::Writable for SPI_W12_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W12 to value 0"] -impl crate::Resettable for SPI_W12_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w13.rs b/esp8266/src/spi1/spi_w13.rs deleted file mode 100644 index bf8a4462fa..0000000000 --- a/esp8266/src/spi1/spi_w13.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W13` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W13` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w13` reader - the data inside the buffer of the SPI module, word 13"] -pub type SPI_W13_R = crate::FieldReader; -#[doc = "Field `spi_w13` writer - the data inside the buffer of the SPI module, word 13"] -pub type SPI_W13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - pub fn spi_w13(&self) -> SPI_W13_R { - SPI_W13_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W13") - .field("spi_w13", &format_args!("{}", self.spi_w13().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 13"] - #[inline(always)] - #[must_use] - pub fn spi_w13(&mut self) -> SPI_W13_W { - SPI_W13_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W13_SPEC; -impl crate::RegisterSpec for SPI_W13_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w13::R`](R) reader structure"] -impl crate::Readable for SPI_W13_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w13::W`](W) writer structure"] -impl crate::Writable for SPI_W13_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W13 to value 0"] -impl crate::Resettable for SPI_W13_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w14.rs b/esp8266/src/spi1/spi_w14.rs deleted file mode 100644 index 47f9865c17..0000000000 --- a/esp8266/src/spi1/spi_w14.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W14` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W14` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w14` reader - the data inside the buffer of the SPI module, word 14"] -pub type SPI_W14_R = crate::FieldReader; -#[doc = "Field `spi_w14` writer - the data inside the buffer of the SPI module, word 14"] -pub type SPI_W14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - pub fn spi_w14(&self) -> SPI_W14_R { - SPI_W14_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W14") - .field("spi_w14", &format_args!("{}", self.spi_w14().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 14"] - #[inline(always)] - #[must_use] - pub fn spi_w14(&mut self) -> SPI_W14_W { - SPI_W14_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W14_SPEC; -impl crate::RegisterSpec for SPI_W14_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w14::R`](R) reader structure"] -impl crate::Readable for SPI_W14_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w14::W`](W) writer structure"] -impl crate::Writable for SPI_W14_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W14 to value 0"] -impl crate::Resettable for SPI_W14_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w15.rs b/esp8266/src/spi1/spi_w15.rs deleted file mode 100644 index 9d613f3985..0000000000 --- a/esp8266/src/spi1/spi_w15.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W15` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W15` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w15` reader - the data inside the buffer of the SPI module, word 15"] -pub type SPI_W15_R = crate::FieldReader; -#[doc = "Field `spi_w15` writer - the data inside the buffer of the SPI module, word 15"] -pub type SPI_W15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - pub fn spi_w15(&self) -> SPI_W15_R { - SPI_W15_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W15") - .field("spi_w15", &format_args!("{}", self.spi_w15().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 15"] - #[inline(always)] - #[must_use] - pub fn spi_w15(&mut self) -> SPI_W15_W { - SPI_W15_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W15_SPEC; -impl crate::RegisterSpec for SPI_W15_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w15::R`](R) reader structure"] -impl crate::Readable for SPI_W15_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w15::W`](W) writer structure"] -impl crate::Writable for SPI_W15_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W15 to value 0"] -impl crate::Resettable for SPI_W15_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w2.rs b/esp8266/src/spi1/spi_w2.rs deleted file mode 100644 index 142dc225b6..0000000000 --- a/esp8266/src/spi1/spi_w2.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W2` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W2` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w2` reader - the data inside the buffer of the SPI module, word 2"] -pub type SPI_W2_R = crate::FieldReader; -#[doc = "Field `spi_w2` writer - the data inside the buffer of the SPI module, word 2"] -pub type SPI_W2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - pub fn spi_w2(&self) -> SPI_W2_R { - SPI_W2_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W2") - .field("spi_w2", &format_args!("{}", self.spi_w2().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 2"] - #[inline(always)] - #[must_use] - pub fn spi_w2(&mut self) -> SPI_W2_W { - SPI_W2_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W2_SPEC; -impl crate::RegisterSpec for SPI_W2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w2::R`](R) reader structure"] -impl crate::Readable for SPI_W2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w2::W`](W) writer structure"] -impl crate::Writable for SPI_W2_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W2 to value 0"] -impl crate::Resettable for SPI_W2_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w3.rs b/esp8266/src/spi1/spi_w3.rs deleted file mode 100644 index e6af27f702..0000000000 --- a/esp8266/src/spi1/spi_w3.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W3` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W3` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w3` reader - the data inside the buffer of the SPI module, word 3"] -pub type SPI_W3_R = crate::FieldReader; -#[doc = "Field `spi_w3` writer - the data inside the buffer of the SPI module, word 3"] -pub type SPI_W3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - pub fn spi_w3(&self) -> SPI_W3_R { - SPI_W3_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W3") - .field("spi_w3", &format_args!("{}", self.spi_w3().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 3"] - #[inline(always)] - #[must_use] - pub fn spi_w3(&mut self) -> SPI_W3_W { - SPI_W3_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W3_SPEC; -impl crate::RegisterSpec for SPI_W3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w3::R`](R) reader structure"] -impl crate::Readable for SPI_W3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w3::W`](W) writer structure"] -impl crate::Writable for SPI_W3_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W3 to value 0"] -impl crate::Resettable for SPI_W3_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w4.rs b/esp8266/src/spi1/spi_w4.rs deleted file mode 100644 index ad2a4a4c36..0000000000 --- a/esp8266/src/spi1/spi_w4.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W4` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W4` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w4` reader - the data inside the buffer of the SPI module, word 4"] -pub type SPI_W4_R = crate::FieldReader; -#[doc = "Field `spi_w4` writer - the data inside the buffer of the SPI module, word 4"] -pub type SPI_W4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - pub fn spi_w4(&self) -> SPI_W4_R { - SPI_W4_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W4") - .field("spi_w4", &format_args!("{}", self.spi_w4().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 4"] - #[inline(always)] - #[must_use] - pub fn spi_w4(&mut self) -> SPI_W4_W { - SPI_W4_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W4_SPEC; -impl crate::RegisterSpec for SPI_W4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w4::R`](R) reader structure"] -impl crate::Readable for SPI_W4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w4::W`](W) writer structure"] -impl crate::Writable for SPI_W4_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W4 to value 0"] -impl crate::Resettable for SPI_W4_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w5.rs b/esp8266/src/spi1/spi_w5.rs deleted file mode 100644 index 581a12b6cc..0000000000 --- a/esp8266/src/spi1/spi_w5.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W5` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W5` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w5` reader - the data inside the buffer of the SPI module, word 5"] -pub type SPI_W5_R = crate::FieldReader; -#[doc = "Field `spi_w5` writer - the data inside the buffer of the SPI module, word 5"] -pub type SPI_W5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - pub fn spi_w5(&self) -> SPI_W5_R { - SPI_W5_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W5") - .field("spi_w5", &format_args!("{}", self.spi_w5().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 5"] - #[inline(always)] - #[must_use] - pub fn spi_w5(&mut self) -> SPI_W5_W { - SPI_W5_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W5_SPEC; -impl crate::RegisterSpec for SPI_W5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w5::R`](R) reader structure"] -impl crate::Readable for SPI_W5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w5::W`](W) writer structure"] -impl crate::Writable for SPI_W5_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W5 to value 0"] -impl crate::Resettable for SPI_W5_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w6.rs b/esp8266/src/spi1/spi_w6.rs deleted file mode 100644 index 9621962619..0000000000 --- a/esp8266/src/spi1/spi_w6.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W6` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W6` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w6` reader - the data inside the buffer of the SPI module, word 6"] -pub type SPI_W6_R = crate::FieldReader; -#[doc = "Field `spi_w6` writer - the data inside the buffer of the SPI module, word 6"] -pub type SPI_W6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - pub fn spi_w6(&self) -> SPI_W6_R { - SPI_W6_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W6") - .field("spi_w6", &format_args!("{}", self.spi_w6().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 6"] - #[inline(always)] - #[must_use] - pub fn spi_w6(&mut self) -> SPI_W6_W { - SPI_W6_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W6_SPEC; -impl crate::RegisterSpec for SPI_W6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w6::R`](R) reader structure"] -impl crate::Readable for SPI_W6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w6::W`](W) writer structure"] -impl crate::Writable for SPI_W6_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W6 to value 0"] -impl crate::Resettable for SPI_W6_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w7.rs b/esp8266/src/spi1/spi_w7.rs deleted file mode 100644 index a944063d60..0000000000 --- a/esp8266/src/spi1/spi_w7.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W7` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W7` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w7` reader - the data inside the buffer of the SPI module, word 7"] -pub type SPI_W7_R = crate::FieldReader; -#[doc = "Field `spi_w7` writer - the data inside the buffer of the SPI module, word 7"] -pub type SPI_W7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - pub fn spi_w7(&self) -> SPI_W7_R { - SPI_W7_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W7") - .field("spi_w7", &format_args!("{}", self.spi_w7().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 7"] - #[inline(always)] - #[must_use] - pub fn spi_w7(&mut self) -> SPI_W7_W { - SPI_W7_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W7_SPEC; -impl crate::RegisterSpec for SPI_W7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w7::R`](R) reader structure"] -impl crate::Readable for SPI_W7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w7::W`](W) writer structure"] -impl crate::Writable for SPI_W7_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W7 to value 0"] -impl crate::Resettable for SPI_W7_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w8.rs b/esp8266/src/spi1/spi_w8.rs deleted file mode 100644 index a2baeeeaaa..0000000000 --- a/esp8266/src/spi1/spi_w8.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W8` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W8` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w8` reader - the data inside the buffer of the SPI module, word 8"] -pub type SPI_W8_R = crate::FieldReader; -#[doc = "Field `spi_w8` writer - the data inside the buffer of the SPI module, word 8"] -pub type SPI_W8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - pub fn spi_w8(&self) -> SPI_W8_R { - SPI_W8_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W8") - .field("spi_w8", &format_args!("{}", self.spi_w8().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 8"] - #[inline(always)] - #[must_use] - pub fn spi_w8(&mut self) -> SPI_W8_W { - SPI_W8_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W8_SPEC; -impl crate::RegisterSpec for SPI_W8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w8::R`](R) reader structure"] -impl crate::Readable for SPI_W8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w8::W`](W) writer structure"] -impl crate::Writable for SPI_W8_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W8 to value 0"] -impl crate::Resettable for SPI_W8_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_w9.rs b/esp8266/src/spi1/spi_w9.rs deleted file mode 100644 index d61d024040..0000000000 --- a/esp8266/src/spi1/spi_w9.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `SPI_W9` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_W9` writer"] -pub type W = crate::W; -#[doc = "Field `spi_w9` reader - the data inside the buffer of the SPI module, word 9"] -pub type SPI_W9_R = crate::FieldReader; -#[doc = "Field `spi_w9` writer - the data inside the buffer of the SPI module, word 9"] -pub type SPI_W9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - pub fn spi_w9(&self) -> SPI_W9_R { - SPI_W9_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_W9") - .field("spi_w9", &format_args!("{}", self.spi_w9().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the data inside the buffer of the SPI module, word 9"] - #[inline(always)] - #[must_use] - pub fn spi_w9(&mut self) -> SPI_W9_W { - SPI_W9_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the data inside the buffer of the SPI module, word 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_W9_SPEC; -impl crate::RegisterSpec for SPI_W9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_w9::R`](R) reader structure"] -impl crate::Readable for SPI_W9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_w9::W`](W) writer structure"] -impl crate::Writable for SPI_W9_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_W9 to value 0"] -impl crate::Resettable for SPI_W9_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/spi1/spi_wr_status.rs b/esp8266/src/spi1/spi_wr_status.rs deleted file mode 100644 index 352c3741d6..0000000000 --- a/esp8266/src/spi1/spi_wr_status.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `SPI_WR_STATUS` reader"] -pub type R = crate::R; -#[doc = "Register `SPI_WR_STATUS` writer"] -pub type W = crate::W; -#[doc = "Field `slv_wr_status` reader - In the slave mode, this register are the status register for the master to write into."] -pub type SLV_WR_STATUS_R = crate::FieldReader; -#[doc = "Field `slv_wr_status` writer - In the slave mode, this register are the status register for the master to write into."] -pub type SLV_WR_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - pub fn slv_wr_status(&self) -> SLV_WR_STATUS_R { - SLV_WR_STATUS_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI_WR_STATUS") - .field( - "slv_wr_status", - &format_args!("{}", self.slv_wr_status().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - In the slave mode, this register are the status register for the master to write into."] - #[inline(always)] - #[must_use] - pub fn slv_wr_status(&mut self) -> SLV_WR_STATUS_W { - SLV_WR_STATUS_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "In the slave mode, this register are the status register for the master to write into.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_wr_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_wr_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SPI_WR_STATUS_SPEC; -impl crate::RegisterSpec for SPI_WR_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`spi_wr_status::R`](R) reader structure"] -impl crate::Readable for SPI_WR_STATUS_SPEC {} -#[doc = "`write(|w| ..)` method takes [`spi_wr_status::W`](W) writer structure"] -impl crate::Writable for SPI_WR_STATUS_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets SPI_WR_STATUS to value 0"] -impl crate::Resettable for SPI_WR_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer.rs b/esp8266/src/timer.rs deleted file mode 100644 index 7a9120f44b..0000000000 --- a/esp8266/src/timer.rs +++ /dev/null @@ -1,98 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - frc1_load: FRC1_LOAD, - frc1_count: FRC1_COUNT, - frc1_ctrl: FRC1_CTRL, - frc1_int: FRC1_INT, - _reserved4: [u8; 0x10], - frc2_load: FRC2_LOAD, - frc2_count: FRC2_COUNT, - frc2_ctrl: FRC2_CTRL, - frc2_int: FRC2_INT, - frc2_alarm: FRC2_ALARM, -} -impl RegisterBlock { - #[doc = "0x00 - the load value into the counter"] - #[inline(always)] - pub const fn frc1_load(&self) -> &FRC1_LOAD { - &self.frc1_load - } - #[doc = "0x04 - the current value of the counter. It is a decreasingcounter."] - #[inline(always)] - pub const fn frc1_count(&self) -> &FRC1_COUNT { - &self.frc1_count - } - #[doc = "0x08 - FRC1_CTRL"] - #[inline(always)] - pub const fn frc1_ctrl(&self) -> &FRC1_CTRL { - &self.frc1_ctrl - } - #[doc = "0x0c - FRC1_INT"] - #[inline(always)] - pub const fn frc1_int(&self) -> &FRC1_INT { - &self.frc1_int - } - #[doc = "0x20 - the load value into the counter"] - #[inline(always)] - pub const fn frc2_load(&self) -> &FRC2_LOAD { - &self.frc2_load - } - #[doc = "0x24 - the current value of the counter. It is a increasingcounter."] - #[inline(always)] - pub const fn frc2_count(&self) -> &FRC2_COUNT { - &self.frc2_count - } - #[doc = "0x28 - FRC2_CTRL"] - #[inline(always)] - pub const fn frc2_ctrl(&self) -> &FRC2_CTRL { - &self.frc2_ctrl - } - #[doc = "0x2c - FRC2_INT"] - #[inline(always)] - pub const fn frc2_int(&self) -> &FRC2_INT { - &self.frc2_int - } - #[doc = "0x30 - the alarm value for the counter"] - #[inline(always)] - pub const fn frc2_alarm(&self) -> &FRC2_ALARM { - &self.frc2_alarm - } -} -#[doc = "FRC1_LOAD (rw) register accessor: the load value into the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_load::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc1_load`] module"] -pub type FRC1_LOAD = crate::Reg; -#[doc = "the load value into the counter"] -pub mod frc1_load; -#[doc = "FRC1_COUNT (r) register accessor: the current value of the counter. It is a decreasingcounter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_count::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc1_count`] module"] -pub type FRC1_COUNT = crate::Reg; -#[doc = "the current value of the counter. It is a decreasingcounter."] -pub mod frc1_count; -#[doc = "FRC1_CTRL (rw) register accessor: FRC1_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc1_ctrl`] module"] -pub type FRC1_CTRL = crate::Reg; -#[doc = "FRC1_CTRL"] -pub mod frc1_ctrl; -#[doc = "FRC1_INT (rw) register accessor: FRC1_INT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_int::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc1_int`] module"] -pub type FRC1_INT = crate::Reg; -#[doc = "FRC1_INT"] -pub mod frc1_int; -#[doc = "FRC2_LOAD (rw) register accessor: the load value into the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_load::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc2_load`] module"] -pub type FRC2_LOAD = crate::Reg; -#[doc = "the load value into the counter"] -pub mod frc2_load; -#[doc = "FRC2_COUNT (r) register accessor: the current value of the counter. It is a increasingcounter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_count::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc2_count`] module"] -pub type FRC2_COUNT = crate::Reg; -#[doc = "the current value of the counter. It is a increasingcounter."] -pub mod frc2_count; -#[doc = "FRC2_CTRL (rw) register accessor: FRC2_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc2_ctrl`] module"] -pub type FRC2_CTRL = crate::Reg; -#[doc = "FRC2_CTRL"] -pub mod frc2_ctrl; -#[doc = "FRC2_INT (rw) register accessor: FRC2_INT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_int::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc2_int`] module"] -pub type FRC2_INT = crate::Reg; -#[doc = "FRC2_INT"] -pub mod frc2_int; -#[doc = "FRC2_ALARM (rw) register accessor: the alarm value for the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_alarm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_alarm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frc2_alarm`] module"] -pub type FRC2_ALARM = crate::Reg; -#[doc = "the alarm value for the counter"] -pub mod frc2_alarm; diff --git a/esp8266/src/timer/frc1_count.rs b/esp8266/src/timer/frc1_count.rs deleted file mode 100644 index 815757575f..0000000000 --- a/esp8266/src/timer/frc1_count.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `FRC1_COUNT` reader"] -pub type R = crate::R; -#[doc = "Field `frc1_count` reader - the current value of the counter. It is a decreasingcounter."] -pub type FRC1_COUNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:22 - the current value of the counter. It is a decreasingcounter."] - #[inline(always)] - pub fn frc1_count(&self) -> FRC1_COUNT_R { - FRC1_COUNT_R::new(self.bits & 0x007f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC1_COUNT") - .field("frc1_count", &format_args!("{}", self.frc1_count().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "the current value of the counter. It is a decreasingcounter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_count::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC1_COUNT_SPEC; -impl crate::RegisterSpec for FRC1_COUNT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc1_count::R`](R) reader structure"] -impl crate::Readable for FRC1_COUNT_SPEC {} -#[doc = "`reset()` method sets FRC1_COUNT to value 0"] -impl crate::Resettable for FRC1_COUNT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc1_ctrl.rs b/esp8266/src/timer/frc1_ctrl.rs deleted file mode 100644 index 4ee73896f5..0000000000 --- a/esp8266/src/timer/frc1_ctrl.rs +++ /dev/null @@ -1,261 +0,0 @@ -#[doc = "Register `FRC1_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `FRC1_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `frc1_ctrl` reader - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] -pub type FRC1_CTRL_R = crate::FieldReader; -#[doc = "Field `frc1_ctrl` writer - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] -pub type FRC1_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `interrupt_type` reader - Configure the interrupt type"] -pub type INTERRUPT_TYPE_R = crate::BitReader; -#[doc = "Configure the interrupt type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum INTERRUPT_TYPE_A { - #[doc = "0: edge"] - EDGE = 0, - #[doc = "1: level"] - LEVEL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: INTERRUPT_TYPE_A) -> Self { - variant as u8 != 0 - } -} -impl INTERRUPT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> INTERRUPT_TYPE_A { - match self.bits { - false => INTERRUPT_TYPE_A::EDGE, - true => INTERRUPT_TYPE_A::LEVEL, - } - } - #[doc = "edge"] - #[inline(always)] - pub fn is_edge(&self) -> bool { - *self == INTERRUPT_TYPE_A::EDGE - } - #[doc = "level"] - #[inline(always)] - pub fn is_level(&self) -> bool { - *self == INTERRUPT_TYPE_A::LEVEL - } -} -#[doc = "Field `interrupt_type` writer - Configure the interrupt type"] -pub type INTERRUPT_TYPE_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_TYPE_A>; -impl<'a, REG> INTERRUPT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "edge"] - #[inline(always)] - pub fn edge(self) -> &'a mut crate::W { - self.variant(INTERRUPT_TYPE_A::EDGE) - } - #[doc = "level"] - #[inline(always)] - pub fn level(self) -> &'a mut crate::W { - self.variant(INTERRUPT_TYPE_A::LEVEL) - } -} -#[doc = "Field `prescale_divider` reader - Pre-scale divider for the timer"] -pub type PRESCALE_DIVIDER_R = crate::FieldReader; -#[doc = "Pre-scale divider for the timer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum PRESCALE_DIVIDER_A { - #[doc = "0: divided by 1"] - DEVIDED_BY_1 = 0, - #[doc = "1: divided by 16"] - DEVIDED_BY_16 = 1, - #[doc = "2: divided by 256"] - DEVIDED_BY_256 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: PRESCALE_DIVIDER_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for PRESCALE_DIVIDER_A { - type Ux = u8; -} -impl PRESCALE_DIVIDER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_1), - 1 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_16), - 2 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_256), - _ => None, - } - } - #[doc = "divided by 1"] - #[inline(always)] - pub fn is_devided_by_1(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_1 - } - #[doc = "divided by 16"] - #[inline(always)] - pub fn is_devided_by_16(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_16 - } - #[doc = "divided by 256"] - #[inline(always)] - pub fn is_devided_by_256(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_256 - } -} -#[doc = "Field `prescale_divider` writer - Pre-scale divider for the timer"] -pub type PRESCALE_DIVIDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PRESCALE_DIVIDER_A>; -impl<'a, REG> PRESCALE_DIVIDER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "divided by 1"] - #[inline(always)] - pub fn devided_by_1(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_1) - } - #[doc = "divided by 16"] - #[inline(always)] - pub fn devided_by_16(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_16) - } - #[doc = "divided by 256"] - #[inline(always)] - pub fn devided_by_256(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_256) - } -} -#[doc = "Field `rollover` reader - Automatically reload when the counter hits zero"] -pub type ROLLOVER_R = crate::BitReader; -#[doc = "Field `rollover` writer - Automatically reload when the counter hits zero"] -pub type ROLLOVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `timer_enable` reader - Enable or disable the timer"] -pub type TIMER_ENABLE_R = crate::BitReader; -#[doc = "Field `timer_enable` writer - Enable or disable the timer"] -pub type TIMER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frc1_int` reader - the status of the interrupt, when the count isdereased to zero"] -pub type FRC1_INT_R = crate::BitReader; -impl R { - #[doc = "Bits 0:7 - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] - #[inline(always)] - pub fn frc1_ctrl(&self) -> FRC1_CTRL_R { - FRC1_CTRL_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 0 - Configure the interrupt type"] - #[inline(always)] - pub fn interrupt_type(&self) -> INTERRUPT_TYPE_R { - INTERRUPT_TYPE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - Pre-scale divider for the timer"] - #[inline(always)] - pub fn prescale_divider(&self) -> PRESCALE_DIVIDER_R { - PRESCALE_DIVIDER_R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 6 - Automatically reload when the counter hits zero"] - #[inline(always)] - pub fn rollover(&self) -> ROLLOVER_R { - ROLLOVER_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Enable or disable the timer"] - #[inline(always)] - pub fn timer_enable(&self) -> TIMER_ENABLE_R { - TIMER_ENABLE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - the status of the interrupt, when the count isdereased to zero"] - #[inline(always)] - pub fn frc1_int(&self) -> FRC1_INT_R { - FRC1_INT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC1_CTRL") - .field("frc1_int", &format_args!("{}", self.frc1_int().bit())) - .field("frc1_ctrl", &format_args!("{}", self.frc1_ctrl().bits())) - .field( - "timer_enable", - &format_args!("{}", self.timer_enable().bit()), - ) - .field("rollover", &format_args!("{}", self.rollover().bit())) - .field( - "prescale_divider", - &format_args!("{}", self.prescale_divider().bits()), - ) - .field( - "interrupt_type", - &format_args!("{}", self.interrupt_type().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] - #[inline(always)] - #[must_use] - pub fn frc1_ctrl(&mut self) -> FRC1_CTRL_W { - FRC1_CTRL_W::new(self, 0) - } - #[doc = "Bit 0 - Configure the interrupt type"] - #[inline(always)] - #[must_use] - pub fn interrupt_type(&mut self) -> INTERRUPT_TYPE_W { - INTERRUPT_TYPE_W::new(self, 0) - } - #[doc = "Bits 2:3 - Pre-scale divider for the timer"] - #[inline(always)] - #[must_use] - pub fn prescale_divider(&mut self) -> PRESCALE_DIVIDER_W { - PRESCALE_DIVIDER_W::new(self, 2) - } - #[doc = "Bit 6 - Automatically reload when the counter hits zero"] - #[inline(always)] - #[must_use] - pub fn rollover(&mut self) -> ROLLOVER_W { - ROLLOVER_W::new(self, 6) - } - #[doc = "Bit 7 - Enable or disable the timer"] - #[inline(always)] - #[must_use] - pub fn timer_enable(&mut self) -> TIMER_ENABLE_W { - TIMER_ENABLE_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "FRC1_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC1_CTRL_SPEC; -impl crate::RegisterSpec for FRC1_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc1_ctrl::R`](R) reader structure"] -impl crate::Readable for FRC1_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc1_ctrl::W`](W) writer structure"] -impl crate::Writable for FRC1_CTRL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC1_CTRL to value 0"] -impl crate::Resettable for FRC1_CTRL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc1_int.rs b/esp8266/src/timer/frc1_int.rs deleted file mode 100644 index 2ad8ee65f8..0000000000 --- a/esp8266/src/timer/frc1_int.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `FRC1_INT` reader"] -pub type R = crate::R; -#[doc = "Register `FRC1_INT` writer"] -pub type W = crate::W; -#[doc = "Field `frc1_int_clr_mask` reader - write to clear the status of the interrupt, if theinterrupt type is \"level\""] -pub type FRC1_INT_CLR_MASK_R = crate::BitReader; -#[doc = "Field `frc1_int_clr_mask` writer - write to clear the status of the interrupt, if theinterrupt type is \"level\""] -pub type FRC1_INT_CLR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - write to clear the status of the interrupt, if theinterrupt type is \"level\""] - #[inline(always)] - pub fn frc1_int_clr_mask(&self) -> FRC1_INT_CLR_MASK_R { - FRC1_INT_CLR_MASK_R::new((self.bits & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC1_INT") - .field( - "frc1_int_clr_mask", - &format_args!("{}", self.frc1_int_clr_mask().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - write to clear the status of the interrupt, if theinterrupt type is \"level\""] - #[inline(always)] - #[must_use] - pub fn frc1_int_clr_mask(&mut self) -> FRC1_INT_CLR_MASK_W { - FRC1_INT_CLR_MASK_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "FRC1_INT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_int::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC1_INT_SPEC; -impl crate::RegisterSpec for FRC1_INT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc1_int::R`](R) reader structure"] -impl crate::Readable for FRC1_INT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc1_int::W`](W) writer structure"] -impl crate::Writable for FRC1_INT_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC1_INT to value 0"] -impl crate::Resettable for FRC1_INT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc1_load.rs b/esp8266/src/timer/frc1_load.rs deleted file mode 100644 index 43361501fc..0000000000 --- a/esp8266/src/timer/frc1_load.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `FRC1_LOAD` reader"] -pub type R = crate::R; -#[doc = "Register `FRC1_LOAD` writer"] -pub type W = crate::W; -#[doc = "Field `frc1_load_value` reader - the load value into the counter"] -pub type FRC1_LOAD_VALUE_R = crate::FieldReader; -#[doc = "Field `frc1_load_value` writer - the load value into the counter"] -pub type FRC1_LOAD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; -impl R { - #[doc = "Bits 0:22 - the load value into the counter"] - #[inline(always)] - pub fn frc1_load_value(&self) -> FRC1_LOAD_VALUE_R { - FRC1_LOAD_VALUE_R::new(self.bits & 0x007f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC1_LOAD") - .field( - "frc1_load_value", - &format_args!("{}", self.frc1_load_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:22 - the load value into the counter"] - #[inline(always)] - #[must_use] - pub fn frc1_load_value(&mut self) -> FRC1_LOAD_VALUE_W { - FRC1_LOAD_VALUE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the load value into the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc1_load::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc1_load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC1_LOAD_SPEC; -impl crate::RegisterSpec for FRC1_LOAD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc1_load::R`](R) reader structure"] -impl crate::Readable for FRC1_LOAD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc1_load::W`](W) writer structure"] -impl crate::Writable for FRC1_LOAD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC1_LOAD to value 0"] -impl crate::Resettable for FRC1_LOAD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc2_alarm.rs b/esp8266/src/timer/frc2_alarm.rs deleted file mode 100644 index 9524dd0d19..0000000000 --- a/esp8266/src/timer/frc2_alarm.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `FRC2_ALARM` reader"] -pub type R = crate::R; -#[doc = "Register `FRC2_ALARM` writer"] -pub type W = crate::W; -#[doc = "Field `frc2_alarm` reader - the alarm value for the counter"] -pub type FRC2_ALARM_R = crate::FieldReader; -#[doc = "Field `frc2_alarm` writer - the alarm value for the counter"] -pub type FRC2_ALARM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the alarm value for the counter"] - #[inline(always)] - pub fn frc2_alarm(&self) -> FRC2_ALARM_R { - FRC2_ALARM_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC2_ALARM") - .field("frc2_alarm", &format_args!("{}", self.frc2_alarm().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the alarm value for the counter"] - #[inline(always)] - #[must_use] - pub fn frc2_alarm(&mut self) -> FRC2_ALARM_W { - FRC2_ALARM_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the alarm value for the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_alarm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_alarm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC2_ALARM_SPEC; -impl crate::RegisterSpec for FRC2_ALARM_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc2_alarm::R`](R) reader structure"] -impl crate::Readable for FRC2_ALARM_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc2_alarm::W`](W) writer structure"] -impl crate::Writable for FRC2_ALARM_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC2_ALARM to value 0"] -impl crate::Resettable for FRC2_ALARM_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc2_count.rs b/esp8266/src/timer/frc2_count.rs deleted file mode 100644 index 72b14ccfba..0000000000 --- a/esp8266/src/timer/frc2_count.rs +++ /dev/null @@ -1,36 +0,0 @@ -#[doc = "Register `FRC2_COUNT` reader"] -pub type R = crate::R; -#[doc = "Field `frc2_count` reader - the current value of the counter. It is a increasingcounter."] -pub type FRC2_COUNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:31 - the current value of the counter. It is a increasingcounter."] - #[inline(always)] - pub fn frc2_count(&self) -> FRC2_COUNT_R { - FRC2_COUNT_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC2_COUNT") - .field("frc2_count", &format_args!("{}", self.frc2_count().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "the current value of the counter. It is a increasingcounter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_count::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC2_COUNT_SPEC; -impl crate::RegisterSpec for FRC2_COUNT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc2_count::R`](R) reader structure"] -impl crate::Readable for FRC2_COUNT_SPEC {} -#[doc = "`reset()` method sets FRC2_COUNT to value 0"] -impl crate::Resettable for FRC2_COUNT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc2_ctrl.rs b/esp8266/src/timer/frc2_ctrl.rs deleted file mode 100644 index 45cdf1b549..0000000000 --- a/esp8266/src/timer/frc2_ctrl.rs +++ /dev/null @@ -1,261 +0,0 @@ -#[doc = "Register `FRC2_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `FRC2_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `frc2_ctrl` reader - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] -pub type FRC2_CTRL_R = crate::FieldReader; -#[doc = "Field `frc2_ctrl` writer - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] -pub type FRC2_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `interrupt_type` reader - Configure the interrupt type"] -pub type INTERRUPT_TYPE_R = crate::BitReader; -#[doc = "Configure the interrupt type\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum INTERRUPT_TYPE_A { - #[doc = "0: edge"] - EDGE = 0, - #[doc = "1: level"] - LEVEL = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: INTERRUPT_TYPE_A) -> Self { - variant as u8 != 0 - } -} -impl INTERRUPT_TYPE_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> INTERRUPT_TYPE_A { - match self.bits { - false => INTERRUPT_TYPE_A::EDGE, - true => INTERRUPT_TYPE_A::LEVEL, - } - } - #[doc = "edge"] - #[inline(always)] - pub fn is_edge(&self) -> bool { - *self == INTERRUPT_TYPE_A::EDGE - } - #[doc = "level"] - #[inline(always)] - pub fn is_level(&self) -> bool { - *self == INTERRUPT_TYPE_A::LEVEL - } -} -#[doc = "Field `interrupt_type` writer - Configure the interrupt type"] -pub type INTERRUPT_TYPE_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_TYPE_A>; -impl<'a, REG> INTERRUPT_TYPE_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "edge"] - #[inline(always)] - pub fn edge(self) -> &'a mut crate::W { - self.variant(INTERRUPT_TYPE_A::EDGE) - } - #[doc = "level"] - #[inline(always)] - pub fn level(self) -> &'a mut crate::W { - self.variant(INTERRUPT_TYPE_A::LEVEL) - } -} -#[doc = "Field `prescale_divider` reader - Pre-scale divider for the timer"] -pub type PRESCALE_DIVIDER_R = crate::FieldReader; -#[doc = "Pre-scale divider for the timer\n\nValue on reset: 0"] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum PRESCALE_DIVIDER_A { - #[doc = "0: divided by 1"] - DEVIDED_BY_1 = 0, - #[doc = "1: divided by 16"] - DEVIDED_BY_16 = 1, - #[doc = "2: divided by 256"] - DEVIDED_BY_256 = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: PRESCALE_DIVIDER_A) -> Self { - variant as _ - } -} -impl crate::FieldSpec for PRESCALE_DIVIDER_A { - type Ux = u8; -} -impl PRESCALE_DIVIDER_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_1), - 1 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_16), - 2 => Some(PRESCALE_DIVIDER_A::DEVIDED_BY_256), - _ => None, - } - } - #[doc = "divided by 1"] - #[inline(always)] - pub fn is_devided_by_1(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_1 - } - #[doc = "divided by 16"] - #[inline(always)] - pub fn is_devided_by_16(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_16 - } - #[doc = "divided by 256"] - #[inline(always)] - pub fn is_devided_by_256(&self) -> bool { - *self == PRESCALE_DIVIDER_A::DEVIDED_BY_256 - } -} -#[doc = "Field `prescale_divider` writer - Pre-scale divider for the timer"] -pub type PRESCALE_DIVIDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PRESCALE_DIVIDER_A>; -impl<'a, REG> PRESCALE_DIVIDER_W<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "divided by 1"] - #[inline(always)] - pub fn devided_by_1(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_1) - } - #[doc = "divided by 16"] - #[inline(always)] - pub fn devided_by_16(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_16) - } - #[doc = "divided by 256"] - #[inline(always)] - pub fn devided_by_256(self) -> &'a mut crate::W { - self.variant(PRESCALE_DIVIDER_A::DEVIDED_BY_256) - } -} -#[doc = "Field `rollover` reader - Automatically reload when the counter hits zero"] -pub type ROLLOVER_R = crate::BitReader; -#[doc = "Field `rollover` writer - Automatically reload when the counter hits zero"] -pub type ROLLOVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `timer_enable` reader - Enable or disable the timer"] -pub type TIMER_ENABLE_R = crate::BitReader; -#[doc = "Field `timer_enable` writer - Enable or disable the timer"] -pub type TIMER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frc2_int` reader - the status of the interrupt, when the count is equal tothe alarm value"] -pub type FRC2_INT_R = crate::BitReader; -impl R { - #[doc = "Bits 0:7 - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] - #[inline(always)] - pub fn frc2_ctrl(&self) -> FRC2_CTRL_R { - FRC2_CTRL_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 0 - Configure the interrupt type"] - #[inline(always)] - pub fn interrupt_type(&self) -> INTERRUPT_TYPE_R { - INTERRUPT_TYPE_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - Pre-scale divider for the timer"] - #[inline(always)] - pub fn prescale_divider(&self) -> PRESCALE_DIVIDER_R { - PRESCALE_DIVIDER_R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bit 6 - Automatically reload when the counter hits zero"] - #[inline(always)] - pub fn rollover(&self) -> ROLLOVER_R { - ROLLOVER_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Enable or disable the timer"] - #[inline(always)] - pub fn timer_enable(&self) -> TIMER_ENABLE_R { - TIMER_ENABLE_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - the status of the interrupt, when the count is equal tothe alarm value"] - #[inline(always)] - pub fn frc2_int(&self) -> FRC2_INT_R { - FRC2_INT_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC2_CTRL") - .field("frc2_int", &format_args!("{}", self.frc2_int().bit())) - .field("frc2_ctrl", &format_args!("{}", self.frc2_ctrl().bits())) - .field( - "timer_enable", - &format_args!("{}", self.timer_enable().bit()), - ) - .field("rollover", &format_args!("{}", self.rollover().bit())) - .field( - "prescale_divider", - &format_args!("{}", self.prescale_divider().bits()), - ) - .field( - "interrupt_type", - &format_args!("{}", self.interrupt_type().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - bit\\[7\\]: timer enable, bit\\[6\\]: automatically reload, when the counter isequal to zero, bit\\[3:2\\]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit\\[0\\]: interrupt type, 0:edge, 1:level"] - #[inline(always)] - #[must_use] - pub fn frc2_ctrl(&mut self) -> FRC2_CTRL_W { - FRC2_CTRL_W::new(self, 0) - } - #[doc = "Bit 0 - Configure the interrupt type"] - #[inline(always)] - #[must_use] - pub fn interrupt_type(&mut self) -> INTERRUPT_TYPE_W { - INTERRUPT_TYPE_W::new(self, 0) - } - #[doc = "Bits 2:3 - Pre-scale divider for the timer"] - #[inline(always)] - #[must_use] - pub fn prescale_divider(&mut self) -> PRESCALE_DIVIDER_W { - PRESCALE_DIVIDER_W::new(self, 2) - } - #[doc = "Bit 6 - Automatically reload when the counter hits zero"] - #[inline(always)] - #[must_use] - pub fn rollover(&mut self) -> ROLLOVER_W { - ROLLOVER_W::new(self, 6) - } - #[doc = "Bit 7 - Enable or disable the timer"] - #[inline(always)] - #[must_use] - pub fn timer_enable(&mut self) -> TIMER_ENABLE_W { - TIMER_ENABLE_W::new(self, 7) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "FRC2_CTRL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC2_CTRL_SPEC; -impl crate::RegisterSpec for FRC2_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc2_ctrl::R`](R) reader structure"] -impl crate::Readable for FRC2_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc2_ctrl::W`](W) writer structure"] -impl crate::Writable for FRC2_CTRL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC2_CTRL to value 0"] -impl crate::Resettable for FRC2_CTRL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc2_int.rs b/esp8266/src/timer/frc2_int.rs deleted file mode 100644 index e41f5baf02..0000000000 --- a/esp8266/src/timer/frc2_int.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `FRC2_INT` reader"] -pub type R = crate::R; -#[doc = "Register `FRC2_INT` writer"] -pub type W = crate::W; -#[doc = "Field `frc2_int_clr_mask` reader - write to clear the status of the interrupt, if theinterrupt type is \"level\""] -pub type FRC2_INT_CLR_MASK_R = crate::BitReader; -#[doc = "Field `frc2_int_clr_mask` writer - write to clear the status of the interrupt, if theinterrupt type is \"level\""] -pub type FRC2_INT_CLR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - write to clear the status of the interrupt, if theinterrupt type is \"level\""] - #[inline(always)] - pub fn frc2_int_clr_mask(&self) -> FRC2_INT_CLR_MASK_R { - FRC2_INT_CLR_MASK_R::new((self.bits & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC2_INT") - .field( - "frc2_int_clr_mask", - &format_args!("{}", self.frc2_int_clr_mask().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - write to clear the status of the interrupt, if theinterrupt type is \"level\""] - #[inline(always)] - #[must_use] - pub fn frc2_int_clr_mask(&mut self) -> FRC2_INT_CLR_MASK_W { - FRC2_INT_CLR_MASK_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "FRC2_INT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_int::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC2_INT_SPEC; -impl crate::RegisterSpec for FRC2_INT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc2_int::R`](R) reader structure"] -impl crate::Readable for FRC2_INT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc2_int::W`](W) writer structure"] -impl crate::Writable for FRC2_INT_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC2_INT to value 0"] -impl crate::Resettable for FRC2_INT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/timer/frc2_load.rs b/esp8266/src/timer/frc2_load.rs deleted file mode 100644 index 5d329543ca..0000000000 --- a/esp8266/src/timer/frc2_load.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `FRC2_LOAD` reader"] -pub type R = crate::R; -#[doc = "Register `FRC2_LOAD` writer"] -pub type W = crate::W; -#[doc = "Field `frc2_load_value` reader - the load value into the counter"] -pub type FRC2_LOAD_VALUE_R = crate::FieldReader; -#[doc = "Field `frc2_load_value` writer - the load value into the counter"] -pub type FRC2_LOAD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - the load value into the counter"] - #[inline(always)] - pub fn frc2_load_value(&self) -> FRC2_LOAD_VALUE_R { - FRC2_LOAD_VALUE_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FRC2_LOAD") - .field( - "frc2_load_value", - &format_args!("{}", self.frc2_load_value().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - the load value into the counter"] - #[inline(always)] - #[must_use] - pub fn frc2_load_value(&mut self) -> FRC2_LOAD_VALUE_W { - FRC2_LOAD_VALUE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "the load value into the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frc2_load::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frc2_load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct FRC2_LOAD_SPEC; -impl crate::RegisterSpec for FRC2_LOAD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`frc2_load::R`](R) reader structure"] -impl crate::Readable for FRC2_LOAD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`frc2_load::W`](W) writer structure"] -impl crate::Writable for FRC2_LOAD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets FRC2_LOAD to value 0"] -impl crate::Resettable for FRC2_LOAD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0.rs b/esp8266/src/uart0.rs deleted file mode 100644 index bf0effa538..0000000000 --- a/esp8266/src/uart0.rs +++ /dev/null @@ -1,158 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - uart_fifo: UART_FIFO, - uart_int_raw: UART_INT_RAW, - uart_int_st: UART_INT_ST, - uart_int_ena: UART_INT_ENA, - uart_int_clr: UART_INT_CLR, - uart_clkdiv: UART_CLKDIV, - uart_autobaud: UART_AUTOBAUD, - uart_status: UART_STATUS, - uart_conf0: UART_CONF0, - uart_conf1: UART_CONF1, - uart_lowpulse: UART_LOWPULSE, - uart_highpulse: UART_HIGHPULSE, - uart_rxd_cnt: UART_RXD_CNT, - _reserved13: [u8; 0x44], - uart_date: UART_DATE, - uart_id: UART_ID, -} -impl RegisterBlock { - #[doc = "0x00 - UART FIFO,length 128"] - #[inline(always)] - pub const fn uart_fifo(&self) -> &UART_FIFO { - &self.uart_fifo - } - #[doc = "0x04 - UART INTERRUPT RAW STATE"] - #[inline(always)] - pub const fn uart_int_raw(&self) -> &UART_INT_RAW { - &self.uart_int_raw - } - #[doc = "0x08 - UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] - #[inline(always)] - pub const fn uart_int_st(&self) -> &UART_INT_ST { - &self.uart_int_st - } - #[doc = "0x0c - UART INTERRUPT ENABLE REGISTER"] - #[inline(always)] - pub const fn uart_int_ena(&self) -> &UART_INT_ENA { - &self.uart_int_ena - } - #[doc = "0x10 - UART INTERRUPT CLEAR REGISTER"] - #[inline(always)] - pub const fn uart_int_clr(&self) -> &UART_INT_CLR { - &self.uart_int_clr - } - #[doc = "0x14 - UART CLK DIV REGISTER"] - #[inline(always)] - pub const fn uart_clkdiv(&self) -> &UART_CLKDIV { - &self.uart_clkdiv - } - #[doc = "0x18 - UART BAUDRATE DETECT REGISTER"] - #[inline(always)] - pub const fn uart_autobaud(&self) -> &UART_AUTOBAUD { - &self.uart_autobaud - } - #[doc = "0x1c - UART STATUS REGISTER"] - #[inline(always)] - pub const fn uart_status(&self) -> &UART_STATUS { - &self.uart_status - } - #[doc = "0x20 - UART CONFIG0(UART0 and UART1)"] - #[inline(always)] - pub const fn uart_conf0(&self) -> &UART_CONF0 { - &self.uart_conf0 - } - #[doc = "0x24 - Set this bit to enable rx time-out function"] - #[inline(always)] - pub const fn uart_conf1(&self) -> &UART_CONF1 { - &self.uart_conf1 - } - #[doc = "0x28 - UART_LOWPULSE"] - #[inline(always)] - pub const fn uart_lowpulse(&self) -> &UART_LOWPULSE { - &self.uart_lowpulse - } - #[doc = "0x2c - UART_HIGHPULSE"] - #[inline(always)] - pub const fn uart_highpulse(&self) -> &UART_HIGHPULSE { - &self.uart_highpulse - } - #[doc = "0x30 - UART_RXD_CNT"] - #[inline(always)] - pub const fn uart_rxd_cnt(&self) -> &UART_RXD_CNT { - &self.uart_rxd_cnt - } - #[doc = "0x78 - UART HW INFO"] - #[inline(always)] - pub const fn uart_date(&self) -> &UART_DATE { - &self.uart_date - } - #[doc = "0x7c - UART_ID"] - #[inline(always)] - pub const fn uart_id(&self) -> &UART_ID { - &self.uart_id - } -} -#[doc = "UART_FIFO (rw) register accessor: UART FIFO,length 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_fifo`] module"] -pub type UART_FIFO = crate::Reg; -#[doc = "UART FIFO,length 128"] -pub mod uart_fifo; -#[doc = "UART_INT_RAW (r) register accessor: UART INTERRUPT RAW STATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_raw`] module"] -pub type UART_INT_RAW = crate::Reg; -#[doc = "UART INTERRUPT RAW STATE"] -pub mod uart_int_raw; -#[doc = "UART_INT_ST (r) register accessor: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_st`] module"] -pub type UART_INT_ST = crate::Reg; -#[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] -pub mod uart_int_st; -#[doc = "UART_INT_ENA (rw) register accessor: UART INTERRUPT ENABLE REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_ena`] module"] -pub type UART_INT_ENA = crate::Reg; -#[doc = "UART INTERRUPT ENABLE REGISTER"] -pub mod uart_int_ena; -#[doc = "UART_INT_CLR (w) register accessor: UART INTERRUPT CLEAR REGISTER\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_clr`] module"] -pub type UART_INT_CLR = crate::Reg; -#[doc = "UART INTERRUPT CLEAR REGISTER"] -pub mod uart_int_clr; -#[doc = "UART_CLKDIV (rw) register accessor: UART CLK DIV REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_clkdiv`] module"] -pub type UART_CLKDIV = crate::Reg; -#[doc = "UART CLK DIV REGISTER"] -pub mod uart_clkdiv; -#[doc = "UART_AUTOBAUD (rw) register accessor: UART BAUDRATE DETECT REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_autobaud::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_autobaud::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_autobaud`] module"] -pub type UART_AUTOBAUD = crate::Reg; -#[doc = "UART BAUDRATE DETECT REGISTER"] -pub mod uart_autobaud; -#[doc = "UART_STATUS (r) register accessor: UART STATUS REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_status`] module"] -pub type UART_STATUS = crate::Reg; -#[doc = "UART STATUS REGISTER"] -pub mod uart_status; -#[doc = "UART_CONF0 (rw) register accessor: UART CONFIG0(UART0 and UART1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_conf0`] module"] -pub type UART_CONF0 = crate::Reg; -#[doc = "UART CONFIG0(UART0 and UART1)"] -pub mod uart_conf0; -#[doc = "UART_CONF1 (rw) register accessor: Set this bit to enable rx time-out function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_conf1`] module"] -pub type UART_CONF1 = crate::Reg; -#[doc = "Set this bit to enable rx time-out function"] -pub mod uart_conf1; -#[doc = "UART_LOWPULSE (r) register accessor: UART_LOWPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_lowpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_lowpulse`] module"] -pub type UART_LOWPULSE = crate::Reg; -#[doc = "UART_LOWPULSE"] -pub mod uart_lowpulse; -#[doc = "UART_HIGHPULSE (r) register accessor: UART_HIGHPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_highpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_highpulse`] module"] -pub type UART_HIGHPULSE = crate::Reg; -#[doc = "UART_HIGHPULSE"] -pub mod uart_highpulse; -#[doc = "UART_RXD_CNT (r) register accessor: UART_RXD_CNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_rxd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_rxd_cnt`] module"] -pub type UART_RXD_CNT = crate::Reg; -#[doc = "UART_RXD_CNT"] -pub mod uart_rxd_cnt; -#[doc = "UART_DATE (rw) register accessor: UART HW INFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_date`] module"] -pub type UART_DATE = crate::Reg; -#[doc = "UART HW INFO"] -pub mod uart_date; -#[doc = "UART_ID (rw) register accessor: UART_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_id`] module"] -pub type UART_ID = crate::Reg; -#[doc = "UART_ID"] -pub mod uart_id; diff --git a/esp8266/src/uart0/uart_autobaud.rs b/esp8266/src/uart0/uart_autobaud.rs deleted file mode 100644 index 8509d7b088..0000000000 --- a/esp8266/src/uart0/uart_autobaud.rs +++ /dev/null @@ -1,82 +0,0 @@ -#[doc = "Register `UART_AUTOBAUD` reader"] -pub type R = crate::R; -#[doc = "Register `UART_AUTOBAUD` writer"] -pub type W = crate::W; -#[doc = "Field `autobaud_en` reader - Set this bit to enable baudrate detect"] -pub type AUTOBAUD_EN_R = crate::BitReader; -#[doc = "Field `autobaud_en` writer - Set this bit to enable baudrate detect"] -pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `glitch_filt` reader - "] -pub type GLITCH_FILT_R = crate::FieldReader; -#[doc = "Field `glitch_filt` writer - "] -pub type GLITCH_FILT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bit 0 - Set this bit to enable baudrate detect"] - #[inline(always)] - pub fn autobaud_en(&self) -> AUTOBAUD_EN_R { - AUTOBAUD_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 8:15"] - #[inline(always)] - pub fn glitch_filt(&self) -> GLITCH_FILT_R { - GLITCH_FILT_R::new(((self.bits >> 8) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_AUTOBAUD") - .field( - "glitch_filt", - &format_args!("{}", self.glitch_filt().bits()), - ) - .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Set this bit to enable baudrate detect"] - #[inline(always)] - #[must_use] - pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W { - AUTOBAUD_EN_W::new(self, 0) - } - #[doc = "Bits 8:15"] - #[inline(always)] - #[must_use] - pub fn glitch_filt(&mut self) -> GLITCH_FILT_W { - GLITCH_FILT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART BAUDRATE DETECT REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_autobaud::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_autobaud::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_AUTOBAUD_SPEC; -impl crate::RegisterSpec for UART_AUTOBAUD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_autobaud::R`](R) reader structure"] -impl crate::Readable for UART_AUTOBAUD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_autobaud::W`](W) writer structure"] -impl crate::Writable for UART_AUTOBAUD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_AUTOBAUD to value 0"] -impl crate::Resettable for UART_AUTOBAUD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_clkdiv.rs b/esp8266/src/uart0/uart_clkdiv.rs deleted file mode 100644 index 71587c41d2..0000000000 --- a/esp8266/src/uart0/uart_clkdiv.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `UART_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `uart_clkdiv` reader - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] -pub type UART_CLKDIV_R = crate::FieldReader; -#[doc = "Field `uart_clkdiv` writer - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] -pub type UART_CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -impl R { - #[doc = "Bits 0:19 - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] - #[inline(always)] - pub fn uart_clkdiv(&self) -> UART_CLKDIV_R { - UART_CLKDIV_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CLKDIV") - .field( - "uart_clkdiv", - &format_args!("{}", self.uart_clkdiv().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:19 - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] - #[inline(always)] - #[must_use] - pub fn uart_clkdiv(&mut self) -> UART_CLKDIV_W { - UART_CLKDIV_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART CLK DIV REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CLKDIV_SPEC; -impl crate::RegisterSpec for UART_CLKDIV_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_clkdiv::R`](R) reader structure"] -impl crate::Readable for UART_CLKDIV_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_clkdiv::W`](W) writer structure"] -impl crate::Writable for UART_CLKDIV_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CLKDIV to value 0"] -impl crate::Resettable for UART_CLKDIV_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_conf0.rs b/esp8266/src/uart0/uart_conf0.rs deleted file mode 100644 index 84406bbd28..0000000000 --- a/esp8266/src/uart0/uart_conf0.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `UART_CONF0` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CONF0` writer"] -pub type W = crate::W; -#[doc = "Field `parity` reader - Set parity check: 0:even 1:odd, UART CONFIG1"] -pub type PARITY_R = crate::BitReader; -#[doc = "Field `parity` writer - Set parity check: 0:even 1:odd, UART CONFIG1"] -pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_en` reader - Set this bit to enable uart parity check"] -pub type PARITY_EN_R = crate::BitReader; -#[doc = "Field `parity_en` writer - Set this bit to enable uart parity check"] -pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `bit_num` reader - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] -pub type BIT_NUM_R = crate::FieldReader; -#[doc = "Field `bit_num` writer - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] -pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `stop_bit_num` reader - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] -pub type STOP_BIT_NUM_R = crate::FieldReader; -#[doc = "Field `stop_bit_num` writer - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] -pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `sw_rts` reader - sw rts"] -pub type SW_RTS_R = crate::BitReader; -#[doc = "Field `sw_rts` writer - sw rts"] -pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sw_dtr` reader - sw dtr"] -pub type SW_DTR_R = crate::BitReader; -#[doc = "Field `sw_dtr` writer - sw dtr"] -pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txd_brk` reader - RESERVED, DO NOT CHANGE THIS BIT"] -pub type TXD_BRK_R = crate::BitReader; -#[doc = "Field `txd_brk` writer - RESERVED, DO NOT CHANGE THIS BIT"] -pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_loopback` reader - Set this bit to enable uart loopback test mode"] -pub type UART_LOOPBACK_R = crate::BitReader; -#[doc = "Field `uart_loopback` writer - Set this bit to enable uart loopback test mode"] -pub type UART_LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `tx_flow_en` reader - Set this bit to enable uart tx hardware flow control"] -pub type TX_FLOW_EN_R = crate::BitReader; -#[doc = "Field `tx_flow_en` writer - Set this bit to enable uart tx hardware flow control"] -pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_rst` reader - Set this bit to reset uart rx fifo"] -pub type RXFIFO_RST_R = crate::BitReader; -#[doc = "Field `rxfifo_rst` writer - Set this bit to reset uart rx fifo"] -pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_rst` reader - Set this bit to reset uart tx fifo"] -pub type TXFIFO_RST_R = crate::BitReader; -#[doc = "Field `txfifo_rst` writer - Set this bit to reset uart tx fifo"] -pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_rxd_inv` reader - Set this bit to inverse uart rxd level"] -pub type UART_RXD_INV_R = crate::BitReader; -#[doc = "Field `uart_rxd_inv` writer - Set this bit to inverse uart rxd level"] -pub type UART_RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_cts_inv` reader - Set this bit to inverse uart cts level"] -pub type UART_CTS_INV_R = crate::BitReader; -#[doc = "Field `uart_cts_inv` writer - Set this bit to inverse uart cts level"] -pub type UART_CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_dsr_inv` reader - Set this bit to inverse uart dsr level"] -pub type UART_DSR_INV_R = crate::BitReader; -#[doc = "Field `uart_dsr_inv` writer - Set this bit to inverse uart dsr level"] -pub type UART_DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_txd_inv` reader - Set this bit to inverse uart txd level"] -pub type UART_TXD_INV_R = crate::BitReader; -#[doc = "Field `uart_txd_inv` writer - Set this bit to inverse uart txd level"] -pub type UART_TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_rts_inv` reader - Set this bit to inverse uart rts level"] -pub type UART_RTS_INV_R = crate::BitReader; -#[doc = "Field `uart_rts_inv` writer - Set this bit to inverse uart rts level"] -pub type UART_RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_dtr_inv` reader - Set this bit to inverse uart dtr level"] -pub type UART_DTR_INV_R = crate::BitReader; -#[doc = "Field `uart_dtr_inv` writer - Set this bit to inverse uart dtr level"] -pub type UART_DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set parity check: 0:even 1:odd, UART CONFIG1"] - #[inline(always)] - pub fn parity(&self) -> PARITY_R { - PARITY_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set this bit to enable uart parity check"] - #[inline(always)] - pub fn parity_en(&self) -> PARITY_EN_R { - PARITY_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] - #[inline(always)] - pub fn bit_num(&self) -> BIT_NUM_R { - BIT_NUM_R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] - #[inline(always)] - pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R { - STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - sw rts"] - #[inline(always)] - pub fn sw_rts(&self) -> SW_RTS_R { - SW_RTS_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - sw dtr"] - #[inline(always)] - pub fn sw_dtr(&self) -> SW_DTR_R { - SW_DTR_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - RESERVED, DO NOT CHANGE THIS BIT"] - #[inline(always)] - pub fn txd_brk(&self) -> TXD_BRK_R { - TXD_BRK_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 14 - Set this bit to enable uart loopback test mode"] - #[inline(always)] - pub fn uart_loopback(&self) -> UART_LOOPBACK_R { - UART_LOOPBACK_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Set this bit to enable uart tx hardware flow control"] - #[inline(always)] - pub fn tx_flow_en(&self) -> TX_FLOW_EN_R { - TX_FLOW_EN_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 17 - Set this bit to reset uart rx fifo"] - #[inline(always)] - pub fn rxfifo_rst(&self) -> RXFIFO_RST_R { - RXFIFO_RST_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Set this bit to reset uart tx fifo"] - #[inline(always)] - pub fn txfifo_rst(&self) -> TXFIFO_RST_R { - TXFIFO_RST_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Set this bit to inverse uart rxd level"] - #[inline(always)] - pub fn uart_rxd_inv(&self) -> UART_RXD_INV_R { - UART_RXD_INV_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Set this bit to inverse uart cts level"] - #[inline(always)] - pub fn uart_cts_inv(&self) -> UART_CTS_INV_R { - UART_CTS_INV_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Set this bit to inverse uart dsr level"] - #[inline(always)] - pub fn uart_dsr_inv(&self) -> UART_DSR_INV_R { - UART_DSR_INV_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Set this bit to inverse uart txd level"] - #[inline(always)] - pub fn uart_txd_inv(&self) -> UART_TXD_INV_R { - UART_TXD_INV_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Set this bit to inverse uart rts level"] - #[inline(always)] - pub fn uart_rts_inv(&self) -> UART_RTS_INV_R { - UART_RTS_INV_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Set this bit to inverse uart dtr level"] - #[inline(always)] - pub fn uart_dtr_inv(&self) -> UART_DTR_INV_R { - UART_DTR_INV_R::new(((self.bits >> 24) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CONF0") - .field( - "uart_dtr_inv", - &format_args!("{}", self.uart_dtr_inv().bit()), - ) - .field( - "uart_rts_inv", - &format_args!("{}", self.uart_rts_inv().bit()), - ) - .field( - "uart_txd_inv", - &format_args!("{}", self.uart_txd_inv().bit()), - ) - .field( - "uart_dsr_inv", - &format_args!("{}", self.uart_dsr_inv().bit()), - ) - .field( - "uart_cts_inv", - &format_args!("{}", self.uart_cts_inv().bit()), - ) - .field( - "uart_rxd_inv", - &format_args!("{}", self.uart_rxd_inv().bit()), - ) - .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit())) - .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit())) - .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit())) - .field( - "uart_loopback", - &format_args!("{}", self.uart_loopback().bit()), - ) - .field("txd_brk", &format_args!("{}", self.txd_brk().bit())) - .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit())) - .field("sw_rts", &format_args!("{}", self.sw_rts().bit())) - .field( - "stop_bit_num", - &format_args!("{}", self.stop_bit_num().bits()), - ) - .field("bit_num", &format_args!("{}", self.bit_num().bits())) - .field("parity_en", &format_args!("{}", self.parity_en().bit())) - .field("parity", &format_args!("{}", self.parity().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Set parity check: 0:even 1:odd, UART CONFIG1"] - #[inline(always)] - #[must_use] - pub fn parity(&mut self) -> PARITY_W { - PARITY_W::new(self, 0) - } - #[doc = "Bit 1 - Set this bit to enable uart parity check"] - #[inline(always)] - #[must_use] - pub fn parity_en(&mut self) -> PARITY_EN_W { - PARITY_EN_W::new(self, 1) - } - #[doc = "Bits 2:3 - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] - #[inline(always)] - #[must_use] - pub fn bit_num(&mut self) -> BIT_NUM_W { - BIT_NUM_W::new(self, 2) - } - #[doc = "Bits 4:5 - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] - #[inline(always)] - #[must_use] - pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W { - STOP_BIT_NUM_W::new(self, 4) - } - #[doc = "Bit 6 - sw rts"] - #[inline(always)] - #[must_use] - pub fn sw_rts(&mut self) -> SW_RTS_W { - SW_RTS_W::new(self, 6) - } - #[doc = "Bit 7 - sw dtr"] - #[inline(always)] - #[must_use] - pub fn sw_dtr(&mut self) -> SW_DTR_W { - SW_DTR_W::new(self, 7) - } - #[doc = "Bit 8 - RESERVED, DO NOT CHANGE THIS BIT"] - #[inline(always)] - #[must_use] - pub fn txd_brk(&mut self) -> TXD_BRK_W { - TXD_BRK_W::new(self, 8) - } - #[doc = "Bit 14 - Set this bit to enable uart loopback test mode"] - #[inline(always)] - #[must_use] - pub fn uart_loopback(&mut self) -> UART_LOOPBACK_W { - UART_LOOPBACK_W::new(self, 14) - } - #[doc = "Bit 15 - Set this bit to enable uart tx hardware flow control"] - #[inline(always)] - #[must_use] - pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W { - TX_FLOW_EN_W::new(self, 15) - } - #[doc = "Bit 17 - Set this bit to reset uart rx fifo"] - #[inline(always)] - #[must_use] - pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W { - RXFIFO_RST_W::new(self, 17) - } - #[doc = "Bit 18 - Set this bit to reset uart tx fifo"] - #[inline(always)] - #[must_use] - pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W { - TXFIFO_RST_W::new(self, 18) - } - #[doc = "Bit 19 - Set this bit to inverse uart rxd level"] - #[inline(always)] - #[must_use] - pub fn uart_rxd_inv(&mut self) -> UART_RXD_INV_W { - UART_RXD_INV_W::new(self, 19) - } - #[doc = "Bit 20 - Set this bit to inverse uart cts level"] - #[inline(always)] - #[must_use] - pub fn uart_cts_inv(&mut self) -> UART_CTS_INV_W { - UART_CTS_INV_W::new(self, 20) - } - #[doc = "Bit 21 - Set this bit to inverse uart dsr level"] - #[inline(always)] - #[must_use] - pub fn uart_dsr_inv(&mut self) -> UART_DSR_INV_W { - UART_DSR_INV_W::new(self, 21) - } - #[doc = "Bit 22 - Set this bit to inverse uart txd level"] - #[inline(always)] - #[must_use] - pub fn uart_txd_inv(&mut self) -> UART_TXD_INV_W { - UART_TXD_INV_W::new(self, 22) - } - #[doc = "Bit 23 - Set this bit to inverse uart rts level"] - #[inline(always)] - #[must_use] - pub fn uart_rts_inv(&mut self) -> UART_RTS_INV_W { - UART_RTS_INV_W::new(self, 23) - } - #[doc = "Bit 24 - Set this bit to inverse uart dtr level"] - #[inline(always)] - #[must_use] - pub fn uart_dtr_inv(&mut self) -> UART_DTR_INV_W { - UART_DTR_INV_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART CONFIG0(UART0 and UART1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CONF0_SPEC; -impl crate::RegisterSpec for UART_CONF0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_conf0::R`](R) reader structure"] -impl crate::Readable for UART_CONF0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_conf0::W`](W) writer structure"] -impl crate::Writable for UART_CONF0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CONF0 to value 0"] -impl crate::Resettable for UART_CONF0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_conf1.rs b/esp8266/src/uart0/uart_conf1.rs deleted file mode 100644 index d5a20399b0..0000000000 --- a/esp8266/src/uart0/uart_conf1.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `UART_CONF1` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CONF1` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_thrhd` reader - The config bits for rx fifo full threshold,0-127"] -pub type RXFIFO_FULL_THRHD_R = crate::FieldReader; -#[doc = "Field `rxfifo_full_thrhd` writer - The config bits for rx fifo full threshold,0-127"] -pub type RXFIFO_FULL_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `txfifo_empty_thrhd` reader - The config bits for tx fifo empty threshold,0-127"] -pub type TXFIFO_EMPTY_THRHD_R = crate::FieldReader; -#[doc = "Field `txfifo_empty_thrhd` writer - The config bits for tx fifo empty threshold,0-127"] -pub type TXFIFO_EMPTY_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_flow_thrhd` reader - The config bits for rx flow control threshold,0-127"] -pub type RX_FLOW_THRHD_R = crate::FieldReader; -#[doc = "Field `rx_flow_thrhd` writer - The config bits for rx flow control threshold,0-127"] -pub type RX_FLOW_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_flow_en` reader - Set this bit to enable rx hardware flow control"] -pub type RX_FLOW_EN_R = crate::BitReader; -#[doc = "Field `rx_flow_en` writer - Set this bit to enable rx hardware flow control"] -pub type RX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rx_tout_thrhd` reader - Config bits for rx time-out threshold,uint: byte,0-127"] -pub type RX_TOUT_THRHD_R = crate::FieldReader; -#[doc = "Field `rx_tout_thrhd` writer - Config bits for rx time-out threshold,uint: byte,0-127"] -pub type RX_TOUT_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_tout_en` reader - Set this bit to enable rx time-out function"] -pub type RX_TOUT_EN_R = crate::BitReader; -#[doc = "Field `rx_tout_en` writer - Set this bit to enable rx time-out function"] -pub type RX_TOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:6 - The config bits for rx fifo full threshold,0-127"] - #[inline(always)] - pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R { - RXFIFO_FULL_THRHD_R::new((self.bits & 0x7f) as u8) - } - #[doc = "Bits 8:14 - The config bits for tx fifo empty threshold,0-127"] - #[inline(always)] - pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R { - TXFIFO_EMPTY_THRHD_R::new(((self.bits >> 8) & 0x7f) as u8) - } - #[doc = "Bits 16:22 - The config bits for rx flow control threshold,0-127"] - #[inline(always)] - pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R { - RX_FLOW_THRHD_R::new(((self.bits >> 16) & 0x7f) as u8) - } - #[doc = "Bit 23 - Set this bit to enable rx hardware flow control"] - #[inline(always)] - pub fn rx_flow_en(&self) -> RX_FLOW_EN_R { - RX_FLOW_EN_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:30 - Config bits for rx time-out threshold,uint: byte,0-127"] - #[inline(always)] - pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R { - RX_TOUT_THRHD_R::new(((self.bits >> 24) & 0x7f) as u8) - } - #[doc = "Bit 31 - Set this bit to enable rx time-out function"] - #[inline(always)] - pub fn rx_tout_en(&self) -> RX_TOUT_EN_R { - RX_TOUT_EN_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CONF1") - .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit())) - .field( - "rx_tout_thrhd", - &format_args!("{}", self.rx_tout_thrhd().bits()), - ) - .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit())) - .field( - "rx_flow_thrhd", - &format_args!("{}", self.rx_flow_thrhd().bits()), - ) - .field( - "txfifo_empty_thrhd", - &format_args!("{}", self.txfifo_empty_thrhd().bits()), - ) - .field( - "rxfifo_full_thrhd", - &format_args!("{}", self.rxfifo_full_thrhd().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:6 - The config bits for rx fifo full threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W { - RXFIFO_FULL_THRHD_W::new(self, 0) - } - #[doc = "Bits 8:14 - The config bits for tx fifo empty threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W { - TXFIFO_EMPTY_THRHD_W::new(self, 8) - } - #[doc = "Bits 16:22 - The config bits for rx flow control threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W { - RX_FLOW_THRHD_W::new(self, 16) - } - #[doc = "Bit 23 - Set this bit to enable rx hardware flow control"] - #[inline(always)] - #[must_use] - pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W { - RX_FLOW_EN_W::new(self, 23) - } - #[doc = "Bits 24:30 - Config bits for rx time-out threshold,uint: byte,0-127"] - #[inline(always)] - #[must_use] - pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W { - RX_TOUT_THRHD_W::new(self, 24) - } - #[doc = "Bit 31 - Set this bit to enable rx time-out function"] - #[inline(always)] - #[must_use] - pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W { - RX_TOUT_EN_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Set this bit to enable rx time-out function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CONF1_SPEC; -impl crate::RegisterSpec for UART_CONF1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_conf1::R`](R) reader structure"] -impl crate::Readable for UART_CONF1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_conf1::W`](W) writer structure"] -impl crate::Writable for UART_CONF1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CONF1 to value 0"] -impl crate::Resettable for UART_CONF1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_date.rs b/esp8266/src/uart0/uart_date.rs deleted file mode 100644 index a6b4b89588..0000000000 --- a/esp8266/src/uart0/uart_date.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `UART_DATE` reader"] -pub type R = crate::R; -#[doc = "Register `UART_DATE` writer"] -pub type W = crate::W; -#[doc = "Field `uart_date` reader - UART HW INFO"] -pub type UART_DATE_R = crate::FieldReader; -#[doc = "Field `uart_date` writer - UART HW INFO"] -pub type UART_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - UART HW INFO"] - #[inline(always)] - pub fn uart_date(&self) -> UART_DATE_R { - UART_DATE_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_DATE") - .field("uart_date", &format_args!("{}", self.uart_date().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - UART HW INFO"] - #[inline(always)] - #[must_use] - pub fn uart_date(&mut self) -> UART_DATE_W { - UART_DATE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART HW INFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_DATE_SPEC; -impl crate::RegisterSpec for UART_DATE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_date::R`](R) reader structure"] -impl crate::Readable for UART_DATE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_date::W`](W) writer structure"] -impl crate::Writable for UART_DATE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_DATE to value 0"] -impl crate::Resettable for UART_DATE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_fifo.rs b/esp8266/src/uart0/uart_fifo.rs deleted file mode 100644 index 73a2a1e6af..0000000000 --- a/esp8266/src/uart0/uart_fifo.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `UART_FIFO` reader"] -pub type R = crate::R; -#[doc = "Register `UART_FIFO` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_rd_byte` reader - R/W share the same address"] -pub type RXFIFO_RD_BYTE_R = crate::FieldReader; -#[doc = "Field `rxfifo_write_byte` reader - R/W share the same address"] -pub type RXFIFO_WRITE_BYTE_R = crate::FieldReader; -#[doc = "Field `rxfifo_write_byte` writer - R/W share the same address"] -pub type RXFIFO_WRITE_BYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - pub fn rxfifo_rd_byte(&self) -> RXFIFO_RD_BYTE_R { - RXFIFO_RD_BYTE_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - pub fn rxfifo_write_byte(&self) -> RXFIFO_WRITE_BYTE_R { - RXFIFO_WRITE_BYTE_R::new((self.bits & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_FIFO") - .field( - "rxfifo_rd_byte", - &format_args!("{}", self.rxfifo_rd_byte().bits()), - ) - .field( - "rxfifo_write_byte", - &format_args!("{}", self.rxfifo_write_byte().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - #[must_use] - pub fn rxfifo_write_byte(&mut self) -> RXFIFO_WRITE_BYTE_W { - RXFIFO_WRITE_BYTE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART FIFO,length 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_FIFO_SPEC; -impl crate::RegisterSpec for UART_FIFO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_fifo::R`](R) reader structure"] -impl crate::Readable for UART_FIFO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_fifo::W`](W) writer structure"] -impl crate::Writable for UART_FIFO_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_FIFO to value 0"] -impl crate::Resettable for UART_FIFO_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_highpulse.rs b/esp8266/src/uart0/uart_highpulse.rs deleted file mode 100644 index 92d559c993..0000000000 --- a/esp8266/src/uart0/uart_highpulse.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_HIGHPULSE` reader"] -pub type R = crate::R; -#[doc = "Field `highpulse_min_cnt` reader - used in baudrate detect"] -pub type HIGHPULSE_MIN_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:19 - used in baudrate detect"] - #[inline(always)] - pub fn highpulse_min_cnt(&self) -> HIGHPULSE_MIN_CNT_R { - HIGHPULSE_MIN_CNT_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_HIGHPULSE") - .field( - "highpulse_min_cnt", - &format_args!("{}", self.highpulse_min_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_HIGHPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_highpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_HIGHPULSE_SPEC; -impl crate::RegisterSpec for UART_HIGHPULSE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_highpulse::R`](R) reader structure"] -impl crate::Readable for UART_HIGHPULSE_SPEC {} -#[doc = "`reset()` method sets UART_HIGHPULSE to value 0"] -impl crate::Resettable for UART_HIGHPULSE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_id.rs b/esp8266/src/uart0/uart_id.rs deleted file mode 100644 index be80237ad9..0000000000 --- a/esp8266/src/uart0/uart_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `UART_ID` reader"] -pub type R = crate::R; -#[doc = "Register `UART_ID` writer"] -pub type W = crate::W; -#[doc = "Field `uart_id` reader - "] -pub type UART_ID_R = crate::FieldReader; -#[doc = "Field `uart_id` writer - "] -pub type UART_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn uart_id(&self) -> UART_ID_R { - UART_ID_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_ID") - .field("uart_id", &format_args!("{}", self.uart_id().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn uart_id(&mut self) -> UART_ID_W { - UART_ID_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_ID_SPEC; -impl crate::RegisterSpec for UART_ID_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_id::R`](R) reader structure"] -impl crate::Readable for UART_ID_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_id::W`](W) writer structure"] -impl crate::Writable for UART_ID_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_ID to value 0"] -impl crate::Resettable for UART_ID_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_int_clr.rs b/esp8266/src/uart0/uart_int_clr.rs deleted file mode 100644 index 9c4b71a2d0..0000000000 --- a/esp8266/src/uart0/uart_int_clr.rs +++ /dev/null @@ -1,106 +0,0 @@ -#[doc = "Register `UART_INT_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_int_clr` writer - Set this bit to clear the rx fifo full interrupt"] -pub type RXFIFO_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_empty_int_clr` writer - Set this bit to clear the tx fifo empty interrupt"] -pub type TXFIFO_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_err_int_clr` writer - Set this bit to clear the parity error interrupt"] -pub type PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frm_err_int_clr` writer - Set this bit to clear other rx error interrupt"] -pub type FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_ovf_int_clr` writer - Set this bit to clear the rx fifo over-flow interrupt"] -pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dsr_chg_int_clr` writer - Set this bit to clear the DSR changing interrupt"] -pub type DSR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cts_chg_int_clr` writer - Set this bit to clear the CTS changing interrupt"] -pub type CTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `brk_det_int_clr` writer - Set this bit to clear the rx byte start interrupt"] -pub type BRK_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_tout_int_clr` writer - Set this bit to clear the rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bit 0 - Set this bit to clear the rx fifo full interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W { - RXFIFO_FULL_INT_CLR_W::new(self, 0) - } - #[doc = "Bit 1 - Set this bit to clear the tx fifo empty interrupt"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W { - TXFIFO_EMPTY_INT_CLR_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to clear the parity error interrupt"] - #[inline(always)] - #[must_use] - pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W { - PARITY_ERR_INT_CLR_W::new(self, 2) - } - #[doc = "Bit 3 - Set this bit to clear other rx error interrupt"] - #[inline(always)] - #[must_use] - pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W { - FRM_ERR_INT_CLR_W::new(self, 3) - } - #[doc = "Bit 4 - Set this bit to clear the rx fifo over-flow interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { - RXFIFO_OVF_INT_CLR_W::new(self, 4) - } - #[doc = "Bit 5 - Set this bit to clear the DSR changing interrupt"] - #[inline(always)] - #[must_use] - pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W { - DSR_CHG_INT_CLR_W::new(self, 5) - } - #[doc = "Bit 6 - Set this bit to clear the CTS changing interrupt"] - #[inline(always)] - #[must_use] - pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W { - CTS_CHG_INT_CLR_W::new(self, 6) - } - #[doc = "Bit 7 - Set this bit to clear the rx byte start interrupt"] - #[inline(always)] - #[must_use] - pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W { - BRK_DET_INT_CLR_W::new(self, 7) - } - #[doc = "Bit 8 - Set this bit to clear the rx time-out interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W { - RXFIFO_TOUT_INT_CLR_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART INTERRUPT CLEAR REGISTER\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_CLR_SPEC; -impl crate::RegisterSpec for UART_INT_CLR_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`uart_int_clr::W`](W) writer structure"] -impl crate::Writable for UART_INT_CLR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_INT_CLR to value 0"] -impl crate::Resettable for UART_INT_CLR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_int_ena.rs b/esp8266/src/uart0/uart_int_ena.rs deleted file mode 100644 index e5e2db0d9c..0000000000 --- a/esp8266/src/uart0/uart_int_ena.rs +++ /dev/null @@ -1,218 +0,0 @@ -#[doc = "Register `UART_INT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `UART_INT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_int_ena` reader - The interrupt enable bit for rx fifo full event"] -pub type RXFIFO_FULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_full_int_ena` writer - The interrupt enable bit for rx fifo full event"] -pub type RXFIFO_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_empty_int_ena` reader - The interrupt enable bit for tx fifo empty event"] -pub type TXFIFO_EMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_ena` writer - The interrupt enable bit for tx fifo empty event"] -pub type TXFIFO_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_err_int_ena` reader - The interrupt enable bit for parity error"] -pub type PARITY_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `parity_err_int_ena` writer - The interrupt enable bit for parity error"] -pub type PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frm_err_int_ena` reader - The interrupt enable bit for other rx error"] -pub type FRM_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `frm_err_int_ena` writer - The interrupt enable bit for other rx error"] -pub type FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_ovf_int_ena` reader - The interrupt enable bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_ena` writer - The interrupt enable bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dsr_chg_int_ena` reader - The interrupt enable bit for DSR changing level"] -pub type DSR_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_ena` writer - The interrupt enable bit for DSR changing level"] -pub type DSR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cts_chg_int_ena` reader - The interrupt enable bit for CTS changing level"] -pub type CTS_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `cts_chg_int_ena` writer - The interrupt enable bit for CTS changing level"] -pub type CTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `brk_det_int_ena` reader - The interrupt enable bit for rx byte start error"] -pub type BRK_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `brk_det_int_ena` writer - The interrupt enable bit for rx byte start error"] -pub type BRK_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_tout_int_ena` reader - The interrupt enable bit for rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_ena` writer - The interrupt enable bit for rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - The interrupt enable bit for rx fifo full event"] - #[inline(always)] - pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R { - RXFIFO_FULL_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt enable bit for tx fifo empty event"] - #[inline(always)] - pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R { - TXFIFO_EMPTY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt enable bit for parity error"] - #[inline(always)] - pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R { - PARITY_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt enable bit for other rx error"] - #[inline(always)] - pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R { - FRM_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt enable bit for rx fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { - RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt enable bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R { - DSR_CHG_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt enable bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R { - CTS_CHG_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt enable bit for rx byte start error"] - #[inline(always)] - pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R { - BRK_DET_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt enable bit for rx time-out interrupt"] - #[inline(always)] - pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R { - RXFIFO_TOUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_ENA") - .field( - "rxfifo_tout_int_ena", - &format_args!("{}", self.rxfifo_tout_int_ena().bit()), - ) - .field( - "brk_det_int_ena", - &format_args!("{}", self.brk_det_int_ena().bit()), - ) - .field( - "cts_chg_int_ena", - &format_args!("{}", self.cts_chg_int_ena().bit()), - ) - .field( - "dsr_chg_int_ena", - &format_args!("{}", self.dsr_chg_int_ena().bit()), - ) - .field( - "rxfifo_ovf_int_ena", - &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), - ) - .field( - "frm_err_int_ena", - &format_args!("{}", self.frm_err_int_ena().bit()), - ) - .field( - "parity_err_int_ena", - &format_args!("{}", self.parity_err_int_ena().bit()), - ) - .field( - "txfifo_empty_int_ena", - &format_args!("{}", self.txfifo_empty_int_ena().bit()), - ) - .field( - "rxfifo_full_int_ena", - &format_args!("{}", self.rxfifo_full_int_ena().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - The interrupt enable bit for rx fifo full event"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W { - RXFIFO_FULL_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1 - The interrupt enable bit for tx fifo empty event"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W { - TXFIFO_EMPTY_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2 - The interrupt enable bit for parity error"] - #[inline(always)] - #[must_use] - pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W { - PARITY_ERR_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3 - The interrupt enable bit for other rx error"] - #[inline(always)] - #[must_use] - pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W { - FRM_ERR_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4 - The interrupt enable bit for rx fifo overflow"] - #[inline(always)] - #[must_use] - pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { - RXFIFO_OVF_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5 - The interrupt enable bit for DSR changing level"] - #[inline(always)] - #[must_use] - pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W { - DSR_CHG_INT_ENA_W::new(self, 5) - } - #[doc = "Bit 6 - The interrupt enable bit for CTS changing level"] - #[inline(always)] - #[must_use] - pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W { - CTS_CHG_INT_ENA_W::new(self, 6) - } - #[doc = "Bit 7 - The interrupt enable bit for rx byte start error"] - #[inline(always)] - #[must_use] - pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W { - BRK_DET_INT_ENA_W::new(self, 7) - } - #[doc = "Bit 8 - The interrupt enable bit for rx time-out interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W { - RXFIFO_TOUT_INT_ENA_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART INTERRUPT ENABLE REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_ENA_SPEC; -impl crate::RegisterSpec for UART_INT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_ena::R`](R) reader structure"] -impl crate::Readable for UART_INT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_int_ena::W`](W) writer structure"] -impl crate::Writable for UART_INT_ENA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_INT_ENA to value 0"] -impl crate::Resettable for UART_INT_ENA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_int_raw.rs b/esp8266/src/uart0/uart_int_raw.rs deleted file mode 100644 index 27768369ae..0000000000 --- a/esp8266/src/uart0/uart_int_raw.rs +++ /dev/null @@ -1,127 +0,0 @@ -#[doc = "Register `UART_INT_RAW` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_full_int_raw` reader - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)"] -pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_raw` reader - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)"] -pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `parity_err_int_raw` reader - The interrupt raw bit for parity check error"] -pub type PARITY_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `frm_err_int_raw` reader - The interrupt raw bit for other rx error"] -pub type FRM_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_raw` reader - The interrupt raw bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_raw` reader - The interrupt raw bit for DSR changing level"] -pub type DSR_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `cts_chg_int_raw` reader - The interrupt raw bit for CTS changing level"] -pub type CTS_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `brk_det_int_raw` reader - The interrupt raw bit for Rx byte start error"] -pub type BRK_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_raw` reader - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)"] -pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)"] - #[inline(always)] - pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R { - RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)"] - #[inline(always)] - pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R { - TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt raw bit for parity check error"] - #[inline(always)] - pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R { - PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt raw bit for other rx error"] - #[inline(always)] - pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R { - FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt raw bit for rx fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { - RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt raw bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R { - DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt raw bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R { - CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt raw bit for Rx byte start error"] - #[inline(always)] - pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R { - BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)"] - #[inline(always)] - pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R { - RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_RAW") - .field( - "rxfifo_tout_int_raw", - &format_args!("{}", self.rxfifo_tout_int_raw().bit()), - ) - .field( - "brk_det_int_raw", - &format_args!("{}", self.brk_det_int_raw().bit()), - ) - .field( - "cts_chg_int_raw", - &format_args!("{}", self.cts_chg_int_raw().bit()), - ) - .field( - "dsr_chg_int_raw", - &format_args!("{}", self.dsr_chg_int_raw().bit()), - ) - .field( - "rxfifo_ovf_int_raw", - &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), - ) - .field( - "frm_err_int_raw", - &format_args!("{}", self.frm_err_int_raw().bit()), - ) - .field( - "parity_err_int_raw", - &format_args!("{}", self.parity_err_int_raw().bit()), - ) - .field( - "txfifo_empty_int_raw", - &format_args!("{}", self.txfifo_empty_int_raw().bit()), - ) - .field( - "rxfifo_full_int_raw", - &format_args!("{}", self.rxfifo_full_int_raw().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART INTERRUPT RAW STATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_RAW_SPEC; -impl crate::RegisterSpec for UART_INT_RAW_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_raw::R`](R) reader structure"] -impl crate::Readable for UART_INT_RAW_SPEC {} -#[doc = "`reset()` method sets UART_INT_RAW to value 0"] -impl crate::Resettable for UART_INT_RAW_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_int_st.rs b/esp8266/src/uart0/uart_int_st.rs deleted file mode 100644 index 7fd6d56576..0000000000 --- a/esp8266/src/uart0/uart_int_st.rs +++ /dev/null @@ -1,127 +0,0 @@ -#[doc = "Register `UART_INT_ST` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_full_int_st` reader - The interrupt state bit for RX fifo full event"] -pub type RXFIFO_FULL_INT_ST_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_st` reader - The interrupt state bit for TX fifo empty"] -pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `parity_err_int_st` reader - The interrupt state bit for rx parity error"] -pub type PARITY_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `frm_err_int_st` reader - The interrupt state for other rx error"] -pub type FRM_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_st` reader - The interrupt state bit for RX fifo overflow"] -pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_st` reader - The interrupt state bit for DSR changing level"] -pub type DSR_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `cts_chg_int_st` reader - The interrupt state bit for CTS changing level"] -pub type CTS_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `brk_det_int_st` reader - The interrupt state bit for rx byte start error"] -pub type BRK_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_st` reader - The interrupt state bit for Rx time-out event"] -pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The interrupt state bit for RX fifo full event"] - #[inline(always)] - pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R { - RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt state bit for TX fifo empty"] - #[inline(always)] - pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R { - TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt state bit for rx parity error"] - #[inline(always)] - pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R { - PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt state for other rx error"] - #[inline(always)] - pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R { - FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt state bit for RX fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { - RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt state bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R { - DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt state bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R { - CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt state bit for rx byte start error"] - #[inline(always)] - pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R { - BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt state bit for Rx time-out event"] - #[inline(always)] - pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R { - RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_ST") - .field( - "rxfifo_tout_int_st", - &format_args!("{}", self.rxfifo_tout_int_st().bit()), - ) - .field( - "brk_det_int_st", - &format_args!("{}", self.brk_det_int_st().bit()), - ) - .field( - "cts_chg_int_st", - &format_args!("{}", self.cts_chg_int_st().bit()), - ) - .field( - "dsr_chg_int_st", - &format_args!("{}", self.dsr_chg_int_st().bit()), - ) - .field( - "rxfifo_ovf_int_st", - &format_args!("{}", self.rxfifo_ovf_int_st().bit()), - ) - .field( - "frm_err_int_st", - &format_args!("{}", self.frm_err_int_st().bit()), - ) - .field( - "parity_err_int_st", - &format_args!("{}", self.parity_err_int_st().bit()), - ) - .field( - "txfifo_empty_int_st", - &format_args!("{}", self.txfifo_empty_int_st().bit()), - ) - .field( - "rxfifo_full_int_st", - &format_args!("{}", self.rxfifo_full_int_st().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_ST_SPEC; -impl crate::RegisterSpec for UART_INT_ST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_st::R`](R) reader structure"] -impl crate::Readable for UART_INT_ST_SPEC {} -#[doc = "`reset()` method sets UART_INT_ST to value 0"] -impl crate::Resettable for UART_INT_ST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_lowpulse.rs b/esp8266/src/uart0/uart_lowpulse.rs deleted file mode 100644 index 15d8cf5750..0000000000 --- a/esp8266/src/uart0/uart_lowpulse.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_LOWPULSE` reader"] -pub type R = crate::R; -#[doc = "Field `lowpulse_min_cnt` reader - used in baudrate detect"] -pub type LOWPULSE_MIN_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:19 - used in baudrate detect"] - #[inline(always)] - pub fn lowpulse_min_cnt(&self) -> LOWPULSE_MIN_CNT_R { - LOWPULSE_MIN_CNT_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_LOWPULSE") - .field( - "lowpulse_min_cnt", - &format_args!("{}", self.lowpulse_min_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_LOWPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_lowpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_LOWPULSE_SPEC; -impl crate::RegisterSpec for UART_LOWPULSE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_lowpulse::R`](R) reader structure"] -impl crate::Readable for UART_LOWPULSE_SPEC {} -#[doc = "`reset()` method sets UART_LOWPULSE to value 0"] -impl crate::Resettable for UART_LOWPULSE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_rxd_cnt.rs b/esp8266/src/uart0/uart_rxd_cnt.rs deleted file mode 100644 index 8e0293ab2e..0000000000 --- a/esp8266/src/uart0/uart_rxd_cnt.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_RXD_CNT` reader"] -pub type R = crate::R; -#[doc = "Field `rxd_edge_cnt` reader - used in baudrate detect"] -pub type RXD_EDGE_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - used in baudrate detect"] - #[inline(always)] - pub fn rxd_edge_cnt(&self) -> RXD_EDGE_CNT_R { - RXD_EDGE_CNT_R::new((self.bits & 0x03ff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_RXD_CNT") - .field( - "rxd_edge_cnt", - &format_args!("{}", self.rxd_edge_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_RXD_CNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_rxd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_RXD_CNT_SPEC; -impl crate::RegisterSpec for UART_RXD_CNT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_rxd_cnt::R`](R) reader structure"] -impl crate::Readable for UART_RXD_CNT_SPEC {} -#[doc = "`reset()` method sets UART_RXD_CNT to value 0"] -impl crate::Resettable for UART_RXD_CNT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart0/uart_status.rs b/esp8266/src/uart0/uart_status.rs deleted file mode 100644 index 5cd1b4cff0..0000000000 --- a/esp8266/src/uart0/uart_status.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `UART_STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_cnt` reader - Number of data in uart rx fifo"] -pub type RXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `dsrn` reader - The level of uart dsr pin"] -pub type DSRN_R = crate::BitReader; -#[doc = "Field `ctsn` reader - The level of uart cts pin"] -pub type CTSN_R = crate::BitReader; -#[doc = "Field `rxd` reader - The level of uart rxd pin"] -pub type RXD_R = crate::BitReader; -#[doc = "Field `txfifo_cnt` reader - Number of data in UART TX fifo"] -pub type TXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `dtrn` reader - The level of uart dtr pin"] -pub type DTRN_R = crate::BitReader; -#[doc = "Field `rtsn` reader - The level of uart rts pin"] -pub type RTSN_R = crate::BitReader; -#[doc = "Field `txd` reader - The level of the uart txd pin"] -pub type TXD_R = crate::BitReader; -impl R { - #[doc = "Bits 0:7 - Number of data in uart rx fifo"] - #[inline(always)] - pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { - RXFIFO_CNT_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 13 - The level of uart dsr pin"] - #[inline(always)] - pub fn dsrn(&self) -> DSRN_R { - DSRN_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - The level of uart cts pin"] - #[inline(always)] - pub fn ctsn(&self) -> CTSN_R { - CTSN_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - The level of uart rxd pin"] - #[inline(always)] - pub fn rxd(&self) -> RXD_R { - RXD_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:23 - Number of data in UART TX fifo"] - #[inline(always)] - pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { - TXFIFO_CNT_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bit 29 - The level of uart dtr pin"] - #[inline(always)] - pub fn dtrn(&self) -> DTRN_R { - DTRN_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - The level of uart rts pin"] - #[inline(always)] - pub fn rtsn(&self) -> RTSN_R { - RTSN_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - The level of the uart txd pin"] - #[inline(always)] - pub fn txd(&self) -> TXD_R { - TXD_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_STATUS") - .field("txd", &format_args!("{}", self.txd().bit())) - .field("rtsn", &format_args!("{}", self.rtsn().bit())) - .field("dtrn", &format_args!("{}", self.dtrn().bit())) - .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) - .field("rxd", &format_args!("{}", self.rxd().bit())) - .field("ctsn", &format_args!("{}", self.ctsn().bit())) - .field("dsrn", &format_args!("{}", self.dsrn().bit())) - .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART STATUS REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_STATUS_SPEC; -impl crate::RegisterSpec for UART_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_status::R`](R) reader structure"] -impl crate::Readable for UART_STATUS_SPEC {} -#[doc = "`reset()` method sets UART_STATUS to value 0"] -impl crate::Resettable for UART_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1.rs b/esp8266/src/uart1.rs deleted file mode 100644 index bf0effa538..0000000000 --- a/esp8266/src/uart1.rs +++ /dev/null @@ -1,158 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - uart_fifo: UART_FIFO, - uart_int_raw: UART_INT_RAW, - uart_int_st: UART_INT_ST, - uart_int_ena: UART_INT_ENA, - uart_int_clr: UART_INT_CLR, - uart_clkdiv: UART_CLKDIV, - uart_autobaud: UART_AUTOBAUD, - uart_status: UART_STATUS, - uart_conf0: UART_CONF0, - uart_conf1: UART_CONF1, - uart_lowpulse: UART_LOWPULSE, - uart_highpulse: UART_HIGHPULSE, - uart_rxd_cnt: UART_RXD_CNT, - _reserved13: [u8; 0x44], - uart_date: UART_DATE, - uart_id: UART_ID, -} -impl RegisterBlock { - #[doc = "0x00 - UART FIFO,length 128"] - #[inline(always)] - pub const fn uart_fifo(&self) -> &UART_FIFO { - &self.uart_fifo - } - #[doc = "0x04 - UART INTERRUPT RAW STATE"] - #[inline(always)] - pub const fn uart_int_raw(&self) -> &UART_INT_RAW { - &self.uart_int_raw - } - #[doc = "0x08 - UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] - #[inline(always)] - pub const fn uart_int_st(&self) -> &UART_INT_ST { - &self.uart_int_st - } - #[doc = "0x0c - UART INTERRUPT ENABLE REGISTER"] - #[inline(always)] - pub const fn uart_int_ena(&self) -> &UART_INT_ENA { - &self.uart_int_ena - } - #[doc = "0x10 - UART INTERRUPT CLEAR REGISTER"] - #[inline(always)] - pub const fn uart_int_clr(&self) -> &UART_INT_CLR { - &self.uart_int_clr - } - #[doc = "0x14 - UART CLK DIV REGISTER"] - #[inline(always)] - pub const fn uart_clkdiv(&self) -> &UART_CLKDIV { - &self.uart_clkdiv - } - #[doc = "0x18 - UART BAUDRATE DETECT REGISTER"] - #[inline(always)] - pub const fn uart_autobaud(&self) -> &UART_AUTOBAUD { - &self.uart_autobaud - } - #[doc = "0x1c - UART STATUS REGISTER"] - #[inline(always)] - pub const fn uart_status(&self) -> &UART_STATUS { - &self.uart_status - } - #[doc = "0x20 - UART CONFIG0(UART0 and UART1)"] - #[inline(always)] - pub const fn uart_conf0(&self) -> &UART_CONF0 { - &self.uart_conf0 - } - #[doc = "0x24 - Set this bit to enable rx time-out function"] - #[inline(always)] - pub const fn uart_conf1(&self) -> &UART_CONF1 { - &self.uart_conf1 - } - #[doc = "0x28 - UART_LOWPULSE"] - #[inline(always)] - pub const fn uart_lowpulse(&self) -> &UART_LOWPULSE { - &self.uart_lowpulse - } - #[doc = "0x2c - UART_HIGHPULSE"] - #[inline(always)] - pub const fn uart_highpulse(&self) -> &UART_HIGHPULSE { - &self.uart_highpulse - } - #[doc = "0x30 - UART_RXD_CNT"] - #[inline(always)] - pub const fn uart_rxd_cnt(&self) -> &UART_RXD_CNT { - &self.uart_rxd_cnt - } - #[doc = "0x78 - UART HW INFO"] - #[inline(always)] - pub const fn uart_date(&self) -> &UART_DATE { - &self.uart_date - } - #[doc = "0x7c - UART_ID"] - #[inline(always)] - pub const fn uart_id(&self) -> &UART_ID { - &self.uart_id - } -} -#[doc = "UART_FIFO (rw) register accessor: UART FIFO,length 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_fifo`] module"] -pub type UART_FIFO = crate::Reg; -#[doc = "UART FIFO,length 128"] -pub mod uart_fifo; -#[doc = "UART_INT_RAW (r) register accessor: UART INTERRUPT RAW STATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_raw`] module"] -pub type UART_INT_RAW = crate::Reg; -#[doc = "UART INTERRUPT RAW STATE"] -pub mod uart_int_raw; -#[doc = "UART_INT_ST (r) register accessor: UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_st`] module"] -pub type UART_INT_ST = crate::Reg; -#[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] -pub mod uart_int_st; -#[doc = "UART_INT_ENA (rw) register accessor: UART INTERRUPT ENABLE REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_ena`] module"] -pub type UART_INT_ENA = crate::Reg; -#[doc = "UART INTERRUPT ENABLE REGISTER"] -pub mod uart_int_ena; -#[doc = "UART_INT_CLR (w) register accessor: UART INTERRUPT CLEAR REGISTER\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_int_clr`] module"] -pub type UART_INT_CLR = crate::Reg; -#[doc = "UART INTERRUPT CLEAR REGISTER"] -pub mod uart_int_clr; -#[doc = "UART_CLKDIV (rw) register accessor: UART CLK DIV REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_clkdiv`] module"] -pub type UART_CLKDIV = crate::Reg; -#[doc = "UART CLK DIV REGISTER"] -pub mod uart_clkdiv; -#[doc = "UART_AUTOBAUD (rw) register accessor: UART BAUDRATE DETECT REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_autobaud::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_autobaud::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_autobaud`] module"] -pub type UART_AUTOBAUD = crate::Reg; -#[doc = "UART BAUDRATE DETECT REGISTER"] -pub mod uart_autobaud; -#[doc = "UART_STATUS (r) register accessor: UART STATUS REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_status`] module"] -pub type UART_STATUS = crate::Reg; -#[doc = "UART STATUS REGISTER"] -pub mod uart_status; -#[doc = "UART_CONF0 (rw) register accessor: UART CONFIG0(UART0 and UART1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_conf0`] module"] -pub type UART_CONF0 = crate::Reg; -#[doc = "UART CONFIG0(UART0 and UART1)"] -pub mod uart_conf0; -#[doc = "UART_CONF1 (rw) register accessor: Set this bit to enable rx time-out function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_conf1`] module"] -pub type UART_CONF1 = crate::Reg; -#[doc = "Set this bit to enable rx time-out function"] -pub mod uart_conf1; -#[doc = "UART_LOWPULSE (r) register accessor: UART_LOWPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_lowpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_lowpulse`] module"] -pub type UART_LOWPULSE = crate::Reg; -#[doc = "UART_LOWPULSE"] -pub mod uart_lowpulse; -#[doc = "UART_HIGHPULSE (r) register accessor: UART_HIGHPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_highpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_highpulse`] module"] -pub type UART_HIGHPULSE = crate::Reg; -#[doc = "UART_HIGHPULSE"] -pub mod uart_highpulse; -#[doc = "UART_RXD_CNT (r) register accessor: UART_RXD_CNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_rxd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_rxd_cnt`] module"] -pub type UART_RXD_CNT = crate::Reg; -#[doc = "UART_RXD_CNT"] -pub mod uart_rxd_cnt; -#[doc = "UART_DATE (rw) register accessor: UART HW INFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_date`] module"] -pub type UART_DATE = crate::Reg; -#[doc = "UART HW INFO"] -pub mod uart_date; -#[doc = "UART_ID (rw) register accessor: UART_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_id`] module"] -pub type UART_ID = crate::Reg; -#[doc = "UART_ID"] -pub mod uart_id; diff --git a/esp8266/src/uart1/uart_autobaud.rs b/esp8266/src/uart1/uart_autobaud.rs deleted file mode 100644 index 8509d7b088..0000000000 --- a/esp8266/src/uart1/uart_autobaud.rs +++ /dev/null @@ -1,82 +0,0 @@ -#[doc = "Register `UART_AUTOBAUD` reader"] -pub type R = crate::R; -#[doc = "Register `UART_AUTOBAUD` writer"] -pub type W = crate::W; -#[doc = "Field `autobaud_en` reader - Set this bit to enable baudrate detect"] -pub type AUTOBAUD_EN_R = crate::BitReader; -#[doc = "Field `autobaud_en` writer - Set this bit to enable baudrate detect"] -pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `glitch_filt` reader - "] -pub type GLITCH_FILT_R = crate::FieldReader; -#[doc = "Field `glitch_filt` writer - "] -pub type GLITCH_FILT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bit 0 - Set this bit to enable baudrate detect"] - #[inline(always)] - pub fn autobaud_en(&self) -> AUTOBAUD_EN_R { - AUTOBAUD_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bits 8:15"] - #[inline(always)] - pub fn glitch_filt(&self) -> GLITCH_FILT_R { - GLITCH_FILT_R::new(((self.bits >> 8) & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_AUTOBAUD") - .field( - "glitch_filt", - &format_args!("{}", self.glitch_filt().bits()), - ) - .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Set this bit to enable baudrate detect"] - #[inline(always)] - #[must_use] - pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W { - AUTOBAUD_EN_W::new(self, 0) - } - #[doc = "Bits 8:15"] - #[inline(always)] - #[must_use] - pub fn glitch_filt(&mut self) -> GLITCH_FILT_W { - GLITCH_FILT_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART BAUDRATE DETECT REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_autobaud::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_autobaud::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_AUTOBAUD_SPEC; -impl crate::RegisterSpec for UART_AUTOBAUD_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_autobaud::R`](R) reader structure"] -impl crate::Readable for UART_AUTOBAUD_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_autobaud::W`](W) writer structure"] -impl crate::Writable for UART_AUTOBAUD_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_AUTOBAUD to value 0"] -impl crate::Resettable for UART_AUTOBAUD_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_clkdiv.rs b/esp8266/src/uart1/uart_clkdiv.rs deleted file mode 100644 index 71587c41d2..0000000000 --- a/esp8266/src/uart1/uart_clkdiv.rs +++ /dev/null @@ -1,66 +0,0 @@ -#[doc = "Register `UART_CLKDIV` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CLKDIV` writer"] -pub type W = crate::W; -#[doc = "Field `uart_clkdiv` reader - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] -pub type UART_CLKDIV_R = crate::FieldReader; -#[doc = "Field `uart_clkdiv` writer - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] -pub type UART_CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; -impl R { - #[doc = "Bits 0:19 - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] - #[inline(always)] - pub fn uart_clkdiv(&self) -> UART_CLKDIV_R { - UART_CLKDIV_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CLKDIV") - .field( - "uart_clkdiv", - &format_args!("{}", self.uart_clkdiv().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:19 - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV"] - #[inline(always)] - #[must_use] - pub fn uart_clkdiv(&mut self) -> UART_CLKDIV_W { - UART_CLKDIV_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART CLK DIV REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CLKDIV_SPEC; -impl crate::RegisterSpec for UART_CLKDIV_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_clkdiv::R`](R) reader structure"] -impl crate::Readable for UART_CLKDIV_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_clkdiv::W`](W) writer structure"] -impl crate::Writable for UART_CLKDIV_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CLKDIV to value 0"] -impl crate::Resettable for UART_CLKDIV_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_conf0.rs b/esp8266/src/uart1/uart_conf0.rs deleted file mode 100644 index 84406bbd28..0000000000 --- a/esp8266/src/uart1/uart_conf0.rs +++ /dev/null @@ -1,343 +0,0 @@ -#[doc = "Register `UART_CONF0` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CONF0` writer"] -pub type W = crate::W; -#[doc = "Field `parity` reader - Set parity check: 0:even 1:odd, UART CONFIG1"] -pub type PARITY_R = crate::BitReader; -#[doc = "Field `parity` writer - Set parity check: 0:even 1:odd, UART CONFIG1"] -pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_en` reader - Set this bit to enable uart parity check"] -pub type PARITY_EN_R = crate::BitReader; -#[doc = "Field `parity_en` writer - Set this bit to enable uart parity check"] -pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `bit_num` reader - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] -pub type BIT_NUM_R = crate::FieldReader; -#[doc = "Field `bit_num` writer - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] -pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `stop_bit_num` reader - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] -pub type STOP_BIT_NUM_R = crate::FieldReader; -#[doc = "Field `stop_bit_num` writer - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] -pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `sw_rts` reader - sw rts"] -pub type SW_RTS_R = crate::BitReader; -#[doc = "Field `sw_rts` writer - sw rts"] -pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sw_dtr` reader - sw dtr"] -pub type SW_DTR_R = crate::BitReader; -#[doc = "Field `sw_dtr` writer - sw dtr"] -pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txd_brk` reader - RESERVED, DO NOT CHANGE THIS BIT"] -pub type TXD_BRK_R = crate::BitReader; -#[doc = "Field `txd_brk` writer - RESERVED, DO NOT CHANGE THIS BIT"] -pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_loopback` reader - Set this bit to enable uart loopback test mode"] -pub type UART_LOOPBACK_R = crate::BitReader; -#[doc = "Field `uart_loopback` writer - Set this bit to enable uart loopback test mode"] -pub type UART_LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `tx_flow_en` reader - Set this bit to enable uart tx hardware flow control"] -pub type TX_FLOW_EN_R = crate::BitReader; -#[doc = "Field `tx_flow_en` writer - Set this bit to enable uart tx hardware flow control"] -pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_rst` reader - Set this bit to reset uart rx fifo"] -pub type RXFIFO_RST_R = crate::BitReader; -#[doc = "Field `rxfifo_rst` writer - Set this bit to reset uart rx fifo"] -pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_rst` reader - Set this bit to reset uart tx fifo"] -pub type TXFIFO_RST_R = crate::BitReader; -#[doc = "Field `txfifo_rst` writer - Set this bit to reset uart tx fifo"] -pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_rxd_inv` reader - Set this bit to inverse uart rxd level"] -pub type UART_RXD_INV_R = crate::BitReader; -#[doc = "Field `uart_rxd_inv` writer - Set this bit to inverse uart rxd level"] -pub type UART_RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_cts_inv` reader - Set this bit to inverse uart cts level"] -pub type UART_CTS_INV_R = crate::BitReader; -#[doc = "Field `uart_cts_inv` writer - Set this bit to inverse uart cts level"] -pub type UART_CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_dsr_inv` reader - Set this bit to inverse uart dsr level"] -pub type UART_DSR_INV_R = crate::BitReader; -#[doc = "Field `uart_dsr_inv` writer - Set this bit to inverse uart dsr level"] -pub type UART_DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_txd_inv` reader - Set this bit to inverse uart txd level"] -pub type UART_TXD_INV_R = crate::BitReader; -#[doc = "Field `uart_txd_inv` writer - Set this bit to inverse uart txd level"] -pub type UART_TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_rts_inv` reader - Set this bit to inverse uart rts level"] -pub type UART_RTS_INV_R = crate::BitReader; -#[doc = "Field `uart_rts_inv` writer - Set this bit to inverse uart rts level"] -pub type UART_RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart_dtr_inv` reader - Set this bit to inverse uart dtr level"] -pub type UART_DTR_INV_R = crate::BitReader; -#[doc = "Field `uart_dtr_inv` writer - Set this bit to inverse uart dtr level"] -pub type UART_DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set parity check: 0:even 1:odd, UART CONFIG1"] - #[inline(always)] - pub fn parity(&self) -> PARITY_R { - PARITY_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set this bit to enable uart parity check"] - #[inline(always)] - pub fn parity_en(&self) -> PARITY_EN_R { - PARITY_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bits 2:3 - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] - #[inline(always)] - pub fn bit_num(&self) -> BIT_NUM_R { - BIT_NUM_R::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:5 - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] - #[inline(always)] - pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R { - STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8) - } - #[doc = "Bit 6 - sw rts"] - #[inline(always)] - pub fn sw_rts(&self) -> SW_RTS_R { - SW_RTS_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - sw dtr"] - #[inline(always)] - pub fn sw_dtr(&self) -> SW_DTR_R { - SW_DTR_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - RESERVED, DO NOT CHANGE THIS BIT"] - #[inline(always)] - pub fn txd_brk(&self) -> TXD_BRK_R { - TXD_BRK_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 14 - Set this bit to enable uart loopback test mode"] - #[inline(always)] - pub fn uart_loopback(&self) -> UART_LOOPBACK_R { - UART_LOOPBACK_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - Set this bit to enable uart tx hardware flow control"] - #[inline(always)] - pub fn tx_flow_en(&self) -> TX_FLOW_EN_R { - TX_FLOW_EN_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bit 17 - Set this bit to reset uart rx fifo"] - #[inline(always)] - pub fn rxfifo_rst(&self) -> RXFIFO_RST_R { - RXFIFO_RST_R::new(((self.bits >> 17) & 1) != 0) - } - #[doc = "Bit 18 - Set this bit to reset uart tx fifo"] - #[inline(always)] - pub fn txfifo_rst(&self) -> TXFIFO_RST_R { - TXFIFO_RST_R::new(((self.bits >> 18) & 1) != 0) - } - #[doc = "Bit 19 - Set this bit to inverse uart rxd level"] - #[inline(always)] - pub fn uart_rxd_inv(&self) -> UART_RXD_INV_R { - UART_RXD_INV_R::new(((self.bits >> 19) & 1) != 0) - } - #[doc = "Bit 20 - Set this bit to inverse uart cts level"] - #[inline(always)] - pub fn uart_cts_inv(&self) -> UART_CTS_INV_R { - UART_CTS_INV_R::new(((self.bits >> 20) & 1) != 0) - } - #[doc = "Bit 21 - Set this bit to inverse uart dsr level"] - #[inline(always)] - pub fn uart_dsr_inv(&self) -> UART_DSR_INV_R { - UART_DSR_INV_R::new(((self.bits >> 21) & 1) != 0) - } - #[doc = "Bit 22 - Set this bit to inverse uart txd level"] - #[inline(always)] - pub fn uart_txd_inv(&self) -> UART_TXD_INV_R { - UART_TXD_INV_R::new(((self.bits >> 22) & 1) != 0) - } - #[doc = "Bit 23 - Set this bit to inverse uart rts level"] - #[inline(always)] - pub fn uart_rts_inv(&self) -> UART_RTS_INV_R { - UART_RTS_INV_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bit 24 - Set this bit to inverse uart dtr level"] - #[inline(always)] - pub fn uart_dtr_inv(&self) -> UART_DTR_INV_R { - UART_DTR_INV_R::new(((self.bits >> 24) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CONF0") - .field( - "uart_dtr_inv", - &format_args!("{}", self.uart_dtr_inv().bit()), - ) - .field( - "uart_rts_inv", - &format_args!("{}", self.uart_rts_inv().bit()), - ) - .field( - "uart_txd_inv", - &format_args!("{}", self.uart_txd_inv().bit()), - ) - .field( - "uart_dsr_inv", - &format_args!("{}", self.uart_dsr_inv().bit()), - ) - .field( - "uart_cts_inv", - &format_args!("{}", self.uart_cts_inv().bit()), - ) - .field( - "uart_rxd_inv", - &format_args!("{}", self.uart_rxd_inv().bit()), - ) - .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit())) - .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit())) - .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit())) - .field( - "uart_loopback", - &format_args!("{}", self.uart_loopback().bit()), - ) - .field("txd_brk", &format_args!("{}", self.txd_brk().bit())) - .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit())) - .field("sw_rts", &format_args!("{}", self.sw_rts().bit())) - .field( - "stop_bit_num", - &format_args!("{}", self.stop_bit_num().bits()), - ) - .field("bit_num", &format_args!("{}", self.bit_num().bits())) - .field("parity_en", &format_args!("{}", self.parity_en().bit())) - .field("parity", &format_args!("{}", self.parity().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - Set parity check: 0:even 1:odd, UART CONFIG1"] - #[inline(always)] - #[must_use] - pub fn parity(&mut self) -> PARITY_W { - PARITY_W::new(self, 0) - } - #[doc = "Bit 1 - Set this bit to enable uart parity check"] - #[inline(always)] - #[must_use] - pub fn parity_en(&mut self) -> PARITY_EN_W { - PARITY_EN_W::new(self, 1) - } - #[doc = "Bits 2:3 - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits"] - #[inline(always)] - #[must_use] - pub fn bit_num(&mut self) -> BIT_NUM_W { - BIT_NUM_W::new(self, 2) - } - #[doc = "Bits 4:5 - Set stop bit: 1:1bit 2:1.5bits 3:2bits"] - #[inline(always)] - #[must_use] - pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W { - STOP_BIT_NUM_W::new(self, 4) - } - #[doc = "Bit 6 - sw rts"] - #[inline(always)] - #[must_use] - pub fn sw_rts(&mut self) -> SW_RTS_W { - SW_RTS_W::new(self, 6) - } - #[doc = "Bit 7 - sw dtr"] - #[inline(always)] - #[must_use] - pub fn sw_dtr(&mut self) -> SW_DTR_W { - SW_DTR_W::new(self, 7) - } - #[doc = "Bit 8 - RESERVED, DO NOT CHANGE THIS BIT"] - #[inline(always)] - #[must_use] - pub fn txd_brk(&mut self) -> TXD_BRK_W { - TXD_BRK_W::new(self, 8) - } - #[doc = "Bit 14 - Set this bit to enable uart loopback test mode"] - #[inline(always)] - #[must_use] - pub fn uart_loopback(&mut self) -> UART_LOOPBACK_W { - UART_LOOPBACK_W::new(self, 14) - } - #[doc = "Bit 15 - Set this bit to enable uart tx hardware flow control"] - #[inline(always)] - #[must_use] - pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W { - TX_FLOW_EN_W::new(self, 15) - } - #[doc = "Bit 17 - Set this bit to reset uart rx fifo"] - #[inline(always)] - #[must_use] - pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W { - RXFIFO_RST_W::new(self, 17) - } - #[doc = "Bit 18 - Set this bit to reset uart tx fifo"] - #[inline(always)] - #[must_use] - pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W { - TXFIFO_RST_W::new(self, 18) - } - #[doc = "Bit 19 - Set this bit to inverse uart rxd level"] - #[inline(always)] - #[must_use] - pub fn uart_rxd_inv(&mut self) -> UART_RXD_INV_W { - UART_RXD_INV_W::new(self, 19) - } - #[doc = "Bit 20 - Set this bit to inverse uart cts level"] - #[inline(always)] - #[must_use] - pub fn uart_cts_inv(&mut self) -> UART_CTS_INV_W { - UART_CTS_INV_W::new(self, 20) - } - #[doc = "Bit 21 - Set this bit to inverse uart dsr level"] - #[inline(always)] - #[must_use] - pub fn uart_dsr_inv(&mut self) -> UART_DSR_INV_W { - UART_DSR_INV_W::new(self, 21) - } - #[doc = "Bit 22 - Set this bit to inverse uart txd level"] - #[inline(always)] - #[must_use] - pub fn uart_txd_inv(&mut self) -> UART_TXD_INV_W { - UART_TXD_INV_W::new(self, 22) - } - #[doc = "Bit 23 - Set this bit to inverse uart rts level"] - #[inline(always)] - #[must_use] - pub fn uart_rts_inv(&mut self) -> UART_RTS_INV_W { - UART_RTS_INV_W::new(self, 23) - } - #[doc = "Bit 24 - Set this bit to inverse uart dtr level"] - #[inline(always)] - #[must_use] - pub fn uart_dtr_inv(&mut self) -> UART_DTR_INV_W { - UART_DTR_INV_W::new(self, 24) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART CONFIG0(UART0 and UART1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CONF0_SPEC; -impl crate::RegisterSpec for UART_CONF0_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_conf0::R`](R) reader structure"] -impl crate::Readable for UART_CONF0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_conf0::W`](W) writer structure"] -impl crate::Writable for UART_CONF0_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CONF0 to value 0"] -impl crate::Resettable for UART_CONF0_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_conf1.rs b/esp8266/src/uart1/uart_conf1.rs deleted file mode 100644 index d5a20399b0..0000000000 --- a/esp8266/src/uart1/uart_conf1.rs +++ /dev/null @@ -1,155 +0,0 @@ -#[doc = "Register `UART_CONF1` reader"] -pub type R = crate::R; -#[doc = "Register `UART_CONF1` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_thrhd` reader - The config bits for rx fifo full threshold,0-127"] -pub type RXFIFO_FULL_THRHD_R = crate::FieldReader; -#[doc = "Field `rxfifo_full_thrhd` writer - The config bits for rx fifo full threshold,0-127"] -pub type RXFIFO_FULL_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `txfifo_empty_thrhd` reader - The config bits for tx fifo empty threshold,0-127"] -pub type TXFIFO_EMPTY_THRHD_R = crate::FieldReader; -#[doc = "Field `txfifo_empty_thrhd` writer - The config bits for tx fifo empty threshold,0-127"] -pub type TXFIFO_EMPTY_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_flow_thrhd` reader - The config bits for rx flow control threshold,0-127"] -pub type RX_FLOW_THRHD_R = crate::FieldReader; -#[doc = "Field `rx_flow_thrhd` writer - The config bits for rx flow control threshold,0-127"] -pub type RX_FLOW_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_flow_en` reader - Set this bit to enable rx hardware flow control"] -pub type RX_FLOW_EN_R = crate::BitReader; -#[doc = "Field `rx_flow_en` writer - Set this bit to enable rx hardware flow control"] -pub type RX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rx_tout_thrhd` reader - Config bits for rx time-out threshold,uint: byte,0-127"] -pub type RX_TOUT_THRHD_R = crate::FieldReader; -#[doc = "Field `rx_tout_thrhd` writer - Config bits for rx time-out threshold,uint: byte,0-127"] -pub type RX_TOUT_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; -#[doc = "Field `rx_tout_en` reader - Set this bit to enable rx time-out function"] -pub type RX_TOUT_EN_R = crate::BitReader; -#[doc = "Field `rx_tout_en` writer - Set this bit to enable rx time-out function"] -pub type RX_TOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:6 - The config bits for rx fifo full threshold,0-127"] - #[inline(always)] - pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R { - RXFIFO_FULL_THRHD_R::new((self.bits & 0x7f) as u8) - } - #[doc = "Bits 8:14 - The config bits for tx fifo empty threshold,0-127"] - #[inline(always)] - pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R { - TXFIFO_EMPTY_THRHD_R::new(((self.bits >> 8) & 0x7f) as u8) - } - #[doc = "Bits 16:22 - The config bits for rx flow control threshold,0-127"] - #[inline(always)] - pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R { - RX_FLOW_THRHD_R::new(((self.bits >> 16) & 0x7f) as u8) - } - #[doc = "Bit 23 - Set this bit to enable rx hardware flow control"] - #[inline(always)] - pub fn rx_flow_en(&self) -> RX_FLOW_EN_R { - RX_FLOW_EN_R::new(((self.bits >> 23) & 1) != 0) - } - #[doc = "Bits 24:30 - Config bits for rx time-out threshold,uint: byte,0-127"] - #[inline(always)] - pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R { - RX_TOUT_THRHD_R::new(((self.bits >> 24) & 0x7f) as u8) - } - #[doc = "Bit 31 - Set this bit to enable rx time-out function"] - #[inline(always)] - pub fn rx_tout_en(&self) -> RX_TOUT_EN_R { - RX_TOUT_EN_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_CONF1") - .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit())) - .field( - "rx_tout_thrhd", - &format_args!("{}", self.rx_tout_thrhd().bits()), - ) - .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit())) - .field( - "rx_flow_thrhd", - &format_args!("{}", self.rx_flow_thrhd().bits()), - ) - .field( - "txfifo_empty_thrhd", - &format_args!("{}", self.txfifo_empty_thrhd().bits()), - ) - .field( - "rxfifo_full_thrhd", - &format_args!("{}", self.rxfifo_full_thrhd().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:6 - The config bits for rx fifo full threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W { - RXFIFO_FULL_THRHD_W::new(self, 0) - } - #[doc = "Bits 8:14 - The config bits for tx fifo empty threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W { - TXFIFO_EMPTY_THRHD_W::new(self, 8) - } - #[doc = "Bits 16:22 - The config bits for rx flow control threshold,0-127"] - #[inline(always)] - #[must_use] - pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W { - RX_FLOW_THRHD_W::new(self, 16) - } - #[doc = "Bit 23 - Set this bit to enable rx hardware flow control"] - #[inline(always)] - #[must_use] - pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W { - RX_FLOW_EN_W::new(self, 23) - } - #[doc = "Bits 24:30 - Config bits for rx time-out threshold,uint: byte,0-127"] - #[inline(always)] - #[must_use] - pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W { - RX_TOUT_THRHD_W::new(self, 24) - } - #[doc = "Bit 31 - Set this bit to enable rx time-out function"] - #[inline(always)] - #[must_use] - pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W { - RX_TOUT_EN_W::new(self, 31) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Set this bit to enable rx time-out function\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_CONF1_SPEC; -impl crate::RegisterSpec for UART_CONF1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_conf1::R`](R) reader structure"] -impl crate::Readable for UART_CONF1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_conf1::W`](W) writer structure"] -impl crate::Writable for UART_CONF1_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_CONF1 to value 0"] -impl crate::Resettable for UART_CONF1_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_date.rs b/esp8266/src/uart1/uart_date.rs deleted file mode 100644 index a6b4b89588..0000000000 --- a/esp8266/src/uart1/uart_date.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `UART_DATE` reader"] -pub type R = crate::R; -#[doc = "Register `UART_DATE` writer"] -pub type W = crate::W; -#[doc = "Field `uart_date` reader - UART HW INFO"] -pub type UART_DATE_R = crate::FieldReader; -#[doc = "Field `uart_date` writer - UART HW INFO"] -pub type UART_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31 - UART HW INFO"] - #[inline(always)] - pub fn uart_date(&self) -> UART_DATE_R { - UART_DATE_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_DATE") - .field("uart_date", &format_args!("{}", self.uart_date().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31 - UART HW INFO"] - #[inline(always)] - #[must_use] - pub fn uart_date(&mut self) -> UART_DATE_W { - UART_DATE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART HW INFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_DATE_SPEC; -impl crate::RegisterSpec for UART_DATE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_date::R`](R) reader structure"] -impl crate::Readable for UART_DATE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_date::W`](W) writer structure"] -impl crate::Writable for UART_DATE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_DATE to value 0"] -impl crate::Resettable for UART_DATE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_fifo.rs b/esp8266/src/uart1/uart_fifo.rs deleted file mode 100644 index 73a2a1e6af..0000000000 --- a/esp8266/src/uart1/uart_fifo.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = "Register `UART_FIFO` reader"] -pub type R = crate::R; -#[doc = "Register `UART_FIFO` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_rd_byte` reader - R/W share the same address"] -pub type RXFIFO_RD_BYTE_R = crate::FieldReader; -#[doc = "Field `rxfifo_write_byte` reader - R/W share the same address"] -pub type RXFIFO_WRITE_BYTE_R = crate::FieldReader; -#[doc = "Field `rxfifo_write_byte` writer - R/W share the same address"] -pub type RXFIFO_WRITE_BYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -impl R { - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - pub fn rxfifo_rd_byte(&self) -> RXFIFO_RD_BYTE_R { - RXFIFO_RD_BYTE_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - pub fn rxfifo_write_byte(&self) -> RXFIFO_WRITE_BYTE_R { - RXFIFO_WRITE_BYTE_R::new((self.bits & 0xff) as u8) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_FIFO") - .field( - "rxfifo_rd_byte", - &format_args!("{}", self.rxfifo_rd_byte().bits()), - ) - .field( - "rxfifo_write_byte", - &format_args!("{}", self.rxfifo_write_byte().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:7 - R/W share the same address"] - #[inline(always)] - #[must_use] - pub fn rxfifo_write_byte(&mut self) -> RXFIFO_WRITE_BYTE_W { - RXFIFO_WRITE_BYTE_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART FIFO,length 128\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_FIFO_SPEC; -impl crate::RegisterSpec for UART_FIFO_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_fifo::R`](R) reader structure"] -impl crate::Readable for UART_FIFO_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_fifo::W`](W) writer structure"] -impl crate::Writable for UART_FIFO_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_FIFO to value 0"] -impl crate::Resettable for UART_FIFO_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_highpulse.rs b/esp8266/src/uart1/uart_highpulse.rs deleted file mode 100644 index 92d559c993..0000000000 --- a/esp8266/src/uart1/uart_highpulse.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_HIGHPULSE` reader"] -pub type R = crate::R; -#[doc = "Field `highpulse_min_cnt` reader - used in baudrate detect"] -pub type HIGHPULSE_MIN_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:19 - used in baudrate detect"] - #[inline(always)] - pub fn highpulse_min_cnt(&self) -> HIGHPULSE_MIN_CNT_R { - HIGHPULSE_MIN_CNT_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_HIGHPULSE") - .field( - "highpulse_min_cnt", - &format_args!("{}", self.highpulse_min_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_HIGHPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_highpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_HIGHPULSE_SPEC; -impl crate::RegisterSpec for UART_HIGHPULSE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_highpulse::R`](R) reader structure"] -impl crate::Readable for UART_HIGHPULSE_SPEC {} -#[doc = "`reset()` method sets UART_HIGHPULSE to value 0"] -impl crate::Resettable for UART_HIGHPULSE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_id.rs b/esp8266/src/uart1/uart_id.rs deleted file mode 100644 index be80237ad9..0000000000 --- a/esp8266/src/uart1/uart_id.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `UART_ID` reader"] -pub type R = crate::R; -#[doc = "Register `UART_ID` writer"] -pub type W = crate::W; -#[doc = "Field `uart_id` reader - "] -pub type UART_ID_R = crate::FieldReader; -#[doc = "Field `uart_id` writer - "] -pub type UART_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn uart_id(&self) -> UART_ID_R { - UART_ID_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_ID") - .field("uart_id", &format_args!("{}", self.uart_id().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn uart_id(&mut self) -> UART_ID_W { - UART_ID_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART_ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_ID_SPEC; -impl crate::RegisterSpec for UART_ID_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_id::R`](R) reader structure"] -impl crate::Readable for UART_ID_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_id::W`](W) writer structure"] -impl crate::Writable for UART_ID_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_ID to value 0"] -impl crate::Resettable for UART_ID_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_int_clr.rs b/esp8266/src/uart1/uart_int_clr.rs deleted file mode 100644 index 9c4b71a2d0..0000000000 --- a/esp8266/src/uart1/uart_int_clr.rs +++ /dev/null @@ -1,106 +0,0 @@ -#[doc = "Register `UART_INT_CLR` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_int_clr` writer - Set this bit to clear the rx fifo full interrupt"] -pub type RXFIFO_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_empty_int_clr` writer - Set this bit to clear the tx fifo empty interrupt"] -pub type TXFIFO_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_err_int_clr` writer - Set this bit to clear the parity error interrupt"] -pub type PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frm_err_int_clr` writer - Set this bit to clear other rx error interrupt"] -pub type FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_ovf_int_clr` writer - Set this bit to clear the rx fifo over-flow interrupt"] -pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dsr_chg_int_clr` writer - Set this bit to clear the DSR changing interrupt"] -pub type DSR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cts_chg_int_clr` writer - Set this bit to clear the CTS changing interrupt"] -pub type CTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `brk_det_int_clr` writer - Set this bit to clear the rx byte start interrupt"] -pub type BRK_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_tout_int_clr` writer - Set this bit to clear the rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W { - #[doc = "Bit 0 - Set this bit to clear the rx fifo full interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W { - RXFIFO_FULL_INT_CLR_W::new(self, 0) - } - #[doc = "Bit 1 - Set this bit to clear the tx fifo empty interrupt"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W { - TXFIFO_EMPTY_INT_CLR_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to clear the parity error interrupt"] - #[inline(always)] - #[must_use] - pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W { - PARITY_ERR_INT_CLR_W::new(self, 2) - } - #[doc = "Bit 3 - Set this bit to clear other rx error interrupt"] - #[inline(always)] - #[must_use] - pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W { - FRM_ERR_INT_CLR_W::new(self, 3) - } - #[doc = "Bit 4 - Set this bit to clear the rx fifo over-flow interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { - RXFIFO_OVF_INT_CLR_W::new(self, 4) - } - #[doc = "Bit 5 - Set this bit to clear the DSR changing interrupt"] - #[inline(always)] - #[must_use] - pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W { - DSR_CHG_INT_CLR_W::new(self, 5) - } - #[doc = "Bit 6 - Set this bit to clear the CTS changing interrupt"] - #[inline(always)] - #[must_use] - pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W { - CTS_CHG_INT_CLR_W::new(self, 6) - } - #[doc = "Bit 7 - Set this bit to clear the rx byte start interrupt"] - #[inline(always)] - #[must_use] - pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W { - BRK_DET_INT_CLR_W::new(self, 7) - } - #[doc = "Bit 8 - Set this bit to clear the rx time-out interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W { - RXFIFO_TOUT_INT_CLR_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART INTERRUPT CLEAR REGISTER\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_CLR_SPEC; -impl crate::RegisterSpec for UART_INT_CLR_SPEC { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`uart_int_clr::W`](W) writer structure"] -impl crate::Writable for UART_INT_CLR_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_INT_CLR to value 0"] -impl crate::Resettable for UART_INT_CLR_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_int_ena.rs b/esp8266/src/uart1/uart_int_ena.rs deleted file mode 100644 index e5e2db0d9c..0000000000 --- a/esp8266/src/uart1/uart_int_ena.rs +++ /dev/null @@ -1,218 +0,0 @@ -#[doc = "Register `UART_INT_ENA` reader"] -pub type R = crate::R; -#[doc = "Register `UART_INT_ENA` writer"] -pub type W = crate::W; -#[doc = "Field `rxfifo_full_int_ena` reader - The interrupt enable bit for rx fifo full event"] -pub type RXFIFO_FULL_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_full_int_ena` writer - The interrupt enable bit for rx fifo full event"] -pub type RXFIFO_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `txfifo_empty_int_ena` reader - The interrupt enable bit for tx fifo empty event"] -pub type TXFIFO_EMPTY_INT_ENA_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_ena` writer - The interrupt enable bit for tx fifo empty event"] -pub type TXFIFO_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `parity_err_int_ena` reader - The interrupt enable bit for parity error"] -pub type PARITY_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `parity_err_int_ena` writer - The interrupt enable bit for parity error"] -pub type PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `frm_err_int_ena` reader - The interrupt enable bit for other rx error"] -pub type FRM_ERR_INT_ENA_R = crate::BitReader; -#[doc = "Field `frm_err_int_ena` writer - The interrupt enable bit for other rx error"] -pub type FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_ovf_int_ena` reader - The interrupt enable bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_ena` writer - The interrupt enable bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dsr_chg_int_ena` reader - The interrupt enable bit for DSR changing level"] -pub type DSR_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_ena` writer - The interrupt enable bit for DSR changing level"] -pub type DSR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `cts_chg_int_ena` reader - The interrupt enable bit for CTS changing level"] -pub type CTS_CHG_INT_ENA_R = crate::BitReader; -#[doc = "Field `cts_chg_int_ena` writer - The interrupt enable bit for CTS changing level"] -pub type CTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `brk_det_int_ena` reader - The interrupt enable bit for rx byte start error"] -pub type BRK_DET_INT_ENA_R = crate::BitReader; -#[doc = "Field `brk_det_int_ena` writer - The interrupt enable bit for rx byte start error"] -pub type BRK_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rxfifo_tout_int_ena` reader - The interrupt enable bit for rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_ENA_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_ena` writer - The interrupt enable bit for rx time-out interrupt"] -pub type RXFIFO_TOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - The interrupt enable bit for rx fifo full event"] - #[inline(always)] - pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R { - RXFIFO_FULL_INT_ENA_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt enable bit for tx fifo empty event"] - #[inline(always)] - pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R { - TXFIFO_EMPTY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt enable bit for parity error"] - #[inline(always)] - pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R { - PARITY_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt enable bit for other rx error"] - #[inline(always)] - pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R { - FRM_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt enable bit for rx fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { - RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt enable bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R { - DSR_CHG_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt enable bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R { - CTS_CHG_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt enable bit for rx byte start error"] - #[inline(always)] - pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R { - BRK_DET_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt enable bit for rx time-out interrupt"] - #[inline(always)] - pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R { - RXFIFO_TOUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_ENA") - .field( - "rxfifo_tout_int_ena", - &format_args!("{}", self.rxfifo_tout_int_ena().bit()), - ) - .field( - "brk_det_int_ena", - &format_args!("{}", self.brk_det_int_ena().bit()), - ) - .field( - "cts_chg_int_ena", - &format_args!("{}", self.cts_chg_int_ena().bit()), - ) - .field( - "dsr_chg_int_ena", - &format_args!("{}", self.dsr_chg_int_ena().bit()), - ) - .field( - "rxfifo_ovf_int_ena", - &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), - ) - .field( - "frm_err_int_ena", - &format_args!("{}", self.frm_err_int_ena().bit()), - ) - .field( - "parity_err_int_ena", - &format_args!("{}", self.parity_err_int_ena().bit()), - ) - .field( - "txfifo_empty_int_ena", - &format_args!("{}", self.txfifo_empty_int_ena().bit()), - ) - .field( - "rxfifo_full_int_ena", - &format_args!("{}", self.rxfifo_full_int_ena().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bit 0 - The interrupt enable bit for rx fifo full event"] - #[inline(always)] - #[must_use] - pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W { - RXFIFO_FULL_INT_ENA_W::new(self, 0) - } - #[doc = "Bit 1 - The interrupt enable bit for tx fifo empty event"] - #[inline(always)] - #[must_use] - pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W { - TXFIFO_EMPTY_INT_ENA_W::new(self, 1) - } - #[doc = "Bit 2 - The interrupt enable bit for parity error"] - #[inline(always)] - #[must_use] - pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W { - PARITY_ERR_INT_ENA_W::new(self, 2) - } - #[doc = "Bit 3 - The interrupt enable bit for other rx error"] - #[inline(always)] - #[must_use] - pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W { - FRM_ERR_INT_ENA_W::new(self, 3) - } - #[doc = "Bit 4 - The interrupt enable bit for rx fifo overflow"] - #[inline(always)] - #[must_use] - pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { - RXFIFO_OVF_INT_ENA_W::new(self, 4) - } - #[doc = "Bit 5 - The interrupt enable bit for DSR changing level"] - #[inline(always)] - #[must_use] - pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W { - DSR_CHG_INT_ENA_W::new(self, 5) - } - #[doc = "Bit 6 - The interrupt enable bit for CTS changing level"] - #[inline(always)] - #[must_use] - pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W { - CTS_CHG_INT_ENA_W::new(self, 6) - } - #[doc = "Bit 7 - The interrupt enable bit for rx byte start error"] - #[inline(always)] - #[must_use] - pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W { - BRK_DET_INT_ENA_W::new(self, 7) - } - #[doc = "Bit 8 - The interrupt enable bit for rx time-out interrupt"] - #[inline(always)] - #[must_use] - pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W { - RXFIFO_TOUT_INT_ENA_W::new(self, 8) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "UART INTERRUPT ENABLE REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_ENA_SPEC; -impl crate::RegisterSpec for UART_INT_ENA_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_ena::R`](R) reader structure"] -impl crate::Readable for UART_INT_ENA_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart_int_ena::W`](W) writer structure"] -impl crate::Writable for UART_INT_ENA_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets UART_INT_ENA to value 0"] -impl crate::Resettable for UART_INT_ENA_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_int_raw.rs b/esp8266/src/uart1/uart_int_raw.rs deleted file mode 100644 index 27768369ae..0000000000 --- a/esp8266/src/uart1/uart_int_raw.rs +++ /dev/null @@ -1,127 +0,0 @@ -#[doc = "Register `UART_INT_RAW` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_full_int_raw` reader - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)"] -pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_raw` reader - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)"] -pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader; -#[doc = "Field `parity_err_int_raw` reader - The interrupt raw bit for parity check error"] -pub type PARITY_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `frm_err_int_raw` reader - The interrupt raw bit for other rx error"] -pub type FRM_ERR_INT_RAW_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_raw` reader - The interrupt raw bit for rx fifo overflow"] -pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_raw` reader - The interrupt raw bit for DSR changing level"] -pub type DSR_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `cts_chg_int_raw` reader - The interrupt raw bit for CTS changing level"] -pub type CTS_CHG_INT_RAW_R = crate::BitReader; -#[doc = "Field `brk_det_int_raw` reader - The interrupt raw bit for Rx byte start error"] -pub type BRK_DET_INT_RAW_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_raw` reader - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)"] -pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)"] - #[inline(always)] - pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R { - RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)"] - #[inline(always)] - pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R { - TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt raw bit for parity check error"] - #[inline(always)] - pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R { - PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt raw bit for other rx error"] - #[inline(always)] - pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R { - FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt raw bit for rx fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { - RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt raw bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R { - DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt raw bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R { - CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt raw bit for Rx byte start error"] - #[inline(always)] - pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R { - BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)"] - #[inline(always)] - pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R { - RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_RAW") - .field( - "rxfifo_tout_int_raw", - &format_args!("{}", self.rxfifo_tout_int_raw().bit()), - ) - .field( - "brk_det_int_raw", - &format_args!("{}", self.brk_det_int_raw().bit()), - ) - .field( - "cts_chg_int_raw", - &format_args!("{}", self.cts_chg_int_raw().bit()), - ) - .field( - "dsr_chg_int_raw", - &format_args!("{}", self.dsr_chg_int_raw().bit()), - ) - .field( - "rxfifo_ovf_int_raw", - &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), - ) - .field( - "frm_err_int_raw", - &format_args!("{}", self.frm_err_int_raw().bit()), - ) - .field( - "parity_err_int_raw", - &format_args!("{}", self.parity_err_int_raw().bit()), - ) - .field( - "txfifo_empty_int_raw", - &format_args!("{}", self.txfifo_empty_int_raw().bit()), - ) - .field( - "rxfifo_full_int_raw", - &format_args!("{}", self.rxfifo_full_int_raw().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART INTERRUPT RAW STATE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_RAW_SPEC; -impl crate::RegisterSpec for UART_INT_RAW_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_raw::R`](R) reader structure"] -impl crate::Readable for UART_INT_RAW_SPEC {} -#[doc = "`reset()` method sets UART_INT_RAW to value 0"] -impl crate::Resettable for UART_INT_RAW_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_int_st.rs b/esp8266/src/uart1/uart_int_st.rs deleted file mode 100644 index 7fd6d56576..0000000000 --- a/esp8266/src/uart1/uart_int_st.rs +++ /dev/null @@ -1,127 +0,0 @@ -#[doc = "Register `UART_INT_ST` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_full_int_st` reader - The interrupt state bit for RX fifo full event"] -pub type RXFIFO_FULL_INT_ST_R = crate::BitReader; -#[doc = "Field `txfifo_empty_int_st` reader - The interrupt state bit for TX fifo empty"] -pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader; -#[doc = "Field `parity_err_int_st` reader - The interrupt state bit for rx parity error"] -pub type PARITY_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `frm_err_int_st` reader - The interrupt state for other rx error"] -pub type FRM_ERR_INT_ST_R = crate::BitReader; -#[doc = "Field `rxfifo_ovf_int_st` reader - The interrupt state bit for RX fifo overflow"] -pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; -#[doc = "Field `dsr_chg_int_st` reader - The interrupt state bit for DSR changing level"] -pub type DSR_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `cts_chg_int_st` reader - The interrupt state bit for CTS changing level"] -pub type CTS_CHG_INT_ST_R = crate::BitReader; -#[doc = "Field `brk_det_int_st` reader - The interrupt state bit for rx byte start error"] -pub type BRK_DET_INT_ST_R = crate::BitReader; -#[doc = "Field `rxfifo_tout_int_st` reader - The interrupt state bit for Rx time-out event"] -pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - The interrupt state bit for RX fifo full event"] - #[inline(always)] - pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R { - RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - The interrupt state bit for TX fifo empty"] - #[inline(always)] - pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R { - TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - The interrupt state bit for rx parity error"] - #[inline(always)] - pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R { - PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3 - The interrupt state for other rx error"] - #[inline(always)] - pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R { - FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4 - The interrupt state bit for RX fifo overflow"] - #[inline(always)] - pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { - RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5 - The interrupt state bit for DSR changing level"] - #[inline(always)] - pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R { - DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0) - } - #[doc = "Bit 6 - The interrupt state bit for CTS changing level"] - #[inline(always)] - pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R { - CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - The interrupt state bit for rx byte start error"] - #[inline(always)] - pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R { - BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bit 8 - The interrupt state bit for Rx time-out event"] - #[inline(always)] - pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R { - RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_INT_ST") - .field( - "rxfifo_tout_int_st", - &format_args!("{}", self.rxfifo_tout_int_st().bit()), - ) - .field( - "brk_det_int_st", - &format_args!("{}", self.brk_det_int_st().bit()), - ) - .field( - "cts_chg_int_st", - &format_args!("{}", self.cts_chg_int_st().bit()), - ) - .field( - "dsr_chg_int_st", - &format_args!("{}", self.dsr_chg_int_st().bit()), - ) - .field( - "rxfifo_ovf_int_st", - &format_args!("{}", self.rxfifo_ovf_int_st().bit()), - ) - .field( - "frm_err_int_st", - &format_args!("{}", self.frm_err_int_st().bit()), - ) - .field( - "parity_err_int_st", - &format_args!("{}", self.parity_err_int_st().bit()), - ) - .field( - "txfifo_empty_int_st", - &format_args!("{}", self.txfifo_empty_int_st().bit()), - ) - .field( - "rxfifo_full_int_st", - &format_args!("{}", self.rxfifo_full_int_st().bit()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_INT_ST_SPEC; -impl crate::RegisterSpec for UART_INT_ST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_int_st::R`](R) reader structure"] -impl crate::Readable for UART_INT_ST_SPEC {} -#[doc = "`reset()` method sets UART_INT_ST to value 0"] -impl crate::Resettable for UART_INT_ST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_lowpulse.rs b/esp8266/src/uart1/uart_lowpulse.rs deleted file mode 100644 index 15d8cf5750..0000000000 --- a/esp8266/src/uart1/uart_lowpulse.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_LOWPULSE` reader"] -pub type R = crate::R; -#[doc = "Field `lowpulse_min_cnt` reader - used in baudrate detect"] -pub type LOWPULSE_MIN_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:19 - used in baudrate detect"] - #[inline(always)] - pub fn lowpulse_min_cnt(&self) -> LOWPULSE_MIN_CNT_R { - LOWPULSE_MIN_CNT_R::new(self.bits & 0x000f_ffff) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_LOWPULSE") - .field( - "lowpulse_min_cnt", - &format_args!("{}", self.lowpulse_min_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_LOWPULSE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_lowpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_LOWPULSE_SPEC; -impl crate::RegisterSpec for UART_LOWPULSE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_lowpulse::R`](R) reader structure"] -impl crate::Readable for UART_LOWPULSE_SPEC {} -#[doc = "`reset()` method sets UART_LOWPULSE to value 0"] -impl crate::Resettable for UART_LOWPULSE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_rxd_cnt.rs b/esp8266/src/uart1/uart_rxd_cnt.rs deleted file mode 100644 index 8e0293ab2e..0000000000 --- a/esp8266/src/uart1/uart_rxd_cnt.rs +++ /dev/null @@ -1,39 +0,0 @@ -#[doc = "Register `UART_RXD_CNT` reader"] -pub type R = crate::R; -#[doc = "Field `rxd_edge_cnt` reader - used in baudrate detect"] -pub type RXD_EDGE_CNT_R = crate::FieldReader; -impl R { - #[doc = "Bits 0:9 - used in baudrate detect"] - #[inline(always)] - pub fn rxd_edge_cnt(&self) -> RXD_EDGE_CNT_R { - RXD_EDGE_CNT_R::new((self.bits & 0x03ff) as u16) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_RXD_CNT") - .field( - "rxd_edge_cnt", - &format_args!("{}", self.rxd_edge_cnt().bits()), - ) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART_RXD_CNT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_rxd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_RXD_CNT_SPEC; -impl crate::RegisterSpec for UART_RXD_CNT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_rxd_cnt::R`](R) reader structure"] -impl crate::Readable for UART_RXD_CNT_SPEC {} -#[doc = "`reset()` method sets UART_RXD_CNT to value 0"] -impl crate::Resettable for UART_RXD_CNT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/uart1/uart_status.rs b/esp8266/src/uart1/uart_status.rs deleted file mode 100644 index 5cd1b4cff0..0000000000 --- a/esp8266/src/uart1/uart_status.rs +++ /dev/null @@ -1,92 +0,0 @@ -#[doc = "Register `UART_STATUS` reader"] -pub type R = crate::R; -#[doc = "Field `rxfifo_cnt` reader - Number of data in uart rx fifo"] -pub type RXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `dsrn` reader - The level of uart dsr pin"] -pub type DSRN_R = crate::BitReader; -#[doc = "Field `ctsn` reader - The level of uart cts pin"] -pub type CTSN_R = crate::BitReader; -#[doc = "Field `rxd` reader - The level of uart rxd pin"] -pub type RXD_R = crate::BitReader; -#[doc = "Field `txfifo_cnt` reader - Number of data in UART TX fifo"] -pub type TXFIFO_CNT_R = crate::FieldReader; -#[doc = "Field `dtrn` reader - The level of uart dtr pin"] -pub type DTRN_R = crate::BitReader; -#[doc = "Field `rtsn` reader - The level of uart rts pin"] -pub type RTSN_R = crate::BitReader; -#[doc = "Field `txd` reader - The level of the uart txd pin"] -pub type TXD_R = crate::BitReader; -impl R { - #[doc = "Bits 0:7 - Number of data in uart rx fifo"] - #[inline(always)] - pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { - RXFIFO_CNT_R::new((self.bits & 0xff) as u8) - } - #[doc = "Bit 13 - The level of uart dsr pin"] - #[inline(always)] - pub fn dsrn(&self) -> DSRN_R { - DSRN_R::new(((self.bits >> 13) & 1) != 0) - } - #[doc = "Bit 14 - The level of uart cts pin"] - #[inline(always)] - pub fn ctsn(&self) -> CTSN_R { - CTSN_R::new(((self.bits >> 14) & 1) != 0) - } - #[doc = "Bit 15 - The level of uart rxd pin"] - #[inline(always)] - pub fn rxd(&self) -> RXD_R { - RXD_R::new(((self.bits >> 15) & 1) != 0) - } - #[doc = "Bits 16:23 - Number of data in UART TX fifo"] - #[inline(always)] - pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { - TXFIFO_CNT_R::new(((self.bits >> 16) & 0xff) as u8) - } - #[doc = "Bit 29 - The level of uart dtr pin"] - #[inline(always)] - pub fn dtrn(&self) -> DTRN_R { - DTRN_R::new(((self.bits >> 29) & 1) != 0) - } - #[doc = "Bit 30 - The level of uart rts pin"] - #[inline(always)] - pub fn rtsn(&self) -> RTSN_R { - RTSN_R::new(((self.bits >> 30) & 1) != 0) - } - #[doc = "Bit 31 - The level of the uart txd pin"] - #[inline(always)] - pub fn txd(&self) -> TXD_R { - TXD_R::new(((self.bits >> 31) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART_STATUS") - .field("txd", &format_args!("{}", self.txd().bit())) - .field("rtsn", &format_args!("{}", self.rtsn().bit())) - .field("dtrn", &format_args!("{}", self.dtrn().bit())) - .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) - .field("rxd", &format_args!("{}", self.rxd().bit())) - .field("ctsn", &format_args!("{}", self.ctsn().bit())) - .field("dsrn", &format_args!("{}", self.dsrn().bit())) - .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "UART STATUS REGISTER\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART_STATUS_SPEC; -impl crate::RegisterSpec for UART_STATUS_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart_status::R`](R) reader structure"] -impl crate::Readable for UART_STATUS_SPEC {} -#[doc = "`reset()` method sets UART_STATUS to value 0"] -impl crate::Resettable for UART_STATUS_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt.rs b/esp8266/src/wdt.rs deleted file mode 100644 index d8e0f96595..0000000000 --- a/esp8266/src/wdt.rs +++ /dev/null @@ -1,77 +0,0 @@ -#[doc = r"Register block"] -#[repr(C)] -#[cfg_attr(feature = "impl-register-debug", derive(Debug))] -pub struct RegisterBlock { - wdt_ctl: WDT_CTL, - wdt_op: WDT_OP, - wdt_op_nd: WDT_OP_ND, - count: COUNT, - stage: STAGE, - wdt_rst: WDT_RST, - reset_stage: RESET_STAGE, -} -impl RegisterBlock { - #[doc = "0x00 - WDT_CTL"] - #[inline(always)] - pub const fn wdt_ctl(&self) -> &WDT_CTL { - &self.wdt_ctl - } - #[doc = "0x04 - Reload value for stage 0"] - #[inline(always)] - pub const fn wdt_op(&self) -> &WDT_OP { - &self.wdt_op - } - #[doc = "0x08 - Reload value for stage 1"] - #[inline(always)] - pub const fn wdt_op_nd(&self) -> &WDT_OP_ND { - &self.wdt_op_nd - } - #[doc = "0x0c - Watchdog clock cycle count"] - #[inline(always)] - pub const fn count(&self) -> &COUNT { - &self.count - } - #[doc = "0x10 - The current watchdog stage"] - #[inline(always)] - pub const fn stage(&self) -> &STAGE { - &self.stage - } - #[doc = "0x14 - Watchdog reset"] - #[inline(always)] - pub const fn wdt_rst(&self) -> &WDT_RST { - &self.wdt_rst - } - #[doc = "0x18 - Watchdog stage reset"] - #[inline(always)] - pub const fn reset_stage(&self) -> &RESET_STAGE { - &self.reset_stage - } -} -#[doc = "WDT_CTL (rw) register accessor: WDT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ctl`] module"] -pub type WDT_CTL = crate::Reg; -#[doc = "WDT_CTL"] -pub mod wdt_ctl; -#[doc = "WDT_OP (rw) register accessor: Reload value for stage 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_op::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_op::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_op`] module"] -pub type WDT_OP = crate::Reg; -#[doc = "Reload value for stage 0"] -pub mod wdt_op; -#[doc = "WDT_OP_ND (rw) register accessor: Reload value for stage 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_op_nd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_op_nd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_op_nd`] module"] -pub type WDT_OP_ND = crate::Reg; -#[doc = "Reload value for stage 1"] -pub mod wdt_op_nd; -#[doc = "WDT_RST (rw) register accessor: Watchdog reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_rst::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_rst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_rst`] module"] -pub type WDT_RST = crate::Reg; -#[doc = "Watchdog reset"] -pub mod wdt_rst; -#[doc = "count (rw) register accessor: Watchdog clock cycle count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@count`] module"] -pub type COUNT = crate::Reg; -#[doc = "Watchdog clock cycle count"] -pub mod count; -#[doc = "stage (rw) register accessor: The current watchdog stage\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stage`] module"] -pub type STAGE = crate::Reg; -#[doc = "The current watchdog stage"] -pub mod stage; -#[doc = "reset_stage (rw) register accessor: Watchdog stage reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_stage::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_stage::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_stage`] module"] -pub type RESET_STAGE = crate::Reg; -#[doc = "Watchdog stage reset"] -pub mod reset_stage; diff --git a/esp8266/src/wdt/count.rs b/esp8266/src/wdt/count.rs deleted file mode 100644 index a2e94beee4..0000000000 --- a/esp8266/src/wdt/count.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `count` reader"] -pub type R = crate::R; -#[doc = "Register `count` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Watchdog clock cycle count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct COUNT_SPEC; -impl crate::RegisterSpec for COUNT_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`count::R`](R) reader structure"] -impl crate::Readable for COUNT_SPEC {} -#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"] -impl crate::Writable for COUNT_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets count to value 0"] -impl crate::Resettable for COUNT_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/reset_stage.rs b/esp8266/src/wdt/reset_stage.rs deleted file mode 100644 index 6c5d1f675c..0000000000 --- a/esp8266/src/wdt/reset_stage.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `reset_stage` reader"] -pub type R = crate::R; -#[doc = "Register `reset_stage` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Watchdog stage reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_stage::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_stage::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct RESET_STAGE_SPEC; -impl crate::RegisterSpec for RESET_STAGE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`reset_stage::R`](R) reader structure"] -impl crate::Readable for RESET_STAGE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`reset_stage::W`](W) writer structure"] -impl crate::Writable for RESET_STAGE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets reset_stage to value 0"] -impl crate::Resettable for RESET_STAGE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/stage.rs b/esp8266/src/wdt/stage.rs deleted file mode 100644 index 68d0e55024..0000000000 --- a/esp8266/src/wdt/stage.rs +++ /dev/null @@ -1,44 +0,0 @@ -#[doc = "Register `stage` reader"] -pub type R = crate::R; -#[doc = "Register `stage` writer"] -pub type W = crate::W; -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "The current watchdog stage\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stage::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stage::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct STAGE_SPEC; -impl crate::RegisterSpec for STAGE_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`stage::R`](R) reader structure"] -impl crate::Readable for STAGE_SPEC {} -#[doc = "`write(|w| ..)` method takes [`stage::W`](W) writer structure"] -impl crate::Writable for STAGE_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets stage to value 0"] -impl crate::Resettable for STAGE_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/wdt_ctl.rs b/esp8266/src/wdt/wdt_ctl.rs deleted file mode 100644 index 33eeda313f..0000000000 --- a/esp8266/src/wdt/wdt_ctl.rs +++ /dev/null @@ -1,165 +0,0 @@ -#[doc = "Register `WDT_CTL` reader"] -pub type R = crate::R; -#[doc = "Register `WDT_CTL` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -#[doc = "Field `enable` reader - Enable the watchdog timer."] -pub type ENABLE_R = crate::BitReader; -#[doc = "Field `enable` writer - Enable the watchdog timer."] -pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `stage_1_no_reset` reader - When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device."] -pub type STAGE_1_NO_RESET_R = crate::BitReader; -#[doc = "Field `stage_1_no_reset` writer - When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device."] -pub type STAGE_1_NO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `stage_1_disable` reader - Set to 1 to disable the stage 1 of the watchdog timer"] -pub type STAGE_1_DISABLE_R = crate::BitReader; -#[doc = "Field `stage_1_disable` writer - Set to 1 to disable the stage 1 of the watchdog timer"] -pub type STAGE_1_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `unknown_3` reader - "] -pub type UNKNOWN_3_R = crate::BitReader; -#[doc = "Field `unknown_3` writer - "] -pub type UNKNOWN_3_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `unknown_4` reader - "] -pub type UNKNOWN_4_R = crate::BitReader; -#[doc = "Field `unknown_4` writer - "] -pub type UNKNOWN_4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `unknown_5` reader - "] -pub type UNKNOWN_5_R = crate::BitReader; -#[doc = "Field `unknown_5` writer - "] -pub type UNKNOWN_5_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } - #[doc = "Bit 0 - Enable the watchdog timer."] - #[inline(always)] - pub fn enable(&self) -> ENABLE_R { - ENABLE_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device."] - #[inline(always)] - pub fn stage_1_no_reset(&self) -> STAGE_1_NO_RESET_R { - STAGE_1_NO_RESET_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Set to 1 to disable the stage 1 of the watchdog timer"] - #[inline(always)] - pub fn stage_1_disable(&self) -> STAGE_1_DISABLE_R { - STAGE_1_DISABLE_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bit 3"] - #[inline(always)] - pub fn unknown_3(&self) -> UNKNOWN_3_R { - UNKNOWN_3_R::new(((self.bits >> 3) & 1) != 0) - } - #[doc = "Bit 4"] - #[inline(always)] - pub fn unknown_4(&self) -> UNKNOWN_4_R { - UNKNOWN_4_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 5"] - #[inline(always)] - pub fn unknown_5(&self) -> UNKNOWN_5_R { - UNKNOWN_5_R::new(((self.bits >> 5) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WDT_CTL") - .field("register", &format_args!("{}", self.register().bits())) - .field("enable", &format_args!("{}", self.enable().bit())) - .field( - "stage_1_no_reset", - &format_args!("{}", self.stage_1_no_reset().bit()), - ) - .field( - "stage_1_disable", - &format_args!("{}", self.stage_1_disable().bit()), - ) - .field("unknown_3", &format_args!("{}", self.unknown_3().bit())) - .field("unknown_4", &format_args!("{}", self.unknown_4().bit())) - .field("unknown_5", &format_args!("{}", self.unknown_5().bit())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = "Bit 0 - Enable the watchdog timer."] - #[inline(always)] - #[must_use] - pub fn enable(&mut self) -> ENABLE_W { - ENABLE_W::new(self, 0) - } - #[doc = "Bit 1 - When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device."] - #[inline(always)] - #[must_use] - pub fn stage_1_no_reset(&mut self) -> STAGE_1_NO_RESET_W { - STAGE_1_NO_RESET_W::new(self, 1) - } - #[doc = "Bit 2 - Set to 1 to disable the stage 1 of the watchdog timer"] - #[inline(always)] - #[must_use] - pub fn stage_1_disable(&mut self) -> STAGE_1_DISABLE_W { - STAGE_1_DISABLE_W::new(self, 2) - } - #[doc = "Bit 3"] - #[inline(always)] - #[must_use] - pub fn unknown_3(&mut self) -> UNKNOWN_3_W { - UNKNOWN_3_W::new(self, 3) - } - #[doc = "Bit 4"] - #[inline(always)] - #[must_use] - pub fn unknown_4(&mut self) -> UNKNOWN_4_W { - UNKNOWN_4_W::new(self, 4) - } - #[doc = "Bit 5"] - #[inline(always)] - #[must_use] - pub fn unknown_5(&mut self) -> UNKNOWN_5_W { - UNKNOWN_5_W::new(self, 5) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "WDT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WDT_CTL_SPEC; -impl crate::RegisterSpec for WDT_CTL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`wdt_ctl::R`](R) reader structure"] -impl crate::Readable for WDT_CTL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`wdt_ctl::W`](W) writer structure"] -impl crate::Writable for WDT_CTL_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets WDT_CTL to value 0"] -impl crate::Resettable for WDT_CTL_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/wdt_op.rs b/esp8266/src/wdt/wdt_op.rs deleted file mode 100644 index ff1dca97c6..0000000000 --- a/esp8266/src/wdt/wdt_op.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `WDT_OP` reader"] -pub type R = crate::R; -#[doc = "Register `WDT_OP` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WDT_OP") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Reload value for stage 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_op::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_op::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WDT_OP_SPEC; -impl crate::RegisterSpec for WDT_OP_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`wdt_op::R`](R) reader structure"] -impl crate::Readable for WDT_OP_SPEC {} -#[doc = "`write(|w| ..)` method takes [`wdt_op::W`](W) writer structure"] -impl crate::Writable for WDT_OP_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets WDT_OP to value 0"] -impl crate::Resettable for WDT_OP_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/wdt_op_nd.rs b/esp8266/src/wdt/wdt_op_nd.rs deleted file mode 100644 index 1b25eed684..0000000000 --- a/esp8266/src/wdt/wdt_op_nd.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `WDT_OP_ND` reader"] -pub type R = crate::R; -#[doc = "Register `WDT_OP_ND` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WDT_OP_ND") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Reload value for stage 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_op_nd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_op_nd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WDT_OP_ND_SPEC; -impl crate::RegisterSpec for WDT_OP_ND_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`wdt_op_nd::R`](R) reader structure"] -impl crate::Readable for WDT_OP_ND_SPEC {} -#[doc = "`write(|w| ..)` method takes [`wdt_op_nd::W`](W) writer structure"] -impl crate::Writable for WDT_OP_ND_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets WDT_OP_ND to value 0"] -impl crate::Resettable for WDT_OP_ND_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/src/wdt/wdt_rst.rs b/esp8266/src/wdt/wdt_rst.rs deleted file mode 100644 index 48b358ccce..0000000000 --- a/esp8266/src/wdt/wdt_rst.rs +++ /dev/null @@ -1,63 +0,0 @@ -#[doc = "Register `WDT_RST` reader"] -pub type R = crate::R; -#[doc = "Register `WDT_RST` writer"] -pub type W = crate::W; -#[doc = "Field `Register` reader - "] -pub type REGISTER_R = crate::FieldReader; -#[doc = "Field `Register` writer - "] -pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; -impl R { - #[doc = "Bits 0:31"] - #[inline(always)] - pub fn register(&self) -> REGISTER_R { - REGISTER_R::new(self.bits) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WDT_RST") - .field("register", &format_args!("{}", self.register().bits())) - .finish() - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -impl W { - #[doc = "Bits 0:31"] - #[inline(always)] - #[must_use] - pub fn register(&mut self) -> REGISTER_W { - REGISTER_W::new(self, 0) - } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = "Watchdog reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_rst::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct WDT_RST_SPEC; -impl crate::RegisterSpec for WDT_RST_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`wdt_rst::R`](R) reader structure"] -impl crate::Readable for WDT_RST_SPEC {} -#[doc = "`write(|w| ..)` method takes [`wdt_rst::W`](W) writer structure"] -impl crate::Writable for WDT_RST_SPEC { - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; -} -#[doc = "`reset()` method sets WDT_RST to value 0"] -impl crate::Resettable for WDT_RST_SPEC { - const RESET_VALUE: Self::Ux = 0; -} diff --git a/esp8266/svd/esp8266.base.svd b/esp8266/svd/esp8266.base.svd deleted file mode 100644 index ea9df2d1e2..0000000000 --- a/esp8266/svd/esp8266.base.svd +++ /dev/null @@ -1,6446 +0,0 @@ - - - ESP8266 - 1.0 - ESP8266 - 8 - 32 - - Xtensa LX106 - 1 - little - false - true - 3 - false - - - - DPORT - 0x3ff00000 - - 0 - 0x00000040 - registers - - - - EDGE_INT_ENABLE - 0x4 - EDGE_INT_ENABLE - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - DPORT_CTL - 0x14 - DPORT_CTL - 32 - 0x00000000 - - - DPORT_CTL_DOUBLE_CLK - 0 - 1 - read-write - - - - - - - EFUSE - 0x3ff00050 - - 0 - 0x00000080 - registers - - - - EFUSE_DATA0 - 0x0 - EFUSE_DATA0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - EFUSE_DATA1 - 0x4 - EFUSE_DATA1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - EFUSE_DATA2 - 0x8 - EFUSE_DATA2 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - EFUSE_DATA3 - 0xc - EFUSE_DATA3 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - - - GPIO - 0x60000300 - - 0 - 0x000003a0 - registers - - - - GPIO_OUT - 0x0 - BT-Coexist Selection register - 32 - 0x00000000 - - - GPIO_BT_SEL - BT-Coexist Selection register - 16 - 16 - read-write - - - GPIO_OUT_DATA - The output value when the GPIO pin is set as output. - 0 - 16 - read-write - - - - - GPIO_OUT_W1TS - 0x4 - GPIO_OUT_W1TS - 32 - 0x00000000 - - - GPIO_OUT_DATA_W1TS - Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA - 0 - 16 - write-only - - - - - GPIO_OUT_W1TC - 0x8 - GPIO_OUT_W1TC - 32 - 0x00000000 - - - GPIO_OUT_DATA_W1TC - Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA - 0 - 16 - write-only - - - - - GPIO_ENABLE - 0xc - GPIO_ENABLE - 32 - 0x00000000 - - - GPIO_SDIO_SEL - SDIO-dis selection register - 16 - 6 - read-write - - - GPIO_ENABLE_DATA - The output enable register. - 0 - 16 - read-write - - - - - GPIO_ENABLE_W1TS - 0x10 - GPIO_ENABLE_W1TS - 32 - 0x00000000 - - - GPIO_ENABLE_DATA_W1TS - Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA - 0 - 16 - write-only - - - - - GPIO_ENABLE_W1TC - 0x14 - GPIO_ENABLE_W1TC - 32 - 0x00000000 - - - GPIO_ENABLE_DATA_W1TC - Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA - 0 - 16 - write-only - - - - - GPIO_IN - 0x18 - The values of the strapping pins. - 32 - 0x00000000 - - - GPIO_STRAPPING - The values of the strapping pins. - 16 - 16 - read-write - - - GPIO_IN_DATA - The values of the GPIO pins when the GPIO pin is set as input. - 0 - 16 - read-write - - - - - GPIO_STATUS - 0x1c - GPIO_STATUS - 32 - 0x00000000 - - - GPIO_STATUS_INTERRUPT - Interrupt enable register. - 0 - 16 - read-write - - - - - GPIO_STATUS_W1TS - 0x20 - GPIO_STATUS_W1TS - 32 - 0x00000000 - - - GPIO_STATUS_INTERRUPT_W1TS - Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT - 0 - 16 - write-only - - - - - GPIO_STATUS_W1TC - 0x24 - GPIO_STATUS_W1TC - 32 - 0x00000000 - - - GPIO_STATUS_INTERRUPT_W1TC - Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT - 0 - 16 - write-only - - - - - GPIO_PIN0 - 0x28 - GPIO_PIN0 - 32 - 0x00000000 - - - GPIO_PIN0_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN0_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN0_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN0_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN1 - 0x2c - GPIO_PIN1 - 32 - 0x00000000 - - - GPIO_PIN1_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN1_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN1_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN1_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN2 - 0x30 - GPIO_PIN2 - 32 - 0x00000000 - - - GPIO_PIN2_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN2_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN2_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN2_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN3 - 0x34 - GPIO_PIN3 - 32 - 0x00000000 - - - GPIO_PIN3_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN3_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN3_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN3_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN4 - 0x38 - GPIO_PIN4 - 32 - 0x00000000 - - - GPIO_PIN4_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN4_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN4_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN4_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN5 - 0x3c - GPIO_PIN5 - 32 - 0x00000000 - - - GPIO_PIN5_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN5_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN5_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN5_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN6 - 0x40 - GPIO_PIN6 - 32 - 0x00000000 - - - GPIO_PIN6_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN6_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN6_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN6_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN7 - 0x44 - GPIO_PIN7 - 32 - 0x00000000 - - - GPIO_PIN7_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN7_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN7_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN7_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN8 - 0x48 - GPIO_PIN8 - 32 - 0x00000000 - - - GPIO_PIN8_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN8_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN8_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN8_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN9 - 0x4c - GPIO_PIN9 - 32 - 0x00000000 - - - GPIO_PIN9_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN9_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN9_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN9_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN10 - 0x50 - GPIO_PIN10 - 32 - 0x00000000 - - - GPIO_PIN10_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN10_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN10_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN10_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN11 - 0x54 - GPIO_PIN11 - 32 - 0x00000000 - - - GPIO_PIN11_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN11_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN11_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN11_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN12 - 0x58 - GPIO_PIN12 - 32 - 0x00000000 - - - GPIO_PIN12_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN12_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN12_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN12_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN13 - 0x5c - GPIO_PIN13 - 32 - 0x00000000 - - - GPIO_PIN13_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN13_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN13_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN13_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN14 - 0x60 - GPIO_PIN14 - 32 - 0x00000000 - - - GPIO_PIN14_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN14_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN14_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN14_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_PIN15 - 0x64 - GPIO_PIN15 - 32 - 0x00000000 - - - GPIO_PIN15_WAKEUP_ENABLE - 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 - 10 - 1 - read-write - - - GPIO_PIN15_INT_TYPE - 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level - 7 - 3 - read-write - - - GPIO_PIN15_DRIVER - 1: open drain; 0: normal - 2 - 1 - read-write - - - GPIO_PIN15_SOURCE - 1: sigma-delta; 0: GPIO_DATA - 0 - 1 - read-write - - - - - GPIO_SIGMA_DELTA - 0x68 - GPIO_SIGMA_DELTA - 32 - 0x00000000 - - - SIGMA_DELTA_ENABLE - 1: enable sigma-delta; 0: disable - 16 - 1 - read-write - - - SIGMA_DELTA_PRESCALAR - Clock pre-divider for sigma-delta. - 8 - 8 - read-write - - - SIGMA_DELTA_TARGET - target level of the sigma-delta. It is a signed byte. - 0 - 8 - read-write - - - - - GPIO_RTC_CALIB_SYNC - 0x6c - Positvie edge of this bit will trigger the RTC-clock-calibration process. - 32 - 0x00000000 - - - RTC_CALIB_START - Positvie edge of this bit will trigger the RTC-clock-calibration process. - 31 - 1 - read-write - - - RTC_PERIOD_NUM - The cycle number of RTC-clock during RTC-clock-calibration - 0 - 10 - read-write - - - - - GPIO_RTC_CALIB_VALUE - 0x70 - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 32 - 0x00000000 - - - RTC_CALIB_RDY - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 31 - 1 - read-write - - - RTC_CALIB_RDY_REAL - 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done - 30 - 1 - read-write - - - RTC_CALIB_VALUE - The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock - 0 - 20 - read-write - - - - - - - I2S - 0x60000e00 - - 0 - 0x00000160 - registers - - - - I2STXFIFO - 0x0 - I2STXFIFO - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - I2SRXFIFO - 0x4 - I2SRXFIFO - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - I2SCONF - 0x8 - I2SCONF - 32 - 0x00000000 - - - I2S_BCK_DIV_NUM - 22 - 6 - read-write - - - I2S_CLKM_DIV_NUM - 16 - 6 - read-write - - - I2S_BITS_MOD - 12 - 4 - read-write - - - I2S_RECE_MSB_SHIFT - 11 - 1 - read-write - - - I2S_TRANS_MSB_SHIFT - 10 - 1 - read-write - - - I2S_I2S_RX_START - 9 - 1 - read-write - - - I2S_I2S_TX_START - 8 - 1 - read-write - - - I2S_MSB_RIGHT - 7 - 1 - read-write - - - I2S_RIGHT_FIRST - 6 - 1 - read-write - - - I2S_RECE_SLAVE_MOD - 5 - 1 - read-write - - - I2S_TRANS_SLAVE_MOD - 4 - 1 - read-write - - - I2S_I2S_RX_FIFO_RESET - 3 - 1 - read-write - - - I2S_I2S_TX_FIFO_RESET - 2 - 1 - read-write - - - I2S_I2S_RX_RESET - 1 - 1 - read-write - - - I2S_I2S_TX_RESET - 0 - 1 - read-write - - - - - I2SINT_RAW - 0xc - I2SINT_RAW - 32 - 0x00000000 - - - I2S_I2S_TX_REMPTY_INT_RAW - 5 - 1 - read-write - - - I2S_I2S_TX_WFULL_INT_RAW - 4 - 1 - read-write - - - I2S_I2S_RX_REMPTY_INT_RAW - 3 - 1 - read-write - - - I2S_I2S_RX_WFULL_INT_RAW - 2 - 1 - read-write - - - I2S_I2S_TX_PUT_DATA_INT_RAW - 1 - 1 - read-write - - - I2S_I2S_RX_TAKE_DATA_INT_RAW - 0 - 1 - read-write - - - - - I2SINT_ST - 0x10 - I2SINT_ST - 32 - 0x00000000 - - - I2S_I2S_TX_REMPTY_INT_ST - 5 - 1 - read-write - - - I2S_I2S_TX_WFULL_INT_ST - 4 - 1 - read-write - - - I2S_I2S_RX_REMPTY_INT_ST - 3 - 1 - read-write - - - I2S_I2S_RX_WFULL_INT_ST - 2 - 1 - read-write - - - I2S_I2S_TX_PUT_DATA_INT_ST - 1 - 1 - read-write - - - I2S_I2S_RX_TAKE_DATA_INT_ST - 0 - 1 - read-write - - - - - I2SINT_ENA - 0x14 - I2SINT_ENA - 32 - 0x00000000 - - - I2S_I2S_TX_REMPTY_INT_ENA - 5 - 1 - read-write - - - I2S_I2S_TX_WFULL_INT_ENA - 4 - 1 - read-write - - - I2S_I2S_RX_REMPTY_INT_ENA - 3 - 1 - read-write - - - I2S_I2S_RX_WFULL_INT_ENA - 2 - 1 - read-write - - - I2S_I2S_TX_PUT_DATA_INT_ENA - 1 - 1 - read-write - - - I2S_I2S_RX_TAKE_DATA_INT_ENA - 0 - 1 - read-write - - - - - I2SINT_CLR - 0x18 - I2SINT_CLR - 32 - 0x00000000 - - - I2S_I2S_TX_REMPTY_INT_CLR - 5 - 1 - read-write - - - I2S_I2S_TX_WFULL_INT_CLR - 4 - 1 - read-write - - - I2S_I2S_RX_REMPTY_INT_CLR - 3 - 1 - read-write - - - I2S_I2S_RX_WFULL_INT_CLR - 2 - 1 - read-write - - - I2S_I2S_PUT_DATA_INT_CLR - 1 - 1 - read-write - - - I2S_I2S_TAKE_DATA_INT_CLR - 0 - 1 - read-write - - - - - I2STIMING - 0x1c - I2STIMING - 32 - 0x00000000 - - - I2S_TRANS_BCK_IN_INV - 22 - 1 - read-write - - - I2S_RECE_DSYNC_SW - 21 - 1 - read-write - - - I2S_TRANS_DSYNC_SW - 20 - 1 - read-write - - - I2S_RECE_BCK_OUT_DELAY - 18 - 2 - read-write - - - I2S_RECE_WS_OUT_DELAY - 16 - 2 - read-write - - - I2S_TRANS_SD_OUT_DELAY - 14 - 2 - read-write - - - I2S_TRANS_WS_OUT_DELAY - 12 - 2 - read-write - - - I2S_TRANS_BCK_OUT_DELAY - 10 - 2 - read-write - - - I2S_RECE_SD_IN_DELAY - 8 - 2 - read-write - - - I2S_RECE_WS_IN_DELAY - 6 - 2 - read-write - - - I2S_RECE_BCK_IN_DELAY - 4 - 2 - read-write - - - I2S_TRANS_WS_IN_DELAY - 2 - 2 - read-write - - - I2S_TRANS_BCK_IN_DELAY - 0 - 2 - read-write - - - - - I2S_FIFO_CONF - 0x20 - I2S_FIFO_CONF - 32 - 0x00000000 - - - I2S_I2S_RX_FIFO_MOD - 16 - 3 - read-write - - - I2S_I2S_TX_FIFO_MOD - 13 - 3 - read-write - - - I2S_I2S_DSCR_EN - 12 - 1 - read-write - - - I2S_I2S_TX_DATA_NUM - 6 - 6 - read-write - - - I2S_I2S_RX_DATA_NUM - 0 - 6 - read-write - - - - - I2SRXEOF_NUM - 0x24 - I2SRXEOF_NUM - 32 - 0x00000000 - - - I2S_I2S_RX_EOF_NUM - 0 - 32 - read-write - - - - - I2SCONF_SIGLE_DATA - 0x28 - I2SCONF_SIGLE_DATA - 32 - 0x00000000 - - - I2S_I2S_SIGLE_DATA - 0 - 32 - read-write - - - - - - - IO_MUX - 0x60000800 - - 0 - 0x00000220 - registers - - - - IO_MUX_CONF - 0x0 - IO_MUX_CONF - 32 - 0x00000000 - - - SPI0_CLK_EQU_SYS_CLK - 8 - 1 - read-write - - - SPI1_CLK_EQU_SYS_CLK - 9 - 1 - read-write - - - - - IO_MUX_MTDI - 0x4 - IO_MUX_MTDI - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_MTCK - 0x8 - IO_MUX_MTCK - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_MTMS - 0xc - IO_MUX_MTMS - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_MTDO - 0x10 - IO_MUX_MTDO - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_U0RXD - 0x14 - IO_MUX_U0RXD - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_U0TXD - 0x18 - IO_MUX_U0TXD - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_CLK - 0x1c - IO_MUX_SD_CLK - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_DATA0 - 0x20 - IO_MUX_SD_DATA0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_DATA1 - 0x24 - IO_MUX_SD_DATA1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_DATA2 - 0x28 - IO_MUX_SD_DATA2 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_DATA3 - 0x2c - IO_MUX_SD_DATA3 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_SD_CMD - 0x30 - IO_MUX_SD_CMD - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_GPIO0 - 0x34 - IO_MUX_GPIO0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_GPIO2 - 0x38 - IO_MUX_GPIO2 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_GPIO4 - 0x3c - IO_MUX_GPIO4 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - IO_MUX_GPIO5 - 0x40 - IO_MUX_GPIO5 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - - - RTC - 0x60000700 - - 0 - 0x00000040 - registers - - - - RTC_STORE0 - 0x30 - RTC_STORE0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - RTC_STATE1 - 0x14 - RTC_STATE1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - - - SLC - 0x60000b00 - - 0 - 0x00000400 - registers - - - - SLC_CONF0 - 0x0 - SLC_CONF0 - 32 - 0x00000000 - - - SLC_MODE - 12 - 2 - read-write - - - SLC_DATA_BURST_EN - 9 - 1 - read-write - - - SLC_DSCR_BURST_EN - 8 - 1 - read-write - - - SLC_RX_NO_RESTART_CLR - 7 - 1 - read-write - - - SLC_RX_AUTO_WRBACK - 6 - 1 - read-write - - - SLC_RX_LOOP_TEST - 5 - 1 - read-write - - - SLC_TX_LOOP_TEST - 4 - 1 - read-write - - - SLC_AHBM_RST - 3 - 1 - read-write - - - SLC_AHBM_FIFO_RST - 2 - 1 - read-write - - - SLC_RXLINK_RST - 1 - 1 - read-write - - - SLC_TXLINK_RST - 0 - 1 - read-write - - - - - SLC_INT_RAW - 0x4 - SLC_INT_RAW - 32 - 0x00000000 - - - SLC_TX_DSCR_EMPTY_INT_RAW - 21 - 1 - read-write - - - SLC_RX_DSCR_ERR_INT_RAW - 20 - 1 - read-write - - - SLC_TX_DSCR_ERR_INT_RAW - 19 - 1 - read-write - - - SLC_TOHOST_INT_RAW - 18 - 1 - read-write - - - SLC_RX_EOF_INT_RAW - 17 - 1 - read-write - - - SLC_RX_DONE_INT_RAW - 16 - 1 - read-write - - - SLC_TX_EOF_INT_RAW - 15 - 1 - read-write - - - SLC_TX_DONE_INT_RAW - 14 - 1 - read-write - - - SLC_TOKEN1_1TO0_INT_RAW - 13 - 1 - read-write - - - SLC_TOKEN0_1TO0_INT_RAW - 12 - 1 - read-write - - - SLC_TX_OVF_INT_RAW - 11 - 1 - read-write - - - SLC_RX_UDF_INT_RAW - 10 - 1 - read-write - - - SLC_TX_START_INT_RAW - 9 - 1 - read-write - - - SLC_RX_START_INT_RAW - 8 - 1 - read-write - - - SLC_FRHOST_BIT7_INT_RAW - 7 - 1 - read-write - - - SLC_FRHOST_BIT6_INT_RAW - 6 - 1 - read-write - - - SLC_FRHOST_BIT5_INT_RAW - 5 - 1 - read-write - - - SLC_FRHOST_BIT4_INT_RAW - 4 - 1 - read-write - - - SLC_FRHOST_BIT3_INT_RAW - 3 - 1 - read-write - - - SLC_FRHOST_BIT2_INT_RAW - 2 - 1 - read-write - - - SLC_FRHOST_BIT1_INT_RAW - 1 - 1 - read-write - - - SLC_FRHOST_BIT0_INT_RAW - 0 - 1 - read-write - - - - - SLC_INT_STATUS - 0x8 - SLC_INT_STATUS - 32 - 0x00000000 - - - SLC_TX_DSCR_EMPTY_INT_ST - 21 - 1 - read-write - - - SLC_RX_DSCR_ERR_INT_ST - 20 - 1 - read-write - - - SLC_TX_DSCR_ERR_INT_ST - 19 - 1 - read-write - - - SLC_TOHOST_INT_ST - 18 - 1 - read-write - - - SLC_RX_EOF_INT_ST - 17 - 1 - read-write - - - SLC_RX_DONE_INT_ST - 16 - 1 - read-write - - - SLC_TX_EOF_INT_ST - 15 - 1 - read-write - - - SLC_TX_DONE_INT_ST - 14 - 1 - read-write - - - SLC_TOKEN1_1TO0_INT_ST - 13 - 1 - read-write - - - SLC_TOKEN0_1TO0_INT_ST - 12 - 1 - read-write - - - SLC_TX_OVF_INT_ST - 11 - 1 - read-write - - - SLC_RX_UDF_INT_ST - 10 - 1 - read-write - - - SLC_TX_START_INT_ST - 9 - 1 - read-write - - - SLC_RX_START_INT_ST - 8 - 1 - read-write - - - SLC_FRHOST_BIT7_INT_ST - 7 - 1 - read-write - - - SLC_FRHOST_BIT6_INT_ST - 6 - 1 - read-write - - - SLC_FRHOST_BIT5_INT_ST - 5 - 1 - read-write - - - SLC_FRHOST_BIT4_INT_ST - 4 - 1 - read-write - - - SLC_FRHOST_BIT3_INT_ST - 3 - 1 - read-write - - - SLC_FRHOST_BIT2_INT_ST - 2 - 1 - read-write - - - SLC_FRHOST_BIT1_INT_ST - 1 - 1 - read-write - - - SLC_FRHOST_BIT0_INT_ST - 0 - 1 - read-write - - - - - SLC_INT_ENA - 0xc - SLC_INT_ENA - 32 - 0x00000000 - - - SLC_TX_DSCR_EMPTY_INT_ENA - 21 - 1 - read-write - - - SLC_RX_DSCR_ERR_INT_ENA - 20 - 1 - read-write - - - SLC_TX_DSCR_ERR_INT_ENA - 19 - 1 - read-write - - - SLC_TOHOST_INT_ENA - 18 - 1 - read-write - - - SLC_RX_EOF_INT_ENA - 17 - 1 - read-write - - - SLC_RX_DONE_INT_ENA - 16 - 1 - read-write - - - SLC_TX_EOF_INT_ENA - 15 - 1 - read-write - - - SLC_TX_DONE_INT_ENA - 14 - 1 - read-write - - - SLC_TOKEN1_1TO0_INT_ENA - 13 - 1 - read-write - - - SLC_TOKEN0_1TO0_INT_ENA - 12 - 1 - read-write - - - SLC_TX_OVF_INT_ENA - 11 - 1 - read-write - - - SLC_RX_UDF_INT_ENA - 10 - 1 - read-write - - - SLC_TX_START_INT_ENA - 9 - 1 - read-write - - - SLC_RX_START_INT_ENA - 8 - 1 - read-write - - - SLC_FRHOST_BIT7_INT_ENA - 7 - 1 - read-write - - - SLC_FRHOST_BIT6_INT_ENA - 6 - 1 - read-write - - - SLC_FRHOST_BIT5_INT_ENA - 5 - 1 - read-write - - - SLC_FRHOST_BIT4_INT_ENA - 4 - 1 - read-write - - - SLC_FRHOST_BIT3_INT_ENA - 3 - 1 - read-write - - - SLC_FRHOST_BIT2_INT_ENA - 2 - 1 - read-write - - - SLC_FRHOST_BIT1_INT_ENA - 1 - 1 - read-write - - - SLC_FRHOST_BIT0_INT_ENA - 0 - 1 - read-write - - - - - SLC_INT_CLR - 0x10 - SLC_INT_CLR - 32 - 0x00000000 - - - SLC_TX_DSCR_EMPTY_INT_CLR - 21 - 1 - read-write - - - SLC_RX_DSCR_ERR_INT_CLR - 20 - 1 - read-write - - - SLC_TX_DSCR_ERR_INT_CLR - 19 - 1 - read-write - - - SLC_TOHOST_INT_CLR - 18 - 1 - read-write - - - SLC_RX_EOF_INT_CLR - 17 - 1 - read-write - - - SLC_RX_DONE_INT_CLR - 16 - 1 - read-write - - - SLC_TX_EOF_INT_CLR - 15 - 1 - read-write - - - SLC_TX_DONE_INT_CLR - 14 - 1 - read-write - - - SLC_TOKEN1_1TO0_INT_CLR - 13 - 1 - read-write - - - SLC_TOKEN0_1TO0_INT_CLR - 12 - 1 - read-write - - - SLC_TX_OVF_INT_CLR - 11 - 1 - read-write - - - SLC_RX_UDF_INT_CLR - 10 - 1 - read-write - - - SLC_TX_START_INT_CLR - 9 - 1 - read-write - - - SLC_RX_START_INT_CLR - 8 - 1 - read-write - - - SLC_FRHOST_BIT7_INT_CLR - 7 - 1 - read-write - - - SLC_FRHOST_BIT6_INT_CLR - 6 - 1 - read-write - - - SLC_FRHOST_BIT5_INT_CLR - 5 - 1 - read-write - - - SLC_FRHOST_BIT4_INT_CLR - 4 - 1 - read-write - - - SLC_FRHOST_BIT3_INT_CLR - 3 - 1 - read-write - - - SLC_FRHOST_BIT2_INT_CLR - 2 - 1 - read-write - - - SLC_FRHOST_BIT1_INT_CLR - 1 - 1 - read-write - - - SLC_FRHOST_BIT0_INT_CLR - 0 - 1 - read-write - - - - - SLC_RX_STATUS - 0x14 - SLC_RX_STATUS - 32 - 0x00000000 - - - SLC_RX_EMPTY - 1 - 1 - read-write - - - SLC_RX_FULL - 0 - 1 - read-write - - - - - SLC_RX_FIFO_PUSH - 0x18 - SLC_RX_FIFO_PUSH - 32 - 0x00000000 - - - SLC_RXFIFO_PUSH - 16 - 1 - read-write - - - SLC_RXFIFO_WDATA - 0 - 9 - read-write - - - - - SLC_TX_STATUS - 0x1c - SLC_TX_STATUS - 32 - 0x00000000 - - - SLC_TX_EMPTY - 1 - 1 - read-write - - - SLC_TX_FULL - 0 - 1 - read-write - - - - - SLC_TX_FIFO_POP - 0x20 - SLC_TX_FIFO_POP - 32 - 0x00000000 - - - SLC_TXFIFO_POP - 16 - 1 - read-write - - - SLC_TXFIFO_RDATA - 0 - 11 - read-write - - - - - SLC_RX_LINK - 0x24 - SLC_RX_LINK - 32 - 0x00000000 - - - SLC_RXLINK_PARK - 31 - 1 - read-write - - - SLC_RXLINK_RESTART - 30 - 1 - read-write - - - SLC_RXLINK_START - 29 - 1 - read-write - - - SLC_RXLINK_STOP - 28 - 1 - read-write - - - SLC_RXLINK_ADDR - 0 - 20 - read-write - - - - - SLC_TX_LINK - 0x28 - SLC_TX_LINK - 32 - 0x00000000 - - - SLC_TXLINK_PARK - 31 - 1 - read-write - - - SLC_TXLINK_RESTART - 30 - 1 - read-write - - - SLC_TXLINK_START - 29 - 1 - read-write - - - SLC_TXLINK_STOP - 28 - 1 - read-write - - - SLC_TXLINK_ADDR - 0 - 20 - read-write - - - - - SLC_INTVEC_TOHOST - 0x2c - SLC_INTVEC_TOHOST - 32 - 0x00000000 - - - SLC_TOHOST_INTVEC - 0 - 8 - read-write - - - - - SLC_TOKEN0 - 0x30 - SLC_TOKEN0 - 32 - 0x00000000 - - - SLC_TOKEN0 - 16 - 12 - read-write - - - SLC_TOKEN0_LOCAL_INC_MORE - 14 - 1 - read-write - - - SLC_TOKEN0_LOCAL_INC - 13 - 1 - read-write - - - SLC_TOKEN0_LOCAL_WR - 12 - 1 - read-write - - - SLC_TOKEN0_LOCAL_WDATA - 0 - 12 - read-write - - - - - SLC_TOKEN1 - 0x34 - SLC_TOKEN1 - 32 - 0x00000000 - - - SLC_TOKEN1 - 16 - 12 - read-write - - - SLC_TOKEN1_LOCAL_INC_MORE - 14 - 1 - read-write - - - SLC_TOKEN1_LOCAL_INC - 13 - 1 - read-write - - - SLC_TOKEN1_LOCAL_WR - 12 - 1 - read-write - - - SLC_TOKEN1_LOCAL_WDATA - 0 - 12 - read-write - - - - - SLC_CONF1 - 0x38 - SLC_CONF1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_STATE0 - 0x3c - SLC_STATE0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_STATE1 - 0x40 - SLC_STATE1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_BRIDGE_CONF - 0x44 - SLC_BRIDGE_CONF - 32 - 0x00000000 - - - SLC_TX_PUSH_IDLE_NUM - 16 - 16 - read-write - - - SLC_TX_DUMMY_MODE - 12 - 1 - read-write - - - SLC_FIFO_MAP_ENA - 8 - 4 - read-write - - - SLC_TXEOF_ENA - 0 - 6 - read-write - - - - - SLC_RX_EOF_DES_ADDR - 0x48 - SLC_RX_EOF_DES_ADDR - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_TX_EOF_DES_ADDR - 0x4c - SLC_TX_EOF_DES_ADDR - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_RX_EOF_BFR_DES_ADDR - 0x50 - SLC_RX_EOF_BFR_DES_ADDR - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_AHB_TEST - 0x54 - SLC_AHB_TEST - 32 - 0x00000000 - - - SLC_AHB_TESTADDR - 4 - 2 - read-write - - - SLC_AHB_TESTMODE - 0 - 3 - read-write - - - - - SLC_SDIO_ST - 0x58 - SLC_SDIO_ST - 32 - 0x00000000 - - - SLC_BUS_ST - 12 - 3 - read-write - - - SLC_SDIO_WAKEUP - 8 - 1 - read-write - - - SLC_FUNC_ST - 4 - 4 - read-write - - - SLC_CMD_ST - 0 - 3 - read-write - - - - - SLC_RX_DSCR_CONF - 0x5c - SLC_RX_DSCR_CONF - 32 - 0x00000000 - - - SLC_INFOR_NO_REPLACE - 9 - 1 - read-write - - - SLC_TOKEN_NO_REPLACE - 8 - 1 - read-write - - - - - SLC_TXLINK_DSCR - 0x60 - SLC_TXLINK_DSCR - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_TXLINK_DSCR_BF0 - 0x64 - SLC_TXLINK_DSCR_BF0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_TXLINK_DSCR_BF1 - 0x68 - SLC_TXLINK_DSCR_BF1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_RXLINK_DSCR - 0x6c - SLC_RXLINK_DSCR - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_RXLINK_DSCR_BF0 - 0x70 - SLC_RXLINK_DSCR_BF0 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_RXLINK_DSCR_BF1 - 0x74 - SLC_RXLINK_DSCR_BF1 - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_DATE - 0x78 - SLC_DATE - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - SLC_ID - 0x7c - SLC_ID - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - - - SPI0 - 0x60000200 - - 0 - 0x00000400 - registers - - - - SPI_CMD - 0x0 - In the master mode, it is the start bit of a single operation. Self-clear by hardware - 32 - 0x00000000 - - - spi_usr - In the master mode, it is the start bit of a single operation. Self-clear by hardware - 18 - 1 - read-write - - - - - SPI_ADDR - 0x4 - In the master mode, it is the value of address in "address" phase. - 32 - 0x00000000 - - - iodata_start_addr - In the master mode, it is the value of address in "address" phase. - 0 - 32 - read-write - - - - - SPI_CTRL - 0x8 - SPI_CTRL - 32 - 0x00000000 - - - spi_wr_bit_order - In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first - 26 - 1 - read-write - - - spi_rd_bit_order - In "read-data" (MISO) phase, 1: LSB first; 0: MSB first - 25 - 1 - read-write - - - spi_qio_mode - In the read operations, "address" phase and "read-data" phase apply 4 signals - 24 - 1 - read-write - - - spi_dio_mode - In the read operations, "address" phase and "read-data" phase apply 2 signals - 23 - 1 - read-write - - - spi_qout_mode - In the read operations, "read-data" phase apply 4 signals - 20 - 1 - read-write - - - spi_dout_mode - In the read operations, "read-data" phase apply 2 signals - 14 - 1 - read-write - - - spi_fastrd_mode - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode - 13 - 1 - read-write - - - - - SPI_RD_STATUS - 0x10 - In the slave mode, this register are the status register for the master to read out. - 32 - 0x00000000 - - - slv_rd_status - In the slave mode, this register are the status register for the master to read out. - 0 - 32 - read-write - - - - - SPI_CTRL2 - 0x14 - spi_cs signal is delayed by 80MHz clock cycles - 32 - 0x00000000 - - - spi_cs_delay_num - spi_cs signal is delayed by 80MHz clock cycles - 28 - 4 - read-write - - - spi_cs_delay_mode - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 26 - 2 - read-write - - - spi_mosi_delay_num - MOSI signals are delayed by 80MHz clock cycles - 23 - 3 - read-write - - - spi_mosi_delay_mode - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 21 - 2 - read-write - - - spi_miso_delay_num - MISO signals are delayed by 80MHz clock cycles - 18 - 3 - read-write - - - spi_miso_delay_mode - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 16 - 2 - read-write - - - - - SPI_CLOCK - 0x18 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. - 32 - 0x00000000 - - - spi_clk_equ_sysclk - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. - 31 - 1 - read-write - - - spi_clkdiv_pre - In the master mode, it is pre-divider of spi_clk. - 18 - 13 - read-write - - - spi_clkcnt_N - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) - 12 - 6 - read-write - - - spi_clkcnt_H - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0. - 6 - 6 - read-write - - - spi_clkcnt_L - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0. - 0 - 6 - read-write - - - - - SPI_USER - 0x1c - This bit enable the "command" phase of an operation. - 32 - 0x00000000 - - - spi_usr_command - This bit enable the "command" phase of an operation. - 31 - 1 - read-write - - - spi_usr_addr - This bit enable the "address" phase of an operation. - 30 - 1 - read-write - - - spi_usr_dummy - This bit enable the "dummy" phase of an operation. - 29 - 1 - read-write - - - spi_usr_miso - This bit enable the "read-data" phase of an operation. - 28 - 1 - read-write - - - spi_usr_mosi - This bit enable the "write-data" phase of an operation. - 27 - 1 - read-write - - - reg_usr_mosi_highpart - 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 - 25 - 1 - read-write - - - reg_usr_miso_highpart - 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 - 24 - 1 - read-write - - - spi_sio - 1: mosi and miso signals share the same pin - 16 - 1 - read-write - - - spi_fwrite_qio - In the write operations, "address" phase and "read-data" phase apply 4 signals - 15 - 1 - read-write - - - spi_fwrite_dio - In the write operations, "address" phase and "read-data" phase apply 2 signals - 14 - 1 - read-write - - - spi_fwrite_quad - In the write operations, "read-data" phase apply 4 signals - 13 - 1 - read-write - - - spi_fwrite_dual - In the write operations, "read-data" phase apply 2 signals - 12 - 1 - read-write - - - spi_wr_byte_order - In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian - 11 - 1 - read-write - - - spi_rd_byte_order - In "read-data" (MISO) phase, 1: little-endian; 0: big_endian - 10 - 1 - read-write - - - spi_ck_i_edge - In the slave mode, 1: rising-edge; 0: falling-edge - 6 - 1 - read-write - - - - - SPI_USER1 - 0x20 - The length in bits of "address" phase. The register value shall be (bit_num-1) - 32 - 0x00000000 - - - reg_usr_addr_bitlen - The length in bits of "address" phase. The register value shall be (bit_num-1) - 26 - 6 - read-write - - - reg_usr_mosi_bitlen - The length in bits of "write-data" phase. The register value shall be (bit_num-1) - 17 - 9 - read-write - - - reg_usr_miso_bitlen - The length in bits of "read-data" phase. The register value shall be (bit_num-1) - 8 - 9 - read-write - - - reg_usr_dummy_cyclelen - The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1) - 0 - 8 - read-write - - - - - SPI_USER2 - 0x24 - The length in bits of "command" phase. The register value shall be (bit_num-1) - 32 - 0x00000000 - - - reg_usr_command_bitlen - The length in bits of "command" phase. The register value shall be (bit_num-1) - 28 - 4 - read-write - - - reg_usr_command_value - The value of "command" phase - 0 - 16 - read-write - - - - - SPI_WR_STATUS - 0x28 - In the slave mode, this register are the status register for the master to write into. - 32 - 0x00000000 - - - slv_wr_status - In the slave mode, this register are the status register for the master to write into. - 0 - 32 - read-write - - - - - SPI_PIN - 0x2c - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin - 32 - 0x00000000 - - - spi_cs2_dis - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin - 2 - 1 - read-write - - - spi_cs1_dis - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin - 1 - 1 - read-write - - - spi_cs0_dis - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin - 0 - 1 - read-write - - - - - SPI_SLAVE - 0x30 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware. - 32 - 0x00000000 - - - spi_sync_reset - It is the synchronous reset signal of the module. This bit is self-cleared by hardware. - 31 - 1 - read-write - - - spi_slave_mode - 1: slave mode, 0: master mode. - 30 - 1 - read-write - - - slv_cmd_define - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". - 27 - 1 - read-write - - - spi_trans_cnt - The operations counter in both the master mode and the slave mode. - 23 - 4 - read-only - - - spi_int_en - Interrupt enable bits for the below 5 sources - 5 - 5 - read-write - - - spi_trans_done - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode. - 4 - 1 - read-write - - - slv_wr_sta_done - The interrupt raw bit for the completement of "write-status" operation in the slave mode. - 3 - 1 - read-write - - - slv_rd_sta_done - The interrupt raw bit for the completement of "read-status" operation in the slave mode. - 2 - 1 - read-write - - - slv_wr_buf_done - The interrupt raw bit for the completement of "write-buffer" operation in the slave mode. - 1 - 1 - read-write - - - slv_rd_buf_done - The interrupt raw bit for the completement of "read-buffer" operation in the slave mode. - 0 - 1 - read-write - - - - - SPI_SLAVE1 - 0x34 - In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) - 32 - 0x00000000 - - - slv_status_bitlen - In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) - 27 - 5 - read-write - - - slv_buf_bitlen - In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1) - 16 - 9 - read-write - - - slv_rd_addr_bitlen - In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1) - 10 - 6 - read-write - - - slv_wr_addr_bitlen - In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1) - 4 - 6 - read-write - - - slv_wrsta_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations. - 3 - 1 - read-write - - - slv_rdsta_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations. - 2 - 1 - read-write - - - slv_wrbuf_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations. - 1 - 1 - read-write - - - slv_rdbuf_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations. - 0 - 1 - read-write - - - - - SPI_SLAVE2 - 0x38 - In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) - 32 - 0x00000000 - - - slv_wrbuf_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) - 24 - 8 - read-write - - - slv_rdbuf_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1) - 16 - 8 - read-write - - - slv_wrsta_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1) - 8 - 8 - read-write - - - slv_rdsta_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1) - 0 - 8 - read-write - - - - - SPI_SLAVE3 - 0x3c - In slave mode, it is the value of "write-status" command - 32 - 0x00000000 - - - slv_wrsta_cmd_value - In slave mode, it is the value of "write-status" command - 24 - 8 - read-write - - - slv_rdsta_cmd_value - In slave mode, it is the value of "read-status" command - 16 - 8 - read-write - - - slv_wrbuf_cmd_value - In slave mode, it is the value of "write-buffer" command - 8 - 8 - read-write - - - slv_rdbuf_cmd_value - In slave mode, it is the value of "read-buffer" command - 0 - 8 - read-write - - - - - SPI_EXT3 - 0xfc - This register is for two SPI masters to share the same cs, clock and data signals. - 32 - 0x00000000 - - - reg_int_hold_ena - This register is for two SPI masters to share the same cs, clock and data signals. - 0 - 2 - read-write - - - - - SPI_W0 - 0x40 - the data inside the buffer of the SPI module, word 0 - 32 - 0x00000000 - - - spi_w0 - the data inside the buffer of the SPI module, word 0 - 0 - 32 - read-write - - - - - SPI_W1 - 0x44 - the data inside the buffer of the SPI module, word 1 - 32 - 0x00000000 - - - spi_w1 - the data inside the buffer of the SPI module, word 1 - 0 - 32 - read-write - - - - - SPI_W2 - 0x48 - the data inside the buffer of the SPI module, word 2 - 32 - 0x00000000 - - - spi_w2 - the data inside the buffer of the SPI module, word 2 - 0 - 32 - read-write - - - - - SPI_W3 - 0x4c - the data inside the buffer of the SPI module, word 3 - 32 - 0x00000000 - - - spi_w3 - the data inside the buffer of the SPI module, word 3 - 0 - 32 - read-write - - - - - SPI_W4 - 0x50 - the data inside the buffer of the SPI module, word 4 - 32 - 0x00000000 - - - spi_w4 - the data inside the buffer of the SPI module, word 4 - 0 - 32 - read-write - - - - - SPI_W5 - 0x54 - the data inside the buffer of the SPI module, word 5 - 32 - 0x00000000 - - - spi_w5 - the data inside the buffer of the SPI module, word 5 - 0 - 32 - read-write - - - - - SPI_W6 - 0x58 - the data inside the buffer of the SPI module, word 6 - 32 - 0x00000000 - - - spi_w6 - the data inside the buffer of the SPI module, word 6 - 0 - 32 - read-write - - - - - SPI_W7 - 0x5c - the data inside the buffer of the SPI module, word 7 - 32 - 0x00000000 - - - spi_w7 - the data inside the buffer of the SPI module, word 7 - 0 - 32 - read-write - - - - - SPI_W8 - 0x60 - the data inside the buffer of the SPI module, word 8 - 32 - 0x00000000 - - - spi_w8 - the data inside the buffer of the SPI module, word 8 - 0 - 32 - read-write - - - - - SPI_W9 - 0x64 - the data inside the buffer of the SPI module, word 9 - 32 - 0x00000000 - - - spi_w9 - the data inside the buffer of the SPI module, word 9 - 0 - 32 - read-write - - - - - SPI_W10 - 0x68 - the data inside the buffer of the SPI module, word 10 - 32 - 0x00000000 - - - spi_w10 - the data inside the buffer of the SPI module, word 10 - 0 - 32 - read-write - - - - - SPI_W11 - 0x6c - the data inside the buffer of the SPI module, word 11 - 32 - 0x00000000 - - - spi_w11 - the data inside the buffer of the SPI module, word 11 - 0 - 32 - read-write - - - - - SPI_W12 - 0x70 - the data inside the buffer of the SPI module, word 12 - 32 - 0x00000000 - - - spi_w12 - the data inside the buffer of the SPI module, word 12 - 0 - 32 - read-write - - - - - SPI_W13 - 0x74 - the data inside the buffer of the SPI module, word 13 - 32 - 0x00000000 - - - spi_w13 - the data inside the buffer of the SPI module, word 13 - 0 - 32 - read-write - - - - - SPI_W14 - 0x78 - the data inside the buffer of the SPI module, word 14 - 32 - 0x00000000 - - - spi_w14 - the data inside the buffer of the SPI module, word 14 - 0 - 32 - read-write - - - - - SPI_W15 - 0x7c - the data inside the buffer of the SPI module, word 15 - 32 - 0x00000000 - - - spi_w15 - the data inside the buffer of the SPI module, word 15 - 0 - 32 - read-write - - - - - - - SPI1 - 0x60000100 - - 0 - 0x00000400 - registers - - - - SPI_CMD - 0x0 - In the master mode, it is the start bit of a single operation. Self-clear by hardware - 32 - 0x00000000 - - - spi_usr - In the master mode, it is the start bit of a single operation. Self-clear by hardware - 18 - 1 - read-write - - - - - SPI_ADDR - 0x4 - In the master mode, it is the value of address in "address" phase. - 32 - 0x00000000 - - - iodata_start_addr - In the master mode, it is the value of address in "address" phase. - 0 - 32 - read-write - - - - - SPI_CTRL - 0x8 - SPI_CTRL - 32 - 0x00000000 - - - spi_wr_bit_order - In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first - 26 - 1 - read-write - - - spi_rd_bit_order - In "read-data" (MISO) phase, 1: LSB first; 0: MSB first - 25 - 1 - read-write - - - spi_qio_mode - In the read operations, "address" phase and "read-data" phase apply 4 signals - 24 - 1 - read-write - - - spi_dio_mode - In the read operations, "address" phase and "read-data" phase apply 2 signals - 23 - 1 - read-write - - - spi_qout_mode - In the read operations, "read-data" phase apply 4 signals - 20 - 1 - read-write - - - spi_dout_mode - In the read operations, "read-data" phase apply 2 signals - 14 - 1 - read-write - - - spi_fastrd_mode - this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode - 13 - 1 - read-write - - - - - SPI_RD_STATUS - 0x10 - In the slave mode, this register are the status register for the master to read out. - 32 - 0x00000000 - - - slv_rd_status - In the slave mode, this register are the status register for the master to read out. - 0 - 32 - read-write - - - - - SPI_CTRL2 - 0x14 - spi_cs signal is delayed by 80MHz clock cycles - 32 - 0x00000000 - - - spi_cs_delay_num - spi_cs signal is delayed by 80MHz clock cycles - 28 - 4 - read-write - - - spi_cs_delay_mode - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 26 - 2 - read-write - - - spi_mosi_delay_num - MOSI signals are delayed by 80MHz clock cycles - 23 - 3 - read-write - - - spi_mosi_delay_mode - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 21 - 2 - read-write - - - spi_miso_delay_num - MISO signals are delayed by 80MHz clock cycles - 18 - 3 - read-write - - - spi_miso_delay_mode - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle - 16 - 2 - read-write - - - - - SPI_CLOCK - 0x18 - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. - 32 - 0x00000000 - - - spi_clk_equ_sysclk - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. - 31 - 1 - read-write - - - spi_clkdiv_pre - In the master mode, it is pre-divider of spi_clk. - 18 - 13 - read-write - - - spi_clkcnt_N - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) - 12 - 6 - read-write - - - spi_clkcnt_H - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0. - 6 - 6 - read-write - - - spi_clkcnt_L - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0. - 0 - 6 - read-write - - - - - SPI_USER - 0x1c - This bit enable the "command" phase of an operation. - 32 - 0x00000000 - - - spi_usr_command - This bit enable the "command" phase of an operation. - 31 - 1 - read-write - - - spi_usr_addr - This bit enable the "address" phase of an operation. - 30 - 1 - read-write - - - spi_usr_dummy - This bit enable the "dummy" phase of an operation. - 29 - 1 - read-write - - - spi_usr_miso - This bit enable the "read-data" phase of an operation. - 28 - 1 - read-write - - - spi_usr_mosi - This bit enable the "write-data" phase of an operation. - 27 - 1 - read-write - - - reg_usr_mosi_highpart - 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 - 25 - 1 - read-write - - - reg_usr_miso_highpart - 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 - 24 - 1 - read-write - - - spi_sio - 1: mosi and miso signals share the same pin - 16 - 1 - read-write - - - spi_fwrite_qio - In the write operations, "address" phase and "read-data" phase apply 4 signals - 15 - 1 - read-write - - - spi_fwrite_dio - In the write operations, "address" phase and "read-data" phase apply 2 signals - 14 - 1 - read-write - - - spi_fwrite_quad - In the write operations, "read-data" phase apply 4 signals - 13 - 1 - read-write - - - spi_fwrite_dual - In the write operations, "read-data" phase apply 2 signals - 12 - 1 - read-write - - - spi_wr_byte_order - In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian - 11 - 1 - read-write - - - spi_rd_byte_order - In "read-data" (MISO) phase, 1: little-endian; 0: big_endian - 10 - 1 - read-write - - - spi_ck_i_edge - In the slave mode, 1: rising-edge; 0: falling-edge - 6 - 1 - read-write - - - - - SPI_USER1 - 0x20 - The length in bits of "address" phase. The register value shall be (bit_num-1) - 32 - 0x00000000 - - - reg_usr_addr_bitlen - The length in bits of "address" phase. The register value shall be (bit_num-1) - 26 - 6 - read-write - - - reg_usr_mosi_bitlen - The length in bits of "write-data" phase. The register value shall be (bit_num-1) - 17 - 9 - read-write - - - reg_usr_miso_bitlen - The length in bits of "read-data" phase. The register value shall be (bit_num-1) - 8 - 9 - read-write - - - reg_usr_dummy_cyclelen - The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1) - 0 - 8 - read-write - - - - - SPI_USER2 - 0x24 - The length in bits of "command" phase. The register value shall be (bit_num-1) - 32 - 0x00000000 - - - reg_usr_command_bitlen - The length in bits of "command" phase. The register value shall be (bit_num-1) - 28 - 4 - read-write - - - reg_usr_command_value - The value of "command" phase - 0 - 16 - read-write - - - - - SPI_WR_STATUS - 0x28 - In the slave mode, this register are the status register for the master to write into. - 32 - 0x00000000 - - - slv_wr_status - In the slave mode, this register are the status register for the master to write into. - 0 - 32 - read-write - - - - - SPI_PIN - 0x2c - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin - 32 - 0x00000000 - - - spi_cs2_dis - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin - 2 - 1 - read-write - - - spi_cs1_dis - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin - 1 - 1 - read-write - - - spi_cs0_dis - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin - 0 - 1 - read-write - - - - - SPI_SLAVE - 0x30 - It is the synchronous reset signal of the module. This bit is self-cleared by hardware. - 32 - 0x00000000 - - - spi_sync_reset - It is the synchronous reset signal of the module. This bit is self-cleared by hardware. - 31 - 1 - read-write - - - spi_slave_mode - 1: slave mode, 0: master mode. - 30 - 1 - read-write - - - slv_cmd_define - 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". - 27 - 1 - read-write - - - spi_trans_cnt - The operations counter in both the master mode and the slave mode. - 23 - 4 - read-only - - - spi_int_en - Interrupt enable bits for the below 5 sources - 5 - 5 - read-write - - - spi_trans_done - The interrupt raw bit for the completement of any operation in both the master mode and the slave mode. - 4 - 1 - read-write - - - slv_wr_sta_done - The interrupt raw bit for the completement of "write-status" operation in the slave mode. - 3 - 1 - read-write - - - slv_rd_sta_done - The interrupt raw bit for the completement of "read-status" operation in the slave mode. - 2 - 1 - read-write - - - slv_wr_buf_done - The interrupt raw bit for the completement of "write-buffer" operation in the slave mode. - 1 - 1 - read-write - - - slv_rd_buf_done - The interrupt raw bit for the completement of "read-buffer" operation in the slave mode. - 0 - 1 - read-write - - - - - SPI_SLAVE1 - 0x34 - In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) - 32 - 0x00000000 - - - slv_status_bitlen - In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) - 27 - 5 - read-write - - - slv_buf_bitlen - In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1) - 16 - 9 - read-write - - - slv_rd_addr_bitlen - In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1) - 10 - 6 - read-write - - - slv_wr_addr_bitlen - In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1) - 4 - 6 - read-write - - - slv_wrsta_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations. - 3 - 1 - read-write - - - slv_rdsta_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations. - 2 - 1 - read-write - - - slv_wrbuf_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations. - 1 - 1 - read-write - - - slv_rdbuf_dummy_en - In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations. - 0 - 1 - read-write - - - - - SPI_SLAVE2 - 0x38 - In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) - 32 - 0x00000000 - - - slv_wrbuf_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) - 24 - 8 - read-write - - - slv_rdbuf_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1) - 16 - 8 - read-write - - - slv_wrsta_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1) - 8 - 8 - read-write - - - slv_rdsta_dummy_cyclelen - In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1) - 0 - 8 - read-write - - - - - SPI_SLAVE3 - 0x3c - In slave mode, it is the value of "write-status" command - 32 - 0x00000000 - - - slv_wrsta_cmd_value - In slave mode, it is the value of "write-status" command - 24 - 8 - read-write - - - slv_rdsta_cmd_value - In slave mode, it is the value of "read-status" command - 16 - 8 - read-write - - - slv_wrbuf_cmd_value - In slave mode, it is the value of "write-buffer" command - 8 - 8 - read-write - - - slv_rdbuf_cmd_value - In slave mode, it is the value of "read-buffer" command - 0 - 8 - read-write - - - - - SPI_EXT3 - 0xfc - This register is for two SPI masters to share the same cs, clock and data signals. - 32 - 0x00000000 - - - reg_int_hold_ena - This register is for two SPI masters to share the same cs, clock and data signals. - 0 - 2 - read-write - - - - - SPI_W0 - 0x40 - the data inside the buffer of the SPI module, word 0 - 32 - 0x00000000 - - - spi_w0 - the data inside the buffer of the SPI module, word 0 - 0 - 32 - read-write - - - - - SPI_W1 - 0x44 - the data inside the buffer of the SPI module, word 1 - 32 - 0x00000000 - - - spi_w1 - the data inside the buffer of the SPI module, word 1 - 0 - 32 - read-write - - - - - SPI_W2 - 0x48 - the data inside the buffer of the SPI module, word 2 - 32 - 0x00000000 - - - spi_w2 - the data inside the buffer of the SPI module, word 2 - 0 - 32 - read-write - - - - - SPI_W3 - 0x4c - the data inside the buffer of the SPI module, word 3 - 32 - 0x00000000 - - - spi_w3 - the data inside the buffer of the SPI module, word 3 - 0 - 32 - read-write - - - - - SPI_W4 - 0x50 - the data inside the buffer of the SPI module, word 4 - 32 - 0x00000000 - - - spi_w4 - the data inside the buffer of the SPI module, word 4 - 0 - 32 - read-write - - - - - SPI_W5 - 0x54 - the data inside the buffer of the SPI module, word 5 - 32 - 0x00000000 - - - spi_w5 - the data inside the buffer of the SPI module, word 5 - 0 - 32 - read-write - - - - - SPI_W6 - 0x58 - the data inside the buffer of the SPI module, word 6 - 32 - 0x00000000 - - - spi_w6 - the data inside the buffer of the SPI module, word 6 - 0 - 32 - read-write - - - - - SPI_W7 - 0x5c - the data inside the buffer of the SPI module, word 7 - 32 - 0x00000000 - - - spi_w7 - the data inside the buffer of the SPI module, word 7 - 0 - 32 - read-write - - - - - SPI_W8 - 0x60 - the data inside the buffer of the SPI module, word 8 - 32 - 0x00000000 - - - spi_w8 - the data inside the buffer of the SPI module, word 8 - 0 - 32 - read-write - - - - - SPI_W9 - 0x64 - the data inside the buffer of the SPI module, word 9 - 32 - 0x00000000 - - - spi_w9 - the data inside the buffer of the SPI module, word 9 - 0 - 32 - read-write - - - - - SPI_W10 - 0x68 - the data inside the buffer of the SPI module, word 10 - 32 - 0x00000000 - - - spi_w10 - the data inside the buffer of the SPI module, word 10 - 0 - 32 - read-write - - - - - SPI_W11 - 0x6c - the data inside the buffer of the SPI module, word 11 - 32 - 0x00000000 - - - spi_w11 - the data inside the buffer of the SPI module, word 11 - 0 - 32 - read-write - - - - - SPI_W12 - 0x70 - the data inside the buffer of the SPI module, word 12 - 32 - 0x00000000 - - - spi_w12 - the data inside the buffer of the SPI module, word 12 - 0 - 32 - read-write - - - - - SPI_W13 - 0x74 - the data inside the buffer of the SPI module, word 13 - 32 - 0x00000000 - - - spi_w13 - the data inside the buffer of the SPI module, word 13 - 0 - 32 - read-write - - - - - SPI_W14 - 0x78 - the data inside the buffer of the SPI module, word 14 - 32 - 0x00000000 - - - spi_w14 - the data inside the buffer of the SPI module, word 14 - 0 - 32 - read-write - - - - - SPI_W15 - 0x7c - the data inside the buffer of the SPI module, word 15 - 32 - 0x00000000 - - - spi_w15 - the data inside the buffer of the SPI module, word 15 - 0 - 32 - read-write - - - - - - - TIMER - 0x60000600 - - 0 - 0x00000120 - registers - - - - FRC1_LOAD - 0x0 - the load value into the counter - 32 - 0x00000000 - - - frc1_load_value - the load value into the counter - 0 - 23 - read-write - - - - - FRC1_COUNT - 0x4 - the current value of the counter. It is a decreasingcounter. - 32 - 0x00000000 - - - frc1_count - the current value of the counter. It is a decreasingcounter. - 0 - 23 - read-only - - - - - FRC1_CTRL - 0x8 - FRC1_CTRL - 32 - 0x00000000 - - - frc1_int - the status of the interrupt, when the count isdereased to zero - 8 - 1 - read-only - - - frc1_ctrl - bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level - 0 - 8 - read-write - - - - - FRC1_INT - 0xc - FRC1_INT - 32 - 0x00000000 - - - frc1_int_clr_mask - write to clear the status of the interrupt, if theinterrupt type is "level" - 0 - 1 - read-write - - - - - FRC2_LOAD - 0x20 - the load value into the counter - 32 - 0x00000000 - - - frc2_load_value - the load value into the counter - 0 - 32 - read-write - - - - - FRC2_COUNT - 0x24 - the current value of the counter. It is a increasingcounter. - 32 - 0x00000000 - - - frc2_count - the current value of the counter. It is a increasingcounter. - 0 - 32 - read-only - - - - - FRC2_CTRL - 0x28 - FRC2_CTRL - 32 - 0x00000000 - - - frc2_int - the status of the interrupt, when the count is equal tothe alarm value - 8 - 1 - read-only - - - frc2_ctrl - bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level - 0 - 8 - read-write - - - - - FRC2_INT - 0x2c - FRC2_INT - 32 - 0x00000000 - - - frc2_int_clr_mask - write to clear the status of the interrupt, if theinterrupt type is "level" - 0 - 1 - read-write - - - - - FRC2_ALARM - 0x30 - the alarm value for the counter - 32 - 0x00000000 - - - frc2_alarm - the alarm value for the counter - 0 - 32 - read-write - - - - - - - UART0 - 0x60000000 - - 0 - 0x000001e0 - registers - - - - UART_FIFO - 0x0 - UART FIFO,length 128 - 32 - 0x00000000 - - - rxfifo_rd_byte - R/W share the same address - 0 - 8 - read-only - - - - - UART_INT_RAW - 0x4 - UART INTERRUPT RAW STATE - 32 - 0x00000000 - - - rxfifo_tout_int_raw - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD) - 8 - 1 - read-only - - - brk_det_int_raw - The interrupt raw bit for Rx byte start error - 7 - 1 - read-only - - - cts_chg_int_raw - The interrupt raw bit for CTS changing level - 6 - 1 - read-only - - - dsr_chg_int_raw - The interrupt raw bit for DSR changing level - 5 - 1 - read-only - - - rxfifo_ovf_int_raw - The interrupt raw bit for rx fifo overflow - 4 - 1 - read-only - - - frm_err_int_raw - The interrupt raw bit for other rx error - 3 - 1 - read-only - - - parity_err_int_raw - The interrupt raw bit for parity check error - 2 - 1 - read-only - - - txfifo_empty_int_raw - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits) - 1 - 1 - read-only - - - rxfifo_full_int_raw - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits) - 0 - 1 - read-only - - - - - UART_INT_ST - 0x8 - UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA - 32 - 0x00000000 - - - rxfifo_tout_int_st - The interrupt state bit for Rx time-out event - 8 - 1 - read-only - - - brk_det_int_st - The interrupt state bit for rx byte start error - 7 - 1 - read-only - - - cts_chg_int_st - The interrupt state bit for CTS changing level - 6 - 1 - read-only - - - dsr_chg_int_st - The interrupt state bit for DSR changing level - 5 - 1 - read-only - - - rxfifo_ovf_int_st - The interrupt state bit for RX fifo overflow - 4 - 1 - read-only - - - frm_err_int_st - The interrupt state for other rx error - 3 - 1 - read-only - - - parity_err_int_st - The interrupt state bit for rx parity error - 2 - 1 - read-only - - - txfifo_empty_int_st - The interrupt state bit for TX fifo empty - 1 - 1 - read-only - - - rxfifo_full_int_st - The interrupt state bit for RX fifo full event - 0 - 1 - read-only - - - - - UART_INT_ENA - 0xc - UART INTERRUPT ENABLE REGISTER - 32 - 0x00000000 - - - rxfifo_tout_int_ena - The interrupt enable bit for rx time-out interrupt - 8 - 1 - read-write - - - brk_det_int_ena - The interrupt enable bit for rx byte start error - 7 - 1 - read-write - - - cts_chg_int_ena - The interrupt enable bit for CTS changing level - 6 - 1 - read-write - - - dsr_chg_int_ena - The interrupt enable bit for DSR changing level - 5 - 1 - read-write - - - rxfifo_ovf_int_ena - The interrupt enable bit for rx fifo overflow - 4 - 1 - read-write - - - frm_err_int_ena - The interrupt enable bit for other rx error - 3 - 1 - read-write - - - parity_err_int_ena - The interrupt enable bit for parity error - 2 - 1 - read-write - - - txfifo_empty_int_ena - The interrupt enable bit for tx fifo empty event - 1 - 1 - read-write - - - rxfifo_full_int_ena - The interrupt enable bit for rx fifo full event - 0 - 1 - read-write - - - - - UART_INT_CLR - 0x10 - UART INTERRUPT CLEAR REGISTER - 32 - 0x00000000 - - - rxfifo_tout_int_clr - Set this bit to clear the rx time-out interrupt - 8 - 1 - write-only - - - brk_det_int_clr - Set this bit to clear the rx byte start interrupt - 7 - 1 - write-only - - - cts_chg_int_clr - Set this bit to clear the CTS changing interrupt - 6 - 1 - write-only - - - dsr_chg_int_clr - Set this bit to clear the DSR changing interrupt - 5 - 1 - write-only - - - rxfifo_ovf_int_clr - Set this bit to clear the rx fifo over-flow interrupt - 4 - 1 - write-only - - - frm_err_int_clr - Set this bit to clear other rx error interrupt - 3 - 1 - write-only - - - parity_err_int_clr - Set this bit to clear the parity error interrupt - 2 - 1 - write-only - - - txfifo_empty_int_clr - Set this bit to clear the tx fifo empty interrupt - 1 - 1 - write-only - - - rxfifo_full_int_clr - Set this bit to clear the rx fifo full interrupt - 0 - 1 - write-only - - - - - UART_CLKDIV - 0x14 - UART CLK DIV REGISTER - 32 - 0x00000000 - - - uart_clkdiv - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV - 0 - 20 - read-write - - - - - UART_AUTOBAUD - 0x18 - UART BAUDRATE DETECT REGISTER - 32 - 0x00000000 - - - glitch_filt - 8 - 8 - read-write - - - autobaud_en - Set this bit to enable baudrate detect - 0 - 1 - read-write - - - - - UART_STATUS - 0x1c - UART STATUS REGISTER - 32 - 0x00000000 - - - txd - The level of the uart txd pin - 31 - 1 - read-only - - - rtsn - The level of uart rts pin - 30 - 1 - read-only - - - dtrn - The level of uart dtr pin - 29 - 1 - read-only - - - txfifo_cnt - Number of data in UART TX fifo - 16 - 8 - read-only - - - rxd - The level of uart rxd pin - 15 - 1 - read-only - - - ctsn - The level of uart cts pin - 14 - 1 - read-only - - - dsrn - The level of uart dsr pin - 13 - 1 - read-only - - - rxfifo_cnt - Number of data in uart rx fifo - 0 - 8 - read-only - - - - - UART_CONF0 - 0x20 - UART CONFIG0(UART0 and UART1) - 32 - 0x00000000 - - - uart_dtr_inv - Set this bit to inverse uart dtr level - 24 - 1 - read-write - - - uart_rts_inv - Set this bit to inverse uart rts level - 23 - 1 - read-write - - - uart_txd_inv - Set this bit to inverse uart txd level - 22 - 1 - read-write - - - uart_dsr_inv - Set this bit to inverse uart dsr level - 21 - 1 - read-write - - - uart_cts_inv - Set this bit to inverse uart cts level - 20 - 1 - read-write - - - uart_rxd_inv - Set this bit to inverse uart rxd level - 19 - 1 - read-write - - - txfifo_rst - Set this bit to reset uart tx fifo - 18 - 1 - read-write - - - rxfifo_rst - Set this bit to reset uart rx fifo - 17 - 1 - read-write - - - tx_flow_en - Set this bit to enable uart tx hardware flow control - 15 - 1 - read-write - - - uart_loopback - Set this bit to enable uart loopback test mode - 14 - 1 - read-write - - - txd_brk - RESERVED, DO NOT CHANGE THIS BIT - 8 - 1 - read-write - - - sw_dtr - sw dtr - 7 - 1 - read-write - - - sw_rts - sw rts - 6 - 1 - read-write - - - stop_bit_num - Set stop bit: 1:1bit 2:1.5bits 3:2bits - 4 - 2 - read-write - - - bit_num - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits - 2 - 2 - read-write - - - parity_en - Set this bit to enable uart parity check - 1 - 1 - read-write - - - parity - Set parity check: 0:even 1:odd, UART CONFIG1 - 0 - 1 - read-write - - - - - UART_CONF1 - 0x24 - Set this bit to enable rx time-out function - 32 - 0x00000000 - - - rx_tout_en - Set this bit to enable rx time-out function - 31 - 1 - read-write - - - rx_tout_thrhd - Config bits for rx time-out threshold,uint: byte,0-127 - 24 - 7 - read-write - - - rx_flow_en - Set this bit to enable rx hardware flow control - 23 - 1 - read-write - - - rx_flow_thrhd - The config bits for rx flow control threshold,0-127 - 16 - 7 - read-write - - - txfifo_empty_thrhd - The config bits for tx fifo empty threshold,0-127 - 8 - 7 - read-write - - - rxfifo_full_thrhd - The config bits for rx fifo full threshold,0-127 - 0 - 7 - read-write - - - - - UART_LOWPULSE - 0x28 - UART_LOWPULSE - 32 - 0x00000000 - - - lowpulse_min_cnt - used in baudrate detect - 0 - 20 - read-only - - - - - UART_HIGHPULSE - 0x2c - UART_HIGHPULSE - 32 - 0x00000000 - - - highpulse_min_cnt - used in baudrate detect - 0 - 20 - read-only - - - - - UART_RXD_CNT - 0x30 - UART_RXD_CNT - 32 - 0x00000000 - - - rxd_edge_cnt - used in baudrate detect - 0 - 10 - read-only - - - - - UART_DATE - 0x78 - UART HW INFO - 32 - 0x00000000 - - - uart_date - UART HW INFO - 0 - 32 - read-write - - - - - UART_ID - 0x7c - UART_ID - 32 - 0x00000000 - - - uart_id - 0 - 32 - read-write - - - - - - - UART1 - 0x60000f00 - - 0 - 0x000001e0 - registers - - - - UART_FIFO - 0x0 - UART FIFO,length 128 - 32 - 0x00000000 - - - rxfifo_rd_byte - R/W share the same address - 0 - 8 - read-only - - - - - UART_INT_RAW - 0x4 - UART INTERRUPT RAW STATE - 32 - 0x00000000 - - - rxfifo_tout_int_raw - The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD) - 8 - 1 - read-only - - - brk_det_int_raw - The interrupt raw bit for Rx byte start error - 7 - 1 - read-only - - - cts_chg_int_raw - The interrupt raw bit for CTS changing level - 6 - 1 - read-only - - - dsr_chg_int_raw - The interrupt raw bit for DSR changing level - 5 - 1 - read-only - - - rxfifo_ovf_int_raw - The interrupt raw bit for rx fifo overflow - 4 - 1 - read-only - - - frm_err_int_raw - The interrupt raw bit for other rx error - 3 - 1 - read-only - - - parity_err_int_raw - The interrupt raw bit for parity check error - 2 - 1 - read-only - - - txfifo_empty_int_raw - The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits) - 1 - 1 - read-only - - - rxfifo_full_int_raw - The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits) - 0 - 1 - read-only - - - - - UART_INT_ST - 0x8 - UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA - 32 - 0x00000000 - - - rxfifo_tout_int_st - The interrupt state bit for Rx time-out event - 8 - 1 - read-only - - - brk_det_int_st - The interrupt state bit for rx byte start error - 7 - 1 - read-only - - - cts_chg_int_st - The interrupt state bit for CTS changing level - 6 - 1 - read-only - - - dsr_chg_int_st - The interrupt state bit for DSR changing level - 5 - 1 - read-only - - - rxfifo_ovf_int_st - The interrupt state bit for RX fifo overflow - 4 - 1 - read-only - - - frm_err_int_st - The interrupt state for other rx error - 3 - 1 - read-only - - - parity_err_int_st - The interrupt state bit for rx parity error - 2 - 1 - read-only - - - txfifo_empty_int_st - The interrupt state bit for TX fifo empty - 1 - 1 - read-only - - - rxfifo_full_int_st - The interrupt state bit for RX fifo full event - 0 - 1 - read-only - - - - - UART_INT_ENA - 0xc - UART INTERRUPT ENABLE REGISTER - 32 - 0x00000000 - - - rxfifo_tout_int_ena - The interrupt enable bit for rx time-out interrupt - 8 - 1 - read-write - - - brk_det_int_ena - The interrupt enable bit for rx byte start error - 7 - 1 - read-write - - - cts_chg_int_ena - The interrupt enable bit for CTS changing level - 6 - 1 - read-write - - - dsr_chg_int_ena - The interrupt enable bit for DSR changing level - 5 - 1 - read-write - - - rxfifo_ovf_int_ena - The interrupt enable bit for rx fifo overflow - 4 - 1 - read-write - - - frm_err_int_ena - The interrupt enable bit for other rx error - 3 - 1 - read-write - - - parity_err_int_ena - The interrupt enable bit for parity error - 2 - 1 - read-write - - - txfifo_empty_int_ena - The interrupt enable bit for tx fifo empty event - 1 - 1 - read-write - - - rxfifo_full_int_ena - The interrupt enable bit for rx fifo full event - 0 - 1 - read-write - - - - - UART_INT_CLR - 0x10 - UART INTERRUPT CLEAR REGISTER - 32 - 0x00000000 - - - rxfifo_tout_int_clr - Set this bit to clear the rx time-out interrupt - 8 - 1 - write-only - - - brk_det_int_clr - Set this bit to clear the rx byte start interrupt - 7 - 1 - write-only - - - cts_chg_int_clr - Set this bit to clear the CTS changing interrupt - 6 - 1 - write-only - - - dsr_chg_int_clr - Set this bit to clear the DSR changing interrupt - 5 - 1 - write-only - - - rxfifo_ovf_int_clr - Set this bit to clear the rx fifo over-flow interrupt - 4 - 1 - write-only - - - frm_err_int_clr - Set this bit to clear other rx error interrupt - 3 - 1 - write-only - - - parity_err_int_clr - Set this bit to clear the parity error interrupt - 2 - 1 - write-only - - - txfifo_empty_int_clr - Set this bit to clear the tx fifo empty interrupt - 1 - 1 - write-only - - - rxfifo_full_int_clr - Set this bit to clear the rx fifo full interrupt - 0 - 1 - write-only - - - - - UART_CLKDIV - 0x14 - UART CLK DIV REGISTER - 32 - 0x00000000 - - - uart_clkdiv - BAUDRATE = UART_CLK_FREQ / UART_CLKDIV - 0 - 20 - read-write - - - - - UART_AUTOBAUD - 0x18 - UART BAUDRATE DETECT REGISTER - 32 - 0x00000000 - - - glitch_filt - 8 - 8 - read-write - - - autobaud_en - Set this bit to enable baudrate detect - 0 - 1 - read-write - - - - - UART_STATUS - 0x1c - UART STATUS REGISTER - 32 - 0x00000000 - - - txd - The level of the uart txd pin - 31 - 1 - read-only - - - rtsn - The level of uart rts pin - 30 - 1 - read-only - - - dtrn - The level of uart dtr pin - 29 - 1 - read-only - - - txfifo_cnt - Number of data in UART TX fifo - 16 - 8 - read-only - - - rxd - The level of uart rxd pin - 15 - 1 - read-only - - - ctsn - The level of uart cts pin - 14 - 1 - read-only - - - dsrn - The level of uart dsr pin - 13 - 1 - read-only - - - rxfifo_cnt - Number of data in uart rx fifo - 0 - 8 - read-only - - - - - UART_CONF0 - 0x20 - UART CONFIG0(UART0 and UART1) - 32 - 0x00000000 - - - uart_dtr_inv - Set this bit to inverse uart dtr level - 24 - 1 - read-write - - - uart_rts_inv - Set this bit to inverse uart rts level - 23 - 1 - read-write - - - uart_txd_inv - Set this bit to inverse uart txd level - 22 - 1 - read-write - - - uart_dsr_inv - Set this bit to inverse uart dsr level - 21 - 1 - read-write - - - uart_cts_inv - Set this bit to inverse uart cts level - 20 - 1 - read-write - - - uart_rxd_inv - Set this bit to inverse uart rxd level - 19 - 1 - read-write - - - txfifo_rst - Set this bit to reset uart tx fifo - 18 - 1 - read-write - - - rxfifo_rst - Set this bit to reset uart rx fifo - 17 - 1 - read-write - - - tx_flow_en - Set this bit to enable uart tx hardware flow control - 15 - 1 - read-write - - - uart_loopback - Set this bit to enable uart loopback test mode - 14 - 1 - read-write - - - txd_brk - RESERVED, DO NOT CHANGE THIS BIT - 8 - 1 - read-write - - - sw_dtr - sw dtr - 7 - 1 - read-write - - - sw_rts - sw rts - 6 - 1 - read-write - - - stop_bit_num - Set stop bit: 1:1bit 2:1.5bits 3:2bits - 4 - 2 - read-write - - - bit_num - Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits - 2 - 2 - read-write - - - parity_en - Set this bit to enable uart parity check - 1 - 1 - read-write - - - parity - Set parity check: 0:even 1:odd, UART CONFIG1 - 0 - 1 - read-write - - - - - UART_CONF1 - 0x24 - Set this bit to enable rx time-out function - 32 - 0x00000000 - - - rx_tout_en - Set this bit to enable rx time-out function - 31 - 1 - read-write - - - rx_tout_thrhd - Config bits for rx time-out threshold,uint: byte,0-127 - 24 - 7 - read-write - - - rx_flow_en - Set this bit to enable rx hardware flow control - 23 - 1 - read-write - - - rx_flow_thrhd - The config bits for rx flow control threshold,0-127 - 16 - 7 - read-write - - - txfifo_empty_thrhd - The config bits for tx fifo empty threshold,0-127 - 8 - 7 - read-write - - - rxfifo_full_thrhd - The config bits for rx fifo full threshold,0-127 - 0 - 7 - read-write - - - - - UART_LOWPULSE - 0x28 - UART_LOWPULSE - 32 - 0x00000000 - - - lowpulse_min_cnt - used in baudrate detect - 0 - 20 - read-only - - - - - UART_HIGHPULSE - 0x2c - UART_HIGHPULSE - 32 - 0x00000000 - - - highpulse_min_cnt - used in baudrate detect - 0 - 20 - read-only - - - - - UART_RXD_CNT - 0x30 - UART_RXD_CNT - 32 - 0x00000000 - - - rxd_edge_cnt - used in baudrate detect - 0 - 10 - read-only - - - - - UART_DATE - 0x78 - UART HW INFO - 32 - 0x00000000 - - - uart_date - UART HW INFO - 0 - 32 - read-write - - - - - UART_ID - 0x7c - UART_ID - 32 - 0x00000000 - - - uart_id - 0 - 32 - read-write - - - - - - - WDT - 0x60000900 - - 0 - 0x00000080 - registers - - - - WDT_CTL - 0x0 - WDT_CTL - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - WDT_OP - 0x4 - WDT_OP - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - WDT_OP_ND - 0x8 - WDT_OP_ND - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - WDT_RST - 0x14 - WDT_RST - 32 - 0x00000000 - - - Register - 0 - 32 - read-write - - - - - - - diff --git a/esp8266/svd/patches/_dport.yaml b/esp8266/svd/patches/_dport.yaml deleted file mode 100644 index 9b2f59fab5..0000000000 --- a/esp8266/svd/patches/_dport.yaml +++ /dev/null @@ -1,114 +0,0 @@ -"DPORT": - EDGE_INT_ENABLE: - _add: - wdt_edge_int_enable: - description: "Enable the watchdog timer edge interrupt" - bitOffset: 0 - bitWidth: 1 - timer1_edge_int_enable: - description: "Enable the timer1 edge interrupt" - bitOffset: 1 - bitWidth: 1 - _add: - IOSWAP: - description: IO Swap register - addressOffset: 0x28 - size: 32 - access: read-write - resetValue: 0x00000000 - fields: - uart: - description: "Swap UART" - bitOffset: 0 - bitWidth: 1 - spi: - description: "Swap SPI" - bitOffset: 1 - bitWidth: 1 - uart0: - description: "Swap UART0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)" - bitOffset: 2 - bitWidth: 1 - uart1: - description: "Swap UART1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)" - bitOffset: 3 - bitWidth: 1 - hspi: - description: "Set HSPI with higher priority" - bitOffset: 5 - bitWidth: 1 - double_hspi: - description: "Set two SPI masters on HSPI" - bitOffset: 6 - bitWidth: 1 - double_cspi: - description: "Set two SPI masters on CSPI" - bitOffset: 7 - bitWidth: 1 - SPI_CACHE: - description: "Controls SPI memory-mapped caching" - addressOffset: 0xc - size: 32 - access: read-write - resetValue: 0x00000000 - fields: - cache_flush_start: - description: "Flush cache" - bitOffset: 0 - bitWidth: 1 - cache_empty: - description: "Cache is empty" - bitOffset: 1 - bitWidth: 1 - cache_enable: - description: "Cache enable" - bitOffset: 8 - bitWidth: 1 - busy: - description: "SPI busy" - bitOffset: 9 - bitWidth: 1 - block: - description: "Flash memory block to map, in 2mb blocks" - bitOffset: 16 - bitWidth: 3 - offset: - description: "Offset within block to map, in megabytes" - bitOffset: 24 - bitWidth: 2 - target: - description: "Controls where the spi flash is mapped (unconfirmed)" - bitOffset: 26 - bitWidth: 1 - SPI_INTERRUPT_TYPE: - description: "SPI interrupt type register" - addressOffset: 0x20 - size: 32 - access: read-only - resetValue: 0x00000000 - fields: - spi0: - description: "SPI0 interrupt" - bitOffset: 4 - bitWidth: 1 - spi1: - description: "SPI1 interrupt" - bitOffset: 7 - bitWidth: 1 - i2s: - description: "I2S interrupt" - bitOffset: 9 - bitWidth: 1 - SPI_CACHE_TARGET: - description: "Control where the cache is mapped (unconfirmed)" - addressOffset: 0x24 - size: 32 - access: read-write - resetValue: 0x00000000 - fields: - target1: - bitOffset: 3 - bitWidth: 1 - target2: - bitOffset: 4 - bitWidth: 1 \ No newline at end of file diff --git a/esp8266/svd/patches/_gpio.yaml b/esp8266/svd/patches/_gpio.yaml deleted file mode 100644 index 02a51f881c..0000000000 --- a/esp8266/svd/patches/_gpio.yaml +++ /dev/null @@ -1,15 +0,0 @@ -GPIO: - "GPIO_PIN*": - "GPIO_PIN*_INT_TYPE": - disabled: [0, "interrupt is disabled"] - positive_edge: [1, "interrupt is triggered on the positive edge"] - negative_edge: [2, "interrupt is triggered on the negative edge"] - both_edges: [3, "interrupt is triggered on both edges"] - low_level: [4, "interrupt is triggered on the low level"] - high_level: [5, "interrupt is triggered on the high level"] - "GPIO_PIN*_DRIVER": - open_drain: [0, "open drain"] - normal: [1, "normal"] - "GPIO_PIN*_SOURCE": - sigma_delta: [0, "sigma-delta"] - gpio_data: [1, "gpio data"] diff --git a/esp8266/svd/patches/_io_mux.yaml b/esp8266/svd/patches/_io_mux.yaml deleted file mode 100644 index 14bbfca0c8..0000000000 --- a/esp8266/svd/patches/_io_mux.yaml +++ /dev/null @@ -1,23 +0,0 @@ -IO_MUX: - "IO_MUX_[MUSG]*": # matches the 16 pin configuration, but not IO_MUX_CONF - _add: - FUNCTION_SELECT_LOW_BITS: - description: "configures IO_MUX function, bottom 2 bits" - bitOffset: 4 - bitWidth: 2 - FUNCTION_SELECT_HIGH_BIT: - description: "configures IO_MUX function, upper bit" - bitOffset: 8 - bitWidth: 1 - PULLUP: - description: "configures pull up" - bitOffset: 7 - bitWidth: 1 - SLEEP_PULLUP: - description: "configures pull up during sleep mode" - bitOffset: 3 - bitWidth: 1 - SLEEP_ENABLE: - description: "configures output enable during sleep mode" - bitOffset: 0 - bitWidth: 1 \ No newline at end of file diff --git a/esp8266/svd/patches/_misc.yaml b/esp8266/svd/patches/_misc.yaml deleted file mode 100644 index 8417111226..0000000000 --- a/esp8266/svd/patches/_misc.yaml +++ /dev/null @@ -1,103 +0,0 @@ -_add: - # See https://web.archive.org/web/20170604020535/http://esp8266-re.foogod.com/wiki/Random_Number_Generator - RNG: - description: RNG register - baseAddress: "0x3FF20E44" - addressBlock: - offset: 0x0 - size: 32 - usage: "registers" - registers: - rng: - description: RNG register - addressOffset: 0x0 - size: 32 - access: read-only - resetValue: 0x00000000 - RTCCNTL: - description: "Internal I2C registers" - baseAddress: 0x60000d00 - addressBlock: - offset: 0x0 - size: 32 - usage: "registers" - registers: - PLL: - description: PLL I2C Register - addressOffset: 0x10 - size: 32 - access: read-write - resetValue: 0 - fields: - BLOCK: - description: Block - bitOffset: 0 - bitWidth: 8 - ADDR: - description: Address - bitOffset: 8 - bitWidth: 8 - DATA: - description: Data - bitOffset: 16 - bitWidth: 8 - WRITE: - description: Write - bitOffset: 24 - bitWidth: 1 - BUSY: - description: Ready - bitOffset: 25 - bitWidth: 1 - -# See https://mongoose-os.com/blog/esp8266-watchdog-timer/ -WDT: - WDT_CTL: - _add: - enable: - description: "Enable the watchdog timer." - bitOffset: 0 - bitWidth: 1 - stage_1_no_reset: - description: "When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device." - bitOffset: 1 - bitWidth: 1 - stage_1_disable: - description: "Set to 1 to disable the stage 1 of the watchdog timer" - bitOffset: 2 - bitWidth: 1 - unknown_3: - bitOffset: 3 - bitWidth: 1 - unknown_4: - bitOffset: 4 - bitWidth: 1 - unknown_5: - bitOffset: 5 - bitWidth: 1 - _modify: - WDT_RST: - description: Watchdog reset - WDT_OP: - description: Reload value for stage 0 - WDT_OP_ND: - description: Reload value for stage 1 - _add: - count: - description: Watchdog clock cycle count - addressOffset: 0xc - size: 32 - access: read-write - resetValue: 0x00000000 - stage: - description: The current watchdog stage - addressOffset: 0x10 - size: 32 - access: read-write - resetValue: 0x00000000 - reset_stage: - description: Watchdog stage reset - addressOffset: 0x18 - size: 32 - access: read-write - resetValue: 0x00000000 diff --git a/esp8266/svd/patches/_rtc.yaml b/esp8266/svd/patches/_rtc.yaml deleted file mode 100644 index 36e11fdcbe..0000000000 --- a/esp8266/svd/patches/_rtc.yaml +++ /dev/null @@ -1,33 +0,0 @@ -# https://github.com/cesanta/mongoose-os/blob/f626b5113861634e9a4acc96bdb73de29ed8a4d0/platforms/esp8266/rboot/rboot/rboot.c#L129-L135 -RTC: - _add: - PAD_XPD_DCDC_CONF: - access: read-write - addressOffset: 0xA0 - description: PAD_XPD_DCDC_CONF - resetValue: 0x0 - size: 32 - RTC_GPIO_CONF: - access: read-write - addressOffset: 0x90 - description: RTC_GPIO_CONF - resetValue: 0x0 - size: 32 - RTC_GPIO_ENABLE: - access: read-write - addressOffset: 0x74 - description: RTC_GPIO_ENABLE - resetValue: 0x0 - size: 32 - RTC_GPIO_IN_DATA: - access: read-write - addressOffset: 0x8C - description: RTC_GPIO_IN_DATA - resetValue: 0x0 - size: 32 - RTC_GPIO_OUT: - access: read-write - addressOffset: 0x68 - description: RTC_GPIO_OUT - resetValue: 0x0 - size: 32 diff --git a/esp8266/svd/patches/_spi.yaml b/esp8266/svd/patches/_spi.yaml deleted file mode 100644 index 41bd3093e3..0000000000 --- a/esp8266/svd/patches/_spi.yaml +++ /dev/null @@ -1,213 +0,0 @@ -"SPI*": - SPI_CMD: - _add: - spi_read: - bitOffset: 31 - bitWidth: 1 - spi_write_enable: - bitOffset: 30 - bitWidth: 1 - spi_write_disable: - bitOffset: 29 - bitWidth: 1 - spi_read_id: - bitOffset: 28 - bitWidth: 1 - spi_read_sr: - bitOffset: 27 - bitWidth: 1 - spi_write_sr: - bitOffset: 26 - bitWidth: 1 - spi_pp: - bitOffset: 25 - bitWidth: 1 - spi_se: - bitOffset: 24 - bitWidth: 1 - spi_be: - bitOffset: 23 - bitWidth: 1 - spi_ce: - bitOffset: 22 - bitWidth: 1 - spi_dp: - bitOffset: 21 - bitWidth: 1 - spi_res: - bitOffset: 20 - bitWidth: 1 - spi_hpm: - bitOffset: 19 - bitWidth: 1 - SPI_ADDR: - _add: - address: - bitOffset: 0 - bitWidth: 24 - size: - bitOffset: 24 - bitWidth: 8 - SPI_USER: - _add: - spi_ck_o_edge: - description: "In the master mode, 1: rising-edge; 0: falling-edge" - bitOffset: 7 - bitWidth: 1 - spi_cs_setup: - description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." - bitOffset: 5 - bitWidth: 1 - spi_cs_hold: - description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." - bitOffset: 4 - bitWidth: 1 - spi_ahb_user_command: - description: "reserved" - bitOffset: 3 - bitWidth: 1 - spi_flash_mode: - bitOffset: 2 - bitWidth: 1 - spi_ahb_user_command_4byte: - description: "reserved" - bitOffset: 1 - bitWidth: 1 - spi_duplex: - description: "set spi in full duplex mode" - bitOffset: 0 - bitWidth: 1 - SPI_PIN: - _add: - spi_idle_edge: - description: "In the master mode, 1: high when idle; 0: low when idle" - bitOffset: 29 - bitWidth: 1 - SPI_SLAVE: - _add: - spi_buffer_enable: - description: "Enable read/write buffer" - bitOffset: 29 - bitWidth: 1 - sta_enable: - description: "Enable read/write buffer" - bitOffset: 28 - bitWidth: 1 - interrupt_trans_enable: - description: "Enable TRANS interrupts" - bitOffset: 9 - bitWidth: 1 - interrupt_ws_enable: - description: "Enable status write interrupts" - bitOffset: 8 - bitWidth: 1 - interrupt_rs_enable: - description: "Enable status read interrupts" - bitOffset: 7 - bitWidth: 1 - interrupt_wb_enable: - description: "Enable buffer write interrupts" - bitOffset: 6 - bitWidth: 1 - interrupt_rb_enable: - description: "Enable buffer read interrupts" - bitOffset: 5 - bitWidth: 1 - SPI_SLAVE1: - _add: - spi_status_fast_enable: - description: "Enable fast spi slave status " - bitOffset: 26 - bitWidth: 1 - spi_status_read: - description: "Enable spi slave status" - bitOffset: 25 - bitWidth: 1 - SPI_CTRL: - _add: - two_byte_status: - description: "Enable two byte status" - bitOffset: 22 - bitWidth: 1 - wp_reg: - description: "Write protect?" - bitOffset: 21 - bitWidth: 1 - share_but: - description: "Share bus" - bitOffset: 19 - bitWidth: 1 - hold_mode: - description: "Hold mode" - bitOffset: 18 - bitWidth: 1 - enable_ahb: - description: "Enable AHB" - bitOffset: 17 - bitWidth: 1 - sst_aai: - description: "SST_AAI?" - bitOffset: 16 - bitWidth: 1 - res_and_res: - description: "'Res and res'?" - bitOffset: 15 - bitWidth: 1 - _add: - SPI_CTRL1: - addressOffset: 0xc - size: 32 - access: read-write - resetValue: 0 - fields: - status: - description: "In the slave mode, it is the status for master to read out." - bitOffset: 0 - bitWidth: 16 - wb_mode: - description: "Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit." - bitOffset: 16 - bitWidth: 8 - status_ext: - description: "In the slave mode,it is the status for master to read out." - bitOffset: 24 - bitWidth: 8 - SPI_EXT0: - addressOffset: 0xF0 - size: 32 - access: read-write - resetValue: 0 - fields: - pp_enable: - bitOffset: 31 - bitWidth: 1 - pp_shift: - bitOffset: 16 - bitWidth: 4 - pp_time: - bitOffset: 0 - bitWidth: 12 - SPI_EXT1: - addressOffset: 0xF4 - size: 32 - access: read-write - resetValue: 0 - fields: - erase_enable: - bitOffset: 31 - bitWidth: 1 - erase_shift: - bitOffset: 16 - bitWidth: 4 - erase_time: - bitOffset: 0 - bitWidth: 12 - SPI_EXT2: - addressOffset: 0xF8 - size: 32 - access: read-write - resetValue: 0 - fields: - st: - bitOffset: 0 - bitWidth: 3 \ No newline at end of file diff --git a/esp8266/svd/patches/_timer.yaml b/esp8266/svd/patches/_timer.yaml deleted file mode 100644 index bdc3483476..0000000000 --- a/esp8266/svd/patches/_timer.yaml +++ /dev/null @@ -1,30 +0,0 @@ -"TIMER*": - FRC*_CTRL: - _add: - timer_enable: - description: "Enable or disable the timer" - bitOffset: 7 - bitWidth: 1 - access: read-write - rollover: - description: "Automatically reload when the counter hits zero" - bitOffset: 6 - bitWidth: 1 - access: read-write - prescale_divider: - description: "Pre-scale divider for the timer" - bitOffset: 2 - bitWidth: 2 - access: read-write - interrupt_type: - description: "Configure the interrupt type" - bitOffset: 0 - bitWidth: 1 - access: read-write - prescale_divider: - devided_by_1: [0, "divided by 1"] - devided_by_16: [1, "divided by 16"] - devided_by_256: [2, "divided by 256"] - interrupt_type: - edge: [0, "edge"] - level: [1, "level"] diff --git a/esp8266/svd/patches/_uart.yaml b/esp8266/svd/patches/_uart.yaml deleted file mode 100644 index 8bfef34787..0000000000 --- a/esp8266/svd/patches/_uart.yaml +++ /dev/null @@ -1,7 +0,0 @@ -"UART*": - UART_FIFO: - _add: - rxfifo_write_byte: - description: "R/W share the same address" - bitOffset: 0 - bitWidth: 8 \ No newline at end of file diff --git a/esp8266/svd/patches/esp8266.yaml b/esp8266/svd/patches/esp8266.yaml deleted file mode 100644 index 52779f8539..0000000000 --- a/esp8266/svd/patches/esp8266.yaml +++ /dev/null @@ -1,11 +0,0 @@ -_svd: ../esp8266.base.svd - -_include: - - "_dport.yaml" - - "_gpio.yaml" - - "_io_mux.yaml" - - "_misc.yaml" - - "_rtc.yaml" - - "_spi.yaml" - - "_timer.yaml" - - "_uart.yaml" From a2e03ed1a7392190e2c42462f42af46901bb7012 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Mon, 5 Feb 2024 10:43:54 -0800 Subject: [PATCH 2/2] Remove ESP8266 from `xtask` package and `README.md` --- README.md | 5 +---- xtask/src/main.rs | 1 - 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/README.md b/README.md index e6947f4d3b..a01267fac5 100644 --- a/README.md +++ b/README.md @@ -92,10 +92,7 @@ Prior to opening a pull request, we ask that you please: ## MSRV -The **M**inimum **S**upported **R**ust **V**ersions are: - -- `1.67.0` for RISC-V devices (**ESP32-C2/C3/C6**, **ESP32-H2**, **ESP32-S2/S3 RISC-V ULP coprocessors**) -- `1.67.0` for Xtensa devices (**ESP32**, **ESP32-S2/S3**, **ESP8266**) +The **M**inimum **S**upported **R**ust **V**ersion is `1.67.0` for all packages. Note that targeting the Xtensa ISA currently requires the use of the [esp-rs/rust] compiler fork, which can be installed using [esp-rs/espup]. diff --git a/xtask/src/main.rs b/xtask/src/main.rs index 1c9e909574..7817fab5d1 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -27,7 +27,6 @@ enum Chip { Esp32s2Ulp, Esp32s3, Esp32s3Ulp, - Esp8266, } #[derive(Debug, Clone, Copy, Display, ValueEnum)]