From fc633202bfa16e4561555abf41a9ca43203d9a42 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 3 Feb 2020 19:56:26 -0800 Subject: [PATCH 01/48] PoC cache configuration control Expaned boards.txt.py to allow new MMU options and create revised .ld's Updated eboot to pass 48K IRAM segments. Added Cache_Read_Enable intercept to modify call for 16K ICACHE Update platform.txt to pass new mmu options through to compiler and linker preprocessor. Added quick example: esp8266/MMU48K --- boards.txt | 567 ++++++++++++------ bootloaders/eboot/eboot.c | 2 +- bootloaders/eboot/eboot.elf | Bin 34956 -> 34956 bytes cores/esp8266/core_esp8266_features.cpp | 28 + cores/esp8266/core_esp8266_features.h | 3 + libraries/esp8266/examples/MMU48K/MMU48K.ino | 98 +++ platform.txt | 10 +- tools/boards.txt.py | 18 +- ...lash.16m14m.ld => eagle.flash.16m14m.ld.h} | 2 +- ...lash.16m15m.ld => eagle.flash.16m15m.ld.h} | 2 +- ...{eagle.flash.1m.ld => eagle.flash.1m.ld.h} | 2 +- ....flash.1m128.ld => eagle.flash.1m128.ld.h} | 2 +- ....flash.1m144.ld => eagle.flash.1m144.ld.h} | 2 +- ....flash.1m160.ld => eagle.flash.1m160.ld.h} | 2 +- ....flash.1m192.ld => eagle.flash.1m192.ld.h} | 2 +- ....flash.1m256.ld => eagle.flash.1m256.ld.h} | 2 +- ....flash.1m512.ld => eagle.flash.1m512.ld.h} | 2 +- ...le.flash.1m64.ld => eagle.flash.1m64.ld.h} | 2 +- ...{eagle.flash.2m.ld => eagle.flash.2m.ld.h} | 2 +- ....flash.2m128.ld => eagle.flash.2m128.ld.h} | 2 +- ...le.flash.2m1m.ld => eagle.flash.2m1m.ld.h} | 2 +- ....flash.2m256.ld => eagle.flash.2m256.ld.h} | 2 +- ....flash.2m512.ld => eagle.flash.2m512.ld.h} | 2 +- ...le.flash.2m64.ld => eagle.flash.2m64.ld.h} | 2 +- ...{eagle.flash.4m.ld => eagle.flash.4m.ld.h} | 2 +- ...le.flash.4m1m.ld => eagle.flash.4m1m.ld.h} | 2 +- ...le.flash.4m2m.ld => eagle.flash.4m2m.ld.h} | 2 +- ...le.flash.4m3m.ld => eagle.flash.4m3m.ld.h} | 2 +- ...le.flash.512k.ld => eagle.flash.512k.ld.h} | 2 +- ...sh.512k128.ld => eagle.flash.512k128.ld.h} | 2 +- ...lash.512k32.ld => eagle.flash.512k32.ld.h} | 2 +- ...lash.512k64.ld => eagle.flash.512k64.ld.h} | 2 +- ...le.flash.8m6m.ld => eagle.flash.8m6m.ld.h} | 2 +- ...le.flash.8m7m.ld => eagle.flash.8m7m.ld.h} | 2 +- 34 files changed, 560 insertions(+), 218 deletions(-) create mode 100644 libraries/esp8266/examples/MMU48K/MMU48K.ino rename tools/sdk/ld/{eagle.flash.16m14m.ld => eagle.flash.16m14m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.16m15m.ld => eagle.flash.16m15m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.1m.ld => eagle.flash.1m.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m128.ld => eagle.flash.1m128.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m144.ld => eagle.flash.1m144.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m160.ld => eagle.flash.1m160.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m192.ld => eagle.flash.1m192.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m256.ld => eagle.flash.1m256.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m512.ld => eagle.flash.1m512.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.1m64.ld => eagle.flash.1m64.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.2m.ld => eagle.flash.2m.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.2m128.ld => eagle.flash.2m128.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.2m1m.ld => eagle.flash.2m1m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.2m256.ld => eagle.flash.2m256.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.2m512.ld => eagle.flash.2m512.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.2m64.ld => eagle.flash.2m64.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.4m.ld => eagle.flash.4m.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.4m1m.ld => eagle.flash.4m1m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.4m2m.ld => eagle.flash.4m2m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.4m3m.ld => eagle.flash.4m3m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.512k.ld => eagle.flash.512k.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.512k128.ld => eagle.flash.512k128.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.512k32.ld => eagle.flash.512k32.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.512k64.ld => eagle.flash.512k64.ld.h} (98%) rename tools/sdk/ld/{eagle.flash.8m6m.ld => eagle.flash.8m6m.ld.h} (99%) rename tools/sdk/ld/{eagle.flash.8m7m.ld => eagle.flash.8m7m.ld.h} (99%) diff --git a/boards.txt b/boards.txt index df56b79807..26ce96fb50 100644 --- a/boards.txt +++ b/boards.txt @@ -22,6 +22,7 @@ menu.exception=Exceptions menu.wipe=Erase Flash menu.sdk=Espressif FW menu.ssl=SSL Support +menu.mmu=MMU ############################################################## generic.name=Generic ESP8266 Module @@ -61,6 +62,12 @@ generic.menu.ssl.all=All SSL ciphers (most compatible) generic.menu.ssl.all.build.sslflags= generic.menu.ssl.basic=Basic SSL ciphers (lower ROM use) generic.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +generic.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +generic.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +generic.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +generic.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +generic.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 generic.menu.ResetMethod.nodemcu=dtr (aka nodemcu) generic.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset generic.menu.ResetMethod.ck=no dtr (aka ck) @@ -93,7 +100,7 @@ generic.menu.FlashMode.qio.build.flash_flags=-DFLASHMODE_QIO generic.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) generic.menu.eesz.1M64.build.flash_size=1M generic.menu.eesz.1M64.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +generic.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h generic.menu.eesz.1M64.build.spiffs_pagesize=256 generic.menu.eesz.1M64.upload.maximum_size=958448 generic.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -103,7 +110,7 @@ generic.menu.eesz.1M64.build.spiffs_blocksize=4096 generic.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) generic.menu.eesz.1M128.build.flash_size=1M generic.menu.eesz.1M128.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +generic.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h generic.menu.eesz.1M128.build.spiffs_pagesize=256 generic.menu.eesz.1M128.upload.maximum_size=892912 generic.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -113,7 +120,7 @@ generic.menu.eesz.1M128.build.spiffs_blocksize=4096 generic.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) generic.menu.eesz.1M144.build.flash_size=1M generic.menu.eesz.1M144.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +generic.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h generic.menu.eesz.1M144.build.spiffs_pagesize=256 generic.menu.eesz.1M144.upload.maximum_size=876528 generic.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -123,7 +130,7 @@ generic.menu.eesz.1M144.build.spiffs_blocksize=4096 generic.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) generic.menu.eesz.1M160.build.flash_size=1M generic.menu.eesz.1M160.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +generic.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h generic.menu.eesz.1M160.build.spiffs_pagesize=256 generic.menu.eesz.1M160.upload.maximum_size=860144 generic.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -133,7 +140,7 @@ generic.menu.eesz.1M160.build.spiffs_blocksize=4096 generic.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) generic.menu.eesz.1M192.build.flash_size=1M generic.menu.eesz.1M192.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +generic.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h generic.menu.eesz.1M192.build.spiffs_pagesize=256 generic.menu.eesz.1M192.upload.maximum_size=827376 generic.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -143,7 +150,7 @@ generic.menu.eesz.1M192.build.spiffs_blocksize=4096 generic.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) generic.menu.eesz.1M256.build.flash_size=1M generic.menu.eesz.1M256.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +generic.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h generic.menu.eesz.1M256.build.spiffs_pagesize=256 generic.menu.eesz.1M256.upload.maximum_size=761840 generic.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -153,7 +160,7 @@ generic.menu.eesz.1M256.build.spiffs_blocksize=4096 generic.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) generic.menu.eesz.1M512.build.flash_size=1M generic.menu.eesz.1M512.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +generic.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h generic.menu.eesz.1M512.build.spiffs_pagesize=256 generic.menu.eesz.1M512.upload.maximum_size=499696 generic.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -163,14 +170,14 @@ generic.menu.eesz.1M512.build.spiffs_blocksize=8192 generic.menu.eesz.1M=1MB (FS:none OTA:~502KB) generic.menu.eesz.1M.build.flash_size=1M generic.menu.eesz.1M.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +generic.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h generic.menu.eesz.1M.build.spiffs_pagesize=256 generic.menu.eesz.1M.upload.maximum_size=1023984 generic.menu.eesz.1M.build.rfcal_addr=0xFC000 generic.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) generic.menu.eesz.2M64.build.flash_size=2M generic.menu.eesz.2M64.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld +generic.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h generic.menu.eesz.2M64.build.spiffs_pagesize=256 generic.menu.eesz.2M64.upload.maximum_size=1044464 generic.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -180,7 +187,7 @@ generic.menu.eesz.2M64.build.spiffs_blocksize=4096 generic.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) generic.menu.eesz.2M128.build.flash_size=2M generic.menu.eesz.2M128.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld +generic.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h generic.menu.eesz.2M128.build.spiffs_pagesize=256 generic.menu.eesz.2M128.upload.maximum_size=1044464 generic.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -190,7 +197,7 @@ generic.menu.eesz.2M128.build.spiffs_blocksize=4096 generic.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) generic.menu.eesz.2M256.build.flash_size=2M generic.menu.eesz.2M256.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld +generic.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h generic.menu.eesz.2M256.build.spiffs_pagesize=256 generic.menu.eesz.2M256.upload.maximum_size=1044464 generic.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -200,7 +207,7 @@ generic.menu.eesz.2M256.build.spiffs_blocksize=4096 generic.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) generic.menu.eesz.2M512.build.flash_size=2M generic.menu.eesz.2M512.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld +generic.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h generic.menu.eesz.2M512.build.spiffs_pagesize=256 generic.menu.eesz.2M512.upload.maximum_size=1044464 generic.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -210,7 +217,7 @@ generic.menu.eesz.2M512.build.spiffs_blocksize=8192 generic.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) generic.menu.eesz.2M1M.build.flash_size=2M generic.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld +generic.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h generic.menu.eesz.2M1M.build.spiffs_pagesize=256 generic.menu.eesz.2M1M.upload.maximum_size=1044464 generic.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -220,14 +227,14 @@ generic.menu.eesz.2M1M.build.spiffs_blocksize=8192 generic.menu.eesz.2M=2MB (FS:none OTA:~1019KB) generic.menu.eesz.2M.build.flash_size=2M generic.menu.eesz.2M.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld +generic.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h generic.menu.eesz.2M.build.spiffs_pagesize=256 generic.menu.eesz.2M.upload.maximum_size=1044464 generic.menu.eesz.2M.build.rfcal_addr=0x1FC000 generic.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) generic.menu.eesz.4M2M.build.flash_size=4M generic.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +generic.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h generic.menu.eesz.4M2M.build.spiffs_pagesize=256 generic.menu.eesz.4M2M.upload.maximum_size=1044464 generic.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -237,7 +244,7 @@ generic.menu.eesz.4M2M.build.spiffs_blocksize=8192 generic.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) generic.menu.eesz.4M3M.build.flash_size=4M generic.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +generic.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h generic.menu.eesz.4M3M.build.spiffs_pagesize=256 generic.menu.eesz.4M3M.upload.maximum_size=1044464 generic.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -247,7 +254,7 @@ generic.menu.eesz.4M3M.build.spiffs_blocksize=8192 generic.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) generic.menu.eesz.4M1M.build.flash_size=4M generic.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +generic.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h generic.menu.eesz.4M1M.build.spiffs_pagesize=256 generic.menu.eesz.4M1M.upload.maximum_size=1044464 generic.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -257,14 +264,14 @@ generic.menu.eesz.4M1M.build.spiffs_blocksize=8192 generic.menu.eesz.4M=4MB (FS:none OTA:~1019KB) generic.menu.eesz.4M.build.flash_size=4M generic.menu.eesz.4M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +generic.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h generic.menu.eesz.4M.build.spiffs_pagesize=256 generic.menu.eesz.4M.upload.maximum_size=1044464 generic.menu.eesz.4M.build.rfcal_addr=0x3FC000 generic.menu.eesz.8M6M=8MB (FS:6MB OTA:~1019KB) generic.menu.eesz.8M6M.build.flash_size=8M generic.menu.eesz.8M6M.build.flash_size_bytes=0x800000 -generic.menu.eesz.8M6M.build.flash_ld=eagle.flash.8m6m.ld +generic.menu.eesz.8M6M.build.flash_ld=eagle.flash.8m6m.ld.h generic.menu.eesz.8M6M.build.spiffs_pagesize=256 generic.menu.eesz.8M6M.upload.maximum_size=1044464 generic.menu.eesz.8M6M.build.rfcal_addr=0x7FC000 @@ -274,7 +281,7 @@ generic.menu.eesz.8M6M.build.spiffs_blocksize=8192 generic.menu.eesz.8M7M=8MB (FS:7MB OTA:~512KB) generic.menu.eesz.8M7M.build.flash_size=8M generic.menu.eesz.8M7M.build.flash_size_bytes=0x800000 -generic.menu.eesz.8M7M.build.flash_ld=eagle.flash.8m7m.ld +generic.menu.eesz.8M7M.build.flash_ld=eagle.flash.8m7m.ld.h generic.menu.eesz.8M7M.build.spiffs_pagesize=256 generic.menu.eesz.8M7M.upload.maximum_size=1044464 generic.menu.eesz.8M7M.build.rfcal_addr=0x7FC000 @@ -284,7 +291,7 @@ generic.menu.eesz.8M7M.build.spiffs_blocksize=8192 generic.menu.eesz.16M14M=16MB (FS:14MB OTA:~1019KB) generic.menu.eesz.16M14M.build.flash_size=16M generic.menu.eesz.16M14M.build.flash_size_bytes=0x1000000 -generic.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld +generic.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld.h generic.menu.eesz.16M14M.build.spiffs_pagesize=256 generic.menu.eesz.16M14M.upload.maximum_size=1044464 generic.menu.eesz.16M14M.build.rfcal_addr=0xFFC000 @@ -294,7 +301,7 @@ generic.menu.eesz.16M14M.build.spiffs_blocksize=8192 generic.menu.eesz.16M15M=16MB (FS:15MB OTA:~512KB) generic.menu.eesz.16M15M.build.flash_size=16M generic.menu.eesz.16M15M.build.flash_size_bytes=0x1000000 -generic.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld +generic.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld.h generic.menu.eesz.16M15M.build.spiffs_pagesize=256 generic.menu.eesz.16M15M.upload.maximum_size=1044464 generic.menu.eesz.16M15M.build.rfcal_addr=0xFFC000 @@ -304,7 +311,7 @@ generic.menu.eesz.16M15M.build.spiffs_blocksize=8192 generic.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) generic.menu.eesz.512K32.build.flash_size=512K generic.menu.eesz.512K32.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld +generic.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h generic.menu.eesz.512K32.build.spiffs_pagesize=256 generic.menu.eesz.512K32.upload.maximum_size=466928 generic.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -314,7 +321,7 @@ generic.menu.eesz.512K32.build.spiffs_blocksize=4096 generic.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) generic.menu.eesz.512K64.build.flash_size=512K generic.menu.eesz.512K64.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld +generic.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h generic.menu.eesz.512K64.build.spiffs_pagesize=256 generic.menu.eesz.512K64.upload.maximum_size=434160 generic.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -324,7 +331,7 @@ generic.menu.eesz.512K64.build.spiffs_blocksize=4096 generic.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) generic.menu.eesz.512K128.build.flash_size=512K generic.menu.eesz.512K128.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld +generic.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h generic.menu.eesz.512K128.build.spiffs_pagesize=256 generic.menu.eesz.512K128.upload.maximum_size=368624 generic.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -334,7 +341,7 @@ generic.menu.eesz.512K128.build.spiffs_blocksize=4096 generic.menu.eesz.512K=512KB (FS:none OTA:~246KB) generic.menu.eesz.512K.build.flash_size=512K generic.menu.eesz.512K.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld +generic.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h generic.menu.eesz.512K.build.spiffs_pagesize=256 generic.menu.eesz.512K.upload.maximum_size=499696 generic.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -536,6 +543,12 @@ esp8285.menu.ssl.all=All SSL ciphers (most compatible) esp8285.menu.ssl.all.build.sslflags= esp8285.menu.ssl.basic=Basic SSL ciphers (lower ROM use) esp8285.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +esp8285.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +esp8285.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +esp8285.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +esp8285.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +esp8285.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 esp8285.menu.ResetMethod.nodemcu=dtr (aka nodemcu) esp8285.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset esp8285.menu.ResetMethod.ck=no dtr (aka ck) @@ -551,7 +564,7 @@ esp8285.build.flash_freq=40 esp8285.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) esp8285.menu.eesz.1M64.build.flash_size=1M esp8285.menu.eesz.1M64.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +esp8285.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h esp8285.menu.eesz.1M64.build.spiffs_pagesize=256 esp8285.menu.eesz.1M64.upload.maximum_size=958448 esp8285.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -561,7 +574,7 @@ esp8285.menu.eesz.1M64.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) esp8285.menu.eesz.1M128.build.flash_size=1M esp8285.menu.eesz.1M128.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +esp8285.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h esp8285.menu.eesz.1M128.build.spiffs_pagesize=256 esp8285.menu.eesz.1M128.upload.maximum_size=892912 esp8285.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -571,7 +584,7 @@ esp8285.menu.eesz.1M128.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) esp8285.menu.eesz.1M144.build.flash_size=1M esp8285.menu.eesz.1M144.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +esp8285.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h esp8285.menu.eesz.1M144.build.spiffs_pagesize=256 esp8285.menu.eesz.1M144.upload.maximum_size=876528 esp8285.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -581,7 +594,7 @@ esp8285.menu.eesz.1M144.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) esp8285.menu.eesz.1M160.build.flash_size=1M esp8285.menu.eesz.1M160.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +esp8285.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h esp8285.menu.eesz.1M160.build.spiffs_pagesize=256 esp8285.menu.eesz.1M160.upload.maximum_size=860144 esp8285.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -591,7 +604,7 @@ esp8285.menu.eesz.1M160.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) esp8285.menu.eesz.1M192.build.flash_size=1M esp8285.menu.eesz.1M192.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +esp8285.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h esp8285.menu.eesz.1M192.build.spiffs_pagesize=256 esp8285.menu.eesz.1M192.upload.maximum_size=827376 esp8285.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -601,7 +614,7 @@ esp8285.menu.eesz.1M192.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) esp8285.menu.eesz.1M256.build.flash_size=1M esp8285.menu.eesz.1M256.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +esp8285.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h esp8285.menu.eesz.1M256.build.spiffs_pagesize=256 esp8285.menu.eesz.1M256.upload.maximum_size=761840 esp8285.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -611,7 +624,7 @@ esp8285.menu.eesz.1M256.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) esp8285.menu.eesz.1M512.build.flash_size=1M esp8285.menu.eesz.1M512.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +esp8285.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h esp8285.menu.eesz.1M512.build.spiffs_pagesize=256 esp8285.menu.eesz.1M512.upload.maximum_size=499696 esp8285.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -621,7 +634,7 @@ esp8285.menu.eesz.1M512.build.spiffs_blocksize=8192 esp8285.menu.eesz.1M=1MB (FS:none OTA:~502KB) esp8285.menu.eesz.1M.build.flash_size=1M esp8285.menu.eesz.1M.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +esp8285.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h esp8285.menu.eesz.1M.build.spiffs_pagesize=256 esp8285.menu.eesz.1M.upload.maximum_size=1023984 esp8285.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -820,13 +833,19 @@ espduino.menu.ssl.all=All SSL ciphers (most compatible) espduino.menu.ssl.all.build.sslflags= espduino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espduino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espduino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espduino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espduino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espduino.build.flash_mode=dio espduino.build.flash_flags=-DFLASHMODE_DIO espduino.build.flash_freq=40 espduino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espduino.menu.eesz.4M2M.build.flash_size=4M espduino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espduino.menu.eesz.4M2M.build.spiffs_pagesize=256 espduino.menu.eesz.4M2M.upload.maximum_size=1044464 espduino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -836,7 +855,7 @@ espduino.menu.eesz.4M2M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espduino.menu.eesz.4M3M.build.flash_size=4M espduino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espduino.menu.eesz.4M3M.build.spiffs_pagesize=256 espduino.menu.eesz.4M3M.upload.maximum_size=1044464 espduino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -846,7 +865,7 @@ espduino.menu.eesz.4M3M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espduino.menu.eesz.4M1M.build.flash_size=4M espduino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espduino.menu.eesz.4M1M.build.spiffs_pagesize=256 espduino.menu.eesz.4M1M.upload.maximum_size=1044464 espduino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -856,7 +875,7 @@ espduino.menu.eesz.4M1M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espduino.menu.eesz.4M.build.flash_size=4M espduino.menu.eesz.4M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espduino.menu.eesz.4M.build.spiffs_pagesize=256 espduino.menu.eesz.4M.upload.maximum_size=1044464 espduino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1012,6 +1031,12 @@ huzzah.menu.ssl.all=All SSL ciphers (most compatible) huzzah.menu.ssl.all.build.sslflags= huzzah.menu.ssl.basic=Basic SSL ciphers (lower ROM use) huzzah.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +huzzah.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +huzzah.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +huzzah.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +huzzah.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +huzzah.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 huzzah.upload.resetmethod=--before default_reset --after hard_reset huzzah.build.flash_mode=qio huzzah.build.flash_flags=-DFLASHMODE_QIO @@ -1019,7 +1044,7 @@ huzzah.build.flash_freq=40 huzzah.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) huzzah.menu.eesz.4M2M.build.flash_size=4M huzzah.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +huzzah.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h huzzah.menu.eesz.4M2M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M2M.upload.maximum_size=1044464 huzzah.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1029,7 +1054,7 @@ huzzah.menu.eesz.4M2M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) huzzah.menu.eesz.4M3M.build.flash_size=4M huzzah.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +huzzah.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h huzzah.menu.eesz.4M3M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M3M.upload.maximum_size=1044464 huzzah.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1039,7 +1064,7 @@ huzzah.menu.eesz.4M3M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) huzzah.menu.eesz.4M1M.build.flash_size=4M huzzah.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +huzzah.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h huzzah.menu.eesz.4M1M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M1M.upload.maximum_size=1044464 huzzah.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1049,7 +1074,7 @@ huzzah.menu.eesz.4M1M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M=4MB (FS:none OTA:~1019KB) huzzah.menu.eesz.4M.build.flash_size=4M huzzah.menu.eesz.4M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +huzzah.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h huzzah.menu.eesz.4M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M.upload.maximum_size=1044464 huzzah.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1205,6 +1230,12 @@ inventone.menu.ssl.all=All SSL ciphers (most compatible) inventone.menu.ssl.all.build.sslflags= inventone.menu.ssl.basic=Basic SSL ciphers (lower ROM use) inventone.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +inventone.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +inventone.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +inventone.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +inventone.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +inventone.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 inventone.upload.resetmethod=--before default_reset --after hard_reset inventone.build.flash_mode=dio inventone.build.flash_flags=-DFLASHMODE_DIO @@ -1212,7 +1243,7 @@ inventone.build.flash_freq=40 inventone.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) inventone.menu.eesz.4M2M.build.flash_size=4M inventone.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +inventone.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h inventone.menu.eesz.4M2M.build.spiffs_pagesize=256 inventone.menu.eesz.4M2M.upload.maximum_size=1044464 inventone.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1222,7 +1253,7 @@ inventone.menu.eesz.4M2M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) inventone.menu.eesz.4M3M.build.flash_size=4M inventone.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +inventone.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h inventone.menu.eesz.4M3M.build.spiffs_pagesize=256 inventone.menu.eesz.4M3M.upload.maximum_size=1044464 inventone.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1232,7 +1263,7 @@ inventone.menu.eesz.4M3M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) inventone.menu.eesz.4M1M.build.flash_size=4M inventone.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +inventone.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h inventone.menu.eesz.4M1M.build.spiffs_pagesize=256 inventone.menu.eesz.4M1M.upload.maximum_size=1044464 inventone.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1242,7 +1273,7 @@ inventone.menu.eesz.4M1M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M=4MB (FS:none OTA:~1019KB) inventone.menu.eesz.4M.build.flash_size=4M inventone.menu.eesz.4M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +inventone.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h inventone.menu.eesz.4M.build.spiffs_pagesize=256 inventone.menu.eesz.4M.upload.maximum_size=1044464 inventone.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1398,6 +1429,12 @@ cw01.menu.ssl.all=All SSL ciphers (most compatible) cw01.menu.ssl.all.build.sslflags= cw01.menu.ssl.basic=Basic SSL ciphers (lower ROM use) cw01.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +cw01.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +cw01.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +cw01.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +cw01.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +cw01.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 cw01.upload.resetmethod=--before default_reset --after hard_reset cw01.menu.CrystalFreq.26=26 MHz cw01.menu.CrystalFreq.40=40 MHz @@ -1408,7 +1445,7 @@ cw01.build.flash_freq=40 cw01.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) cw01.menu.eesz.4M2M.build.flash_size=4M cw01.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +cw01.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h cw01.menu.eesz.4M2M.build.spiffs_pagesize=256 cw01.menu.eesz.4M2M.upload.maximum_size=1044464 cw01.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1418,7 +1455,7 @@ cw01.menu.eesz.4M2M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) cw01.menu.eesz.4M3M.build.flash_size=4M cw01.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +cw01.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h cw01.menu.eesz.4M3M.build.spiffs_pagesize=256 cw01.menu.eesz.4M3M.upload.maximum_size=1044464 cw01.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1428,7 +1465,7 @@ cw01.menu.eesz.4M3M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) cw01.menu.eesz.4M1M.build.flash_size=4M cw01.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +cw01.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h cw01.menu.eesz.4M1M.build.spiffs_pagesize=256 cw01.menu.eesz.4M1M.upload.maximum_size=1044464 cw01.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1438,7 +1475,7 @@ cw01.menu.eesz.4M1M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M=4MB (FS:none OTA:~1019KB) cw01.menu.eesz.4M.build.flash_size=4M cw01.menu.eesz.4M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +cw01.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h cw01.menu.eesz.4M.build.spiffs_pagesize=256 cw01.menu.eesz.4M.upload.maximum_size=1044464 cw01.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1594,13 +1631,19 @@ espresso_lite_v1.menu.ssl.all=All SSL ciphers (most compatible) espresso_lite_v1.menu.ssl.all.build.sslflags= espresso_lite_v1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espresso_lite_v1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espresso_lite_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espresso_lite_v1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espresso_lite_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espresso_lite_v1.build.flash_mode=dio espresso_lite_v1.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v1.build.flash_freq=40 espresso_lite_v1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espresso_lite_v1.menu.eesz.4M2M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espresso_lite_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espresso_lite_v1.menu.eesz.4M2M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M2M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1610,7 +1653,7 @@ espresso_lite_v1.menu.eesz.4M2M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espresso_lite_v1.menu.eesz.4M3M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espresso_lite_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espresso_lite_v1.menu.eesz.4M3M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M3M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1620,7 +1663,7 @@ espresso_lite_v1.menu.eesz.4M3M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espresso_lite_v1.menu.eesz.4M1M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espresso_lite_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espresso_lite_v1.menu.eesz.4M1M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M1M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1630,7 +1673,7 @@ espresso_lite_v1.menu.eesz.4M1M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espresso_lite_v1.menu.eesz.4M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espresso_lite_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espresso_lite_v1.menu.eesz.4M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1790,13 +1833,19 @@ espresso_lite_v2.menu.ssl.all=All SSL ciphers (most compatible) espresso_lite_v2.menu.ssl.all.build.sslflags= espresso_lite_v2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espresso_lite_v2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espresso_lite_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espresso_lite_v2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espresso_lite_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espresso_lite_v2.build.flash_mode=dio espresso_lite_v2.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v2.build.flash_freq=40 espresso_lite_v2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espresso_lite_v2.menu.eesz.4M2M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espresso_lite_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espresso_lite_v2.menu.eesz.4M2M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M2M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1806,7 +1855,7 @@ espresso_lite_v2.menu.eesz.4M2M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espresso_lite_v2.menu.eesz.4M3M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espresso_lite_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espresso_lite_v2.menu.eesz.4M3M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M3M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1816,7 +1865,7 @@ espresso_lite_v2.menu.eesz.4M3M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espresso_lite_v2.menu.eesz.4M1M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espresso_lite_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espresso_lite_v2.menu.eesz.4M1M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M1M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1826,7 +1875,7 @@ espresso_lite_v2.menu.eesz.4M1M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espresso_lite_v2.menu.eesz.4M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espresso_lite_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espresso_lite_v2.menu.eesz.4M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1986,13 +2035,19 @@ phoenix_v1.menu.ssl.all=All SSL ciphers (most compatible) phoenix_v1.menu.ssl.all.build.sslflags= phoenix_v1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) phoenix_v1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +phoenix_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +phoenix_v1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +phoenix_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +phoenix_v1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +phoenix_v1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 phoenix_v1.build.flash_mode=dio phoenix_v1.build.flash_flags=-DFLASHMODE_DIO phoenix_v1.build.flash_freq=40 phoenix_v1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) phoenix_v1.menu.eesz.4M2M.build.flash_size=4M phoenix_v1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +phoenix_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h phoenix_v1.menu.eesz.4M2M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M2M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2002,7 +2057,7 @@ phoenix_v1.menu.eesz.4M2M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) phoenix_v1.menu.eesz.4M3M.build.flash_size=4M phoenix_v1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +phoenix_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h phoenix_v1.menu.eesz.4M3M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M3M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2012,7 +2067,7 @@ phoenix_v1.menu.eesz.4M3M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) phoenix_v1.menu.eesz.4M1M.build.flash_size=4M phoenix_v1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +phoenix_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h phoenix_v1.menu.eesz.4M1M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M1M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2022,7 +2077,7 @@ phoenix_v1.menu.eesz.4M1M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) phoenix_v1.menu.eesz.4M.build.flash_size=4M phoenix_v1.menu.eesz.4M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +phoenix_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h phoenix_v1.menu.eesz.4M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2182,13 +2237,19 @@ phoenix_v2.menu.ssl.all=All SSL ciphers (most compatible) phoenix_v2.menu.ssl.all.build.sslflags= phoenix_v2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) phoenix_v2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +phoenix_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +phoenix_v2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +phoenix_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +phoenix_v2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +phoenix_v2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 phoenix_v2.build.flash_mode=dio phoenix_v2.build.flash_flags=-DFLASHMODE_DIO phoenix_v2.build.flash_freq=40 phoenix_v2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) phoenix_v2.menu.eesz.4M2M.build.flash_size=4M phoenix_v2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +phoenix_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h phoenix_v2.menu.eesz.4M2M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M2M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2198,7 +2259,7 @@ phoenix_v2.menu.eesz.4M2M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) phoenix_v2.menu.eesz.4M3M.build.flash_size=4M phoenix_v2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +phoenix_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h phoenix_v2.menu.eesz.4M3M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M3M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2208,7 +2269,7 @@ phoenix_v2.menu.eesz.4M3M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) phoenix_v2.menu.eesz.4M1M.build.flash_size=4M phoenix_v2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +phoenix_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h phoenix_v2.menu.eesz.4M1M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M1M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2218,7 +2279,7 @@ phoenix_v2.menu.eesz.4M1M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) phoenix_v2.menu.eesz.4M.build.flash_size=4M phoenix_v2.menu.eesz.4M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +phoenix_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h phoenix_v2.menu.eesz.4M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2378,6 +2439,12 @@ nodemcu.menu.ssl.all=All SSL ciphers (most compatible) nodemcu.menu.ssl.all.build.sslflags= nodemcu.menu.ssl.basic=Basic SSL ciphers (lower ROM use) nodemcu.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +nodemcu.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +nodemcu.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +nodemcu.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +nodemcu.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +nodemcu.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 nodemcu.upload.resetmethod=--before default_reset --after hard_reset nodemcu.build.flash_mode=qio nodemcu.build.flash_flags=-DFLASHMODE_QIO @@ -2385,7 +2452,7 @@ nodemcu.build.flash_freq=40 nodemcu.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) nodemcu.menu.eesz.4M2M.build.flash_size=4M nodemcu.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +nodemcu.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h nodemcu.menu.eesz.4M2M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M2M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2395,7 +2462,7 @@ nodemcu.menu.eesz.4M2M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) nodemcu.menu.eesz.4M3M.build.flash_size=4M nodemcu.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +nodemcu.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h nodemcu.menu.eesz.4M3M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M3M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2405,7 +2472,7 @@ nodemcu.menu.eesz.4M3M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) nodemcu.menu.eesz.4M1M.build.flash_size=4M nodemcu.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +nodemcu.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h nodemcu.menu.eesz.4M1M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M1M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2415,7 +2482,7 @@ nodemcu.menu.eesz.4M1M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M=4MB (FS:none OTA:~1019KB) nodemcu.menu.eesz.4M.build.flash_size=4M nodemcu.menu.eesz.4M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +nodemcu.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h nodemcu.menu.eesz.4M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2571,6 +2638,12 @@ nodemcuv2.menu.ssl.all=All SSL ciphers (most compatible) nodemcuv2.menu.ssl.all.build.sslflags= nodemcuv2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) nodemcuv2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +nodemcuv2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +nodemcuv2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +nodemcuv2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +nodemcuv2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +nodemcuv2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 nodemcuv2.upload.resetmethod=--before default_reset --after hard_reset nodemcuv2.build.flash_mode=dio nodemcuv2.build.flash_flags=-DFLASHMODE_DIO @@ -2578,7 +2651,7 @@ nodemcuv2.build.flash_freq=40 nodemcuv2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) nodemcuv2.menu.eesz.4M2M.build.flash_size=4M nodemcuv2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +nodemcuv2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h nodemcuv2.menu.eesz.4M2M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M2M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2588,7 +2661,7 @@ nodemcuv2.menu.eesz.4M2M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) nodemcuv2.menu.eesz.4M3M.build.flash_size=4M nodemcuv2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +nodemcuv2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h nodemcuv2.menu.eesz.4M3M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M3M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2598,7 +2671,7 @@ nodemcuv2.menu.eesz.4M3M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) nodemcuv2.menu.eesz.4M1M.build.flash_size=4M nodemcuv2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +nodemcuv2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h nodemcuv2.menu.eesz.4M1M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M1M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2608,7 +2681,7 @@ nodemcuv2.menu.eesz.4M1M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) nodemcuv2.menu.eesz.4M.build.flash_size=4M nodemcuv2.menu.eesz.4M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +nodemcuv2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h nodemcuv2.menu.eesz.4M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2768,6 +2841,12 @@ modwifi.menu.ssl.all=All SSL ciphers (most compatible) modwifi.menu.ssl.all.build.sslflags= modwifi.menu.ssl.basic=Basic SSL ciphers (lower ROM use) modwifi.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +modwifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +modwifi.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +modwifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +modwifi.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +modwifi.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 modwifi.upload.resetmethod=--before no_reset --after soft_reset modwifi.build.flash_mode=qio modwifi.build.flash_flags=-DFLASHMODE_QIO @@ -2775,7 +2854,7 @@ modwifi.build.flash_freq=40 modwifi.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) modwifi.menu.eesz.2M64.build.flash_size=2M modwifi.menu.eesz.2M64.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld +modwifi.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h modwifi.menu.eesz.2M64.build.spiffs_pagesize=256 modwifi.menu.eesz.2M64.upload.maximum_size=1044464 modwifi.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -2785,7 +2864,7 @@ modwifi.menu.eesz.2M64.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) modwifi.menu.eesz.2M128.build.flash_size=2M modwifi.menu.eesz.2M128.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld +modwifi.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h modwifi.menu.eesz.2M128.build.spiffs_pagesize=256 modwifi.menu.eesz.2M128.upload.maximum_size=1044464 modwifi.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -2795,7 +2874,7 @@ modwifi.menu.eesz.2M128.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) modwifi.menu.eesz.2M256.build.flash_size=2M modwifi.menu.eesz.2M256.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld +modwifi.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h modwifi.menu.eesz.2M256.build.spiffs_pagesize=256 modwifi.menu.eesz.2M256.upload.maximum_size=1044464 modwifi.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -2805,7 +2884,7 @@ modwifi.menu.eesz.2M256.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) modwifi.menu.eesz.2M512.build.flash_size=2M modwifi.menu.eesz.2M512.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld +modwifi.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h modwifi.menu.eesz.2M512.build.spiffs_pagesize=256 modwifi.menu.eesz.2M512.upload.maximum_size=1044464 modwifi.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -2815,7 +2894,7 @@ modwifi.menu.eesz.2M512.build.spiffs_blocksize=8192 modwifi.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) modwifi.menu.eesz.2M1M.build.flash_size=2M modwifi.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld +modwifi.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h modwifi.menu.eesz.2M1M.build.spiffs_pagesize=256 modwifi.menu.eesz.2M1M.upload.maximum_size=1044464 modwifi.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -2825,7 +2904,7 @@ modwifi.menu.eesz.2M1M.build.spiffs_blocksize=8192 modwifi.menu.eesz.2M=2MB (FS:none OTA:~1019KB) modwifi.menu.eesz.2M.build.flash_size=2M modwifi.menu.eesz.2M.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld +modwifi.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h modwifi.menu.eesz.2M.build.spiffs_pagesize=256 modwifi.menu.eesz.2M.upload.maximum_size=1044464 modwifi.menu.eesz.2M.build.rfcal_addr=0x1FC000 @@ -2981,6 +3060,12 @@ thing.menu.ssl.all=All SSL ciphers (most compatible) thing.menu.ssl.all.build.sslflags= thing.menu.ssl.basic=Basic SSL ciphers (lower ROM use) thing.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +thing.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +thing.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +thing.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +thing.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +thing.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 thing.upload.resetmethod=--before no_reset --after soft_reset thing.build.flash_mode=qio thing.build.flash_flags=-DFLASHMODE_QIO @@ -2988,7 +3073,7 @@ thing.build.flash_freq=40 thing.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) thing.menu.eesz.512K32.build.flash_size=512K thing.menu.eesz.512K32.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld +thing.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h thing.menu.eesz.512K32.build.spiffs_pagesize=256 thing.menu.eesz.512K32.upload.maximum_size=466928 thing.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -2998,7 +3083,7 @@ thing.menu.eesz.512K32.build.spiffs_blocksize=4096 thing.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) thing.menu.eesz.512K64.build.flash_size=512K thing.menu.eesz.512K64.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld +thing.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h thing.menu.eesz.512K64.build.spiffs_pagesize=256 thing.menu.eesz.512K64.upload.maximum_size=434160 thing.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -3008,7 +3093,7 @@ thing.menu.eesz.512K64.build.spiffs_blocksize=4096 thing.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) thing.menu.eesz.512K128.build.flash_size=512K thing.menu.eesz.512K128.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld +thing.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h thing.menu.eesz.512K128.build.spiffs_pagesize=256 thing.menu.eesz.512K128.upload.maximum_size=368624 thing.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -3018,7 +3103,7 @@ thing.menu.eesz.512K128.build.spiffs_blocksize=4096 thing.menu.eesz.512K=512KB (FS:none OTA:~246KB) thing.menu.eesz.512K.build.flash_size=512K thing.menu.eesz.512K.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld +thing.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h thing.menu.eesz.512K.build.spiffs_pagesize=256 thing.menu.eesz.512K.upload.maximum_size=499696 thing.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -3174,6 +3259,12 @@ thingdev.menu.ssl.all=All SSL ciphers (most compatible) thingdev.menu.ssl.all.build.sslflags= thingdev.menu.ssl.basic=Basic SSL ciphers (lower ROM use) thingdev.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +thingdev.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +thingdev.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +thingdev.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +thingdev.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +thingdev.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 thingdev.upload.resetmethod=--before default_reset --after hard_reset thingdev.build.flash_mode=dio thingdev.build.flash_flags=-DFLASHMODE_DIO @@ -3181,7 +3272,7 @@ thingdev.build.flash_freq=40 thingdev.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) thingdev.menu.eesz.512K32.build.flash_size=512K thingdev.menu.eesz.512K32.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld +thingdev.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h thingdev.menu.eesz.512K32.build.spiffs_pagesize=256 thingdev.menu.eesz.512K32.upload.maximum_size=466928 thingdev.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -3191,7 +3282,7 @@ thingdev.menu.eesz.512K32.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) thingdev.menu.eesz.512K64.build.flash_size=512K thingdev.menu.eesz.512K64.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld +thingdev.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h thingdev.menu.eesz.512K64.build.spiffs_pagesize=256 thingdev.menu.eesz.512K64.upload.maximum_size=434160 thingdev.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -3201,7 +3292,7 @@ thingdev.menu.eesz.512K64.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) thingdev.menu.eesz.512K128.build.flash_size=512K thingdev.menu.eesz.512K128.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld +thingdev.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h thingdev.menu.eesz.512K128.build.spiffs_pagesize=256 thingdev.menu.eesz.512K128.upload.maximum_size=368624 thingdev.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -3211,7 +3302,7 @@ thingdev.menu.eesz.512K128.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K=512KB (FS:none OTA:~246KB) thingdev.menu.eesz.512K.build.flash_size=512K thingdev.menu.eesz.512K.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld +thingdev.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h thingdev.menu.eesz.512K.build.spiffs_pagesize=256 thingdev.menu.eesz.512K.upload.maximum_size=499696 thingdev.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -3367,6 +3458,12 @@ blynk.menu.ssl.all=All SSL ciphers (most compatible) blynk.menu.ssl.all.build.sslflags= blynk.menu.ssl.basic=Basic SSL ciphers (lower ROM use) blynk.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +blynk.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +blynk.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +blynk.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +blynk.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +blynk.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 blynk.upload.resetmethod=--before default_reset --after hard_reset blynk.build.flash_mode=qio blynk.build.flash_flags=-DFLASHMODE_QIO @@ -3374,7 +3471,7 @@ blynk.build.flash_freq=40 blynk.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) blynk.menu.eesz.4M2M.build.flash_size=4M blynk.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +blynk.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h blynk.menu.eesz.4M2M.build.spiffs_pagesize=256 blynk.menu.eesz.4M2M.upload.maximum_size=1044464 blynk.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3384,7 +3481,7 @@ blynk.menu.eesz.4M2M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) blynk.menu.eesz.4M3M.build.flash_size=4M blynk.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +blynk.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h blynk.menu.eesz.4M3M.build.spiffs_pagesize=256 blynk.menu.eesz.4M3M.upload.maximum_size=1044464 blynk.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3394,7 +3491,7 @@ blynk.menu.eesz.4M3M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) blynk.menu.eesz.4M1M.build.flash_size=4M blynk.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +blynk.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h blynk.menu.eesz.4M1M.build.spiffs_pagesize=256 blynk.menu.eesz.4M1M.upload.maximum_size=1044464 blynk.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3404,7 +3501,7 @@ blynk.menu.eesz.4M1M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M=4MB (FS:none OTA:~1019KB) blynk.menu.eesz.4M.build.flash_size=4M blynk.menu.eesz.4M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +blynk.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h blynk.menu.eesz.4M.build.spiffs_pagesize=256 blynk.menu.eesz.4M.upload.maximum_size=1044464 blynk.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -3560,6 +3657,12 @@ esp210.menu.ssl.all=All SSL ciphers (most compatible) esp210.menu.ssl.all.build.sslflags= esp210.menu.ssl.basic=Basic SSL ciphers (lower ROM use) esp210.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +esp210.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +esp210.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +esp210.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +esp210.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +esp210.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 esp210.upload.resetmethod=--before no_reset --after soft_reset esp210.build.flash_mode=qio esp210.build.flash_flags=-DFLASHMODE_QIO @@ -3567,7 +3670,7 @@ esp210.build.flash_freq=40 esp210.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) esp210.menu.eesz.4M2M.build.flash_size=4M esp210.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +esp210.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h esp210.menu.eesz.4M2M.build.spiffs_pagesize=256 esp210.menu.eesz.4M2M.upload.maximum_size=1044464 esp210.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3577,7 +3680,7 @@ esp210.menu.eesz.4M2M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) esp210.menu.eesz.4M3M.build.flash_size=4M esp210.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +esp210.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h esp210.menu.eesz.4M3M.build.spiffs_pagesize=256 esp210.menu.eesz.4M3M.upload.maximum_size=1044464 esp210.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3587,7 +3690,7 @@ esp210.menu.eesz.4M3M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) esp210.menu.eesz.4M1M.build.flash_size=4M esp210.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +esp210.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h esp210.menu.eesz.4M1M.build.spiffs_pagesize=256 esp210.menu.eesz.4M1M.upload.maximum_size=1044464 esp210.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3597,7 +3700,7 @@ esp210.menu.eesz.4M1M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M=4MB (FS:none OTA:~1019KB) esp210.menu.eesz.4M.build.flash_size=4M esp210.menu.eesz.4M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +esp210.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h esp210.menu.eesz.4M.build.spiffs_pagesize=256 esp210.menu.eesz.4M.upload.maximum_size=1044464 esp210.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -3753,6 +3856,12 @@ d1_mini.menu.ssl.all=All SSL ciphers (most compatible) d1_mini.menu.ssl.all.build.sslflags= d1_mini.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +d1_mini.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +d1_mini.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +d1_mini.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 d1_mini.upload.resetmethod=--before default_reset --after hard_reset d1_mini.build.flash_mode=dio d1_mini.build.flash_flags=-DFLASHMODE_DIO @@ -3760,7 +3869,7 @@ d1_mini.build.flash_freq=40 d1_mini.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) d1_mini.menu.eesz.4M2M.build.flash_size=4M d1_mini.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +d1_mini.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h d1_mini.menu.eesz.4M2M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M2M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3770,7 +3879,7 @@ d1_mini.menu.eesz.4M2M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) d1_mini.menu.eesz.4M3M.build.flash_size=4M d1_mini.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +d1_mini.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h d1_mini.menu.eesz.4M3M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M3M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3780,7 +3889,7 @@ d1_mini.menu.eesz.4M3M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) d1_mini.menu.eesz.4M1M.build.flash_size=4M d1_mini.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +d1_mini.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h d1_mini.menu.eesz.4M1M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M1M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3790,7 +3899,7 @@ d1_mini.menu.eesz.4M1M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M=4MB (FS:none OTA:~1019KB) d1_mini.menu.eesz.4M.build.flash_size=4M d1_mini.menu.eesz.4M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +d1_mini.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h d1_mini.menu.eesz.4M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -3946,6 +4055,12 @@ d1_mini_pro.menu.ssl.all=All SSL ciphers (most compatible) d1_mini_pro.menu.ssl.all.build.sslflags= d1_mini_pro.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini_pro.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +d1_mini_pro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +d1_mini_pro.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini_pro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +d1_mini_pro.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini_pro.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 d1_mini_pro.upload.resetmethod=--before default_reset --after hard_reset d1_mini_pro.build.flash_mode=dio d1_mini_pro.build.flash_flags=-DFLASHMODE_DIO @@ -3953,7 +4068,7 @@ d1_mini_pro.build.flash_freq=40 d1_mini_pro.menu.eesz.16M14M=16MB (FS:14MB OTA:~1019KB) d1_mini_pro.menu.eesz.16M14M.build.flash_size=16M d1_mini_pro.menu.eesz.16M14M.build.flash_size_bytes=0x1000000 -d1_mini_pro.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld +d1_mini_pro.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld.h d1_mini_pro.menu.eesz.16M14M.build.spiffs_pagesize=256 d1_mini_pro.menu.eesz.16M14M.upload.maximum_size=1044464 d1_mini_pro.menu.eesz.16M14M.build.rfcal_addr=0xFFC000 @@ -3963,7 +4078,7 @@ d1_mini_pro.menu.eesz.16M14M.build.spiffs_blocksize=8192 d1_mini_pro.menu.eesz.16M15M=16MB (FS:15MB OTA:~512KB) d1_mini_pro.menu.eesz.16M15M.build.flash_size=16M d1_mini_pro.menu.eesz.16M15M.build.flash_size_bytes=0x1000000 -d1_mini_pro.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld +d1_mini_pro.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld.h d1_mini_pro.menu.eesz.16M15M.build.spiffs_pagesize=256 d1_mini_pro.menu.eesz.16M15M.upload.maximum_size=1044464 d1_mini_pro.menu.eesz.16M15M.build.rfcal_addr=0xFFC000 @@ -4122,6 +4237,12 @@ d1_mini_lite.menu.ssl.all=All SSL ciphers (most compatible) d1_mini_lite.menu.ssl.all.build.sslflags= d1_mini_lite.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini_lite.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +d1_mini_lite.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +d1_mini_lite.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini_lite.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +d1_mini_lite.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini_lite.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 d1_mini_lite.upload.resetmethod=--before default_reset --after hard_reset d1_mini_lite.build.flash_mode=dout d1_mini_lite.build.flash_flags=-DFLASHMODE_DOUT @@ -4129,7 +4250,7 @@ d1_mini_lite.build.flash_freq=40 d1_mini_lite.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) d1_mini_lite.menu.eesz.1M64.build.flash_size=1M d1_mini_lite.menu.eesz.1M64.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +d1_mini_lite.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h d1_mini_lite.menu.eesz.1M64.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M64.upload.maximum_size=958448 d1_mini_lite.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -4139,7 +4260,7 @@ d1_mini_lite.menu.eesz.1M64.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) d1_mini_lite.menu.eesz.1M128.build.flash_size=1M d1_mini_lite.menu.eesz.1M128.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +d1_mini_lite.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h d1_mini_lite.menu.eesz.1M128.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M128.upload.maximum_size=892912 d1_mini_lite.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -4149,7 +4270,7 @@ d1_mini_lite.menu.eesz.1M128.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) d1_mini_lite.menu.eesz.1M144.build.flash_size=1M d1_mini_lite.menu.eesz.1M144.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +d1_mini_lite.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h d1_mini_lite.menu.eesz.1M144.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M144.upload.maximum_size=876528 d1_mini_lite.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -4159,7 +4280,7 @@ d1_mini_lite.menu.eesz.1M144.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) d1_mini_lite.menu.eesz.1M160.build.flash_size=1M d1_mini_lite.menu.eesz.1M160.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +d1_mini_lite.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h d1_mini_lite.menu.eesz.1M160.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M160.upload.maximum_size=860144 d1_mini_lite.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -4169,7 +4290,7 @@ d1_mini_lite.menu.eesz.1M160.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) d1_mini_lite.menu.eesz.1M192.build.flash_size=1M d1_mini_lite.menu.eesz.1M192.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +d1_mini_lite.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h d1_mini_lite.menu.eesz.1M192.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M192.upload.maximum_size=827376 d1_mini_lite.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -4179,7 +4300,7 @@ d1_mini_lite.menu.eesz.1M192.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) d1_mini_lite.menu.eesz.1M256.build.flash_size=1M d1_mini_lite.menu.eesz.1M256.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +d1_mini_lite.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h d1_mini_lite.menu.eesz.1M256.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M256.upload.maximum_size=761840 d1_mini_lite.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -4189,7 +4310,7 @@ d1_mini_lite.menu.eesz.1M256.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) d1_mini_lite.menu.eesz.1M512.build.flash_size=1M d1_mini_lite.menu.eesz.1M512.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +d1_mini_lite.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h d1_mini_lite.menu.eesz.1M512.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M512.upload.maximum_size=499696 d1_mini_lite.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -4199,7 +4320,7 @@ d1_mini_lite.menu.eesz.1M512.build.spiffs_blocksize=8192 d1_mini_lite.menu.eesz.1M=1MB (FS:none OTA:~502KB) d1_mini_lite.menu.eesz.1M.build.flash_size=1M d1_mini_lite.menu.eesz.1M.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +d1_mini_lite.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h d1_mini_lite.menu.eesz.1M.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M.upload.maximum_size=1023984 d1_mini_lite.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -4355,6 +4476,12 @@ d1.menu.ssl.all=All SSL ciphers (most compatible) d1.menu.ssl.all.build.sslflags= d1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +d1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +d1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +d1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 d1.upload.resetmethod=--before default_reset --after hard_reset d1.build.flash_mode=dio d1.build.flash_flags=-DFLASHMODE_DIO @@ -4362,7 +4489,7 @@ d1.build.flash_freq=40 d1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) d1.menu.eesz.4M2M.build.flash_size=4M d1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +d1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h d1.menu.eesz.4M2M.build.spiffs_pagesize=256 d1.menu.eesz.4M2M.upload.maximum_size=1044464 d1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4372,7 +4499,7 @@ d1.menu.eesz.4M2M.build.spiffs_blocksize=8192 d1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) d1.menu.eesz.4M3M.build.flash_size=4M d1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +d1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h d1.menu.eesz.4M3M.build.spiffs_pagesize=256 d1.menu.eesz.4M3M.upload.maximum_size=1044464 d1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -4382,7 +4509,7 @@ d1.menu.eesz.4M3M.build.spiffs_blocksize=8192 d1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) d1.menu.eesz.4M1M.build.flash_size=4M d1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +d1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h d1.menu.eesz.4M1M.build.spiffs_pagesize=256 d1.menu.eesz.4M1M.upload.maximum_size=1044464 d1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -4392,7 +4519,7 @@ d1.menu.eesz.4M1M.build.spiffs_blocksize=8192 d1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) d1.menu.eesz.4M.build.flash_size=4M d1.menu.eesz.4M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +d1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h d1.menu.eesz.4M.build.spiffs_pagesize=256 d1.menu.eesz.4M.upload.maximum_size=1044464 d1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4548,6 +4675,12 @@ espino.menu.ssl.all=All SSL ciphers (most compatible) espino.menu.ssl.all.build.sslflags= espino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espino.menu.ResetMethod.nodemcu=dtr (aka nodemcu) espino.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset espino.menu.ResetMethod.ck=no dtr (aka ck) @@ -4558,7 +4691,7 @@ espino.build.flash_freq=40 espino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espino.menu.eesz.4M2M.build.flash_size=4M espino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espino.menu.eesz.4M2M.build.spiffs_pagesize=256 espino.menu.eesz.4M2M.upload.maximum_size=1044464 espino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4568,7 +4701,7 @@ espino.menu.eesz.4M2M.build.spiffs_blocksize=8192 espino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espino.menu.eesz.4M3M.build.flash_size=4M espino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espino.menu.eesz.4M3M.build.spiffs_pagesize=256 espino.menu.eesz.4M3M.upload.maximum_size=1044464 espino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -4578,7 +4711,7 @@ espino.menu.eesz.4M3M.build.spiffs_blocksize=8192 espino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espino.menu.eesz.4M1M.build.flash_size=4M espino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espino.menu.eesz.4M1M.build.spiffs_pagesize=256 espino.menu.eesz.4M1M.upload.maximum_size=1044464 espino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -4588,7 +4721,7 @@ espino.menu.eesz.4M1M.build.spiffs_blocksize=8192 espino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espino.menu.eesz.4M.build.flash_size=4M espino.menu.eesz.4M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espino.menu.eesz.4M.build.spiffs_pagesize=256 espino.menu.eesz.4M.upload.maximum_size=1044464 espino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4744,6 +4877,12 @@ espinotee.menu.ssl.all=All SSL ciphers (most compatible) espinotee.menu.ssl.all.build.sslflags= espinotee.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espinotee.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espinotee.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espinotee.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espinotee.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espinotee.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espinotee.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espinotee.upload.resetmethod=--before default_reset --after hard_reset espinotee.build.flash_mode=qio espinotee.build.flash_flags=-DFLASHMODE_QIO @@ -4751,7 +4890,7 @@ espinotee.build.flash_freq=40 espinotee.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espinotee.menu.eesz.4M2M.build.flash_size=4M espinotee.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espinotee.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espinotee.menu.eesz.4M2M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M2M.upload.maximum_size=1044464 espinotee.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4761,7 +4900,7 @@ espinotee.menu.eesz.4M2M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espinotee.menu.eesz.4M3M.build.flash_size=4M espinotee.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espinotee.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espinotee.menu.eesz.4M3M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M3M.upload.maximum_size=1044464 espinotee.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -4771,7 +4910,7 @@ espinotee.menu.eesz.4M3M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espinotee.menu.eesz.4M1M.build.flash_size=4M espinotee.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espinotee.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espinotee.menu.eesz.4M1M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M1M.upload.maximum_size=1044464 espinotee.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -4781,7 +4920,7 @@ espinotee.menu.eesz.4M1M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espinotee.menu.eesz.4M.build.flash_size=4M espinotee.menu.eesz.4M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espinotee.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espinotee.menu.eesz.4M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M.upload.maximum_size=1044464 espinotee.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4954,6 +5093,12 @@ wifinfo.menu.ssl.all=All SSL ciphers (most compatible) wifinfo.menu.ssl.all.build.sslflags= wifinfo.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifinfo.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +wifinfo.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +wifinfo.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifinfo.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +wifinfo.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifinfo.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 wifinfo.upload.resetmethod=--before default_reset --after hard_reset wifinfo.build.flash_mode=qio wifinfo.build.flash_flags=-DFLASHMODE_QIO @@ -4968,7 +5113,7 @@ wifinfo.menu.FlashFreq.26.build.flash_freq=26 wifinfo.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) wifinfo.menu.eesz.1M64.build.flash_size=1M wifinfo.menu.eesz.1M64.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +wifinfo.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h wifinfo.menu.eesz.1M64.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M64.upload.maximum_size=958448 wifinfo.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -4978,7 +5123,7 @@ wifinfo.menu.eesz.1M64.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) wifinfo.menu.eesz.1M128.build.flash_size=1M wifinfo.menu.eesz.1M128.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +wifinfo.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h wifinfo.menu.eesz.1M128.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M128.upload.maximum_size=892912 wifinfo.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -4988,7 +5133,7 @@ wifinfo.menu.eesz.1M128.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) wifinfo.menu.eesz.1M144.build.flash_size=1M wifinfo.menu.eesz.1M144.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +wifinfo.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h wifinfo.menu.eesz.1M144.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M144.upload.maximum_size=876528 wifinfo.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -4998,7 +5143,7 @@ wifinfo.menu.eesz.1M144.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) wifinfo.menu.eesz.1M160.build.flash_size=1M wifinfo.menu.eesz.1M160.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +wifinfo.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h wifinfo.menu.eesz.1M160.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M160.upload.maximum_size=860144 wifinfo.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -5008,7 +5153,7 @@ wifinfo.menu.eesz.1M160.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) wifinfo.menu.eesz.1M192.build.flash_size=1M wifinfo.menu.eesz.1M192.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +wifinfo.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h wifinfo.menu.eesz.1M192.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M192.upload.maximum_size=827376 wifinfo.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -5018,7 +5163,7 @@ wifinfo.menu.eesz.1M192.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) wifinfo.menu.eesz.1M256.build.flash_size=1M wifinfo.menu.eesz.1M256.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +wifinfo.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h wifinfo.menu.eesz.1M256.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M256.upload.maximum_size=761840 wifinfo.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -5028,7 +5173,7 @@ wifinfo.menu.eesz.1M256.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) wifinfo.menu.eesz.1M512.build.flash_size=1M wifinfo.menu.eesz.1M512.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +wifinfo.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h wifinfo.menu.eesz.1M512.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M512.upload.maximum_size=499696 wifinfo.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -5038,7 +5183,7 @@ wifinfo.menu.eesz.1M512.build.spiffs_blocksize=8192 wifinfo.menu.eesz.1M=1MB (FS:none OTA:~502KB) wifinfo.menu.eesz.1M.build.flash_size=1M wifinfo.menu.eesz.1M.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +wifinfo.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h wifinfo.menu.eesz.1M.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M.upload.maximum_size=1023984 wifinfo.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -5206,6 +5351,12 @@ arduino-esp8266.menu.ssl.all=All SSL ciphers (most compatible) arduino-esp8266.menu.ssl.all.build.sslflags= arduino-esp8266.menu.ssl.basic=Basic SSL ciphers (lower ROM use) arduino-esp8266.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +arduino-esp8266.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +arduino-esp8266.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +arduino-esp8266.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +arduino-esp8266.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +arduino-esp8266.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 arduino-esp8266.upload.resetmethod=--before no_reset --after soft_reset arduino-esp8266.build.flash_mode=qio arduino-esp8266.build.flash_flags=-DFLASHMODE_QIO @@ -5213,7 +5364,7 @@ arduino-esp8266.build.flash_freq=40 arduino-esp8266.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) arduino-esp8266.menu.eesz.4M2M.build.flash_size=4M arduino-esp8266.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +arduino-esp8266.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h arduino-esp8266.menu.eesz.4M2M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M2M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -5223,7 +5374,7 @@ arduino-esp8266.menu.eesz.4M2M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) arduino-esp8266.menu.eesz.4M3M.build.flash_size=4M arduino-esp8266.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +arduino-esp8266.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h arduino-esp8266.menu.eesz.4M3M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M3M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5233,7 +5384,7 @@ arduino-esp8266.menu.eesz.4M3M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) arduino-esp8266.menu.eesz.4M1M.build.flash_size=4M arduino-esp8266.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +arduino-esp8266.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h arduino-esp8266.menu.eesz.4M1M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M1M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5243,7 +5394,7 @@ arduino-esp8266.menu.eesz.4M1M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M=4MB (FS:none OTA:~1019KB) arduino-esp8266.menu.eesz.4M.build.flash_size=4M arduino-esp8266.menu.eesz.4M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +arduino-esp8266.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h arduino-esp8266.menu.eesz.4M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -5400,6 +5551,12 @@ gen4iod.menu.ssl.all=All SSL ciphers (most compatible) gen4iod.menu.ssl.all.build.sslflags= gen4iod.menu.ssl.basic=Basic SSL ciphers (lower ROM use) gen4iod.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +gen4iod.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +gen4iod.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +gen4iod.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +gen4iod.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +gen4iod.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 gen4iod.upload.resetmethod=--before default_reset --after hard_reset gen4iod.build.flash_mode=dio gen4iod.build.flash_flags=-DFLASHMODE_DIO @@ -5407,7 +5564,7 @@ gen4iod.build.flash_freq=80 gen4iod.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) gen4iod.menu.eesz.512K32.build.flash_size=512K gen4iod.menu.eesz.512K32.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld +gen4iod.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h gen4iod.menu.eesz.512K32.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K32.upload.maximum_size=466928 gen4iod.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -5417,7 +5574,7 @@ gen4iod.menu.eesz.512K32.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) gen4iod.menu.eesz.512K64.build.flash_size=512K gen4iod.menu.eesz.512K64.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld +gen4iod.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h gen4iod.menu.eesz.512K64.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K64.upload.maximum_size=434160 gen4iod.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -5427,7 +5584,7 @@ gen4iod.menu.eesz.512K64.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) gen4iod.menu.eesz.512K128.build.flash_size=512K gen4iod.menu.eesz.512K128.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld +gen4iod.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h gen4iod.menu.eesz.512K128.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K128.upload.maximum_size=368624 gen4iod.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -5437,7 +5594,7 @@ gen4iod.menu.eesz.512K128.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K=512KB (FS:none OTA:~246KB) gen4iod.menu.eesz.512K.build.flash_size=512K gen4iod.menu.eesz.512K.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld +gen4iod.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h gen4iod.menu.eesz.512K.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K.upload.maximum_size=499696 gen4iod.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -5594,6 +5751,12 @@ oak.menu.ssl.all=All SSL ciphers (most compatible) oak.menu.ssl.all.build.sslflags= oak.menu.ssl.basic=Basic SSL ciphers (lower ROM use) oak.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +oak.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +oak.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +oak.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +oak.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +oak.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 oak.upload.resetmethod=--before no_reset --after soft_reset oak.build.flash_mode=dio oak.build.flash_flags=-DFLASHMODE_DIO @@ -5601,7 +5764,7 @@ oak.build.flash_freq=40 oak.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) oak.menu.eesz.4M2M.build.flash_size=4M oak.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +oak.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h oak.menu.eesz.4M2M.build.spiffs_pagesize=256 oak.menu.eesz.4M2M.upload.maximum_size=1044464 oak.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -5611,7 +5774,7 @@ oak.menu.eesz.4M2M.build.spiffs_blocksize=8192 oak.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) oak.menu.eesz.4M3M.build.flash_size=4M oak.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +oak.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h oak.menu.eesz.4M3M.build.spiffs_pagesize=256 oak.menu.eesz.4M3M.upload.maximum_size=1044464 oak.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5621,7 +5784,7 @@ oak.menu.eesz.4M3M.build.spiffs_blocksize=8192 oak.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) oak.menu.eesz.4M1M.build.flash_size=4M oak.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +oak.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h oak.menu.eesz.4M1M.build.spiffs_pagesize=256 oak.menu.eesz.4M1M.upload.maximum_size=1044464 oak.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5631,7 +5794,7 @@ oak.menu.eesz.4M1M.build.spiffs_blocksize=8192 oak.menu.eesz.4M=4MB (FS:none OTA:~1019KB) oak.menu.eesz.4M.build.flash_size=4M oak.menu.eesz.4M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +oak.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h oak.menu.eesz.4M.build.spiffs_pagesize=256 oak.menu.eesz.4M.upload.maximum_size=1044464 oak.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -5787,6 +5950,12 @@ wifiduino.menu.ssl.all=All SSL ciphers (most compatible) wifiduino.menu.ssl.all.build.sslflags= wifiduino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifiduino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +wifiduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +wifiduino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifiduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +wifiduino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifiduino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 wifiduino.upload.resetmethod=--before default_reset --after hard_reset wifiduino.build.flash_mode=dio wifiduino.build.flash_flags=-DFLASHMODE_DIO @@ -5794,7 +5963,7 @@ wifiduino.build.flash_freq=40 wifiduino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) wifiduino.menu.eesz.4M2M.build.flash_size=4M wifiduino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +wifiduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h wifiduino.menu.eesz.4M2M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M2M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -5804,7 +5973,7 @@ wifiduino.menu.eesz.4M2M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) wifiduino.menu.eesz.4M3M.build.flash_size=4M wifiduino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +wifiduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h wifiduino.menu.eesz.4M3M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M3M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5814,7 +5983,7 @@ wifiduino.menu.eesz.4M3M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) wifiduino.menu.eesz.4M1M.build.flash_size=4M wifiduino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +wifiduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h wifiduino.menu.eesz.4M1M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M1M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5824,7 +5993,7 @@ wifiduino.menu.eesz.4M1M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) wifiduino.menu.eesz.4M.build.flash_size=4M wifiduino.menu.eesz.4M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +wifiduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h wifiduino.menu.eesz.4M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -5980,6 +6149,12 @@ wifi_slot.menu.ssl.all=All SSL ciphers (most compatible) wifi_slot.menu.ssl.all.build.sslflags= wifi_slot.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifi_slot.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +wifi_slot.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +wifi_slot.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifi_slot.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +wifi_slot.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifi_slot.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 wifi_slot.upload.resetmethod=--before default_reset --after hard_reset wifi_slot.menu.FlashFreq.40=40MHz wifi_slot.menu.FlashFreq.40.build.flash_freq=40 @@ -6004,7 +6179,7 @@ wifi_slot.menu.FlashMode.qio.build.flash_flags=-DFLASHMODE_QIO wifi_slot.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) wifi_slot.menu.eesz.1M64.build.flash_size=1M wifi_slot.menu.eesz.1M64.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +wifi_slot.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h wifi_slot.menu.eesz.1M64.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M64.upload.maximum_size=958448 wifi_slot.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -6014,7 +6189,7 @@ wifi_slot.menu.eesz.1M64.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) wifi_slot.menu.eesz.1M128.build.flash_size=1M wifi_slot.menu.eesz.1M128.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +wifi_slot.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h wifi_slot.menu.eesz.1M128.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M128.upload.maximum_size=892912 wifi_slot.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -6024,7 +6199,7 @@ wifi_slot.menu.eesz.1M128.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) wifi_slot.menu.eesz.1M144.build.flash_size=1M wifi_slot.menu.eesz.1M144.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +wifi_slot.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h wifi_slot.menu.eesz.1M144.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M144.upload.maximum_size=876528 wifi_slot.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -6034,7 +6209,7 @@ wifi_slot.menu.eesz.1M144.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) wifi_slot.menu.eesz.1M160.build.flash_size=1M wifi_slot.menu.eesz.1M160.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +wifi_slot.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h wifi_slot.menu.eesz.1M160.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M160.upload.maximum_size=860144 wifi_slot.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -6044,7 +6219,7 @@ wifi_slot.menu.eesz.1M160.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) wifi_slot.menu.eesz.1M192.build.flash_size=1M wifi_slot.menu.eesz.1M192.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +wifi_slot.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h wifi_slot.menu.eesz.1M192.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M192.upload.maximum_size=827376 wifi_slot.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -6054,7 +6229,7 @@ wifi_slot.menu.eesz.1M192.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) wifi_slot.menu.eesz.1M256.build.flash_size=1M wifi_slot.menu.eesz.1M256.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +wifi_slot.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h wifi_slot.menu.eesz.1M256.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M256.upload.maximum_size=761840 wifi_slot.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -6064,7 +6239,7 @@ wifi_slot.menu.eesz.1M256.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) wifi_slot.menu.eesz.1M512.build.flash_size=1M wifi_slot.menu.eesz.1M512.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +wifi_slot.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h wifi_slot.menu.eesz.1M512.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M512.upload.maximum_size=499696 wifi_slot.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -6074,14 +6249,14 @@ wifi_slot.menu.eesz.1M512.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.1M=1MB (FS:none OTA:~502KB) wifi_slot.menu.eesz.1M.build.flash_size=1M wifi_slot.menu.eesz.1M.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +wifi_slot.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h wifi_slot.menu.eesz.1M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M.upload.maximum_size=1023984 wifi_slot.menu.eesz.1M.build.rfcal_addr=0xFC000 wifi_slot.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) wifi_slot.menu.eesz.2M64.build.flash_size=2M wifi_slot.menu.eesz.2M64.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld +wifi_slot.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h wifi_slot.menu.eesz.2M64.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M64.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -6091,7 +6266,7 @@ wifi_slot.menu.eesz.2M64.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) wifi_slot.menu.eesz.2M128.build.flash_size=2M wifi_slot.menu.eesz.2M128.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld +wifi_slot.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h wifi_slot.menu.eesz.2M128.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M128.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -6101,7 +6276,7 @@ wifi_slot.menu.eesz.2M128.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) wifi_slot.menu.eesz.2M256.build.flash_size=2M wifi_slot.menu.eesz.2M256.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld +wifi_slot.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h wifi_slot.menu.eesz.2M256.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M256.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -6111,7 +6286,7 @@ wifi_slot.menu.eesz.2M256.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) wifi_slot.menu.eesz.2M512.build.flash_size=2M wifi_slot.menu.eesz.2M512.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld +wifi_slot.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h wifi_slot.menu.eesz.2M512.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M512.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -6121,7 +6296,7 @@ wifi_slot.menu.eesz.2M512.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) wifi_slot.menu.eesz.2M1M.build.flash_size=2M wifi_slot.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld +wifi_slot.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h wifi_slot.menu.eesz.2M1M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M1M.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -6131,7 +6306,7 @@ wifi_slot.menu.eesz.2M1M.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.2M=2MB (FS:none OTA:~1019KB) wifi_slot.menu.eesz.2M.build.flash_size=2M wifi_slot.menu.eesz.2M.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld +wifi_slot.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h wifi_slot.menu.eesz.2M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M.build.rfcal_addr=0x1FC000 @@ -6287,6 +6462,12 @@ wiolink.menu.ssl.all=All SSL ciphers (most compatible) wiolink.menu.ssl.all.build.sslflags= wiolink.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wiolink.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +wiolink.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +wiolink.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wiolink.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +wiolink.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wiolink.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 wiolink.upload.resetmethod=--before default_reset --after hard_reset wiolink.build.flash_mode=qio wiolink.build.flash_flags=-DFLASHMODE_QIO @@ -6294,7 +6475,7 @@ wiolink.build.flash_freq=40 wiolink.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) wiolink.menu.eesz.4M2M.build.flash_size=4M wiolink.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +wiolink.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h wiolink.menu.eesz.4M2M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M2M.upload.maximum_size=1044464 wiolink.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -6304,7 +6485,7 @@ wiolink.menu.eesz.4M2M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) wiolink.menu.eesz.4M3M.build.flash_size=4M wiolink.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +wiolink.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h wiolink.menu.eesz.4M3M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M3M.upload.maximum_size=1044464 wiolink.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -6314,7 +6495,7 @@ wiolink.menu.eesz.4M3M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) wiolink.menu.eesz.4M1M.build.flash_size=4M wiolink.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +wiolink.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h wiolink.menu.eesz.4M1M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M1M.upload.maximum_size=1044464 wiolink.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -6324,7 +6505,7 @@ wiolink.menu.eesz.4M1M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M=4MB (FS:none OTA:~1019KB) wiolink.menu.eesz.4M.build.flash_size=4M wiolink.menu.eesz.4M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +wiolink.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h wiolink.menu.eesz.4M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M.upload.maximum_size=1044464 wiolink.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -6480,6 +6661,12 @@ espectro.menu.ssl.all=All SSL ciphers (most compatible) espectro.menu.ssl.all.build.sslflags= espectro.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espectro.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espectro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espectro.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espectro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espectro.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espectro.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espectro.upload.resetmethod=--before default_reset --after hard_reset espectro.build.flash_mode=dio espectro.build.flash_flags=-DFLASHMODE_DIO @@ -6487,7 +6674,7 @@ espectro.build.flash_freq=40 espectro.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espectro.menu.eesz.4M2M.build.flash_size=4M espectro.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld +espectro.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h espectro.menu.eesz.4M2M.build.spiffs_pagesize=256 espectro.menu.eesz.4M2M.upload.maximum_size=1044464 espectro.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -6497,7 +6684,7 @@ espectro.menu.eesz.4M2M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espectro.menu.eesz.4M3M.build.flash_size=4M espectro.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld +espectro.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h espectro.menu.eesz.4M3M.build.spiffs_pagesize=256 espectro.menu.eesz.4M3M.upload.maximum_size=1044464 espectro.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -6507,7 +6694,7 @@ espectro.menu.eesz.4M3M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espectro.menu.eesz.4M1M.build.flash_size=4M espectro.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld +espectro.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h espectro.menu.eesz.4M1M.build.spiffs_pagesize=256 espectro.menu.eesz.4M1M.upload.maximum_size=1044464 espectro.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -6517,7 +6704,7 @@ espectro.menu.eesz.4M1M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espectro.menu.eesz.4M.build.flash_size=4M espectro.menu.eesz.4M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld +espectro.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h espectro.menu.eesz.4M.build.spiffs_pagesize=256 espectro.menu.eesz.4M.upload.maximum_size=1044464 espectro.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -6683,6 +6870,12 @@ sonoff.menu.ssl.all=All SSL ciphers (most compatible) sonoff.menu.ssl.all.build.sslflags= sonoff.menu.ssl.basic=Basic SSL ciphers (lower ROM use) sonoff.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +sonoff.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +sonoff.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +sonoff.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +sonoff.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +sonoff.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 sonoff.upload.resetmethod=--before no_reset --after soft_reset sonoff.build.flash_mode=dout sonoff.build.flash_flags=-DFLASHMODE_DOUT @@ -6690,7 +6883,7 @@ sonoff.build.flash_freq=40 sonoff.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) sonoff.menu.eesz.1M64.build.flash_size=1M sonoff.menu.eesz.1M64.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +sonoff.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h sonoff.menu.eesz.1M64.build.spiffs_pagesize=256 sonoff.menu.eesz.1M64.upload.maximum_size=958448 sonoff.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -6700,7 +6893,7 @@ sonoff.menu.eesz.1M64.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) sonoff.menu.eesz.1M128.build.flash_size=1M sonoff.menu.eesz.1M128.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +sonoff.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h sonoff.menu.eesz.1M128.build.spiffs_pagesize=256 sonoff.menu.eesz.1M128.upload.maximum_size=892912 sonoff.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -6710,7 +6903,7 @@ sonoff.menu.eesz.1M128.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) sonoff.menu.eesz.1M144.build.flash_size=1M sonoff.menu.eesz.1M144.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +sonoff.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h sonoff.menu.eesz.1M144.build.spiffs_pagesize=256 sonoff.menu.eesz.1M144.upload.maximum_size=876528 sonoff.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -6720,7 +6913,7 @@ sonoff.menu.eesz.1M144.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) sonoff.menu.eesz.1M160.build.flash_size=1M sonoff.menu.eesz.1M160.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +sonoff.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h sonoff.menu.eesz.1M160.build.spiffs_pagesize=256 sonoff.menu.eesz.1M160.upload.maximum_size=860144 sonoff.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -6730,7 +6923,7 @@ sonoff.menu.eesz.1M160.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) sonoff.menu.eesz.1M192.build.flash_size=1M sonoff.menu.eesz.1M192.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +sonoff.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h sonoff.menu.eesz.1M192.build.spiffs_pagesize=256 sonoff.menu.eesz.1M192.upload.maximum_size=827376 sonoff.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -6740,7 +6933,7 @@ sonoff.menu.eesz.1M192.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) sonoff.menu.eesz.1M256.build.flash_size=1M sonoff.menu.eesz.1M256.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +sonoff.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h sonoff.menu.eesz.1M256.build.spiffs_pagesize=256 sonoff.menu.eesz.1M256.upload.maximum_size=761840 sonoff.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -6750,7 +6943,7 @@ sonoff.menu.eesz.1M256.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) sonoff.menu.eesz.1M512.build.flash_size=1M sonoff.menu.eesz.1M512.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +sonoff.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h sonoff.menu.eesz.1M512.build.spiffs_pagesize=256 sonoff.menu.eesz.1M512.upload.maximum_size=499696 sonoff.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -6760,7 +6953,7 @@ sonoff.menu.eesz.1M512.build.spiffs_blocksize=8192 sonoff.menu.eesz.1M=1MB (FS:none OTA:~502KB) sonoff.menu.eesz.1M.build.flash_size=1M sonoff.menu.eesz.1M.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +sonoff.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h sonoff.menu.eesz.1M.build.spiffs_pagesize=256 sonoff.menu.eesz.1M.upload.maximum_size=1023984 sonoff.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -6917,6 +7110,12 @@ espmxdevkit.menu.ssl.all=All SSL ciphers (most compatible) espmxdevkit.menu.ssl.all.build.sslflags= espmxdevkit.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espmxdevkit.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +espmxdevkit.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +espmxdevkit.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espmxdevkit.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +espmxdevkit.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espmxdevkit.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 espmxdevkit.upload.resetmethod=--before default_reset --after hard_reset espmxdevkit.build.flash_mode=dout espmxdevkit.build.flash_flags=-DFLASHMODE_DOUT @@ -6924,7 +7123,7 @@ espmxdevkit.build.flash_freq=40 espmxdevkit.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) espmxdevkit.menu.eesz.1M64.build.flash_size=1M espmxdevkit.menu.eesz.1M64.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld +espmxdevkit.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h espmxdevkit.menu.eesz.1M64.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M64.upload.maximum_size=958448 espmxdevkit.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -6934,7 +7133,7 @@ espmxdevkit.menu.eesz.1M64.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) espmxdevkit.menu.eesz.1M128.build.flash_size=1M espmxdevkit.menu.eesz.1M128.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld +espmxdevkit.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h espmxdevkit.menu.eesz.1M128.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M128.upload.maximum_size=892912 espmxdevkit.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -6944,7 +7143,7 @@ espmxdevkit.menu.eesz.1M128.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) espmxdevkit.menu.eesz.1M144.build.flash_size=1M espmxdevkit.menu.eesz.1M144.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld +espmxdevkit.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h espmxdevkit.menu.eesz.1M144.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M144.upload.maximum_size=876528 espmxdevkit.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -6954,7 +7153,7 @@ espmxdevkit.menu.eesz.1M144.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) espmxdevkit.menu.eesz.1M160.build.flash_size=1M espmxdevkit.menu.eesz.1M160.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld +espmxdevkit.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h espmxdevkit.menu.eesz.1M160.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M160.upload.maximum_size=860144 espmxdevkit.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -6964,7 +7163,7 @@ espmxdevkit.menu.eesz.1M160.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) espmxdevkit.menu.eesz.1M192.build.flash_size=1M espmxdevkit.menu.eesz.1M192.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld +espmxdevkit.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h espmxdevkit.menu.eesz.1M192.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M192.upload.maximum_size=827376 espmxdevkit.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -6974,7 +7173,7 @@ espmxdevkit.menu.eesz.1M192.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) espmxdevkit.menu.eesz.1M256.build.flash_size=1M espmxdevkit.menu.eesz.1M256.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld +espmxdevkit.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h espmxdevkit.menu.eesz.1M256.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M256.upload.maximum_size=761840 espmxdevkit.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -6984,7 +7183,7 @@ espmxdevkit.menu.eesz.1M256.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) espmxdevkit.menu.eesz.1M512.build.flash_size=1M espmxdevkit.menu.eesz.1M512.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld +espmxdevkit.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h espmxdevkit.menu.eesz.1M512.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M512.upload.maximum_size=499696 espmxdevkit.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -6994,7 +7193,7 @@ espmxdevkit.menu.eesz.1M512.build.spiffs_blocksize=8192 espmxdevkit.menu.eesz.1M=1MB (FS:none OTA:~502KB) espmxdevkit.menu.eesz.1M.build.flash_size=1M espmxdevkit.menu.eesz.1M.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld +espmxdevkit.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h espmxdevkit.menu.eesz.1M.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M.upload.maximum_size=1023984 espmxdevkit.menu.eesz.1M.build.rfcal_addr=0xFC000 diff --git a/bootloaders/eboot/eboot.c b/bootloaders/eboot/eboot.c index c7cf285c0b..13620b853d 100644 --- a/bootloaders/eboot/eboot.c +++ b/bootloaders/eboot/eboot.c @@ -68,7 +68,7 @@ int load_app_from_flash_raw(const uint32_t flash_addr) load = true; } - if (address >= 0x40100000 && address < 0x40108000) { + if (address >= 0x40100000 && address < 0x4010C000) { load = true; } diff --git a/bootloaders/eboot/eboot.elf b/bootloaders/eboot/eboot.elf index 0d862f6a9f6bf2b014610c46d4ba14d4eb088fc0..26f550ff7df21e606fd6782fd7f4337b66e318ef 100755 GIT binary patch delta 16 XcmeB~$ka2DX@jBw +#include /* precache() * pre-loads flash data into the flash cache @@ -45,6 +46,33 @@ void precache(void *f, uint32_t bytes) { (void)x; } + + +int Cache_Read_Enable_status = -1; + +#if (ICACHE_SIZE == 0x4000) +#define SOC_CACHE_SIZE 0 // 16KB +// #define SOC_CACHE_SIZE 1 // 32KB + +#pragma message("ICACHE size 16K") + + +#ifndef ROM_Cache_Read_Enable +#define ROM_Cache_Read_Enable 0x40004678 +#endif + +typedef void (*fp_Cache_Read_Enable_t)(uint32_t map, uint32_t p, uint32_t v); +constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; +/* + * Override SDK's ICACHE size + */ +void IRAM_ATTR Cache_Read_Enable(uint32_t map, uint32_t p, uint32_t v) { + (void)v; + real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); + Cache_Read_Enable_status = SOC_CACHE_SIZE; +} +#endif + #ifdef __cplusplus } #endif diff --git a/cores/esp8266/core_esp8266_features.h b/cores/esp8266/core_esp8266_features.h index d3b70f3dcc..dae34f6f8d 100644 --- a/cores/esp8266/core_esp8266_features.h +++ b/cores/esp8266/core_esp8266_features.h @@ -112,6 +112,9 @@ extern "C" { void precache(void *f, uint32_t bytes); +void Cache_Read_Enable(uint32_t map, uint32_t p, uint32_t v); +extern int Cache_Read_Enable_status; + #ifdef __cplusplus } #endif diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino new file mode 100644 index 0000000000..18e41f5eec --- /dev/null +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -0,0 +1,98 @@ +#include +#include + +/* + Notes, + When accessing IRAM as data storage all access must be word aligned and + full word length. + +*/ + +#if (IRAM_SIZE > 32*1024) +uint32_t gobble[4 * 1024] IRAM_ATTR; +constexpr size_t gobble_sz = sizeof(gobble); +#endif + +#ifdef SEC_HEAP +constexpr uint32_t *gobble = (uint32_t *)SEC_HEAP; +constexpr size_t gobble_sz = SEC_HEAP_SIZE; +#endif + +bool isValid(uint32_t *probe) { + bool rc = true; + ets_uart_printf("\nTesting for valid memory at %p ...\n", probe); + uint32_t savePS = xt_rsil(15); + uint32_t saveData = *probe; + for (size_t i = 0; i < 32; i++) { + *probe = BIT(i); + asm volatile ("" ::: "memory"); + uint32_t val = *probe; + if (val != BIT(i)) { + ets_uart_printf(" Read 0x%08X != Wrote 0x%08X\n", val, (uint32_t)BIT(i)); + rc = false; + } + } + *probe = saveData; + xt_wsr_ps(savePS); + ets_uart_printf(" %s\n", (rc) ? "Pass" : "Fail!"); + return rc; +} + + +void dump_mem(void * addr, size_t len) { + uint32_t *addr32 = (uint32_t *)((uintptr_t)addr & ~3); + len = (len + 3) & ~3; + + ets_uart_printf("\n"); + for (size_t i = 0; i < len;) { + ets_uart_printf("%p: ", &addr32[i]); + do { + ets_uart_printf("0x%08x ", addr32[i]); + } while (i++, (i & 3)); + ets_uart_printf("\n"); + } + ets_uart_printf("\n"); +} + + +void setup() { + WiFi.persistent(false); + WiFi.mode(WIFI_OFF); + Serial.begin(115200); + delay(20); + Serial.printf_P(PSTR("\n\nI am Alive!\n")); + + Serial.printf_P(PSTR("\nMMU Configuration\n")); + Serial.printf_P(PSTR(" Cache_Read_Enable status %d\n"), Cache_Read_Enable_status); +#ifdef ICACHE_SIZE + Serial.printf_P(PSTR(" ICACHE Size: %u\n"), ICACHE_SIZE); +#endif +#ifdef IRAM_SIZE + Serial.printf_P(PSTR(" IRAM Size: %u\n"), IRAM_SIZE); +#endif +#ifdef SEC_HEAP + Serial.printf_P(PSTR(" Secondary Heap at: %p\n"), SEC_HEAP); + Serial.printf_P(PSTR(" Secondary Heap Size: %u\n"), SEC_HEAP_SIZE); +#endif + +#if (IRAM_SIZE > 0x8000) || defined(SEC_HEAP) + if (isValid(gobble)) { + // Put something in our new memory + for (size_t i = 0; i < (gobble_sz/4); i++) { + gobble[i] = (uint32_t)&gobble[i]; + } + } + + // Now is it there? + dump_mem(gobble, 32); + dump_mem(&gobble[gobble_sz/4/2], 32); + dump_mem(&gobble[gobble_sz/4 - 32], 32); +#endif + + // Lets peak over the edge + dump_mem((void *)(0x4010C000 - 16 * 4), 32); +} + +void loop() { + +} diff --git a/platform.txt b/platform.txt index 678be1ba9d..ddf8ed8e0c 100644 --- a/platform.txt +++ b/platform.txt @@ -32,6 +32,7 @@ build.lwip_flags=-DLWIP_OPEN_SRC build.vtable_flags=-DVTABLES_IN_FLASH build.sslflags= +build.mmuflags= build.exception_flags=-fno-exceptions build.stdcpp_lib=-lstdc++ @@ -53,18 +54,18 @@ compiler.libc.path={runtime.platform.path}/tools/sdk/libc/xtensa-lx106-elf compiler.cpreprocessor.flags=-D__ets__ -DICACHE_FLASH -U__STRICT_ANSI__ "-I{compiler.sdk.path}/include" "-I{compiler.sdk.path}/{build.lwip_include}" "-I{compiler.libc.path}/include" "-I{build.path}/core" compiler.c.cmd=xtensa-lx106-elf-gcc -compiler.c.flags=-c {compiler.warning_flags} -Os -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals -falign-functions=4 -MMD -std=gnu99 -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} +compiler.c.flags=-c {compiler.warning_flags} -Os -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals -falign-functions=4 -MMD -std=gnu99 -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} compiler.S.cmd=xtensa-lx106-elf-gcc compiler.S.flags=-c -g -x assembler-with-cpp -MMD -mlongcalls -compiler.c.elf.flags=-g {compiler.warning_flags} -Os -nostdlib -Wl,--no-check-sections -u app_entry {build.float} -Wl,-static "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/lib/{build.sdk}" "-L{compiler.sdk.path}/ld" "-L{compiler.libc.path}/lib" "-T{build.flash_ld}" -Wl,--gc-sections -Wl,-wrap,system_restart_local -Wl,-wrap,spi_flash_read +compiler.c.elf.flags= -g {compiler.warning_flags} -Os -nostdlib -Wl,--no-check-sections -u app_entry {build.float} -Wl,-static "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/lib/{build.sdk}" "-L{build.path}" "-L{compiler.libc.path}/lib" "-Tlocal.eagle.flash.ld" -Wl,--gc-sections -Wl,-wrap,system_restart_local -Wl,-wrap,spi_flash_read compiler.c.elf.cmd=xtensa-lx106-elf-gcc compiler.c.elf.libs=-lhal -lphy -lpp -lnet80211 {build.lwip_lib} -lwpa -lcrypto -lmain -lwps -lbearssl -laxtls -lespnow -lsmartconfig -lairkiss -lwpa2 {build.stdcpp_lib} -lm -lc -lgcc compiler.cpp.cmd=xtensa-lx106-elf-g++ -compiler.cpp.flags=-c {compiler.warning_flags} -Os -g -mlongcalls -mtext-section-literals -fno-rtti -falign-functions=4 {build.stdcpp_level} -MMD -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} +compiler.cpp.flags=-c {compiler.warning_flags} -Os -g -mlongcalls -mtext-section-literals -fno-rtti -falign-functions=4 {build.stdcpp_level} -MMD -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} compiler.as.cmd=xtensa-lx106-elf-as @@ -95,7 +96,8 @@ recipe.hooks.sketch.prebuild.pattern="{runtime.tools.python3.path}/python3" "{ru recipe.hooks.prebuild.10.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.makecorever}" --build_path "{build.path}" --platform_path "{runtime.platform.path}" --version "unix-{version}" ## Build the app.ld linker file -recipe.hooks.linking.prelink.1.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} "{runtime.platform.path}/tools/sdk/ld/eagle.app.v6.common.ld.h" -o "{build.path}/local.eagle.app.v6.common.ld" +recipe.hooks.linking.prelink.1.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{runtime.platform.path}/tools/sdk/ld/eagle.app.v6.common.ld.h" -o "{build.path}/local.eagle.app.v6.common.ld" +recipe.hooks.linking.prelink.2.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{runtime.platform.path}/tools/sdk/ld/{build.flash_ld}" -o "{build.path}/local.eagle.flash.ld" ## Compile c files recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} -D{build.sdk}=1 -DF_CPU={build.f_cpu} {build.lwip_flags} {build.debug_port} {build.debug_level} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" {build.led} {build.flash_flags} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" diff --git a/tools/boards.txt.py b/tools/boards.txt.py index 47b80a93bd..b8991015c6 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1186,6 +1186,17 @@ ( '.menu.ssl.basic.build.sslflags', '-DBEARSSL_SSL_BASIC'), ]), + ####################### mmu + + 'mmu_menu': collections.OrderedDict([ + ( '.menu.mmu.3232', '32KB cache + 32KB IRAM (balanced)' ), + ( '.menu.mmu.3232.build.mmuflags', '-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000'), + ( '.menu.mmu.4816', '16KB cache + 48KB IRAM (IRAM)' ), + ( '.menu.mmu.4816.build.mmuflags', '-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000' ), + ( '.menu.mmu.3216', '16KB cache + 32KB IRAM + 16KB sec heap (Heap)' ), + ( '.menu.mmu.3216.build.mmuflags', '-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000' ), + ]), + } ################################################################ @@ -1302,7 +1313,7 @@ def flash_map (flashsize_kb, fs_kb = 0): strfs = str(int(fs_kb / 1024)) + 'M' if (fs_kb >= 1024) else str(fs_kb) + 'K' strfs_strip = str(int(fs_kb / 1024)) + 'M' if (fs_kb >= 1024) else str(fs_kb) if (fs_kb > 0) else '' - ld = 'eagle.flash.' + strsize.lower() + strfs_strip.lower() + '.ld' + ld = 'eagle.flash.' + strsize.lower() + strfs_strip.lower() + '.ld.h' menu = '.menu.eesz.' + strsize + strfs_strip menub = menu + '.build.' desc = 'none' if (fs_kb == 0) else strfs + 'B' @@ -1356,7 +1367,7 @@ def flash_map (flashsize_kb, fs_kb = 0): print("{") print(" dport0_0_seg : org = 0x3FF00000, len = 0x10") print(" dram0_0_seg : org = 0x3FFE8000, len = 0x14000") - print(" iram1_0_seg : org = 0x40100000, len = 0x8000") + print(" iram1_0_seg : org = 0x40100000, len = IRAM_SIZE") print(" irom0_0_seg : org = 0x40201010, len = 0x%x" % max_upload_size) print("}") print("") @@ -1546,6 +1557,7 @@ def all_boards (): print('menu.wipe=Erase Flash') print('menu.sdk=Espressif FW') print('menu.ssl=SSL Support') + print('menu.mmu=MMU') print('') missingboards = [] @@ -1564,7 +1576,7 @@ def all_boards (): print(id + optname + '=' + board['opts'][optname]) # macros - macrolist = [ 'defaults', 'cpufreq_menu', 'vtable_menu', 'exception_menu', 'ssl_cipher_menu' ] + macrolist = [ 'defaults', 'cpufreq_menu', 'vtable_menu', 'exception_menu', 'ssl_cipher_menu', 'mmu_menu' ] if 'macro' in board: macrolist += board['macro'] if lwip == 2: diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld b/tools/sdk/ld/eagle.flash.16m14m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.16m14m.ld rename to tools/sdk/ld/eagle.flash.16m14m.ld.h index a67ef97d15..b2f7556bad 100644 --- a/tools/sdk/ld/eagle.flash.16m14m.ld +++ b/tools/sdk/ld/eagle.flash.16m14m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld b/tools/sdk/ld/eagle.flash.16m15m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.16m15m.ld rename to tools/sdk/ld/eagle.flash.16m15m.ld.h index bca117f761..b0d14bbb3c 100644 --- a/tools/sdk/ld/eagle.flash.16m15m.ld +++ b/tools/sdk/ld/eagle.flash.16m15m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.1m.ld b/tools/sdk/ld/eagle.flash.1m.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m.ld rename to tools/sdk/ld/eagle.flash.1m.ld.h index 57c35adbc0..d90c0f297a 100644 --- a/tools/sdk/ld/eagle.flash.1m.ld +++ b/tools/sdk/ld/eagle.flash.1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xf9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m128.ld b/tools/sdk/ld/eagle.flash.1m128.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m128.ld rename to tools/sdk/ld/eagle.flash.1m128.ld.h index f518f08fa0..2e299a03c5 100644 --- a/tools/sdk/ld/eagle.flash.1m128.ld +++ b/tools/sdk/ld/eagle.flash.1m128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m144.ld b/tools/sdk/ld/eagle.flash.1m144.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m144.ld rename to tools/sdk/ld/eagle.flash.1m144.ld.h index 4a4f986511..ed29e04de6 100644 --- a/tools/sdk/ld/eagle.flash.1m144.ld +++ b/tools/sdk/ld/eagle.flash.1m144.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd5ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m160.ld b/tools/sdk/ld/eagle.flash.1m160.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m160.ld rename to tools/sdk/ld/eagle.flash.1m160.ld.h index 289c0ad0f3..4b9af5f3e1 100644 --- a/tools/sdk/ld/eagle.flash.1m160.ld +++ b/tools/sdk/ld/eagle.flash.1m160.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd1ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m192.ld b/tools/sdk/ld/eagle.flash.1m192.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m192.ld rename to tools/sdk/ld/eagle.flash.1m192.ld.h index 2b71f41acd..0747eff0af 100644 --- a/tools/sdk/ld/eagle.flash.1m192.ld +++ b/tools/sdk/ld/eagle.flash.1m192.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xc9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m256.ld b/tools/sdk/ld/eagle.flash.1m256.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m256.ld rename to tools/sdk/ld/eagle.flash.1m256.ld.h index 6a90e9fcb9..e0fc9a95b6 100644 --- a/tools/sdk/ld/eagle.flash.1m256.ld +++ b/tools/sdk/ld/eagle.flash.1m256.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xb9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m512.ld b/tools/sdk/ld/eagle.flash.1m512.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m512.ld rename to tools/sdk/ld/eagle.flash.1m512.ld.h index e3c6db39ee..d0cb913f6a 100644 --- a/tools/sdk/ld/eagle.flash.1m512.ld +++ b/tools/sdk/ld/eagle.flash.1m512.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m64.ld b/tools/sdk/ld/eagle.flash.1m64.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.1m64.ld rename to tools/sdk/ld/eagle.flash.1m64.ld.h index 87032bd029..1248031d9a 100644 --- a/tools/sdk/ld/eagle.flash.1m64.ld +++ b/tools/sdk/ld/eagle.flash.1m64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xe9ff0 } diff --git a/tools/sdk/ld/eagle.flash.2m.ld b/tools/sdk/ld/eagle.flash.2m.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.2m.ld rename to tools/sdk/ld/eagle.flash.2m.ld.h index e39377b28b..7ce1948640 100644 --- a/tools/sdk/ld/eagle.flash.2m.ld +++ b/tools/sdk/ld/eagle.flash.2m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m128.ld b/tools/sdk/ld/eagle.flash.2m128.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.2m128.ld rename to tools/sdk/ld/eagle.flash.2m128.ld.h index fd71ce4587..9b2c61db61 100644 --- a/tools/sdk/ld/eagle.flash.2m128.ld +++ b/tools/sdk/ld/eagle.flash.2m128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld b/tools/sdk/ld/eagle.flash.2m1m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.2m1m.ld rename to tools/sdk/ld/eagle.flash.2m1m.ld.h index 1726367401..95569d0ca6 100644 --- a/tools/sdk/ld/eagle.flash.2m1m.ld +++ b/tools/sdk/ld/eagle.flash.2m1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m256.ld b/tools/sdk/ld/eagle.flash.2m256.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.2m256.ld rename to tools/sdk/ld/eagle.flash.2m256.ld.h index 6b72dc1673..432175e8cd 100644 --- a/tools/sdk/ld/eagle.flash.2m256.ld +++ b/tools/sdk/ld/eagle.flash.2m256.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m512.ld b/tools/sdk/ld/eagle.flash.2m512.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.2m512.ld rename to tools/sdk/ld/eagle.flash.2m512.ld.h index eab32089f6..7109316e85 100644 --- a/tools/sdk/ld/eagle.flash.2m512.ld +++ b/tools/sdk/ld/eagle.flash.2m512.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m64.ld b/tools/sdk/ld/eagle.flash.2m64.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.2m64.ld rename to tools/sdk/ld/eagle.flash.2m64.ld.h index 61a94b26dd..6303d89b3d 100644 --- a/tools/sdk/ld/eagle.flash.2m64.ld +++ b/tools/sdk/ld/eagle.flash.2m64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m.ld b/tools/sdk/ld/eagle.flash.4m.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.4m.ld rename to tools/sdk/ld/eagle.flash.4m.ld.h index 31c0598072..ad96b432dd 100644 --- a/tools/sdk/ld/eagle.flash.4m.ld +++ b/tools/sdk/ld/eagle.flash.4m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld b/tools/sdk/ld/eagle.flash.4m1m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.4m1m.ld rename to tools/sdk/ld/eagle.flash.4m1m.ld.h index cf6bd7aa1e..1d71422f7b 100644 --- a/tools/sdk/ld/eagle.flash.4m1m.ld +++ b/tools/sdk/ld/eagle.flash.4m1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld b/tools/sdk/ld/eagle.flash.4m2m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.4m2m.ld rename to tools/sdk/ld/eagle.flash.4m2m.ld.h index 9723b9490c..2f7d238ff9 100644 --- a/tools/sdk/ld/eagle.flash.4m2m.ld +++ b/tools/sdk/ld/eagle.flash.4m2m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld b/tools/sdk/ld/eagle.flash.4m3m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.4m3m.ld rename to tools/sdk/ld/eagle.flash.4m3m.ld.h index a85a1da02c..fa06d982b4 100644 --- a/tools/sdk/ld/eagle.flash.4m3m.ld +++ b/tools/sdk/ld/eagle.flash.4m3m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.512k.ld b/tools/sdk/ld/eagle.flash.512k.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.512k.ld rename to tools/sdk/ld/eagle.flash.512k.ld.h index 44ecf057d5..66d5f68321 100644 --- a/tools/sdk/ld/eagle.flash.512k.ld +++ b/tools/sdk/ld/eagle.flash.512k.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k128.ld b/tools/sdk/ld/eagle.flash.512k128.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.512k128.ld rename to tools/sdk/ld/eagle.flash.512k128.ld.h index 63c5a4c6e4..6c1c1f757e 100644 --- a/tools/sdk/ld/eagle.flash.512k128.ld +++ b/tools/sdk/ld/eagle.flash.512k128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x59ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k32.ld b/tools/sdk/ld/eagle.flash.512k32.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.512k32.ld rename to tools/sdk/ld/eagle.flash.512k32.ld.h index ef031f4cd2..6fced18369 100644 --- a/tools/sdk/ld/eagle.flash.512k32.ld +++ b/tools/sdk/ld/eagle.flash.512k32.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x71ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k64.ld b/tools/sdk/ld/eagle.flash.512k64.ld.h similarity index 98% rename from tools/sdk/ld/eagle.flash.512k64.ld rename to tools/sdk/ld/eagle.flash.512k64.ld.h index 3cd80b5da1..57755446b6 100644 --- a/tools/sdk/ld/eagle.flash.512k64.ld +++ b/tools/sdk/ld/eagle.flash.512k64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x69ff0 } diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld b/tools/sdk/ld/eagle.flash.8m6m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.8m6m.ld rename to tools/sdk/ld/eagle.flash.8m6m.ld.h index 1077454228..ec3701ab62 100644 --- a/tools/sdk/ld/eagle.flash.8m6m.ld +++ b/tools/sdk/ld/eagle.flash.8m6m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld b/tools/sdk/ld/eagle.flash.8m7m.ld.h similarity index 99% rename from tools/sdk/ld/eagle.flash.8m7m.ld rename to tools/sdk/ld/eagle.flash.8m7m.ld.h index 099f801f1d..b261f7f07d 100644 --- a/tools/sdk/ld/eagle.flash.8m7m.ld +++ b/tools/sdk/ld/eagle.flash.8m7m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0x8000 + iram1_0_seg : org = 0x40100000, len = IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } From 57043bd41aac0961627b9daf4a1831edb57683a7 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 4 Feb 2020 08:29:40 -0800 Subject: [PATCH 02/48] Style corrections Added MMU_ qualifier to new defines. Moved changes into their own file. Don't know how to fix platformio issue. --- boards.txt | 198 +++++++++---------- cores/esp8266/Arduino.h | 4 + cores/esp8266/core_esp8266_features.cpp | 28 --- cores/esp8266/core_esp8266_features.h | 3 - cores/esp8266/mmu_iram.cpp | 52 +++++ cores/esp8266/mmu_iram.h | 40 ++++ libraries/esp8266/examples/MMU48K/MMU48K.ino | 42 ++-- tools/boards.txt.py | 8 +- tools/sdk/ld/eagle.flash.16m14m.ld.h | 2 +- tools/sdk/ld/eagle.flash.16m15m.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m128.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m144.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m160.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m192.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m256.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m512.ld.h | 2 +- tools/sdk/ld/eagle.flash.1m64.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m128.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m1m.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m256.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m512.ld.h | 2 +- tools/sdk/ld/eagle.flash.2m64.ld.h | 2 +- tools/sdk/ld/eagle.flash.4m.ld.h | 2 +- tools/sdk/ld/eagle.flash.4m1m.ld.h | 2 +- tools/sdk/ld/eagle.flash.4m2m.ld.h | 2 +- tools/sdk/ld/eagle.flash.4m3m.ld.h | 2 +- tools/sdk/ld/eagle.flash.512k.ld.h | 2 +- tools/sdk/ld/eagle.flash.512k128.ld.h | 2 +- tools/sdk/ld/eagle.flash.512k32.ld.h | 2 +- tools/sdk/ld/eagle.flash.512k64.ld.h | 2 +- tools/sdk/ld/eagle.flash.8m6m.ld.h | 2 +- tools/sdk/ld/eagle.flash.8m7m.ld.h | 2 +- 34 files changed, 250 insertions(+), 177 deletions(-) create mode 100644 cores/esp8266/mmu_iram.cpp create mode 100644 cores/esp8266/mmu_iram.h diff --git a/boards.txt b/boards.txt index 26ce96fb50..3b107ba437 100644 --- a/boards.txt +++ b/boards.txt @@ -63,11 +63,11 @@ generic.menu.ssl.all.build.sslflags= generic.menu.ssl.basic=Basic SSL ciphers (lower ROM use) generic.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC generic.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -generic.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +generic.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 generic.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -generic.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +generic.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -generic.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +generic.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 generic.menu.ResetMethod.nodemcu=dtr (aka nodemcu) generic.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset generic.menu.ResetMethod.ck=no dtr (aka ck) @@ -544,11 +544,11 @@ esp8285.menu.ssl.all.build.sslflags= esp8285.menu.ssl.basic=Basic SSL ciphers (lower ROM use) esp8285.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC esp8285.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -esp8285.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +esp8285.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp8285.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -esp8285.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +esp8285.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -esp8285.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +esp8285.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp8285.menu.ResetMethod.nodemcu=dtr (aka nodemcu) esp8285.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset esp8285.menu.ResetMethod.ck=no dtr (aka ck) @@ -834,11 +834,11 @@ espduino.menu.ssl.all.build.sslflags= espduino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espduino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espduino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espduino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espduino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espduino.build.flash_mode=dio espduino.build.flash_flags=-DFLASHMODE_DIO espduino.build.flash_freq=40 @@ -1032,11 +1032,11 @@ huzzah.menu.ssl.all.build.sslflags= huzzah.menu.ssl.basic=Basic SSL ciphers (lower ROM use) huzzah.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC huzzah.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -huzzah.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +huzzah.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 huzzah.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -huzzah.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +huzzah.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -huzzah.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +huzzah.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 huzzah.upload.resetmethod=--before default_reset --after hard_reset huzzah.build.flash_mode=qio huzzah.build.flash_flags=-DFLASHMODE_QIO @@ -1231,11 +1231,11 @@ inventone.menu.ssl.all.build.sslflags= inventone.menu.ssl.basic=Basic SSL ciphers (lower ROM use) inventone.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC inventone.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -inventone.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +inventone.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 inventone.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -inventone.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +inventone.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -inventone.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +inventone.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 inventone.upload.resetmethod=--before default_reset --after hard_reset inventone.build.flash_mode=dio inventone.build.flash_flags=-DFLASHMODE_DIO @@ -1430,11 +1430,11 @@ cw01.menu.ssl.all.build.sslflags= cw01.menu.ssl.basic=Basic SSL ciphers (lower ROM use) cw01.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC cw01.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -cw01.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +cw01.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 cw01.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -cw01.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +cw01.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -cw01.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +cw01.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 cw01.upload.resetmethod=--before default_reset --after hard_reset cw01.menu.CrystalFreq.26=26 MHz cw01.menu.CrystalFreq.40=40 MHz @@ -1632,11 +1632,11 @@ espresso_lite_v1.menu.ssl.all.build.sslflags= espresso_lite_v1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espresso_lite_v1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espresso_lite_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espresso_lite_v1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espresso_lite_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v1.build.flash_mode=dio espresso_lite_v1.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v1.build.flash_freq=40 @@ -1834,11 +1834,11 @@ espresso_lite_v2.menu.ssl.all.build.sslflags= espresso_lite_v2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espresso_lite_v2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espresso_lite_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espresso_lite_v2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espresso_lite_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v2.build.flash_mode=dio espresso_lite_v2.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v2.build.flash_freq=40 @@ -2036,11 +2036,11 @@ phoenix_v1.menu.ssl.all.build.sslflags= phoenix_v1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) phoenix_v1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC phoenix_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -phoenix_v1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +phoenix_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -phoenix_v1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +phoenix_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -phoenix_v1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +phoenix_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v1.build.flash_mode=dio phoenix_v1.build.flash_flags=-DFLASHMODE_DIO phoenix_v1.build.flash_freq=40 @@ -2238,11 +2238,11 @@ phoenix_v2.menu.ssl.all.build.sslflags= phoenix_v2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) phoenix_v2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC phoenix_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -phoenix_v2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +phoenix_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -phoenix_v2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +phoenix_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -phoenix_v2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +phoenix_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v2.build.flash_mode=dio phoenix_v2.build.flash_flags=-DFLASHMODE_DIO phoenix_v2.build.flash_freq=40 @@ -2440,11 +2440,11 @@ nodemcu.menu.ssl.all.build.sslflags= nodemcu.menu.ssl.basic=Basic SSL ciphers (lower ROM use) nodemcu.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC nodemcu.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -nodemcu.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +nodemcu.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcu.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -nodemcu.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +nodemcu.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -nodemcu.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +nodemcu.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcu.upload.resetmethod=--before default_reset --after hard_reset nodemcu.build.flash_mode=qio nodemcu.build.flash_flags=-DFLASHMODE_QIO @@ -2639,11 +2639,11 @@ nodemcuv2.menu.ssl.all.build.sslflags= nodemcuv2.menu.ssl.basic=Basic SSL ciphers (lower ROM use) nodemcuv2.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC nodemcuv2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -nodemcuv2.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +nodemcuv2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcuv2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -nodemcuv2.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +nodemcuv2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -nodemcuv2.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +nodemcuv2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcuv2.upload.resetmethod=--before default_reset --after hard_reset nodemcuv2.build.flash_mode=dio nodemcuv2.build.flash_flags=-DFLASHMODE_DIO @@ -2842,11 +2842,11 @@ modwifi.menu.ssl.all.build.sslflags= modwifi.menu.ssl.basic=Basic SSL ciphers (lower ROM use) modwifi.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC modwifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -modwifi.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +modwifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 modwifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -modwifi.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +modwifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -modwifi.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +modwifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 modwifi.upload.resetmethod=--before no_reset --after soft_reset modwifi.build.flash_mode=qio modwifi.build.flash_flags=-DFLASHMODE_QIO @@ -3061,11 +3061,11 @@ thing.menu.ssl.all.build.sslflags= thing.menu.ssl.basic=Basic SSL ciphers (lower ROM use) thing.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC thing.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -thing.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +thing.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thing.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -thing.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +thing.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -thing.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +thing.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thing.upload.resetmethod=--before no_reset --after soft_reset thing.build.flash_mode=qio thing.build.flash_flags=-DFLASHMODE_QIO @@ -3260,11 +3260,11 @@ thingdev.menu.ssl.all.build.sslflags= thingdev.menu.ssl.basic=Basic SSL ciphers (lower ROM use) thingdev.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC thingdev.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -thingdev.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +thingdev.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thingdev.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -thingdev.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +thingdev.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -thingdev.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +thingdev.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thingdev.upload.resetmethod=--before default_reset --after hard_reset thingdev.build.flash_mode=dio thingdev.build.flash_flags=-DFLASHMODE_DIO @@ -3459,11 +3459,11 @@ blynk.menu.ssl.all.build.sslflags= blynk.menu.ssl.basic=Basic SSL ciphers (lower ROM use) blynk.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC blynk.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -blynk.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +blynk.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 blynk.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -blynk.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +blynk.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -blynk.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +blynk.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 blynk.upload.resetmethod=--before default_reset --after hard_reset blynk.build.flash_mode=qio blynk.build.flash_flags=-DFLASHMODE_QIO @@ -3658,11 +3658,11 @@ esp210.menu.ssl.all.build.sslflags= esp210.menu.ssl.basic=Basic SSL ciphers (lower ROM use) esp210.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC esp210.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -esp210.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +esp210.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp210.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -esp210.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +esp210.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -esp210.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +esp210.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp210.upload.resetmethod=--before no_reset --after soft_reset esp210.build.flash_mode=qio esp210.build.flash_flags=-DFLASHMODE_QIO @@ -3857,11 +3857,11 @@ d1_mini.menu.ssl.all.build.sslflags= d1_mini.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC d1_mini.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -d1_mini.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -d1_mini.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -d1_mini.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +d1_mini.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini.upload.resetmethod=--before default_reset --after hard_reset d1_mini.build.flash_mode=dio d1_mini.build.flash_flags=-DFLASHMODE_DIO @@ -4056,11 +4056,11 @@ d1_mini_pro.menu.ssl.all.build.sslflags= d1_mini_pro.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini_pro.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC d1_mini_pro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -d1_mini_pro.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini_pro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_pro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -d1_mini_pro.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini_pro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -d1_mini_pro.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +d1_mini_pro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_pro.upload.resetmethod=--before default_reset --after hard_reset d1_mini_pro.build.flash_mode=dio d1_mini_pro.build.flash_flags=-DFLASHMODE_DIO @@ -4238,11 +4238,11 @@ d1_mini_lite.menu.ssl.all.build.sslflags= d1_mini_lite.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1_mini_lite.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC d1_mini_lite.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -d1_mini_lite.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1_mini_lite.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_lite.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -d1_mini_lite.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1_mini_lite.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -d1_mini_lite.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +d1_mini_lite.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_lite.upload.resetmethod=--before default_reset --after hard_reset d1_mini_lite.build.flash_mode=dout d1_mini_lite.build.flash_flags=-DFLASHMODE_DOUT @@ -4477,11 +4477,11 @@ d1.menu.ssl.all.build.sslflags= d1.menu.ssl.basic=Basic SSL ciphers (lower ROM use) d1.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC d1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -d1.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +d1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -d1.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +d1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -d1.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +d1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1.upload.resetmethod=--before default_reset --after hard_reset d1.build.flash_mode=dio d1.build.flash_flags=-DFLASHMODE_DIO @@ -4676,11 +4676,11 @@ espino.menu.ssl.all.build.sslflags= espino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espino.menu.ResetMethod.nodemcu=dtr (aka nodemcu) espino.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset espino.menu.ResetMethod.ck=no dtr (aka ck) @@ -4878,11 +4878,11 @@ espinotee.menu.ssl.all.build.sslflags= espinotee.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espinotee.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espinotee.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espinotee.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espinotee.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espinotee.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espinotee.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espinotee.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espinotee.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espinotee.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espinotee.upload.resetmethod=--before default_reset --after hard_reset espinotee.build.flash_mode=qio espinotee.build.flash_flags=-DFLASHMODE_QIO @@ -5094,11 +5094,11 @@ wifinfo.menu.ssl.all.build.sslflags= wifinfo.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifinfo.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC wifinfo.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -wifinfo.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifinfo.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifinfo.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -wifinfo.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifinfo.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -wifinfo.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +wifinfo.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifinfo.upload.resetmethod=--before default_reset --after hard_reset wifinfo.build.flash_mode=qio wifinfo.build.flash_flags=-DFLASHMODE_QIO @@ -5352,11 +5352,11 @@ arduino-esp8266.menu.ssl.all.build.sslflags= arduino-esp8266.menu.ssl.basic=Basic SSL ciphers (lower ROM use) arduino-esp8266.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC arduino-esp8266.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -arduino-esp8266.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +arduino-esp8266.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 arduino-esp8266.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -arduino-esp8266.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +arduino-esp8266.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -arduino-esp8266.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +arduino-esp8266.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 arduino-esp8266.upload.resetmethod=--before no_reset --after soft_reset arduino-esp8266.build.flash_mode=qio arduino-esp8266.build.flash_flags=-DFLASHMODE_QIO @@ -5552,11 +5552,11 @@ gen4iod.menu.ssl.all.build.sslflags= gen4iod.menu.ssl.basic=Basic SSL ciphers (lower ROM use) gen4iod.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC gen4iod.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -gen4iod.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +gen4iod.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 gen4iod.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -gen4iod.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +gen4iod.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -gen4iod.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +gen4iod.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 gen4iod.upload.resetmethod=--before default_reset --after hard_reset gen4iod.build.flash_mode=dio gen4iod.build.flash_flags=-DFLASHMODE_DIO @@ -5752,11 +5752,11 @@ oak.menu.ssl.all.build.sslflags= oak.menu.ssl.basic=Basic SSL ciphers (lower ROM use) oak.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC oak.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -oak.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +oak.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 oak.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -oak.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +oak.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -oak.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +oak.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 oak.upload.resetmethod=--before no_reset --after soft_reset oak.build.flash_mode=dio oak.build.flash_flags=-DFLASHMODE_DIO @@ -5951,11 +5951,11 @@ wifiduino.menu.ssl.all.build.sslflags= wifiduino.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifiduino.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC wifiduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -wifiduino.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifiduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifiduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -wifiduino.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifiduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -wifiduino.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +wifiduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifiduino.upload.resetmethod=--before default_reset --after hard_reset wifiduino.build.flash_mode=dio wifiduino.build.flash_flags=-DFLASHMODE_DIO @@ -6150,11 +6150,11 @@ wifi_slot.menu.ssl.all.build.sslflags= wifi_slot.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wifi_slot.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC wifi_slot.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -wifi_slot.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wifi_slot.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifi_slot.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -wifi_slot.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wifi_slot.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -wifi_slot.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +wifi_slot.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifi_slot.upload.resetmethod=--before default_reset --after hard_reset wifi_slot.menu.FlashFreq.40=40MHz wifi_slot.menu.FlashFreq.40.build.flash_freq=40 @@ -6463,11 +6463,11 @@ wiolink.menu.ssl.all.build.sslflags= wiolink.menu.ssl.basic=Basic SSL ciphers (lower ROM use) wiolink.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC wiolink.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -wiolink.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +wiolink.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wiolink.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -wiolink.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +wiolink.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -wiolink.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +wiolink.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wiolink.upload.resetmethod=--before default_reset --after hard_reset wiolink.build.flash_mode=qio wiolink.build.flash_flags=-DFLASHMODE_QIO @@ -6662,11 +6662,11 @@ espectro.menu.ssl.all.build.sslflags= espectro.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espectro.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espectro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espectro.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espectro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espectro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espectro.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espectro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espectro.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espectro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espectro.upload.resetmethod=--before default_reset --after hard_reset espectro.build.flash_mode=dio espectro.build.flash_flags=-DFLASHMODE_DIO @@ -6871,11 +6871,11 @@ sonoff.menu.ssl.all.build.sslflags= sonoff.menu.ssl.basic=Basic SSL ciphers (lower ROM use) sonoff.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC sonoff.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -sonoff.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +sonoff.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 sonoff.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -sonoff.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +sonoff.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -sonoff.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +sonoff.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 sonoff.upload.resetmethod=--before no_reset --after soft_reset sonoff.build.flash_mode=dout sonoff.build.flash_flags=-DFLASHMODE_DOUT @@ -7111,11 +7111,11 @@ espmxdevkit.menu.ssl.all.build.sslflags= espmxdevkit.menu.ssl.basic=Basic SSL ciphers (lower ROM use) espmxdevkit.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC espmxdevkit.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) -espmxdevkit.menu.mmu.3232.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000 +espmxdevkit.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espmxdevkit.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) -espmxdevkit.menu.mmu.4816.build.mmuflags=-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000 +espmxdevkit.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) -espmxdevkit.menu.mmu.3216.build.mmuflags=-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000 +espmxdevkit.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espmxdevkit.upload.resetmethod=--before default_reset --after hard_reset espmxdevkit.build.flash_mode=dout espmxdevkit.build.flash_flags=-DFLASHMODE_DOUT diff --git a/cores/esp8266/Arduino.h b/cores/esp8266/Arduino.h index 54919ba100..fa8f1a7967 100644 --- a/cores/esp8266/Arduino.h +++ b/cores/esp8266/Arduino.h @@ -246,6 +246,10 @@ const int TIM_DIV265 __attribute__((deprecated, weak)) = TIM_DIV256; #include "Updater.h" #include "debug.h" + +#include "mmu_iram.h" + + using std::min; using std::max; using std::isinf; diff --git a/cores/esp8266/core_esp8266_features.cpp b/cores/esp8266/core_esp8266_features.cpp index ea6a9e44b4..03396e5008 100644 --- a/cores/esp8266/core_esp8266_features.cpp +++ b/cores/esp8266/core_esp8266_features.cpp @@ -21,7 +21,6 @@ */ #include -#include /* precache() * pre-loads flash data into the flash cache @@ -46,33 +45,6 @@ void precache(void *f, uint32_t bytes) { (void)x; } - - -int Cache_Read_Enable_status = -1; - -#if (ICACHE_SIZE == 0x4000) -#define SOC_CACHE_SIZE 0 // 16KB -// #define SOC_CACHE_SIZE 1 // 32KB - -#pragma message("ICACHE size 16K") - - -#ifndef ROM_Cache_Read_Enable -#define ROM_Cache_Read_Enable 0x40004678 -#endif - -typedef void (*fp_Cache_Read_Enable_t)(uint32_t map, uint32_t p, uint32_t v); -constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; -/* - * Override SDK's ICACHE size - */ -void IRAM_ATTR Cache_Read_Enable(uint32_t map, uint32_t p, uint32_t v) { - (void)v; - real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); - Cache_Read_Enable_status = SOC_CACHE_SIZE; -} -#endif - #ifdef __cplusplus } #endif diff --git a/cores/esp8266/core_esp8266_features.h b/cores/esp8266/core_esp8266_features.h index dae34f6f8d..d3b70f3dcc 100644 --- a/cores/esp8266/core_esp8266_features.h +++ b/cores/esp8266/core_esp8266_features.h @@ -112,9 +112,6 @@ extern "C" { void precache(void *f, uint32_t bytes); -void Cache_Read_Enable(uint32_t map, uint32_t p, uint32_t v); -extern int Cache_Read_Enable_status; - #ifdef __cplusplus } #endif diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp new file mode 100644 index 0000000000..bf09134ecf --- /dev/null +++ b/cores/esp8266/mmu_iram.cpp @@ -0,0 +1,52 @@ +/* + * Copyright 2020 M Hightower + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Arduino.h" +#include "mmu_iram.h" + +extern "C" { + +int Cache_Read_Enable_status = -1; + +mmu_cre_status_t mmu_status __attribute__((section(".noinit"))); + +#if (MMU_ICACHE_SIZE == 0x4000) +#define SOC_CACHE_SIZE 0 // 16KB +// #define SOC_CACHE_SIZE 1 // 32KB + +#pragma message("ICACHE size 16K") + + +#ifndef ROM_Cache_Read_Enable +#define ROM_Cache_Read_Enable 0x40004678 +#endif + +typedef void (*fp_Cache_Read_Enable_t)(uint8_t map, uint8_t p, uint8_t v); +constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; +/* + * Override SDK's ICACHE size + */ +void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { + mmu_status.map = map; + mmu_status.p = p; + mmu_status.v = v; + real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); + mmu_status.v_cfg = SOC_CACHE_SIZE; + Cache_Read_Enable_status = SOC_CACHE_SIZE; +} +#endif + +}; diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h new file mode 100644 index 0000000000..1d24e0aeae --- /dev/null +++ b/cores/esp8266/mmu_iram.h @@ -0,0 +1,40 @@ +/* + * Copyright 2020 M Hightower + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MMU_IRAM_H +#define MMU_IRAM_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct MMU_CRE_STATUS { + uint32_t v_cfg; + uint32_t map; + uint32_t p; + uint32_t v; +} mmu_cre_status_t; + +extern mmu_cre_status_t mmu_status; +extern int Cache_Read_Enable_status; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 18e41f5eec..4a5f6cf14d 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -8,14 +8,14 @@ */ -#if (IRAM_SIZE > 32*1024) +#if (MMU_IRAM_SIZE > 32*1024) uint32_t gobble[4 * 1024] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); #endif -#ifdef SEC_HEAP -constexpr uint32_t *gobble = (uint32_t *)SEC_HEAP; -constexpr size_t gobble_sz = SEC_HEAP_SIZE; +#ifdef MMU_SEC_HEAP +constexpr uint32_t *gobble = (uint32_t *)MMU_SEC_HEAP; +constexpr size_t gobble_sz = MMU_SEC_HEAP_SIZE; #endif bool isValid(uint32_t *probe) { @@ -25,7 +25,7 @@ bool isValid(uint32_t *probe) { uint32_t saveData = *probe; for (size_t i = 0; i < 32; i++) { *probe = BIT(i); - asm volatile ("" ::: "memory"); + asm volatile("" ::: "memory"); uint32_t val = *probe; if (val != BIT(i)) { ets_uart_printf(" Read 0x%08X != Wrote 0x%08X\n", val, (uint32_t)BIT(i)); @@ -60,33 +60,41 @@ void setup() { WiFi.mode(WIFI_OFF); Serial.begin(115200); delay(20); - Serial.printf_P(PSTR("\n\nI am Alive!\n")); + Serial.printf_P(PSTR("\n\nSetup ...\n")); Serial.printf_P(PSTR("\nMMU Configuration\n")); Serial.printf_P(PSTR(" Cache_Read_Enable status %d\n"), Cache_Read_Enable_status); -#ifdef ICACHE_SIZE - Serial.printf_P(PSTR(" ICACHE Size: %u\n"), ICACHE_SIZE); +#ifdef MMU_ICACHE_SIZE + Serial.printf_P(PSTR(" ICACHE Size: %u\n"), MMU_ICACHE_SIZE); #endif -#ifdef IRAM_SIZE - Serial.printf_P(PSTR(" IRAM Size: %u\n"), IRAM_SIZE); +#ifdef MMU_IRAM_SIZE + Serial.printf_P(PSTR(" IRAM Size: %u\n"), MMU_IRAM_SIZE); #endif -#ifdef SEC_HEAP - Serial.printf_P(PSTR(" Secondary Heap at: %p\n"), SEC_HEAP); - Serial.printf_P(PSTR(" Secondary Heap Size: %u\n"), SEC_HEAP_SIZE); +#ifdef MMU_SEC_HEAP + Serial.printf_P(PSTR(" Secondary Heap at: %p\n"), MMU_SEC_HEAP); + Serial.printf_P(PSTR(" Secondary Heap Size: %u\n"), MMU_SEC_HEAP_SIZE); #endif + constexpr uint32_t volatile *dport_ = (uint32_t volatile *)0x3FF00000; + uint32_t dport_6 = dport_[9]; + if (0 == (dport_6 & 0x10)) { + Serial.printf_P(PSTR(" IRAM block mapped to: 0x40108000\n")); + } + if (0 == (dport_6 & 0x08)) { + Serial.printf_P(PSTR(" IRAM block mapped to: 0x4010C000\n")); + } -#if (IRAM_SIZE > 0x8000) || defined(SEC_HEAP) +#if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_SEC_HEAP) if (isValid(gobble)) { // Put something in our new memory - for (size_t i = 0; i < (gobble_sz/4); i++) { + for (size_t i = 0; i < (gobble_sz / 4); i++) { gobble[i] = (uint32_t)&gobble[i]; } } // Now is it there? dump_mem(gobble, 32); - dump_mem(&gobble[gobble_sz/4/2], 32); - dump_mem(&gobble[gobble_sz/4 - 32], 32); + dump_mem(&gobble[gobble_sz / 4 / 2], 32); + dump_mem(&gobble[gobble_sz / 4 - 32], 32); #endif // Lets peak over the edge diff --git a/tools/boards.txt.py b/tools/boards.txt.py index b8991015c6..c1fe6a2b64 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1190,11 +1190,11 @@ 'mmu_menu': collections.OrderedDict([ ( '.menu.mmu.3232', '32KB cache + 32KB IRAM (balanced)' ), - ( '.menu.mmu.3232.build.mmuflags', '-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x8000'), + ( '.menu.mmu.3232.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000'), ( '.menu.mmu.4816', '16KB cache + 48KB IRAM (IRAM)' ), - ( '.menu.mmu.4816.build.mmuflags', '-DIRAM_SIZE=0xC000 -DICACHE_SIZE=0x4000' ), + ( '.menu.mmu.4816.build.mmuflags', '-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000' ), ( '.menu.mmu.3216', '16KB cache + 32KB IRAM + 16KB sec heap (Heap)' ), - ( '.menu.mmu.3216.build.mmuflags', '-DIRAM_SIZE=0x8000 -DICACHE_SIZE=0x4000 -DSEC_HEAP=0x40108000 -DSEC_HEAP_SIZE=0x4000' ), + ( '.menu.mmu.3216.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000' ), ]), } @@ -1367,7 +1367,7 @@ def flash_map (flashsize_kb, fs_kb = 0): print("{") print(" dport0_0_seg : org = 0x3FF00000, len = 0x10") print(" dram0_0_seg : org = 0x3FFE8000, len = 0x14000") - print(" iram1_0_seg : org = 0x40100000, len = IRAM_SIZE") + print(" iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE") print(" irom0_0_seg : org = 0x40201010, len = 0x%x" % max_upload_size) print("}") print("") diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld.h b/tools/sdk/ld/eagle.flash.16m14m.ld.h index b2f7556bad..174a4b1c51 100644 --- a/tools/sdk/ld/eagle.flash.16m14m.ld.h +++ b/tools/sdk/ld/eagle.flash.16m14m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld.h b/tools/sdk/ld/eagle.flash.16m15m.ld.h index b0d14bbb3c..011280a498 100644 --- a/tools/sdk/ld/eagle.flash.16m15m.ld.h +++ b/tools/sdk/ld/eagle.flash.16m15m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.1m.ld.h b/tools/sdk/ld/eagle.flash.1m.ld.h index d90c0f297a..81cc98ef87 100644 --- a/tools/sdk/ld/eagle.flash.1m.ld.h +++ b/tools/sdk/ld/eagle.flash.1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xf9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m128.ld.h b/tools/sdk/ld/eagle.flash.1m128.ld.h index 2e299a03c5..0bd9c3b0f6 100644 --- a/tools/sdk/ld/eagle.flash.1m128.ld.h +++ b/tools/sdk/ld/eagle.flash.1m128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m144.ld.h b/tools/sdk/ld/eagle.flash.1m144.ld.h index ed29e04de6..8e1601fa25 100644 --- a/tools/sdk/ld/eagle.flash.1m144.ld.h +++ b/tools/sdk/ld/eagle.flash.1m144.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd5ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m160.ld.h b/tools/sdk/ld/eagle.flash.1m160.ld.h index 4b9af5f3e1..2295f7ad47 100644 --- a/tools/sdk/ld/eagle.flash.1m160.ld.h +++ b/tools/sdk/ld/eagle.flash.1m160.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xd1ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m192.ld.h b/tools/sdk/ld/eagle.flash.1m192.ld.h index 0747eff0af..77b136074a 100644 --- a/tools/sdk/ld/eagle.flash.1m192.ld.h +++ b/tools/sdk/ld/eagle.flash.1m192.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xc9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m256.ld.h b/tools/sdk/ld/eagle.flash.1m256.ld.h index e0fc9a95b6..8e0517c9f3 100644 --- a/tools/sdk/ld/eagle.flash.1m256.ld.h +++ b/tools/sdk/ld/eagle.flash.1m256.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xb9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m512.ld.h b/tools/sdk/ld/eagle.flash.1m512.ld.h index d0cb913f6a..39c5bf7b4d 100644 --- a/tools/sdk/ld/eagle.flash.1m512.ld.h +++ b/tools/sdk/ld/eagle.flash.1m512.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m64.ld.h b/tools/sdk/ld/eagle.flash.1m64.ld.h index 1248031d9a..428eba4550 100644 --- a/tools/sdk/ld/eagle.flash.1m64.ld.h +++ b/tools/sdk/ld/eagle.flash.1m64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xe9ff0 } diff --git a/tools/sdk/ld/eagle.flash.2m.ld.h b/tools/sdk/ld/eagle.flash.2m.ld.h index 7ce1948640..148939d978 100644 --- a/tools/sdk/ld/eagle.flash.2m.ld.h +++ b/tools/sdk/ld/eagle.flash.2m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m128.ld.h b/tools/sdk/ld/eagle.flash.2m128.ld.h index 9b2c61db61..86ac5acf96 100644 --- a/tools/sdk/ld/eagle.flash.2m128.ld.h +++ b/tools/sdk/ld/eagle.flash.2m128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld.h b/tools/sdk/ld/eagle.flash.2m1m.ld.h index 95569d0ca6..7b9d72f568 100644 --- a/tools/sdk/ld/eagle.flash.2m1m.ld.h +++ b/tools/sdk/ld/eagle.flash.2m1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m256.ld.h b/tools/sdk/ld/eagle.flash.2m256.ld.h index 432175e8cd..7330204bda 100644 --- a/tools/sdk/ld/eagle.flash.2m256.ld.h +++ b/tools/sdk/ld/eagle.flash.2m256.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m512.ld.h b/tools/sdk/ld/eagle.flash.2m512.ld.h index 7109316e85..a2fe0b1a59 100644 --- a/tools/sdk/ld/eagle.flash.2m512.ld.h +++ b/tools/sdk/ld/eagle.flash.2m512.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m64.ld.h b/tools/sdk/ld/eagle.flash.2m64.ld.h index 6303d89b3d..cbec1093c9 100644 --- a/tools/sdk/ld/eagle.flash.2m64.ld.h +++ b/tools/sdk/ld/eagle.flash.2m64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m.ld.h b/tools/sdk/ld/eagle.flash.4m.ld.h index ad96b432dd..b90edca998 100644 --- a/tools/sdk/ld/eagle.flash.4m.ld.h +++ b/tools/sdk/ld/eagle.flash.4m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld.h b/tools/sdk/ld/eagle.flash.4m1m.ld.h index 1d71422f7b..408ff297e2 100644 --- a/tools/sdk/ld/eagle.flash.4m1m.ld.h +++ b/tools/sdk/ld/eagle.flash.4m1m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld.h b/tools/sdk/ld/eagle.flash.4m2m.ld.h index 2f7d238ff9..5122bf2f2f 100644 --- a/tools/sdk/ld/eagle.flash.4m2m.ld.h +++ b/tools/sdk/ld/eagle.flash.4m2m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld.h b/tools/sdk/ld/eagle.flash.4m3m.ld.h index fa06d982b4..ef1753f0a1 100644 --- a/tools/sdk/ld/eagle.flash.4m3m.ld.h +++ b/tools/sdk/ld/eagle.flash.4m3m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.512k.ld.h b/tools/sdk/ld/eagle.flash.512k.ld.h index 66d5f68321..977b2346be 100644 --- a/tools/sdk/ld/eagle.flash.512k.ld.h +++ b/tools/sdk/ld/eagle.flash.512k.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k128.ld.h b/tools/sdk/ld/eagle.flash.512k128.ld.h index 6c1c1f757e..a474e33920 100644 --- a/tools/sdk/ld/eagle.flash.512k128.ld.h +++ b/tools/sdk/ld/eagle.flash.512k128.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x59ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k32.ld.h b/tools/sdk/ld/eagle.flash.512k32.ld.h index 6fced18369..b829917da8 100644 --- a/tools/sdk/ld/eagle.flash.512k32.ld.h +++ b/tools/sdk/ld/eagle.flash.512k32.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x71ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k64.ld.h b/tools/sdk/ld/eagle.flash.512k64.ld.h index 57755446b6..24ea7f69fe 100644 --- a/tools/sdk/ld/eagle.flash.512k64.ld.h +++ b/tools/sdk/ld/eagle.flash.512k64.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0x69ff0 } diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld.h b/tools/sdk/ld/eagle.flash.8m6m.ld.h index ec3701ab62..c6eadba876 100644 --- a/tools/sdk/ld/eagle.flash.8m6m.ld.h +++ b/tools/sdk/ld/eagle.flash.8m6m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld.h b/tools/sdk/ld/eagle.flash.8m7m.ld.h index b261f7f07d..196aed5ecc 100644 --- a/tools/sdk/ld/eagle.flash.8m7m.ld.h +++ b/tools/sdk/ld/eagle.flash.8m7m.ld.h @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE irom0_0_seg : org = 0x40201010, len = 0xfeff0 } From 7424aed1c5c0e423edcb554ee88708daf54d1dc1 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 10 Feb 2020 22:12:43 -0800 Subject: [PATCH 03/48] Added detailed description for Cache_Read_Enable. Updated tools/sizes.py to report correct IRAM size and indicate ICACHE size. Merged in earlephilhower's work on unaligned exception. Refactored and added support for store operations and changed the name to be more closely aligned with its function. Improved crash reporting path. --- boards.txt | 133 ++++++++++++ cores/esp8266/core_esp8266_main.cpp | 10 + cores/esp8266/core_esp8266_non32xfer.cpp | 216 +++++++++++++++++++ cores/esp8266/core_esp8266_non32xfer.h | 15 ++ cores/esp8266/core_esp8266_postmortem.cpp | 6 +- cores/esp8266/esp8266_undocumented.h | 51 +++++ cores/esp8266/mmu_iram.cpp | 120 +++++++++-- cores/esp8266/mmu_iram.h | 62 +++++- libraries/esp8266/examples/MMU48K/MMU48K.ino | 214 +++++++++++++++--- platform.txt | 7 +- tools/boards.txt.py | 11 +- tools/sizes.py | 21 +- 12 files changed, 809 insertions(+), 57 deletions(-) create mode 100644 cores/esp8266/core_esp8266_non32xfer.cpp create mode 100644 cores/esp8266/core_esp8266_non32xfer.h diff --git a/boards.txt b/boards.txt index 3b107ba437..2af1af13f1 100644 --- a/boards.txt +++ b/boards.txt @@ -23,6 +23,7 @@ menu.wipe=Erase Flash menu.sdk=Espressif FW menu.ssl=SSL Support menu.mmu=MMU +menu.non32xfer=Non-32-Bit Access ############################################################## generic.name=Generic ESP8266 Module @@ -68,6 +69,10 @@ generic.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) generic.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) generic.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +generic.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +generic.menu.non32xfer.fast.build.non32xferflags= +generic.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +generic.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER generic.menu.ResetMethod.nodemcu=dtr (aka nodemcu) generic.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset generic.menu.ResetMethod.ck=no dtr (aka ck) @@ -549,6 +554,10 @@ esp8285.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp8285.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) esp8285.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +esp8285.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +esp8285.menu.non32xfer.fast.build.non32xferflags= +esp8285.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +esp8285.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER esp8285.menu.ResetMethod.nodemcu=dtr (aka nodemcu) esp8285.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset esp8285.menu.ResetMethod.ck=no dtr (aka ck) @@ -839,6 +848,10 @@ espduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espduino.menu.non32xfer.fast.build.non32xferflags= +espduino.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espduino.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espduino.build.flash_mode=dio espduino.build.flash_flags=-DFLASHMODE_DIO espduino.build.flash_freq=40 @@ -1037,6 +1050,10 @@ huzzah.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) huzzah.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) huzzah.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +huzzah.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +huzzah.menu.non32xfer.fast.build.non32xferflags= +huzzah.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +huzzah.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER huzzah.upload.resetmethod=--before default_reset --after hard_reset huzzah.build.flash_mode=qio huzzah.build.flash_flags=-DFLASHMODE_QIO @@ -1236,6 +1253,10 @@ inventone.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) inventone.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) inventone.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +inventone.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +inventone.menu.non32xfer.fast.build.non32xferflags= +inventone.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +inventone.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER inventone.upload.resetmethod=--before default_reset --after hard_reset inventone.build.flash_mode=dio inventone.build.flash_flags=-DFLASHMODE_DIO @@ -1435,6 +1456,10 @@ cw01.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) cw01.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) cw01.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +cw01.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +cw01.menu.non32xfer.fast.build.non32xferflags= +cw01.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +cw01.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER cw01.upload.resetmethod=--before default_reset --after hard_reset cw01.menu.CrystalFreq.26=26 MHz cw01.menu.CrystalFreq.40=40 MHz @@ -1637,6 +1662,10 @@ espresso_lite_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espresso_lite_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espresso_lite_v1.menu.non32xfer.fast.build.non32xferflags= +espresso_lite_v1.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espresso_lite_v1.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espresso_lite_v1.build.flash_mode=dio espresso_lite_v1.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v1.build.flash_freq=40 @@ -1839,6 +1868,10 @@ espresso_lite_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espresso_lite_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espresso_lite_v2.menu.non32xfer.fast.build.non32xferflags= +espresso_lite_v2.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espresso_lite_v2.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espresso_lite_v2.build.flash_mode=dio espresso_lite_v2.build.flash_flags=-DFLASHMODE_DIO espresso_lite_v2.build.flash_freq=40 @@ -2041,6 +2074,10 @@ phoenix_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) phoenix_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +phoenix_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +phoenix_v1.menu.non32xfer.fast.build.non32xferflags= +phoenix_v1.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +phoenix_v1.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER phoenix_v1.build.flash_mode=dio phoenix_v1.build.flash_flags=-DFLASHMODE_DIO phoenix_v1.build.flash_freq=40 @@ -2243,6 +2280,10 @@ phoenix_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) phoenix_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +phoenix_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +phoenix_v2.menu.non32xfer.fast.build.non32xferflags= +phoenix_v2.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +phoenix_v2.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER phoenix_v2.build.flash_mode=dio phoenix_v2.build.flash_flags=-DFLASHMODE_DIO phoenix_v2.build.flash_freq=40 @@ -2445,6 +2486,10 @@ nodemcu.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcu.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) nodemcu.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +nodemcu.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +nodemcu.menu.non32xfer.fast.build.non32xferflags= +nodemcu.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +nodemcu.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER nodemcu.upload.resetmethod=--before default_reset --after hard_reset nodemcu.build.flash_mode=qio nodemcu.build.flash_flags=-DFLASHMODE_QIO @@ -2644,6 +2689,10 @@ nodemcuv2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcuv2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) nodemcuv2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +nodemcuv2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +nodemcuv2.menu.non32xfer.fast.build.non32xferflags= +nodemcuv2.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +nodemcuv2.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER nodemcuv2.upload.resetmethod=--before default_reset --after hard_reset nodemcuv2.build.flash_mode=dio nodemcuv2.build.flash_flags=-DFLASHMODE_DIO @@ -2847,6 +2896,10 @@ modwifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) modwifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) modwifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +modwifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +modwifi.menu.non32xfer.fast.build.non32xferflags= +modwifi.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +modwifi.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER modwifi.upload.resetmethod=--before no_reset --after soft_reset modwifi.build.flash_mode=qio modwifi.build.flash_flags=-DFLASHMODE_QIO @@ -3066,6 +3119,10 @@ thing.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thing.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) thing.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +thing.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +thing.menu.non32xfer.fast.build.non32xferflags= +thing.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +thing.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER thing.upload.resetmethod=--before no_reset --after soft_reset thing.build.flash_mode=qio thing.build.flash_flags=-DFLASHMODE_QIO @@ -3265,6 +3322,10 @@ thingdev.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thingdev.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) thingdev.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +thingdev.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +thingdev.menu.non32xfer.fast.build.non32xferflags= +thingdev.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +thingdev.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER thingdev.upload.resetmethod=--before default_reset --after hard_reset thingdev.build.flash_mode=dio thingdev.build.flash_flags=-DFLASHMODE_DIO @@ -3464,6 +3525,10 @@ blynk.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) blynk.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) blynk.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +blynk.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +blynk.menu.non32xfer.fast.build.non32xferflags= +blynk.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +blynk.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER blynk.upload.resetmethod=--before default_reset --after hard_reset blynk.build.flash_mode=qio blynk.build.flash_flags=-DFLASHMODE_QIO @@ -3663,6 +3728,10 @@ esp210.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp210.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) esp210.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +esp210.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +esp210.menu.non32xfer.fast.build.non32xferflags= +esp210.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +esp210.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER esp210.upload.resetmethod=--before no_reset --after soft_reset esp210.build.flash_mode=qio esp210.build.flash_flags=-DFLASHMODE_QIO @@ -3862,6 +3931,10 @@ d1_mini.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +d1_mini.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +d1_mini.menu.non32xfer.fast.build.non32xferflags= +d1_mini.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +d1_mini.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER d1_mini.upload.resetmethod=--before default_reset --after hard_reset d1_mini.build.flash_mode=dio d1_mini.build.flash_flags=-DFLASHMODE_DIO @@ -4061,6 +4134,10 @@ d1_mini_pro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_pro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini_pro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +d1_mini_pro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +d1_mini_pro.menu.non32xfer.fast.build.non32xferflags= +d1_mini_pro.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +d1_mini_pro.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER d1_mini_pro.upload.resetmethod=--before default_reset --after hard_reset d1_mini_pro.build.flash_mode=dio d1_mini_pro.build.flash_flags=-DFLASHMODE_DIO @@ -4243,6 +4320,10 @@ d1_mini_lite.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_lite.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini_lite.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +d1_mini_lite.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +d1_mini_lite.menu.non32xfer.fast.build.non32xferflags= +d1_mini_lite.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +d1_mini_lite.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER d1_mini_lite.upload.resetmethod=--before default_reset --after hard_reset d1_mini_lite.build.flash_mode=dout d1_mini_lite.build.flash_flags=-DFLASHMODE_DOUT @@ -4482,6 +4563,10 @@ d1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +d1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +d1.menu.non32xfer.fast.build.non32xferflags= +d1.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +d1.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER d1.upload.resetmethod=--before default_reset --after hard_reset d1.build.flash_mode=dio d1.build.flash_flags=-DFLASHMODE_DIO @@ -4681,6 +4766,10 @@ espino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espino.menu.non32xfer.fast.build.non32xferflags= +espino.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espino.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espino.menu.ResetMethod.nodemcu=dtr (aka nodemcu) espino.menu.ResetMethod.nodemcu.upload.resetmethod=--before default_reset --after hard_reset espino.menu.ResetMethod.ck=no dtr (aka ck) @@ -4883,6 +4972,10 @@ espinotee.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espinotee.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espinotee.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espinotee.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espinotee.menu.non32xfer.fast.build.non32xferflags= +espinotee.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espinotee.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espinotee.upload.resetmethod=--before default_reset --after hard_reset espinotee.build.flash_mode=qio espinotee.build.flash_flags=-DFLASHMODE_QIO @@ -5099,6 +5192,10 @@ wifinfo.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifinfo.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifinfo.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +wifinfo.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +wifinfo.menu.non32xfer.fast.build.non32xferflags= +wifinfo.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +wifinfo.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER wifinfo.upload.resetmethod=--before default_reset --after hard_reset wifinfo.build.flash_mode=qio wifinfo.build.flash_flags=-DFLASHMODE_QIO @@ -5357,6 +5454,10 @@ arduino-esp8266.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) arduino-esp8266.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) arduino-esp8266.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +arduino-esp8266.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +arduino-esp8266.menu.non32xfer.fast.build.non32xferflags= +arduino-esp8266.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +arduino-esp8266.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER arduino-esp8266.upload.resetmethod=--before no_reset --after soft_reset arduino-esp8266.build.flash_mode=qio arduino-esp8266.build.flash_flags=-DFLASHMODE_QIO @@ -5557,6 +5658,10 @@ gen4iod.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) gen4iod.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) gen4iod.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +gen4iod.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +gen4iod.menu.non32xfer.fast.build.non32xferflags= +gen4iod.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +gen4iod.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER gen4iod.upload.resetmethod=--before default_reset --after hard_reset gen4iod.build.flash_mode=dio gen4iod.build.flash_flags=-DFLASHMODE_DIO @@ -5757,6 +5862,10 @@ oak.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) oak.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) oak.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +oak.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +oak.menu.non32xfer.fast.build.non32xferflags= +oak.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +oak.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER oak.upload.resetmethod=--before no_reset --after soft_reset oak.build.flash_mode=dio oak.build.flash_flags=-DFLASHMODE_DIO @@ -5956,6 +6065,10 @@ wifiduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifiduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifiduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +wifiduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +wifiduino.menu.non32xfer.fast.build.non32xferflags= +wifiduino.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +wifiduino.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER wifiduino.upload.resetmethod=--before default_reset --after hard_reset wifiduino.build.flash_mode=dio wifiduino.build.flash_flags=-DFLASHMODE_DIO @@ -6155,6 +6268,10 @@ wifi_slot.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifi_slot.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifi_slot.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +wifi_slot.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +wifi_slot.menu.non32xfer.fast.build.non32xferflags= +wifi_slot.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +wifi_slot.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER wifi_slot.upload.resetmethod=--before default_reset --after hard_reset wifi_slot.menu.FlashFreq.40=40MHz wifi_slot.menu.FlashFreq.40.build.flash_freq=40 @@ -6468,6 +6585,10 @@ wiolink.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wiolink.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wiolink.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +wiolink.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +wiolink.menu.non32xfer.fast.build.non32xferflags= +wiolink.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +wiolink.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER wiolink.upload.resetmethod=--before default_reset --after hard_reset wiolink.build.flash_mode=qio wiolink.build.flash_flags=-DFLASHMODE_QIO @@ -6667,6 +6788,10 @@ espectro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espectro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espectro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espectro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espectro.menu.non32xfer.fast.build.non32xferflags= +espectro.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espectro.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espectro.upload.resetmethod=--before default_reset --after hard_reset espectro.build.flash_mode=dio espectro.build.flash_flags=-DFLASHMODE_DIO @@ -6876,6 +7001,10 @@ sonoff.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) sonoff.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) sonoff.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +sonoff.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +sonoff.menu.non32xfer.fast.build.non32xferflags= +sonoff.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +sonoff.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER sonoff.upload.resetmethod=--before no_reset --after soft_reset sonoff.build.flash_mode=dout sonoff.build.flash_flags=-DFLASHMODE_DOUT @@ -7116,6 +7245,10 @@ espmxdevkit.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espmxdevkit.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espmxdevkit.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +espmxdevkit.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +espmxdevkit.menu.non32xfer.fast.build.non32xferflags= +espmxdevkit.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +espmxdevkit.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER espmxdevkit.upload.resetmethod=--before default_reset --after hard_reset espmxdevkit.build.flash_mode=dout espmxdevkit.build.flash_flags=-DFLASHMODE_DOUT diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 850d9b95a8..058a47efef 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -34,6 +34,8 @@ extern "C" { } #include #include "gdb_hooks.h" +#include + #define LOOP_TASK_PRIORITY 1 #define LOOP_QUEUE_SIZE 1 @@ -291,6 +293,10 @@ extern "C" void app_entry_redefinable(void) cont_t s_cont __attribute__((aligned(16))); g_pcont = &s_cont; + DBG_MM_PRINT_STATUS(); + + DBG_MMU_PRINT_IRAM_BANK_REG(0); + /* Call the entry point of the SDK code. */ call_user_start(); } @@ -320,6 +326,10 @@ extern "C" void user_init(void) { cont_init(g_pcont); +#ifdef NON32XFER_HANDLER + install_non32xfer_exception_handler(); +#endif + preinit(); // Prior to C++ Dynamic Init (not related to above init() ). Meant to be user redefinable. ets_task(loop_task, diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp new file mode 100644 index 0000000000..0d130ad26e --- /dev/null +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -0,0 +1,216 @@ +/* 020819 + Based on PR https://github.com/esp8266/Arduino/pull/6978 + Enhanced to also handle store operations to iRAM and optional range + validation. Also improved failed path to generate crash report. + And, partially refactored. + + Apologies if this is being pedantic, I was getting confused over these so + I tried to understand what makes them different. + + EXCCAUSE_LOAD_STORE_ERROR 3 is a non-32-bit load or store to an address that + only supports a full 32-bit aligned transfer like IRAM or ICACHE. i.e., No + 8-bit char or 16-bit short transfers allowed. + + EXCCAUSE_UNALIGNED 9 is an exception cause when load or store is not on an + aligned boundary that matches the element's width. + eg. *(short *)0x3FFF8001 = 1; or *(long *)0x3FFF8002 = 1; + + */ + +/* + * This exception handler, allows for byte or short accesses to iRAM or PROGMEM + * to succeed without causing a crash. It is still preferred to use the xxx_P + * macros whenever possible, since they are probably 30x faster than this + * exception handler method. + * + * Code taken directly from @pvvx's public domain code in + * https://github.com/pvvx/esp8266web/blob/master/app/sdklib/system/app_main.c + * + * + */ + +#include +#include +#include +#include +#include +#include + +extern "C" { + +#if 1 +#define ETS_PRINTF ets_uart_printf +#else +#define ETS_PRINTF(...) do {} while(false) +#endif + +#ifndef __MMU_IRAM_H +bool inline is_iram(uint32_t addr) { + (void)addr; + return true; +} + +bool inline is_icache(uint32_t addr) { + (void)addr; + return true; +} +#endif + +#define LOAD_MASK 0x00f00fu +#define L8UI_MATCH 0x000002u +#define L16UI_MATCH 0x001002u +#define L16SI_MATCH 0x009002u +#define S8I_MATCH 0x004002u +#define S16I_MATCH 0x005002u + +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Non 32-bit read/write error */ + +uint32_t mmu_non32xfer_count = 0; +static void warning(void) +{ + DEBUGV("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); +} +static fn_exception_handler_t old_handler = NULL; + +static ICACHE_RAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) +{ + do { + /* + Had to split out some of the asm, compiler was reusing a register that it + needed later. A crash would come or go away with the slightest unrelated + changes elsewhere in the function. + + Register a15 was used for epc1, then clobbered for rsr. Maybe an + __asm("":::"memory") before starting the asm would help for these cases. + For this instance moved setting epc1 closer to where it was used. + */ + uint32_t insn; + __asm( + "movi a4, ~3;" /* prepare a mask for the EPC */ + "and a4, a4, %1;" /* apply mask for 32bit aligned base */ + "l32i a5, a4, 0;" /* load part 1 */ + "l32i a6, a4, 4;" /* load part 2 */ + "ssa8l %1;" /* set up shift register for src op */ + "src %0, a6, a5;" /* right shift to get faulting instruction */ + :"=r"(insn) + :"r"(ef->epc) + :"a4", "a5", "a6" + ); + + /* + This is a concern area - exception handlers are called with interrupts + turned back on by _xtos_c_wrapper_handler. Is there something about an + exception that would prevent the CPU from servicing an interrupt while in + an exception handler? + */ + if (ef->ps & 0x0F) { + ETS_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); +#if 0 + continue; /* fail, not safe for IRQ disabled ?? */ +#endif + } + + uint32_t what = insn & LOAD_MASK; + uint32_t valmask = 0; + + uint32_t is_read = 1; + if (L8UI_MATCH == what || S8I_MATCH == what) { + valmask = 0xffu; + if (S8I_MATCH == what) { + is_read = 0; + } + } else if (L16UI_MATCH == what || L16SI_MATCH == what || S16I_MATCH == what) { + valmask = 0xffffu; + if (S16I_MATCH == what) { + is_read = 0; + } + } else { + continue; /* fail */ + } + + if (0 == mmu_non32xfer_count) { + schedule_function(warning); + } + // Some accounting information so we know this is happending. + if (0 == ++mmu_non32xfer_count) { + --mmu_non32xfer_count; // saturated + } + + int regno = (insn & 0x0000f0u) >> 4; + if (regno == 1) { + continue; /* we can't support storing into a1, just die */ + } else if (regno != 0) { + --regno; /* account for skipped a1 in exception_frame */ + } + + uint32_t excvaddr; + /* read out the faulting address */ + __asm("rsr %0, EXCVADDR;" :"=r"(excvaddr)::); + + /* debug option, validate address so we don't hide memory access bugs in APP */ + if ((is_read && is_icache(excvaddr)) || is_iram(excvaddr)) { + /* all is good */ + } else { + continue; /* fail */ + } + + if (is_read) { + /* Load, shift and mask down to correct size */ + uint32_t val = (*(uint32_t *)(excvaddr & ~0x3)); + val >>= (excvaddr & 0x3) * 8; + val &= valmask; + + /* Sign-extend for L16SI, if applicable */ + if (what == L16SI_MATCH && (val & 0x8000)) { + val |= 0xffff0000; + } + + ef->a_reg[regno] = val; /* carry out the load */ + + } else { /* is write */ + uint32_t val = ef->a_reg[regno]; /* get value to store from register */ + val <<= (excvaddr & 0x3) * 8; + valmask <<= (excvaddr & 0x3) * 8; + val &= valmask; + + /* Load, mask out field, and merge */ + uint32_t dst_val = (*(uint32_t *)(excvaddr & ~0x3)); + dst_val &= (~valmask); + dst_val |= val; + (*(uint32_t *)(excvaddr & ~0x3)) = dst_val; /* carry out the store */ + } + + ef->epc += 3; /* resume at following instruction */ + return; + + } while(false); + +/* Fail request, die */ + /* + The old handler points to the SDK. Be alert for HWDT when Calling with + INTLEVEL != 0. I cannot create it any more. I thought I saw this as a + problem; however, my test case shows no problem ?? Maybe I was confused. + */ + if (old_handler) { // if (0 == (ef->ps & 0x0F)) { + ETS_PRINTF("\ncalling previous load/store handler(%p)\n", old_handler); + old_handler(ef, cause); + return; + } + + /* + Calling _xtos_unhandled_exception(ef, cause) in the Boot ROM, gets us a + hardware wdt. + + Use panic instead as a fall back. It will at least give us a stack trace. + */ + panic(); +} + + +void install_non32xfer_exception_handler(void) +{ + old_handler = + _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, non32xfer_exception_handler); +} + +}; diff --git a/cores/esp8266/core_esp8266_non32xfer.h b/cores/esp8266/core_esp8266_non32xfer.h new file mode 100644 index 0000000000..407fab8d10 --- /dev/null +++ b/cores/esp8266/core_esp8266_non32xfer.h @@ -0,0 +1,15 @@ +#ifndef __CORE_ESP8266_NON32XFER_H +#define __CORE_ESP8266_NON32XFER_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern void install_non32xfer_exception_handler(); +extern uint32_t mmu_non32xfer_count; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/cores/esp8266/core_esp8266_postmortem.cpp b/cores/esp8266/core_esp8266_postmortem.cpp index 0486ee5735..84aad50a0c 100644 --- a/cores/esp8266/core_esp8266_postmortem.cpp +++ b/cores/esp8266/core_esp8266_postmortem.cpp @@ -89,7 +89,7 @@ static void ets_printf_P(const char *str, ...) { vsnprintf(destStr, sizeof(destStr), str, argPtr); va_end(argPtr); while (*c) { - ets_putc(*(c++)); + ets_uart_putc1(*(c++)); } } @@ -147,10 +147,10 @@ void __wrap_system_restart_local() { // (determined empirically, might break) uint32_t offset = 0; if (rst_info.reason == REASON_SOFT_WDT_RST) { - offset = 0x1b0; + offset = 0x1a0; } else if (rst_info.reason == REASON_EXCEPTION_RST) { - offset = 0x1a0; + offset = 0x190; } else if (rst_info.reason == REASON_WDT_RST) { offset = 0x10; diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index 22216d962a..f56c8d4711 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -1,5 +1,8 @@ // ROM and blob calls without official headers available +#ifndef __ESP8266_UNDOCUMENTED_H +#define __ESP8266_UNDOCUMENTED_H + #ifdef __cplusplus extern "C" { #endif @@ -34,6 +37,54 @@ extern int ets_uart_printf(const char *format, ...) __attribute__ ((format (prin extern void ets_delay_us(uint32_t us); +/* The Xtensa OS code in ROM for handling hardware exceptions */ +struct __exception_frame +{ + uint32_t epc; + uint32_t ps; + uint32_t sar; + uint32_t unused; + union { + struct { + uint32_t a0; + // note: no a1 here! + uint32_t a2; + uint32_t a3; + uint32_t a4; + uint32_t a5; + uint32_t a6; + uint32_t a7; + uint32_t a8; + uint32_t a9; + uint32_t a10; + uint32_t a11; + uint32_t a12; + uint32_t a13; + uint32_t a14; + uint32_t a15; + }; + uint32_t a_reg[15]; + }; + uint32_t cause; +}; + +/* + ROM Function, _xtos_set_exception_handler(), installs a "C" callable exception handler. + If reason is out of range, >=64, it returns NULL. + If the new exception handler is installed, it returns the previous handler. + If the previous handler was _xtos_unhandled_exception/_xtos_p_none, it returns + NULL. + + Note, the installed "C" exception handler is called from the + _xtos_c_wrapper_handler with IRQs enabled. + */ +typedef void (*fn_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); +extern fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); + +//D extern void _xtos_unhandled_exception(struct __exception_frame *ef, uint32_t cause); + #ifdef __cplusplus }; #endif + +#endif diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index bf09134ecf..5b3d29470c 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -14,39 +14,135 @@ * limitations under the License. */ + #include "Arduino.h" #include "mmu_iram.h" extern "C" { -int Cache_Read_Enable_status = -1; - -mmu_cre_status_t mmu_status __attribute__((section(".noinit"))); - #if (MMU_ICACHE_SIZE == 0x4000) #define SOC_CACHE_SIZE 0 // 16KB -// #define SOC_CACHE_SIZE 1 // 32KB - #pragma message("ICACHE size 16K") +#else +#define SOC_CACHE_SIZE 1 // 32KB +#endif + +// IS this set as part of segment data at load time? appears to be +mmu_cre_status_t mmu_status = {SOC_CACHE_SIZE, -1, 0, 0, 0, 0, 0}; +// Enable all the time so we can gather information on Cache_Read_Enable usage. +#if 1 //(MMU_ICACHE_SIZE == 0x4000) +/* + * "Cache_Read_Enable" as in Instruction Read Cache enable, ICACHE. + * + * The Boot ROM "Cache_Read_Enable" API enables virtual execution of code in + * flash memory via an instruction cache, ICACHE. The cache size can be set to + * 16K or 32K, and the NONOS SDK 2.x will always set ICACHE to 32K during + * initialization. + * + * When you select a 16K vs. a 32K ICACHE size, you get 48K contiguous IRAM to + * work with. The NONOS SDK 2.x does not have an option to select 16K/32K. This + * is where this Boot ROM wrapper for Cache_Read_Enable comes in. + * Note, there is support for 16K/32K cache size in NONOS SDK 3.0; however, I + * do not see an option to have it has part of your general IRAM. That SDK adds + * it to the heap. + * + * With this wrapper function, we override the SDK's ICACHE size. + * A build-time define MMU_ICACHE_SIZE selects 16K or 32K ICACHE size. + * + * mmu_status is used to help understand calling behavior. At some point, it + * should be trimmed down to the essentials. + * + * During NONOS SDK init, it will call to enable. Then call later, to process a + * spi_flash_get_id request, it will disable/enable around the Boot ROM SPI calls. + * + * + * + * Arguments for Cache_Read_Enable + * + * The first two arguments appear to specify which 1MB block of the flash to + * access with the ICACHE. + * + * The first argument, map, is partly understood. It has three values 0, 1, + * and 2+. The value 0 selects the even 1MB block, and 1 selects the odd 1MB + * block, in other words, bit20 of the flash address. No guesses for a value + * of 2 or greater. + * + * The second argument, p, bit 21 of the flash address. Or, it may be bits 23, + * 22, 21 of the flash address. A three-bit field is cleared in the register + * for this argument; however, I have not seen any examples of it being used + * that way. + * + * The third argument, v, holds our center of attention. A value of 0 selects + * 16K, and a value of 1 selects a 32K ICACHE. This is the only parameter we + * need to modify on Cache_Read_Enable calls. + * + * + * + * Clues and Information sources + * + * "Cache_Read_Enable" is underdocumented. Main sources of information were from + * rboot, zboot, https://richard.burtons.org/2015/06/12/esp8266-cache_read_enable/, + * and other places. And some additional expermentation. + * + * Searching through the NONOS SDK shows nothing on this API; however, some + * clues on what the NONOS SDK might be doing with ICACHE related calls can be + * found in the RTOS SDK. + * eg. ESP8266_RTOS_SDK/blob/master/components/spi_flash/src/spi_flash_raw.c + * also calls to it in the bootloader. + * + */ #ifndef ROM_Cache_Read_Enable #define ROM_Cache_Read_Enable 0x40004678 #endif typedef void (*fp_Cache_Read_Enable_t)(uint8_t map, uint8_t p, uint8_t v); -constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; -/* - * Override SDK's ICACHE size - */ +constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = + (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; + void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { mmu_status.map = map; mmu_status.p = p; mmu_status.v = v; + mmu_status.enable_count++; + mmu_status.state = 1; + if (0 == mmu_status.enable_count) { + mmu_status.enable_count--; // keep saturated value + } + DBG_MMU_PRINT_IRAM_BANK_REG("before"); + real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); - mmu_status.v_cfg = SOC_CACHE_SIZE; - Cache_Read_Enable_status = SOC_CACHE_SIZE; + + DBG_MMU_PRINT_IRAM_BANK_REG("after"); + DBG_MM_PRINT_STATUS(); } + +#ifndef ROM_Cache_Read_Disable +#define ROM_Cache_Read_Disable 0x400047f0 +#endif + +typedef void (*fp_Cache_Read_Disable_t)(void); +constexpr fp_Cache_Read_Disable_t real_Cache_Read_Disable = + (fp_Cache_Read_Disable_t)ROM_Cache_Read_Disable; +/* + * + */ +void IRAM_ATTR Cache_Read_Disable(void) { + + mmu_status.disable_count++; + mmu_status.state = 0; + if (0 == mmu_status.disable_count) { + mmu_status.disable_count--; // keep saturated value + } + DBG_MMU_PRINT_IRAM_BANK_REG("before"); + + real_Cache_Read_Disable(); + + DBG_MMU_PRINT_IRAM_BANK_REG("after"); + DBG_MM_PRINT_STATUS(); +} + #endif }; diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 1d24e0aeae..4555e5d58a 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -14,25 +14,81 @@ * limitations under the License. */ -#ifndef MMU_IRAM_H -#define MMU_IRAM_H +#ifndef __MMU_IRAM_H +#define __MMU_IRAM_H #include #include +#ifdef DEBUG_ESP_CORE +#endif +#define DEBUG_MMU + #ifdef __cplusplus extern "C" { #endif typedef struct MMU_CRE_STATUS { uint32_t v_cfg; + int32_t state; // -1 - not initialized, 0 - disabled, 1 - enabled + uint32_t enable_count; + uint32_t disable_count; uint32_t map; uint32_t p; uint32_t v; } mmu_cre_status_t; extern mmu_cre_status_t mmu_status; -extern int Cache_Read_Enable_status; + +#ifdef DEBUG_MMU +bool inline is_iram(uint32_t addr) { + constexpr uint32_t iram_start = 0x40100000u; + constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; + return (iram_start <= addr && iram_end > addr); +} + +bool inline is_icache(uint32_t addr) { + constexpr uint32_t icache_start = 0x40200000u; + constexpr uint32_t icache_end = icache_start + 0x100000; + return (icache_start <= addr && icache_end > addr); +} + +#else +bool inline is_iram(uint32_t addr) { + (void)addr; + return true; +} + +bool inline is_icache(uint32_t addr) { + (void)addr; + return true; +} +#endif + +#if DEV_DEBUG +#define DBG_MMU_PRINTF ets_uart_printf + +#define DBG_MM_PRINT_STATUS() { \ + DBG_MMU_PRINTF("\nmmu_status = {" \ + "v_cfg = %u, state = %d, enable/disable count = %u/%u, " \ + "map = 0x%02X, p = 0x%02X, v = 0x%02X}\n", \ + mmu_status.v_cfg, mmu_status.state, \ + mmu_status.enable_count, mmu_status.disable_count, \ + mmu_status.map, mmu_status.p, mmu_status.v); \ + ets_delay_us(12000); \ +} + +#define DBG_MMU_PRINT_IRAM_BANK_REG(a) { \ + uint32_t iram_bank_reg = ESP8266_DREG(0x24); \ + DBG_MMU_PRINTF("\niram_bank_reg %s%s0x%08X\n", (0 == a) ? "" : a, (0 == a) ? "" : " Cache_Read_Enable ", iram_bank_reg); \ +} + +#else +#define DBG_MMU_PRINTF(...) do {} while(false) +#define DBG_MM_PRINT_STATUS(...) do {} while(false) +#define DBG_MMU_PRINT_IRAM_BANK_REG(...) do {} while(false) +#endif + #ifdef __cplusplus } diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 4a5f6cf14d..2d599471a0 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -39,49 +39,76 @@ bool isValid(uint32_t *probe) { } -void dump_mem(void * addr, size_t len) { - uint32_t *addr32 = (uint32_t *)((uintptr_t)addr & ~3); - len = (len + 3) & ~3; - +void dump_mem32(const void * addr, const size_t len) { + uint32_t *addr32 = (uint32_t *)addr; ets_uart_printf("\n"); + if ((uintptr_t)addr32 & 3) { + ets_uart_printf("non-32-bit access\n"); + ets_delay_us(12000); + } for (size_t i = 0; i < len;) { - ets_uart_printf("%p: ", &addr32[i]); + ets_uart_printf("%p: ", &addr32[i]); do { - ets_uart_printf("0x%08x ", addr32[i]); - } while (i++, (i & 3)); + ets_uart_printf(" 0x%08x", addr32[i]); + } while (i++, (i & 3) && (i < len)); ets_uart_printf("\n"); } ets_uart_printf("\n"); } +extern "C" void _text_end(void); +// extern void *_text_end; +void print_mmu_status(Print& oStream) { + oStream.println(); + oStream.printf_P(PSTR("MMU Configuration")); + oStream.println(); + oStream.printf_P(PSTR(" mmu_status = {" + "v_cfg = %u, state = %d, enable/disable count = %u/%u, " + "map = 0x%02X, p = 0x%02X, v = 0x%02X}"), + mmu_status.v_cfg, mmu_status.state, + mmu_status.enable_count, mmu_status.disable_count, + mmu_status.map, mmu_status.p, mmu_status.v); + oStream.println(); + uint32_t iram_bank_reg = ESP8266_DREG(0x24); + if (0 == (iram_bank_reg & 0x10)) { // if bit clear, is enabled + oStream.printf_P(PSTR(" IRAM block mapped to: 0x40108000")); + oStream.println(); + } + if (0 == (iram_bank_reg & 0x08)) { + oStream.printf_P(PSTR(" IRAM block mapped to: 0x4010C000")); + oStream.println(); + } +#ifdef MMU_ICACHE_SIZE + oStream.printf_P(PSTR(" ICACHE Size: %u"), MMU_ICACHE_SIZE); + oStream.println(); +#endif +#ifdef MMU_IRAM_SIZE + oStream.printf_P(PSTR(" IRAM Size: %u"), MMU_IRAM_SIZE); + oStream.println(); + const uint32_t iram_free = MMU_IRAM_SIZE - (uint32_t)((uintptr_t)_text_end - 0x40100000UL); + oStream.printf_P(PSTR(" IRAM free: %u"), iram_free); + oStream.println(); +#endif + oStream.printf_P(PSTR(" IRAM _text_end: %p"), _text_end); + oStream.println(); +#ifdef MMU_SEC_HEAP + oStream.printf_P(PSTR(" Secondary Heap at: %p"), MMU_SEC_HEAP); + oStream.println(); + oStream.printf_P(PSTR(" Secondary Heap Size: %u"), MMU_SEC_HEAP_SIZE); + oStream.println(); +#endif +} + void setup() { WiFi.persistent(false); WiFi.mode(WIFI_OFF); + // Serial.begin(74880); Serial.begin(115200); delay(20); Serial.printf_P(PSTR("\n\nSetup ...\n")); - Serial.printf_P(PSTR("\nMMU Configuration\n")); - Serial.printf_P(PSTR(" Cache_Read_Enable status %d\n"), Cache_Read_Enable_status); -#ifdef MMU_ICACHE_SIZE - Serial.printf_P(PSTR(" ICACHE Size: %u\n"), MMU_ICACHE_SIZE); -#endif -#ifdef MMU_IRAM_SIZE - Serial.printf_P(PSTR(" IRAM Size: %u\n"), MMU_IRAM_SIZE); -#endif -#ifdef MMU_SEC_HEAP - Serial.printf_P(PSTR(" Secondary Heap at: %p\n"), MMU_SEC_HEAP); - Serial.printf_P(PSTR(" Secondary Heap Size: %u\n"), MMU_SEC_HEAP_SIZE); -#endif - constexpr uint32_t volatile *dport_ = (uint32_t volatile *)0x3FF00000; - uint32_t dport_6 = dport_[9]; - if (0 == (dport_6 & 0x10)) { - Serial.printf_P(PSTR(" IRAM block mapped to: 0x40108000\n")); - } - if (0 == (dport_6 & 0x08)) { - Serial.printf_P(PSTR(" IRAM block mapped to: 0x4010C000\n")); - } + print_mmu_status(Serial); #if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_SEC_HEAP) if (isValid(gobble)) { @@ -92,15 +119,138 @@ void setup() { } // Now is it there? - dump_mem(gobble, 32); - dump_mem(&gobble[gobble_sz / 4 / 2], 32); - dump_mem(&gobble[gobble_sz / 4 - 32], 32); + dump_mem32(gobble, 32); + // dump_mem32(&gobble[gobble_sz / 4 / 2], 32); + dump_mem32(&gobble[gobble_sz / 4 - 32], 32); #endif // Lets peak over the edge - dump_mem((void *)(0x4010C000 - 16 * 4), 32); + dump_mem32((void *)(0x4010C000 - 16 * 4), 32); } -void loop() { +int* nullPointer = NULL; +constexpr char *probe_b = (char *)0x40108000; +constexpr short *probe_s = (short *)0x40108000; +constexpr char *probe_c = (char *)0x40110000; +constexpr short *unaligned_probe_s = (short *)0x3FFF8001; +void processKey(Print& out, int hotKey) { + switch (hotKey) { + case '9': + out.printf_P(PSTR("Unaligned exception by reading short")); + out.println(); + out.flush(); + xt_rsil(3); + out.printf_P(PSTR("Read short, 0x%02X at %p"), unaligned_probe_s[0], unaligned_probe_s); + xt_rsil(0); + out.println(); + break; + case 'c': + out.printf_P(PSTR("Load/Store exception by reading byte outside of handler range")); + out.println(); + out.flush(); + xt_rsil(3); + out.printf_P(PSTR("Read Byte, 0x%02X at %p"), probe_c[0], probe_c); + xt_rsil(0); + out.println(); + break; + case 'b': + out.printf_P(PSTR("Load/Store exception by reading byte from iRAM")); + out.println(); + out.flush(); + out.printf_P(PSTR("Read Byte from iRAM, 0x%02X at %p"), probe_b[0], probe_b); + out.println(); + break; + case 'B': + { + out.printf_P(PSTR("Load/Store exception by writing byte to iRAM")); + out.println(); + char val = 0x55; + out.printf_P(PSTR("Write byte, 0x%02X, to iRAM at %p"), val, probe_b); + out.println(); + out.flush(); + probe_b[0] = val; + out.printf_P(PSTR("Read Byte back from iRAM, 0x%02X at %p"), probe_b[0], probe_b); + out.println(); + break; + } + case 's': + out.printf_P(PSTR("Load/Store exception by reading short from iRAM")); + out.println(); + out.flush(); + out.printf_P(PSTR("Read short from iRAM, 0x%04X at %p"), probe_s[0], probe_s); + out.println(); + break; + case 'S': + { + out.printf_P(PSTR("Load/Store exception by writing short to iRAM")); + out.println(); + short int val = 0x0AA0; + out.printf_P(PSTR("Write short, 0x%04X, to iRAM at %p"), val, probe_s); + out.println(); + out.flush(); + probe_s[0] = val; + out.printf_P(PSTR("Read short back from iRAM, 0x%04X at %p"), probe_s[0], probe_s); + out.println(); + break; + } + case 'R': + out.printf_P(PSTR("Restart, ESP.restart(); ...")); + out.println(); + ESP.restart(); + break; + case 'p': + out.println(F("Time to panic()!")); + panic(); + break; + case '0': + out.println(F("Crashing by dividing by zero.")); + out.printf_P(PSTR("This should not print %d"), divideA_B(1, 0)); + out.println(); + break; + case '\r': + out.println(); + case '\n': + break; + case '?': + out.println(); + out.println(F("Press a key + ")); + out.println(F(" R - Restart, ESP.restart();")); + out.println(F(" ? - Print Help")); + out.println(); + out.println(F("Crash with:")); + out.println(F(" b - read byte, Load/Store exception")); + out.println(F(" B - write byte, Load/Store exception")); + out.println(F(" s - read short, Load/Store exception")); + out.println(F(" S - write short, Load/Store exception")); + out.println(F(" c - read byte, Load/Store exception outside of handler range")); + out.println(F(" 9 - read short, Unaligned exception")); + + out.println(F(" 0 - Divide by zero, exception(0);")); + out.println(F(" p - panic();")); + out.println(); + break; + default: + out.printf_P(PSTR("\"%c\" - Not an option? / ? - help"), hotKey); + out.println(); + processKey(out, '?'); + break; + } } + + +void serialClientLoop(void) { + if (Serial.available() > 0) { + int hotKey = Serial.read(); + processKey(Serial, hotKey); + } +} + +void loop() { + serialClientLoop(); +} + + +int divideA_B(int a, int b) { + return (a / b); + } diff --git a/platform.txt b/platform.txt index ddf8ed8e0c..2990343001 100644 --- a/platform.txt +++ b/platform.txt @@ -33,6 +33,7 @@ build.vtable_flags=-DVTABLES_IN_FLASH build.sslflags= build.mmuflags= +build.non32xferflags= build.exception_flags=-fno-exceptions build.stdcpp_lib=-lstdc++ @@ -54,7 +55,7 @@ compiler.libc.path={runtime.platform.path}/tools/sdk/libc/xtensa-lx106-elf compiler.cpreprocessor.flags=-D__ets__ -DICACHE_FLASH -U__STRICT_ANSI__ "-I{compiler.sdk.path}/include" "-I{compiler.sdk.path}/{build.lwip_include}" "-I{compiler.libc.path}/include" "-I{build.path}/core" compiler.c.cmd=xtensa-lx106-elf-gcc -compiler.c.flags=-c {compiler.warning_flags} -Os -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals -falign-functions=4 -MMD -std=gnu99 -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} +compiler.c.flags=-c {compiler.warning_flags} -Os -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals -falign-functions=4 -MMD -std=gnu99 -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} {build.non32xferflags} compiler.S.cmd=xtensa-lx106-elf-gcc compiler.S.flags=-c -g -x assembler-with-cpp -MMD -mlongcalls @@ -65,7 +66,7 @@ compiler.c.elf.cmd=xtensa-lx106-elf-gcc compiler.c.elf.libs=-lhal -lphy -lpp -lnet80211 {build.lwip_lib} -lwpa -lcrypto -lmain -lwps -lbearssl -laxtls -lespnow -lsmartconfig -lairkiss -lwpa2 {build.stdcpp_lib} -lm -lc -lgcc compiler.cpp.cmd=xtensa-lx106-elf-g++ -compiler.cpp.flags=-c {compiler.warning_flags} -Os -g -mlongcalls -mtext-section-literals -fno-rtti -falign-functions=4 {build.stdcpp_level} -MMD -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} +compiler.cpp.flags=-c {compiler.warning_flags} -Os -g -mlongcalls -mtext-section-literals -fno-rtti -falign-functions=4 {build.stdcpp_level} -MMD -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} {build.non32xferflags} compiler.as.cmd=xtensa-lx106-elf-as @@ -120,7 +121,7 @@ recipe.objcopy.eep.pattern= ## Create hex recipe.objcopy.hex.1.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.elf2bin}" --eboot "{runtime.tools.eboot}" --app "{build.path}/{build.project_name}.elf" --flash_mode {build.flash_mode} --flash_freq {build.flash_freq} --flash_size {build.flash_size} --path "{runtime.tools.xtensa-lx106-elf-gcc.path}/bin" --out "{build.path}/{build.project_name}.bin" recipe.objcopy.hex.2.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.signing}" --mode sign --privatekey "{build.source.path}/private.key" --bin "{build.path}/{build.project_name}.bin" --out "{build.path}/{build.project_name}.bin.signed" --legacy "{build.path}/{build.project_name}.bin.legacy_sig" -recipe.objcopy.hex.3.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.sizes}" --elf "{build.path}/{build.project_name}.elf" --path "{runtime.tools.xtensa-lx106-elf-gcc.path}/bin" +recipe.objcopy.hex.3.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.sizes}" --elf "{build.path}/{build.project_name}.elf" --path "{runtime.tools.xtensa-lx106-elf-gcc.path}/bin" --mmu "{build.mmuflags}" ## Save hex recipe.output.tmp_file={build.project_name}.bin diff --git a/tools/boards.txt.py b/tools/boards.txt.py index c1fe6a2b64..692e784ea3 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1197,6 +1197,14 @@ ( '.menu.mmu.3216.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000' ), ]), + ######################## Non 32-bit load/store exception handler + + 'non32xfer_menu': collections.OrderedDict([ + ('.menu.non32xfer.fast', 'Use pgm_read macros for IRAM/PROGMEM' ), + ('.menu.non32xfer.fast.build.non32xferflags', ''), + ('.menu.non32xfer.safe', 'Byte/Word access to IRAM/PROGMEM (very slow)' ), + ('.menu.non32xfer.safe.build.non32xferflags', '-DNON32XFER_HANDLER'), + ]) } ################################################################ @@ -1558,6 +1566,7 @@ def all_boards (): print('menu.sdk=Espressif FW') print('menu.ssl=SSL Support') print('menu.mmu=MMU') + print('menu.non32xfer=Non-32-Bit Access') print('') missingboards = [] @@ -1576,7 +1585,7 @@ def all_boards (): print(id + optname + '=' + board['opts'][optname]) # macros - macrolist = [ 'defaults', 'cpufreq_menu', 'vtable_menu', 'exception_menu', 'ssl_cipher_menu', 'mmu_menu' ] + macrolist = [ 'defaults', 'cpufreq_menu', 'vtable_menu', 'exception_menu', 'ssl_cipher_menu', 'mmu_menu', 'non32xfer_menu' ] if 'macro' in board: macrolist += board['macro'] if lwip == 2: diff --git a/tools/sizes.py b/tools/sizes.py index f633f8a6a5..3c599ebf30 100755 --- a/tools/sizes.py +++ b/tools/sizes.py @@ -23,13 +23,14 @@ import subprocess import sys -def get_segment_hints(): +def get_segment_hints(iram): hints = {} hints['IROM'] = ' - code in flash (default or ICACHE_FLASH_ATTR)' - hints['IRAM'] = ' / 32768 - code in IRAM (ICACHE_RAM_ATTR, ISRs...)' + hints['IRAM'] = ' / ' + str(iram) + ' - code in IRAM (ICACHE_RAM_ATTR, ISRs...)' hints['DATA'] = ') - initialized variables (global, static) in RAM/HEAP' hints['RODATA'] = ') / 81920 - constants (global, static) in RAM/HEAP' hints['BSS'] = ') - zeroed variables (global, static) in RAM/HEAP' + hints['ICACHE'] = ') - flash instruction cache' return hints def get_segment_sizes(elf, path): @@ -55,14 +56,28 @@ def get_segment_sizes(elf, path): sizes['BSS'] = sizes['BSS'] + int(words[1]) return sizes +def get_mmu_sizes(mmu, sizes): + iram = 0x8000 + sizes['ICACHE'] = 0x8000 + lines = mmu.split(' ') + for line in lines: + words = line.split('=') + if line.startswith('-DMMU_IRAM_SIZE'): + iram = int(words[1], 16) + elif line.startswith('-DMMU_ICACHE_SIZE'): + sizes['ICACHE'] = int(words[1], 16) + return [iram, sizes] + def main(): parser = argparse.ArgumentParser(description='Report the different segment sizes of a compiled ELF file') parser.add_argument('-e', '--elf', action='store', required=True, help='Path to the Arduino sketch ELF') parser.add_argument('-p', '--path', action='store', required=True, help='Path to Xtensa toolchain binaries') + parser.add_argument('-i', '--mmu', action='store', required=False, help='MMU build options') args = parser.parse_args() sizes = get_segment_sizes(args.elf, args.path) - hints = get_segment_hints() + [iram, sizes] = get_mmu_sizes(args.mmu, sizes) + hints = get_segment_hints(iram) sys.stderr.write("Executable segment sizes:" + os.linesep) for k in sizes.keys(): From 06459236ff63b002133cf11e447e33ecdc9098db Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 12 Feb 2020 20:00:40 -0800 Subject: [PATCH 04/48] Style and MMU_SEC_HEAP corrections. --- cores/esp8266/mmu_iram.h | 4 ++ libraries/esp8266/examples/MMU48K/MMU48K.ino | 62 ++++++++++---------- 2 files changed, 34 insertions(+), 32 deletions(-) diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 4555e5d58a..e61bd546c3 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -43,7 +43,11 @@ extern mmu_cre_status_t mmu_status; #ifdef DEBUG_MMU bool inline is_iram(uint32_t addr) { constexpr uint32_t iram_start = 0x40100000u; +#ifdef MMU_SEC_HEAP_SIZE constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; +#else + constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE; +#endif return (iram_start <= addr && iram_end > addr); } diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 2d599471a0..e8e6962c83 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -63,11 +63,11 @@ void print_mmu_status(Print& oStream) { oStream.printf_P(PSTR("MMU Configuration")); oStream.println(); oStream.printf_P(PSTR(" mmu_status = {" - "v_cfg = %u, state = %d, enable/disable count = %u/%u, " - "map = 0x%02X, p = 0x%02X, v = 0x%02X}"), - mmu_status.v_cfg, mmu_status.state, - mmu_status.enable_count, mmu_status.disable_count, - mmu_status.map, mmu_status.p, mmu_status.v); + "v_cfg = %u, state = %d, enable/disable count = %u/%u, " + "map = 0x%02X, p = 0x%02X, v = 0x%02X}"), + mmu_status.v_cfg, mmu_status.state, + mmu_status.enable_count, mmu_status.disable_count, + mmu_status.map, mmu_status.p, mmu_status.v); oStream.println(); uint32_t iram_bank_reg = ESP8266_DREG(0x24); if (0 == (iram_bank_reg & 0x10)) { // if bit clear, is enabled @@ -161,19 +161,18 @@ void processKey(Print& out, int hotKey) { out.printf_P(PSTR("Read Byte from iRAM, 0x%02X at %p"), probe_b[0], probe_b); out.println(); break; - case 'B': - { - out.printf_P(PSTR("Load/Store exception by writing byte to iRAM")); - out.println(); - char val = 0x55; - out.printf_P(PSTR("Write byte, 0x%02X, to iRAM at %p"), val, probe_b); - out.println(); - out.flush(); - probe_b[0] = val; - out.printf_P(PSTR("Read Byte back from iRAM, 0x%02X at %p"), probe_b[0], probe_b); - out.println(); - break; - } + case 'B': { + out.printf_P(PSTR("Load/Store exception by writing byte to iRAM")); + out.println(); + char val = 0x55; + out.printf_P(PSTR("Write byte, 0x%02X, to iRAM at %p"), val, probe_b); + out.println(); + out.flush(); + probe_b[0] = val; + out.printf_P(PSTR("Read Byte back from iRAM, 0x%02X at %p"), probe_b[0], probe_b); + out.println(); + break; + } case 's': out.printf_P(PSTR("Load/Store exception by reading short from iRAM")); out.println(); @@ -181,19 +180,18 @@ void processKey(Print& out, int hotKey) { out.printf_P(PSTR("Read short from iRAM, 0x%04X at %p"), probe_s[0], probe_s); out.println(); break; - case 'S': - { - out.printf_P(PSTR("Load/Store exception by writing short to iRAM")); - out.println(); - short int val = 0x0AA0; - out.printf_P(PSTR("Write short, 0x%04X, to iRAM at %p"), val, probe_s); - out.println(); - out.flush(); - probe_s[0] = val; - out.printf_P(PSTR("Read short back from iRAM, 0x%04X at %p"), probe_s[0], probe_s); - out.println(); - break; - } + case 'S': { + out.printf_P(PSTR("Load/Store exception by writing short to iRAM")); + out.println(); + short int val = 0x0AA0; + out.printf_P(PSTR("Write short, 0x%04X, to iRAM at %p"), val, probe_s); + out.println(); + out.flush(); + probe_s[0] = val; + out.printf_P(PSTR("Read short back from iRAM, 0x%04X at %p"), probe_s[0], probe_s); + out.println(); + break; + } case 'R': out.printf_P(PSTR("Restart, ESP.restart(); ...")); out.println(); @@ -253,4 +251,4 @@ void loop() { int divideA_B(int a, int b) { return (a / b); - } +} From a6bb5a1f7c4209bb8b5c63ae207a61ff7cd1dd42 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 13 Feb 2020 17:02:36 -0800 Subject: [PATCH 05/48] Improved asm register usage. Added some inline functions to aid in byte and short access to iRAM. * only byte read has been tested Updated .ld file to work better with platform.io; however, I am still missing some steps, so platformio will still fail. --- boards.txt | 368 +++++++++--------- cores/esp8266/core_esp8266_non32xfer.cpp | 23 +- cores/esp8266/mmu_iram.h | 102 ++++- libraries/esp8266/examples/MMU48K/MMU48K.ino | 45 +++ libraries/esp8266/examples/MMU48K/timed.cpp | 16 + platform.txt | 8 +- tools/boards.txt.py | 2 +- ...lash.16m14m.ld.h => eagle.flash.16m14m.ld} | 0 ...lash.16m15m.ld.h => eagle.flash.16m15m.ld} | 0 ...{eagle.flash.1m.ld.h => eagle.flash.1m.ld} | 0 ....flash.1m128.ld.h => eagle.flash.1m128.ld} | 0 ....flash.1m144.ld.h => eagle.flash.1m144.ld} | 0 ....flash.1m160.ld.h => eagle.flash.1m160.ld} | 0 ....flash.1m192.ld.h => eagle.flash.1m192.ld} | 0 ....flash.1m256.ld.h => eagle.flash.1m256.ld} | 0 ....flash.1m512.ld.h => eagle.flash.1m512.ld} | 0 ...le.flash.1m64.ld.h => eagle.flash.1m64.ld} | 0 ...{eagle.flash.2m.ld.h => eagle.flash.2m.ld} | 0 ....flash.2m128.ld.h => eagle.flash.2m128.ld} | 0 ...le.flash.2m1m.ld.h => eagle.flash.2m1m.ld} | 0 ....flash.2m256.ld.h => eagle.flash.2m256.ld} | 0 ....flash.2m512.ld.h => eagle.flash.2m512.ld} | 0 ...le.flash.2m64.ld.h => eagle.flash.2m64.ld} | 0 ...{eagle.flash.4m.ld.h => eagle.flash.4m.ld} | 0 ...le.flash.4m1m.ld.h => eagle.flash.4m1m.ld} | 0 ...le.flash.4m2m.ld.h => eagle.flash.4m2m.ld} | 0 ...le.flash.4m3m.ld.h => eagle.flash.4m3m.ld} | 0 ...le.flash.512k.ld.h => eagle.flash.512k.ld} | 0 ...sh.512k128.ld.h => eagle.flash.512k128.ld} | 0 ...lash.512k32.ld.h => eagle.flash.512k32.ld} | 0 ...lash.512k64.ld.h => eagle.flash.512k64.ld} | 0 ...le.flash.8m6m.ld.h => eagle.flash.8m6m.ld} | 0 ...le.flash.8m7m.ld.h => eagle.flash.8m7m.ld} | 0 33 files changed, 359 insertions(+), 205 deletions(-) create mode 100644 libraries/esp8266/examples/MMU48K/timed.cpp rename tools/sdk/ld/{eagle.flash.16m14m.ld.h => eagle.flash.16m14m.ld} (100%) rename tools/sdk/ld/{eagle.flash.16m15m.ld.h => eagle.flash.16m15m.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m.ld.h => eagle.flash.1m.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m128.ld.h => eagle.flash.1m128.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m144.ld.h => eagle.flash.1m144.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m160.ld.h => eagle.flash.1m160.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m192.ld.h => eagle.flash.1m192.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m256.ld.h => eagle.flash.1m256.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m512.ld.h => eagle.flash.1m512.ld} (100%) rename tools/sdk/ld/{eagle.flash.1m64.ld.h => eagle.flash.1m64.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m.ld.h => eagle.flash.2m.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m128.ld.h => eagle.flash.2m128.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m1m.ld.h => eagle.flash.2m1m.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m256.ld.h => eagle.flash.2m256.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m512.ld.h => eagle.flash.2m512.ld} (100%) rename tools/sdk/ld/{eagle.flash.2m64.ld.h => eagle.flash.2m64.ld} (100%) rename tools/sdk/ld/{eagle.flash.4m.ld.h => eagle.flash.4m.ld} (100%) rename tools/sdk/ld/{eagle.flash.4m1m.ld.h => eagle.flash.4m1m.ld} (100%) rename tools/sdk/ld/{eagle.flash.4m2m.ld.h => eagle.flash.4m2m.ld} (100%) rename tools/sdk/ld/{eagle.flash.4m3m.ld.h => eagle.flash.4m3m.ld} (100%) rename tools/sdk/ld/{eagle.flash.512k.ld.h => eagle.flash.512k.ld} (100%) rename tools/sdk/ld/{eagle.flash.512k128.ld.h => eagle.flash.512k128.ld} (100%) rename tools/sdk/ld/{eagle.flash.512k32.ld.h => eagle.flash.512k32.ld} (100%) rename tools/sdk/ld/{eagle.flash.512k64.ld.h => eagle.flash.512k64.ld} (100%) rename tools/sdk/ld/{eagle.flash.8m6m.ld.h => eagle.flash.8m6m.ld} (100%) rename tools/sdk/ld/{eagle.flash.8m7m.ld.h => eagle.flash.8m7m.ld} (100%) diff --git a/boards.txt b/boards.txt index 2af1af13f1..43a4231e97 100644 --- a/boards.txt +++ b/boards.txt @@ -105,7 +105,7 @@ generic.menu.FlashMode.qio.build.flash_flags=-DFLASHMODE_QIO generic.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) generic.menu.eesz.1M64.build.flash_size=1M generic.menu.eesz.1M64.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +generic.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld generic.menu.eesz.1M64.build.spiffs_pagesize=256 generic.menu.eesz.1M64.upload.maximum_size=958448 generic.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -115,7 +115,7 @@ generic.menu.eesz.1M64.build.spiffs_blocksize=4096 generic.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) generic.menu.eesz.1M128.build.flash_size=1M generic.menu.eesz.1M128.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +generic.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld generic.menu.eesz.1M128.build.spiffs_pagesize=256 generic.menu.eesz.1M128.upload.maximum_size=892912 generic.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -125,7 +125,7 @@ generic.menu.eesz.1M128.build.spiffs_blocksize=4096 generic.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) generic.menu.eesz.1M144.build.flash_size=1M generic.menu.eesz.1M144.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +generic.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld generic.menu.eesz.1M144.build.spiffs_pagesize=256 generic.menu.eesz.1M144.upload.maximum_size=876528 generic.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -135,7 +135,7 @@ generic.menu.eesz.1M144.build.spiffs_blocksize=4096 generic.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) generic.menu.eesz.1M160.build.flash_size=1M generic.menu.eesz.1M160.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +generic.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld generic.menu.eesz.1M160.build.spiffs_pagesize=256 generic.menu.eesz.1M160.upload.maximum_size=860144 generic.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -145,7 +145,7 @@ generic.menu.eesz.1M160.build.spiffs_blocksize=4096 generic.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) generic.menu.eesz.1M192.build.flash_size=1M generic.menu.eesz.1M192.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +generic.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld generic.menu.eesz.1M192.build.spiffs_pagesize=256 generic.menu.eesz.1M192.upload.maximum_size=827376 generic.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -155,7 +155,7 @@ generic.menu.eesz.1M192.build.spiffs_blocksize=4096 generic.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) generic.menu.eesz.1M256.build.flash_size=1M generic.menu.eesz.1M256.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +generic.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld generic.menu.eesz.1M256.build.spiffs_pagesize=256 generic.menu.eesz.1M256.upload.maximum_size=761840 generic.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -165,7 +165,7 @@ generic.menu.eesz.1M256.build.spiffs_blocksize=4096 generic.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) generic.menu.eesz.1M512.build.flash_size=1M generic.menu.eesz.1M512.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +generic.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld generic.menu.eesz.1M512.build.spiffs_pagesize=256 generic.menu.eesz.1M512.upload.maximum_size=499696 generic.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -175,14 +175,14 @@ generic.menu.eesz.1M512.build.spiffs_blocksize=8192 generic.menu.eesz.1M=1MB (FS:none OTA:~502KB) generic.menu.eesz.1M.build.flash_size=1M generic.menu.eesz.1M.build.flash_size_bytes=0x100000 -generic.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +generic.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld generic.menu.eesz.1M.build.spiffs_pagesize=256 generic.menu.eesz.1M.upload.maximum_size=1023984 generic.menu.eesz.1M.build.rfcal_addr=0xFC000 generic.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) generic.menu.eesz.2M64.build.flash_size=2M generic.menu.eesz.2M64.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h +generic.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld generic.menu.eesz.2M64.build.spiffs_pagesize=256 generic.menu.eesz.2M64.upload.maximum_size=1044464 generic.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -192,7 +192,7 @@ generic.menu.eesz.2M64.build.spiffs_blocksize=4096 generic.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) generic.menu.eesz.2M128.build.flash_size=2M generic.menu.eesz.2M128.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h +generic.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld generic.menu.eesz.2M128.build.spiffs_pagesize=256 generic.menu.eesz.2M128.upload.maximum_size=1044464 generic.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -202,7 +202,7 @@ generic.menu.eesz.2M128.build.spiffs_blocksize=4096 generic.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) generic.menu.eesz.2M256.build.flash_size=2M generic.menu.eesz.2M256.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h +generic.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld generic.menu.eesz.2M256.build.spiffs_pagesize=256 generic.menu.eesz.2M256.upload.maximum_size=1044464 generic.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -212,7 +212,7 @@ generic.menu.eesz.2M256.build.spiffs_blocksize=4096 generic.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) generic.menu.eesz.2M512.build.flash_size=2M generic.menu.eesz.2M512.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h +generic.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld generic.menu.eesz.2M512.build.spiffs_pagesize=256 generic.menu.eesz.2M512.upload.maximum_size=1044464 generic.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -222,7 +222,7 @@ generic.menu.eesz.2M512.build.spiffs_blocksize=8192 generic.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) generic.menu.eesz.2M1M.build.flash_size=2M generic.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h +generic.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld generic.menu.eesz.2M1M.build.spiffs_pagesize=256 generic.menu.eesz.2M1M.upload.maximum_size=1044464 generic.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -232,14 +232,14 @@ generic.menu.eesz.2M1M.build.spiffs_blocksize=8192 generic.menu.eesz.2M=2MB (FS:none OTA:~1019KB) generic.menu.eesz.2M.build.flash_size=2M generic.menu.eesz.2M.build.flash_size_bytes=0x200000 -generic.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h +generic.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld generic.menu.eesz.2M.build.spiffs_pagesize=256 generic.menu.eesz.2M.upload.maximum_size=1044464 generic.menu.eesz.2M.build.rfcal_addr=0x1FC000 generic.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) generic.menu.eesz.4M2M.build.flash_size=4M generic.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +generic.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld generic.menu.eesz.4M2M.build.spiffs_pagesize=256 generic.menu.eesz.4M2M.upload.maximum_size=1044464 generic.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -249,7 +249,7 @@ generic.menu.eesz.4M2M.build.spiffs_blocksize=8192 generic.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) generic.menu.eesz.4M3M.build.flash_size=4M generic.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +generic.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld generic.menu.eesz.4M3M.build.spiffs_pagesize=256 generic.menu.eesz.4M3M.upload.maximum_size=1044464 generic.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -259,7 +259,7 @@ generic.menu.eesz.4M3M.build.spiffs_blocksize=8192 generic.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) generic.menu.eesz.4M1M.build.flash_size=4M generic.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +generic.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld generic.menu.eesz.4M1M.build.spiffs_pagesize=256 generic.menu.eesz.4M1M.upload.maximum_size=1044464 generic.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -269,14 +269,14 @@ generic.menu.eesz.4M1M.build.spiffs_blocksize=8192 generic.menu.eesz.4M=4MB (FS:none OTA:~1019KB) generic.menu.eesz.4M.build.flash_size=4M generic.menu.eesz.4M.build.flash_size_bytes=0x400000 -generic.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +generic.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld generic.menu.eesz.4M.build.spiffs_pagesize=256 generic.menu.eesz.4M.upload.maximum_size=1044464 generic.menu.eesz.4M.build.rfcal_addr=0x3FC000 generic.menu.eesz.8M6M=8MB (FS:6MB OTA:~1019KB) generic.menu.eesz.8M6M.build.flash_size=8M generic.menu.eesz.8M6M.build.flash_size_bytes=0x800000 -generic.menu.eesz.8M6M.build.flash_ld=eagle.flash.8m6m.ld.h +generic.menu.eesz.8M6M.build.flash_ld=eagle.flash.8m6m.ld generic.menu.eesz.8M6M.build.spiffs_pagesize=256 generic.menu.eesz.8M6M.upload.maximum_size=1044464 generic.menu.eesz.8M6M.build.rfcal_addr=0x7FC000 @@ -286,7 +286,7 @@ generic.menu.eesz.8M6M.build.spiffs_blocksize=8192 generic.menu.eesz.8M7M=8MB (FS:7MB OTA:~512KB) generic.menu.eesz.8M7M.build.flash_size=8M generic.menu.eesz.8M7M.build.flash_size_bytes=0x800000 -generic.menu.eesz.8M7M.build.flash_ld=eagle.flash.8m7m.ld.h +generic.menu.eesz.8M7M.build.flash_ld=eagle.flash.8m7m.ld generic.menu.eesz.8M7M.build.spiffs_pagesize=256 generic.menu.eesz.8M7M.upload.maximum_size=1044464 generic.menu.eesz.8M7M.build.rfcal_addr=0x7FC000 @@ -296,7 +296,7 @@ generic.menu.eesz.8M7M.build.spiffs_blocksize=8192 generic.menu.eesz.16M14M=16MB (FS:14MB OTA:~1019KB) generic.menu.eesz.16M14M.build.flash_size=16M generic.menu.eesz.16M14M.build.flash_size_bytes=0x1000000 -generic.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld.h +generic.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld generic.menu.eesz.16M14M.build.spiffs_pagesize=256 generic.menu.eesz.16M14M.upload.maximum_size=1044464 generic.menu.eesz.16M14M.build.rfcal_addr=0xFFC000 @@ -306,7 +306,7 @@ generic.menu.eesz.16M14M.build.spiffs_blocksize=8192 generic.menu.eesz.16M15M=16MB (FS:15MB OTA:~512KB) generic.menu.eesz.16M15M.build.flash_size=16M generic.menu.eesz.16M15M.build.flash_size_bytes=0x1000000 -generic.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld.h +generic.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld generic.menu.eesz.16M15M.build.spiffs_pagesize=256 generic.menu.eesz.16M15M.upload.maximum_size=1044464 generic.menu.eesz.16M15M.build.rfcal_addr=0xFFC000 @@ -316,7 +316,7 @@ generic.menu.eesz.16M15M.build.spiffs_blocksize=8192 generic.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) generic.menu.eesz.512K32.build.flash_size=512K generic.menu.eesz.512K32.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h +generic.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld generic.menu.eesz.512K32.build.spiffs_pagesize=256 generic.menu.eesz.512K32.upload.maximum_size=466928 generic.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -326,7 +326,7 @@ generic.menu.eesz.512K32.build.spiffs_blocksize=4096 generic.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) generic.menu.eesz.512K64.build.flash_size=512K generic.menu.eesz.512K64.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h +generic.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld generic.menu.eesz.512K64.build.spiffs_pagesize=256 generic.menu.eesz.512K64.upload.maximum_size=434160 generic.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -336,7 +336,7 @@ generic.menu.eesz.512K64.build.spiffs_blocksize=4096 generic.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) generic.menu.eesz.512K128.build.flash_size=512K generic.menu.eesz.512K128.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h +generic.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld generic.menu.eesz.512K128.build.spiffs_pagesize=256 generic.menu.eesz.512K128.upload.maximum_size=368624 generic.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -346,7 +346,7 @@ generic.menu.eesz.512K128.build.spiffs_blocksize=4096 generic.menu.eesz.512K=512KB (FS:none OTA:~246KB) generic.menu.eesz.512K.build.flash_size=512K generic.menu.eesz.512K.build.flash_size_bytes=0x80000 -generic.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h +generic.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld generic.menu.eesz.512K.build.spiffs_pagesize=256 generic.menu.eesz.512K.upload.maximum_size=499696 generic.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -573,7 +573,7 @@ esp8285.build.flash_freq=40 esp8285.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) esp8285.menu.eesz.1M64.build.flash_size=1M esp8285.menu.eesz.1M64.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +esp8285.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld esp8285.menu.eesz.1M64.build.spiffs_pagesize=256 esp8285.menu.eesz.1M64.upload.maximum_size=958448 esp8285.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -583,7 +583,7 @@ esp8285.menu.eesz.1M64.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) esp8285.menu.eesz.1M128.build.flash_size=1M esp8285.menu.eesz.1M128.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +esp8285.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld esp8285.menu.eesz.1M128.build.spiffs_pagesize=256 esp8285.menu.eesz.1M128.upload.maximum_size=892912 esp8285.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -593,7 +593,7 @@ esp8285.menu.eesz.1M128.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) esp8285.menu.eesz.1M144.build.flash_size=1M esp8285.menu.eesz.1M144.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +esp8285.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld esp8285.menu.eesz.1M144.build.spiffs_pagesize=256 esp8285.menu.eesz.1M144.upload.maximum_size=876528 esp8285.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -603,7 +603,7 @@ esp8285.menu.eesz.1M144.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) esp8285.menu.eesz.1M160.build.flash_size=1M esp8285.menu.eesz.1M160.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +esp8285.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld esp8285.menu.eesz.1M160.build.spiffs_pagesize=256 esp8285.menu.eesz.1M160.upload.maximum_size=860144 esp8285.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -613,7 +613,7 @@ esp8285.menu.eesz.1M160.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) esp8285.menu.eesz.1M192.build.flash_size=1M esp8285.menu.eesz.1M192.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +esp8285.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld esp8285.menu.eesz.1M192.build.spiffs_pagesize=256 esp8285.menu.eesz.1M192.upload.maximum_size=827376 esp8285.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -623,7 +623,7 @@ esp8285.menu.eesz.1M192.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) esp8285.menu.eesz.1M256.build.flash_size=1M esp8285.menu.eesz.1M256.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +esp8285.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld esp8285.menu.eesz.1M256.build.spiffs_pagesize=256 esp8285.menu.eesz.1M256.upload.maximum_size=761840 esp8285.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -633,7 +633,7 @@ esp8285.menu.eesz.1M256.build.spiffs_blocksize=4096 esp8285.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) esp8285.menu.eesz.1M512.build.flash_size=1M esp8285.menu.eesz.1M512.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +esp8285.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld esp8285.menu.eesz.1M512.build.spiffs_pagesize=256 esp8285.menu.eesz.1M512.upload.maximum_size=499696 esp8285.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -643,7 +643,7 @@ esp8285.menu.eesz.1M512.build.spiffs_blocksize=8192 esp8285.menu.eesz.1M=1MB (FS:none OTA:~502KB) esp8285.menu.eesz.1M.build.flash_size=1M esp8285.menu.eesz.1M.build.flash_size_bytes=0x100000 -esp8285.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +esp8285.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld esp8285.menu.eesz.1M.build.spiffs_pagesize=256 esp8285.menu.eesz.1M.upload.maximum_size=1023984 esp8285.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -858,7 +858,7 @@ espduino.build.flash_freq=40 espduino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espduino.menu.eesz.4M2M.build.flash_size=4M espduino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espduino.menu.eesz.4M2M.build.spiffs_pagesize=256 espduino.menu.eesz.4M2M.upload.maximum_size=1044464 espduino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -868,7 +868,7 @@ espduino.menu.eesz.4M2M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espduino.menu.eesz.4M3M.build.flash_size=4M espduino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espduino.menu.eesz.4M3M.build.spiffs_pagesize=256 espduino.menu.eesz.4M3M.upload.maximum_size=1044464 espduino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -878,7 +878,7 @@ espduino.menu.eesz.4M3M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espduino.menu.eesz.4M1M.build.flash_size=4M espduino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espduino.menu.eesz.4M1M.build.spiffs_pagesize=256 espduino.menu.eesz.4M1M.upload.maximum_size=1044464 espduino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -888,7 +888,7 @@ espduino.menu.eesz.4M1M.build.spiffs_blocksize=8192 espduino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espduino.menu.eesz.4M.build.flash_size=4M espduino.menu.eesz.4M.build.flash_size_bytes=0x400000 -espduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espduino.menu.eesz.4M.build.spiffs_pagesize=256 espduino.menu.eesz.4M.upload.maximum_size=1044464 espduino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1061,7 +1061,7 @@ huzzah.build.flash_freq=40 huzzah.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) huzzah.menu.eesz.4M2M.build.flash_size=4M huzzah.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +huzzah.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld huzzah.menu.eesz.4M2M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M2M.upload.maximum_size=1044464 huzzah.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1071,7 +1071,7 @@ huzzah.menu.eesz.4M2M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) huzzah.menu.eesz.4M3M.build.flash_size=4M huzzah.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +huzzah.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld huzzah.menu.eesz.4M3M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M3M.upload.maximum_size=1044464 huzzah.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1081,7 +1081,7 @@ huzzah.menu.eesz.4M3M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) huzzah.menu.eesz.4M1M.build.flash_size=4M huzzah.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +huzzah.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld huzzah.menu.eesz.4M1M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M1M.upload.maximum_size=1044464 huzzah.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1091,7 +1091,7 @@ huzzah.menu.eesz.4M1M.build.spiffs_blocksize=8192 huzzah.menu.eesz.4M=4MB (FS:none OTA:~1019KB) huzzah.menu.eesz.4M.build.flash_size=4M huzzah.menu.eesz.4M.build.flash_size_bytes=0x400000 -huzzah.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +huzzah.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld huzzah.menu.eesz.4M.build.spiffs_pagesize=256 huzzah.menu.eesz.4M.upload.maximum_size=1044464 huzzah.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1264,7 +1264,7 @@ inventone.build.flash_freq=40 inventone.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) inventone.menu.eesz.4M2M.build.flash_size=4M inventone.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +inventone.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld inventone.menu.eesz.4M2M.build.spiffs_pagesize=256 inventone.menu.eesz.4M2M.upload.maximum_size=1044464 inventone.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1274,7 +1274,7 @@ inventone.menu.eesz.4M2M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) inventone.menu.eesz.4M3M.build.flash_size=4M inventone.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +inventone.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld inventone.menu.eesz.4M3M.build.spiffs_pagesize=256 inventone.menu.eesz.4M3M.upload.maximum_size=1044464 inventone.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1284,7 +1284,7 @@ inventone.menu.eesz.4M3M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) inventone.menu.eesz.4M1M.build.flash_size=4M inventone.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +inventone.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld inventone.menu.eesz.4M1M.build.spiffs_pagesize=256 inventone.menu.eesz.4M1M.upload.maximum_size=1044464 inventone.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1294,7 +1294,7 @@ inventone.menu.eesz.4M1M.build.spiffs_blocksize=8192 inventone.menu.eesz.4M=4MB (FS:none OTA:~1019KB) inventone.menu.eesz.4M.build.flash_size=4M inventone.menu.eesz.4M.build.flash_size_bytes=0x400000 -inventone.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +inventone.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld inventone.menu.eesz.4M.build.spiffs_pagesize=256 inventone.menu.eesz.4M.upload.maximum_size=1044464 inventone.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1470,7 +1470,7 @@ cw01.build.flash_freq=40 cw01.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) cw01.menu.eesz.4M2M.build.flash_size=4M cw01.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +cw01.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld cw01.menu.eesz.4M2M.build.spiffs_pagesize=256 cw01.menu.eesz.4M2M.upload.maximum_size=1044464 cw01.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1480,7 +1480,7 @@ cw01.menu.eesz.4M2M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) cw01.menu.eesz.4M3M.build.flash_size=4M cw01.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +cw01.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld cw01.menu.eesz.4M3M.build.spiffs_pagesize=256 cw01.menu.eesz.4M3M.upload.maximum_size=1044464 cw01.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1490,7 +1490,7 @@ cw01.menu.eesz.4M3M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) cw01.menu.eesz.4M1M.build.flash_size=4M cw01.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +cw01.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld cw01.menu.eesz.4M1M.build.spiffs_pagesize=256 cw01.menu.eesz.4M1M.upload.maximum_size=1044464 cw01.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1500,7 +1500,7 @@ cw01.menu.eesz.4M1M.build.spiffs_blocksize=8192 cw01.menu.eesz.4M=4MB (FS:none OTA:~1019KB) cw01.menu.eesz.4M.build.flash_size=4M cw01.menu.eesz.4M.build.flash_size_bytes=0x400000 -cw01.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +cw01.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld cw01.menu.eesz.4M.build.spiffs_pagesize=256 cw01.menu.eesz.4M.upload.maximum_size=1044464 cw01.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1672,7 +1672,7 @@ espresso_lite_v1.build.flash_freq=40 espresso_lite_v1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espresso_lite_v1.menu.eesz.4M2M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espresso_lite_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espresso_lite_v1.menu.eesz.4M2M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M2M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1682,7 +1682,7 @@ espresso_lite_v1.menu.eesz.4M2M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espresso_lite_v1.menu.eesz.4M3M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espresso_lite_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espresso_lite_v1.menu.eesz.4M3M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M3M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1692,7 +1692,7 @@ espresso_lite_v1.menu.eesz.4M3M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espresso_lite_v1.menu.eesz.4M1M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espresso_lite_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espresso_lite_v1.menu.eesz.4M1M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M1M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1702,7 +1702,7 @@ espresso_lite_v1.menu.eesz.4M1M.build.spiffs_blocksize=8192 espresso_lite_v1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espresso_lite_v1.menu.eesz.4M.build.flash_size=4M espresso_lite_v1.menu.eesz.4M.build.flash_size_bytes=0x400000 -espresso_lite_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espresso_lite_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espresso_lite_v1.menu.eesz.4M.build.spiffs_pagesize=256 espresso_lite_v1.menu.eesz.4M.upload.maximum_size=1044464 espresso_lite_v1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -1878,7 +1878,7 @@ espresso_lite_v2.build.flash_freq=40 espresso_lite_v2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espresso_lite_v2.menu.eesz.4M2M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espresso_lite_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espresso_lite_v2.menu.eesz.4M2M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M2M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -1888,7 +1888,7 @@ espresso_lite_v2.menu.eesz.4M2M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espresso_lite_v2.menu.eesz.4M3M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espresso_lite_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espresso_lite_v2.menu.eesz.4M3M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M3M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -1898,7 +1898,7 @@ espresso_lite_v2.menu.eesz.4M3M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espresso_lite_v2.menu.eesz.4M1M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espresso_lite_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espresso_lite_v2.menu.eesz.4M1M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M1M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -1908,7 +1908,7 @@ espresso_lite_v2.menu.eesz.4M1M.build.spiffs_blocksize=8192 espresso_lite_v2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espresso_lite_v2.menu.eesz.4M.build.flash_size=4M espresso_lite_v2.menu.eesz.4M.build.flash_size_bytes=0x400000 -espresso_lite_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espresso_lite_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espresso_lite_v2.menu.eesz.4M.build.spiffs_pagesize=256 espresso_lite_v2.menu.eesz.4M.upload.maximum_size=1044464 espresso_lite_v2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2084,7 +2084,7 @@ phoenix_v1.build.flash_freq=40 phoenix_v1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) phoenix_v1.menu.eesz.4M2M.build.flash_size=4M phoenix_v1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +phoenix_v1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld phoenix_v1.menu.eesz.4M2M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M2M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2094,7 +2094,7 @@ phoenix_v1.menu.eesz.4M2M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) phoenix_v1.menu.eesz.4M3M.build.flash_size=4M phoenix_v1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +phoenix_v1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld phoenix_v1.menu.eesz.4M3M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M3M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2104,7 +2104,7 @@ phoenix_v1.menu.eesz.4M3M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) phoenix_v1.menu.eesz.4M1M.build.flash_size=4M phoenix_v1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +phoenix_v1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld phoenix_v1.menu.eesz.4M1M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M1M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2114,7 +2114,7 @@ phoenix_v1.menu.eesz.4M1M.build.spiffs_blocksize=8192 phoenix_v1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) phoenix_v1.menu.eesz.4M.build.flash_size=4M phoenix_v1.menu.eesz.4M.build.flash_size_bytes=0x400000 -phoenix_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +phoenix_v1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld phoenix_v1.menu.eesz.4M.build.spiffs_pagesize=256 phoenix_v1.menu.eesz.4M.upload.maximum_size=1044464 phoenix_v1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2290,7 +2290,7 @@ phoenix_v2.build.flash_freq=40 phoenix_v2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) phoenix_v2.menu.eesz.4M2M.build.flash_size=4M phoenix_v2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +phoenix_v2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld phoenix_v2.menu.eesz.4M2M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M2M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2300,7 +2300,7 @@ phoenix_v2.menu.eesz.4M2M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) phoenix_v2.menu.eesz.4M3M.build.flash_size=4M phoenix_v2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +phoenix_v2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld phoenix_v2.menu.eesz.4M3M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M3M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2310,7 +2310,7 @@ phoenix_v2.menu.eesz.4M3M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) phoenix_v2.menu.eesz.4M1M.build.flash_size=4M phoenix_v2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +phoenix_v2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld phoenix_v2.menu.eesz.4M1M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M1M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2320,7 +2320,7 @@ phoenix_v2.menu.eesz.4M1M.build.spiffs_blocksize=8192 phoenix_v2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) phoenix_v2.menu.eesz.4M.build.flash_size=4M phoenix_v2.menu.eesz.4M.build.flash_size_bytes=0x400000 -phoenix_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +phoenix_v2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld phoenix_v2.menu.eesz.4M.build.spiffs_pagesize=256 phoenix_v2.menu.eesz.4M.upload.maximum_size=1044464 phoenix_v2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2497,7 +2497,7 @@ nodemcu.build.flash_freq=40 nodemcu.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) nodemcu.menu.eesz.4M2M.build.flash_size=4M nodemcu.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +nodemcu.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld nodemcu.menu.eesz.4M2M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M2M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2507,7 +2507,7 @@ nodemcu.menu.eesz.4M2M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) nodemcu.menu.eesz.4M3M.build.flash_size=4M nodemcu.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +nodemcu.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld nodemcu.menu.eesz.4M3M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M3M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2517,7 +2517,7 @@ nodemcu.menu.eesz.4M3M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) nodemcu.menu.eesz.4M1M.build.flash_size=4M nodemcu.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +nodemcu.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld nodemcu.menu.eesz.4M1M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M1M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2527,7 +2527,7 @@ nodemcu.menu.eesz.4M1M.build.spiffs_blocksize=8192 nodemcu.menu.eesz.4M=4MB (FS:none OTA:~1019KB) nodemcu.menu.eesz.4M.build.flash_size=4M nodemcu.menu.eesz.4M.build.flash_size_bytes=0x400000 -nodemcu.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +nodemcu.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld nodemcu.menu.eesz.4M.build.spiffs_pagesize=256 nodemcu.menu.eesz.4M.upload.maximum_size=1044464 nodemcu.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2700,7 +2700,7 @@ nodemcuv2.build.flash_freq=40 nodemcuv2.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) nodemcuv2.menu.eesz.4M2M.build.flash_size=4M nodemcuv2.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +nodemcuv2.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld nodemcuv2.menu.eesz.4M2M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M2M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -2710,7 +2710,7 @@ nodemcuv2.menu.eesz.4M2M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) nodemcuv2.menu.eesz.4M3M.build.flash_size=4M nodemcuv2.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +nodemcuv2.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld nodemcuv2.menu.eesz.4M3M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M3M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -2720,7 +2720,7 @@ nodemcuv2.menu.eesz.4M3M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) nodemcuv2.menu.eesz.4M1M.build.flash_size=4M nodemcuv2.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +nodemcuv2.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld nodemcuv2.menu.eesz.4M1M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M1M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -2730,7 +2730,7 @@ nodemcuv2.menu.eesz.4M1M.build.spiffs_blocksize=8192 nodemcuv2.menu.eesz.4M=4MB (FS:none OTA:~1019KB) nodemcuv2.menu.eesz.4M.build.flash_size=4M nodemcuv2.menu.eesz.4M.build.flash_size_bytes=0x400000 -nodemcuv2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +nodemcuv2.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld nodemcuv2.menu.eesz.4M.build.spiffs_pagesize=256 nodemcuv2.menu.eesz.4M.upload.maximum_size=1044464 nodemcuv2.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -2907,7 +2907,7 @@ modwifi.build.flash_freq=40 modwifi.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) modwifi.menu.eesz.2M64.build.flash_size=2M modwifi.menu.eesz.2M64.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h +modwifi.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld modwifi.menu.eesz.2M64.build.spiffs_pagesize=256 modwifi.menu.eesz.2M64.upload.maximum_size=1044464 modwifi.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -2917,7 +2917,7 @@ modwifi.menu.eesz.2M64.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) modwifi.menu.eesz.2M128.build.flash_size=2M modwifi.menu.eesz.2M128.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h +modwifi.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld modwifi.menu.eesz.2M128.build.spiffs_pagesize=256 modwifi.menu.eesz.2M128.upload.maximum_size=1044464 modwifi.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -2927,7 +2927,7 @@ modwifi.menu.eesz.2M128.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) modwifi.menu.eesz.2M256.build.flash_size=2M modwifi.menu.eesz.2M256.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h +modwifi.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld modwifi.menu.eesz.2M256.build.spiffs_pagesize=256 modwifi.menu.eesz.2M256.upload.maximum_size=1044464 modwifi.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -2937,7 +2937,7 @@ modwifi.menu.eesz.2M256.build.spiffs_blocksize=4096 modwifi.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) modwifi.menu.eesz.2M512.build.flash_size=2M modwifi.menu.eesz.2M512.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h +modwifi.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld modwifi.menu.eesz.2M512.build.spiffs_pagesize=256 modwifi.menu.eesz.2M512.upload.maximum_size=1044464 modwifi.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -2947,7 +2947,7 @@ modwifi.menu.eesz.2M512.build.spiffs_blocksize=8192 modwifi.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) modwifi.menu.eesz.2M1M.build.flash_size=2M modwifi.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h +modwifi.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld modwifi.menu.eesz.2M1M.build.spiffs_pagesize=256 modwifi.menu.eesz.2M1M.upload.maximum_size=1044464 modwifi.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -2957,7 +2957,7 @@ modwifi.menu.eesz.2M1M.build.spiffs_blocksize=8192 modwifi.menu.eesz.2M=2MB (FS:none OTA:~1019KB) modwifi.menu.eesz.2M.build.flash_size=2M modwifi.menu.eesz.2M.build.flash_size_bytes=0x200000 -modwifi.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h +modwifi.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld modwifi.menu.eesz.2M.build.spiffs_pagesize=256 modwifi.menu.eesz.2M.upload.maximum_size=1044464 modwifi.menu.eesz.2M.build.rfcal_addr=0x1FC000 @@ -3130,7 +3130,7 @@ thing.build.flash_freq=40 thing.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) thing.menu.eesz.512K32.build.flash_size=512K thing.menu.eesz.512K32.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h +thing.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld thing.menu.eesz.512K32.build.spiffs_pagesize=256 thing.menu.eesz.512K32.upload.maximum_size=466928 thing.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -3140,7 +3140,7 @@ thing.menu.eesz.512K32.build.spiffs_blocksize=4096 thing.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) thing.menu.eesz.512K64.build.flash_size=512K thing.menu.eesz.512K64.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h +thing.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld thing.menu.eesz.512K64.build.spiffs_pagesize=256 thing.menu.eesz.512K64.upload.maximum_size=434160 thing.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -3150,7 +3150,7 @@ thing.menu.eesz.512K64.build.spiffs_blocksize=4096 thing.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) thing.menu.eesz.512K128.build.flash_size=512K thing.menu.eesz.512K128.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h +thing.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld thing.menu.eesz.512K128.build.spiffs_pagesize=256 thing.menu.eesz.512K128.upload.maximum_size=368624 thing.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -3160,7 +3160,7 @@ thing.menu.eesz.512K128.build.spiffs_blocksize=4096 thing.menu.eesz.512K=512KB (FS:none OTA:~246KB) thing.menu.eesz.512K.build.flash_size=512K thing.menu.eesz.512K.build.flash_size_bytes=0x80000 -thing.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h +thing.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld thing.menu.eesz.512K.build.spiffs_pagesize=256 thing.menu.eesz.512K.upload.maximum_size=499696 thing.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -3333,7 +3333,7 @@ thingdev.build.flash_freq=40 thingdev.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) thingdev.menu.eesz.512K32.build.flash_size=512K thingdev.menu.eesz.512K32.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h +thingdev.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld thingdev.menu.eesz.512K32.build.spiffs_pagesize=256 thingdev.menu.eesz.512K32.upload.maximum_size=466928 thingdev.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -3343,7 +3343,7 @@ thingdev.menu.eesz.512K32.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) thingdev.menu.eesz.512K64.build.flash_size=512K thingdev.menu.eesz.512K64.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h +thingdev.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld thingdev.menu.eesz.512K64.build.spiffs_pagesize=256 thingdev.menu.eesz.512K64.upload.maximum_size=434160 thingdev.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -3353,7 +3353,7 @@ thingdev.menu.eesz.512K64.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) thingdev.menu.eesz.512K128.build.flash_size=512K thingdev.menu.eesz.512K128.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h +thingdev.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld thingdev.menu.eesz.512K128.build.spiffs_pagesize=256 thingdev.menu.eesz.512K128.upload.maximum_size=368624 thingdev.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -3363,7 +3363,7 @@ thingdev.menu.eesz.512K128.build.spiffs_blocksize=4096 thingdev.menu.eesz.512K=512KB (FS:none OTA:~246KB) thingdev.menu.eesz.512K.build.flash_size=512K thingdev.menu.eesz.512K.build.flash_size_bytes=0x80000 -thingdev.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h +thingdev.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld thingdev.menu.eesz.512K.build.spiffs_pagesize=256 thingdev.menu.eesz.512K.upload.maximum_size=499696 thingdev.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -3536,7 +3536,7 @@ blynk.build.flash_freq=40 blynk.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) blynk.menu.eesz.4M2M.build.flash_size=4M blynk.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +blynk.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld blynk.menu.eesz.4M2M.build.spiffs_pagesize=256 blynk.menu.eesz.4M2M.upload.maximum_size=1044464 blynk.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3546,7 +3546,7 @@ blynk.menu.eesz.4M2M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) blynk.menu.eesz.4M3M.build.flash_size=4M blynk.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +blynk.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld blynk.menu.eesz.4M3M.build.spiffs_pagesize=256 blynk.menu.eesz.4M3M.upload.maximum_size=1044464 blynk.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3556,7 +3556,7 @@ blynk.menu.eesz.4M3M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) blynk.menu.eesz.4M1M.build.flash_size=4M blynk.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +blynk.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld blynk.menu.eesz.4M1M.build.spiffs_pagesize=256 blynk.menu.eesz.4M1M.upload.maximum_size=1044464 blynk.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3566,7 +3566,7 @@ blynk.menu.eesz.4M1M.build.spiffs_blocksize=8192 blynk.menu.eesz.4M=4MB (FS:none OTA:~1019KB) blynk.menu.eesz.4M.build.flash_size=4M blynk.menu.eesz.4M.build.flash_size_bytes=0x400000 -blynk.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +blynk.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld blynk.menu.eesz.4M.build.spiffs_pagesize=256 blynk.menu.eesz.4M.upload.maximum_size=1044464 blynk.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -3739,7 +3739,7 @@ esp210.build.flash_freq=40 esp210.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) esp210.menu.eesz.4M2M.build.flash_size=4M esp210.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +esp210.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld esp210.menu.eesz.4M2M.build.spiffs_pagesize=256 esp210.menu.eesz.4M2M.upload.maximum_size=1044464 esp210.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3749,7 +3749,7 @@ esp210.menu.eesz.4M2M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) esp210.menu.eesz.4M3M.build.flash_size=4M esp210.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +esp210.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld esp210.menu.eesz.4M3M.build.spiffs_pagesize=256 esp210.menu.eesz.4M3M.upload.maximum_size=1044464 esp210.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3759,7 +3759,7 @@ esp210.menu.eesz.4M3M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) esp210.menu.eesz.4M1M.build.flash_size=4M esp210.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +esp210.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld esp210.menu.eesz.4M1M.build.spiffs_pagesize=256 esp210.menu.eesz.4M1M.upload.maximum_size=1044464 esp210.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3769,7 +3769,7 @@ esp210.menu.eesz.4M1M.build.spiffs_blocksize=8192 esp210.menu.eesz.4M=4MB (FS:none OTA:~1019KB) esp210.menu.eesz.4M.build.flash_size=4M esp210.menu.eesz.4M.build.flash_size_bytes=0x400000 -esp210.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +esp210.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld esp210.menu.eesz.4M.build.spiffs_pagesize=256 esp210.menu.eesz.4M.upload.maximum_size=1044464 esp210.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -3942,7 +3942,7 @@ d1_mini.build.flash_freq=40 d1_mini.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) d1_mini.menu.eesz.4M2M.build.flash_size=4M d1_mini.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +d1_mini.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld d1_mini.menu.eesz.4M2M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M2M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -3952,7 +3952,7 @@ d1_mini.menu.eesz.4M2M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) d1_mini.menu.eesz.4M3M.build.flash_size=4M d1_mini.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +d1_mini.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld d1_mini.menu.eesz.4M3M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M3M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -3962,7 +3962,7 @@ d1_mini.menu.eesz.4M3M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) d1_mini.menu.eesz.4M1M.build.flash_size=4M d1_mini.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +d1_mini.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld d1_mini.menu.eesz.4M1M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M1M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -3972,7 +3972,7 @@ d1_mini.menu.eesz.4M1M.build.spiffs_blocksize=8192 d1_mini.menu.eesz.4M=4MB (FS:none OTA:~1019KB) d1_mini.menu.eesz.4M.build.flash_size=4M d1_mini.menu.eesz.4M.build.flash_size_bytes=0x400000 -d1_mini.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +d1_mini.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld d1_mini.menu.eesz.4M.build.spiffs_pagesize=256 d1_mini.menu.eesz.4M.upload.maximum_size=1044464 d1_mini.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4145,7 +4145,7 @@ d1_mini_pro.build.flash_freq=40 d1_mini_pro.menu.eesz.16M14M=16MB (FS:14MB OTA:~1019KB) d1_mini_pro.menu.eesz.16M14M.build.flash_size=16M d1_mini_pro.menu.eesz.16M14M.build.flash_size_bytes=0x1000000 -d1_mini_pro.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld.h +d1_mini_pro.menu.eesz.16M14M.build.flash_ld=eagle.flash.16m14m.ld d1_mini_pro.menu.eesz.16M14M.build.spiffs_pagesize=256 d1_mini_pro.menu.eesz.16M14M.upload.maximum_size=1044464 d1_mini_pro.menu.eesz.16M14M.build.rfcal_addr=0xFFC000 @@ -4155,7 +4155,7 @@ d1_mini_pro.menu.eesz.16M14M.build.spiffs_blocksize=8192 d1_mini_pro.menu.eesz.16M15M=16MB (FS:15MB OTA:~512KB) d1_mini_pro.menu.eesz.16M15M.build.flash_size=16M d1_mini_pro.menu.eesz.16M15M.build.flash_size_bytes=0x1000000 -d1_mini_pro.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld.h +d1_mini_pro.menu.eesz.16M15M.build.flash_ld=eagle.flash.16m15m.ld d1_mini_pro.menu.eesz.16M15M.build.spiffs_pagesize=256 d1_mini_pro.menu.eesz.16M15M.upload.maximum_size=1044464 d1_mini_pro.menu.eesz.16M15M.build.rfcal_addr=0xFFC000 @@ -4331,7 +4331,7 @@ d1_mini_lite.build.flash_freq=40 d1_mini_lite.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) d1_mini_lite.menu.eesz.1M64.build.flash_size=1M d1_mini_lite.menu.eesz.1M64.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +d1_mini_lite.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld d1_mini_lite.menu.eesz.1M64.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M64.upload.maximum_size=958448 d1_mini_lite.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -4341,7 +4341,7 @@ d1_mini_lite.menu.eesz.1M64.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) d1_mini_lite.menu.eesz.1M128.build.flash_size=1M d1_mini_lite.menu.eesz.1M128.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +d1_mini_lite.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld d1_mini_lite.menu.eesz.1M128.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M128.upload.maximum_size=892912 d1_mini_lite.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -4351,7 +4351,7 @@ d1_mini_lite.menu.eesz.1M128.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) d1_mini_lite.menu.eesz.1M144.build.flash_size=1M d1_mini_lite.menu.eesz.1M144.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +d1_mini_lite.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld d1_mini_lite.menu.eesz.1M144.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M144.upload.maximum_size=876528 d1_mini_lite.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -4361,7 +4361,7 @@ d1_mini_lite.menu.eesz.1M144.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) d1_mini_lite.menu.eesz.1M160.build.flash_size=1M d1_mini_lite.menu.eesz.1M160.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +d1_mini_lite.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld d1_mini_lite.menu.eesz.1M160.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M160.upload.maximum_size=860144 d1_mini_lite.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -4371,7 +4371,7 @@ d1_mini_lite.menu.eesz.1M160.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) d1_mini_lite.menu.eesz.1M192.build.flash_size=1M d1_mini_lite.menu.eesz.1M192.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +d1_mini_lite.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld d1_mini_lite.menu.eesz.1M192.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M192.upload.maximum_size=827376 d1_mini_lite.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -4381,7 +4381,7 @@ d1_mini_lite.menu.eesz.1M192.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) d1_mini_lite.menu.eesz.1M256.build.flash_size=1M d1_mini_lite.menu.eesz.1M256.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +d1_mini_lite.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld d1_mini_lite.menu.eesz.1M256.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M256.upload.maximum_size=761840 d1_mini_lite.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -4391,7 +4391,7 @@ d1_mini_lite.menu.eesz.1M256.build.spiffs_blocksize=4096 d1_mini_lite.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) d1_mini_lite.menu.eesz.1M512.build.flash_size=1M d1_mini_lite.menu.eesz.1M512.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +d1_mini_lite.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld d1_mini_lite.menu.eesz.1M512.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M512.upload.maximum_size=499696 d1_mini_lite.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -4401,7 +4401,7 @@ d1_mini_lite.menu.eesz.1M512.build.spiffs_blocksize=8192 d1_mini_lite.menu.eesz.1M=1MB (FS:none OTA:~502KB) d1_mini_lite.menu.eesz.1M.build.flash_size=1M d1_mini_lite.menu.eesz.1M.build.flash_size_bytes=0x100000 -d1_mini_lite.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +d1_mini_lite.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld d1_mini_lite.menu.eesz.1M.build.spiffs_pagesize=256 d1_mini_lite.menu.eesz.1M.upload.maximum_size=1023984 d1_mini_lite.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -4574,7 +4574,7 @@ d1.build.flash_freq=40 d1.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) d1.menu.eesz.4M2M.build.flash_size=4M d1.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +d1.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld d1.menu.eesz.4M2M.build.spiffs_pagesize=256 d1.menu.eesz.4M2M.upload.maximum_size=1044464 d1.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4584,7 +4584,7 @@ d1.menu.eesz.4M2M.build.spiffs_blocksize=8192 d1.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) d1.menu.eesz.4M3M.build.flash_size=4M d1.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +d1.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld d1.menu.eesz.4M3M.build.spiffs_pagesize=256 d1.menu.eesz.4M3M.upload.maximum_size=1044464 d1.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -4594,7 +4594,7 @@ d1.menu.eesz.4M3M.build.spiffs_blocksize=8192 d1.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) d1.menu.eesz.4M1M.build.flash_size=4M d1.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +d1.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld d1.menu.eesz.4M1M.build.spiffs_pagesize=256 d1.menu.eesz.4M1M.upload.maximum_size=1044464 d1.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -4604,7 +4604,7 @@ d1.menu.eesz.4M1M.build.spiffs_blocksize=8192 d1.menu.eesz.4M=4MB (FS:none OTA:~1019KB) d1.menu.eesz.4M.build.flash_size=4M d1.menu.eesz.4M.build.flash_size_bytes=0x400000 -d1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +d1.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld d1.menu.eesz.4M.build.spiffs_pagesize=256 d1.menu.eesz.4M.upload.maximum_size=1044464 d1.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4780,7 +4780,7 @@ espino.build.flash_freq=40 espino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espino.menu.eesz.4M2M.build.flash_size=4M espino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espino.menu.eesz.4M2M.build.spiffs_pagesize=256 espino.menu.eesz.4M2M.upload.maximum_size=1044464 espino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4790,7 +4790,7 @@ espino.menu.eesz.4M2M.build.spiffs_blocksize=8192 espino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espino.menu.eesz.4M3M.build.flash_size=4M espino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espino.menu.eesz.4M3M.build.spiffs_pagesize=256 espino.menu.eesz.4M3M.upload.maximum_size=1044464 espino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -4800,7 +4800,7 @@ espino.menu.eesz.4M3M.build.spiffs_blocksize=8192 espino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espino.menu.eesz.4M1M.build.flash_size=4M espino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espino.menu.eesz.4M1M.build.spiffs_pagesize=256 espino.menu.eesz.4M1M.upload.maximum_size=1044464 espino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -4810,7 +4810,7 @@ espino.menu.eesz.4M1M.build.spiffs_blocksize=8192 espino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espino.menu.eesz.4M.build.flash_size=4M espino.menu.eesz.4M.build.flash_size_bytes=0x400000 -espino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espino.menu.eesz.4M.build.spiffs_pagesize=256 espino.menu.eesz.4M.upload.maximum_size=1044464 espino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -4983,7 +4983,7 @@ espinotee.build.flash_freq=40 espinotee.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espinotee.menu.eesz.4M2M.build.flash_size=4M espinotee.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espinotee.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espinotee.menu.eesz.4M2M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M2M.upload.maximum_size=1044464 espinotee.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -4993,7 +4993,7 @@ espinotee.menu.eesz.4M2M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espinotee.menu.eesz.4M3M.build.flash_size=4M espinotee.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espinotee.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espinotee.menu.eesz.4M3M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M3M.upload.maximum_size=1044464 espinotee.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5003,7 +5003,7 @@ espinotee.menu.eesz.4M3M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espinotee.menu.eesz.4M1M.build.flash_size=4M espinotee.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espinotee.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espinotee.menu.eesz.4M1M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M1M.upload.maximum_size=1044464 espinotee.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5013,7 +5013,7 @@ espinotee.menu.eesz.4M1M.build.spiffs_blocksize=8192 espinotee.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espinotee.menu.eesz.4M.build.flash_size=4M espinotee.menu.eesz.4M.build.flash_size_bytes=0x400000 -espinotee.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espinotee.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espinotee.menu.eesz.4M.build.spiffs_pagesize=256 espinotee.menu.eesz.4M.upload.maximum_size=1044464 espinotee.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -5210,7 +5210,7 @@ wifinfo.menu.FlashFreq.26.build.flash_freq=26 wifinfo.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) wifinfo.menu.eesz.1M64.build.flash_size=1M wifinfo.menu.eesz.1M64.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +wifinfo.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld wifinfo.menu.eesz.1M64.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M64.upload.maximum_size=958448 wifinfo.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -5220,7 +5220,7 @@ wifinfo.menu.eesz.1M64.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) wifinfo.menu.eesz.1M128.build.flash_size=1M wifinfo.menu.eesz.1M128.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +wifinfo.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld wifinfo.menu.eesz.1M128.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M128.upload.maximum_size=892912 wifinfo.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -5230,7 +5230,7 @@ wifinfo.menu.eesz.1M128.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) wifinfo.menu.eesz.1M144.build.flash_size=1M wifinfo.menu.eesz.1M144.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +wifinfo.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld wifinfo.menu.eesz.1M144.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M144.upload.maximum_size=876528 wifinfo.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -5240,7 +5240,7 @@ wifinfo.menu.eesz.1M144.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) wifinfo.menu.eesz.1M160.build.flash_size=1M wifinfo.menu.eesz.1M160.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +wifinfo.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld wifinfo.menu.eesz.1M160.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M160.upload.maximum_size=860144 wifinfo.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -5250,7 +5250,7 @@ wifinfo.menu.eesz.1M160.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) wifinfo.menu.eesz.1M192.build.flash_size=1M wifinfo.menu.eesz.1M192.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +wifinfo.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld wifinfo.menu.eesz.1M192.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M192.upload.maximum_size=827376 wifinfo.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -5260,7 +5260,7 @@ wifinfo.menu.eesz.1M192.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) wifinfo.menu.eesz.1M256.build.flash_size=1M wifinfo.menu.eesz.1M256.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +wifinfo.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld wifinfo.menu.eesz.1M256.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M256.upload.maximum_size=761840 wifinfo.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -5270,7 +5270,7 @@ wifinfo.menu.eesz.1M256.build.spiffs_blocksize=4096 wifinfo.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) wifinfo.menu.eesz.1M512.build.flash_size=1M wifinfo.menu.eesz.1M512.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +wifinfo.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld wifinfo.menu.eesz.1M512.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M512.upload.maximum_size=499696 wifinfo.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -5280,7 +5280,7 @@ wifinfo.menu.eesz.1M512.build.spiffs_blocksize=8192 wifinfo.menu.eesz.1M=1MB (FS:none OTA:~502KB) wifinfo.menu.eesz.1M.build.flash_size=1M wifinfo.menu.eesz.1M.build.flash_size_bytes=0x100000 -wifinfo.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +wifinfo.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld wifinfo.menu.eesz.1M.build.spiffs_pagesize=256 wifinfo.menu.eesz.1M.upload.maximum_size=1023984 wifinfo.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -5465,7 +5465,7 @@ arduino-esp8266.build.flash_freq=40 arduino-esp8266.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) arduino-esp8266.menu.eesz.4M2M.build.flash_size=4M arduino-esp8266.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +arduino-esp8266.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld arduino-esp8266.menu.eesz.4M2M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M2M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -5475,7 +5475,7 @@ arduino-esp8266.menu.eesz.4M2M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) arduino-esp8266.menu.eesz.4M3M.build.flash_size=4M arduino-esp8266.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +arduino-esp8266.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld arduino-esp8266.menu.eesz.4M3M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M3M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5485,7 +5485,7 @@ arduino-esp8266.menu.eesz.4M3M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) arduino-esp8266.menu.eesz.4M1M.build.flash_size=4M arduino-esp8266.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +arduino-esp8266.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld arduino-esp8266.menu.eesz.4M1M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M1M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5495,7 +5495,7 @@ arduino-esp8266.menu.eesz.4M1M.build.spiffs_blocksize=8192 arduino-esp8266.menu.eesz.4M=4MB (FS:none OTA:~1019KB) arduino-esp8266.menu.eesz.4M.build.flash_size=4M arduino-esp8266.menu.eesz.4M.build.flash_size_bytes=0x400000 -arduino-esp8266.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +arduino-esp8266.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld arduino-esp8266.menu.eesz.4M.build.spiffs_pagesize=256 arduino-esp8266.menu.eesz.4M.upload.maximum_size=1044464 arduino-esp8266.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -5669,7 +5669,7 @@ gen4iod.build.flash_freq=80 gen4iod.menu.eesz.512K32=512KB (FS:32KB OTA:~230KB) gen4iod.menu.eesz.512K32.build.flash_size=512K gen4iod.menu.eesz.512K32.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld.h +gen4iod.menu.eesz.512K32.build.flash_ld=eagle.flash.512k32.ld gen4iod.menu.eesz.512K32.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K32.upload.maximum_size=466928 gen4iod.menu.eesz.512K32.build.rfcal_addr=0x7C000 @@ -5679,7 +5679,7 @@ gen4iod.menu.eesz.512K32.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K64=512KB (FS:64KB OTA:~214KB) gen4iod.menu.eesz.512K64.build.flash_size=512K gen4iod.menu.eesz.512K64.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld.h +gen4iod.menu.eesz.512K64.build.flash_ld=eagle.flash.512k64.ld gen4iod.menu.eesz.512K64.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K64.upload.maximum_size=434160 gen4iod.menu.eesz.512K64.build.rfcal_addr=0x7C000 @@ -5689,7 +5689,7 @@ gen4iod.menu.eesz.512K64.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K128=512KB (FS:128KB OTA:~182KB) gen4iod.menu.eesz.512K128.build.flash_size=512K gen4iod.menu.eesz.512K128.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld.h +gen4iod.menu.eesz.512K128.build.flash_ld=eagle.flash.512k128.ld gen4iod.menu.eesz.512K128.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K128.upload.maximum_size=368624 gen4iod.menu.eesz.512K128.build.rfcal_addr=0x7C000 @@ -5699,7 +5699,7 @@ gen4iod.menu.eesz.512K128.build.spiffs_blocksize=4096 gen4iod.menu.eesz.512K=512KB (FS:none OTA:~246KB) gen4iod.menu.eesz.512K.build.flash_size=512K gen4iod.menu.eesz.512K.build.flash_size_bytes=0x80000 -gen4iod.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld.h +gen4iod.menu.eesz.512K.build.flash_ld=eagle.flash.512k.ld gen4iod.menu.eesz.512K.build.spiffs_pagesize=256 gen4iod.menu.eesz.512K.upload.maximum_size=499696 gen4iod.menu.eesz.512K.build.rfcal_addr=0x7C000 @@ -5873,7 +5873,7 @@ oak.build.flash_freq=40 oak.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) oak.menu.eesz.4M2M.build.flash_size=4M oak.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +oak.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld oak.menu.eesz.4M2M.build.spiffs_pagesize=256 oak.menu.eesz.4M2M.upload.maximum_size=1044464 oak.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -5883,7 +5883,7 @@ oak.menu.eesz.4M2M.build.spiffs_blocksize=8192 oak.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) oak.menu.eesz.4M3M.build.flash_size=4M oak.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +oak.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld oak.menu.eesz.4M3M.build.spiffs_pagesize=256 oak.menu.eesz.4M3M.upload.maximum_size=1044464 oak.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -5893,7 +5893,7 @@ oak.menu.eesz.4M3M.build.spiffs_blocksize=8192 oak.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) oak.menu.eesz.4M1M.build.flash_size=4M oak.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +oak.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld oak.menu.eesz.4M1M.build.spiffs_pagesize=256 oak.menu.eesz.4M1M.upload.maximum_size=1044464 oak.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -5903,7 +5903,7 @@ oak.menu.eesz.4M1M.build.spiffs_blocksize=8192 oak.menu.eesz.4M=4MB (FS:none OTA:~1019KB) oak.menu.eesz.4M.build.flash_size=4M oak.menu.eesz.4M.build.flash_size_bytes=0x400000 -oak.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +oak.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld oak.menu.eesz.4M.build.spiffs_pagesize=256 oak.menu.eesz.4M.upload.maximum_size=1044464 oak.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -6076,7 +6076,7 @@ wifiduino.build.flash_freq=40 wifiduino.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) wifiduino.menu.eesz.4M2M.build.flash_size=4M wifiduino.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +wifiduino.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld wifiduino.menu.eesz.4M2M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M2M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -6086,7 +6086,7 @@ wifiduino.menu.eesz.4M2M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) wifiduino.menu.eesz.4M3M.build.flash_size=4M wifiduino.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +wifiduino.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld wifiduino.menu.eesz.4M3M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M3M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -6096,7 +6096,7 @@ wifiduino.menu.eesz.4M3M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) wifiduino.menu.eesz.4M1M.build.flash_size=4M wifiduino.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +wifiduino.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld wifiduino.menu.eesz.4M1M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M1M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -6106,7 +6106,7 @@ wifiduino.menu.eesz.4M1M.build.spiffs_blocksize=8192 wifiduino.menu.eesz.4M=4MB (FS:none OTA:~1019KB) wifiduino.menu.eesz.4M.build.flash_size=4M wifiduino.menu.eesz.4M.build.flash_size_bytes=0x400000 -wifiduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +wifiduino.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld wifiduino.menu.eesz.4M.build.spiffs_pagesize=256 wifiduino.menu.eesz.4M.upload.maximum_size=1044464 wifiduino.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -6296,7 +6296,7 @@ wifi_slot.menu.FlashMode.qio.build.flash_flags=-DFLASHMODE_QIO wifi_slot.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) wifi_slot.menu.eesz.1M64.build.flash_size=1M wifi_slot.menu.eesz.1M64.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +wifi_slot.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld wifi_slot.menu.eesz.1M64.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M64.upload.maximum_size=958448 wifi_slot.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -6306,7 +6306,7 @@ wifi_slot.menu.eesz.1M64.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) wifi_slot.menu.eesz.1M128.build.flash_size=1M wifi_slot.menu.eesz.1M128.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +wifi_slot.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld wifi_slot.menu.eesz.1M128.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M128.upload.maximum_size=892912 wifi_slot.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -6316,7 +6316,7 @@ wifi_slot.menu.eesz.1M128.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) wifi_slot.menu.eesz.1M144.build.flash_size=1M wifi_slot.menu.eesz.1M144.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +wifi_slot.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld wifi_slot.menu.eesz.1M144.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M144.upload.maximum_size=876528 wifi_slot.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -6326,7 +6326,7 @@ wifi_slot.menu.eesz.1M144.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) wifi_slot.menu.eesz.1M160.build.flash_size=1M wifi_slot.menu.eesz.1M160.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +wifi_slot.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld wifi_slot.menu.eesz.1M160.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M160.upload.maximum_size=860144 wifi_slot.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -6336,7 +6336,7 @@ wifi_slot.menu.eesz.1M160.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) wifi_slot.menu.eesz.1M192.build.flash_size=1M wifi_slot.menu.eesz.1M192.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +wifi_slot.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld wifi_slot.menu.eesz.1M192.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M192.upload.maximum_size=827376 wifi_slot.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -6346,7 +6346,7 @@ wifi_slot.menu.eesz.1M192.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) wifi_slot.menu.eesz.1M256.build.flash_size=1M wifi_slot.menu.eesz.1M256.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +wifi_slot.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld wifi_slot.menu.eesz.1M256.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M256.upload.maximum_size=761840 wifi_slot.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -6356,7 +6356,7 @@ wifi_slot.menu.eesz.1M256.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) wifi_slot.menu.eesz.1M512.build.flash_size=1M wifi_slot.menu.eesz.1M512.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +wifi_slot.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld wifi_slot.menu.eesz.1M512.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M512.upload.maximum_size=499696 wifi_slot.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -6366,14 +6366,14 @@ wifi_slot.menu.eesz.1M512.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.1M=1MB (FS:none OTA:~502KB) wifi_slot.menu.eesz.1M.build.flash_size=1M wifi_slot.menu.eesz.1M.build.flash_size_bytes=0x100000 -wifi_slot.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +wifi_slot.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld wifi_slot.menu.eesz.1M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.1M.upload.maximum_size=1023984 wifi_slot.menu.eesz.1M.build.rfcal_addr=0xFC000 wifi_slot.menu.eesz.2M64=2MB (FS:64KB OTA:~992KB) wifi_slot.menu.eesz.2M64.build.flash_size=2M wifi_slot.menu.eesz.2M64.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld.h +wifi_slot.menu.eesz.2M64.build.flash_ld=eagle.flash.2m64.ld wifi_slot.menu.eesz.2M64.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M64.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M64.build.rfcal_addr=0x1FC000 @@ -6383,7 +6383,7 @@ wifi_slot.menu.eesz.2M64.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M128=2MB (FS:128KB OTA:~960KB) wifi_slot.menu.eesz.2M128.build.flash_size=2M wifi_slot.menu.eesz.2M128.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld.h +wifi_slot.menu.eesz.2M128.build.flash_ld=eagle.flash.2m128.ld wifi_slot.menu.eesz.2M128.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M128.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M128.build.rfcal_addr=0x1FC000 @@ -6393,7 +6393,7 @@ wifi_slot.menu.eesz.2M128.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M256=2MB (FS:256KB OTA:~896KB) wifi_slot.menu.eesz.2M256.build.flash_size=2M wifi_slot.menu.eesz.2M256.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld.h +wifi_slot.menu.eesz.2M256.build.flash_ld=eagle.flash.2m256.ld wifi_slot.menu.eesz.2M256.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M256.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M256.build.rfcal_addr=0x1FC000 @@ -6403,7 +6403,7 @@ wifi_slot.menu.eesz.2M256.build.spiffs_blocksize=4096 wifi_slot.menu.eesz.2M512=2MB (FS:512KB OTA:~768KB) wifi_slot.menu.eesz.2M512.build.flash_size=2M wifi_slot.menu.eesz.2M512.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld.h +wifi_slot.menu.eesz.2M512.build.flash_ld=eagle.flash.2m512.ld wifi_slot.menu.eesz.2M512.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M512.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M512.build.rfcal_addr=0x1FC000 @@ -6413,7 +6413,7 @@ wifi_slot.menu.eesz.2M512.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.2M1M=2MB (FS:1MB OTA:~512KB) wifi_slot.menu.eesz.2M1M.build.flash_size=2M wifi_slot.menu.eesz.2M1M.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld.h +wifi_slot.menu.eesz.2M1M.build.flash_ld=eagle.flash.2m1m.ld wifi_slot.menu.eesz.2M1M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M1M.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M1M.build.rfcal_addr=0x1FC000 @@ -6423,7 +6423,7 @@ wifi_slot.menu.eesz.2M1M.build.spiffs_blocksize=8192 wifi_slot.menu.eesz.2M=2MB (FS:none OTA:~1019KB) wifi_slot.menu.eesz.2M.build.flash_size=2M wifi_slot.menu.eesz.2M.build.flash_size_bytes=0x200000 -wifi_slot.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld.h +wifi_slot.menu.eesz.2M.build.flash_ld=eagle.flash.2m.ld wifi_slot.menu.eesz.2M.build.spiffs_pagesize=256 wifi_slot.menu.eesz.2M.upload.maximum_size=1044464 wifi_slot.menu.eesz.2M.build.rfcal_addr=0x1FC000 @@ -6596,7 +6596,7 @@ wiolink.build.flash_freq=40 wiolink.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) wiolink.menu.eesz.4M2M.build.flash_size=4M wiolink.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +wiolink.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld wiolink.menu.eesz.4M2M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M2M.upload.maximum_size=1044464 wiolink.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -6606,7 +6606,7 @@ wiolink.menu.eesz.4M2M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) wiolink.menu.eesz.4M3M.build.flash_size=4M wiolink.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +wiolink.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld wiolink.menu.eesz.4M3M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M3M.upload.maximum_size=1044464 wiolink.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -6616,7 +6616,7 @@ wiolink.menu.eesz.4M3M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) wiolink.menu.eesz.4M1M.build.flash_size=4M wiolink.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +wiolink.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld wiolink.menu.eesz.4M1M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M1M.upload.maximum_size=1044464 wiolink.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -6626,7 +6626,7 @@ wiolink.menu.eesz.4M1M.build.spiffs_blocksize=8192 wiolink.menu.eesz.4M=4MB (FS:none OTA:~1019KB) wiolink.menu.eesz.4M.build.flash_size=4M wiolink.menu.eesz.4M.build.flash_size_bytes=0x400000 -wiolink.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +wiolink.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld wiolink.menu.eesz.4M.build.spiffs_pagesize=256 wiolink.menu.eesz.4M.upload.maximum_size=1044464 wiolink.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -6799,7 +6799,7 @@ espectro.build.flash_freq=40 espectro.menu.eesz.4M2M=4MB (FS:2MB OTA:~1019KB) espectro.menu.eesz.4M2M.build.flash_size=4M espectro.menu.eesz.4M2M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld.h +espectro.menu.eesz.4M2M.build.flash_ld=eagle.flash.4m2m.ld espectro.menu.eesz.4M2M.build.spiffs_pagesize=256 espectro.menu.eesz.4M2M.upload.maximum_size=1044464 espectro.menu.eesz.4M2M.build.rfcal_addr=0x3FC000 @@ -6809,7 +6809,7 @@ espectro.menu.eesz.4M2M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M3M=4MB (FS:3MB OTA:~512KB) espectro.menu.eesz.4M3M.build.flash_size=4M espectro.menu.eesz.4M3M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld.h +espectro.menu.eesz.4M3M.build.flash_ld=eagle.flash.4m3m.ld espectro.menu.eesz.4M3M.build.spiffs_pagesize=256 espectro.menu.eesz.4M3M.upload.maximum_size=1044464 espectro.menu.eesz.4M3M.build.rfcal_addr=0x3FC000 @@ -6819,7 +6819,7 @@ espectro.menu.eesz.4M3M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M1M=4MB (FS:1MB OTA:~1019KB) espectro.menu.eesz.4M1M.build.flash_size=4M espectro.menu.eesz.4M1M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld.h +espectro.menu.eesz.4M1M.build.flash_ld=eagle.flash.4m1m.ld espectro.menu.eesz.4M1M.build.spiffs_pagesize=256 espectro.menu.eesz.4M1M.upload.maximum_size=1044464 espectro.menu.eesz.4M1M.build.rfcal_addr=0x3FC000 @@ -6829,7 +6829,7 @@ espectro.menu.eesz.4M1M.build.spiffs_blocksize=8192 espectro.menu.eesz.4M=4MB (FS:none OTA:~1019KB) espectro.menu.eesz.4M.build.flash_size=4M espectro.menu.eesz.4M.build.flash_size_bytes=0x400000 -espectro.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld.h +espectro.menu.eesz.4M.build.flash_ld=eagle.flash.4m.ld espectro.menu.eesz.4M.build.spiffs_pagesize=256 espectro.menu.eesz.4M.upload.maximum_size=1044464 espectro.menu.eesz.4M.build.rfcal_addr=0x3FC000 @@ -7012,7 +7012,7 @@ sonoff.build.flash_freq=40 sonoff.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) sonoff.menu.eesz.1M64.build.flash_size=1M sonoff.menu.eesz.1M64.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +sonoff.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld sonoff.menu.eesz.1M64.build.spiffs_pagesize=256 sonoff.menu.eesz.1M64.upload.maximum_size=958448 sonoff.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -7022,7 +7022,7 @@ sonoff.menu.eesz.1M64.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) sonoff.menu.eesz.1M128.build.flash_size=1M sonoff.menu.eesz.1M128.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +sonoff.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld sonoff.menu.eesz.1M128.build.spiffs_pagesize=256 sonoff.menu.eesz.1M128.upload.maximum_size=892912 sonoff.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -7032,7 +7032,7 @@ sonoff.menu.eesz.1M128.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) sonoff.menu.eesz.1M144.build.flash_size=1M sonoff.menu.eesz.1M144.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +sonoff.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld sonoff.menu.eesz.1M144.build.spiffs_pagesize=256 sonoff.menu.eesz.1M144.upload.maximum_size=876528 sonoff.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -7042,7 +7042,7 @@ sonoff.menu.eesz.1M144.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) sonoff.menu.eesz.1M160.build.flash_size=1M sonoff.menu.eesz.1M160.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +sonoff.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld sonoff.menu.eesz.1M160.build.spiffs_pagesize=256 sonoff.menu.eesz.1M160.upload.maximum_size=860144 sonoff.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -7052,7 +7052,7 @@ sonoff.menu.eesz.1M160.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) sonoff.menu.eesz.1M192.build.flash_size=1M sonoff.menu.eesz.1M192.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +sonoff.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld sonoff.menu.eesz.1M192.build.spiffs_pagesize=256 sonoff.menu.eesz.1M192.upload.maximum_size=827376 sonoff.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -7062,7 +7062,7 @@ sonoff.menu.eesz.1M192.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) sonoff.menu.eesz.1M256.build.flash_size=1M sonoff.menu.eesz.1M256.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +sonoff.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld sonoff.menu.eesz.1M256.build.spiffs_pagesize=256 sonoff.menu.eesz.1M256.upload.maximum_size=761840 sonoff.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -7072,7 +7072,7 @@ sonoff.menu.eesz.1M256.build.spiffs_blocksize=4096 sonoff.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) sonoff.menu.eesz.1M512.build.flash_size=1M sonoff.menu.eesz.1M512.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +sonoff.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld sonoff.menu.eesz.1M512.build.spiffs_pagesize=256 sonoff.menu.eesz.1M512.upload.maximum_size=499696 sonoff.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -7082,7 +7082,7 @@ sonoff.menu.eesz.1M512.build.spiffs_blocksize=8192 sonoff.menu.eesz.1M=1MB (FS:none OTA:~502KB) sonoff.menu.eesz.1M.build.flash_size=1M sonoff.menu.eesz.1M.build.flash_size_bytes=0x100000 -sonoff.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +sonoff.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld sonoff.menu.eesz.1M.build.spiffs_pagesize=256 sonoff.menu.eesz.1M.upload.maximum_size=1023984 sonoff.menu.eesz.1M.build.rfcal_addr=0xFC000 @@ -7256,7 +7256,7 @@ espmxdevkit.build.flash_freq=40 espmxdevkit.menu.eesz.1M64=1MB (FS:64KB OTA:~470KB) espmxdevkit.menu.eesz.1M64.build.flash_size=1M espmxdevkit.menu.eesz.1M64.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld.h +espmxdevkit.menu.eesz.1M64.build.flash_ld=eagle.flash.1m64.ld espmxdevkit.menu.eesz.1M64.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M64.upload.maximum_size=958448 espmxdevkit.menu.eesz.1M64.build.rfcal_addr=0xFC000 @@ -7266,7 +7266,7 @@ espmxdevkit.menu.eesz.1M64.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M128=1MB (FS:128KB OTA:~438KB) espmxdevkit.menu.eesz.1M128.build.flash_size=1M espmxdevkit.menu.eesz.1M128.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld.h +espmxdevkit.menu.eesz.1M128.build.flash_ld=eagle.flash.1m128.ld espmxdevkit.menu.eesz.1M128.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M128.upload.maximum_size=892912 espmxdevkit.menu.eesz.1M128.build.rfcal_addr=0xFC000 @@ -7276,7 +7276,7 @@ espmxdevkit.menu.eesz.1M128.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M144=1MB (FS:144KB OTA:~430KB) espmxdevkit.menu.eesz.1M144.build.flash_size=1M espmxdevkit.menu.eesz.1M144.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld.h +espmxdevkit.menu.eesz.1M144.build.flash_ld=eagle.flash.1m144.ld espmxdevkit.menu.eesz.1M144.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M144.upload.maximum_size=876528 espmxdevkit.menu.eesz.1M144.build.rfcal_addr=0xFC000 @@ -7286,7 +7286,7 @@ espmxdevkit.menu.eesz.1M144.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M160=1MB (FS:160KB OTA:~422KB) espmxdevkit.menu.eesz.1M160.build.flash_size=1M espmxdevkit.menu.eesz.1M160.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld.h +espmxdevkit.menu.eesz.1M160.build.flash_ld=eagle.flash.1m160.ld espmxdevkit.menu.eesz.1M160.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M160.upload.maximum_size=860144 espmxdevkit.menu.eesz.1M160.build.rfcal_addr=0xFC000 @@ -7296,7 +7296,7 @@ espmxdevkit.menu.eesz.1M160.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M192=1MB (FS:192KB OTA:~406KB) espmxdevkit.menu.eesz.1M192.build.flash_size=1M espmxdevkit.menu.eesz.1M192.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld.h +espmxdevkit.menu.eesz.1M192.build.flash_ld=eagle.flash.1m192.ld espmxdevkit.menu.eesz.1M192.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M192.upload.maximum_size=827376 espmxdevkit.menu.eesz.1M192.build.rfcal_addr=0xFC000 @@ -7306,7 +7306,7 @@ espmxdevkit.menu.eesz.1M192.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M256=1MB (FS:256KB OTA:~374KB) espmxdevkit.menu.eesz.1M256.build.flash_size=1M espmxdevkit.menu.eesz.1M256.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld.h +espmxdevkit.menu.eesz.1M256.build.flash_ld=eagle.flash.1m256.ld espmxdevkit.menu.eesz.1M256.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M256.upload.maximum_size=761840 espmxdevkit.menu.eesz.1M256.build.rfcal_addr=0xFC000 @@ -7316,7 +7316,7 @@ espmxdevkit.menu.eesz.1M256.build.spiffs_blocksize=4096 espmxdevkit.menu.eesz.1M512=1MB (FS:512KB OTA:~246KB) espmxdevkit.menu.eesz.1M512.build.flash_size=1M espmxdevkit.menu.eesz.1M512.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld.h +espmxdevkit.menu.eesz.1M512.build.flash_ld=eagle.flash.1m512.ld espmxdevkit.menu.eesz.1M512.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M512.upload.maximum_size=499696 espmxdevkit.menu.eesz.1M512.build.rfcal_addr=0xFC000 @@ -7326,7 +7326,7 @@ espmxdevkit.menu.eesz.1M512.build.spiffs_blocksize=8192 espmxdevkit.menu.eesz.1M=1MB (FS:none OTA:~502KB) espmxdevkit.menu.eesz.1M.build.flash_size=1M espmxdevkit.menu.eesz.1M.build.flash_size_bytes=0x100000 -espmxdevkit.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld.h +espmxdevkit.menu.eesz.1M.build.flash_ld=eagle.flash.1m.ld espmxdevkit.menu.eesz.1M.build.spiffs_pagesize=256 espmxdevkit.menu.eesz.1M.upload.maximum_size=1023984 espmxdevkit.menu.eesz.1M.build.rfcal_addr=0xFC000 diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 0d130ad26e..25607c765c 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -72,7 +72,7 @@ static void warning(void) } static fn_exception_handler_t old_handler = NULL; -static ICACHE_RAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) +static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) { do { /* @@ -83,20 +83,21 @@ static ICACHE_RAM_ATTR void non32xfer_exception_handler(struct __exception_frame Register a15 was used for epc1, then clobbered for rsr. Maybe an __asm("":::"memory") before starting the asm would help for these cases. For this instance moved setting epc1 closer to where it was used. + Edit. "&"" on output register would have resolved the problem. + Refactored to reduce and consolidate register usage. */ uint32_t insn; __asm( - "movi a4, ~3;" /* prepare a mask for the EPC */ - "and a4, a4, %1;" /* apply mask for 32bit aligned base */ - "l32i a5, a4, 0;" /* load part 1 */ - "l32i a6, a4, 4;" /* load part 2 */ + "movi %0, ~3;" /* prepare a mask for the EPC */ + "and %0, %0, %1;" /* apply mask for 32bit aligned base */ "ssa8l %1;" /* set up shift register for src op */ - "src %0, a6, a5;" /* right shift to get faulting instruction */ - :"=r"(insn) + "l32i %1, %0, 0;" /* load part 1 */ + "l32i %0, %0, 4;" /* load part 2 */ + "src %0, %0, %1;" /* right shift to get faulting instruction */ + :"=&r"(insn) :"r"(ef->epc) - :"a4", "a5", "a6" + : ); - /* This is a concern area - exception handlers are called with interrupts turned back on by _xtos_c_wrapper_handler. Is there something about an @@ -148,7 +149,7 @@ static ICACHE_RAM_ATTR void non32xfer_exception_handler(struct __exception_frame __asm("rsr %0, EXCVADDR;" :"=r"(excvaddr)::); /* debug option, validate address so we don't hide memory access bugs in APP */ - if ((is_read && is_icache(excvaddr)) || is_iram(excvaddr)) { + if (is_iram(excvaddr) || (is_read && is_icache(excvaddr))) { /* all is good */ } else { continue; /* fail */ @@ -201,7 +202,7 @@ static ICACHE_RAM_ATTR void non32xfer_exception_handler(struct __exception_frame Calling _xtos_unhandled_exception(ef, cause) in the Boot ROM, gets us a hardware wdt. - Use panic instead as a fall back. It will at least give us a stack trace. + Use panic instead as a fall back. It will produce a stack trace. */ panic(); } diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index e61bd546c3..ffe079e455 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -24,6 +24,10 @@ #endif #define DEBUG_MMU +#ifndef assert +#define assert(...) do{}while(false) +#endif + #ifdef __cplusplus extern "C" { #endif @@ -40,38 +44,120 @@ typedef struct MMU_CRE_STATUS { extern mmu_cre_status_t mmu_status; + #ifdef DEBUG_MMU -bool inline is_iram(uint32_t addr) { +static inline bool is_iram(uint32_t addr) { constexpr uint32_t iram_start = 0x40100000u; + #ifdef MMU_SEC_HEAP_SIZE constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; #else constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE; #endif + return (iram_start <= addr && iram_end > addr); } -bool inline is_icache(uint32_t addr) { +static inline bool is_icache(uint32_t addr) { constexpr uint32_t icache_start = 0x40200000u; constexpr uint32_t icache_end = icache_start + 0x100000; return (icache_start <= addr && icache_end > addr); } #else -bool inline is_iram(uint32_t addr) { +static inline bool is_iram(uint32_t addr) { (void)addr; return true; } -bool inline is_icache(uint32_t addr) { +static inline bool is_icache(uint32_t addr) { (void)addr; return true; } -#endif +#endif // #ifdef DEBUG_MMU + + +/* + * Some inlines to allow faster random access to non32bit access of iRAM or + * iCACHE data elements. These remove the extra time and stack space that would + * have occured by relying on exception processing. + */ +static inline uint8_t get_uint8_iram(const void *p8) { + assert((is_iram((uint32_t)p8) || is_icache((uint32_t)p8))); + uint32_t val = (*(uint32_t *)((uintptr_t)p8 & ~0x3)); + uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; + val >>= pos; + return (uint8_t)val; +} + +static inline uint16_t get_uint16_iram(const void *p16) { + assert((is_iram((uint32_t)p16) || is_icache((uint32_t)p16))); + uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); + uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; + val >>= pos; + return (uint16_t)val; +} + +static inline int16_t get_int16_iram(const void *p16) { + assert((is_iram((uint32_t)p16) || is_icache((uint32_t)p16))); + uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); + uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; + val >>= pos; + return (int16_t)val; +} + + + +static inline uint8_t set_uint8_iram(void *p8, const uint8_t val) { + assert((is_iram((uint32_t)p8))); + uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; + uint32_t sval = val << pos; + uint32_t valmask = 0x0FF << pos; + + uint32_t *p32 = (uint32_t *)((uintptr_t)p8 & ~0x3); + uint32_t ival = *p32; + ival &= (~valmask); + ival |= sval; + *p32 = ival; + return val; +} + +static inline uint16_t set_uint16_iram(void *p16, const uint16_t val) { + assert((is_iram((uint32_t)p16))); + uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; + uint32_t sval = val << pos; + uint32_t valmask = 0x0FFFF << pos; + + uint32_t *p32 = (uint32_t *)((uintptr_t)p16 & ~0x3); + uint32_t ival = *p32; + ival &= (~valmask); + ival |= sval; + *p32 = ival; + return val; +} + +static inline int16_t set_int16_iram(void *p16, const int16_t val) { + assert((is_iram((uint32_t)p16))); + uint32_t sval = (uint16_t)val; + uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; + sval <<= pos; + uint32_t valmask = 0x0FFFF << pos; + + uint32_t *p32 = (uint32_t *)((uintptr_t)p16 & ~0x3); + uint32_t ival = *p32; + ival &= (~valmask); + ival |= sval; + *p32 = ival; + return val; +} + + #if DEV_DEBUG #define DBG_MMU_PRINTF ets_uart_printf +#define ETS_FLUSH(a) while((USS(a) >> USTXC) & 0xff){} + #define DBG_MM_PRINT_STATUS() { \ DBG_MMU_PRINTF("\nmmu_status = {" \ "v_cfg = %u, state = %d, enable/disable count = %u/%u, " \ @@ -79,7 +165,7 @@ bool inline is_icache(uint32_t addr) { mmu_status.v_cfg, mmu_status.state, \ mmu_status.enable_count, mmu_status.disable_count, \ mmu_status.map, mmu_status.p, mmu_status.v); \ - ets_delay_us(12000); \ + ETS_FLUSH(0); \ } #define DBG_MMU_PRINT_IRAM_BANK_REG(a) { \ @@ -88,13 +174,15 @@ bool inline is_icache(uint32_t addr) { } #else +#define ETS_FLUSH(...) do {} while(false) #define DBG_MMU_PRINTF(...) do {} while(false) #define DBG_MM_PRINT_STATUS(...) do {} while(false) #define DBG_MMU_PRINT_IRAM_BANK_REG(...) do {} while(false) -#endif +#endif // #if DEV_DEBUG #ifdef __cplusplus } #endif + #endif diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index e8e6962c83..1fc94310af 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -1,6 +1,15 @@ #include #include +uint32_t timed_byte_read(char *pc, uint32_t * o); +uint32_t timed_byte_read2(char *pc, uint32_t * o); + +#define GET_BYTE_FN(name,wo,bo) \ +static inline char get ## name(void *o) { \ + char res; /* extract named field */ \ + asm ("l32i %0, %1, " #wo "; extui %0, %0, " #bo ", 8;" : "=r"(res) : "r"(o) : );\ + return res; } + /* Notes, When accessing IRAM as data storage all access must be word aligned and @@ -134,8 +143,43 @@ constexpr short *probe_s = (short *)0x40108000; constexpr char *probe_c = (char *)0x40110000; constexpr short *unaligned_probe_s = (short *)0x3FFF8001; +uint32_t read_var = 0x11223344; + +extern uint32_t mmu_non32xfer_count; + void processKey(Print& out, int hotKey) { switch (hotKey) { + case 't': { + uint32_t tmp; + out.printf_P(PSTR("Test how much time is added by exception handling")); + out.println(); + out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); + out.println(); + out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read((char *)0x40200003, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read((char *)0x40200003, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from iRAM %u cpu cycle count, 0x%02X."), timed_byte_read((char *)0x40108000, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from dRAM %u cpu cycle count, 0x%02X."), timed_byte_read((char *)((uintptr_t)&read_var + 1), &tmp), tmp); + out.println(); + out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); + out.println(); + out.printf_P(PSTR("Test how much time is used by the inline function method")); + out.println(); + out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)0x40200003, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)0x40200003, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from iRAM %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)0x40108000, &tmp), tmp); + out.println(); + out.printf_P(PSTR("Timed byte read from dRAM %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)((uintptr_t)&read_var + 1), &tmp), tmp); + out.println(); + out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); + out.println(); + out.println(); + break; + } case '9': out.printf_P(PSTR("Unaligned exception by reading short")); out.println(); @@ -214,6 +258,7 @@ void processKey(Print& out, int hotKey) { out.println(); out.println(F("Press a key + ")); out.println(F(" R - Restart, ESP.restart();")); + out.println(F(" t - exception vs inline method timing info.")); out.println(F(" ? - Print Help")); out.println(); out.println(F("Crash with:")); diff --git a/libraries/esp8266/examples/MMU48K/timed.cpp b/libraries/esp8266/examples/MMU48K/timed.cpp new file mode 100644 index 0000000000..aa603dc273 --- /dev/null +++ b/libraries/esp8266/examples/MMU48K/timed.cpp @@ -0,0 +1,16 @@ +#include +#include + +uint32_t IRAM_ATTR timed_byte_read(char *pc, uint32_t * o) { + uint32_t start = esp_get_cycle_count(); + *o = *pc; + // return clockCyclesToMicroseconds(esp_get_cycle_count() - start); + return (esp_get_cycle_count() - start); +} + +uint32_t IRAM_ATTR timed_byte_read2(char *pc, uint32_t * o) { + uint32_t start = esp_get_cycle_count(); + *o = get_uint8_iram(pc); + // return clockCyclesToMicroseconds(esp_get_cycle_count() - start); + return (esp_get_cycle_count() - start); +} diff --git a/platform.txt b/platform.txt index 2990343001..378774ee16 100644 --- a/platform.txt +++ b/platform.txt @@ -97,8 +97,12 @@ recipe.hooks.sketch.prebuild.pattern="{runtime.tools.python3.path}/python3" "{ru recipe.hooks.prebuild.10.pattern="{runtime.tools.python3.path}/python3" "{runtime.tools.makecorever}" --build_path "{build.path}" --platform_path "{runtime.platform.path}" --version "unix-{version}" ## Build the app.ld linker file -recipe.hooks.linking.prelink.1.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{runtime.platform.path}/tools/sdk/ld/eagle.app.v6.common.ld.h" -o "{build.path}/local.eagle.app.v6.common.ld" -recipe.hooks.linking.prelink.2.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{runtime.platform.path}/tools/sdk/ld/{build.flash_ld}" -o "{build.path}/local.eagle.flash.ld" +recipe.hooks.linking.prelink.11.pattern.windows=cmd /v:on /e:on /c "if not exist {build.path}/ld_h/ (mkdir {build.path}/ld_h/ )" +recipe.hooks.linking.prelink.12.pattern.windows=copy "{runtime.platform.path}/tools/sdk/ld/{build.flash_ld}" "{build.path}/ld_h/local.eagle.flash.ld.h" +recipe.hooks.linking.prelink.11.pattern=mkdir -p "{build.path}/ld_h/" +recipe.hooks.linking.prelink.12.pattern=cp "{runtime.platform.path}/tools/sdk/ld/{build.flash_ld}" "{build.path}/ld_h/local.eagle.flash.ld.h" +recipe.hooks.linking.prelink.13.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{build.path}/ld_h/local.eagle.flash.ld.h" -o "{build.path}/local.eagle.flash.ld" +recipe.hooks.linking.prelink.14.pattern="{compiler.path}{compiler.c.cmd}" -CC -E -P {build.vtable_flags} {build.mmuflags} "{runtime.platform.path}/tools/sdk/ld/eagle.app.v6.common.ld.h" -o "{build.path}/local.eagle.app.v6.common.ld" ## Compile c files recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} -D{build.sdk}=1 -DF_CPU={build.f_cpu} {build.lwip_flags} {build.debug_port} {build.debug_level} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" {build.led} {build.flash_flags} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" diff --git a/tools/boards.txt.py b/tools/boards.txt.py index 692e784ea3..dbda7b1a72 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1321,7 +1321,7 @@ def flash_map (flashsize_kb, fs_kb = 0): strfs = str(int(fs_kb / 1024)) + 'M' if (fs_kb >= 1024) else str(fs_kb) + 'K' strfs_strip = str(int(fs_kb / 1024)) + 'M' if (fs_kb >= 1024) else str(fs_kb) if (fs_kb > 0) else '' - ld = 'eagle.flash.' + strsize.lower() + strfs_strip.lower() + '.ld.h' + ld = 'eagle.flash.' + strsize.lower() + strfs_strip.lower() + '.ld' menu = '.menu.eesz.' + strsize + strfs_strip menub = menu + '.build.' desc = 'none' if (fs_kb == 0) else strfs + 'B' diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld.h b/tools/sdk/ld/eagle.flash.16m14m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.16m14m.ld.h rename to tools/sdk/ld/eagle.flash.16m14m.ld diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld.h b/tools/sdk/ld/eagle.flash.16m15m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.16m15m.ld.h rename to tools/sdk/ld/eagle.flash.16m15m.ld diff --git a/tools/sdk/ld/eagle.flash.1m.ld.h b/tools/sdk/ld/eagle.flash.1m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m.ld.h rename to tools/sdk/ld/eagle.flash.1m.ld diff --git a/tools/sdk/ld/eagle.flash.1m128.ld.h b/tools/sdk/ld/eagle.flash.1m128.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m128.ld.h rename to tools/sdk/ld/eagle.flash.1m128.ld diff --git a/tools/sdk/ld/eagle.flash.1m144.ld.h b/tools/sdk/ld/eagle.flash.1m144.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m144.ld.h rename to tools/sdk/ld/eagle.flash.1m144.ld diff --git a/tools/sdk/ld/eagle.flash.1m160.ld.h b/tools/sdk/ld/eagle.flash.1m160.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m160.ld.h rename to tools/sdk/ld/eagle.flash.1m160.ld diff --git a/tools/sdk/ld/eagle.flash.1m192.ld.h b/tools/sdk/ld/eagle.flash.1m192.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m192.ld.h rename to tools/sdk/ld/eagle.flash.1m192.ld diff --git a/tools/sdk/ld/eagle.flash.1m256.ld.h b/tools/sdk/ld/eagle.flash.1m256.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m256.ld.h rename to tools/sdk/ld/eagle.flash.1m256.ld diff --git a/tools/sdk/ld/eagle.flash.1m512.ld.h b/tools/sdk/ld/eagle.flash.1m512.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m512.ld.h rename to tools/sdk/ld/eagle.flash.1m512.ld diff --git a/tools/sdk/ld/eagle.flash.1m64.ld.h b/tools/sdk/ld/eagle.flash.1m64.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.1m64.ld.h rename to tools/sdk/ld/eagle.flash.1m64.ld diff --git a/tools/sdk/ld/eagle.flash.2m.ld.h b/tools/sdk/ld/eagle.flash.2m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m.ld.h rename to tools/sdk/ld/eagle.flash.2m.ld diff --git a/tools/sdk/ld/eagle.flash.2m128.ld.h b/tools/sdk/ld/eagle.flash.2m128.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m128.ld.h rename to tools/sdk/ld/eagle.flash.2m128.ld diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld.h b/tools/sdk/ld/eagle.flash.2m1m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m1m.ld.h rename to tools/sdk/ld/eagle.flash.2m1m.ld diff --git a/tools/sdk/ld/eagle.flash.2m256.ld.h b/tools/sdk/ld/eagle.flash.2m256.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m256.ld.h rename to tools/sdk/ld/eagle.flash.2m256.ld diff --git a/tools/sdk/ld/eagle.flash.2m512.ld.h b/tools/sdk/ld/eagle.flash.2m512.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m512.ld.h rename to tools/sdk/ld/eagle.flash.2m512.ld diff --git a/tools/sdk/ld/eagle.flash.2m64.ld.h b/tools/sdk/ld/eagle.flash.2m64.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.2m64.ld.h rename to tools/sdk/ld/eagle.flash.2m64.ld diff --git a/tools/sdk/ld/eagle.flash.4m.ld.h b/tools/sdk/ld/eagle.flash.4m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.4m.ld.h rename to tools/sdk/ld/eagle.flash.4m.ld diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld.h b/tools/sdk/ld/eagle.flash.4m1m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.4m1m.ld.h rename to tools/sdk/ld/eagle.flash.4m1m.ld diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld.h b/tools/sdk/ld/eagle.flash.4m2m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.4m2m.ld.h rename to tools/sdk/ld/eagle.flash.4m2m.ld diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld.h b/tools/sdk/ld/eagle.flash.4m3m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.4m3m.ld.h rename to tools/sdk/ld/eagle.flash.4m3m.ld diff --git a/tools/sdk/ld/eagle.flash.512k.ld.h b/tools/sdk/ld/eagle.flash.512k.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.512k.ld.h rename to tools/sdk/ld/eagle.flash.512k.ld diff --git a/tools/sdk/ld/eagle.flash.512k128.ld.h b/tools/sdk/ld/eagle.flash.512k128.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.512k128.ld.h rename to tools/sdk/ld/eagle.flash.512k128.ld diff --git a/tools/sdk/ld/eagle.flash.512k32.ld.h b/tools/sdk/ld/eagle.flash.512k32.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.512k32.ld.h rename to tools/sdk/ld/eagle.flash.512k32.ld diff --git a/tools/sdk/ld/eagle.flash.512k64.ld.h b/tools/sdk/ld/eagle.flash.512k64.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.512k64.ld.h rename to tools/sdk/ld/eagle.flash.512k64.ld diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld.h b/tools/sdk/ld/eagle.flash.8m6m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.8m6m.ld.h rename to tools/sdk/ld/eagle.flash.8m6m.ld diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld.h b/tools/sdk/ld/eagle.flash.8m7m.ld similarity index 100% rename from tools/sdk/ld/eagle.flash.8m7m.ld.h rename to tools/sdk/ld/eagle.flash.8m7m.ld From b443e4301b917a37465160f1019112d6ed89b88a Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 27 Feb 2020 16:11:30 -0800 Subject: [PATCH 06/48] Interesting glitch in boards.txt after github merge. A new board in master was missing new additions added by boards.txt.py in the PR. Which the CI flags when it rebuilds boards.txt. --- boards.txt | 10 ++++++++++ cores/esp8266/mmu_iram.h | 6 +++++- package/package_esp8266com_index.template.json | 2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/boards.txt b/boards.txt index df0e40ead9..ee6c347cdf 100644 --- a/boards.txt +++ b/boards.txt @@ -6985,6 +6985,16 @@ eduinowifi.menu.ssl.all=All SSL ciphers (most compatible) eduinowifi.menu.ssl.all.build.sslflags= eduinowifi.menu.ssl.basic=Basic SSL ciphers (lower ROM use) eduinowifi.menu.ssl.basic.build.sslflags=-DBEARSSL_SSL_BASIC +eduinowifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) +eduinowifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 +eduinowifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) +eduinowifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +eduinowifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +eduinowifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 +eduinowifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM +eduinowifi.menu.non32xfer.fast.build.non32xferflags= +eduinowifi.menu.non32xfer.safe=Byte/Word access to IRAM/PROGMEM (very slow) +eduinowifi.menu.non32xfer.safe.build.non32xferflags=-DNON32XFER_HANDLER eduinowifi.upload.resetmethod=--before default_reset --after hard_reset eduinowifi.build.flash_mode=dio eduinowifi.build.flash_flags=-DFLASHMODE_DIO diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index ffe079e455..452313edf6 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -47,7 +47,11 @@ extern mmu_cre_status_t mmu_status; #ifdef DEBUG_MMU static inline bool is_iram(uint32_t addr) { - constexpr uint32_t iram_start = 0x40100000u; +constexpr uint32_t iram_start = 0x40100000u; + +#ifndef MMU_IRAM_SIZE +#define MMU_IRAM_SIZE 0x8000 +#endif #ifdef MMU_SEC_HEAP_SIZE constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; diff --git a/package/package_esp8266com_index.template.json b/package/package_esp8266com_index.template.json index 86a9570bf0..97a05e2bbe 100644 --- a/package/package_esp8266com_index.template.json +++ b/package/package_esp8266com_index.template.json @@ -378,4 +378,4 @@ ] } ] -} +} \ No newline at end of file From 0c661db4afc2fa4a2e32dd70aa8acf40a29b2bed Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 2 Mar 2020 11:07:40 -0800 Subject: [PATCH 07/48] Support for 2nd Heap, excess IRAM, through umm_malloc. Adapted changes to umm_malloc, Esp.cpp, StackThunk.cpp, WiFiClientSecureBearSSL.cpp, and virtualmem.ino to irammem.ino from @earlephilhower PR #6994. Reworked umm_malloc to use context pointers instead of copy context. umm_malloc now supports allocations from IRAM. Added class HeapSelectIram, ... to aid in selecting alternate heaps, modeled after class InterruptLock. Restrict alloc request from ISRs to DRAM. Never ending improvements to debug printing. Sec Heap option now pulls in free IRAM left over in the 1st 32K block. Managed through umm_malloc with HeapSelectIram. Updated examples. --- cores/esp8266/Esp.cpp | 46 +++ cores/esp8266/Esp.h | 11 + cores/esp8266/StackThunk.cpp | 4 + cores/esp8266/core_esp8266_main.cpp | 15 +- cores/esp8266/core_esp8266_non32xfer.cpp | 65 ++-- cores/esp8266/esp8266_undocumented.h | 2 +- cores/esp8266/mmu_iram.cpp | 81 +++- cores/esp8266/mmu_iram.h | 166 ++++++--- cores/esp8266/umm_malloc/umm_info.c | 12 +- cores/esp8266/umm_malloc/umm_integrity.c | 7 +- cores/esp8266/umm_malloc/umm_local.c | 107 +++++- cores/esp8266/umm_malloc/umm_local.h | 17 +- cores/esp8266/umm_malloc/umm_malloc.cpp | 345 +++++++++++++++--- cores/esp8266/umm_malloc/umm_malloc.h | 87 +++++ cores/esp8266/umm_malloc/umm_malloc_cfg.h | 142 +++---- cores/esp8266/umm_malloc/umm_poison.c | 12 +- .../HelloServerBearSSL/HelloServerBearSSL.ino | 62 ++++ .../src/WiFiClientSecureBearSSL.cpp | 58 ++- libraries/esp8266/examples/MMU48K/MMU48K.ino | 60 ++- .../esp8266/examples/irammem/irammem.ino | 260 +++++++++++++ libraries/esp8266/keywords.txt | 5 + tests/host/common/MockEsp.cpp | 12 + 22 files changed, 1300 insertions(+), 276 deletions(-) create mode 100644 libraries/esp8266/examples/irammem/irammem.ino diff --git a/cores/esp8266/Esp.cpp b/cores/esp8266/Esp.cpp index a0e525f2bb..92c305f620 100644 --- a/cores/esp8266/Esp.cpp +++ b/cores/esp8266/Esp.cpp @@ -27,6 +27,8 @@ #include "umm_malloc/umm_malloc.h" #include "cont.h" #include "coredecls.h" +#include "umm_malloc/umm_malloc.h" +// #include "core_esp8266_vm.h" extern "C" { #include "user_interface.h" @@ -698,3 +700,47 @@ String EspClass::getSketchMD5() result = md5.toString(); return result; } + +void EspClass::enableVM() +{ +#ifdef UMM_HEAP_EXTERNAL + if (!vmEnabled) + install_vm_exception_handler(); + vmEnabled = true; +#endif +} + +void EspClass::setExternalHeap() +{ +#ifdef UMM_HEAP_EXTERNAL + if (vmEnabled) + umm_push_heap(UMM_HEAP_EXTERNAL); +#endif +} + +void EspClass::setIramHeap() +{ +#ifdef UMM_HEAP_IRAM + umm_push_heap(UMM_HEAP_IRAM); +#endif +} + +void EspClass::setDramHeap() +{ +#if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM) + if (vmEnabled) + umm_push_heap(UMM_HEAP_DRAM); +#elif defined(UMM_HEAP_IRAM) + umm_push_heap(UMM_HEAP_DRAM); +#endif +} + +void EspClass::resetHeap() +{ +#if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM) + if (vmEnabled) + umm_pop_heap(); +#elif defined(UMM_HEAP_IRAM) + umm_pop_heap(); +#endif +} diff --git a/cores/esp8266/Esp.h b/cores/esp8266/Esp.h index f4529c839a..f42f3c9f36 100644 --- a/cores/esp8266/Esp.h +++ b/cores/esp8266/Esp.h @@ -198,6 +198,17 @@ class EspClass { #else uint32_t getCycleCount(); #endif + + void enableVM(); + void setDramHeap(); + void setIramHeap(); + void setExternalHeap(); + void setInternalHeap() {setDramHeap();}; // depricated + void resetHeap(); +private: +#ifdef UMM_HEAP_EXTERNAL + bool vmEnabled = false; +#endif }; #ifndef CORE_MOCK diff --git a/cores/esp8266/StackThunk.cpp b/cores/esp8266/StackThunk.cpp index 541cd440ff..07e683ab91 100644 --- a/cores/esp8266/StackThunk.cpp +++ b/cores/esp8266/StackThunk.cpp @@ -28,6 +28,7 @@ #include #include "StackThunk.h" #include +#include extern "C" { @@ -45,7 +46,10 @@ void stack_thunk_add_ref() { stack_thunk_refcnt++; if (stack_thunk_refcnt == 1) { + ETS_PRINTF("\nStackThunk malloc(%u)\n", _stackSize * sizeof(uint32_t)); + HeapSelectDram ephemeral; stack_thunk_ptr = (uint32_t *)malloc(_stackSize * sizeof(uint32_t)); + ETS_PRINTF("StackThunk stack_thunk_ptr: %p\n", stack_thunk_ptr); stack_thunk_top = stack_thunk_ptr + _stackSize - 1; stack_thunk_save = NULL; stack_thunk_repaint(); diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 4d8ad32b86..0d6c55aebb 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -34,6 +34,7 @@ extern "C" { } #include #include "gdb_hooks.h" +#include #include @@ -298,18 +299,20 @@ extern "C" void app_entry_redefinable(void) cont_t s_cont __attribute__((aligned(16))); g_pcont = &s_cont; - DBG_MM_PRINT_STATUS(); + DBG_MMU_PRINT_STATUS(); - DBG_MMU_PRINT_IRAM_BANK_REG(0); + DBG_MMU_PRINT_IRAM_BANK_REG(0, ""); + + DBG_MMU_PRINTF("\nCall call_user_start()\n"); /* Call the entry point of the SDK code. */ call_user_start(); } - static void app_entry_custom (void) __attribute__((weakref("app_entry_redefinable"))); extern "C" void app_entry (void) { + umm_init(); return app_entry_custom(); } @@ -331,10 +334,12 @@ extern "C" void user_init(void) { cont_init(g_pcont); -#ifdef NON32XFER_HANDLER +#if defined(NON32XFER_HANDLER) || defined(MMU_SEC_HEAP) install_non32xfer_exception_handler(); #endif - +#if defined(MMU_SEC_HEAP) + umm_init_iram(); +#endif preinit(); // Prior to C++ Dynamic Init (not related to above init() ). Meant to be user redefinable. ets_task(loop_task, diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 25607c765c..7fec1e4f4c 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -38,24 +38,6 @@ extern "C" { -#if 1 -#define ETS_PRINTF ets_uart_printf -#else -#define ETS_PRINTF(...) do {} while(false) -#endif - -#ifndef __MMU_IRAM_H -bool inline is_iram(uint32_t addr) { - (void)addr; - return true; -} - -bool inline is_icache(uint32_t addr) { - (void)addr; - return true; -} -#endif - #define LOAD_MASK 0x00f00fu #define L8UI_MATCH 0x000002u #define L16UI_MATCH 0x001002u @@ -66,10 +48,16 @@ bool inline is_icache(uint32_t addr) { #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Non 32-bit read/write error */ uint32_t mmu_non32xfer_count = 0; +uint32_t mmu_non32xfer_withinisr_count = 0; + +#define DEBUG_WARNING +#ifdef DEBUG_WARNING static void warning(void) { - DEBUGV("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); + ETS_PRINTF("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); } +#endif + static fn_exception_handler_t old_handler = NULL; static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) @@ -88,12 +76,13 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, */ uint32_t insn; __asm( - "movi %0, ~3;" /* prepare a mask for the EPC */ - "and %0, %0, %1;" /* apply mask for 32bit aligned base */ - "ssa8l %1;" /* set up shift register for src op */ - "l32i %1, %0, 0;" /* load part 1 */ - "l32i %0, %0, 4;" /* load part 2 */ - "src %0, %0, %1;" /* right shift to get faulting instruction */ + "rsil %0, 15\n\t" /* Turn IRQs back off, let exit wrapper restore PS */ + "movi %0, ~3\n\t" /* prepare a mask for the EPC */ + "and %0, %0, %1\n\t" /* apply mask for 32bit aligned base */ + "ssa8l %1\n\t" /* set up shift register for src op */ + "l32i %1, %0, 0\n\t" /* load part 1 */ + "l32i %0, %0, 4\n\t" /* load part 2 */ + "src %0, %0, %1\n\t" /* right shift to get faulting instruction */ :"=&r"(insn) :"r"(ef->epc) : @@ -105,10 +94,15 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, an exception handler? */ if (ef->ps & 0x0F) { - ETS_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); -#if 0 - continue; /* fail, not safe for IRQ disabled ?? */ -#endif + if (0 == mmu_non32xfer_withinisr_count) { + ETS_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); + #if 0 + continue; /* fail, not safe for IRQ disabled ?? */ + #endif + } + if (0 == ++mmu_non32xfer_withinisr_count) { + --mmu_non32xfer_withinisr_count; // saturated + } } uint32_t what = insn & LOAD_MASK; @@ -129,9 +123,13 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, continue; /* fail */ } +#ifdef DEBUG_WARNING if (0 == mmu_non32xfer_count) { + // This may be causing some issues TODO retest with umm_malloc within + // interrupt context. schedule_function(warning); } +#endif // Some accounting information so we know this is happending. if (0 == ++mmu_non32xfer_count) { --mmu_non32xfer_count; // saturated @@ -208,10 +206,13 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, } -void install_non32xfer_exception_handler(void) +void IRAM_ATTR install_non32xfer_exception_handler(void) { - old_handler = - _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, non32xfer_exception_handler); + if (NULL == old_handler) { + old_handler = + _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, + non32xfer_exception_handler); + } } }; diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index f56c8d4711..031d2d38fe 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -81,7 +81,7 @@ struct __exception_frame typedef void (*fn_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); extern fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); -//D extern void _xtos_unhandled_exception(struct __exception_frame *ef, uint32_t cause); +extern void _xtos_unhandled_exception(struct __exception_frame *ef, uint32_t cause); #ifdef __cplusplus }; diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 5b3d29470c..800b022c06 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -17,6 +17,7 @@ #include "Arduino.h" #include "mmu_iram.h" +#include extern "C" { @@ -110,12 +111,12 @@ void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { if (0 == mmu_status.enable_count) { mmu_status.enable_count--; // keep saturated value } - DBG_MMU_PRINT_IRAM_BANK_REG("before"); + DBG_MMU_PRINT_IRAM_BANK_REG("before", "Enable"); real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); - DBG_MMU_PRINT_IRAM_BANK_REG("after"); - DBG_MM_PRINT_STATUS(); + DBG_MMU_PRINT_IRAM_BANK_REG("after", "Enable"); + DBG_MMU_PRINT_STATUS(); } #ifndef ROM_Cache_Read_Disable @@ -129,20 +130,86 @@ constexpr fp_Cache_Read_Disable_t real_Cache_Read_Disable = * */ void IRAM_ATTR Cache_Read_Disable(void) { - mmu_status.disable_count++; mmu_status.state = 0; if (0 == mmu_status.disable_count) { mmu_status.disable_count--; // keep saturated value } - DBG_MMU_PRINT_IRAM_BANK_REG("before"); + DBG_MMU_PRINT_IRAM_BANK_REG("before", "Disable"); real_Cache_Read_Disable(); - DBG_MMU_PRINT_IRAM_BANK_REG("after"); - DBG_MM_PRINT_STATUS(); + DBG_MMU_PRINT_IRAM_BANK_REG("after", "Disable"); + DBG_MMU_PRINT_STATUS(); +} + +#ifdef DEV_DEBUG_PRINT +/* + * Early adjustment for CPU crystal frequency, so debug printing will work. + * This should not be left enabled all the time in Crash_Read..., I am concerned + * that there may be unknown interference with the NONOS SDK startup. + * + * Inspired by: + * https://github.com/pvvx/esp8266web/blob/2e25559bc489487747205db2ef171d48326b32d4/app/sdklib/system/app_main.c#L581-L591 + */ +extern "C" uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); +extern "C" void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); + +extern "C" void IRAM_ATTR set_pll(void) +{ +#if !defined(F_CRYSTAL) +#define F_CRYSTAL 26000000 +#endif + if (F_CRYSTAL != 40000000) { + // At Boot ROM(-BIOS) start, it assumes a 40MHz crystal. + // If it is not, we assume a 26MHz crystal. + // There is no support for 24MHz crustal at this time. + if(rom_i2c_readReg(103,4,1) != 136) { // 8: 40MHz, 136: 26MHz + // Assume 26MHz crystal + // soc_param0: 0: 40MHz, 1: 26MHz, 2: 24MHz + // set 80MHz PLL CPU + rom_i2c_writeReg(103,4,1,136); + rom_i2c_writeReg(103,4,2,145); + } + } } +extern "C" void IRAM_ATTR dbg_set_pll(void) +{ + char r103_4_1 = rom_i2c_readReg(103,4,1); + char r103_4_2 = rom_i2c_readReg(103,4,2); + set_pll(); + ets_uart_printf("\nrom_i2c_readReg(103,4,1) == %u\n", r103_4_1); + ets_uart_printf( "rom_i2c_readReg(103,4,2) == %u\n", r103_4_2); +} + +/* + This helps keep the UART enabled at user_init() so we can get a few more + messages printed. +*/ +extern struct rst_info resetInfo; +extern "C" void __pinMode( uint8_t pin, uint8_t mode ); + +inline bool is_gpio_persistent(void) { + return REASON_EXCEPTION_RST <= resetInfo.reason && + REASON_SOFT_RESTART >= resetInfo.reason; +} + +extern "C" void pinMode( uint8_t pin, uint8_t mode ) { + static bool in_initPins = true; + if (in_initPins && (1 == pin)) { + if (!is_gpio_persistent()) { + /* Restore pin to TX after Power-on and EXT_RST */ + __pinMode(pin, FUNCTION_0); + } + in_initPins = false; + return; + } + + __pinMode( pin, mode ); +} +#endif + #endif }; diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 452313edf6..e1ca6340ee 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -19,15 +19,78 @@ #include #include +#include + +/* + * DEV_DEBUG_MMU_IRAM: + * Debug printing for developing mmu_iram. I don't think it would be usful for + * general debugging. + * + * DEV_DEBUG_PRINT: + * Debug printing macros for printing before before, during, and after + * NONOS SDK initializes. May or maynot be safe during NONOS SDK + * initialization. As in printing from functions called on by the SDK + * during the SDK initialization. + * + #define DEV_DEBUG_MMU_IRAM + #define DEV_DEBUG_PRINT + */ #ifdef DEBUG_ESP_CORE -#endif #define DEBUG_MMU +#endif + -#ifndef assert -#define assert(...) do{}while(false) + +#if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_MMU) +#include + +#if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) +extern "C" void set_pll(void); +extern "C" void dbg_set_pll(void); +#define SET_PLL() set_pll() + +#else +#define SET_PLL() do {} while(false) #endif +#define ETS_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {} + +#define ETS_PRINTF(fmt, ...) \ + SET_PLL(); \ + uart_buff_switch(0); \ + ets_uart_printf(fmt, ##__VA_ARGS__); \ + ETS_FLUSH(0) + +#else // ! DEV_DEBUG_PRINT +#define ETS_FLUSH(...) do {} while(false) +#define ETS_PRINTF(...) do {} while(false) +#endif // DEV_DEBUG_PRINT + +#define DBG_MMU_PRINTF ETS_PRINTF + +#ifdef DEV_DEBUG_MMU_IRAM +#define DBG_MMU_PRINT_STATUS() { \ + DBG_MMU_PRINTF("\nmmu_status = {" \ + "v_cfg = %u, state = %d, enable/disable count = %u/%u, " \ + "map = 0x%02X, p = 0x%02X, v = 0x%02X}\n", \ + mmu_status.v_cfg, mmu_status.state, \ + mmu_status.enable_count, mmu_status.disable_count, \ + mmu_status.map, mmu_status.p, mmu_status.v); \ + ETS_FLUSH(0); \ +} + +#define DBG_MMU_PRINT_IRAM_BANK_REG(a, b) { \ + uint32_t iram_bank_reg = ESP8266_DREG(0x24); \ + DBG_MMU_PRINTF("\niram_bank_reg %s%s 0x%08X\n", (0 == a) ? "" : a, (0 == a) ? "" : " Cache_Read_" b, iram_bank_reg); \ +} + +#else // ! DEV_DEBUG_MMU_IRAM +#define DBG_MMU_PRINT_STATUS(...) do {} while(false) +#define DBG_MMU_PRINT_IRAM_BANK_REG(...) do {} while(false) +#endif // #if DEV_DEBUG_MMU_IRAM + + #ifdef __cplusplus extern "C" { #endif @@ -46,26 +109,35 @@ extern mmu_cre_status_t mmu_status; #ifdef DEBUG_MMU + static inline bool is_iram(uint32_t addr) { -constexpr uint32_t iram_start = 0x40100000u; +constexpr uint32_t _start = 0x40100000UL; +#define IRAM_START 0x40100000UL #ifndef MMU_IRAM_SIZE #define MMU_IRAM_SIZE 0x8000 #endif #ifdef MMU_SEC_HEAP_SIZE - constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; + constexpr uint32_t _end = _start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; + #define IRAM_END (IRAM_START + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE) #else - constexpr uint32_t iram_end = iram_start + MMU_IRAM_SIZE; + constexpr uint32_t _end = _start + MMU_IRAM_SIZE; #endif - return (iram_start <= addr && iram_end > addr); + return (_start <= addr && _end > addr); +} + +static inline bool is_dram(uint32_t addr) { + constexpr uint32_t _start = 0x3FF80000UL; + constexpr uint32_t _end = 0x40000000; + return (_start <= addr && _end > addr); } static inline bool is_icache(uint32_t addr) { - constexpr uint32_t icache_start = 0x40200000u; - constexpr uint32_t icache_end = icache_start + 0x100000; - return (icache_start <= addr && icache_end > addr); + constexpr uint32_t _start = 0x40200000UL; + constexpr uint32_t _end = _start + 0x100000; + return (_start <= addr && _end > addr); } #else @@ -74,12 +146,36 @@ static inline bool is_iram(uint32_t addr) { return true; } +static inline bool is_dram(uint32_t addr) { + (void)addr; + return true; +} + static inline bool is_icache(uint32_t addr) { (void)addr; return true; } #endif // #ifdef DEBUG_MMU +#ifdef DEBUG_MMU +#define ASSERT_RANGE_TEST_WRITE(a) \ + if (is_iram((uint32_t)a) || is_dram((uint32_t)a)) { \ + } else { \ + DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ + assert(("Outside of Range Write", false)); \ + } + +#define ASSERT_RANGE_TEST_READ(a) \ + if (is_iram((uint32_t)a) || is_icache((uint32_t)a) || is_dram((uint32_t)a)) { \ + } else { \ + DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ + assert(("Outside of Range Read", false)); \ + } + +#else +#define ASSERT_RANGE_TEST_WRITE(a) do {} while(false) +#define ASSERT_RANGE_TEST_READ(a) do {} while(false) +#endif /* * Some inlines to allow faster random access to non32bit access of iRAM or @@ -87,23 +183,23 @@ static inline bool is_icache(uint32_t addr) { * have occured by relying on exception processing. */ static inline uint8_t get_uint8_iram(const void *p8) { - assert((is_iram((uint32_t)p8) || is_icache((uint32_t)p8))); + ASSERT_RANGE_TEST_READ(p8); uint32_t val = (*(uint32_t *)((uintptr_t)p8 & ~0x3)); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; val >>= pos; return (uint8_t)val; } -static inline uint16_t get_uint16_iram(const void *p16) { - assert((is_iram((uint32_t)p16) || is_icache((uint32_t)p16))); +static inline uint16_t get_uint16_iram(const unsigned short *p16) { + ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; val >>= pos; return (uint16_t)val; } -static inline int16_t get_int16_iram(const void *p16) { - assert((is_iram((uint32_t)p16) || is_icache((uint32_t)p16))); +static inline int16_t get_int16_iram(const short *p16) { + ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; val >>= pos; @@ -113,7 +209,7 @@ static inline int16_t get_int16_iram(const void *p16) { static inline uint8_t set_uint8_iram(void *p8, const uint8_t val) { - assert((is_iram((uint32_t)p8))); + ASSERT_RANGE_TEST_WRITE(p8); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; uint32_t sval = val << pos; uint32_t valmask = 0x0FF << pos; @@ -126,8 +222,8 @@ static inline uint8_t set_uint8_iram(void *p8, const uint8_t val) { return val; } -static inline uint16_t set_uint16_iram(void *p16, const uint16_t val) { - assert((is_iram((uint32_t)p16))); +static inline uint16_t set_uint16_iram(unsigned short *p16, const uint16_t val) { + ASSERT_RANGE_TEST_WRITE(p16); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; uint32_t sval = val << pos; uint32_t valmask = 0x0FFFF << pos; @@ -140,8 +236,8 @@ static inline uint16_t set_uint16_iram(void *p16, const uint16_t val) { return val; } -static inline int16_t set_int16_iram(void *p16, const int16_t val) { - assert((is_iram((uint32_t)p16))); +static inline int16_t set_int16_iram(short *p16, const int16_t val) { + ASSERT_RANGE_TEST_WRITE(p16); uint32_t sval = (uint16_t)val; uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; sval <<= pos; @@ -155,36 +251,6 @@ static inline int16_t set_int16_iram(void *p16, const int16_t val) { return val; } - - -#if DEV_DEBUG -#define DBG_MMU_PRINTF ets_uart_printf - -#define ETS_FLUSH(a) while((USS(a) >> USTXC) & 0xff){} - -#define DBG_MM_PRINT_STATUS() { \ - DBG_MMU_PRINTF("\nmmu_status = {" \ - "v_cfg = %u, state = %d, enable/disable count = %u/%u, " \ - "map = 0x%02X, p = 0x%02X, v = 0x%02X}\n", \ - mmu_status.v_cfg, mmu_status.state, \ - mmu_status.enable_count, mmu_status.disable_count, \ - mmu_status.map, mmu_status.p, mmu_status.v); \ - ETS_FLUSH(0); \ -} - -#define DBG_MMU_PRINT_IRAM_BANK_REG(a) { \ - uint32_t iram_bank_reg = ESP8266_DREG(0x24); \ - DBG_MMU_PRINTF("\niram_bank_reg %s%s0x%08X\n", (0 == a) ? "" : a, (0 == a) ? "" : " Cache_Read_Enable ", iram_bank_reg); \ -} - -#else -#define ETS_FLUSH(...) do {} while(false) -#define DBG_MMU_PRINTF(...) do {} while(false) -#define DBG_MM_PRINT_STATUS(...) do {} while(false) -#define DBG_MMU_PRINT_IRAM_BANK_REG(...) do {} while(false) -#endif // #if DEV_DEBUG - - #ifdef __cplusplus } #endif diff --git a/cores/esp8266/umm_malloc/umm_info.c b/cores/esp8266/umm_malloc/umm_info.c index 96a0f89bee..8aca3d49e2 100644 --- a/cores/esp8266/umm_malloc/umm_info.c +++ b/cores/esp8266/umm_malloc/umm_info.c @@ -24,13 +24,13 @@ void *umm_info( void *ptr, int force ) { unsigned short int blockNo = 0; - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; /* Protect the critical section... */ UMM_CRITICAL_ENTRY(id_info); + umm_heap_context_t *_context = umm_get_current_heap(); + /* * Clear out all of the entries in the ummHeapInfo structure before doing * any calculations.. @@ -148,16 +148,16 @@ void *umm_info( void *ptr, int force ) { DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); #if defined(UMM_STATS) || defined(UMM_STATS_FULL) - if (ummHeapInfo.freeBlocks == ummStats.free_blocks) { + if (ummHeapInfo.freeBlocks == _context->stats.free_blocks) { DBGLOG_FORCE( force, "heap info Free blocks and heap statistics Free blocks match.\n"); } else { DBGLOG_FORCE( force, "\nheap info Free blocks %5d != heap statistics Free Blocks %5d\n\n", ummHeapInfo.freeBlocks, - ummStats.free_blocks ); + _context->stats.free_blocks ); } DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); - print_stats(force); + umm_print_stats(force); #endif /* Release the critical section... */ diff --git a/cores/esp8266/umm_malloc/umm_integrity.c b/cores/esp8266/umm_malloc/umm_integrity.c index ff3cb24a1a..2f3a2e1981 100644 --- a/cores/esp8266/umm_malloc/umm_integrity.c +++ b/cores/esp8266/umm_malloc/umm_integrity.c @@ -29,13 +29,14 @@ int umm_integrity_check(void) { unsigned short int prev; unsigned short int cur; - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; /* Iterate through all free blocks */ prev = 0; UMM_CRITICAL_ENTRY(id_integrity); + + umm_heap_context_t *_context = umm_get_current_heap(); + while(1) { cur = UMM_NFREE(prev); diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index 1b20bcf7d7..b20b30779a 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -42,7 +42,7 @@ bool ICACHE_FLASH_ATTR get_umm_get_perf_data(UMM_TIME_STATS *p, size_t size) #if defined(UMM_POISON_CHECK_LITE) // We skip this when doing the full poison check. -static int check_poison_neighbors( unsigned short cur ) { +static int check_poison_neighbors(umm_heap_context_t *_context, unsigned short cur ) { unsigned short int c; if ( 0 == cur ) @@ -96,12 +96,16 @@ static void *get_unpoisoned_check_neighbors( void *v_ptr, const char* file, int UMM_CRITICAL_DECL(id_poison); unsigned short int c; bool poison = false; - + umm_heap_context_t *_context = umm_get_ptr_context( v_ptr ); + if (NULL == _context) { + panic(); + return NULL; + } /* Figure out which block we're in. Note the use of truncated division... */ - c = (((char *)ptr)-(char *)(&(umm_heap[0])))/sizeof(umm_block); + c = (((char *)ptr)-(char *)(&(_context->heap[0])))/sizeof(umm_block); UMM_CRITICAL_ENTRY(id_poison); - poison = check_poison_block(&UMM_BLOCK(c)) && check_poison_neighbors(c); + poison = check_poison_block(&UMM_BLOCK(c)) && check_poison_neighbors(_context, c); UMM_CRITICAL_EXIT(id_poison); if (!poison) { @@ -158,15 +162,14 @@ size_t umm_block_size( void ) { #endif #if defined(UMM_STATS) || defined(UMM_STATS_FULL) -UMM_STATISTICS ummStats; +// UMM_STATISTICS ummStats; // Keep complete call path in IRAM size_t umm_free_heap_size_lw( void ) { - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; - return (size_t)ummStats.free_blocks * sizeof(umm_block); + umm_heap_context_t *_context = umm_get_current_heap(); + return (size_t)_context->stats.free_blocks * sizeof(umm_block) - umm_block_size() - umm_block_size()/2; } #endif @@ -183,14 +186,17 @@ size_t xPortGetFreeHeapSize(void) __attribute__ ((alias("umm_free_heap_size"))); #endif #if defined(UMM_STATS) || defined(UMM_STATS_FULL) -void print_stats(int force) { +void umm_print_stats(int force) { + umm_heap_context_t *_context = umm_get_current_heap(); + DBGLOG_FORCE( force, "umm heap statistics:\n"); - DBGLOG_FORCE( force, " Free Space %5u\n", ummStats.free_blocks * sizeof(umm_block)); - DBGLOG_FORCE( force, " OOM Count %5u\n", ummStats.oom_count); + DBGLOG_FORCE( force, " Heap ID %5u\n", _context->id); + DBGLOG_FORCE( force, " Free Space %5u\n", _context->stats.free_blocks * sizeof(umm_block)); + DBGLOG_FORCE( force, " OOM Count %5u\n", _context->stats.oom_count); #if defined(UMM_STATS_FULL) - DBGLOG_FORCE( force, " Low Watermark %5u\n", ummStats.free_blocks_min * sizeof(umm_block)); - DBGLOG_FORCE( force, " Low Watermark ISR %5u\n", ummStats.free_blocks_isr_min * sizeof(umm_block)); - DBGLOG_FORCE( force, " MAX Alloc Request %5u\n", ummStats.alloc_max_size); + DBGLOG_FORCE( force, " Low Watermark %5u\n", _context->stats.free_blocks_min * sizeof(umm_block)); + DBGLOG_FORCE( force, " Low Watermark ISR %5u\n", _context->stats.free_blocks_isr_min * sizeof(umm_block)); + DBGLOG_FORCE( force, " MAX Alloc Request %5u\n", _context->stats.alloc_max_size); #endif DBGLOG_FORCE( force, " Size of umm_block %5u\n", sizeof(umm_block)); DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); @@ -214,4 +220,75 @@ int ICACHE_FLASH_ATTR umm_info_safe_printf_P(const char *fmt, ...) { return result; } +#if defined(UMM_STATS) +size_t ICACHE_FLASH_ATTR umm_get_oom_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.oom_count; +} +#endif + +#ifdef UMM_STATS_FULL + +size_t ICACHE_FLASH_ATTR umm_free_heap_size_lw_min( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return (size_t)_context->stats.free_blocks_min * umm_block_size() - umm_block_size() - umm_block_size()/2; +} + +size_t ICACHE_FLASH_ATTR umm_free_heap_size_min_reset( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + _context->stats.free_blocks_min = _context->stats.free_blocks; + return (size_t)_context->stats.free_blocks_min * umm_block_size(); +} + +size_t ICACHE_FLASH_ATTR umm_free_heap_size_min( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.free_blocks_min * umm_block_size() - umm_block_size() - umm_block_size()/2; +} + +size_t ICACHE_FLASH_ATTR umm_free_heap_size_isr_min( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.free_blocks_isr_min * umm_block_size() - umm_block_size() - umm_block_size()/2; +} + +size_t ICACHE_FLASH_ATTR umm_get_max_alloc_size( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.alloc_max_size; +} + +size_t ICACHE_FLASH_ATTR umm_get_last_alloc_size( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.last_alloc_size; +} + +size_t ICACHE_FLASH_ATTR umm_get_malloc_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_malloc_count; +} + +size_t ICACHE_FLASH_ATTR umm_get_malloc_zero_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_malloc_zero_count; +} + +size_t ICACHE_FLASH_ATTR umm_get_realloc_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_realloc_count; +} + +size_t ICACHE_FLASH_ATTR umm_get_realloc_zero_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_realloc_zero_count; +} + +size_t ICACHE_FLASH_ATTR umm_get_free_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_free_count; +} + +size_t ICACHE_FLASH_ATTR umm_get_free_null_count( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->stats.id_free_null_count; +} +#endif // UMM_STATS_FULL + #endif // BUILD_UMM_MALLOC_C diff --git a/cores/esp8266/umm_malloc/umm_local.h b/cores/esp8266/umm_malloc/umm_local.h index c2f05a57dc..9a51063145 100644 --- a/cores/esp8266/umm_malloc/umm_local.h +++ b/cores/esp8266/umm_malloc/umm_local.h @@ -15,7 +15,7 @@ #define memset ets_memset -/* +/* * This redefines DBGLOG_FORCE defined in dbglog/dbglog.h * Just for printing from umm_info() which is assumed to always be called from * non-ISR. Thus SPI bus is available to handle cache-miss and reading a flash @@ -42,7 +42,7 @@ static int check_poison_neighbors( unsigned short cur ); #if defined(UMM_STATS) || defined(UMM_STATS_FULL) -void ICACHE_FLASH_ATTR print_stats(int force); +void ICACHE_FLASH_ATTR umm_print_stats(int force); #endif @@ -51,4 +51,17 @@ int ICACHE_FLASH_ATTR umm_info_safe_printf_P(const char *fmt, ...) __attribute__ #define UMM_INFO_PRINTF(fmt, ...) umm_info_safe_printf_P(PSTR(fmt), ##__VA_ARGS__) +typedef struct umm_block_t umm_block; + +struct UMM_HEAP_CONTEXT { + umm_block *heap; + void *heap_end; +#if defined(UMM_STATS) || defined(UMM_STATS_FULL) + UMM_STATISTICS stats; +#endif + unsigned short int numblocks; + unsigned char id; +}; + + #endif diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 5feaa2edea..390daf42bb 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -59,6 +59,11 @@ extern "C" { #define DBGLOG_LEVEL 0 #endif +// Save 104 bytes by calling umm_init() early once from app_entry() +// Some minor UMM_CRITICAL_METRICS counts will be lost through CRT0 init. +// #define UMM_INIT_HEAP if (!umm_heap) { umm_init(); } +#define UMM_INIT_HEAP (void)0 + #include "dbglog/dbglog.h" #include "umm_local.h" // target-dependent supplemental @@ -85,16 +90,129 @@ UMM_H_ATTPACKPRE typedef struct umm_block_t { #define UMM_BLOCKNO_MASK (0x7FFF) /* ------------------------------------------------------------------------- */ +umm_heap_context_t heap_context[UMM_NUM_HEAPS] __attribute__((section(".noinit"))); +// void *umm_heap = NULL; + +/* A stack allowing push/popping of heaps for library use */ +#if (UMM_NUM_HEAPS == 1) + +#else +static size_t umm_heap_cur = UMM_HEAP_DRAM; +#define UMM_HEAP_STACK_DEPTH 32 +static int umm_heap_stack_ptr = 0; +static unsigned char umm_heap_stack[UMM_HEAP_STACK_DEPTH]; +#endif +/* ------------------------------------------------------------------------ */ +/* + * Methods to get heap id or context + * + */ + +#if (UMM_NUM_HEAPS == 1) +size_t umm_get_current_heap_id(void) { + return 0; +} + +static umm_heap_context_t *umm_get_current_heap(void) { + return &heap_context[0]; +} + +static umm_heap_context_t *umm_get_heap_by_id( size_t which ) { + (void)which; + return &heap_context[0]; +} + +umm_heap_context_t *umm_set_heap_by_id( size_t which ) { + (void)which; + return &heap_context[0]; +} + +#else +size_t umm_get_current_heap_id(void) { + return umm_heap_cur; +} + +static umm_heap_context_t *umm_get_current_heap(void) { + return &heap_context[umm_heap_cur]; +} + +static umm_heap_context_t *umm_get_heap_by_id( size_t which ) { + if (which < UMM_NUM_HEAPS) { + return &heap_context[which]; + } + return NULL; +} + +umm_heap_context_t *umm_set_heap_by_id( size_t which ) { + umm_heap_context_t *_context = umm_get_heap_by_id(which); + if (_context && _context->heap) { + umm_heap_cur = which; + return _context; + } + return NULL; +} +#endif -umm_block *umm_heap = NULL; -unsigned short int umm_numblocks = 0; +#if (UMM_NUM_HEAPS == 1) +umm_heap_context_t *umm_push_heap( size_t which ) { + (void)which; + return &heap_context[0]; +} -#define UMM_NUMBLOCKS (umm_numblocks) +umm_heap_context_t *umm_pop_heap( void ) { + return &heap_context[0]; +} + +#else +/* ------------------------------------------------------------------------ */ + +umm_heap_context_t *umm_push_heap( size_t which ) { + if (umm_heap_stack_ptr < UMM_HEAP_STACK_DEPTH) { + umm_heap_stack[umm_heap_stack_ptr++] = umm_heap_cur; + return umm_set_heap_by_id( which ); + } + return NULL; +} + +/* ------------------------------------------------------------------------ */ +umm_heap_context_t *umm_pop_heap( void ) { + if (umm_heap_stack_ptr > 0 ) { + return umm_set_heap_by_id(umm_heap_stack[--umm_heap_stack_ptr]); + } + return NULL; +} +#endif /* ------------------------------------------------------------------------ */ +/* + * Returns the correct heap context for a given pointer. Useful for + * realloc or free since you may not be in the right heap to handle it. + * + */ +static bool test_ptr_context( size_t which, void *ptr ) { + return + heap_context[which].heap && + ptr >= (void *)heap_context[which].heap && + ptr < heap_context[which].heap_end; +} -#define UMM_BLOCK(b) (umm_heap[b]) +static umm_heap_context_t *umm_get_ptr_context(void *ptr) { + for (size_t i = 0; i < UMM_NUM_HEAPS; i++) { + if (test_ptr_context( i, ptr ) ) { + return umm_get_heap_by_id( i ); + } + } + + panic(); + return NULL; +} + +#define UMM_NUMBLOCKS (_context->numblocks) +/* ------------------------------------------------------------------------ */ + +// #define UMM_BLOCK(b) (umm_heap[b]) +#define UMM_BLOCK(b) (_context->heap[b]) #define UMM_NBLOCK(b) (UMM_BLOCK(b).header.used.next) #define UMM_PBLOCK(b) (UMM_BLOCK(b).header.used.prev) #define UMM_NFREE(b) (UMM_BLOCK(b).body.free.next) @@ -149,7 +267,9 @@ static unsigned short int umm_blocks( size_t size ) { * * Note that free pointers are NOT modified by this function. */ -static void umm_split_block( unsigned short int c, +static void umm_split_block( + umm_heap_context_t *_context, + unsigned short int c, unsigned short int blocks, unsigned short int new_freemask ) { @@ -162,7 +282,9 @@ static void umm_split_block( unsigned short int c, /* ------------------------------------------------------------------------ */ -static void umm_disconnect_from_free_list( unsigned short int c ) { +static void umm_disconnect_from_free_list( + umm_heap_context_t *_context, + unsigned short int c ) { /* Disconnect this block from the FREE list */ UMM_NFREE(UMM_PFREE(c)) = UMM_NFREE(c); @@ -178,7 +300,9 @@ static void umm_disconnect_from_free_list( unsigned short int c ) { * have the UMM_FREELIST_MASK bit set! */ -static void umm_assimilate_up( unsigned short int c ) { +static void umm_assimilate_up( + umm_heap_context_t *_context, + unsigned short int c ) { if( UMM_NBLOCK(UMM_NBLOCK(c)) & UMM_FREELIST_MASK ) { /* @@ -190,7 +314,7 @@ static void umm_assimilate_up( unsigned short int c ) { /* Disconnect the next block from the FREE list */ - umm_disconnect_from_free_list( UMM_NBLOCK(c) ); + umm_disconnect_from_free_list( _context, UMM_NBLOCK(c) ); /* Assimilate the next block with this one */ @@ -204,7 +328,10 @@ static void umm_assimilate_up( unsigned short int c ) { * have the UMM_FREELIST_MASK bit set! */ -static unsigned short int umm_assimilate_down( unsigned short int c, unsigned short int freemask ) { +static unsigned short int umm_assimilate_down( + umm_heap_context_t *_context, + unsigned short int c, + unsigned short int freemask ) { UMM_NBLOCK(UMM_PBLOCK(c)) = UMM_NBLOCK(c) | freemask; UMM_PBLOCK(UMM_NBLOCK(c)) = UMM_PBLOCK(c); @@ -214,12 +341,7 @@ static unsigned short int umm_assimilate_down( unsigned short int c, unsigned sh /* ------------------------------------------------------------------------- */ -void umm_init( void ) { - /* init heap pointer and size, and memset it to 0 */ - umm_heap = (umm_block *)UMM_MALLOC_CFG_HEAP_ADDR; - umm_numblocks = (UMM_MALLOC_CFG_HEAP_SIZE / sizeof(umm_block)); - memset(umm_heap, 0x00, UMM_MALLOC_CFG_HEAP_SIZE); - +static void umm_init_stage_2( umm_heap_context_t *_context ) { /* setup initial blank heap structure */ { /* index of the 0th `umm_block` */ @@ -232,10 +354,10 @@ void umm_init( void ) { /* init ummStats.free_blocks */ #if defined(UMM_STATS) || defined(UMM_STATS_FULL) #if defined(UMM_STATS_FULL) - ummStats.free_blocks_min = - ummStats.free_blocks_isr_min = + _context->stats.free_blocks_min = + _context->stats.free_blocks_isr_min = #endif - ummStats.free_blocks = block_last; + _context->stats.free_blocks = block_last; #endif /* setup the 0th `umm_block`, which just points to the 1st */ @@ -279,15 +401,105 @@ void umm_init( void ) { } } + +void umm_init_common( size_t id, void *start_addr, size_t size, bool zero ) { + /* Preserve internal setup */ + umm_heap_context_t *_context = umm_get_heap_by_id(id); + if (NULL == _context || _context->heap) { + return; + } + + /* init heap pointer and size, and memset it to 0 */ + _context->id = id; + _context->heap = (umm_block *)start_addr; + _context->heap_end = (void *)((uintptr_t)start_addr + size); + _context->numblocks = (size / sizeof(umm_block)); + + // An option for blocking the zeroing of extra heaps allows for performing + // post-crash discovery. + if (zero) { + memset(_context->heap, 0x00, size); +#if defined(UMM_STATS) || defined(UMM_STATS_FULL) + memset(&_context->stats, 0x00, sizeof(_context->stats)); +#endif + + /* Set up internal data structures */ + umm_init_stage_2(_context); + } +} + +void umm_init( void ) { + // if (umm_heap) { + // return; + // } + for (size_t i = 0; i < UMM_NUM_HEAPS; i++) { + heap_context[i].heap = NULL; + } + memset(&heap_context[0], 0, sizeof(heap_context)); + umm_init_common( UMM_HEAP_DRAM, (void *)UMM_MALLOC_CFG_HEAP_ADDR, UMM_MALLOC_CFG_HEAP_SIZE, true ); + // umm_heap = (void *)&heap_context; +} + +#ifdef UMM_HEAP_IRAM +#include + +void umm_init_iram_ex( void *addr, unsigned int size, bool zero ) { + /* We need the main, internal heap set up first */ + UMM_INIT_HEAP; + + /* Required to use umm_malloc on iRAM */ + install_non32xfer_exception_handler(); + + // umm_init_common(UMM_HEAP_IRAM, addr, size); + umm_init_common(UMM_HEAP_IRAM, addr, size, zero); +} + +void _text_end(void); +void umm_init_iram(void) __attribute__((weak)); + +void umm_init_iram(void) { + uint32_t sec_heap = MMU_SEC_HEAP; + size_t sec_heap_sz = MMU_SEC_HEAP_SIZE; + +#ifdef UUM_MERGE_FREE_IRAM_W_SEC_HEAP + // Combine free IRAM from 1st 32K with 16K of Second Heap + uint32_t iram_free = MMU_IRAM_SIZE - (uint32_t)((uintptr_t)_text_end - 0x40100000UL); + iram_free &= ~7; + if (iram_free > 40) { + iram_free -= 32; + sec_heap -= iram_free; + sec_heap_sz += iram_free; + } +#endif + + umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); +} + +#endif // #ifdef UMM_HEAP_IRAM + +#ifdef UMM_HEAP_EXTERNAL +void umm_init_vm( void *vmaddr, unsigned int vmsize ) { + /* We need the main, internal heap set up first */ + UMM_INIT_HEAP; + + umm_init_common(UMM_HEAP_EXTERNAL, vmaddr, vmsize, true); +} +#endif + /* ------------------------------------------------------------------------ * Must be called only from within critical sections guarded by * UMM_CRITICAL_ENTRY() and UMM_CRITICAL_EXIT(). */ -static void umm_free_core( void *ptr ) { +static void umm_free_core( umm_heap_context_t *_context, void *ptr ) { unsigned short int c; + if (NULL == _context) { + panic(); + return; + } + STATS__FREE_REQUEST(id_free); /* * FIXME: At some point it might be a good idea to add a check to make sure @@ -300,7 +512,7 @@ static void umm_free_core( void *ptr ) { /* Figure out which block we're in. Note the use of truncated division... */ - c = (((char *)ptr)-(char *)(&(umm_heap[0])))/sizeof(umm_block); + c = (((char *)ptr)-(char *)(&(_context->heap[0])))/sizeof(umm_block); DBGLOG_DEBUG( "Freeing block %6d\n", c ); @@ -309,7 +521,7 @@ static void umm_free_core( void *ptr ) { /* Now let's assimilate this block with the next one if possible. */ - umm_assimilate_up( c ); + umm_assimilate_up( _context, c ); /* Then assimilate with the previous block if possible */ @@ -317,7 +529,7 @@ static void umm_free_core( void *ptr ) { DBGLOG_DEBUG( "Assimilate down to next block, which is FREE\n" ); - c = umm_assimilate_down(c, UMM_FREELIST_MASK); + c = umm_assimilate_down(_context, c, UMM_FREELIST_MASK); } else { /* * The previous block is not a free block, so add this one to the head @@ -340,9 +552,7 @@ static void umm_free_core( void *ptr ) { void umm_free( void *ptr ) { UMM_CRITICAL_DECL(id_free); - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; /* If we're being asked to free a NULL pointer, well that's just silly! */ @@ -357,7 +567,8 @@ void umm_free( void *ptr ) { UMM_CRITICAL_ENTRY(id_free); - umm_free_core( ptr ); + /* Need to be in the heap in which this block lives */ + umm_free_core( umm_get_ptr_context( ptr ), ptr ); UMM_CRITICAL_EXIT(id_free); } @@ -367,7 +578,7 @@ void umm_free( void *ptr ) { * UMM_CRITICAL_ENTRY() and UMM_CRITICAL_EXIT(). */ -static void *umm_malloc_core( size_t size ) { +static void *umm_malloc_core( umm_heap_context_t *_context, size_t size ) { unsigned short int blocks; unsigned short int blockSize = 0; @@ -378,6 +589,11 @@ static void *umm_malloc_core( size_t size ) { STATS__ALLOC_REQUEST(id_malloc, size); + if (NULL == _context) { + panic(); + return NULL; + } + blocks = umm_blocks( size ); /* @@ -435,7 +651,7 @@ static void *umm_malloc_core( size_t size ) { /* Disconnect this block from the FREE list */ - umm_disconnect_from_free_list( cf ); + umm_disconnect_from_free_list( _context, cf ); } else { /* It's not an exact fit and we need to split off a block. */ @@ -445,7 +661,7 @@ static void *umm_malloc_core( size_t size ) { * split current free block `cf` into two blocks. The first one will be * returned to user, so it's not free, and the second one will be free. */ - umm_split_block( cf, blocks, UMM_FREELIST_MASK /*new block is free*/ ); + umm_split_block( _context, cf, blocks, UMM_FREELIST_MASK /*new block is free*/ ); /* * `umm_split_block()` does not update the free pointers (it affects @@ -484,9 +700,7 @@ void *umm_malloc( size_t size ) { void *ptr = NULL; - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; /* * the very first thing we do is figure out if we're being asked to allocate @@ -495,6 +709,8 @@ void *umm_malloc( size_t size ) { * the number of blocks to allocate are easier... */ + umm_heap_context_t *_context = umm_get_current_heap(); + if( 0 == size ) { DBGLOG_DEBUG( "malloc a block of 0 bytes -> do nothing\n" ); STATS__ZERO_ALLOC_REQUEST(id_malloc, size); @@ -506,7 +722,11 @@ void *umm_malloc( size_t size ) { UMM_CRITICAL_ENTRY(id_malloc); - ptr = umm_malloc_core( size ); + if (UMM_CRITICAL_WITHINISR(id_malloc)) { + _context = umm_get_heap_by_id(UMM_HEAP_DRAM); + } + + ptr = umm_malloc_core( _context, size ); UMM_CRITICAL_EXIT(id_malloc); @@ -527,9 +747,7 @@ void *umm_realloc( void *ptr, size_t size ) { size_t curSize; - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; /* * This code looks after the case of a NULL value for ptr. The ANSI C @@ -551,6 +769,12 @@ void *umm_realloc( void *ptr, size_t size ) { * we should operate the same as free. */ + /* Need to be in the heap in which this block lives */ + umm_heap_context_t *_context = umm_get_ptr_context( ptr ); + if (NULL == _context) { + panic(); + return NULL; + } if( 0 == size ) { DBGLOG_DEBUG( "realloc to 0 size, just free the block\n" ); @@ -563,6 +787,11 @@ void *umm_realloc( void *ptr, size_t size ) { STATS__ALLOC_REQUEST(id_realloc, size); + // Require ISR use DRAM for now. + if (ETS_INTR_WITHINISR() && UMM_HEAP_DRAM != _context->id) { + return( (void *)NULL ); + } + /* * Otherwise we need to actually do a reallocation. A naiive approach * would be to malloc() a new block of the correct size, copy the old data @@ -576,7 +805,7 @@ void *umm_realloc( void *ptr, size_t size ) { /* Figure out which block we're in. Note the use of truncated division... */ - c = (((char *)ptr)-(char *)(&(umm_heap[0])))/sizeof(umm_block); + c = (((char *)ptr)-(char *)(&(_context->heap[0])))/sizeof(umm_block); /* Figure out how big this block is ... the free bit is not set :-) */ @@ -636,13 +865,13 @@ void *umm_realloc( void *ptr, size_t size ) { /* This space intentionally left blank */ } else if ((blockSize + nextBlockSize) >= blocks) { DBGLOG_DEBUG( "realloc using next block - %i\n", blocks ); - umm_assimilate_up( c ); + umm_assimilate_up( _context, c ); STATS__FREE_BLOCKS_UPDATE( - nextBlockSize ); blockSize += nextBlockSize; } else if ((prevBlockSize + blockSize) >= blocks) { DBGLOG_DEBUG( "realloc using prev block - %i\n", blocks ); - umm_disconnect_from_free_list( UMM_PBLOCK(c) ); - c = umm_assimilate_down(c, 0); + umm_disconnect_from_free_list( _context, UMM_PBLOCK(c) ); + c = umm_assimilate_down(_context, c, 0); STATS__FREE_BLOCKS_UPDATE( - prevBlockSize ); STATS__FREE_BLOCKS_ISR_MIN(); blockSize += prevBlockSize; @@ -652,14 +881,14 @@ void *umm_realloc( void *ptr, size_t size ) { UMM_CRITICAL_RESUME(id_realloc); } else if ((prevBlockSize + blockSize + nextBlockSize) >= blocks) { DBGLOG_DEBUG( "realloc using prev and next block - %d\n", blocks ); - umm_assimilate_up( c ); - umm_disconnect_from_free_list( UMM_PBLOCK(c) ); - c = umm_assimilate_down(c, 0); + umm_assimilate_up( _context, c ); + umm_disconnect_from_free_list( _context, UMM_PBLOCK(c) ); + c = umm_assimilate_down(_context, c, 0); STATS__FREE_BLOCKS_UPDATE( - prevBlockSize - nextBlockSize ); #ifdef UMM_LIGHTWEIGHT_CPU if ((prevBlockSize + blockSize + nextBlockSize) > blocks) { - umm_split_block( c, blocks, 0 ); - umm_free_core( (void *)&UMM_DATA(c+blocks) ); + umm_split_block( _context, c, blocks, 0 ); + umm_free_core( _context, (void *)&UMM_DATA(c+blocks) ); } STATS__FREE_BLOCKS_ISR_MIN(); blockSize = blocks; @@ -673,12 +902,12 @@ void *umm_realloc( void *ptr, size_t size ) { } else { DBGLOG_DEBUG( "realloc a completely new block %i\n", blocks ); void *oldptr = ptr; - if( (ptr = umm_malloc_core( size )) ) { + if( (ptr = umm_malloc_core( _context, size )) ) { DBGLOG_DEBUG( "realloc %i to a bigger block %i, copy, and free the old\n", blockSize, blocks ); UMM_CRITICAL_SUSPEND(id_realloc); memcpy( ptr, oldptr, curSize ); UMM_CRITICAL_RESUME(id_realloc); - umm_free_core( oldptr ); + umm_free_core( _context, oldptr ); } else { DBGLOG_DEBUG( "realloc %i to a bigger block %i failed - return NULL and leave the old block!\n", blockSize, blocks ); /* This space intentionally left blnk */ @@ -716,8 +945,8 @@ void *umm_realloc( void *ptr, size_t size ) { * requested number of blocks and add what's left to the free list. */ if (prevBlockSize && (prevBlockSize + blockSize + nextBlockSize) >= blocks) { // 1 - umm_disconnect_from_free_list( UMM_PBLOCK(c) ); - c = umm_assimilate_down(c, 0); + umm_disconnect_from_free_list( _context, UMM_PBLOCK(c) ); + c = umm_assimilate_down( _context, c, 0 ); STATS__FREE_BLOCKS_UPDATE( - prevBlockSize ); blockSize += prevBlockSize; if (blockSize >= blocks) { @@ -725,13 +954,13 @@ void *umm_realloc( void *ptr, size_t size ) { STATS__FREE_BLOCKS_ISR_MIN(); } else { DBGLOG_DEBUG( "realloc using prev and next block - %d\n", blocks ); - umm_assimilate_up( c ); + umm_assimilate_up( _context, c ); STATS__FREE_BLOCKS_UPDATE( - nextBlockSize ); blockSize += nextBlockSize; #ifdef UMM_LIGHTWEIGHT_CPU if (blockSize > blocks) { - umm_split_block( c, blocks, 0 ); - umm_free_core( (void *)&UMM_DATA(c+blocks) ); + umm_split_block( _context, c, blocks, 0 ); + umm_free_core( _context, (void *)&UMM_DATA(c+blocks) ); } STATS__FREE_BLOCKS_ISR_MIN(); blockSize = blocks; @@ -746,18 +975,18 @@ void *umm_realloc( void *ptr, size_t size ) { /* This space intentionally left blank */ } else if ((blockSize + nextBlockSize) >= blocks) { // 3 DBGLOG_DEBUG( "realloc using next block - %d\n", blocks ); - umm_assimilate_up( c ); + umm_assimilate_up( _context, c ); STATS__FREE_BLOCKS_UPDATE( - nextBlockSize ); blockSize += nextBlockSize; } else { // 4 DBGLOG_DEBUG( "realloc a completely new block %d\n", blocks ); void *oldptr = ptr; - if( (ptr = umm_malloc_core( size )) ) { + if( (ptr = umm_malloc_core( _context, size )) ) { DBGLOG_DEBUG( "realloc %d to a bigger block %d, copy, and free the old\n", blockSize, blocks ); UMM_CRITICAL_SUSPEND(id_realloc); memcpy( ptr, oldptr, curSize ); UMM_CRITICAL_RESUME(id_realloc); - umm_free_core( oldptr); + umm_free_core( _context, oldptr); } else { DBGLOG_DEBUG( "realloc %d to a bigger block %d failed - return NULL and leave the old block!\n", blockSize, blocks ); /* This space intentionally left blnk */ @@ -782,7 +1011,7 @@ void *umm_realloc( void *ptr, size_t size ) { UMM_CRITICAL_SUSPEND(id_realloc); memcpy( ptr, oldptr, curSize ); UMM_CRITICAL_RESUME(id_realloc); - umm_free_core( oldptr ); + umm_free_core( _context, oldptr ); } else { DBGLOG_DEBUG( "realloc %d to a bigger block %d failed - return NULL and leave the old block!\n", blockSize, blocks ); /* This space intentionally left blnk */ @@ -800,8 +1029,8 @@ void *umm_realloc( void *ptr, size_t size ) { if (blockSize > blocks ) { DBGLOG_DEBUG( "split and free %d blocks from %d\n", blocks, blockSize ); - umm_split_block( c, blocks, 0 ); - umm_free_core( (void *)&UMM_DATA(c+blocks) ); + umm_split_block( _context, c, blocks, 0 ); + umm_free_core( _context, (void *)&UMM_DATA(c+blocks) ); } STATS__FREE_BLOCKS_MIN(); diff --git a/cores/esp8266/umm_malloc/umm_malloc.h b/cores/esp8266/umm_malloc/umm_malloc.h index 4c68b72027..0f25feeeb7 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.h +++ b/cores/esp8266/umm_malloc/umm_malloc.h @@ -18,14 +18,101 @@ extern "C" { #endif void umm_init( void ); + +#ifdef UMM_HEAP_EXTERNAL +void umm_init_vm( void *vmaddr, unsigned int vmsize ); +#endif +#ifdef UMM_HEAP_IRAM +void umm_init_iram(void); +void umm_init_iram_ex( void *addr, unsigned int size, bool zero ); +#endif + void *umm_malloc( size_t size ); void *umm_calloc( size_t num, size_t size ); void *umm_realloc( void *ptr, size_t size ); void umm_free( void *ptr ); +umm_heap_context_t *umm_push_heap( size_t heap_number ); +umm_heap_context_t *umm_pop_heap( void ); +umm_heap_context_t *umm_set_heap_by_id( size_t which ); +size_t umm_get_current_heap_id(void); + + #ifdef __cplusplus } #endif +/* + This is pattered after interrupts.h + + HeapSelectIram is used to temporarily select an alternate Heap. + + { + { + HeapSelectIram lock; + // allocate memory here + } + allocations here are from the old Heap selection + } + */ + +class HeapSelect { +public: +#if (UMM_NUM_HEAPS == 1) + HeapSelect(size_t id) { (void)id; } + ~HeapSelect() {} +#else + HeapSelect(size_t id) : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(id); + } + + ~HeapSelect() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; +#endif +}; + +class HeapSelectIram { +public: +#ifdef UMM_HEAP_IRAM + HeapSelectIram() : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(UMM_HEAP_IRAM); + } + + ~HeapSelectIram() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; + +#else + HeapSelectIram() {} + ~HeapSelectIram() {} +#endif +}; + +class HeapSelectDram { +public: +#if (UMM_NUM_HEAPS == 1) + HeapSelectDram() {} + ~HeapSelectDram() {} +#else + HeapSelectDram() : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(UMM_HEAP_DRAM); + } + + ~HeapSelectDram() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; +#endif +}; + /* ------------------------------------------------------------------------ */ diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index 9d41d96b4e..2f083f4746 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -11,6 +11,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -22,6 +23,45 @@ extern "C" { #include "c_types.h" +// Combine free IRAM from 1st 32K with 16K of Second Heap +#define UUM_MERGE_FREE_IRAM_W_SEC_HEAP + +/* + * Define active Heaps + */ +#ifdef MMU_SEC_HEAP +#define UMM_HEAP_IRAM +#else +#undef UMM_HEAP_IRAM +#endif + +// #define UMM_HEAP_EXTERNAL + +/* + * Assign IDs to active Heaps and tally. DRAM is always active. + */ +#define UMM_HEAP_DRAM 0 +#define UMM_HEAP_DRAM_DEFINED 1 + +#ifdef UMM_HEAP_IRAM +#undef UMM_HEAP_IRAM +#define UMM_HEAP_IRAM_DEFINED 1 +#define UMM_HEAP_IRAM UMM_HEAP_DRAM_DEFINED +#else +#define UMM_HEAP_IRAM_DEFINED 0 +#endif + +#ifdef UMM_HEAP_EXTERNAL +#undef UMM_HEAP_EXTERNAL +#define UMM_HEAP_EXTERNAL_DEFINED 1 +#define UMM_HEAP_EXTERNAL (UMM_HEAP_DRAM_DEFINED + UMM_HEAP_IRAM_DEFINED) +#else +#define UMM_HEAP_EXTERNAL_DEFINED 0 +#endif + +#define UMM_NUM_HEAPS (UMM_HEAP_DRAM_DEFINED + UMM_HEAP_IRAM_DEFINED + UMM_HEAP_EXTERNAL_DEFINED) + + /* * There are a number of defines you can set at compile time that affect how * the memory allocator will operate. @@ -67,8 +107,9 @@ extern char test_umm_heap[]; #else /* Start addresses and the size of the heap */ extern char _heap_start[]; +#define UMM_HEAP_END_ADDR 0x3FFFC000UL #define UMM_MALLOC_CFG_HEAP_ADDR ((uint32_t)&_heap_start[0]) -#define UMM_MALLOC_CFG_HEAP_SIZE ((size_t)(0x3fffc000 - UMM_MALLOC_CFG_HEAP_ADDR)) +#define UMM_MALLOC_CFG_HEAP_SIZE ((size_t)(UMM_HEAP_END_ADDR - UMM_MALLOC_CFG_HEAP_ADDR)) #endif /* A couple of macros to make packing structures less compiler dependent */ @@ -113,6 +154,9 @@ extern char _heap_start[]; #else #endif +struct UMM_HEAP_CONTEXT; +typedef struct UMM_HEAP_CONTEXT umm_heap_context_t; + /* * -D UMM_STATS : * -D UMM_STATS_FULL @@ -172,14 +216,11 @@ typedef struct UMM_STATISTICS_t { UMM_STATISTICS; extern UMM_STATISTICS ummStats; -#define STATS__FREE_BLOCKS_UPDATE(s) ummStats.free_blocks += (s) -#define STATS__OOM_UPDATE() ummStats.oom_count += 1 +#define STATS__FREE_BLOCKS_UPDATE(s) _context->stats.free_blocks += (s) +#define STATS__OOM_UPDATE() _context->stats.oom_count += 1 size_t umm_free_heap_size_lw( void ); - -static inline size_t ICACHE_FLASH_ATTR umm_get_oom_count( void ) { - return ummStats.oom_count; -} +size_t umm_get_oom_count( void ); #else // not UMM_STATS or UMM_STATS_FULL #define STATS__FREE_BLOCKS_UPDATE(s) (void)(s) @@ -193,87 +234,53 @@ size_t ICACHE_FLASH_ATTR umm_block_size( void ); #ifdef UMM_STATS_FULL #define STATS__FREE_BLOCKS_MIN() \ do { \ - if (ummStats.free_blocks < ummStats.free_blocks_min) \ - ummStats.free_blocks_min = ummStats.free_blocks; \ + if (_context->stats.free_blocks < _context->stats.free_blocks_min) \ + _context->stats.free_blocks_min = _context->stats.free_blocks; \ } while(false) #define STATS__FREE_BLOCKS_ISR_MIN() \ do { \ - if (ummStats.free_blocks < ummStats.free_blocks_isr_min) \ - ummStats.free_blocks_isr_min = ummStats.free_blocks; \ + if (_context->stats.free_blocks < _context->stats.free_blocks_isr_min) \ + _context->stats.free_blocks_isr_min = _context->stats.free_blocks; \ } while(false) #define STATS__ALLOC_REQUEST(tag, s) \ do { \ - ummStats.tag##_count += 1; \ - ummStats.last_alloc_size = s; \ - if (ummStats.alloc_max_size < s) \ - ummStats.alloc_max_size = s; \ + _context->stats.tag##_count += 1; \ + _context->stats.last_alloc_size = s; \ + if (_context->stats.alloc_max_size < s) \ + _context->stats.alloc_max_size = s; \ } while(false) #define STATS__ZERO_ALLOC_REQUEST(tag, s) \ do { \ - ummStats.tag##_zero_count += 1; \ + _context->stats.tag##_zero_count += 1; \ } while(false) #define STATS__NULL_FREE_REQUEST(tag) \ do { \ - ummStats.tag##_null_count += 1; \ + umm_heap_context_t *_context = umm_get_current_heap(); \ + _context->stats.tag##_null_count += 1; \ } while(false) #define STATS__FREE_REQUEST(tag) \ do { \ - ummStats.tag##_count += 1; \ + _context->stats.tag##_count += 1; \ } while(false) -static inline size_t ICACHE_FLASH_ATTR umm_free_heap_size_lw_min( void ) { - return (size_t)ummStats.free_blocks_min * umm_block_size(); -} - -static inline size_t ICACHE_FLASH_ATTR umm_free_heap_size_min_reset( void ) { - ummStats.free_blocks_min = ummStats.free_blocks; - return (size_t)ummStats.free_blocks_min * umm_block_size(); -} - -static inline size_t ICACHE_FLASH_ATTR umm_free_heap_size_min( void ) { - return ummStats.free_blocks_min * umm_block_size(); -} - -static inline size_t ICACHE_FLASH_ATTR umm_free_heap_size_isr_min( void ) { - return ummStats.free_blocks_isr_min * umm_block_size(); -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_max_alloc_size( void ) { - return ummStats.alloc_max_size; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_last_alloc_size( void ) { - return ummStats.last_alloc_size; -} -static inline size_t ICACHE_FLASH_ATTR umm_get_malloc_count( void ) { - return ummStats.id_malloc_count; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_malloc_zero_count( void ) { - return ummStats.id_malloc_zero_count; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_realloc_count( void ) { - return ummStats.id_realloc_count; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_realloc_zero_count( void ) { - return ummStats.id_realloc_zero_count; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_free_count( void ) { - return ummStats.id_free_count; -} - -static inline size_t ICACHE_FLASH_ATTR umm_get_free_null_count( void ) { - return ummStats.id_free_null_count; -} +size_t umm_free_heap_size_lw_min( void ); +size_t umm_free_heap_size_min_reset( void ); +size_t umm_free_heap_size_min( void ); +size_t umm_free_heap_size_isr_min( void ); +size_t umm_get_max_alloc_size( void ); +size_t umm_get_last_alloc_size( void ); +size_t umm_get_malloc_count( void ); +size_t umm_get_malloc_zero_count( void ); +size_t umm_get_realloc_count( void ); +size_t umm_get_realloc_zero_count( void ); +size_t umm_get_free_count( void ); +size_t umm_get_free_null_count( void ); #else // Not UMM_STATS_FULL #define STATS__FREE_BLOCKS_MIN() (void)0 @@ -375,6 +382,7 @@ static inline void _critical_exit(UMM_TIME_STAT *p, uint32_t *saved_ps) { #define UMM_CRITICAL_DECL(tag) uint32_t _saved_ps_##tag #define UMM_CRITICAL_ENTRY(tag)_critical_entry(&time_stats.tag, &_saved_ps_##tag) #define UMM_CRITICAL_EXIT(tag) _critical_exit(&time_stats.tag, &_saved_ps_##tag) + #define UMM_CRITICAL_WITHINISR(tag) (0 != (_saved_ps_##tag & 0x0F)) #else // ! UMM_CRITICAL_METRICS // This method preserves the intlevel on entry and restores the @@ -382,6 +390,7 @@ static inline void _critical_exit(UMM_TIME_STAT *p, uint32_t *saved_ps) { #define UMM_CRITICAL_DECL(tag) uint32_t _saved_ps_##tag #define UMM_CRITICAL_ENTRY(tag) _saved_ps_##tag = xt_rsil(DEFAULT_CRITICAL_SECTION_INTLEVEL) #define UMM_CRITICAL_EXIT(tag) xt_wsr_ps(_saved_ps_##tag) + #define UMM_CRITICAL_WITHINISR(tag) (0 != (_saved_ps_##tag & 0x0F)) #endif #endif @@ -625,6 +634,9 @@ void free_loc (void* p, const char* file, int line); #else // !defined(ESP_DEBUG_OOM) #endif + + + #ifdef __cplusplus } #endif diff --git a/cores/esp8266/umm_malloc/umm_poison.c b/cores/esp8266/umm_malloc/umm_poison.c index 760ce1802c..38ff3176b9 100644 --- a/cores/esp8266/umm_malloc/umm_poison.c +++ b/cores/esp8266/umm_malloc/umm_poison.c @@ -132,8 +132,13 @@ static void *get_unpoisoned( void *v_ptr ) { ptr -= (sizeof(UMM_POISONED_BLOCK_LEN_TYPE) + UMM_POISON_SIZE_BEFORE); + umm_heap_context_t *_context = umm_get_ptr_context( v_ptr ); + if (NULL == _context) { + panic(); + return NULL: + } /* Figure out which block we're in. Note the use of truncated division... */ - c = (((char *)ptr)-(char *)(&(umm_heap[0])))/sizeof(umm_block); + c = (((char *)ptr)-(char *)(&(_context->heap[0])))/sizeof(umm_block); check_poison_block(&UMM_BLOCK(c)); } @@ -209,11 +214,10 @@ int umm_poison_check(void) { int ok = 1; unsigned short int cur; - if (umm_heap == NULL) { - umm_init(); - } + UMM_INIT_HEAP; UMM_CRITICAL_ENTRY(id_poison); + umm_heap_context_t *_context = umm_get_current_heap(); /* Now iterate through the blocks list */ cur = UMM_NBLOCK(0) & UMM_BLOCKNO_MASK; diff --git a/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino b/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino index 4b786dc1a5..e02e589fc0 100644 --- a/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino +++ b/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino @@ -13,6 +13,7 @@ #include #include #include +#include #ifndef STASSID #define STASSID "your-ssid" @@ -142,7 +143,68 @@ void setup(void){ Serial.println("HTTPS server started"); } +extern "C" void stack_thunk_dump_stack(); + +void processKey(Print& out, int hotKey) { + switch (hotKey) { + case 'd': { + HeapSelectDram ephemeral; + umm_info(NULL, true); + break; + } + case 'i': { + HeapSelectIram ephemeral; + umm_info(NULL, true); + break; + } + case 'h': { + { + HeapSelectIram ephemeral; + Serial.printf(PSTR("IRAM ESP.getFreeHeap: %u\n"), ESP.getFreeHeap()); + } + { + HeapSelectDram ephemeral; + Serial.printf(PSTR("DRAM ESP.getFreeHeap: %u\n"), ESP.getFreeHeap()); + } + break; + } + case 'P': + out.println(F("Calling stack_thunk_dump_stack();")); + stack_thunk_dump_stack(); + break; + case 'R': + out.printf_P(PSTR("Restart, ESP.restart(); ...\r\n")); + ESP.restart(); + break; + case '\r': + out.println(); + case '\n': + break; + case '?': + out.println(); + out.println(F("Press a key + ")); + out.println(F(" h - Free Heap Report;")); + out.println(F(" i - iRAM umm_info(null, true);")); + out.println(F(" d - dRAM umm_info(null, true);")); + out.println(F(" p - call stack_thunk_dump_stack();")); + out.println(F(" R - Restart, ESP.restart();")); + out.println(F(" ? - Print Help")); + out.println(); + break; + default: + out.printf_P(PSTR("\"%c\" - Not an option? / ? - help"), hotKey); + out.println(); + processKey(out, '?'); + break; + } +} + + void loop(void){ server.handleClient(); MDNS.update(); + if (Serial.available() > 0) { + int hotKey = Serial.read(); + processKey(Serial, hotKey); + } } diff --git a/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp b/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp index 773f68cfdc..d48287c5ed 100644 --- a/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp +++ b/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp @@ -25,6 +25,7 @@ #include #include #include +#include extern "C" { #include "osapi.h" @@ -44,6 +45,8 @@ extern "C" { #include #include "c_types.h" #include "coredecls.h" +#include +#include #if !CORE_MOCK @@ -438,17 +441,17 @@ int WiFiClientSecure::_run_until(unsigned target, bool blocking) { DEBUG_BSSL("_run_until: Not connected\n"); return -1; } - + esp8266::polledTimeout::oneShotMs loopTimeout(_timeout); - - for (int no_work = 0; blocking || no_work < 2;) { + + for (int no_work = 0; blocking || no_work < 2;) { optimistic_yield(100); - + if (loopTimeout) { DEBUG_BSSL("_run_until: Timeout\n"); return -1; } - + int state; state = br_ssl_engine_current_state(_eng); if (state & BR_SSL_CLOSED) { @@ -471,15 +474,15 @@ int WiFiClientSecure::_run_until(unsigned target, bool blocking) { buf = br_ssl_engine_sendrec_buf(_eng, &len); availForWrite = WiFiClient::availableForWrite(); - + if (!blocking && len > availForWrite) { - /* + /* writes on WiFiClient will block if len > availableForWrite() this is needed to prevent available() calls from blocking - on dropped connections + on dropped connections */ len = availForWrite; - } + } wlen = WiFiClient::write(buf, len); if (wlen <= 0) { /* @@ -1067,8 +1070,15 @@ bool WiFiClientSecure::_connectSSL(const char* hostName) { _sc = std::make_shared(); _eng = &_sc->eng; // Allocation/deallocation taken care of by the _sc shared_ptr - _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); - _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + { // ESP.setIramHeap(); + HeapSelectIram ephemeral; + _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); + _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + } // ESP.resetHeap(); if (!_sc || !_iobuf_in || !_iobuf_out) { _freeSSL(); // Frees _sc, _iobuf* @@ -1183,8 +1193,15 @@ bool WiFiClientSecure::_connectSSLServerRSA(const X509List *chain, _oom_err = false; _sc_svr = std::make_shared(); _eng = &_sc_svr->eng; // Allocation/deallocation taken care of by the _sc shared_ptr - _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); - _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + { // ESP.setIramHeap(); + HeapSelectIram ephemeral; + _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); + _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + } // ESP.resetHeap(); if (!_sc_svr || !_iobuf_in || !_iobuf_out) { _freeSSL(); @@ -1196,7 +1213,7 @@ bool WiFiClientSecure::_connectSSLServerRSA(const X509List *chain, br_ssl_server_base_init(_sc_svr.get(), suites_server_rsa_P, sizeof(suites_server_rsa_P) / sizeof(suites_server_rsa_P[0])); br_ssl_server_set_single_rsa(_sc_svr.get(), chain ? chain->getX509Certs() : nullptr, chain ? chain->getCount() : 0, sk ? sk->getRSA() : nullptr, BR_KEYTYPE_KEYX | BR_KEYTYPE_SIGN, - br_rsa_private_get_default(), br_rsa_pkcs1_sign_get_default()); + br_rsa_private_get_default(), br_rsa_pkcs1_sign_get_default()); br_ssl_engine_set_buffers_bidi(_eng, _iobuf_in.get(), _iobuf_in_size, _iobuf_out.get(), _iobuf_out_size); if (client_CA_ta && !_installServerX509Validator(client_CA_ta)) { DEBUG_BSSL("_connectSSLServerRSA: Can't install serverX509check\n"); @@ -1220,8 +1237,15 @@ bool WiFiClientSecure::_connectSSLServerEC(const X509List *chain, _oom_err = false; _sc_svr = std::make_shared(); _eng = &_sc_svr->eng; // Allocation/deallocation taken care of by the _sc shared_ptr - _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); - _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + { // ESP.setIramHeap(); + HeapSelectIram ephemeral; + _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); + _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); + ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + } // ESP.resetHeap(); if (!_sc_svr || !_iobuf_in || !_iobuf_out) { _freeSSL(); @@ -1402,7 +1426,7 @@ bool WiFiClientSecure::probeMaxFragmentLength(IPAddress ip, uint16_t port, uint1 0x00, 26 + 14 + 6 + 5, // Extension length 0x00, 0x0d, 0x00, 0x16, 0x00, 0x14, 0x04, 0x03, 0x03, 0x03, 0x05, 0x03, 0x06, 0x03, 0x02, 0x03, 0x04, 0x01, 0x03, 0x01, 0x05, 0x01, 0x06, - 0x01, 0x02, 0x01, // Supported signature algorithms + 0x01, 0x02, 0x01, // Supported signature algorithms 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x08, 0x00, 0x17, 0x00, 0x18, 0x00, 0x19, 0x00, 0x1d, // Supported groups 0x00, 0x0b, 0x00, 0x02, 0x01, 0x00, // Supported EC formats diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 1fc94310af..747b209c4f 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -1,5 +1,6 @@ #include #include +#include uint32_t timed_byte_read(char *pc, uint32_t * o); uint32_t timed_byte_read2(char *pc, uint32_t * o); @@ -23,12 +24,17 @@ constexpr size_t gobble_sz = sizeof(gobble); #endif #ifdef MMU_SEC_HEAP -constexpr uint32_t *gobble = (uint32_t *)MMU_SEC_HEAP; -constexpr size_t gobble_sz = MMU_SEC_HEAP_SIZE; +uint32_t *gobble; +size_t gobble_sz; #endif bool isValid(uint32_t *probe) { bool rc = true; + if (NULL == probe) { + ets_uart_printf("\nNULL memory pointer %p ...\n", probe); + return false; + } + ets_uart_printf("\nTesting for valid memory at %p ...\n", probe); uint32_t savePS = xt_rsil(15); uint32_t saveData = *probe; @@ -119,18 +125,30 @@ void setup() { print_mmu_status(Serial); +#ifdef MMU_SEC_HEAP + { + HeapSelectIram ephemeral; + // Serial.printf_P(PSTR("ESP.getFreeHeap(): %u\n"), ESP.getFreeHeap()); + gobble_sz = ESP.getFreeHeap(); // - 4096; + gobble = (uint32_t *)malloc(gobble_sz); + } + Serial.printf_P(PSTR("gobble_sz: %u\n"), gobble_sz); + Serial.printf_P(PSTR("gobble: %p\n"), gobble); + +#endif + #if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_SEC_HEAP) if (isValid(gobble)) { // Put something in our new memory for (size_t i = 0; i < (gobble_sz / 4); i++) { gobble[i] = (uint32_t)&gobble[i]; } - } - // Now is it there? - dump_mem32(gobble, 32); - // dump_mem32(&gobble[gobble_sz / 4 / 2], 32); - dump_mem32(&gobble[gobble_sz / 4 - 32], 32); + // Now is it there? + dump_mem32(gobble, 32); + // dump_mem32(&gobble[gobble_sz / 4 / 2], 32); + dump_mem32(&gobble[gobble_sz / 4 - 32], 32); + } #endif // Lets peak over the edge @@ -138,10 +156,10 @@ void setup() { } int* nullPointer = NULL; -constexpr char *probe_b = (char *)0x40108000; -constexpr short *probe_s = (short *)0x40108000; -constexpr char *probe_c = (char *)0x40110000; -constexpr short *unaligned_probe_s = (short *)0x3FFF8001; +char *probe_b = (char *)gobble; +short *probe_s = (short *)((uintptr_t)gobble); +char *probe_c = (char *)0x40110000; +short *unaligned_probe_s = (short *)((uintptr_t)gobble + 1); uint32_t read_var = 0x11223344; @@ -297,3 +315,23 @@ void loop() { int divideA_B(int a, int b) { return (a / b); } + +#if 0 +#ifdef MMU_SEC_HEAP +extern "C" void _text_end(void); + +extern "C" void umm_init_iram(void) { + // Merge free IRAM into Second Heap + uint32_t iram_free = MMU_IRAM_SIZE - (uint32_t)((uintptr_t)_text_end - 0x40100000UL); + uint32_t sec_heap = MMU_SEC_HEAP; + size_t sec_heap_sz = MMU_SEC_HEAP_SIZE; + iram_free &= ~7; + if (iram_free > 40) { + iram_free -= 32; + sec_heap -= iram_free; + sec_heap_sz += iram_free; + } + umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); +} +#endif +#endif diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino new file mode 100644 index 0000000000..3e5f2f696e --- /dev/null +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -0,0 +1,260 @@ +/* + This sketch assumes you have selected IRAM as a Second Heap from + the Arduino IDE tools menu. + */ + +#include +#include + +// #define USE_SET_IRAM_HEAP + + +#ifndef ETS_PRINTF +#define ETS_PRINTF ets_uart_printf +#endif + +uint32_t cyclesToRead1Kx32(unsigned int *x, uint32_t *res) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += *(x++); + } + *res = sum; + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToWrite1Kx32(unsigned int *x) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += i; + *(x++) = sum; + } + return ESP.getCycleCount() - b; +} + + +uint32_t cyclesToRead1Kx16(unsigned short *x, uint32_t *res) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += *(x++); + } + *res = sum; + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToWrite1Kx16(unsigned short *x) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += i; + *(x++) = sum; + } + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToRead1Kx8(unsigned char*x, uint32_t *res) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += *(x++); + } + *res = sum; + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToWrite1Kx8(unsigned char*x) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += i; + *(x++) = sum; + } + return ESP.getCycleCount() - b; +} + +// Compare with Inline + +uint32_t cyclesToRead1Kx16_viaInline(unsigned short *x, uint32_t *res) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += get_uint16_iram(x++); //*(x++); + } + *res = sum; + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToWrite1Kx16_viaInline(unsigned short *x) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += i; + // *(x++) = sum; + set_uint16_iram(x++, sum); + } + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToRead1Kx8_viaInline(unsigned char*x, uint32_t *res) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += get_uint8_iram(x++); //*(x++); + } + *res = sum; + return ESP.getCycleCount() - b; +} + +uint32_t cyclesToWrite1Kx8_viaInline(unsigned char*x) { + uint32_t b = ESP.getCycleCount(); + uint32_t sum = 0; + for (int i = 0; i < 1024; i++) { + sum += i; + // *(x++) = sum; + set_uint8_iram(x++, sum); + } + return ESP.getCycleCount() - b; +} + +void setup() { + WiFi.persistent(false); + WiFi.mode(WIFI_OFF); + // Serial.begin(74880); + Serial.begin(115200); + delay(20); + Serial.printf_P(PSTR("\n\nSetup ...\n")); + + // IRAM Heap Inialized moed to user_init() in core_esp8266_main.cpp + // umm_init_iram(); + + // Compiling with Secondary Heap option VM does not change malloc to use the + // IRAM region. It will continue to use the builtin DRAM until we request + // otherwise. + Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + uint32_t *mem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + Serial.printf("DRAM buffer: Address %p, free %d\n", mem, ESP.getFreeHeap()); + + // Now request from the IRAM heap +#ifdef USE_SET_IRAM_HEAP + ESP.setIramHeap(); + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + uint32_t *imem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); + // Make sure we go back to the DRAM heap for other allocations. Don't forget to ESP.resetHeap()! + ESP.resetHeap(); +#else + uint32_t *imem; + { + HeapSelectIram ephemeral; + // size_t _heap_id = umm_get_current_heap_id(); + // umm_set_heap_by_id(UMM_HEAP_IRAM); + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + imem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); + // umm_set_heap_by_id(_heap_id); + } +#endif + + uint32_t res; + uint32_t t; + t = cyclesToWrite1Kx32(imem); + Serial.printf("IRAM Memory Write: %6d cycles for 4K\n", t); + t = cyclesToWrite1Kx32(mem); + Serial.printf("DRAM Memory Write: %6d cycles for 4K\n", t); + + t = cyclesToRead1Kx32(imem, &res); + Serial.printf_P(PSTR("IRAM Memory Read: %6d cycles for 4K (sum %08x)\n"), t, res); + t = cyclesToRead1Kx32(mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for 4K (sum %08x)\n", t, res); + + t = cyclesToWrite1Kx16((uint16_t*)imem); + Serial.printf("IRAM Memory Write: %6d cycles for 2K by 16\n", t); + t = cyclesToWrite1Kx16_viaInline((uint16_t*)imem); + Serial.printf("IRAM Memory Write Inline: %6d cycles for 2K by 16\n", t); + t = cyclesToWrite1Kx16((uint16_t*)mem); + Serial.printf("DRAM Memory Write: %6d cycles for 2K by 16\n", t); + + t = cyclesToRead1Kx16((uint16_t*)imem, &res); + Serial.printf("IRAM Memory Read: %6d cycles for 2K by 16 (sum %08x)\n", t, res); + t = cyclesToRead1Kx16_viaInline((uint16_t*)imem, &res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for 2K by 16 (sum %08x)\n", t, res); + t = cyclesToRead1Kx16((uint16_t*)mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for 2K by 16 (sum %08x)\n", t, res); + + t = cyclesToWrite1Kx8((uint8_t*)imem); + Serial.printf("IRAM Memory Write: %6d cycles for 1K by 8\n", t); + t = cyclesToWrite1Kx8_viaInline((uint8_t*)imem); + Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 8\n", t); + t = cyclesToWrite1Kx8((uint8_t*)mem); + Serial.printf("DRAM Memory Write: %6d cycles for 1K by 8\n", t); + + t = cyclesToRead1Kx8((uint8_t*)imem, &res); + Serial.printf("IRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + t = cyclesToRead1Kx8_viaInline((uint8_t*)imem, &res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + t = cyclesToRead1Kx8((uint8_t*)mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + +#ifdef USE_SET_IRAM_HEAP + // Let's use IRAM heap to make a big ole' String + ESP.setIramHeap(); + String s = ""; + for (int i = 0; i < 100; i++) { + s += i; + s += ' '; + } + ESP.resetHeap(); + Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + ESP.setIramHeap(); + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + ESP.resetHeap(); + Serial.printf("String: %s\n", s.c_str()); + ESP.setIramHeap(); + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + ESP.resetHeap(); +#else + { + // Let's use IRAM heap to make a big ole' String + HeapSelectIram ephemeral; + String s = ""; + for (int i = 0; i < 100; i++) { + s += i; + s += ' '; + } + { + HeapSelectDram ephemeral; + Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + } + // Back to IRAM + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("String: %s\n", s.c_str()); + } + { + HeapSelectIram ephemeral; + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + } +#endif + + // Note that free/realloc will all use the heap specified when the pointer was created. + // No need to change heaps to delete an object, only to create it. + free(imem); + free(mem); + + Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); +#ifdef USE_SET_IRAM_HEAP + ESP.setIramHeap(); + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + ESP.resetHeap(); +#else + { + HeapSelectIram ephemeral; + Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + } +#endif +} + +void loop() { + +} diff --git a/libraries/esp8266/keywords.txt b/libraries/esp8266/keywords.txt index 902db205c9..41bf19674f 100644 --- a/libraries/esp8266/keywords.txt +++ b/libraries/esp8266/keywords.txt @@ -60,6 +60,11 @@ getResetInfo KEYWORD2 getResetInfoPtr KEYWORD2 eraseConfig KEYWORD2 getCycleCount KEYWORD2 +enableVM KEYWORD2 +setExternalHeap KEYWORD2 +setDramHeap KEYWORD2 +setIramHeap KEYWORD2 +resetHeap KEYWORD2 ####################################### # Constants (LITERAL1) diff --git a/tests/host/common/MockEsp.cpp b/tests/host/common/MockEsp.cpp index c5ca502eda..ad34971189 100644 --- a/tests/host/common/MockEsp.cpp +++ b/tests/host/common/MockEsp.cpp @@ -226,3 +226,15 @@ uint32_t EspClass::getCycleCount() gettimeofday(&t, NULL); return (((uint64_t)t.tv_sec) * 1000000 + t.tv_usec) * (F_CPU / 1000000); } + +void EspClass::setInternalHeap() +{ +} + +void EspClass::setExternalHeap() +{ +} + +void EspClass::resetHeap() +{ +} From 70842dee2012b6dcc708dd8ba0bacfd6c3fc6282 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 2 Mar 2020 14:50:39 -0800 Subject: [PATCH 08/48] Post push CI cleanup. --- cores/esp8266/umm_malloc/umm_local.c | 23 +++++++++++++++---- cores/esp8266/umm_malloc/umm_local.h | 2 +- cores/esp8266/umm_malloc/umm_malloc_cfg.h | 2 +- cores/esp8266/umm_malloc/umm_poison.c | 2 +- libraries/esp8266/examples/MMU48K/MMU48K.ino | 10 ++++---- .../esp8266/examples/irammem/irammem.ino | 2 +- tests/host/common/MockEsp.cpp | 6 ++++- 7 files changed, 33 insertions(+), 14 deletions(-) diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index b20b30779a..ae5f5c6a7c 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -162,14 +162,27 @@ size_t umm_block_size( void ) { #endif #if defined(UMM_STATS) || defined(UMM_STATS_FULL) -// UMM_STATISTICS ummStats; + +#if defined(UMM_POISON_CHECK) || defined(UMM_POISON_CHECK_LITE) + +// Adjustment needed for free_blocks to express the number of bytes that can +// actually be allocated. +#define UMM_OVERHEAD_ADJUST \ + (umm_block_size() + \ + umm_block_size()/2 + \ + UMM_POISON_SIZE_BEFORE + \ + UMM_POISON_SIZE_AFTER + \ + sizeof(UMM_POISONED_BLOCK_LEN_TYPE)) +#else +#define UMM_OVERHEAD_ADJUST (umm_block_size() + umm_block_size()/2) +#endif // Keep complete call path in IRAM size_t umm_free_heap_size_lw( void ) { UMM_INIT_HEAP; umm_heap_context_t *_context = umm_get_current_heap(); - return (size_t)_context->stats.free_blocks * sizeof(umm_block) - umm_block_size() - umm_block_size()/2; + return (size_t)_context->stats.free_blocks * sizeof(umm_block) - UMM_OVERHEAD_ADJUST; } #endif @@ -231,7 +244,7 @@ size_t ICACHE_FLASH_ATTR umm_get_oom_count( void ) { size_t ICACHE_FLASH_ATTR umm_free_heap_size_lw_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return (size_t)_context->stats.free_blocks_min * umm_block_size() - umm_block_size() - umm_block_size()/2; + return (size_t)_context->stats.free_blocks_min * umm_block_size() - UMM_OVERHEAD_ADJUST; } size_t ICACHE_FLASH_ATTR umm_free_heap_size_min_reset( void ) { @@ -242,12 +255,12 @@ size_t ICACHE_FLASH_ATTR umm_free_heap_size_min_reset( void ) { size_t ICACHE_FLASH_ATTR umm_free_heap_size_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return _context->stats.free_blocks_min * umm_block_size() - umm_block_size() - umm_block_size()/2; + return _context->stats.free_blocks_min * umm_block_size() - UMM_OVERHEAD_ADJUST; } size_t ICACHE_FLASH_ATTR umm_free_heap_size_isr_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return _context->stats.free_blocks_isr_min * umm_block_size() - umm_block_size() - umm_block_size()/2; + return _context->stats.free_blocks_isr_min * umm_block_size() - UMM_OVERHEAD_ADJUST; } size_t ICACHE_FLASH_ATTR umm_get_max_alloc_size( void ) { diff --git a/cores/esp8266/umm_malloc/umm_local.h b/cores/esp8266/umm_malloc/umm_local.h index 9a51063145..c16512d2f8 100644 --- a/cores/esp8266/umm_malloc/umm_local.h +++ b/cores/esp8266/umm_malloc/umm_local.h @@ -37,7 +37,7 @@ #if defined(UMM_POISON_CHECK_LITE) -static int check_poison_neighbors( unsigned short cur ); +static int check_poison_neighbors( umm_heap_context_t *_context, unsigned short cur ); #endif diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index 2f083f4746..1b79874d48 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -558,7 +558,7 @@ static inline void _critical_exit(UMM_TIME_STAT *p, uint32_t *saved_ps) { # define POISON_CHECK() 1 # define POISON_CHECK_NEIGHBORS(c) \ do {\ - if(!check_poison_neighbors(c)) \ + if(!check_poison_neighbors(_context, c)) \ panic();\ } while(false) #else diff --git a/cores/esp8266/umm_malloc/umm_poison.c b/cores/esp8266/umm_malloc/umm_poison.c index 38ff3176b9..c091feb959 100644 --- a/cores/esp8266/umm_malloc/umm_poison.c +++ b/cores/esp8266/umm_malloc/umm_poison.c @@ -135,7 +135,7 @@ static void *get_unpoisoned( void *v_ptr ) { umm_heap_context_t *_context = umm_get_ptr_context( v_ptr ); if (NULL == _context) { panic(); - return NULL: + return NULL; } /* Figure out which block we're in. Note the use of truncated division... */ c = (((char *)ptr)-(char *)(&(_context->heap[0])))/sizeof(umm_block); diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 747b209c4f..f61c4db7ac 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -21,17 +21,18 @@ static inline char get ## name(void *o) { \ #if (MMU_IRAM_SIZE > 32*1024) uint32_t gobble[4 * 1024] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); -#endif - -#ifdef MMU_SEC_HEAP +#elif defined(MMU_SEC_HEAP) uint32_t *gobble; size_t gobble_sz; +#else +uint32_t gobble[256] IRAM_ATTR; +constexpr size_t gobble_sz = sizeof(gobble); #endif bool isValid(uint32_t *probe) { bool rc = true; if (NULL == probe) { - ets_uart_printf("\nNULL memory pointer %p ...\n", probe); + ets_uart_printf("\nNULL memory pointer %p ...\n", probe); return false; } @@ -156,6 +157,7 @@ void setup() { } int* nullPointer = NULL; + char *probe_b = (char *)gobble; short *probe_s = (short *)((uintptr_t)gobble); char *probe_c = (char *)0x40110000; diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 3e5f2f696e..e2257b7603 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -1,7 +1,7 @@ /* This sketch assumes you have selected IRAM as a Second Heap from the Arduino IDE tools menu. - */ +*/ #include #include diff --git a/tests/host/common/MockEsp.cpp b/tests/host/common/MockEsp.cpp index ad34971189..e018e7f5c0 100644 --- a/tests/host/common/MockEsp.cpp +++ b/tests/host/common/MockEsp.cpp @@ -227,7 +227,11 @@ uint32_t EspClass::getCycleCount() return (((uint64_t)t.tv_sec) * 1000000 + t.tv_usec) * (F_CPU / 1000000); } -void EspClass::setInternalHeap() +void EspClass::setDramHeap() +{ +} + +void EspClass::setIramHeap() { } From f35290b884eaf9f0e2bb5b29156923ccadfe44a4 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 2 Mar 2020 16:46:14 -0800 Subject: [PATCH 09/48] Cleanup part II --- boards.txt | 68 ++++++++++++++++++++ cores/esp8266/core_esp8266_main.cpp | 2 +- cores/esp8266/mmu_iram.h | 29 +++++---- cores/esp8266/umm_malloc/umm_malloc.cpp | 17 +---- cores/esp8266/umm_malloc/umm_malloc_cfg.h | 5 +- libraries/esp8266/examples/MMU48K/MMU48K.ino | 29 ++++----- tools/boards.txt.py | 6 +- tools/sdk/ld/eagle.flash.16m14m.ld | 2 +- tools/sdk/ld/eagle.flash.16m15m.ld | 2 +- tools/sdk/ld/eagle.flash.1m.ld | 2 +- tools/sdk/ld/eagle.flash.1m128.ld | 2 +- tools/sdk/ld/eagle.flash.1m144.ld | 2 +- tools/sdk/ld/eagle.flash.1m160.ld | 2 +- tools/sdk/ld/eagle.flash.1m192.ld | 2 +- tools/sdk/ld/eagle.flash.1m256.ld | 2 +- tools/sdk/ld/eagle.flash.1m512.ld | 2 +- tools/sdk/ld/eagle.flash.1m64.ld | 2 +- tools/sdk/ld/eagle.flash.2m.ld | 2 +- tools/sdk/ld/eagle.flash.2m128.ld | 2 +- tools/sdk/ld/eagle.flash.2m1m.ld | 2 +- tools/sdk/ld/eagle.flash.2m256.ld | 2 +- tools/sdk/ld/eagle.flash.2m512.ld | 2 +- tools/sdk/ld/eagle.flash.2m64.ld | 2 +- tools/sdk/ld/eagle.flash.4m.ld | 2 +- tools/sdk/ld/eagle.flash.4m1m.ld | 2 +- tools/sdk/ld/eagle.flash.4m2m.ld | 2 +- tools/sdk/ld/eagle.flash.4m3m.ld | 2 +- tools/sdk/ld/eagle.flash.512k.ld | 2 +- tools/sdk/ld/eagle.flash.512k128.ld | 2 +- tools/sdk/ld/eagle.flash.512k32.ld | 2 +- tools/sdk/ld/eagle.flash.512k64.ld | 2 +- tools/sdk/ld/eagle.flash.8m6m.ld | 2 +- tools/sdk/ld/eagle.flash.8m7m.ld | 2 +- 33 files changed, 133 insertions(+), 75 deletions(-) diff --git a/boards.txt b/boards.txt index ee6c347cdf..6e200c545c 100644 --- a/boards.txt +++ b/boards.txt @@ -67,6 +67,8 @@ generic.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) generic.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 generic.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) generic.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +generic.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +generic.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) generic.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 generic.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -552,6 +554,8 @@ esp8285.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) esp8285.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp8285.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp8285.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +esp8285.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +esp8285.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) esp8285.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp8285.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -846,6 +850,8 @@ espduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espduino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espduino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -1048,6 +1054,8 @@ huzzah.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) huzzah.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 huzzah.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) huzzah.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +huzzah.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +huzzah.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) huzzah.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 huzzah.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -1251,6 +1259,8 @@ inventone.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) inventone.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 inventone.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) inventone.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +inventone.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +inventone.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) inventone.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 inventone.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -1454,6 +1464,8 @@ cw01.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) cw01.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 cw01.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) cw01.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +cw01.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +cw01.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) cw01.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 cw01.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -1660,6 +1672,8 @@ espresso_lite_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espresso_lite_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espresso_lite_v1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espresso_lite_v1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -1866,6 +1880,8 @@ espresso_lite_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espresso_lite_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espresso_lite_v2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espresso_lite_v2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -2072,6 +2088,8 @@ phoenix_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) phoenix_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +phoenix_v1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +phoenix_v1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) phoenix_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -2278,6 +2296,8 @@ phoenix_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) phoenix_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +phoenix_v2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +phoenix_v2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) phoenix_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -2484,6 +2504,8 @@ nodemcu.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) nodemcu.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcu.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcu.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +nodemcu.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +nodemcu.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) nodemcu.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcu.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -2687,6 +2709,8 @@ nodemcuv2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) nodemcuv2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcuv2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcuv2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +nodemcuv2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +nodemcuv2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) nodemcuv2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcuv2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -2894,6 +2918,8 @@ modwifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) modwifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 modwifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) modwifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +modwifi.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +modwifi.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) modwifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 modwifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -3117,6 +3143,8 @@ thing.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) thing.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thing.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thing.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +thing.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +thing.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) thing.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thing.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -3320,6 +3348,8 @@ thingdev.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) thingdev.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thingdev.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thingdev.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +thingdev.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +thingdev.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) thingdev.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thingdev.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -3523,6 +3553,8 @@ blynk.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) blynk.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 blynk.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) blynk.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +blynk.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +blynk.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) blynk.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 blynk.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -3726,6 +3758,8 @@ esp210.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) esp210.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp210.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp210.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +esp210.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +esp210.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) esp210.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp210.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -3929,6 +3963,8 @@ d1_mini.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +d1_mini.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -4132,6 +4168,8 @@ d1_mini_pro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini_pro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_pro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_pro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +d1_mini_pro.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini_pro.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini_pro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_pro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -4318,6 +4356,8 @@ d1_mini_lite.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini_lite.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_lite.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_lite.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +d1_mini_lite.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini_lite.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1_mini_lite.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_lite.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -4561,6 +4601,8 @@ d1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +d1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) d1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -4764,6 +4806,8 @@ espino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -4970,6 +5014,8 @@ espinotee.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espinotee.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espinotee.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espinotee.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espinotee.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espinotee.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espinotee.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espinotee.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -5190,6 +5236,8 @@ wifinfo.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifinfo.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifinfo.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifinfo.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +wifinfo.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifinfo.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifinfo.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifinfo.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -5452,6 +5500,8 @@ arduino-esp8266.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) arduino-esp8266.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 arduino-esp8266.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) arduino-esp8266.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +arduino-esp8266.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +arduino-esp8266.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) arduino-esp8266.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 arduino-esp8266.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -5656,6 +5706,8 @@ gen4iod.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) gen4iod.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 gen4iod.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) gen4iod.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +gen4iod.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +gen4iod.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) gen4iod.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 gen4iod.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -5860,6 +5912,8 @@ oak.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) oak.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 oak.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) oak.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +oak.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +oak.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) oak.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 oak.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -6063,6 +6117,8 @@ wifiduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifiduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifiduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifiduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +wifiduino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifiduino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifiduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifiduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -6266,6 +6322,8 @@ wifi_slot.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifi_slot.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifi_slot.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifi_slot.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +wifi_slot.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifi_slot.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wifi_slot.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifi_slot.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -6583,6 +6641,8 @@ wiolink.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wiolink.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wiolink.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wiolink.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +wiolink.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wiolink.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) wiolink.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wiolink.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -6786,6 +6846,8 @@ espectro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espectro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espectro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espectro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espectro.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espectro.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espectro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espectro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -6989,6 +7051,8 @@ eduinowifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) eduinowifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 eduinowifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) eduinowifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +eduinowifi.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +eduinowifi.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP eduinowifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) eduinowifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 eduinowifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -7202,6 +7266,8 @@ sonoff.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) sonoff.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 sonoff.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) sonoff.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +sonoff.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +sonoff.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) sonoff.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 sonoff.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM @@ -7446,6 +7512,8 @@ espmxdevkit.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espmxdevkit.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espmxdevkit.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espmxdevkit.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 +espmxdevkit.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espmxdevkit.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) espmxdevkit.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espmxdevkit.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 0d6c55aebb..8543224e46 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -337,7 +337,7 @@ extern "C" void user_init(void) { #if defined(NON32XFER_HANDLER) || defined(MMU_SEC_HEAP) install_non32xfer_exception_handler(); #endif -#if defined(MMU_SEC_HEAP) +#if defined(MMU_IRAM_HEAP) umm_init_iram(); #endif preinit(); // Prior to C++ Dynamic Init (not related to above init() ). Meant to be user redefinable. diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index e1ca6340ee..82ebbd3e83 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -111,33 +111,36 @@ extern mmu_cre_status_t mmu_status; #ifdef DEBUG_MMU static inline bool is_iram(uint32_t addr) { -constexpr uint32_t _start = 0x40100000UL; +// constexpr uint32_t _start = 0x40100000UL; #define IRAM_START 0x40100000UL #ifndef MMU_IRAM_SIZE -#define MMU_IRAM_SIZE 0x8000 +#define MMU_IRAM_SIZE 0xC000UL #endif #ifdef MMU_SEC_HEAP_SIZE - constexpr uint32_t _end = _start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; + // constexpr uint32_t _end = _start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; #define IRAM_END (IRAM_START + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE) #else - constexpr uint32_t _end = _start + MMU_IRAM_SIZE; + // constexpr uint32_t _end = _start + MMU_IRAM_SIZE; + #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) #endif - return (_start <= addr && _end > addr); + return (IRAM_START <= addr && IRAM_END > addr); } static inline bool is_dram(uint32_t addr) { - constexpr uint32_t _start = 0x3FF80000UL; - constexpr uint32_t _end = 0x40000000; - return (_start <= addr && _end > addr); + // constexpr uint32_t _start = 0x3FF80000UL; + // constexpr uint32_t _end = 0x40000000UL; + return (0x3FF80000UL <= addr && 0x40000000UL > addr); } static inline bool is_icache(uint32_t addr) { - constexpr uint32_t _start = 0x40200000UL; - constexpr uint32_t _end = _start + 0x100000; - return (_start <= addr && _end > addr); + // constexpr uint32_t _start = 0x40200000UL; + // constexpr uint32_t _end = _start + 0x100000UL; + #define ICACHE_START 0x40200000UL + #define ICACHE_END (ICACHE_START + 0x100000UL) + return (ICACHE_START <= addr && ICACHE_END > addr); } #else @@ -162,14 +165,14 @@ static inline bool is_icache(uint32_t addr) { if (is_iram((uint32_t)a) || is_dram((uint32_t)a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ - assert(("Outside of Range Write", false)); \ + assert(("Outside of Range Write" && false)); \ } #define ASSERT_RANGE_TEST_READ(a) \ if (is_iram((uint32_t)a) || is_icache((uint32_t)a) || is_dram((uint32_t)a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ - assert(("Outside of Range Read", false)); \ + assert(("Outside of Range Read" && false)); \ } #else diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 390daf42bb..5c6c1baf7e 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -458,23 +458,12 @@ void _text_end(void); void umm_init_iram(void) __attribute__((weak)); void umm_init_iram(void) { - uint32_t sec_heap = MMU_SEC_HEAP; - size_t sec_heap_sz = MMU_SEC_HEAP_SIZE; - -#ifdef UUM_MERGE_FREE_IRAM_W_SEC_HEAP - // Combine free IRAM from 1st 32K with 16K of Second Heap - uint32_t iram_free = MMU_IRAM_SIZE - (uint32_t)((uintptr_t)_text_end - 0x40100000UL); - iram_free &= ~7; - if (iram_free > 40) { - iram_free -= 32; - sec_heap -= iram_free; - sec_heap_sz += iram_free; - } -#endif + uint32_t sec_heap = (uint32_t)_text_end + 32; + sec_heap &= ~7; + size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); } - #endif // #ifdef UMM_HEAP_IRAM #ifdef UMM_HEAP_EXTERNAL diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index 1b79874d48..e058b4218d 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -23,13 +23,10 @@ extern "C" { #include "c_types.h" -// Combine free IRAM from 1st 32K with 16K of Second Heap -#define UUM_MERGE_FREE_IRAM_W_SEC_HEAP - /* * Define active Heaps */ -#ifdef MMU_SEC_HEAP +#if defined(MMU_IRAM_HEAP) #define UMM_HEAP_IRAM #else #undef UMM_HEAP_IRAM diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index f61c4db7ac..91b10103a1 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -18,12 +18,15 @@ static inline char get ## name(void *o) { \ */ -#if (MMU_IRAM_SIZE > 32*1024) +#if defined(MMU_IRAM_HEAP) +uint32_t *gobble; +size_t gobble_sz; +#elif (MMU_IRAM_SIZE > 32*1024) uint32_t gobble[4 * 1024] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); #elif defined(MMU_SEC_HEAP) -uint32_t *gobble; -size_t gobble_sz; +uint32_t *gobble = (uint32_t *)MMU_SEC_HEAP; +size_t gobble_sz = MMU_SEC_HEAP_SIZE; #else uint32_t gobble[256] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); @@ -126,7 +129,7 @@ void setup() { print_mmu_status(Serial); -#ifdef MMU_SEC_HEAP +#if defined(MMU_IRAM_HEAP) { HeapSelectIram ephemeral; // Serial.printf_P(PSTR("ESP.getFreeHeap(): %u\n"), ESP.getFreeHeap()); @@ -138,7 +141,7 @@ void setup() { #endif -#if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_SEC_HEAP) +#if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_IRAM_HEAP) || defined(MMU_SEC_HEAP) if (isValid(gobble)) { // Put something in our new memory for (size_t i = 0; i < (gobble_sz / 4); i++) { @@ -323,16 +326,12 @@ int divideA_B(int a, int b) { extern "C" void _text_end(void); extern "C" void umm_init_iram(void) { - // Merge free IRAM into Second Heap - uint32_t iram_free = MMU_IRAM_SIZE - (uint32_t)((uintptr_t)_text_end - 0x40100000UL); - uint32_t sec_heap = MMU_SEC_HEAP; - size_t sec_heap_sz = MMU_SEC_HEAP_SIZE; - iram_free &= ~7; - if (iram_free > 40) { - iram_free -= 32; - sec_heap -= iram_free; - sec_heap_sz += iram_free; - } + +void umm_init_iram(void) { + uint32_t sec_heap = (uint32_t)_text_end + 32; + sec_heap &= ~7; + size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); + umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); } #endif diff --git a/tools/boards.txt.py b/tools/boards.txt.py index 55bbe29f8f..688f5942ee 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -955,7 +955,7 @@ }) ]) - + ################################################################ @@ -1215,6 +1215,8 @@ ( '.menu.mmu.3232.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000'), ( '.menu.mmu.4816', '16KB cache + 48KB IRAM (IRAM)' ), ( '.menu.mmu.4816.build.mmuflags', '-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000' ), + ( '.menu.mmu.4816H', '16KB cache + 48KB IRAM (IRAM and Heap)' ), + ( '.menu.mmu.4816H.build.mmuflags', '-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP' ), ( '.menu.mmu.3216', '16KB cache + 32KB IRAM + 16KB sec heap (Heap)' ), ( '.menu.mmu.3216.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000' ), ]), @@ -1397,7 +1399,7 @@ def flash_map (flashsize_kb, fs_kb = 0): print("{") print(" dport0_0_seg : org = 0x3FF00000, len = 0x10") print(" dram0_0_seg : org = 0x3FFE8000, len = 0x14000") - print(" iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE") + print(" iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */") print(" irom0_0_seg : org = 0x40201010, len = 0x%x" % max_upload_size) print("}") print("") diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld b/tools/sdk/ld/eagle.flash.16m14m.ld index 174a4b1c51..09f8831f33 100644 --- a/tools/sdk/ld/eagle.flash.16m14m.ld +++ b/tools/sdk/ld/eagle.flash.16m14m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld b/tools/sdk/ld/eagle.flash.16m15m.ld index 011280a498..4997825f8f 100644 --- a/tools/sdk/ld/eagle.flash.16m15m.ld +++ b/tools/sdk/ld/eagle.flash.16m15m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.1m.ld b/tools/sdk/ld/eagle.flash.1m.ld index 81cc98ef87..fcc99e01e6 100644 --- a/tools/sdk/ld/eagle.flash.1m.ld +++ b/tools/sdk/ld/eagle.flash.1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xf9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m128.ld b/tools/sdk/ld/eagle.flash.1m128.ld index 0bd9c3b0f6..1f3de948f6 100644 --- a/tools/sdk/ld/eagle.flash.1m128.ld +++ b/tools/sdk/ld/eagle.flash.1m128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m144.ld b/tools/sdk/ld/eagle.flash.1m144.ld index 8e1601fa25..104b86b113 100644 --- a/tools/sdk/ld/eagle.flash.1m144.ld +++ b/tools/sdk/ld/eagle.flash.1m144.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd5ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m160.ld b/tools/sdk/ld/eagle.flash.1m160.ld index 2295f7ad47..c8b36df628 100644 --- a/tools/sdk/ld/eagle.flash.1m160.ld +++ b/tools/sdk/ld/eagle.flash.1m160.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd1ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m192.ld b/tools/sdk/ld/eagle.flash.1m192.ld index 77b136074a..e926c49b13 100644 --- a/tools/sdk/ld/eagle.flash.1m192.ld +++ b/tools/sdk/ld/eagle.flash.1m192.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xc9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m256.ld b/tools/sdk/ld/eagle.flash.1m256.ld index 8e0517c9f3..73c9a9de91 100644 --- a/tools/sdk/ld/eagle.flash.1m256.ld +++ b/tools/sdk/ld/eagle.flash.1m256.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xb9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m512.ld b/tools/sdk/ld/eagle.flash.1m512.ld index 39c5bf7b4d..a2416eea49 100644 --- a/tools/sdk/ld/eagle.flash.1m512.ld +++ b/tools/sdk/ld/eagle.flash.1m512.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m64.ld b/tools/sdk/ld/eagle.flash.1m64.ld index 428eba4550..d7a4adee03 100644 --- a/tools/sdk/ld/eagle.flash.1m64.ld +++ b/tools/sdk/ld/eagle.flash.1m64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xe9ff0 } diff --git a/tools/sdk/ld/eagle.flash.2m.ld b/tools/sdk/ld/eagle.flash.2m.ld index 148939d978..2c047273c3 100644 --- a/tools/sdk/ld/eagle.flash.2m.ld +++ b/tools/sdk/ld/eagle.flash.2m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m128.ld b/tools/sdk/ld/eagle.flash.2m128.ld index 86ac5acf96..4dfbd14810 100644 --- a/tools/sdk/ld/eagle.flash.2m128.ld +++ b/tools/sdk/ld/eagle.flash.2m128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld b/tools/sdk/ld/eagle.flash.2m1m.ld index 7b9d72f568..c3b4444b5f 100644 --- a/tools/sdk/ld/eagle.flash.2m1m.ld +++ b/tools/sdk/ld/eagle.flash.2m1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m256.ld b/tools/sdk/ld/eagle.flash.2m256.ld index 7330204bda..186d368bfb 100644 --- a/tools/sdk/ld/eagle.flash.2m256.ld +++ b/tools/sdk/ld/eagle.flash.2m256.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m512.ld b/tools/sdk/ld/eagle.flash.2m512.ld index a2fe0b1a59..106e46008c 100644 --- a/tools/sdk/ld/eagle.flash.2m512.ld +++ b/tools/sdk/ld/eagle.flash.2m512.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m64.ld b/tools/sdk/ld/eagle.flash.2m64.ld index cbec1093c9..61bd0f2f9d 100644 --- a/tools/sdk/ld/eagle.flash.2m64.ld +++ b/tools/sdk/ld/eagle.flash.2m64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m.ld b/tools/sdk/ld/eagle.flash.4m.ld index b90edca998..92d2bc54cf 100644 --- a/tools/sdk/ld/eagle.flash.4m.ld +++ b/tools/sdk/ld/eagle.flash.4m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld b/tools/sdk/ld/eagle.flash.4m1m.ld index 408ff297e2..c8c78c4bb2 100644 --- a/tools/sdk/ld/eagle.flash.4m1m.ld +++ b/tools/sdk/ld/eagle.flash.4m1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld b/tools/sdk/ld/eagle.flash.4m2m.ld index 5122bf2f2f..4a3d600f53 100644 --- a/tools/sdk/ld/eagle.flash.4m2m.ld +++ b/tools/sdk/ld/eagle.flash.4m2m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld b/tools/sdk/ld/eagle.flash.4m3m.ld index ef1753f0a1..89aada7082 100644 --- a/tools/sdk/ld/eagle.flash.4m3m.ld +++ b/tools/sdk/ld/eagle.flash.4m3m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.512k.ld b/tools/sdk/ld/eagle.flash.512k.ld index 977b2346be..71c3f13378 100644 --- a/tools/sdk/ld/eagle.flash.512k.ld +++ b/tools/sdk/ld/eagle.flash.512k.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k128.ld b/tools/sdk/ld/eagle.flash.512k128.ld index a474e33920..3ddad01e8a 100644 --- a/tools/sdk/ld/eagle.flash.512k128.ld +++ b/tools/sdk/ld/eagle.flash.512k128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x59ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k32.ld b/tools/sdk/ld/eagle.flash.512k32.ld index b829917da8..45189f0055 100644 --- a/tools/sdk/ld/eagle.flash.512k32.ld +++ b/tools/sdk/ld/eagle.flash.512k32.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x71ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k64.ld b/tools/sdk/ld/eagle.flash.512k64.ld index 24ea7f69fe..0c6bd93069 100644 --- a/tools/sdk/ld/eagle.flash.512k64.ld +++ b/tools/sdk/ld/eagle.flash.512k64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x69ff0 } diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld b/tools/sdk/ld/eagle.flash.8m6m.ld index c6eadba876..f995cde7aa 100644 --- a/tools/sdk/ld/eagle.flash.8m6m.ld +++ b/tools/sdk/ld/eagle.flash.8m6m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld b/tools/sdk/ld/eagle.flash.8m7m.ld index 196aed5ecc..1aa72b2332 100644 --- a/tools/sdk/ld/eagle.flash.8m7m.ld +++ b/tools/sdk/ld/eagle.flash.8m7m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } From 71e36cbeabc5ceaa7874da8c78a1ba7036b14ac9 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 2 Mar 2020 19:16:44 -0800 Subject: [PATCH 10/48] Cleanup part III --- libraries/esp8266/examples/MMU48K/MMU48K.ino | 2 -- tools/boards.txt.py | 2 +- tools/sdk/ld/eagle.flash.16m14m.ld | 2 +- tools/sdk/ld/eagle.flash.16m15m.ld | 2 +- tools/sdk/ld/eagle.flash.1m.ld | 2 +- tools/sdk/ld/eagle.flash.1m128.ld | 2 +- tools/sdk/ld/eagle.flash.1m144.ld | 2 +- tools/sdk/ld/eagle.flash.1m160.ld | 2 +- tools/sdk/ld/eagle.flash.1m192.ld | 2 +- tools/sdk/ld/eagle.flash.1m256.ld | 2 +- tools/sdk/ld/eagle.flash.1m512.ld | 2 +- tools/sdk/ld/eagle.flash.1m64.ld | 2 +- tools/sdk/ld/eagle.flash.2m.ld | 2 +- tools/sdk/ld/eagle.flash.2m128.ld | 2 +- tools/sdk/ld/eagle.flash.2m1m.ld | 2 +- tools/sdk/ld/eagle.flash.2m256.ld | 2 +- tools/sdk/ld/eagle.flash.2m512.ld | 2 +- tools/sdk/ld/eagle.flash.2m64.ld | 2 +- tools/sdk/ld/eagle.flash.4m.ld | 2 +- tools/sdk/ld/eagle.flash.4m1m.ld | 2 +- tools/sdk/ld/eagle.flash.4m2m.ld | 2 +- tools/sdk/ld/eagle.flash.4m3m.ld | 2 +- tools/sdk/ld/eagle.flash.512k.ld | 2 +- tools/sdk/ld/eagle.flash.512k128.ld | 2 +- tools/sdk/ld/eagle.flash.512k32.ld | 2 +- tools/sdk/ld/eagle.flash.512k64.ld | 2 +- tools/sdk/ld/eagle.flash.8m6m.ld | 2 +- tools/sdk/ld/eagle.flash.8m7m.ld | 2 +- 28 files changed, 27 insertions(+), 29 deletions(-) diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 91b10103a1..bfda4d79cf 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -326,8 +326,6 @@ int divideA_B(int a, int b) { extern "C" void _text_end(void); extern "C" void umm_init_iram(void) { - -void umm_init_iram(void) { uint32_t sec_heap = (uint32_t)_text_end + 32; sec_heap &= ~7; size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); diff --git a/tools/boards.txt.py b/tools/boards.txt.py index 688f5942ee..2aea09bfaa 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1399,7 +1399,7 @@ def flash_map (flashsize_kb, fs_kb = 0): print("{") print(" dport0_0_seg : org = 0x3FF00000, len = 0x10") print(" dram0_0_seg : org = 0x3FFE8000, len = 0x14000") - print(" iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */") + print(" iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */") print(" irom0_0_seg : org = 0x40201010, len = 0x%x" % max_upload_size) print("}") print("") diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld b/tools/sdk/ld/eagle.flash.16m14m.ld index 09f8831f33..2b967fc2b0 100644 --- a/tools/sdk/ld/eagle.flash.16m14m.ld +++ b/tools/sdk/ld/eagle.flash.16m14m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld b/tools/sdk/ld/eagle.flash.16m15m.ld index 4997825f8f..124b2f8dac 100644 --- a/tools/sdk/ld/eagle.flash.16m15m.ld +++ b/tools/sdk/ld/eagle.flash.16m15m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.1m.ld b/tools/sdk/ld/eagle.flash.1m.ld index fcc99e01e6..4aba05d6a8 100644 --- a/tools/sdk/ld/eagle.flash.1m.ld +++ b/tools/sdk/ld/eagle.flash.1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xf9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m128.ld b/tools/sdk/ld/eagle.flash.1m128.ld index 1f3de948f6..9dc5b23e33 100644 --- a/tools/sdk/ld/eagle.flash.1m128.ld +++ b/tools/sdk/ld/eagle.flash.1m128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m144.ld b/tools/sdk/ld/eagle.flash.1m144.ld index 104b86b113..1edfe7bd22 100644 --- a/tools/sdk/ld/eagle.flash.1m144.ld +++ b/tools/sdk/ld/eagle.flash.1m144.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd5ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m160.ld b/tools/sdk/ld/eagle.flash.1m160.ld index c8b36df628..df1c19646c 100644 --- a/tools/sdk/ld/eagle.flash.1m160.ld +++ b/tools/sdk/ld/eagle.flash.1m160.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd1ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m192.ld b/tools/sdk/ld/eagle.flash.1m192.ld index e926c49b13..8ddafc4695 100644 --- a/tools/sdk/ld/eagle.flash.1m192.ld +++ b/tools/sdk/ld/eagle.flash.1m192.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xc9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m256.ld b/tools/sdk/ld/eagle.flash.1m256.ld index 73c9a9de91..835ab6fdf8 100644 --- a/tools/sdk/ld/eagle.flash.1m256.ld +++ b/tools/sdk/ld/eagle.flash.1m256.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xb9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m512.ld b/tools/sdk/ld/eagle.flash.1m512.ld index a2416eea49..387961cde6 100644 --- a/tools/sdk/ld/eagle.flash.1m512.ld +++ b/tools/sdk/ld/eagle.flash.1m512.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m64.ld b/tools/sdk/ld/eagle.flash.1m64.ld index d7a4adee03..24fc53c23d 100644 --- a/tools/sdk/ld/eagle.flash.1m64.ld +++ b/tools/sdk/ld/eagle.flash.1m64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xe9ff0 } diff --git a/tools/sdk/ld/eagle.flash.2m.ld b/tools/sdk/ld/eagle.flash.2m.ld index 2c047273c3..7494bcd874 100644 --- a/tools/sdk/ld/eagle.flash.2m.ld +++ b/tools/sdk/ld/eagle.flash.2m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m128.ld b/tools/sdk/ld/eagle.flash.2m128.ld index 4dfbd14810..330748bcc9 100644 --- a/tools/sdk/ld/eagle.flash.2m128.ld +++ b/tools/sdk/ld/eagle.flash.2m128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld b/tools/sdk/ld/eagle.flash.2m1m.ld index c3b4444b5f..7d768d9d12 100644 --- a/tools/sdk/ld/eagle.flash.2m1m.ld +++ b/tools/sdk/ld/eagle.flash.2m1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m256.ld b/tools/sdk/ld/eagle.flash.2m256.ld index 186d368bfb..b9b60305a6 100644 --- a/tools/sdk/ld/eagle.flash.2m256.ld +++ b/tools/sdk/ld/eagle.flash.2m256.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m512.ld b/tools/sdk/ld/eagle.flash.2m512.ld index 106e46008c..558aa38782 100644 --- a/tools/sdk/ld/eagle.flash.2m512.ld +++ b/tools/sdk/ld/eagle.flash.2m512.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m64.ld b/tools/sdk/ld/eagle.flash.2m64.ld index 61bd0f2f9d..615c109c1b 100644 --- a/tools/sdk/ld/eagle.flash.2m64.ld +++ b/tools/sdk/ld/eagle.flash.2m64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m.ld b/tools/sdk/ld/eagle.flash.4m.ld index 92d2bc54cf..0894518385 100644 --- a/tools/sdk/ld/eagle.flash.4m.ld +++ b/tools/sdk/ld/eagle.flash.4m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld b/tools/sdk/ld/eagle.flash.4m1m.ld index c8c78c4bb2..9a9ec54fed 100644 --- a/tools/sdk/ld/eagle.flash.4m1m.ld +++ b/tools/sdk/ld/eagle.flash.4m1m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld b/tools/sdk/ld/eagle.flash.4m2m.ld index 4a3d600f53..f0a5d34835 100644 --- a/tools/sdk/ld/eagle.flash.4m2m.ld +++ b/tools/sdk/ld/eagle.flash.4m2m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld b/tools/sdk/ld/eagle.flash.4m3m.ld index 89aada7082..056d836655 100644 --- a/tools/sdk/ld/eagle.flash.4m3m.ld +++ b/tools/sdk/ld/eagle.flash.4m3m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.512k.ld b/tools/sdk/ld/eagle.flash.512k.ld index 71c3f13378..3c36174bee 100644 --- a/tools/sdk/ld/eagle.flash.512k.ld +++ b/tools/sdk/ld/eagle.flash.512k.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k128.ld b/tools/sdk/ld/eagle.flash.512k128.ld index 3ddad01e8a..1eac5d5f9c 100644 --- a/tools/sdk/ld/eagle.flash.512k128.ld +++ b/tools/sdk/ld/eagle.flash.512k128.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x59ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k32.ld b/tools/sdk/ld/eagle.flash.512k32.ld index 45189f0055..65500df59d 100644 --- a/tools/sdk/ld/eagle.flash.512k32.ld +++ b/tools/sdk/ld/eagle.flash.512k32.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x71ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k64.ld b/tools/sdk/ld/eagle.flash.512k64.ld index 0c6bd93069..c773b80647 100644 --- a/tools/sdk/ld/eagle.flash.512k64.ld +++ b/tools/sdk/ld/eagle.flash.512k64.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x69ff0 } diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld b/tools/sdk/ld/eagle.flash.8m6m.ld index f995cde7aa..38fe7c13b6 100644 --- a/tools/sdk/ld/eagle.flash.8m6m.ld +++ b/tools/sdk/ld/eagle.flash.8m6m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld b/tools/sdk/ld/eagle.flash.8m7m.ld index 1aa72b2332..c752cdae60 100644 --- a/tools/sdk/ld/eagle.flash.8m7m.ld +++ b/tools/sdk/ld/eagle.flash.8m7m.ld @@ -10,7 +10,7 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: IRAM_SIZE */ + iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } From edf008abff8fde195337f0ad069f645ad54b1e91 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 4 Mar 2020 19:30:41 -0800 Subject: [PATCH 11/48] Updates to support platformio, maybe. --- boards.txt | 136 +++++++++++++------------- tools/boards.txt.py | 7 +- tools/sdk/ld/eagle.app.v6.common.ld.h | 11 ++- tools/sdk/ld/eagle.flash.16m14m.ld | 1 - tools/sdk/ld/eagle.flash.16m15m.ld | 1 - tools/sdk/ld/eagle.flash.1m.ld | 1 - tools/sdk/ld/eagle.flash.1m128.ld | 1 - tools/sdk/ld/eagle.flash.1m144.ld | 1 - tools/sdk/ld/eagle.flash.1m160.ld | 1 - tools/sdk/ld/eagle.flash.1m192.ld | 1 - tools/sdk/ld/eagle.flash.1m256.ld | 1 - tools/sdk/ld/eagle.flash.1m512.ld | 1 - tools/sdk/ld/eagle.flash.1m64.ld | 1 - tools/sdk/ld/eagle.flash.2m.ld | 1 - tools/sdk/ld/eagle.flash.2m128.ld | 1 - tools/sdk/ld/eagle.flash.2m1m.ld | 1 - tools/sdk/ld/eagle.flash.2m256.ld | 1 - tools/sdk/ld/eagle.flash.2m512.ld | 1 - tools/sdk/ld/eagle.flash.2m64.ld | 1 - tools/sdk/ld/eagle.flash.4m.ld | 1 - tools/sdk/ld/eagle.flash.4m1m.ld | 1 - tools/sdk/ld/eagle.flash.4m2m.ld | 1 - tools/sdk/ld/eagle.flash.4m3m.ld | 1 - tools/sdk/ld/eagle.flash.512k.ld | 1 - tools/sdk/ld/eagle.flash.512k128.ld | 1 - tools/sdk/ld/eagle.flash.512k32.ld | 1 - tools/sdk/ld/eagle.flash.512k64.ld | 1 - tools/sdk/ld/eagle.flash.8m6m.ld | 1 - tools/sdk/ld/eagle.flash.8m7m.ld | 1 - tools/sdk/ld/eagle.rom.addr.v6.ld | 5 + 30 files changed, 87 insertions(+), 98 deletions(-) diff --git a/boards.txt b/boards.txt index 6e200c545c..e6ba49c9e7 100644 --- a/boards.txt +++ b/boards.txt @@ -67,9 +67,9 @@ generic.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) generic.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 generic.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) generic.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -generic.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +generic.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) generic.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +generic.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) generic.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 generic.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM generic.menu.non32xfer.fast.build.non32xferflags= @@ -554,9 +554,9 @@ esp8285.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) esp8285.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp8285.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp8285.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -esp8285.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +esp8285.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) esp8285.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +esp8285.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) esp8285.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp8285.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM esp8285.menu.non32xfer.fast.build.non32xferflags= @@ -850,9 +850,9 @@ espduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espduino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espduino.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espduino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espduino.menu.non32xfer.fast.build.non32xferflags= @@ -1054,9 +1054,9 @@ huzzah.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) huzzah.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 huzzah.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) huzzah.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -huzzah.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +huzzah.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) huzzah.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +huzzah.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) huzzah.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 huzzah.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM huzzah.menu.non32xfer.fast.build.non32xferflags= @@ -1259,9 +1259,9 @@ inventone.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) inventone.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 inventone.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) inventone.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -inventone.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +inventone.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) inventone.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +inventone.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) inventone.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 inventone.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM inventone.menu.non32xfer.fast.build.non32xferflags= @@ -1464,9 +1464,9 @@ cw01.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) cw01.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 cw01.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) cw01.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -cw01.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +cw01.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) cw01.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +cw01.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) cw01.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 cw01.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM cw01.menu.non32xfer.fast.build.non32xferflags= @@ -1672,9 +1672,9 @@ espresso_lite_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espresso_lite_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espresso_lite_v1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espresso_lite_v1.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espresso_lite_v1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espresso_lite_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espresso_lite_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espresso_lite_v1.menu.non32xfer.fast.build.non32xferflags= @@ -1880,9 +1880,9 @@ espresso_lite_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espresso_lite_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espresso_lite_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espresso_lite_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espresso_lite_v2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espresso_lite_v2.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espresso_lite_v2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espresso_lite_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espresso_lite_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espresso_lite_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espresso_lite_v2.menu.non32xfer.fast.build.non32xferflags= @@ -2088,9 +2088,9 @@ phoenix_v1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) phoenix_v1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -phoenix_v1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +phoenix_v1.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) phoenix_v1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +phoenix_v1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) phoenix_v1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM phoenix_v1.menu.non32xfer.fast.build.non32xferflags= @@ -2296,9 +2296,9 @@ phoenix_v2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) phoenix_v2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 phoenix_v2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) phoenix_v2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -phoenix_v2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +phoenix_v2.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) phoenix_v2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +phoenix_v2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) phoenix_v2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 phoenix_v2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM phoenix_v2.menu.non32xfer.fast.build.non32xferflags= @@ -2504,9 +2504,9 @@ nodemcu.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) nodemcu.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcu.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcu.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -nodemcu.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +nodemcu.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) nodemcu.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +nodemcu.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) nodemcu.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcu.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM nodemcu.menu.non32xfer.fast.build.non32xferflags= @@ -2709,9 +2709,9 @@ nodemcuv2.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) nodemcuv2.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 nodemcuv2.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) nodemcuv2.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -nodemcuv2.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +nodemcuv2.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) nodemcuv2.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +nodemcuv2.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) nodemcuv2.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 nodemcuv2.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM nodemcuv2.menu.non32xfer.fast.build.non32xferflags= @@ -2918,9 +2918,9 @@ modwifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) modwifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 modwifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) modwifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -modwifi.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +modwifi.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) modwifi.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +modwifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) modwifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 modwifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM modwifi.menu.non32xfer.fast.build.non32xferflags= @@ -3143,9 +3143,9 @@ thing.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) thing.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thing.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thing.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -thing.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +thing.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) thing.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +thing.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) thing.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thing.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM thing.menu.non32xfer.fast.build.non32xferflags= @@ -3348,9 +3348,9 @@ thingdev.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) thingdev.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 thingdev.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) thingdev.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -thingdev.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +thingdev.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) thingdev.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +thingdev.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) thingdev.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 thingdev.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM thingdev.menu.non32xfer.fast.build.non32xferflags= @@ -3553,9 +3553,9 @@ blynk.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) blynk.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 blynk.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) blynk.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -blynk.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +blynk.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) blynk.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +blynk.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) blynk.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 blynk.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM blynk.menu.non32xfer.fast.build.non32xferflags= @@ -3758,9 +3758,9 @@ esp210.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) esp210.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 esp210.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) esp210.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -esp210.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +esp210.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) esp210.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +esp210.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) esp210.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 esp210.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM esp210.menu.non32xfer.fast.build.non32xferflags= @@ -3963,9 +3963,9 @@ d1_mini.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -d1_mini.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) d1_mini.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) d1_mini.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM d1_mini.menu.non32xfer.fast.build.non32xferflags= @@ -4168,9 +4168,9 @@ d1_mini_pro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini_pro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_pro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_pro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -d1_mini_pro.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini_pro.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) d1_mini_pro.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini_pro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) d1_mini_pro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_pro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM d1_mini_pro.menu.non32xfer.fast.build.non32xferflags= @@ -4356,9 +4356,9 @@ d1_mini_lite.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1_mini_lite.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1_mini_lite.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1_mini_lite.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -d1_mini_lite.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1_mini_lite.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) d1_mini_lite.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1_mini_lite.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) d1_mini_lite.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1_mini_lite.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM d1_mini_lite.menu.non32xfer.fast.build.non32xferflags= @@ -4601,9 +4601,9 @@ d1.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) d1.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 d1.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) d1.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -d1.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +d1.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) d1.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +d1.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) d1.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 d1.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM d1.menu.non32xfer.fast.build.non32xferflags= @@ -4806,9 +4806,9 @@ espino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espino.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espino.menu.non32xfer.fast.build.non32xferflags= @@ -5014,9 +5014,9 @@ espinotee.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espinotee.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espinotee.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espinotee.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espinotee.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espinotee.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espinotee.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espinotee.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espinotee.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espinotee.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espinotee.menu.non32xfer.fast.build.non32xferflags= @@ -5236,9 +5236,9 @@ wifinfo.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifinfo.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifinfo.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifinfo.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -wifinfo.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifinfo.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) wifinfo.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifinfo.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) wifinfo.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifinfo.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM wifinfo.menu.non32xfer.fast.build.non32xferflags= @@ -5500,9 +5500,9 @@ arduino-esp8266.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) arduino-esp8266.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 arduino-esp8266.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) arduino-esp8266.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -arduino-esp8266.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +arduino-esp8266.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) arduino-esp8266.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +arduino-esp8266.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) arduino-esp8266.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 arduino-esp8266.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM arduino-esp8266.menu.non32xfer.fast.build.non32xferflags= @@ -5706,9 +5706,9 @@ gen4iod.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) gen4iod.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 gen4iod.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) gen4iod.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -gen4iod.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +gen4iod.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) gen4iod.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +gen4iod.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) gen4iod.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 gen4iod.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM gen4iod.menu.non32xfer.fast.build.non32xferflags= @@ -5912,9 +5912,9 @@ oak.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) oak.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 oak.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) oak.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -oak.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +oak.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) oak.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +oak.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) oak.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 oak.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM oak.menu.non32xfer.fast.build.non32xferflags= @@ -6117,9 +6117,9 @@ wifiduino.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifiduino.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifiduino.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifiduino.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -wifiduino.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifiduino.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) wifiduino.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifiduino.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) wifiduino.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifiduino.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM wifiduino.menu.non32xfer.fast.build.non32xferflags= @@ -6322,9 +6322,9 @@ wifi_slot.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wifi_slot.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wifi_slot.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wifi_slot.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -wifi_slot.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wifi_slot.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) wifi_slot.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wifi_slot.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) wifi_slot.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wifi_slot.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM wifi_slot.menu.non32xfer.fast.build.non32xferflags= @@ -6641,9 +6641,9 @@ wiolink.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) wiolink.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 wiolink.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) wiolink.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -wiolink.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +wiolink.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) wiolink.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +wiolink.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) wiolink.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 wiolink.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM wiolink.menu.non32xfer.fast.build.non32xferflags= @@ -6846,9 +6846,9 @@ espectro.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espectro.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espectro.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espectro.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espectro.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espectro.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espectro.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espectro.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espectro.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espectro.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espectro.menu.non32xfer.fast.build.non32xferflags= @@ -7051,9 +7051,9 @@ eduinowifi.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) eduinowifi.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 eduinowifi.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) eduinowifi.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -eduinowifi.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +eduinowifi.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) eduinowifi.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -eduinowifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +eduinowifi.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) eduinowifi.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 eduinowifi.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM eduinowifi.menu.non32xfer.fast.build.non32xferflags= @@ -7266,9 +7266,9 @@ sonoff.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) sonoff.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 sonoff.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) sonoff.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -sonoff.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +sonoff.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) sonoff.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +sonoff.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) sonoff.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 sonoff.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM sonoff.menu.non32xfer.fast.build.non32xferflags= @@ -7512,9 +7512,9 @@ espmxdevkit.menu.mmu.3232=32KB cache + 32KB IRAM (balanced) espmxdevkit.menu.mmu.3232.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000 espmxdevkit.menu.mmu.4816=16KB cache + 48KB IRAM (IRAM) espmxdevkit.menu.mmu.4816.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -espmxdevkit.menu.mmu.4816H=16KB cache + 48KB IRAM (IRAM and Heap) +espmxdevkit.menu.mmu.4816H=16KB cache + 48KB IRAM and 2nd Heap (shared) espmxdevkit.menu.mmu.4816H.build.mmuflags=-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP -espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB sec heap (Heap) +espmxdevkit.menu.mmu.3216=16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared) espmxdevkit.menu.mmu.3216.build.mmuflags=-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000 espmxdevkit.menu.non32xfer.fast=Use pgm_read macros for IRAM/PROGMEM espmxdevkit.menu.non32xfer.fast.build.non32xferflags= diff --git a/tools/boards.txt.py b/tools/boards.txt.py index 2aea09bfaa..63a2835cc7 100755 --- a/tools/boards.txt.py +++ b/tools/boards.txt.py @@ -1215,9 +1215,9 @@ ( '.menu.mmu.3232.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x8000'), ( '.menu.mmu.4816', '16KB cache + 48KB IRAM (IRAM)' ), ( '.menu.mmu.4816.build.mmuflags', '-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000' ), - ( '.menu.mmu.4816H', '16KB cache + 48KB IRAM (IRAM and Heap)' ), + ( '.menu.mmu.4816H', '16KB cache + 48KB IRAM and 2nd Heap (shared)' ), ( '.menu.mmu.4816H.build.mmuflags', '-DMMU_IRAM_SIZE=0xC000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_IRAM_HEAP' ), - ( '.menu.mmu.3216', '16KB cache + 32KB IRAM + 16KB sec heap (Heap)' ), + ( '.menu.mmu.3216', '16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared)' ), ( '.menu.mmu.3216.build.mmuflags', '-DMMU_IRAM_SIZE=0x8000 -DMMU_ICACHE_SIZE=0x4000 -DMMU_SEC_HEAP=0x40108000 -DMMU_SEC_HEAP_SIZE=0x4000' ), ]), @@ -1399,7 +1399,8 @@ def flash_map (flashsize_kb, fs_kb = 0): print("{") print(" dport0_0_seg : org = 0x3FF00000, len = 0x10") print(" dram0_0_seg : org = 0x3FFE8000, len = 0x14000") - print(" iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */") + # Moved to ld/eagle.app.v6.common.ld.h as a 2nd MEMORY command. + # print(" iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE") print(" irom0_0_seg : org = 0x40201010, len = 0x%x" % max_upload_size) print("}") print("") diff --git a/tools/sdk/ld/eagle.app.v6.common.ld.h b/tools/sdk/ld/eagle.app.v6.common.ld.h index 383154e491..1d184466be 100644 --- a/tools/sdk/ld/eagle.app.v6.common.ld.h +++ b/tools/sdk/ld/eagle.app.v6.common.ld.h @@ -1,6 +1,15 @@ /* This linker script generated from xt-genldscripts.tpp for LSP . */ /* Linker Script for ld -N */ +/* The restriction to one MEMORY command, appears to be a restriction in + past versions. https://stackoverflow.com/a/55673816 + This 2nd MEMORY command appears to work fine. +*/ +MEMORY +{ + iram1_0_seg : org = 0x40100000, len = MMU_IRAM_SIZE +} + PHDRS { dport0_0_phdr PT_LOAD; @@ -88,7 +97,7 @@ SECTIONS { *(.noinit) } >dram0_0_seg :dram0_0_phdr - + #ifdef VTABLES_IN_DRAM #include "eagle.app.v6.common.ld.vtables.h" #endif diff --git a/tools/sdk/ld/eagle.flash.16m14m.ld b/tools/sdk/ld/eagle.flash.16m14m.ld index 2b967fc2b0..13c1243fef 100644 --- a/tools/sdk/ld/eagle.flash.16m14m.ld +++ b/tools/sdk/ld/eagle.flash.16m14m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.16m15m.ld b/tools/sdk/ld/eagle.flash.16m15m.ld index 124b2f8dac..ad689f0e9f 100644 --- a/tools/sdk/ld/eagle.flash.16m15m.ld +++ b/tools/sdk/ld/eagle.flash.16m15m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.1m.ld b/tools/sdk/ld/eagle.flash.1m.ld index 4aba05d6a8..65c4e06ac5 100644 --- a/tools/sdk/ld/eagle.flash.1m.ld +++ b/tools/sdk/ld/eagle.flash.1m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xf9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m128.ld b/tools/sdk/ld/eagle.flash.1m128.ld index 9dc5b23e33..26de470135 100644 --- a/tools/sdk/ld/eagle.flash.1m128.ld +++ b/tools/sdk/ld/eagle.flash.1m128.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m144.ld b/tools/sdk/ld/eagle.flash.1m144.ld index 1edfe7bd22..cb3df4da48 100644 --- a/tools/sdk/ld/eagle.flash.1m144.ld +++ b/tools/sdk/ld/eagle.flash.1m144.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd5ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m160.ld b/tools/sdk/ld/eagle.flash.1m160.ld index df1c19646c..b4a26c4a78 100644 --- a/tools/sdk/ld/eagle.flash.1m160.ld +++ b/tools/sdk/ld/eagle.flash.1m160.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xd1ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m192.ld b/tools/sdk/ld/eagle.flash.1m192.ld index 8ddafc4695..0999e501da 100644 --- a/tools/sdk/ld/eagle.flash.1m192.ld +++ b/tools/sdk/ld/eagle.flash.1m192.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xc9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m256.ld b/tools/sdk/ld/eagle.flash.1m256.ld index 835ab6fdf8..1e07141235 100644 --- a/tools/sdk/ld/eagle.flash.1m256.ld +++ b/tools/sdk/ld/eagle.flash.1m256.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xb9ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m512.ld b/tools/sdk/ld/eagle.flash.1m512.ld index 387961cde6..1e3b42f1b3 100644 --- a/tools/sdk/ld/eagle.flash.1m512.ld +++ b/tools/sdk/ld/eagle.flash.1m512.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.1m64.ld b/tools/sdk/ld/eagle.flash.1m64.ld index 24fc53c23d..9fa4bae54a 100644 --- a/tools/sdk/ld/eagle.flash.1m64.ld +++ b/tools/sdk/ld/eagle.flash.1m64.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xe9ff0 } diff --git a/tools/sdk/ld/eagle.flash.2m.ld b/tools/sdk/ld/eagle.flash.2m.ld index 7494bcd874..125f20278b 100644 --- a/tools/sdk/ld/eagle.flash.2m.ld +++ b/tools/sdk/ld/eagle.flash.2m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m128.ld b/tools/sdk/ld/eagle.flash.2m128.ld index 330748bcc9..e15a7896f1 100644 --- a/tools/sdk/ld/eagle.flash.2m128.ld +++ b/tools/sdk/ld/eagle.flash.2m128.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m1m.ld b/tools/sdk/ld/eagle.flash.2m1m.ld index 7d768d9d12..1190e54d74 100644 --- a/tools/sdk/ld/eagle.flash.2m1m.ld +++ b/tools/sdk/ld/eagle.flash.2m1m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m256.ld b/tools/sdk/ld/eagle.flash.2m256.ld index b9b60305a6..51259864e7 100644 --- a/tools/sdk/ld/eagle.flash.2m256.ld +++ b/tools/sdk/ld/eagle.flash.2m256.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m512.ld b/tools/sdk/ld/eagle.flash.2m512.ld index 558aa38782..1c495fca01 100644 --- a/tools/sdk/ld/eagle.flash.2m512.ld +++ b/tools/sdk/ld/eagle.flash.2m512.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.2m64.ld b/tools/sdk/ld/eagle.flash.2m64.ld index 615c109c1b..5d4fcddc8a 100644 --- a/tools/sdk/ld/eagle.flash.2m64.ld +++ b/tools/sdk/ld/eagle.flash.2m64.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m.ld b/tools/sdk/ld/eagle.flash.4m.ld index 0894518385..36e71f64a2 100644 --- a/tools/sdk/ld/eagle.flash.4m.ld +++ b/tools/sdk/ld/eagle.flash.4m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m1m.ld b/tools/sdk/ld/eagle.flash.4m1m.ld index 9a9ec54fed..5b0c692e70 100644 --- a/tools/sdk/ld/eagle.flash.4m1m.ld +++ b/tools/sdk/ld/eagle.flash.4m1m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m2m.ld b/tools/sdk/ld/eagle.flash.4m2m.ld index f0a5d34835..554237fb97 100644 --- a/tools/sdk/ld/eagle.flash.4m2m.ld +++ b/tools/sdk/ld/eagle.flash.4m2m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.4m3m.ld b/tools/sdk/ld/eagle.flash.4m3m.ld index 056d836655..47cf1f93e6 100644 --- a/tools/sdk/ld/eagle.flash.4m3m.ld +++ b/tools/sdk/ld/eagle.flash.4m3m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.512k.ld b/tools/sdk/ld/eagle.flash.512k.ld index 3c36174bee..df8d6fd3dc 100644 --- a/tools/sdk/ld/eagle.flash.512k.ld +++ b/tools/sdk/ld/eagle.flash.512k.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x79ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k128.ld b/tools/sdk/ld/eagle.flash.512k128.ld index 1eac5d5f9c..86132a9cf6 100644 --- a/tools/sdk/ld/eagle.flash.512k128.ld +++ b/tools/sdk/ld/eagle.flash.512k128.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x59ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k32.ld b/tools/sdk/ld/eagle.flash.512k32.ld index 65500df59d..12042444ac 100644 --- a/tools/sdk/ld/eagle.flash.512k32.ld +++ b/tools/sdk/ld/eagle.flash.512k32.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x71ff0 } diff --git a/tools/sdk/ld/eagle.flash.512k64.ld b/tools/sdk/ld/eagle.flash.512k64.ld index c773b80647..47a8b1fd1d 100644 --- a/tools/sdk/ld/eagle.flash.512k64.ld +++ b/tools/sdk/ld/eagle.flash.512k64.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0x69ff0 } diff --git a/tools/sdk/ld/eagle.flash.8m6m.ld b/tools/sdk/ld/eagle.flash.8m6m.ld index 38fe7c13b6..f3febe2085 100644 --- a/tools/sdk/ld/eagle.flash.8m6m.ld +++ b/tools/sdk/ld/eagle.flash.8m6m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.flash.8m7m.ld b/tools/sdk/ld/eagle.flash.8m7m.ld index c752cdae60..ee4de71084 100644 --- a/tools/sdk/ld/eagle.flash.8m7m.ld +++ b/tools/sdk/ld/eagle.flash.8m7m.ld @@ -10,7 +10,6 @@ MEMORY { dport0_0_seg : org = 0x3FF00000, len = 0x10 dram0_0_seg : org = 0x3FFE8000, len = 0x14000 - iram1_0_seg : org = 0x40100000, len = 0xC000 /* Actual len: MMU_IRAM_SIZE */ irom0_0_seg : org = 0x40201010, len = 0xfeff0 } diff --git a/tools/sdk/ld/eagle.rom.addr.v6.ld b/tools/sdk/ld/eagle.rom.addr.v6.ld index 84c5e3acf5..e2cff957a9 100644 --- a/tools/sdk/ld/eagle.rom.addr.v6.ld +++ b/tools/sdk/ld/eagle.rom.addr.v6.ld @@ -79,6 +79,11 @@ PROVIDE ( _xtos_l1int_handler = 0x4000048c ); PROVIDE ( _xtos_p_none = 0x4000dbf8 ); PROVIDE ( _xtos_restore_intlevel = 0x4000056c ); PROVIDE ( _xtos_return_from_exc = 0x4000dc54 ); + +/* Added to support replacing the ROM _xtos_c_wrapper_handler */ +PROVIDE ( _xtos_c_handler_table = 0x3fffc100 ); +PROVIDE ( _xtos_exc_handler_table = 0x3fffc000 ); + PROVIDE ( _xtos_set_exception_handler = 0x40000454 ); PROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 ); PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 ); From 161e7bc936f60ceb21397219507fa500ff9eaccb Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 4 Mar 2020 19:42:55 -0800 Subject: [PATCH 12/48] Added exception C wrapper replacement. --- cores/esp8266/core_esp8266_main.cpp | 2 +- cores/esp8266/core_esp8266_non32xfer.cpp | 29 +++- cores/esp8266/esp8266_undocumented.h | 90 +++++++++- cores/esp8266/exc-c-wrapper-handler.S | 127 ++++++++++++++ cores/esp8266/mmu_iram.h | 41 +++-- cores/esp8266/umm_malloc/umm_local.c | 34 +++- cores/esp8266/umm_malloc/umm_malloc.cpp | 12 +- cores/esp8266/xtruntime-frames.h | 162 ++++++++++++++++++ libraries/esp8266/examples/MMU48K/MMU48K.ino | 10 +- .../esp8266/examples/irammem/irammem.ino | 55 +++++- platform.txt | 4 +- tools/platformio-build.py | 14 +- 12 files changed, 534 insertions(+), 46 deletions(-) create mode 100644 cores/esp8266/exc-c-wrapper-handler.S create mode 100644 cores/esp8266/xtruntime-frames.h diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 8543224e46..60e74b2c90 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -334,7 +334,7 @@ extern "C" void user_init(void) { cont_init(g_pcont); -#if defined(NON32XFER_HANDLER) || defined(MMU_SEC_HEAP) +#if defined(NON32XFER_HANDLER) install_non32xfer_exception_handler(); #endif #if defined(MMU_IRAM_HEAP) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 7fec1e4f4c..ff548112fe 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -50,7 +50,8 @@ extern "C" { uint32_t mmu_non32xfer_count = 0; uint32_t mmu_non32xfer_withinisr_count = 0; -#define DEBUG_WARNING + +// #define DEBUG_WARNING #ifdef DEBUG_WARNING static void warning(void) { @@ -76,7 +77,9 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, */ uint32_t insn; __asm( +#if !defined(USE_ISR_SAFE_EXC_WRAPPER) "rsil %0, 15\n\t" /* Turn IRQs back off, let exit wrapper restore PS */ +#endif "movi %0, ~3\n\t" /* prepare a mask for the EPC */ "and %0, %0, %1\n\t" /* apply mask for 32bit aligned base */ "ssa8l %1\n\t" /* set up shift register for src op */ @@ -94,12 +97,14 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, an exception handler? */ if (ef->ps & 0x0F) { +#if !defined(USE_ISR_SAFE_EXC_WRAPPER) if (0 == mmu_non32xfer_withinisr_count) { ETS_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); #if 0 continue; /* fail, not safe for IRQ disabled ?? */ #endif } +#endif if (0 == ++mmu_non32xfer_withinisr_count) { --mmu_non32xfer_withinisr_count; // saturated } @@ -205,7 +210,28 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, panic(); } +#if defined(USE_ISR_SAFE_EXC_WRAPPER) + +constexpr _xtos_handler ROM_xtos_c_wrapper_handler = (_xtos_handler)0x40000598; + +static void IRAM_ATTR _set_exception_handler_wrapper(uint32_t cause) { + _xtos_handler old_wrapper = _xtos_exc_handler_table[cause]; + if (old_wrapper == ROM_xtos_c_wrapper_handler) { + _xtos_exc_handler_table[cause] = _xtos_c_wrapper_handler; + } +} + +void IRAM_ATTR install_non32xfer_exception_handler(void) { + if (NULL == old_handler) { + old_handler = + _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, + non32xfer_exception_handler); + _set_exception_handler_wrapper(EXCCAUSE_LOAD_STORE_ERROR); + } +} + +#else void IRAM_ATTR install_non32xfer_exception_handler(void) { if (NULL == old_handler) { @@ -214,5 +240,6 @@ void IRAM_ATTR install_non32xfer_exception_handler(void) non32xfer_exception_handler); } } +#endif }; diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index 031d2d38fe..dfdccc8062 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -67,24 +67,102 @@ struct __exception_frame }; uint32_t cause; }; +/*? + TODO: A set of static_asserts to confim we are matching these. + + Extracted from information at + From https://github.com/fdivitto/ESPWebFramework/blob/master/SDK/xtensa-lx106-elf/xtensa-lx106-elf/lib/libhandlers-null.txt + +#define UEXC_pc 0x0000 +#define UEXC_ps 0x0004 +#define UEXC_sar 0x0008 +#define UEXC_vpri 0x000c +#define UEXC_a0 0x0010 +#define UEXC_a2 0x0014 +#define UEXC_a3 0x0018 +#define UEXC_a4 0x001c +#define UEXC_a5 0x0020 +#define UEXC_a6 0x0024 +#define UEXC_a7 0x0028 +#define UEXC_a8 0x002c +#define UEXC_a9 0x0030 +#define UEXC_a10 0x0034 +#define UEXC_a11 0x0038 +#define UEXC_a12 0x003c +#define UEXC_a13 0x0040 +#define UEXC_a14 0x0044 +#define UEXC_a15 0x0048 +#define UEXC_exccause 0x004c +#define UserFrameSize 0x0050 +#define UserFrameTotalSize 0x0100 +*/ + +/* + Most of the comments here are gleamed from the xtensa files found at the site + listed below and are mostly unverified: + https://github.com/qca/open-ath9k-htc-firmware/tree/master/sboot/magpie_1_1/sboot/athos/src/xtos + * exc-c-wrapper-handler.S + * exc-sethandler.c +*/ /* ROM Function, _xtos_set_exception_handler(), installs a "C" callable exception handler. - If reason is out of range, >=64, it returns NULL. - If the new exception handler is installed, it returns the previous handler. - If the previous handler was _xtos_unhandled_exception/_xtos_p_none, it returns - NULL. + * If reason is out of range, >=64, it returns NULL. + * If the new exception handler is installed, it returns the previous handler. + * If the previous handler was _xtos_unhandled_exception/_xtos_p_none, it + returns NULL. Note, the installed "C" exception handler is called from the _xtos_c_wrapper_handler with IRQs enabled. */ typedef void (*fn_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); -extern fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); +fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); + +/* + Added to eagle.rom.addr.v6.ld + PROVIDE ( _xtos_exc_handler_table = 0x3fffc000 ); + PROVIDE ( _xtos_c_handler_table = 0x3fffc100 ); +*/ +#ifdef __cplusplus +typedef void (_xtos_handler_func)(...); + +/* + Assembly-level handler, used in the _xtos_exc_handler_table[], a wrapper for + calling registered "C" exception handlers. +*/ +void _xtos_c_wrapper_handler(...); -extern void _xtos_unhandled_exception(struct __exception_frame *ef, uint32_t cause); +/* + Assembly-level handler, used in the _xtos_exc_handler_table[], for exceptions + without a registered handler. +*/ +void _xtos_unhandled_exception(...); + +/* + The default/empty "C" exception handler, used in the _xtos_c_handler_table[], + when an exception handler has not been registered. + Supply this to _xtos_set_exception_handler() to reset an exception handler + back to the unhandled state, _xtos_unhandled_exception. + Note, if you have nesting handlers this is much more complicated than this. +*/ +void _xtos_p_none(void); + +#else +typedef void (_xtos_handler_func)(); +void _xtos_c_wrapper_handler(); +void _xtos_unhandled_exception()); +void _xtos_p_none(); + +#endif + +typedef _xtos_handler_func *_xtos_handler; + +extern _xtos_handler _xtos_exc_handler_table[]; +extern _xtos_handler _xtos_c_handler_table[]; #ifdef __cplusplus }; #endif + #endif diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S new file mode 100644 index 0000000000..b7a1f01337 --- /dev/null +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -0,0 +1,127 @@ +// exc-c-wrapper-handler.S, this is a reduced version of the original file at +// https://github.com/qca/open-ath9k-htc-firmware/blob/master/sboot/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S#L62-L67 +// + +// exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers + +// Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +// #include "xtos-internal.h" +// #ifdef SIMULATOR +// #include +// #endif + +#include "xtruntime-frames.h" + +/* + * This is the general exception assembly-level handler that dispatches C handlers. + */ + .align 4 + .global _xtos_c_wrapper_handler +_xtos_c_wrapper_handler: + + // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp). + // a2 contains EXCCAUSE. + s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4 + // (a4..a15 spilled as needed; save if modified) + + //NOTA: Possible future improvement: + // keep interrupts disabled until we get into the handler, such that + // we don't have to save other critical state such as EXCVADDR here. +// @mhightower83 - This promise was broken by an "rsil a13, 0" below. + //rsr a3, EXCVADDR + s32i a2, a1, UEXC_exccause + //s32i a3, a1, UEXC_excvaddr + + // Set PS fields: + // EXCM = 0 + // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1 + // UM = 1 + // INTLEVEL = EXCM_LEVEL = 1 + // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1 + // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__) + + movi a2, 0x23 // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) + rsr a3, EPC_1 +// @mhightower83 - I assume PS.EXCM was set and now is being cleared, thus +// allowing new exceptions and interrupts within PS_INTLEVEL to be possible. + xsr a2, PS + + // HERE: window overflows enabled, but NOT SAFE because we're not quite + // in a valid windowed context (haven't restored a1 yet...); + // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1: + + // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1. + s32i a3, a1, UEXC_pc + s32i a2, a1, UEXC_ps + s32i a0, a1, UEXC_a0 // save the rest of the registers + s32i a6, a1, UEXC_a6 + s32i a7, a1, UEXC_a7 + s32i a8, a1, UEXC_a8 + s32i a9, a1, UEXC_a9 + s32i a10, a1, UEXC_a10 + s32i a11, a1, UEXC_a11 + s32i a12, a1, UEXC_a12 + s32i a13, a1, UEXC_a13 + s32i a14, a1, UEXC_a14 + s32i a15, a1, UEXC_a15 + rsync // wait for WSR to PS to complete + rsr a12, SAR + +// @mhightower83 - I think after the next instruction we have the potential of +// loosing UEXC_excvaddr Which the earlier comment said we need to preserve for +// the exception handler. +// +// rsil a13, 0 + + movi a13, _xtos_c_handler_table // &table + l32i a15, a1, UEXC_exccause // arg2: exccause + s32i a12, a1, UEXC_sar + addx4 a12, a15, a13 // a12 = table[exccause] + l32i a12, a12, 0 // ... + mov a2, a1 // arg1: exception parameters + mov a3, a15 // arg2: exccause + beqz a12, 1f // null handler => skip call + callx0 a12 // call C exception handler for this exception +1: + // Now exit the handler. + + // Restore special registers + l32i a14, a1, UEXC_sar + + /* + * Disable interrupts while returning from the pseudo-CALL setup above, + * for the same reason they were disabled while doing the pseudo-CALL: + * this sequence restores SP such that it doesn't reflect the allocation + * of the exception stack frame, which we still need to return from + * the exception. + */ +// rsil a12, 1 // XCHAL_EXCM_LEVEL + wsr a14, SAR + movi a0, _xtos_return_from_exc + jx a0 + + /* FIXME: what about _GeneralException ? */ + .size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 82ebbd3e83..c5426ef473 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -40,7 +40,11 @@ #define DEBUG_MMU #endif - +/* + The more I look at _xtos_c_wrapper_handler the more convinced I am that this + USE_ISR_SAFE_EXC_WRAPPER is required. +*/ +#define USE_ISR_SAFE_EXC_WRAPPER #if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_MMU) #include @@ -113,18 +117,10 @@ extern mmu_cre_status_t mmu_status; static inline bool is_iram(uint32_t addr) { // constexpr uint32_t _start = 0x40100000UL; #define IRAM_START 0x40100000UL - #ifndef MMU_IRAM_SIZE -#define MMU_IRAM_SIZE 0xC000UL -#endif - -#ifdef MMU_SEC_HEAP_SIZE - // constexpr uint32_t _end = _start + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE; - #define IRAM_END (IRAM_START + MMU_IRAM_SIZE + MMU_SEC_HEAP_SIZE) -#else - // constexpr uint32_t _end = _start + MMU_IRAM_SIZE; - #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) +#define MMU_IRAM_SIZE 0x8000UL #endif +#define IRAM_END (IRAM_START + MMU_IRAM_SIZE) return (IRAM_START <= addr && IRAM_END > addr); } @@ -165,14 +161,14 @@ static inline bool is_icache(uint32_t addr) { if (is_iram((uint32_t)a) || is_dram((uint32_t)a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ - assert(("Outside of Range Write" && false)); \ + assert(("Outside of Range - Write" && false)); \ } #define ASSERT_RANGE_TEST_READ(a) \ - if (is_iram((uint32_t)a) || is_icache((uint32_t)a) || is_dram((uint32_t)a)) { \ + if (is_iram((uint32_t)a) || is_dram((uint32_t)a) || is_icache((uint32_t)a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ - assert(("Outside of Range Read" && false)); \ + assert(("Outside of Range - Read" && false)); \ } #else @@ -258,4 +254,21 @@ static inline int16_t set_int16_iram(short *p16, const int16_t val) { } #endif +#if (MMU_IRAM_SIZE > 32*1024) && !defined(MMU_SEC_HEAP) +extern "C" void _text_end(void); +#define MMU_SEC_HEAP mmu_sec_heap() +#define MMU_SEC_HEAP_SIZE mmu_sec_heap_size() + +static inline __attribute__((always_inline)) +void *mmu_sec_heap(void) { + uint32_t sec_heap = (uint32_t)_text_end + 32; + return (void *)(sec_heap &= ~7); +} + +static inline __attribute__((always_inline)) +size_t mmu_sec_heap_size(void) { + return (size_t)0xC000UL - ((size_t)mmu_sec_heap() - 0x40100000UL); +} +#endif + #endif diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index ae5f5c6a7c..ca05d5b330 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -164,9 +164,10 @@ size_t umm_block_size( void ) { #if defined(UMM_STATS) || defined(UMM_STATS_FULL) #if defined(UMM_POISON_CHECK) || defined(UMM_POISON_CHECK_LITE) - -// Adjustment needed for free_blocks to express the number of bytes that can -// actually be allocated. +/* + Overhead adjustments needed for free_blocks to express the number of bytes + that can actually be allocated. +*/ #define UMM_OVERHEAD_ADJUST \ (umm_block_size() + \ umm_block_size()/2 + \ @@ -177,12 +178,17 @@ size_t umm_block_size( void ) { #define UMM_OVERHEAD_ADJUST (umm_block_size() + umm_block_size()/2) #endif +static size_t free_blocks_to_free_space(unsigned short int blocks) { + int free_space = (int)blocks * sizeof(umm_block) - UMM_OVERHEAD_ADJUST; + return (free_space > 0) ? (size_t)free_space : 0; +} + // Keep complete call path in IRAM size_t umm_free_heap_size_lw( void ) { UMM_INIT_HEAP; umm_heap_context_t *_context = umm_get_current_heap(); - return (size_t)_context->stats.free_blocks * sizeof(umm_block) - UMM_OVERHEAD_ADJUST; + return free_blocks_to_free_space(_context->stats.free_blocks); } #endif @@ -241,26 +247,36 @@ size_t ICACHE_FLASH_ATTR umm_get_oom_count( void ) { #endif #ifdef UMM_STATS_FULL - +// TODO - Did I mix something up +// +// umm_free_heap_size_min is the same code as +// umm_free_heap_size_lw_min +// +// If this is correct use alias. +// size_t ICACHE_FLASH_ATTR umm_free_heap_size_lw_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return (size_t)_context->stats.free_blocks_min * umm_block_size() - UMM_OVERHEAD_ADJUST; + return free_blocks_to_free_space(_context->stats.free_blocks_min); } size_t ICACHE_FLASH_ATTR umm_free_heap_size_min_reset( void ) { umm_heap_context_t *_context = umm_get_current_heap(); _context->stats.free_blocks_min = _context->stats.free_blocks; - return (size_t)_context->stats.free_blocks_min * umm_block_size(); + return free_blocks_to_free_space(_context->stats.free_blocks_min); } +#if 0 // TODO - Don't understand this why do both umm_free_heap_size_(lw_)min exist +size_t umm_free_heap_size_min(void) __attribute__ ((alias("umm_free_heap_size_lw_min"))); +#else size_t ICACHE_FLASH_ATTR umm_free_heap_size_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return _context->stats.free_blocks_min * umm_block_size() - UMM_OVERHEAD_ADJUST; + return free_blocks_to_free_space(_context->stats.free_blocks_min); } +#endif size_t ICACHE_FLASH_ATTR umm_free_heap_size_isr_min( void ) { umm_heap_context_t *_context = umm_get_current_heap(); - return _context->stats.free_blocks_isr_min * umm_block_size() - UMM_OVERHEAD_ADJUST; + return free_blocks_to_free_space(_context->stats.free_blocks_isr_min); } size_t ICACHE_FLASH_ATTR umm_get_max_alloc_size( void ) { diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 5c6c1baf7e..de057bea2d 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -405,7 +405,7 @@ static void umm_init_stage_2( umm_heap_context_t *_context ) { void umm_init_common( size_t id, void *start_addr, size_t size, bool zero ) { /* Preserve internal setup */ umm_heap_context_t *_context = umm_get_heap_by_id(id); - if (NULL == _context || _context->heap) { + if (NULL == start_addr || NULL == _context || _context->heap) { return; } @@ -458,11 +458,7 @@ void _text_end(void); void umm_init_iram(void) __attribute__((weak)); void umm_init_iram(void) { - uint32_t sec_heap = (uint32_t)_text_end + 32; - sec_heap &= ~7; - size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); - - umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); + umm_init_iram_ex(mmu_sec_heap(), mmu_sec_heap_size(), true); } #endif // #ifdef UMM_HEAP_IRAM @@ -711,9 +707,11 @@ void *umm_malloc( size_t size ) { UMM_CRITICAL_ENTRY(id_malloc); +#if 1 // !defined(USE_ISR_SAFE_EXC_WRAPPER) if (UMM_CRITICAL_WITHINISR(id_malloc)) { _context = umm_get_heap_by_id(UMM_HEAP_DRAM); } +#endif ptr = umm_malloc_core( _context, size ); @@ -776,10 +774,12 @@ void *umm_realloc( void *ptr, size_t size ) { STATS__ALLOC_REQUEST(id_realloc, size); +#if !defined(USE_ISR_SAFE_EXC_WRAPPER) // Require ISR use DRAM for now. if (ETS_INTR_WITHINISR() && UMM_HEAP_DRAM != _context->id) { return( (void *)NULL ); } +#endif /* * Otherwise we need to actually do a reallocation. A naiive approach diff --git a/cores/esp8266/xtruntime-frames.h b/cores/esp8266/xtruntime-frames.h new file mode 100644 index 0000000000..8b5a7463ab --- /dev/null +++ b/cores/esp8266/xtruntime-frames.h @@ -0,0 +1,162 @@ +/* xtruntime-frames.h - exception stack frames for single-threaded run-time */ +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */ + +/* + * Copyright (c) 2002-2012 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _XTRUNTIME_FRAMES_H_ +#define _XTRUNTIME_FRAMES_H_ + +#include + +/* Macros that help define structures for both C and assembler: */ +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,pre,name) pre##name: .space size +#define STRUCT_AFIELD(ctype,size,pre,name,n) pre##name: .if n ; .space (size)*(n) ; .endif +#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) .balign align ; pre##name: .if n ; .space (size)*(n) ; .endif +#define STRUCT_END(sname) sname##Size:; .popsection +#else /*_ASMLANGUAGE||__ASSEMBLER__*/ +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,pre,name) ctype name; +#define STRUCT_AFIELD(ctype,size,pre,name,n) ctype name[n]; +#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) ctype name[n] __attribute__((aligned(align))); +#define STRUCT_END(sname) } sname; +#endif /*_ASMLANGUAGE||__ASSEMBLER__*/ + + +/* + * Kernel vector mode exception stack frame. + * + * NOTE: due to the limited range of addi used in the current + * kernel exception vector, and the fact that historically + * the vector is limited to 12 bytes, the size of this + * stack frame is limited to 128 bytes (currently at 64). + */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,KEXC_,pc) /* "parm" */ +STRUCT_FIELD (long,4,KEXC_,ps) +STRUCT_AFIELD(long,4,KEXC_,areg, 4) /* a12 .. a15 */ +STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */ +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,KEXC_,lcount) +STRUCT_FIELD (long,4,KEXC_,lbeg) +STRUCT_FIELD (long,4,KEXC_,lend) +#endif +#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,KEXC_,acclo) +STRUCT_FIELD (long,4,KEXC_,acchi) +STRUCT_AFIELD(long,4,KEXC_,mr, 4) +#endif +STRUCT_END(KernelFrame) + + +/* + * User vector mode exception stack frame: + * + * WARNING: if you modify this structure, you MUST modify the + * computation of the pad size (ALIGNPAD) accordingly. + */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,UEXC_,pc) +STRUCT_FIELD (long,4,UEXC_,ps) +STRUCT_FIELD (long,4,UEXC_,sar) +STRUCT_FIELD (long,4,UEXC_,vpri) +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long,4,UEXC_,a0) +#endif +STRUCT_FIELD (long,4,UEXC_,a2) +STRUCT_FIELD (long,4,UEXC_,a3) +STRUCT_FIELD (long,4,UEXC_,a4) +STRUCT_FIELD (long,4,UEXC_,a5) +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long,4,UEXC_,a6) +STRUCT_FIELD (long,4,UEXC_,a7) +STRUCT_FIELD (long,4,UEXC_,a8) +STRUCT_FIELD (long,4,UEXC_,a9) +STRUCT_FIELD (long,4,UEXC_,a10) +STRUCT_FIELD (long,4,UEXC_,a11) +STRUCT_FIELD (long,4,UEXC_,a12) +STRUCT_FIELD (long,4,UEXC_,a13) +STRUCT_FIELD (long,4,UEXC_,a14) +STRUCT_FIELD (long,4,UEXC_,a15) +#endif +STRUCT_FIELD (long,4,UEXC_,exccause) /* NOTE: can probably rid of this one (pass direct) */ +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,UEXC_,lcount) +STRUCT_FIELD (long,4,UEXC_,lbeg) +STRUCT_FIELD (long,4,UEXC_,lend) +#endif +#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,UEXC_,acclo) +STRUCT_FIELD (long,4,UEXC_,acchi) +STRUCT_AFIELD(long,4,UEXC_,mr, 4) +#endif +/* ALIGNPAD is the 16-byte alignment padding. */ +#ifdef __XTENSA_CALL0_ABI__ +# define CALL0_ABI 1 +#else +# define CALL0_ABI 0 +#endif +#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3) +#if ALIGNPAD +STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */ +#endif +/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/ /* not used */ +STRUCT_END(UserFrame) + + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + + +/* Check for UserFrameSize small enough not to require rounding...: */ + /* Skip 16-byte save area, then 32-byte space for 8 regs of call12 + * (which overlaps with 16-byte GCC nested func chaining area), + * then exception stack frame: */ + .set UserFrameTotalSize, 16+32+UserFrameSize + /* Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes): */ + .ifgt UserFrameTotalSize-112 + /* Round up to 256-byte multiple to accelerate immediate adds: */ + .set UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00) + .endif +# define ESF_TOTALSIZE UserFrameTotalSize + +#endif /* _ASMLANGUAGE || __ASSEMBLER__ */ + + +#if XCHAL_NUM_CONTEXTS > 1 +/* Structure of info stored on new context's stack for setup: */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,INFO_,sp) +STRUCT_FIELD (long,4,INFO_,arg1) +STRUCT_FIELD (long,4,INFO_,funcpc) +STRUCT_FIELD (long,4,INFO_,prevps) +STRUCT_END(SetupInfo) +#endif + + +#define KERNELSTACKSIZE 1024 + + +#endif /* _XTRUNTIME_FRAMES_H_ */ + diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index bfda4d79cf..8c634a7324 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -18,15 +18,14 @@ static inline char get ## name(void *o) { \ */ -#if defined(MMU_IRAM_HEAP) +#if defined(MMU_IRAM_HEAP) || defined(MMU_SEC_HEAP) uint32_t *gobble; size_t gobble_sz; + #elif (MMU_IRAM_SIZE > 32*1024) uint32_t gobble[4 * 1024] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); -#elif defined(MMU_SEC_HEAP) -uint32_t *gobble = (uint32_t *)MMU_SEC_HEAP; -size_t gobble_sz = MMU_SEC_HEAP_SIZE; + #else uint32_t gobble[256] IRAM_ATTR; constexpr size_t gobble_sz = sizeof(gobble); @@ -139,6 +138,9 @@ void setup() { Serial.printf_P(PSTR("gobble_sz: %u\n"), gobble_sz); Serial.printf_P(PSTR("gobble: %p\n"), gobble); +#elif defined(MMU_SEC_HEAP) + gobble = (uint32_t *)MMU_SEC_HEAP; + gobble_sz = MMU_SEC_HEAP_SIZE; #endif #if (MMU_IRAM_SIZE > 0x8000) || defined(MMU_IRAM_HEAP) || defined(MMU_SEC_HEAP) diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index e2257b7603..76bb9da708 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -255,6 +255,59 @@ void setup() { #endif } -void loop() { +void processKey(Print& out, int hotKey) { + switch (hotKey) { + case 'd': { + HeapSelectDram ephemeral; + umm_info(NULL, true); + break; + } + case 'i': { + HeapSelectIram ephemeral; + umm_info(NULL, true); + break; + } + case 'h': { + { + HeapSelectIram ephemeral; + Serial.printf(PSTR("IRAM ESP.getFreeHeap: %u\n"), ESP.getFreeHeap()); + } + { + HeapSelectDram ephemeral; + Serial.printf(PSTR("DRAM ESP.getFreeHeap: %u\n"), ESP.getFreeHeap()); + } + break; + } + case 'R': + out.printf_P(PSTR("Restart, ESP.restart(); ...\r\n")); + ESP.restart(); + break; + case '\r': + out.println(); + case '\n': + break; + case '?': + out.println(); + out.println(F("Press a key + ")); + out.println(F(" h - Free Heap Report;")); + out.println(F(" i - iRAM umm_info(null, true);")); + out.println(F(" d - dRAM umm_info(null, true);")); + out.println(F(" R - Restart, ESP.restart();")); + out.println(F(" ? - Print Help")); + out.println(); + break; + default: + out.printf_P(PSTR("\"%c\" - Not an option? / ? - help"), hotKey); + out.println(); + processKey(out, '?'); + break; + } +} + +void loop(void){ + if (Serial.available() > 0) { + int hotKey = Serial.read(); + processKey(Serial, hotKey); + } } diff --git a/platform.txt b/platform.txt index 378774ee16..77e0e141cd 100644 --- a/platform.txt +++ b/platform.txt @@ -58,7 +58,7 @@ compiler.c.cmd=xtensa-lx106-elf-gcc compiler.c.flags=-c {compiler.warning_flags} -Os -g -Wpointer-arith -Wno-implicit-function-declaration -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -mtext-section-literals -falign-functions=4 -MMD -std=gnu99 -ffunction-sections -fdata-sections {build.exception_flags} {build.sslflags} {build.mmuflags} {build.non32xferflags} compiler.S.cmd=xtensa-lx106-elf-gcc -compiler.S.flags=-c -g -x assembler-with-cpp -MMD -mlongcalls +compiler.S.flags=-c -g -x assembler-with-cpp -MMD -mlongcalls -I{runtime.tools.xtensa-lx106-elf-gcc.path}/include/ compiler.c.elf.flags= -g {compiler.warning_flags} -Os -nostdlib -Wl,--no-check-sections -u app_entry {build.float} -Wl,-static "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/lib/{build.sdk}" "-L{build.path}" "-L{compiler.libc.path}/lib" "-Tlocal.eagle.flash.ld" -Wl,--gc-sections -Wl,-wrap,system_restart_local -Wl,-wrap,spi_flash_read @@ -111,7 +111,7 @@ recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.fla recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpreprocessor.flags} {compiler.cpp.flags} -D{build.sdk}=1 -DF_CPU={build.f_cpu} {build.lwip_flags} {build.debug_port} {build.debug_level} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" {build.led} {build.flash_flags} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" ## Compile S files -recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.S.flags} -D{build.sdk}=1 -DF_CPU={build.f_cpu} {build.lwip_flags} {build.debug_port} {build.debug_level} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" {build.led} {build.flash_flags} {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.S.flags} -D{build.sdk}=1 -DF_CPU={build.f_cpu} {build.lwip_flags} {build.debug_port} {build.debug_level} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" {build.led} {build.flash_flags} {compiler.S.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" ## Create archives recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" diff --git a/tools/platformio-build.py b/tools/platformio-build.py index c595497cbd..7529502796 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -255,17 +255,27 @@ def scons_patched_match_splitext(path, suffixes=None): env.Append(CPPDEFINES=[current_vtables]) assert current_vtables +current_mmu_iram_size = None +for d in flatten_cppdefines: + if str(d).startswith("MMU_IRAM_SIZE"): + current_mmu_iram_size = d +if not current_mmu_iram_size: + current_mmu_iram_size = "MMU_IRAM_SIZE=0x8000" + env.Append(CPPDEFINES=[current_mmu_iram_size]) +assert current_mmu_iram_size + + # Build the eagle.app.v6.common.ld linker file app_ld = env.Command( join("$BUILD_DIR", "ld", "local.eagle.app.v6.common.ld"), join(FRAMEWORK_DIR, "tools", "sdk", "ld", "eagle.app.v6.common.ld.h"), env.VerboseAction( - "$CC -CC -E -P -D%s $SOURCE -o $TARGET" % current_vtables, + "$CC -CC -E -P -D%s -D%s $SOURCE -o $TARGET" % (current_vtables, current_mmu_iram_size), "Generating LD script $TARGET")) env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", app_ld) if not env.BoardConfig().get("build.ldscript", ""): - env.Replace(LDSCRIPT_PATH=env.BoardConfig().get("build.arduino.ldscript", "")) + env.Replace(LDSCRIPT_PATH=env.BoardConfig().get("build.arduino.ldscript", "")) # # Dynamic core_version.h for staging builds From 91fc39130e6b39d3f4cf25c3956fda07a7d5c981 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 5 Mar 2020 20:05:47 -0800 Subject: [PATCH 13/48] CI Cleanup --- cores/esp8266/esp8266_undocumented.h | 2 +- cores/esp8266/umm_malloc/umm_local.c | 5 ++++ .../esp8266/examples/irammem/irammem.ino | 25 ++++++++++++++++++- tools/platformio-build.py | 3 ++- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index dfdccc8062..8ff33e508e 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -150,7 +150,7 @@ void _xtos_p_none(void); #else typedef void (_xtos_handler_func)(); void _xtos_c_wrapper_handler(); -void _xtos_unhandled_exception()); +void _xtos_unhandled_exception(); void _xtos_p_none(); #endif diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index ca05d5b330..693b96a53a 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -180,6 +180,11 @@ size_t umm_block_size( void ) { static size_t free_blocks_to_free_space(unsigned short int blocks) { int free_space = (int)blocks * sizeof(umm_block) - UMM_OVERHEAD_ADJUST; + /* + * There are some strange boundary things at play I don't quite follow. + * However, these adjustments allow malloc to be called and succeed in + * allocating all of the available memory, assuming it is contiguous. + */ return (free_space > 0) ? (size_t)free_space : 0; } diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 76bb9da708..648c739f71 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -253,6 +253,29 @@ void setup() { Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); } #endif + { + ets_uart_printf("Try and allocate all of the heap in one chunk\n"); + HeapSelectIram ephemeral; + size_t free_iram = ESP.getFreeHeap(); + ets_uart_printf("IRAM free: %6d\n", free_iram); + uint32_t hfree; + uint16_t hmax; + uint8_t hfrag; + ESP.getHeapStats(&hfree, &hmax, &hfrag); + ets_uart_printf("ESP.getHeapStats(free: %u, max: %u, frag: %u)\n", + hfree, hmax, hfrag); + + void *all = malloc(free_iram); + ets_uart_printf("%p = malloc(%lu)\n", all, free_iram); + umm_info(NULL, true); + + free_iram = ESP.getFreeHeap(); + ets_uart_printf("IRAM free: %6d\n", free_iram); + + free(all); + ets_uart_printf("IRAM free: %6d\n", ESP.getFreeHeap()); + + } } void processKey(Print& out, int hotKey) { @@ -305,7 +328,7 @@ void processKey(Print& out, int hotKey) { } -void loop(void){ +void loop(void) { if (Serial.available() > 0) { int hotKey = Serial.read(); processKey(Serial, hotKey); diff --git a/tools/platformio-build.py b/tools/platformio-build.py index 7529502796..33e3c2c792 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -111,7 +111,8 @@ def scons_patched_match_splitext(path, suffixes=None): join(FRAMEWORK_DIR, "tools", "sdk", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "libc", "xtensa-lx106-elf", "include"), - join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")) + join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")), + join(FRAMEWORK_DIR, "tools", "xtensa-lx106-elf", "include") ], LIBPATH=[ From eb9882e8ad05f82aa051e85af44facd2a39a670b Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 5 Mar 2020 20:38:42 -0800 Subject: [PATCH 14/48] CI Cleanup II Don't know what to do with platformio it doesn't like my .S file. ifdef out USE_ISR_SAFE_EXC_WRAPPER to block the new assemlby module from building on platformio only. --- cores/esp8266/exc-c-wrapper-handler.S | 7 +++++++ cores/esp8266/mmu_iram.h | 2 ++ libraries/esp8266/examples/irammem/irammem.ino | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S index b7a1f01337..fefe6edf09 100644 --- a/cores/esp8266/exc-c-wrapper-handler.S +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -2,6 +2,12 @@ // https://github.com/qca/open-ath9k-htc-firmware/blob/master/sboot/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S#L62-L67 // + + +#ifndef PLATFORMIO + + + // exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers // Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc. @@ -125,3 +131,4 @@ _xtos_c_wrapper_handler: /* FIXME: what about _GeneralException ? */ .size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler +#endif diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index c5426ef473..e604e1c994 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -44,7 +44,9 @@ The more I look at _xtos_c_wrapper_handler the more convinced I am that this USE_ISR_SAFE_EXC_WRAPPER is required. */ +#ifndef PLATFORMIO #define USE_ISR_SAFE_EXC_WRAPPER +#endif #if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_MMU) #include diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 648c739f71..d29ae2dd53 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -266,7 +266,7 @@ void setup() { hfree, hmax, hfrag); void *all = malloc(free_iram); - ets_uart_printf("%p = malloc(%lu)\n", all, free_iram); + ets_uart_printf("%p = malloc(%u)\n", all, free_iram); umm_info(NULL, true); free_iram = ESP.getFreeHeap(); From 1422b8d76c4af05440e6e182d995add4131dde27 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 5 Mar 2020 23:39:53 -0800 Subject: [PATCH 15/48] Changes to exc-c-wrapper-handler.S to assemble under platformio. --- cores/esp8266/exc-c-wrapper-handler.S | 9 ++------- cores/esp8266/mmu_iram.cpp | 9 +++++---- cores/esp8266/mmu_iram.h | 2 -- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S index fefe6edf09..c71e93fc03 100644 --- a/cores/esp8266/exc-c-wrapper-handler.S +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -2,12 +2,6 @@ // https://github.com/qca/open-ath9k-htc-firmware/blob/master/sboot/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S#L62-L67 // - - -#ifndef PLATFORMIO - - - // exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers // Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc. @@ -44,7 +38,9 @@ /* * This is the general exception assembly-level handler that dispatches C handlers. */ + .section .iram.text .align 4 + .literal_position .global _xtos_c_wrapper_handler _xtos_c_wrapper_handler: @@ -131,4 +127,3 @@ _xtos_c_wrapper_handler: /* FIXME: what about _GeneralException ? */ .size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler -#endif diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 800b022c06..420bf7bc30 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -31,8 +31,9 @@ extern "C" { // IS this set as part of segment data at load time? appears to be mmu_cre_status_t mmu_status = {SOC_CACHE_SIZE, -1, 0, 0, 0, 0, 0}; -// Enable all the time so we can gather information on Cache_Read_Enable usage. -#if 1 //(MMU_ICACHE_SIZE == 0x4000) +//C Enable all the time so we can gather information on Cache_Read_Enable usage. +//+ #if (MMU_ICACHE_SIZE == 0x4000) +#if 1 //D /* * "Cache_Read_Enable" as in Instruction Read Cache enable, ICACHE. * @@ -208,8 +209,8 @@ extern "C" void pinMode( uint8_t pin, uint8_t mode ) { __pinMode( pin, mode ); } -#endif +#endif // #ifdef DEV_DEBUG_PRINT -#endif +#endif // #if (MMU_ICACHE_SIZE == 0x4000) }; diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index e604e1c994..c5426ef473 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -44,9 +44,7 @@ The more I look at _xtos_c_wrapper_handler the more convinced I am that this USE_ISR_SAFE_EXC_WRAPPER is required. */ -#ifndef PLATFORMIO #define USE_ISR_SAFE_EXC_WRAPPER -#endif #if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_MMU) #include From b921e11928e819c032a0122e2265c428cdcbb2de Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Fri, 6 Mar 2020 08:30:15 -0800 Subject: [PATCH 16/48] For platformio, Correction to toolchain-xtensa include path. @mcspr, Thankyou! --- tools/platformio-build.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/platformio-build.py b/tools/platformio-build.py index 33e3c2c792..6e2820003b 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -112,7 +112,7 @@ def scons_patched_match_splitext(path, suffixes=None): join(FRAMEWORK_DIR, "tools", "sdk", "libc", "xtensa-lx106-elf", "include"), join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core")), - join(FRAMEWORK_DIR, "tools", "xtensa-lx106-elf", "include") + join(platform.get_package_dir("toolchain-xtensa"), "include") ], LIBPATH=[ From cfb38268e8cb73c87d84683b4206d1863a093e40 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Fri, 6 Mar 2020 12:03:20 -0800 Subject: [PATCH 17/48] Temporarily added --print-memory-usage to ld parameters for cross-checking IRAM size. --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index 77e0e141cd..ddcd6651cf 100644 --- a/platform.txt +++ b/platform.txt @@ -117,7 +117,7 @@ recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.fla recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" ## Combine gc-sections, archives, and objects -recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {build.exception_flags} -Wl,-Map "-Wl,{build.path}/{build.project_name}.map" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" -Wl,--start-group {object_files} "{archive_file_path}" {compiler.c.elf.libs} -Wl,--end-group "-L{build.path}" +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {build.exception_flags} -Wl,-Map "-Wl,{build.path}/{build.project_name}.map" "-Wl,--print-memory-usage" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" -Wl,--start-group {object_files} "{archive_file_path}" {compiler.c.elf.libs} -Wl,--end-group "-L{build.path}" ## Create eeprom recipe.objcopy.eep.pattern= From ecd826c25bad59f48d868ddd9246e15172af3b69 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 27 Apr 2020 19:04:30 -0700 Subject: [PATCH 18/48] undo change to platform.txt --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index ddcd6651cf..77e0e141cd 100644 --- a/platform.txt +++ b/platform.txt @@ -117,7 +117,7 @@ recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.fla recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" ## Combine gc-sections, archives, and objects -recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {build.exception_flags} -Wl,-Map "-Wl,{build.path}/{build.project_name}.map" "-Wl,--print-memory-usage" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" -Wl,--start-group {object_files} "{archive_file_path}" {compiler.c.elf.libs} -Wl,--end-group "-L{build.path}" +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {build.exception_flags} -Wl,-Map "-Wl,{build.path}/{build.project_name}.map" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" -Wl,--start-group {object_files} "{archive_file_path}" {compiler.c.elf.libs} -Wl,--end-group "-L{build.path}" ## Create eeprom recipe.objcopy.eep.pattern= From a9b92e2c3ed9f191cbcf3995554adf770c493c02 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 27 Apr 2020 19:09:13 -0700 Subject: [PATCH 19/48] correct merge conflict. take 1 --- bootloaders/eboot/eboot.elf | Bin 34956 -> 36640 bytes cores/esp8266/core_esp8266_main.cpp | 1 + 2 files changed, 1 insertion(+) diff --git a/bootloaders/eboot/eboot.elf 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zO^W|oyq$bkylw}sKM$h(t-#&wN$e_9HbmGUaXE9I|I3w4E&a&_*F}`u4ZZwv5tZ`J3Li1B2&g$I#n3l9`2TQIeoQhRRM?xsd= zZQVO;*(jwc8eP*6UASic!WHtAyI^7c{Q78AT)=1?q}$uE(QLyGS#4o1C?s2UKBsXD z&X8R^g`UrYKX5eN(y^@_=kDe$I8Bzbu{;_%2hYTjKw8d@&}U=47w4IkRq&XqH}ZqL zI%r>gz8$bJ(L`>(xvjpixk<4Lxo_d+3+O_pC0(7|Tsx*|qMOu)V?ue9{V3x_2XA8U zc3zzAXpFfWb^*3_^`L$GpuTRXsa?JhhPn#LM{^}V^9(icb1)9?6@>+6OyG9hB zTC_T2Jhf7F2u*z+qnjxEk`0WydeRwP7wDXh|FrWEgUPYbEeE&Li+qfe@^~ioAq!5M zEjU+gi8Zw(Pq61Z0s7SlWv|PJFiL&0Thv1x-8elC**-B9$2QD`$a}g}zDYy!06A6K zJGHr`aoa}N6WiP(90U`1r-oyVja@Cz+dCFN2Ivb4U>2HD(tOX1PyK)BzFq`55reA)5Y8Ff&q$s_$2z~p@h_>i|hqTxZI(qb)hY; zqZ@flw>i0%E4_|;pyZ|HJ_C}gxR?vMs-#$=jg)t`B9glkaw~9z#P71m-#KP~peyAm jQO1Cj!v1g%_FQsbq6pN(i?+DsHtoYN=u3{eX}SLcRo}p| diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index a2d59ae5d6..f97d697c9d 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -34,6 +34,7 @@ extern "C" { } #include #include "gdb_hooks.h" +#include "flash_quirks.h" #include #include From 1a9d909211b2791283a88e6e04bc589856501bba Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 9 May 2020 20:09:18 -0700 Subject: [PATCH 20/48] Fixed #if... for building umm_get_oom_count. It was not building when UMM_STATS_FULL was used. --- cores/esp8266/umm_malloc/umm_local.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index 693b96a53a..304d58bce9 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -244,7 +244,7 @@ int ICACHE_FLASH_ATTR umm_info_safe_printf_P(const char *fmt, ...) { return result; } -#if defined(UMM_STATS) +#if defined(UMM_STATS) || defined(UMM_STATS_FULL) size_t ICACHE_FLASH_ATTR umm_get_oom_count( void ) { umm_heap_context_t *_context = umm_get_current_heap(); return _context->stats.oom_count; From 7b4a8d44478eb16d6e4e57a75fe572e7cef0d4b4 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 17 May 2020 11:39:27 -0700 Subject: [PATCH 21/48] Commented out XMC support. Compatibility issues with PoC when using 16K ICACHE. --- cores/esp8266/core_esp8266_main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 3fc0faaf3a..eccc7f7fd0 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -344,7 +344,7 @@ extern "C" void user_init(void) { initVariant(); - experimental::initFlashQuirks(); // Chip specific flash init. + // experimental::initFlashQuirks(); // Chip specific flash init. cont_init(g_pcont); From 6d18190c8fa86afa331b6e616fe0103d36e7ab62 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 25 May 2020 08:06:32 -0700 Subject: [PATCH 22/48] Corrected size.py, DRAM bracketing changed to not include ICACHE with DRAM total. --- tools/sizes.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/sizes.py b/tools/sizes.py index 3c599ebf30..470e526c7a 100755 --- a/tools/sizes.py +++ b/tools/sizes.py @@ -25,16 +25,17 @@ def get_segment_hints(iram): hints = {} + hints['ICACHE'] = ' - flash instruction cache' hints['IROM'] = ' - code in flash (default or ICACHE_FLASH_ATTR)' hints['IRAM'] = ' / ' + str(iram) + ' - code in IRAM (ICACHE_RAM_ATTR, ISRs...)' hints['DATA'] = ') - initialized variables (global, static) in RAM/HEAP' hints['RODATA'] = ') / 81920 - constants (global, static) in RAM/HEAP' hints['BSS'] = ') - zeroed variables (global, static) in RAM/HEAP' - hints['ICACHE'] = ') - flash instruction cache' return hints def get_segment_sizes(elf, path): sizes = {} + sizes['ICACHE'] = 0 sizes['IROM'] = 0 sizes['IRAM'] = 0 sizes['DATA'] = 0 From d3ace64113b25f6162b65c9c4c6f897714d86e9d Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 18 Jun 2020 17:26:19 -0700 Subject: [PATCH 23/48] Added additional _context for support of use of UMM_INLINE_METRICS. Corrected some UMM_POSION missed edits. --- cores/esp8266/Esp-frag.cpp | 19 ++-- cores/esp8266/umm_malloc/umm_info.c | 103 +++++++++++++--------- cores/esp8266/umm_malloc/umm_local.c | 4 +- cores/esp8266/umm_malloc/umm_local.h | 3 + cores/esp8266/umm_malloc/umm_malloc.cpp | 2 +- cores/esp8266/umm_malloc/umm_malloc_cfg.h | 18 ++-- 6 files changed, 88 insertions(+), 61 deletions(-) diff --git a/cores/esp8266/Esp-frag.cpp b/cores/esp8266/Esp-frag.cpp index dc5970e854..f4bf5ec9ca 100644 --- a/cores/esp8266/Esp-frag.cpp +++ b/cores/esp8266/Esp-frag.cpp @@ -30,14 +30,15 @@ void EspClass::getHeapStats(uint32_t* hfree, uint16_t* hmax, uint8_t* hfrag) // 100 * (1 - sqrt(sum(hole-size²)) / sum(hole-size)) umm_info(NULL, false); - uint8_t block_size = umm_block_size(); + + uint32_t free_size = umm_free_heap_size_core(); if (hfree) - *hfree = ummHeapInfo.freeBlocks * block_size; + *hfree = free_size; if (hmax) - *hmax = (uint16_t)ummHeapInfo.maxFreeContiguousBlocks * block_size; + *hmax = (uint16_t)umm_max_block_size_core(); if (hfrag) { - if (ummHeapInfo.freeBlocks) { - *hfrag = 100 - (sqrt32(ummHeapInfo.freeBlocksSquared) * 100) / ummHeapInfo.freeBlocks; + if (free_size) { + *hfrag = umm_fragmentation_metric_core(); } else { *hfrag = 0; } @@ -46,11 +47,5 @@ void EspClass::getHeapStats(uint32_t* hfree, uint16_t* hmax, uint8_t* hfrag) uint8_t EspClass::getHeapFragmentation() { -#ifdef UMM_INLINE_METRICS - return (uint8_t)umm_fragmentation_metric(); -#else - uint8_t hfrag; - getHeapStats(nullptr, nullptr, &hfrag); - return hfrag; -#endif + return (uint8_t)umm_fragmentation_metric(); } diff --git a/cores/esp8266/umm_malloc/umm_info.c b/cores/esp8266/umm_malloc/umm_info.c index 3635414772..df879a1953 100644 --- a/cores/esp8266/umm_malloc/umm_info.c +++ b/cores/esp8266/umm_malloc/umm_info.c @@ -23,7 +23,7 @@ * ---------------------------------------------------------------------------- */ -UMM_HEAP_INFO ummHeapInfo; +// UMM_HEAP_INFO ummHeapInfo; void *umm_info( void *ptr, bool force ) { UMM_CRITICAL_DECL(id_info); @@ -41,7 +41,7 @@ void *umm_info( void *ptr, bool force ) { * Clear out all of the entries in the ummHeapInfo structure before doing * any calculations.. */ - memset( &ummHeapInfo, 0, sizeof( ummHeapInfo ) ); + memset( &_context->info, 0, sizeof( _context->info ) ); DBGLOG_FORCE( force, "\n" ); DBGLOG_FORCE( force, "+----------+-------+--------+--------+-------+--------+--------+\n" ); @@ -65,18 +65,18 @@ void *umm_info( void *ptr, bool force ) { while( UMM_NBLOCK(blockNo) & UMM_BLOCKNO_MASK ) { size_t curBlocks = (UMM_NBLOCK(blockNo) & UMM_BLOCKNO_MASK )-blockNo; - ++ummHeapInfo.totalEntries; - ummHeapInfo.totalBlocks += curBlocks; + ++_context->info.totalEntries; + _context->info.totalBlocks += curBlocks; /* Is this a free block? */ if( UMM_NBLOCK(blockNo) & UMM_FREELIST_MASK ) { - ++ummHeapInfo.freeEntries; - ummHeapInfo.freeBlocks += curBlocks; - ummHeapInfo.freeBlocksSquared += (curBlocks * curBlocks); + ++_context->info.freeEntries; + _context->info.freeBlocks += curBlocks; + _context->info.freeBlocksSquared += (curBlocks * curBlocks); - if (ummHeapInfo.maxFreeContiguousBlocks < curBlocks) { - ummHeapInfo.maxFreeContiguousBlocks = curBlocks; + if (_context->info.maxFreeContiguousBlocks < curBlocks) { + _context->info.maxFreeContiguousBlocks = curBlocks; } DBGLOG_FORCE( force, "|0x%08lx|B %5d|NB %5d|PB %5d|Z %5u|NF %5d|PF %5d|\n", @@ -98,8 +98,8 @@ void *umm_info( void *ptr, bool force ) { return( ptr ); } } else { - ++ummHeapInfo.usedEntries; - ummHeapInfo.usedBlocks += curBlocks; + ++_context->info.usedEntries; + _context->info.usedBlocks += curBlocks; DBGLOG_FORCE( force, "|0x%08lx|B %5d|NB %5d|PB %5d|Z %5u|\n", DBGLOG_32_BIT_PTR(&UMM_BLOCK(blockNo)), @@ -131,14 +131,14 @@ void *umm_info( void *ptr, bool force ) { DBGLOG_FORCE( force, "+----------+-------+--------+--------+-------+--------+--------+\n" ); DBGLOG_FORCE( force, "Total Entries %5d Used Entries %5d Free Entries %5d\n", - ummHeapInfo.totalEntries, - ummHeapInfo.usedEntries, - ummHeapInfo.freeEntries ); + _context->info.totalEntries, + _context->info.usedEntries, + _context->info.freeEntries ); DBGLOG_FORCE( force, "Total Blocks %5d Used Blocks %5d Free Blocks %5d\n", - ummHeapInfo.totalBlocks, - ummHeapInfo.usedBlocks, - ummHeapInfo.freeBlocks ); + _context->info.totalBlocks, + _context->info.usedBlocks, + _context->info.freeBlocks ); DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); @@ -149,11 +149,11 @@ void *umm_info( void *ptr, bool force ) { #if defined(UMM_STATS) || defined(UMM_STATS_FULL) #if !defined(UMM_INLINE_METRICS) - if (ummHeapInfo.freeBlocks == _context->stats.free_blocks) { + if (_context->info.freeBlocks == _context->stats.free_blocks) { DBGLOG_FORCE( force, "heap info Free blocks and heap statistics Free blocks match.\n"); } else { DBGLOG_FORCE( force, "\nheap info Free blocks %5d != heap statistics Free Blocks %5d\n\n", - ummHeapInfo.freeBlocks, + _context->info.freeBlocks, _context->stats.free_blocks ); } DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); @@ -170,20 +170,31 @@ void *umm_info( void *ptr, bool force ) { /* ------------------------------------------------------------------------ */ +size_t umm_free_heap_size_core( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return (size_t)_context->info.freeBlocks * sizeof(umm_block); +} + size_t umm_free_heap_size( void ) { #ifndef UMM_INLINE_METRICS umm_info(NULL, false); #endif - return (size_t)ummHeapInfo.freeBlocks * sizeof(umm_block); + + return umm_free_heap_size_core(); } //C Breaking change in upstream umm_max_block_size() was changed to //C umm_max_free_block_size() keeping old function name for (dot) releases. //C TODO: update at next major release. //C size_t umm_max_free_block_size( void ) { +size_t umm_max_block_size_core( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + return _context->info.maxFreeContiguousBlocks * sizeof(umm_block); +} + size_t umm_max_block_size( void ) { umm_info(NULL, false); - return ummHeapInfo.maxFreeContiguousBlocks * sizeof(umm_block); + return umm_max_block_size_core(); } /* @@ -195,46 +206,58 @@ int umm_usage_metric( void ) { #ifndef UMM_INLINE_METRICS umm_info(NULL, false); #endif - DBGLOG_DEBUG( "usedBlocks %d totalBlocks %d\n", umm_metrics.usedBlocks, ummHeapInfo.totalBlocks); - if (ummHeapInfo.freeBlocks) - return (int)((ummHeapInfo.usedBlocks * 100)/(ummHeapInfo.freeBlocks)); + + umm_heap_context_t *_context = umm_get_current_heap(); + +//C Note, umm_metrics also appears in the upstrean w/o definition. I suspect it is suppose to be ummHeapInfo. + // DBGLOG_DEBUG( "usedBlocks %d totalBlocks %d\n", umm_metrics.usedBlocks, ummHeapInfo.totalBlocks); + DBGLOG_DEBUG( "usedBlocks %d totalBlocks %d\n", _context->info.usedBlocks, _context->info.totalBlocks); + if (_context->info.freeBlocks) + return (int)((_context->info.usedBlocks * 100)/(_context->info.freeBlocks)); return -1; // no freeBlocks } uint32_t sqrt32 (uint32_t n); -int umm_fragmentation_metric( void ) { -#ifndef UMM_INLINE_METRICS - umm_info(NULL, false); -#endif - DBGLOG_DEBUG( "freeBlocks %d freeBlocksSquared %d\n", umm_metrics.freeBlocks, ummHeapInfo.freeBlocksSquared); - if (0 == ummHeapInfo.freeBlocks) { +int umm_fragmentation_metric_core( void ) { + umm_heap_context_t *_context = umm_get_current_heap(); + // DBGLOG_DEBUG( "freeBlocks %d freeBlocksSquared %d\n", umm_metrics.freeBlocks, ummHeapInfo.freeBlocksSquared); + DBGLOG_DEBUG( "freeBlocks %d freeBlocksSquared %d\n", _context->info.freeBlocks, _context->info.freeBlocksSquared); + if (0 == _context->info.freeBlocks) { return 0; } else { //upstream version: return (100 - (((uint32_t)(sqrtf(ummHeapInfo.freeBlocksSquared)) * 100)/(ummHeapInfo.freeBlocks))); - return (100 - (((uint32_t)(sqrt32(ummHeapInfo.freeBlocksSquared)) * 100)/(ummHeapInfo.freeBlocks))); + return (100 - (((uint32_t)(sqrt32(_context->info.freeBlocksSquared)) * 100)/(_context->info.freeBlocks))); } } +int umm_fragmentation_metric( void ) { +#ifndef UMM_INLINE_METRICS + umm_info(NULL, false); +#endif + + return umm_fragmentation_metric_core(); +} + #ifdef UMM_INLINE_METRICS -static void umm_fragmentation_metric_init( void ) { - ummHeapInfo.freeBlocks = UMM_NUMBLOCKS - 2; - ummHeapInfo.freeBlocksSquared = ummHeapInfo.freeBlocks * ummHeapInfo.freeBlocks; +static void umm_fragmentation_metric_init( umm_heap_context_t *_context ) { + _context->info.freeBlocks = UMM_NUMBLOCKS - 2; + _context->info.freeBlocksSquared = _context->info.freeBlocks * _context->info.freeBlocks; } -static void umm_fragmentation_metric_add( uint16_t c ) { +static void umm_fragmentation_metric_add( umm_heap_context_t *_context, uint16_t c ) { uint16_t blocks = (UMM_NBLOCK(c) & UMM_BLOCKNO_MASK) - c; DBGLOG_DEBUG( "Add block %d size %d to free metric\n", c, blocks); - ummHeapInfo.freeBlocks += blocks; - ummHeapInfo.freeBlocksSquared += (blocks * blocks); + _context->info.freeBlocks += blocks; + _context->info.freeBlocksSquared += (blocks * blocks); } -static void umm_fragmentation_metric_remove( uint16_t c ) { +static void umm_fragmentation_metric_remove( umm_heap_context_t *_context, uint16_t c ) { uint16_t blocks = (UMM_NBLOCK(c) & UMM_BLOCKNO_MASK) - c; DBGLOG_DEBUG( "Remove block %d size %d from free metric\n", c, blocks); - ummHeapInfo.freeBlocks -= blocks; - ummHeapInfo.freeBlocksSquared -= (blocks * blocks); + _context->info.freeBlocks -= blocks; + _context->info.freeBlocksSquared -= (blocks * blocks); } #endif // UMM_INLINE_METRICS diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index 74c516a082..2e4e417b27 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -15,7 +15,7 @@ UMM_TIME_STATS time_stats = { #ifdef UMM_INFO {0xFFFFFFFF, 0U, 0U, 0U}, #endif -#ifdef UMM_POISON_CHECK +#if defined(UMM_POISON_CHECK) || defined(UMM_POISON_CHECK_LITE) {0xFFFFFFFF, 0U, 0U, 0U}, #endif #ifdef UMM_INTEGRITY_CHECK @@ -96,7 +96,7 @@ static void *get_unpoisoned_check_neighbors( void *vptr, const char* file, int l UMM_CRITICAL_DECL(id_poison); uint16_t c; bool poison = false; - umm_heap_context_t *_context = umm_get_ptr_context( v_ptr ); + umm_heap_context_t *_context = umm_get_ptr_context( vptr ); if (NULL == _context) { panic(); return NULL; diff --git a/cores/esp8266/umm_malloc/umm_local.h b/cores/esp8266/umm_malloc/umm_local.h index a309886bf5..cb72d669c1 100644 --- a/cores/esp8266/umm_malloc/umm_local.h +++ b/cores/esp8266/umm_malloc/umm_local.h @@ -59,6 +59,9 @@ struct UMM_HEAP_CONTEXT { void *heap_end; #if (!defined(UMM_INLINE_METRICS) && defined(UMM_STATS)) || defined(UMM_STATS_FULL) UMM_STATISTICS stats; +#endif +#ifdef UMM_INFO + UMM_HEAP_INFO info; #endif unsigned short int numblocks; unsigned char id; diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 4d88a8c353..60455a860c 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -449,7 +449,7 @@ void umm_init_common( size_t id, void *start_addr, size_t size, bool zero ) { // post-crash discovery. if (zero) { memset(_context->heap, 0x00, size); -#if defined(UMM_STATS) || defined(UMM_STATS_FULL) +#if (!defined(UMM_INLINE_METRICS) && defined(UMM_STATS)) || defined(UMM_STATS_FULL) memset(&_context->stats, 0x00, sizeof(_context->stats)); #endif diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index cacb47d2cb..6d24bfb8f9 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -195,9 +195,9 @@ extern char _heap_start[]; /* -------------------------------------------------------------------------- */ #ifdef UMM_INLINE_METRICS - #define UMM_FRAGMENTATION_METRIC_INIT() umm_fragmentation_metric_init() - #define UMM_FRAGMENTATION_METRIC_ADD(c) umm_fragmentation_metric_add(c) - #define UMM_FRAGMENTATION_METRIC_REMOVE(c) umm_fragmentation_metric_remove(c) + #define UMM_FRAGMENTATION_METRIC_INIT() umm_fragmentation_metric_init(_context) + #define UMM_FRAGMENTATION_METRIC_ADD(c) umm_fragmentation_metric_add(_context, c) + #define UMM_FRAGMENTATION_METRIC_REMOVE(c) umm_fragmentation_metric_remove(_context, c) #ifndef UMM_INFO #define UMM_INFO #endif @@ -231,14 +231,14 @@ extern char _heap_start[]; unsigned int freeBlocksSquared; #ifdef UMM_INLINE_METRICS size_t oom_count; - #define UMM_OOM_COUNT ummHeapInfo.oom_count - #define UMM_FREE_BLOCKS ummHeapInfo.freeBlocks + #define UMM_OOM_COUNT info.oom_count + #define UMM_FREE_BLOCKS info.freeBlocks #endif unsigned int maxFreeContiguousBlocks; } UMM_HEAP_INFO; - extern UMM_HEAP_INFO ummHeapInfo; + // extern UMM_HEAP_INFO ummHeapInfo; extern ICACHE_FLASH_ATTR void *umm_info( void *ptr, bool force ); #ifdef UMM_INLINE_METRICS @@ -250,12 +250,18 @@ extern char _heap_start[]; extern ICACHE_FLASH_ATTR size_t umm_max_block_size( void ); extern ICACHE_FLASH_ATTR int umm_usage_metric( void ); extern ICACHE_FLASH_ATTR int umm_fragmentation_metric( void ); + extern ICACHE_FLASH_ATTR size_t umm_free_heap_size_core( void ); + extern ICACHE_FLASH_ATTR size_t umm_max_block_size_core( void ); + extern ICACHE_FLASH_ATTR int umm_fragmentation_metric_core( void ); #else #define umm_info(p,b) #define umm_free_heap_size() (0) #define umm_max_block_size() (0) #define umm_fragmentation_metric() (0) #define umm_usage_metric() (0) + #define umm_free_heap_size_core() (0) + #define umm_max_block_size_core() (0) + #define umm_fragmentation_metric_core() (0) #endif struct UMM_HEAP_CONTEXT; From 74df810b862ebf44c8203a156a3899a71526fc73 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 12 Jul 2020 19:16:41 -0700 Subject: [PATCH 24/48] Changes to clear errors and warnings from toolchain 10.1 Several fixes and improvements to example MMU48K. With the improved optimization in toolchain 10.1 The example divide by 0 exception was failing with a HWDT event instead of its exception handler. The compiler saw the obscured divide by 0 and replaced it with a break point. --- cores/esp8266/core_esp8266_non32xfer.cpp | 2 +- cores/esp8266/exc-c-wrapper-handler.S | 4 +- cores/esp8266/mmu_iram.cpp | 8 ++-- libraries/esp8266/examples/MMU48K/MMU48K.ino | 40 ++++++++++++++------ 4 files changed, 35 insertions(+), 19 deletions(-) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index ff548112fe..0c5312e78f 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -212,7 +212,7 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, #if defined(USE_ISR_SAFE_EXC_WRAPPER) -constexpr _xtos_handler ROM_xtos_c_wrapper_handler = (_xtos_handler)0x40000598; +#define ROM_xtos_c_wrapper_handler (reinterpret_cast<_xtos_handler>(0x40000598)) static void IRAM_ATTR _set_exception_handler_wrapper(uint32_t cause) { _xtos_handler old_wrapper = _xtos_exc_handler_table[cause]; diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S index c71e93fc03..646af756cf 100644 --- a/cores/esp8266/exc-c-wrapper-handler.S +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -65,7 +65,9 @@ _xtos_c_wrapper_handler: // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1 // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__) - movi a2, 0x23 // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +// movi a2, 0x23 // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +// @mhightower83 - testing to see if we need INTLEVEL 15 instead of 3 + movi a2, 0x2F // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) rsr a3, EPC_1 // @mhightower83 - I assume PS.EXCM was set and now is being cleared, thus // allowing new exceptions and interrupts within PS_INTLEVEL to be possible. diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 420bf7bc30..33822bed0a 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -96,12 +96,11 @@ mmu_cre_status_t mmu_status = {SOC_CACHE_SIZE, -1, 0, 0, 0, 0, 0}; */ #ifndef ROM_Cache_Read_Enable -#define ROM_Cache_Read_Enable 0x40004678 +#define ROM_Cache_Read_Enable 0x40004678U #endif typedef void (*fp_Cache_Read_Enable_t)(uint8_t map, uint8_t p, uint8_t v); -constexpr fp_Cache_Read_Enable_t real_Cache_Read_Enable = - (fp_Cache_Read_Enable_t)ROM_Cache_Read_Enable; +#define real_Cache_Read_Enable (reinterpret_cast(ROM_Cache_Read_Enable)) void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { mmu_status.map = map; @@ -125,8 +124,7 @@ void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { #endif typedef void (*fp_Cache_Read_Disable_t)(void); -constexpr fp_Cache_Read_Disable_t real_Cache_Read_Disable = - (fp_Cache_Read_Disable_t)ROM_Cache_Read_Disable; +#define real_Cache_Read_Disable (reinterpret_cast(ROM_Cache_Read_Disable)) /* * */ diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 8c634a7324..710c5a4330 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -4,6 +4,16 @@ uint32_t timed_byte_read(char *pc, uint32_t * o); uint32_t timed_byte_read2(char *pc, uint32_t * o); +int divideA_B(int a, int b); + +int* nullPointer = NULL; + +char *probe_b = NULL; +short *probe_s = NULL; +char *probe_c = (char *)0x40110000; +short *unaligned_probe_s = NULL; + +uint32_t read_var = 0x11223344; #define GET_BYTE_FN(name,wo,bo) \ static inline char get ## name(void *o) { \ @@ -132,11 +142,12 @@ void setup() { { HeapSelectIram ephemeral; // Serial.printf_P(PSTR("ESP.getFreeHeap(): %u\n"), ESP.getFreeHeap()); - gobble_sz = ESP.getFreeHeap(); // - 4096; + gobble_sz = ESP.getFreeHeap() - UMM_OVERHEAD_ADJUST; // - 4096; gobble = (uint32_t *)malloc(gobble_sz); } - Serial.printf_P(PSTR("gobble_sz: %u\n"), gobble_sz); - Serial.printf_P(PSTR("gobble: %p\n"), gobble); + Serial.printf_P(PSTR("\nmalloc() from IRAM Heap:\n")); + Serial.printf_P(PSTR(" gobble_sz: %u\n"), gobble_sz); + Serial.printf_P(PSTR(" gobble: %p\n"), gobble); #elif defined(MMU_SEC_HEAP) gobble = (uint32_t *)MMU_SEC_HEAP; @@ -158,17 +169,15 @@ void setup() { #endif // Lets peak over the edge + Serial.printf_P(PSTR("\nPeek over the edge of memory at 0x4010C000\n")); dump_mem32((void *)(0x4010C000 - 16 * 4), 32); -} -int* nullPointer = NULL; + probe_b = (char *)gobble; + probe_s = (short *)((uintptr_t)gobble); + unaligned_probe_s = (short *)((uintptr_t)gobble + 1); -char *probe_b = (char *)gobble; -short *probe_s = (short *)((uintptr_t)gobble); -char *probe_c = (char *)0x40110000; -short *unaligned_probe_s = (short *)((uintptr_t)gobble + 1); +} -uint32_t read_var = 0x11223344; extern uint32_t mmu_non32xfer_count; @@ -286,11 +295,19 @@ void processKey(Print& out, int hotKey) { out.println(F(" t - exception vs inline method timing info.")); out.println(F(" ? - Print Help")); out.println(); +#if defined(NON32XFER_HANDLER) + out.println(F("Test exception handling with non-32 bit transfer handler:")); +#else out.println(F("Crash with:")); +#endif out.println(F(" b - read byte, Load/Store exception")); out.println(F(" B - write byte, Load/Store exception")); out.println(F(" s - read short, Load/Store exception")); out.println(F(" S - write short, Load/Store exception")); +#if defined(NON32XFER_HANDLER) + out.println(); + out.println(F("Crash with:")); +#endif out.println(F(" c - read byte, Load/Store exception outside of handler range")); out.println(F(" 9 - read short, Unaligned exception")); @@ -301,7 +318,6 @@ void processKey(Print& out, int hotKey) { default: out.printf_P(PSTR("\"%c\" - Not an option? / ? - help"), hotKey); out.println(); - processKey(out, '?'); break; } } @@ -319,7 +335,7 @@ void loop() { } -int divideA_B(int a, int b) { +int __attribute__((noinline)) divideA_B(int a, int b) { return (a / b); } From b767a5d012d92532fa13ec27703ca2eb42f300af Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 13 Jul 2020 22:43:46 -0700 Subject: [PATCH 25/48] Isolated incompatable definitions related to _xtos_set_exception_handler. GDBSTUB definitions are different from the BootROM's. --- cores/esp8266/esp8266_undocumented.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index 8ff33e508e..f568f15427 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -37,6 +37,14 @@ extern int ets_uart_printf(const char *format, ...) __attribute__ ((format (prin extern void ets_delay_us(uint32_t us); +#ifndef GDBSTUB_H +/* + GDBSTUB duplicates these with some variances that are not compatible with our + references (offsets), which are synced with those used by the BootROM. In + particular, the BootROM does not have register "a1" in the structure where + GDBSTUB does. +*/ + /* The Xtensa OS code in ROM for handling hardware exceptions */ struct __exception_frame { @@ -118,6 +126,8 @@ struct __exception_frame typedef void (*fn_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); +#endif + /* Added to eagle.rom.addr.v6.ld PROVIDE ( _xtos_exc_handler_table = 0x3fffc000 ); From e7402d81d80a96bbed26612e92dcbdfdad9f8a32 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Fri, 17 Jul 2020 13:49:19 -0700 Subject: [PATCH 26/48] Update tools/platformio-build.py Co-authored-by: Max Prokhorov --- tools/platformio-build.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tools/platformio-build.py b/tools/platformio-build.py index 4e79a96916..16ccaddc54 100644 --- a/tools/platformio-build.py +++ b/tools/platformio-build.py @@ -260,9 +260,13 @@ def scons_patched_match_splitext(path, suffixes=None): assert current_vtables current_mmu_iram_size = None -for d in flatten_cppdefines: - if str(d).startswith("MMU_IRAM_SIZE"): - current_mmu_iram_size = d +for flag in env["CPPDEFINES"]: + try: + d, val = flag + if str(d).startswith("MMU_IRAM_SIZE"): + current_mmu_iram_size = "{}={}".format(d, val) + except ValueError: + continue if not current_mmu_iram_size: current_mmu_iram_size = "MMU_IRAM_SIZE=0x8000" env.Append(CPPDEFINES=[current_mmu_iram_size]) From 232dce46b57c7e92c509d1ed1013dd3d6c8c8338 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 19 Jul 2020 10:53:43 -0700 Subject: [PATCH 27/48] Requested changes Changed mmu related usages of ETS_... defines to DBG_MMU_... Cleanup in example MMU48K.ino. Removed stale memory reference macro and mmu_status print statement. Cleanup printf '\n' to be '\r\n'. Improved issolation of development debug prints from the rest of the debug prints. --- bootloaders/eboot/eboot.c | 2 + cores/esp8266/Esp.h | 1 - cores/esp8266/StackThunk.cpp | 10 +- cores/esp8266/core_esp8266_main.cpp | 6 +- cores/esp8266/core_esp8266_non32xfer.cpp | 22 +++- cores/esp8266/mmu_iram.cpp | 17 ++- cores/esp8266/mmu_iram.h | 103 +++++++++--------- cores/esp8266/umm_malloc/umm_heap_select.h | 78 +++++++++++++ cores/esp8266/umm_malloc/umm_malloc.cpp | 13 +-- cores/esp8266/umm_malloc/umm_malloc.h | 72 ------------ .../src/WiFiClientSecureBearSSL.cpp | 29 ++--- libraries/esp8266/examples/MMU48K/MMU48K.ino | 41 ++----- libraries/esp8266/examples/MMU48K/timed.cpp | 2 +- .../esp8266/examples/irammem/irammem.ino | 26 +++-- 14 files changed, 220 insertions(+), 202 deletions(-) create mode 100644 cores/esp8266/umm_malloc/umm_heap_select.h diff --git a/bootloaders/eboot/eboot.c b/bootloaders/eboot/eboot.c index ad4752085b..87f8a47668 100644 --- a/bootloaders/eboot/eboot.c +++ b/bootloaders/eboot/eboot.c @@ -68,6 +68,8 @@ int load_app_from_flash_raw(const uint32_t flash_addr) load = true; } + // The final IRAM size, once boot has completed, can be either 32K or 48K. + // Allow for the higher in range testing. if (address >= 0x40100000 && address < 0x4010C000) { load = true; } diff --git a/cores/esp8266/Esp.h b/cores/esp8266/Esp.h index 2e5c362871..796a490ccb 100644 --- a/cores/esp8266/Esp.h +++ b/cores/esp8266/Esp.h @@ -177,7 +177,6 @@ class EspClass { void setDramHeap(); void setIramHeap(); void setExternalHeap(); - void setInternalHeap() {setDramHeap();}; // depricated void resetHeap(); private: #ifdef UMM_HEAP_EXTERNAL diff --git a/cores/esp8266/StackThunk.cpp b/cores/esp8266/StackThunk.cpp index 38247ae584..be50211c4b 100644 --- a/cores/esp8266/StackThunk.cpp +++ b/cores/esp8266/StackThunk.cpp @@ -32,6 +32,7 @@ #include "StackThunk.h" #include #include +#include extern "C" { @@ -49,10 +50,15 @@ void stack_thunk_add_ref() { stack_thunk_refcnt++; if (stack_thunk_refcnt == 1) { - ETS_PRINTF("\nStackThunk malloc(%u)\n", _stackSize * sizeof(uint32_t)); + DBG_MMU_PRINTF("\nStackThunk malloc(%u)\n", _stackSize * sizeof(uint32_t)); + // The stack must be in DRAM, or an HWDT will follow. I am not sure why + // maybe an exception handler hits a non32-bit access exception. Or too much + // time is consumed in a non32-bit exception handler with IRQs off. Also, + // interrupt handling on an IRAM stack would greatly slow an ISR handler + // with interrupts turned off. HeapSelectDram ephemeral; stack_thunk_ptr = (uint32_t *)malloc(_stackSize * sizeof(uint32_t)); - ETS_PRINTF("StackThunk stack_thunk_ptr: %p\n", stack_thunk_ptr); + DBG_MMU_PRINTF("StackThunk stack_thunk_ptr: %p\n", stack_thunk_ptr); if (!stack_thunk_ptr) { // This is a fatal error, stop the sketch DEBUGV("Unable to allocate BearSSL stack\n"); diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 84771e6bc6..1d62ea6d4c 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -311,11 +311,13 @@ extern "C" void app_entry_redefinable(void) cont_t s_cont __attribute__((aligned(16))); g_pcont = &s_cont; +#ifdef DEV_DEBUG_MMU_IRAM DBG_MMU_PRINT_STATUS(); DBG_MMU_PRINT_IRAM_BANK_REG(0, ""); DBG_MMU_PRINTF("\nCall call_user_start()\n"); +#endif /* Call the entry point of the SDK code. */ call_user_start(); @@ -344,11 +346,11 @@ extern "C" void user_init(void) { initVariant(); - // experimental::initFlashQuirks(); // Chip specific flash init. + experimental::initFlashQuirks(); // Chip specific flash init. cont_init(g_pcont); -#if defined(NON32XFER_HANDLER) +#if defined(NON32XFER_HANDLER) || defined(MMU_IRAM_HEAP) install_non32xfer_exception_handler(); #endif #if defined(MMU_IRAM_HEAP) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 0c5312e78f..d6713ff2c3 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -52,10 +52,11 @@ uint32_t mmu_non32xfer_withinisr_count = 0; // #define DEBUG_WARNING +//C Do we want to keep this warning #ifdef DEBUG_WARNING static void warning(void) { - ETS_PRINTF("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); + DBG_MMU_PRINTF("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); } #endif @@ -95,16 +96,27 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, turned back on by _xtos_c_wrapper_handler. Is there something about an exception that would prevent the CPU from servicing an interrupt while in an exception handler? + + New interrupts are blocked by EXCM being set. Once cleared, interrupts + above the current INTLEVEL and exceptions (w/o creating a DoubleException) + can occur. With USE_ISR_SAFE_EXC_WRAPPER, INTLEVEL is raised to 15 with + EXCM cleared. The original ROM _xtos_c_wrapper_handler: set INTLEVEL to 1 + with EXCM cleared, saved registers, then did an rsil 0, and called the + registerd C Exception handler with interrupts fully enabled! + Our replacement keeps INTLEVEL at 15. This must be done for umm_malloc to + safely work with an IRAM heap from an ISR call. */ + //C Should we make defined(USE_ISR_SAFE_EXC_WRAPPER) the only build path if (ef->ps & 0x0F) { #if !defined(USE_ISR_SAFE_EXC_WRAPPER) if (0 == mmu_non32xfer_withinisr_count) { - ETS_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); + DBG_MMU_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); #if 0 continue; /* fail, not safe for IRQ disabled ?? */ #endif } #endif + //C Do we want to keep this tracking if (0 == ++mmu_non32xfer_withinisr_count) { --mmu_non32xfer_withinisr_count; // saturated } @@ -129,12 +141,14 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, } #ifdef DEBUG_WARNING + //C Do we want to keep this warning if (0 == mmu_non32xfer_count) { // This may be causing some issues TODO retest with umm_malloc within // interrupt context. schedule_function(warning); } #endif + //C Do we want to keep this tracking // Some accounting information so we know this is happending. if (0 == ++mmu_non32xfer_count) { --mmu_non32xfer_count; // saturated @@ -152,7 +166,7 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, __asm("rsr %0, EXCVADDR;" :"=r"(excvaddr)::); /* debug option, validate address so we don't hide memory access bugs in APP */ - if (is_iram(excvaddr) || (is_read && is_icache(excvaddr))) { + if (is_iram((void *)excvaddr) || (is_read && is_icache((void *)excvaddr))) { /* all is good */ } else { continue; /* fail */ @@ -196,7 +210,7 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, problem; however, my test case shows no problem ?? Maybe I was confused. */ if (old_handler) { // if (0 == (ef->ps & 0x0F)) { - ETS_PRINTF("\ncalling previous load/store handler(%p)\n", old_handler); + DBG_MMU_PRINTF("\ncalling previous load/store handler(%p)\n", old_handler); old_handler(ef, cause); return; } diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 33822bed0a..8de64d3571 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -28,12 +28,12 @@ extern "C" { #define SOC_CACHE_SIZE 1 // 32KB #endif -// IS this set as part of segment data at load time? appears to be +#ifdef DEV_DEBUG_MMU_IRAM +// Is this set as part of segment data at load time? appears to be mmu_cre_status_t mmu_status = {SOC_CACHE_SIZE, -1, 0, 0, 0, 0, 0}; +#endif -//C Enable all the time so we can gather information on Cache_Read_Enable usage. -//+ #if (MMU_ICACHE_SIZE == 0x4000) -#if 1 //D +#if (MMU_ICACHE_SIZE == 0x4000) /* * "Cache_Read_Enable" as in Instruction Read Cache enable, ICACHE. * @@ -103,6 +103,8 @@ typedef void (*fp_Cache_Read_Enable_t)(uint8_t map, uint8_t p, uint8_t v); #define real_Cache_Read_Enable (reinterpret_cast(ROM_Cache_Read_Enable)) void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { + (void)v; +#ifdef DEV_DEBUG_MMU_IRAM mmu_status.map = map; mmu_status.p = p; mmu_status.v = v; @@ -111,6 +113,7 @@ void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { if (0 == mmu_status.enable_count) { mmu_status.enable_count--; // keep saturated value } +#endif DBG_MMU_PRINT_IRAM_BANK_REG("before", "Enable"); real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); @@ -129,11 +132,13 @@ typedef void (*fp_Cache_Read_Disable_t)(void); * */ void IRAM_ATTR Cache_Read_Disable(void) { +#ifdef DEV_DEBUG_MMU_IRAM mmu_status.disable_count++; mmu_status.state = 0; if (0 == mmu_status.disable_count) { mmu_status.disable_count--; // keep saturated value } +#endif DBG_MMU_PRINT_IRAM_BANK_REG("before", "Disable"); real_Cache_Read_Disable(); @@ -145,7 +150,7 @@ void IRAM_ATTR Cache_Read_Disable(void) { #ifdef DEV_DEBUG_PRINT /* * Early adjustment for CPU crystal frequency, so debug printing will work. - * This should not be left enabled all the time in Crash_Read..., I am concerned + * This should not be left enabled all the time in Cashe_Read..., I am concerned * that there may be unknown interference with the NONOS SDK startup. * * Inspired by: @@ -173,6 +178,8 @@ extern "C" void IRAM_ATTR set_pll(void) } } +//C This was used to probe at different stages of boot the state of the PLL +//C register. I think we can get rid of this one. extern "C" void IRAM_ATTR dbg_set_pll(void) { char r103_4_1 = rom_i2c_readReg(103,4,1); diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index c5426ef473..ad745e883f 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -36,8 +36,9 @@ #define DEV_DEBUG_PRINT */ +//C This turns on range checking. Is this the value you want to trigger it? #ifdef DEBUG_ESP_CORE -#define DEBUG_MMU +#define DEBUG_ESP_MMU #endif /* @@ -46,32 +47,30 @@ */ #define USE_ISR_SAFE_EXC_WRAPPER -#if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_MMU) +#if defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) #include -#if defined( DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) +#define DBG_MMU_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {} + +#if defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) extern "C" void set_pll(void); extern "C" void dbg_set_pll(void); -#define SET_PLL() set_pll() + +#define DBG_MMU_PRINTF(fmt, ...) \ +set_pll(); \ +uart_buff_switch(0); \ +ets_uart_printf(fmt, ##__VA_ARGS__); \ +DBG_MMU_FLUSH(0) #else -#define SET_PLL() do {} while(false) +// ! defined(DEBUG_ESP_MMU) +#define DBG_MMU_PRINTF(fmt, ...) ets_uart_printf(fmt, ##__VA_ARGS__) #endif -#define ETS_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {} - -#define ETS_PRINTF(fmt, ...) \ - SET_PLL(); \ - uart_buff_switch(0); \ - ets_uart_printf(fmt, ##__VA_ARGS__); \ - ETS_FLUSH(0) - -#else // ! DEV_DEBUG_PRINT -#define ETS_FLUSH(...) do {} while(false) -#define ETS_PRINTF(...) do {} while(false) -#endif // DEV_DEBUG_PRINT - -#define DBG_MMU_PRINTF ETS_PRINTF +#else // ! defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) +#define DBG_MMU_FLUSH(...) do {} while(false) +#define DBG_MMU_PRINTF(...) do {} while(false) +#endif // defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) #ifdef DEV_DEBUG_MMU_IRAM #define DBG_MMU_PRINT_STATUS() { \ @@ -81,7 +80,7 @@ extern "C" void dbg_set_pll(void); mmu_status.v_cfg, mmu_status.state, \ mmu_status.enable_count, mmu_status.disable_count, \ mmu_status.map, mmu_status.p, mmu_status.v); \ - ETS_FLUSH(0); \ + DBG_MMU_FLUSH(0); \ } #define DBG_MMU_PRINT_IRAM_BANK_REG(a, b) { \ @@ -99,6 +98,7 @@ extern "C" void dbg_set_pll(void); extern "C" { #endif +#ifdef DEV_DEBUG_MMU_IRAM typedef struct MMU_CRE_STATUS { uint32_t v_cfg; int32_t state; // -1 - not initialized, 0 - disabled, 1 - enabled @@ -110,62 +110,61 @@ typedef struct MMU_CRE_STATUS { } mmu_cre_status_t; extern mmu_cre_status_t mmu_status; +#endif +#ifdef DEBUG_ESP_MMU -#ifdef DEBUG_MMU - -static inline bool is_iram(uint32_t addr) { -// constexpr uint32_t _start = 0x40100000UL; -#define IRAM_START 0x40100000UL -#ifndef MMU_IRAM_SIZE -#define MMU_IRAM_SIZE 0x8000UL -#endif -#define IRAM_END (IRAM_START + MMU_IRAM_SIZE) +static inline bool is_iram(const void *addr) { + #define IRAM_START 0x40100000UL + #ifndef MMU_IRAM_SIZE + #error "MMU_IRAM_SIZE was undefined!" + #endif + #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) - return (IRAM_START <= addr && IRAM_END > addr); + return (IRAM_START <= (uint32_t)addr && IRAM_END > (uint32_t)addr); } -static inline bool is_dram(uint32_t addr) { - // constexpr uint32_t _start = 0x3FF80000UL; - // constexpr uint32_t _end = 0x40000000UL; - return (0x3FF80000UL <= addr && 0x40000000UL > addr); +static inline bool is_dram(const void *addr) { + #define DRAM_START 0x3FF80000UL + #define DRAM_END 0x40000000UL + + return (DRAM_START <= (uint32_t)addr && DRAM_END > (uint32_t)addr); } -static inline bool is_icache(uint32_t addr) { - // constexpr uint32_t _start = 0x40200000UL; - // constexpr uint32_t _end = _start + 0x100000UL; +static inline bool is_icache(const void *addr) { #define ICACHE_START 0x40200000UL #define ICACHE_END (ICACHE_START + 0x100000UL) - return (ICACHE_START <= addr && ICACHE_END > addr); + + return (ICACHE_START <= (uint32_t)addr && ICACHE_END > (uint32_t)addr); } #else -static inline bool is_iram(uint32_t addr) { +static inline bool is_iram(const void *addr) { (void)addr; return true; } -static inline bool is_dram(uint32_t addr) { +static inline bool is_dram(const void *addr) { (void)addr; return true; } -static inline bool is_icache(uint32_t addr) { +static inline bool is_icache(const void *addr) { (void)addr; return true; } -#endif // #ifdef DEBUG_MMU +#endif // #ifdef DEBUG_ESP_MMU -#ifdef DEBUG_MMU +#ifdef DEBUG_ESP_MMU #define ASSERT_RANGE_TEST_WRITE(a) \ - if (is_iram((uint32_t)a) || is_dram((uint32_t)a)) { \ + if (is_iram(a) || is_dram(a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ assert(("Outside of Range - Write" && false)); \ } #define ASSERT_RANGE_TEST_READ(a) \ - if (is_iram((uint32_t)a) || is_dram((uint32_t)a) || is_icache((uint32_t)a)) { \ + if (is_iram(a) || is_dram(a) || is_icache(a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ assert(("Outside of Range - Read" && false)); \ @@ -181,7 +180,7 @@ static inline bool is_icache(uint32_t addr) { * iCACHE data elements. These remove the extra time and stack space that would * have occured by relying on exception processing. */ -static inline uint8_t get_uint8_iram(const void *p8) { +static inline uint8_t mmu_get_uint8(const void *p8) { ASSERT_RANGE_TEST_READ(p8); uint32_t val = (*(uint32_t *)((uintptr_t)p8 & ~0x3)); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; @@ -189,7 +188,7 @@ static inline uint8_t get_uint8_iram(const void *p8) { return (uint8_t)val; } -static inline uint16_t get_uint16_iram(const unsigned short *p16) { +static inline uint16_t mmu_get_uint16(const unsigned short *p16) { ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; @@ -197,7 +196,7 @@ static inline uint16_t get_uint16_iram(const unsigned short *p16) { return (uint16_t)val; } -static inline int16_t get_int16_iram(const short *p16) { +static inline int16_t mmu_get_int16(const short *p16) { ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; @@ -205,9 +204,7 @@ static inline int16_t get_int16_iram(const short *p16) { return (int16_t)val; } - - -static inline uint8_t set_uint8_iram(void *p8, const uint8_t val) { +static inline uint8_t mmu_set_uint8(void *p8, const uint8_t val) { ASSERT_RANGE_TEST_WRITE(p8); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; uint32_t sval = val << pos; @@ -221,7 +218,7 @@ static inline uint8_t set_uint8_iram(void *p8, const uint8_t val) { return val; } -static inline uint16_t set_uint16_iram(unsigned short *p16, const uint16_t val) { +static inline uint16_t mmu_set_uint16(unsigned short *p16, const uint16_t val) { ASSERT_RANGE_TEST_WRITE(p16); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; uint32_t sval = val << pos; @@ -235,7 +232,7 @@ static inline uint16_t set_uint16_iram(unsigned short *p16, const uint16_t val) return val; } -static inline int16_t set_int16_iram(short *p16, const int16_t val) { +static inline int16_t mmu_set_int16(short *p16, const int16_t val) { ASSERT_RANGE_TEST_WRITE(p16); uint32_t sval = (uint16_t)val; uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; diff --git a/cores/esp8266/umm_malloc/umm_heap_select.h b/cores/esp8266/umm_malloc/umm_heap_select.h new file mode 100644 index 0000000000..4c9150819f --- /dev/null +++ b/cores/esp8266/umm_malloc/umm_heap_select.h @@ -0,0 +1,78 @@ +#ifndef UMM_MALLOC_SELECT_H +#define UMM_MALLOC_SELECT_H + +#include + +/* + This class is modeled after interrupts.h + + HeapSelectIram is used to temporarily select an alternate Heap. + + { + { + HeapSelectIram lock; + // allocate memory here + } + allocations here are from the old Heap selection + } + */ + +class HeapSelect { +public: +#if (UMM_NUM_HEAPS == 1) + HeapSelect(size_t id) { (void)id; } + ~HeapSelect() {} +#else + HeapSelect(size_t id) : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(id); + } + + ~HeapSelect() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; +#endif +}; + +class HeapSelectIram { +public: +#ifdef UMM_HEAP_IRAM + HeapSelectIram() : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(UMM_HEAP_IRAM); + } + + ~HeapSelectIram() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; + +#else + HeapSelectIram() {} + ~HeapSelectIram() {} +#endif +}; + +class HeapSelectDram { +public: +#if (UMM_NUM_HEAPS == 1) + HeapSelectDram() {} + ~HeapSelectDram() {} +#else + HeapSelectDram() : _heap_id(umm_get_current_heap_id()) { + umm_set_heap_by_id(UMM_HEAP_DRAM); + } + + ~HeapSelectDram() { + umm_set_heap_by_id(_heap_id); + } + +protected: + size_t _heap_id; +#endif +}; + +#endif // UMM_MALLOC_SELECT_H diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index ae81b6b7ae..12b22af5c5 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -471,22 +471,21 @@ void umm_init( void ) { } #ifdef UMM_HEAP_IRAM -#include - void umm_init_iram_ex( void *addr, unsigned int size, bool zero ) { /* We need the main, internal heap set up first */ UMM_INIT_HEAP; - /* Required to use umm_malloc on iRAM */ - install_non32xfer_exception_handler(); - - // umm_init_common(UMM_HEAP_IRAM, addr, size); umm_init_common(UMM_HEAP_IRAM, addr, size, zero); } void _text_end(void); void umm_init_iram(void) __attribute__((weak)); +/* + By using a weak link, it is possible to reduce the IRAM heap size with a + user-supplied init function. This would allow the creation of a block of IRAM + dedicated to a sketch and possibly used/preserved across reboots. + */ void umm_init_iram(void) { umm_init_iram_ex(mmu_sec_heap(), mmu_sec_heap_size(), true); } @@ -494,7 +493,7 @@ void umm_init_iram(void) { #ifdef UMM_HEAP_EXTERNAL void umm_init_vm( void *vmaddr, unsigned int vmsize ) { - /* We need the main, internal heap set up first */ + /* We need the main, internal (DRAM) heap set up first */ UMM_INIT_HEAP; umm_init_common(UMM_HEAP_EXTERNAL, vmaddr, vmsize, true); diff --git a/cores/esp8266/umm_malloc/umm_malloc.h b/cores/esp8266/umm_malloc/umm_malloc.h index 853782bc89..cdc38899f8 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.h +++ b/cores/esp8266/umm_malloc/umm_malloc.h @@ -44,77 +44,5 @@ extern size_t umm_get_current_heap_id(void); #ifdef __cplusplus } #endif -/* - This is pattered after interrupts.h - - HeapSelectIram is used to temporarily select an alternate Heap. - - { - { - HeapSelectIram lock; - // allocate memory here - } - allocations here are from the old Heap selection - } - */ - -class HeapSelect { -public: -#if (UMM_NUM_HEAPS == 1) - HeapSelect(size_t id) { (void)id; } - ~HeapSelect() {} -#else - HeapSelect(size_t id) : _heap_id(umm_get_current_heap_id()) { - umm_set_heap_by_id(id); - } - - ~HeapSelect() { - umm_set_heap_by_id(_heap_id); - } - -protected: - size_t _heap_id; -#endif -}; - -class HeapSelectIram { -public: -#ifdef UMM_HEAP_IRAM - HeapSelectIram() : _heap_id(umm_get_current_heap_id()) { - umm_set_heap_by_id(UMM_HEAP_IRAM); - } - - ~HeapSelectIram() { - umm_set_heap_by_id(_heap_id); - } - -protected: - size_t _heap_id; - -#else - HeapSelectIram() {} - ~HeapSelectIram() {} -#endif -}; - -class HeapSelectDram { -public: -#if (UMM_NUM_HEAPS == 1) - HeapSelectDram() {} - ~HeapSelectDram() {} -#else - HeapSelectDram() : _heap_id(umm_get_current_heap_id()) { - umm_set_heap_by_id(UMM_HEAP_DRAM); - } - - ~HeapSelectDram() { - umm_set_heap_by_id(_heap_id); - } - -protected: - size_t _heap_id; -#endif -}; - #endif /* UMM_MALLOC_H */ diff --git a/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp b/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp index 88a2ad39de..521a3b5ce3 100644 --- a/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp +++ b/libraries/ESP8266WiFi/src/WiFiClientSecureBearSSL.cpp @@ -47,6 +47,7 @@ extern "C" { #include "coredecls.h" #include #include +#include #if !CORE_MOCK @@ -1067,14 +1068,16 @@ bool WiFiClientSecure::_connectSSL(const char* hostName) { _sc = std::make_shared(); _eng = &_sc->eng; // Allocation/deallocation taken care of by the _sc shared_ptr - { // ESP.setIramHeap(); + //C This was borrowed from @earlephilhower PoC, to exemplify the use of IRAM. + //C Is this something we want to keep in the final release? + { // ESP.setIramHeap(); would be an alternative to using a class to set a scope for IRAM usage. HeapSelectIram ephemeral; _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); - ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); - ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); - ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); - ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + DBG_MMU_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + DBG_MMU_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + DBG_MMU_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + DBG_MMU_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); } // ESP.resetHeap(); if (!_sc || !_iobuf_in || !_iobuf_out) { @@ -1194,10 +1197,10 @@ bool WiFiClientSecure::_connectSSLServerRSA(const X509List *chain, HeapSelectIram ephemeral; _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); - ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); - ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); - ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); - ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + DBG_MMU_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + DBG_MMU_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + DBG_MMU_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + DBG_MMU_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); } // ESP.resetHeap(); if (!_sc_svr || !_iobuf_in || !_iobuf_out) { @@ -1238,10 +1241,10 @@ bool WiFiClientSecure::_connectSSLServerEC(const X509List *chain, HeapSelectIram ephemeral; _iobuf_in = std::shared_ptr(new unsigned char[_iobuf_in_size], std::default_delete()); _iobuf_out = std::shared_ptr(new unsigned char[_iobuf_out_size], std::default_delete()); - ETS_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); - ETS_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); - ETS_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); - ETS_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); + DBG_MMU_PRINTF("\n_iobuf_in: %p\n", _iobuf_in.get()); + DBG_MMU_PRINTF( "_iobuf_out: %p\n", _iobuf_out.get()); + DBG_MMU_PRINTF( "_iobuf_in_size: %u\n", _iobuf_in_size); + DBG_MMU_PRINTF( "_iobuf_out_size: %u\n", _iobuf_out_size); } // ESP.resetHeap(); if (!_sc_svr || !_iobuf_in || !_iobuf_out) { diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 710c5a4330..0916e8e855 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -1,6 +1,7 @@ #include #include #include +#include uint32_t timed_byte_read(char *pc, uint32_t * o); uint32_t timed_byte_read2(char *pc, uint32_t * o); @@ -15,12 +16,6 @@ short *unaligned_probe_s = NULL; uint32_t read_var = 0x11223344; -#define GET_BYTE_FN(name,wo,bo) \ -static inline char get ## name(void *o) { \ - char res; /* extract named field */ \ - asm ("l32i %0, %1, " #wo "; extui %0, %0, " #bo ", 8;" : "=r"(res) : "r"(o) : );\ - return res; } - /* Notes, When accessing IRAM as data storage all access must be word aligned and @@ -90,12 +85,6 @@ void print_mmu_status(Print& oStream) { oStream.println(); oStream.printf_P(PSTR("MMU Configuration")); oStream.println(); - oStream.printf_P(PSTR(" mmu_status = {" - "v_cfg = %u, state = %d, enable/disable count = %u/%u, " - "map = 0x%02X, p = 0x%02X, v = 0x%02X}"), - mmu_status.v_cfg, mmu_status.state, - mmu_status.enable_count, mmu_status.disable_count, - mmu_status.map, mmu_status.p, mmu_status.v); oStream.println(); uint32_t iram_bank_reg = ESP8266_DREG(0x24); if (0 == (iram_bank_reg & 0x10)) { // if bit clear, is enabled @@ -133,8 +122,8 @@ void setup() { WiFi.mode(WIFI_OFF); // Serial.begin(74880); Serial.begin(115200); - delay(20); - Serial.printf_P(PSTR("\n\nSetup ...\n")); + delay(10); + Serial.printf_P(PSTR("\r\n\r\nSetup ...\r\n")); print_mmu_status(Serial); @@ -145,9 +134,9 @@ void setup() { gobble_sz = ESP.getFreeHeap() - UMM_OVERHEAD_ADJUST; // - 4096; gobble = (uint32_t *)malloc(gobble_sz); } - Serial.printf_P(PSTR("\nmalloc() from IRAM Heap:\n")); - Serial.printf_P(PSTR(" gobble_sz: %u\n"), gobble_sz); - Serial.printf_P(PSTR(" gobble: %p\n"), gobble); + Serial.printf_P(PSTR("\r\nmalloc() from IRAM Heap:\r\n")); + Serial.printf_P(PSTR(" gobble_sz: %u\r\n"), gobble_sz); + Serial.printf_P(PSTR(" gobble: %p\r\n"), gobble); #elif defined(MMU_SEC_HEAP) gobble = (uint32_t *)MMU_SEC_HEAP; @@ -169,7 +158,7 @@ void setup() { #endif // Lets peak over the edge - Serial.printf_P(PSTR("\nPeek over the edge of memory at 0x4010C000\n")); + Serial.printf_P(PSTR("\r\nPeek over the edge of memory at 0x4010C000\r\n")); dump_mem32((void *)(0x4010C000 - 16 * 4), 32); probe_b = (char *)gobble; @@ -231,6 +220,8 @@ void processKey(Print& out, int hotKey) { out.printf_P(PSTR("Read Byte, 0x%02X at %p"), probe_c[0], probe_c); xt_rsil(0); out.println(); + out.printf_P(PSTR("With Non32-bit access enabled, access range check is only done when 'Tools->Debug Level: CORE ...' is set.")); + out.println(); break; case 'b': out.printf_P(PSTR("Load/Store exception by reading byte from iRAM")); @@ -338,17 +329,3 @@ void loop() { int __attribute__((noinline)) divideA_B(int a, int b) { return (a / b); } - -#if 0 -#ifdef MMU_SEC_HEAP -extern "C" void _text_end(void); - -extern "C" void umm_init_iram(void) { - uint32_t sec_heap = (uint32_t)_text_end + 32; - sec_heap &= ~7; - size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); - - umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); -} -#endif -#endif diff --git a/libraries/esp8266/examples/MMU48K/timed.cpp b/libraries/esp8266/examples/MMU48K/timed.cpp index aa603dc273..80bd0c30df 100644 --- a/libraries/esp8266/examples/MMU48K/timed.cpp +++ b/libraries/esp8266/examples/MMU48K/timed.cpp @@ -10,7 +10,7 @@ uint32_t IRAM_ATTR timed_byte_read(char *pc, uint32_t * o) { uint32_t IRAM_ATTR timed_byte_read2(char *pc, uint32_t * o) { uint32_t start = esp_get_cycle_count(); - *o = get_uint8_iram(pc); + *o = mmu_get_uint8(pc); // return clockCyclesToMicroseconds(esp_get_cycle_count() - start); return (esp_get_cycle_count() - start); } diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index d29ae2dd53..876d3d826c 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -5,6 +5,7 @@ #include #include +#include // #define USE_SET_IRAM_HEAP @@ -80,7 +81,7 @@ uint32_t cyclesToRead1Kx16_viaInline(unsigned short *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; for (int i = 0; i < 1024; i++) { - sum += get_uint16_iram(x++); //*(x++); + sum += mmu_get_uint16(x++); //*(x++); } *res = sum; return ESP.getCycleCount() - b; @@ -92,7 +93,7 @@ uint32_t cyclesToWrite1Kx16_viaInline(unsigned short *x) { for (int i = 0; i < 1024; i++) { sum += i; // *(x++) = sum; - set_uint16_iram(x++, sum); + mmu_set_uint16(x++, sum); } return ESP.getCycleCount() - b; } @@ -101,7 +102,7 @@ uint32_t cyclesToRead1Kx8_viaInline(unsigned char*x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; for (int i = 0; i < 1024; i++) { - sum += get_uint8_iram(x++); //*(x++); + sum += mmu_get_uint8(x++); //*(x++); } *res = sum; return ESP.getCycleCount() - b; @@ -113,7 +114,7 @@ uint32_t cyclesToWrite1Kx8_viaInline(unsigned char*x) { for (int i = 0; i < 1024; i++) { sum += i; // *(x++) = sum; - set_uint8_iram(x++, sum); + mmu_set_uint8(x++, sum); } return ESP.getCycleCount() - b; } @@ -125,11 +126,15 @@ void setup() { Serial.begin(115200); delay(20); Serial.printf_P(PSTR("\n\nSetup ...\n")); +#ifndef UMM_HEAP_IRAM + Serial.printf("\r\n" + "This example needs IRAM Heap support enabled.\r\n" + " eg. Arduino IDE 'Tools->MMU:\"16KB cache + 48KB IRAM and 2nd Heap (shared)\"'\r\n" + "This build has IRAM Heap support disabled.\r\n" + "In this situation, all IRAM requests are satisfied with DRAM.\r\n\r\n"); +#endif - // IRAM Heap Inialized moed to user_init() in core_esp8266_main.cpp - // umm_init_iram(); - - // Compiling with Secondary Heap option VM does not change malloc to use the + // Compiling with Secondary Heap option does not change malloc to use the // IRAM region. It will continue to use the builtin DRAM until we request // otherwise. Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); @@ -148,15 +153,16 @@ void setup() { uint32_t *imem; { HeapSelectIram ephemeral; + // This class effectively does this // size_t _heap_id = umm_get_current_heap_id(); // umm_set_heap_by_id(UMM_HEAP_IRAM); + // ... + // umm_set_heap_by_id(_heap_id); Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); imem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); - // umm_set_heap_by_id(_heap_id); } #endif - uint32_t res; uint32_t t; t = cyclesToWrite1Kx32(imem); From a3c9e020f7d7e1b16fcbcaf9faba44ece55f662b Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 22 Jul 2020 17:38:24 -0700 Subject: [PATCH 28/48] Corrected comment. And added missing include. --- cores/esp8266/StackThunk.cpp | 9 ++++----- .../examples/HelloServerBearSSL/HelloServerBearSSL.ino | 1 + 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/cores/esp8266/StackThunk.cpp b/cores/esp8266/StackThunk.cpp index be50211c4b..3bab041b55 100644 --- a/cores/esp8266/StackThunk.cpp +++ b/cores/esp8266/StackThunk.cpp @@ -51,11 +51,10 @@ void stack_thunk_add_ref() stack_thunk_refcnt++; if (stack_thunk_refcnt == 1) { DBG_MMU_PRINTF("\nStackThunk malloc(%u)\n", _stackSize * sizeof(uint32_t)); - // The stack must be in DRAM, or an HWDT will follow. I am not sure why - // maybe an exception handler hits a non32-bit access exception. Or too much - // time is consumed in a non32-bit exception handler with IRQs off. Also, - // interrupt handling on an IRAM stack would greatly slow an ISR handler - // with interrupts turned off. + // The stack must be in DRAM, or an Soft WDT will follow. Maybe too much + // time is consumed with the non32-bit exception handler. Also, + // interrupt handling on an IRAM stack would als be greatly slower. + // Strings on the stack would be very slow to access as well. HeapSelectDram ephemeral; stack_thunk_ptr = (uint32_t *)malloc(_stackSize * sizeof(uint32_t)); DBG_MMU_PRINTF("StackThunk stack_thunk_ptr: %p\n", stack_thunk_ptr); diff --git a/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino b/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino index e02e589fc0..ab36e54805 100644 --- a/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino +++ b/libraries/ESP8266WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino @@ -14,6 +14,7 @@ #include #include #include +#include #ifndef STASSID #define STASSID "your-ssid" From fc5f6111dcea869ac3310294e19b6104f59713e5 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 22 Jul 2020 17:48:05 -0700 Subject: [PATCH 29/48] Improve comment. --- cores/esp8266/StackThunk.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cores/esp8266/StackThunk.cpp b/cores/esp8266/StackThunk.cpp index 3bab041b55..7456fcaeeb 100644 --- a/cores/esp8266/StackThunk.cpp +++ b/cores/esp8266/StackThunk.cpp @@ -51,9 +51,9 @@ void stack_thunk_add_ref() stack_thunk_refcnt++; if (stack_thunk_refcnt == 1) { DBG_MMU_PRINTF("\nStackThunk malloc(%u)\n", _stackSize * sizeof(uint32_t)); - // The stack must be in DRAM, or an Soft WDT will follow. Maybe too much - // time is consumed with the non32-bit exception handler. Also, - // interrupt handling on an IRAM stack would als be greatly slower. + // The stack must be in DRAM, or an Soft WDT will follow. Not sure why, + // maybe too much time is consumed with the non32-bit exception handler. + // Also, interrupt handling on an IRAM stack would be very slow. // Strings on the stack would be very slow to access as well. HeapSelectDram ephemeral; stack_thunk_ptr = (uint32_t *)malloc(_stackSize * sizeof(uint32_t)); From bbdf166f53c4f9bfa013820752cef8709ca51556 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 22 Jul 2020 18:11:21 -0700 Subject: [PATCH 30/48] style and comment correction --- libraries/esp8266/examples/irammem/irammem.ino | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 876d3d826c..1aed45c704 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -128,10 +128,10 @@ void setup() { Serial.printf_P(PSTR("\n\nSetup ...\n")); #ifndef UMM_HEAP_IRAM Serial.printf("\r\n" - "This example needs IRAM Heap support enabled.\r\n" - " eg. Arduino IDE 'Tools->MMU:\"16KB cache + 48KB IRAM and 2nd Heap (shared)\"'\r\n" - "This build has IRAM Heap support disabled.\r\n" - "In this situation, all IRAM requests are satisfied with DRAM.\r\n\r\n"); + "This example needs IRAM Heap support enabled.\r\n" + " eg. Arduino IDE 'Tools->MMU:\"16KB cache + 48KB IRAM and 2nd Heap (shared)\"'\r\n" + "This build has IRAM Heap support disabled.\r\n" + "In this situation, all IRAM requests are satisfied with DRAM.\r\n\r\n"); #endif // Compiling with Secondary Heap option does not change malloc to use the From b88d1975a6ea89a93157b09fcbf383f84ef8029d Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 23 Jul 2020 16:44:52 -0700 Subject: [PATCH 31/48] Added draft mmu.rst file and updated index. Updated example HeapMetric.ino to also illustrate use of IRAM Improved comments in exc-c-wrapper-handler.S. Added insurance IRQ disable. --- cores/esp8266/exc-c-wrapper-handler.S | 22 +- doc/index.rst | 3 +- doc/mmu.rst | 216 ++++++++++++++++++ .../examples/HeapMetric/HeapMetric.ino | 17 ++ 4 files changed, 248 insertions(+), 10 deletions(-) create mode 100644 doc/mmu.rst diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S index 646af756cf..1e63211ece 100644 --- a/cores/esp8266/exc-c-wrapper-handler.S +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -66,11 +66,12 @@ _xtos_c_wrapper_handler: // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__) // movi a2, 0x23 // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) -// @mhightower83 - testing to see if we need INTLEVEL 15 instead of 3 - movi a2, 0x2F // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +// @mhightower83 - use INTLEVEL 15 instead of 3 for Arduino like interrupt support?? + movi a2, 0x2F // 0x21, PS_UM|PS_INTLEVEL(15) rsr a3, EPC_1 // @mhightower83 - I assume PS.EXCM was set and now is being cleared, thus // allowing new exceptions and interrupts within PS_INTLEVEL to be possible. +// We have set INTLEVEL to 15 to block any possible interrupts. xsr a2, PS // HERE: window overflows enabled, but NOT SAFE because we're not quite @@ -115,14 +116,17 @@ _xtos_c_wrapper_handler: // Restore special registers l32i a14, a1, UEXC_sar - /* - * Disable interrupts while returning from the pseudo-CALL setup above, - * for the same reason they were disabled while doing the pseudo-CALL: - * this sequence restores SP such that it doesn't reflect the allocation - * of the exception stack frame, which we still need to return from - * the exception. - */ +// For compatibility with Arduino interrupt architecture, we keep interrupts 100% +// disabled. +// /* +// * Disable interrupts while returning from the pseudo-CALL setup above, +// * for the same reason they were disabled while doing the pseudo-CALL: +// * this sequence restores SP such that it doesn't reflect the allocation +// * of the exception stack frame, which we still need to return from +// * the exception. +// */ // rsil a12, 1 // XCHAL_EXCM_LEVEL + rsil a12, 15 // All levels blocked. wsr a14, SAR movi a0, _xtos_return_from_exc jx a0 diff --git a/doc/index.rst b/doc/index.rst index 9fdba0f1de..dcc5f69628 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -13,10 +13,11 @@ Welcome to ESP8266 Arduino Core's documentation! OTA Updates PROGMEM Using GDB to debug + MMU Boards FAQ - + Exception causes Debugging Stack Dump diff --git a/doc/mmu.rst b/doc/mmu.rst new file mode 100644 index 0000000000..a7c48e54bf --- /dev/null +++ b/doc/mmu.rst @@ -0,0 +1,216 @@ +MMU - Adjust the Ratio of ICACHE to IRAM +======================================== + +Overview +-------- + +The ESP8266 has a total of 64K of instruction memory, IRAM. This 64K of +IRAM is composed of one dedicated 32K block of IRAM and two 16K blocks +of IRAM. The last two 16K blocks of IRAM are flexible in the sense that +it can be used as a transparent cache for external flash memory. These +blocks can either be used for IRAM or an instruction cache for executing +code out of flash, ICACHE. + +The instructions generated for a sketch are divided up into two groups +ICACHE and IRAM. IRAM offers faster access/execution. It is commonly +used for interrupt service routines, exception handling, and +time-critical code. ICACHE allows for the execution of up to 1MB of code +in flash. On a cache miss, a delay occurs as the instructions are read +from flash via the SPI bus. + +There is 96KB of DRAM space. This memory can be accessed as byte, short, +or a 32-bit word. Access must be aligned according to the data element +size. A 16bit short must be on a multiple of 2-byte address boundary, +likewise, a 32-bit word must be on a multiple of 4-byte address +boundary. In contrast, data access to IRAM or ICACHE must always be a +full 32-bit word and aligned. We will introduce a non32-bit exception +handler for this later. + +Option Summary +-------------- + +**The Arduino IDE Tools menu option, ``MMU`` allows for the following +selections:** + +1. ``32KB cache + 32KB IRAM (balanced)`` + + - This is the legacy ratio. + - Try this option 1st. + +2. ``16KB cache + 48KB IRAM (IRAM)`` + + - With just 16KB cache, execution of code out of flash may be slowed + by more cache misses when compared to 32KB. The slowness will vary + with the sketch. + - Use this if you need a little more IRAM space and you are good on + DRAM space. + +3. ``16KB cache + 48KB IRAM and 2nd Heap (shared)`` + + - This option builds on the previous option and builds a 2nd Heap + made with IRAM. + - The 2nd Heap size will vary with free IRAM. + - This option is flexible. IRAM usage for code can overflow into the + additional 16KB IRAM region shrinking the 2nd Heap below 16KB. Or + IRAM can be under 32KB allowing the 2nd Heap to be larger than + 16KB. + - Installs a Non-32-Bit Access handler for IRAM. This allows for + byte and 16-bit aligned short access. + - This 2nd Heap is supported by the standard ``malloc`` APIs. + - Heap selection is handled through a ``HeapSelect`` class. This + allows a specific heap selection for the duration of a scope. + - Use this option, if you are still running out of DRAM space after + you have moved as many of your constant strings/data elements that + you can to PROGMEM. + +4. ``16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared)`` + + - Not managed by the ``umm_malloc`` heap library + - Non-32-Bit Access for IRAM must be enabled separately + - A 16KB block of unmanaged memory. + - Data persist across reboots, but not deep sleep. + - This may be best for when you just need a large chunk of memory. + This option will free up the additional resources needed by + ``umm_malloc`` to support managing the 2nd Heap. + +MMU related build defines and possible values.These values change as +indicated with the menu options above: + ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ +| ``#define`` | balanced | IRAM | shared (IRAM and Heap) | not shared (IRAM and Heap) | ++=========================+==============+==============+====================================+==============================+ +| ``MMU_IRAM_SIZE`` | ``0x8000`` | ``0xC000`` | ``0xC000`` | ``0x8000`` | ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ +| ``MMU_ICACHE_SIZE`` | ``0x8000`` | ``0x4000`` | ``0x4000`` | ``0x4000`` | ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ +| ``MMU_IRAM_HEAP`` | -- | -- | defined, enables\ ``umm_malloc`` | -- | ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ +| ``MMU_SEC_HEAP`` | -- | \*\* | \*\* | ``0x40108000`` | ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ +| ``MMU_SEC_HEAP_SIZE`` | -- | \*\* | \*\* | ``0x4000`` | ++-------------------------+--------------+--------------+------------------------------------+------------------------------+ + +\*\* This define is to an inline function that calculates the value, +based on unused code space. + +**The Arduino IDE Tools menu option, ``Non-32-Bit Access`` allows for +the following selections:** + +- ``Use pgm_read macros for IRAM/PROGMEM`` +- ``Byte/Word access to IRAM/PROGMEM (very slow)`` + + - This option adds a non32-bit exception handler to your build. + - Handles read/writes to IRAM and reads to ICACHE. + - Supports short and byte access to IRAM. + - Not recommended for high-frequency access data, use DRAM if you + can. + - Expect it to be slower than DRAM, each character access will + require a complete save and restore of all 16+ registers. + - Processing an exception uses 256 bytes of stack space just to get + started. The actual handler will add a little more. + - This option is implicitly enabled and required when you select MMU + option ``16KB cache + 48KB IRAM and 2nd Heap (shared)``. + +IRAM, unlike DRAM, must be accessed as aligned full 32-bit words, no +byte or short access. The pgm\_read macros are an option; however, the +store operation remains an issue. For a block copy ets\_memcpy - appears +to work well as long as the byte count is rounded up to be evenly +divided by 4 and source and destination addresses are 4 bytes aligned. + +A word of caution, I have seen one case with the new toolchain 10.1 +where code that reads a 32-bit word to extract a byte was optimized away +to be a byte read. Using ``volatile`` on the pointer stopped the +over-optimization. + +To get a sense of how memory access time is effected, see examples +``MMU48K`` and ``irammem`` in ``ESP8266``. + +Miscellaneous +------------- + +For calls to ``umm_malloc`` with interrupts disabled. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- ``malloc`` will always allocate from the ``DRAM`` heap when called + with interrupts disabled. +- ``realloc`` with a NULL pointer will use ``malloc`` and return a + ``DRAM`` heap allocation. Note, calling ``realloc`` with interrupts + disabled is **not** officially supported. You are on your own if you + do this. +- If you must use IRAM memory in your ISR, allocate the memory ahead of + time. And avoid non32-bit access that would trigger the exception + handler. + + I think this block should go away and we always use + ``USE_ISR_SAFE_EXC_WRAPPER`` with the exception handler. + + - ``realloc`` will fail if not built with + ``USE_ISR_SAFE_EXC_WRAPPER`` defined. + - The current build has ``USE_ISR_SAFE_EXC_WRAPPER`` defined in + ``mmu_iram.h``. + + .. rubric:: ISR/Exception Handler Issue + :name: isrexception-handler-issue + + The non-32-bit exception handler is called by a "C" wrapper function + in ROM. This ROM function enables interrupts before calling our + registered handler. Defining ``USE_ISR_SAFE_EXC_WRAPPER`` in + ``mmu_iram.h`` will install a replacement that does not enable + interrupts (now default). The effects on Network performance are + unknown. + + To keep ISR execution time with interrupts disabled at a minimum, + avoid the use of IRAM from ISRs. Especially the use of non-32-bit + read/writes on IRAM. + +How to Select Heap +~~~~~~~~~~~~~~~~~~ + +The ``MMU`` selection ``16KB cache + 48KB IRAM and 2nd Heap (shared)`` +allows you to use the standard heap API function calls (``malloc``, +``calloc``, ``free``, ... ). to allocate memory from DRAM or IRAM. The +selection can be made by instantiating the class ``HeapSelectIram`` or +``HeapSelectDram``.The usage is similar to that of the ``InterruptLock`` +class. The default/initial heap source is DRAM. The class is in +``umm_malloc/umm_heap_select.h`` + +:: + + ... + char *bufferDram; + bufferDram = (char *)malloc(33); + char *bufferIram; + { + HeapSelectIram ephemeral; + bufferIram = (char *)malloc(33); + } + ... + free(bufferIram); + free(bufferDram); + ... + +``free`` will always return memory to the correct heap. There is no need +for tracking and selecting before freeing. + +``realloc`` with a non-NULL pointer will always resize the allocation +from the original heap it was allocated from. When the supplied pointer +is NULL, then the current heap selection is used. + +Low level primatives for selecting a heap. These are used by the above +Classes: + +- ``umm_get_current_heap_id()`` +- ``umm_set_heap_by_id( ID value )`` +- Possible ID values +- ``UMM_HEAP_DRAM`` +- ``UMM_HEAP_IRAM`` + +Also, an alternate stack select based API is available. This is not as +easy as the class method; however, for some small set of cases it may +provide some additional control: + +- ``ESP.setIramHeap()`` Pushes current heap ID onto a stack and sets + Heap API for an IRAM selection. +- ``ESP.setDramHeap()`` Pushes current heap ID onto a stack and sets + Heap API for a DRAM selection. +- ``ESP.resetHeap()`` Restores previously pushed heap. diff --git a/libraries/esp8266/examples/HeapMetric/HeapMetric.ino b/libraries/esp8266/examples/HeapMetric/HeapMetric.ino index e56fc0d24e..3119042cac 100644 --- a/libraries/esp8266/examples/HeapMetric/HeapMetric.ino +++ b/libraries/esp8266/examples/HeapMetric/HeapMetric.ino @@ -4,6 +4,7 @@ #include #include +#include void stats(const char* what) { // we could use getFreeHeap() getMaxFreeBlockSize() and getHeapFragmentation() @@ -109,6 +110,7 @@ void setup() { Serial.begin(115200); WiFi.mode(WIFI_OFF); + Serial.printf("\r\nDemo Heap Metrics for DRAM\r\n"); tryit(8000); tryit(4000); tryit(2000); @@ -118,6 +120,21 @@ void setup() { tryit(100); tryit(50); tryit(15); +#ifdef UMM_HEAP_IRAM + { + HeapSelectIram ephemeral; + Serial.printf("\r\nDemo Heap Metrics for IRAM\r\n"); + tryit(8000); + tryit(4000); + tryit(2000); + tryit(1000); + tryit(500); + tryit(200); + tryit(100); + tryit(50); + tryit(15); + } +#endif } void loop() { From b058f17b9a30ec649984c069e5cf2490b342822b Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 25 Jul 2020 07:27:03 -0700 Subject: [PATCH 32/48] Updated mmu.rst Improved function name uniqueness for is_iram, is_dram, and is_icache by adding prefix mmu_. Also, made them available outside of a debug build. Made pointer precision width more specific. Made some of the static inline functions in mmu_irm.h safe for ISRs by setting then for always inline. --- cores/esp8266/core_esp8266_non32xfer.cpp | 6 ++- cores/esp8266/mmu_iram.h | 50 +++++++++------------ doc/mmu.rst | 57 ++++++++++++++++++++---- 3 files changed, 73 insertions(+), 40 deletions(-) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index d6713ff2c3..ce2fc02ccc 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -165,12 +165,14 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, /* read out the faulting address */ __asm("rsr %0, EXCVADDR;" :"=r"(excvaddr)::); - /* debug option, validate address so we don't hide memory access bugs in APP */ - if (is_iram((void *)excvaddr) || (is_read && is_icache((void *)excvaddr))) { +#ifdef DEBUG_ESP_MMU + /* debug option to validate address so we don't hide memory access bugs in APP */ + if (mmu_is_iram((void *)excvaddr) || (is_read && mmu_is_icache((void *)excvaddr))) { /* all is good */ } else { continue; /* fail */ } +#endif if (is_read) { /* Load, shift and mask down to correct size */ diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index ad745e883f..8e5f037efb 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -112,9 +112,8 @@ typedef struct MMU_CRE_STATUS { extern mmu_cre_status_t mmu_status; #endif -#ifdef DEBUG_ESP_MMU - -static inline bool is_iram(const void *addr) { +static inline __attribute__((always_inline)) +bool mmu_is_iram(const void *addr) { #define IRAM_START 0x40100000UL #ifndef MMU_IRAM_SIZE #error "MMU_IRAM_SIZE was undefined!" @@ -124,47 +123,32 @@ static inline bool is_iram(const void *addr) { return (IRAM_START <= (uint32_t)addr && IRAM_END > (uint32_t)addr); } -static inline bool is_dram(const void *addr) { +static inline __attribute__((always_inline)) +bool mmu_is_dram(const void *addr) { #define DRAM_START 0x3FF80000UL #define DRAM_END 0x40000000UL return (DRAM_START <= (uint32_t)addr && DRAM_END > (uint32_t)addr); } -static inline bool is_icache(const void *addr) { +static inline __attribute__((always_inline)) +bool mmu_is_icache(const void *addr) { #define ICACHE_START 0x40200000UL #define ICACHE_END (ICACHE_START + 0x100000UL) return (ICACHE_START <= (uint32_t)addr && ICACHE_END > (uint32_t)addr); } -#else -static inline bool is_iram(const void *addr) { - (void)addr; - return true; -} - -static inline bool is_dram(const void *addr) { - (void)addr; - return true; -} - -static inline bool is_icache(const void *addr) { - (void)addr; - return true; -} -#endif // #ifdef DEBUG_ESP_MMU - #ifdef DEBUG_ESP_MMU #define ASSERT_RANGE_TEST_WRITE(a) \ - if (is_iram(a) || is_dram(a)) { \ + if (mmu_is_iram(a) || mmu_is_dram(a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ assert(("Outside of Range - Write" && false)); \ } #define ASSERT_RANGE_TEST_READ(a) \ - if (is_iram(a) || is_dram(a) || is_icache(a)) { \ + if (mmu_is_iram(a) || mmu_is_dram(a) || mmu_is_icache(a)) { \ } else { \ DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \ assert(("Outside of Range - Read" && false)); \ @@ -180,7 +164,8 @@ static inline bool is_icache(const void *addr) { * iCACHE data elements. These remove the extra time and stack space that would * have occured by relying on exception processing. */ -static inline uint8_t mmu_get_uint8(const void *p8) { +static inline __attribute__((always_inline)) +uint8_t mmu_get_uint8(const void *p8) { ASSERT_RANGE_TEST_READ(p8); uint32_t val = (*(uint32_t *)((uintptr_t)p8 & ~0x3)); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; @@ -188,7 +173,8 @@ static inline uint8_t mmu_get_uint8(const void *p8) { return (uint8_t)val; } -static inline uint16_t mmu_get_uint16(const unsigned short *p16) { +static inline __attribute__((always_inline)) +uint16_t mmu_get_uint16(const uint16_t *p16) { ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; @@ -196,7 +182,8 @@ static inline uint16_t mmu_get_uint16(const unsigned short *p16) { return (uint16_t)val; } -static inline int16_t mmu_get_int16(const short *p16) { +static inline __attribute__((always_inline)) +int16_t mmu_get_int16(const int16_t *p16) { ASSERT_RANGE_TEST_READ(p16); uint32_t val = (*(uint32_t *)((uintptr_t)p16 & ~0x3)); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; @@ -204,7 +191,8 @@ static inline int16_t mmu_get_int16(const short *p16) { return (int16_t)val; } -static inline uint8_t mmu_set_uint8(void *p8, const uint8_t val) { +static inline __attribute__((always_inline)) +uint8_t mmu_set_uint8(void *p8, const uint8_t val) { ASSERT_RANGE_TEST_WRITE(p8); uint32_t pos = ((uintptr_t)p8 & 0x3) * 8; uint32_t sval = val << pos; @@ -218,7 +206,8 @@ static inline uint8_t mmu_set_uint8(void *p8, const uint8_t val) { return val; } -static inline uint16_t mmu_set_uint16(unsigned short *p16, const uint16_t val) { +static inline __attribute__((always_inline)) +uint16_t mmu_set_uint16(uint16_t *p16, const uint16_t val) { ASSERT_RANGE_TEST_WRITE(p16); uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; uint32_t sval = val << pos; @@ -232,7 +221,8 @@ static inline uint16_t mmu_set_uint16(unsigned short *p16, const uint16_t val) { return val; } -static inline int16_t mmu_set_int16(short *p16, const int16_t val) { +static inline __attribute__((always_inline)) +int16_t mmu_set_int16(int16_t *p16, const int16_t val) { ASSERT_RANGE_TEST_WRITE(p16); uint32_t sval = (uint16_t)val; uint32_t pos = ((uintptr_t)p16 & 0x3) * 8; diff --git a/doc/mmu.rst b/doc/mmu.rst index a7c48e54bf..6a5ebdfc07 100644 --- a/doc/mmu.rst +++ b/doc/mmu.rst @@ -29,8 +29,8 @@ handler for this later. Option Summary -------------- -**The Arduino IDE Tools menu option, ``MMU`` allows for the following -selections:** +The Arduino IDE Tools menu option, ``MMU`` has the following selections: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1. ``32KB cache + 32KB IRAM (balanced)`` @@ -91,10 +91,10 @@ indicated with the menu options above: +-------------------------+--------------+--------------+------------------------------------+------------------------------+ \*\* This define is to an inline function that calculates the value, -based on unused code space. +based on unused code space, requires ``#include ``. -**The Arduino IDE Tools menu option, ``Non-32-Bit Access`` allows for -the following selections:** +The Arduino IDE Tools menu option, ``Non-32-Bit Access`` has the following selections: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - ``Use pgm_read macros for IRAM/PROGMEM`` - ``Byte/Word access to IRAM/PROGMEM (very slow)`` @@ -138,8 +138,8 @@ For calls to ``umm_malloc`` with interrupts disabled. disabled is **not** officially supported. You are on your own if you do this. - If you must use IRAM memory in your ISR, allocate the memory ahead of - time. And avoid non32-bit access that would trigger the exception - handler. + time. To reduce the time spent in the ISR, avoid non32-bit access + that would trigger the exception handler. I think this block should go away and we always use ``USE_ISR_SAFE_EXC_WRAPPER`` with the exception handler. @@ -213,4 +213,45 @@ provide some additional control: Heap API for an IRAM selection. - ``ESP.setDramHeap()`` Pushes current heap ID onto a stack and sets Heap API for a DRAM selection. -- ``ESP.resetHeap()`` Restores previously pushed heap. +- ``ESP.resetHeap()`` Restores previously pushed heap. ### Identify + Memory + +These always inlined functions can be used to determine the resource of +a pointer: + +.. code:: cpp + + bool mmu_is_iram(const void *addr); + bool mmu_is_dram(const void *addr); + bool mmu_is_icache(const void *addr); + +Performance Functions +~~~~~~~~~~~~~~~~~~~~~ + +While these, always inlined functions, will bypass the need for the +exception handler reducing execution time and stack use, it comes at the +cost of increased code size. + +These are an alternative to the ``pgm_read`` macros for reading from +IRAM. When compiled with 'Debug Level: core' range checks are performed +on the pointer value to make sure you are reading from the address range +of IRAM, DRAM, or ICACHE. + +.. code:: cpp + + uint8_t mmu_get_uint8(const void *p8); + uint16_t mmu_get_uint16(const uint16_t *p16); + int16_t mmu_get_int16(const int16_t *p16); + +While these functions are intended for writing to IRAM, they will work +with DRAM. When compiled with 'Debug Level: core', range checks are +performed on the pointer value to make sure you are writing to the +address range of IRAM or DRAM. + +.. code:: cpp + + uint8_t mmu_set_uint8(void *p8, const uint8_t val); + uint16_t mmu_set_uint16(uint16_t *p16, const uint16_t val); + int16_t mmu_set_int16(int16_t *p16, const int16_t val); + +:: From 5e31ed59837e72539ce8c837cafaa66f5726405a Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 25 Jul 2020 15:37:15 -0700 Subject: [PATCH 33/48] Add a default MMU_IRAM_SIZE value for a new CI test to pass. Extended use 'umm_heap_context_t *_context' argument in ..._core functions and expanded its usage to reduce unnecessary repeated calls to umm_info(NULL, false), also removed recursion from umm_info(NULL, true). Fixed stack buffer length in umm_info_safe_printf_P and heap.cpp. Added example for creating an IRAM reserve section. Updated mmu.rst. Grammar and spelling corrections. --- cores/esp8266/Esp-frag.cpp | 6 +- cores/esp8266/core_esp8266_non32xfer.h | 1 - cores/esp8266/heap.cpp | 2 +- cores/esp8266/mmu_iram.h | 7 +- cores/esp8266/umm_malloc/umm_info.c | 34 +++-- cores/esp8266/umm_malloc/umm_local.c | 2 +- cores/esp8266/umm_malloc/umm_malloc.cpp | 4 +- cores/esp8266/umm_malloc/umm_malloc.h | 2 +- cores/esp8266/umm_malloc/umm_malloc_cfg.h | 12 +- doc/mmu.rst | 78 ++++++------ .../examples/IramReserve/IramReserve.ino | 117 ++++++++++++++++++ .../examples/IramReserve/ProcessKey.ino | 116 +++++++++++++++++ 12 files changed, 307 insertions(+), 74 deletions(-) create mode 100644 libraries/esp8266/examples/IramReserve/IramReserve.ino create mode 100644 libraries/esp8266/examples/IramReserve/ProcessKey.ino diff --git a/cores/esp8266/Esp-frag.cpp b/cores/esp8266/Esp-frag.cpp index f4bf5ec9ca..30332aca62 100644 --- a/cores/esp8266/Esp-frag.cpp +++ b/cores/esp8266/Esp-frag.cpp @@ -31,14 +31,14 @@ void EspClass::getHeapStats(uint32_t* hfree, uint16_t* hmax, uint8_t* hfrag) umm_info(NULL, false); - uint32_t free_size = umm_free_heap_size_core(); + uint32_t free_size = umm_free_heap_size_core(umm_get_current_heap()); if (hfree) *hfree = free_size; if (hmax) - *hmax = (uint16_t)umm_max_block_size_core(); + *hmax = (uint16_t)umm_max_block_size_core(umm_get_current_heap()); if (hfrag) { if (free_size) { - *hfrag = umm_fragmentation_metric_core(); + *hfrag = umm_fragmentation_metric_core(umm_get_current_heap()); } else { *hfrag = 0; } diff --git a/cores/esp8266/core_esp8266_non32xfer.h b/cores/esp8266/core_esp8266_non32xfer.h index 407fab8d10..93151239c4 100644 --- a/cores/esp8266/core_esp8266_non32xfer.h +++ b/cores/esp8266/core_esp8266_non32xfer.h @@ -6,7 +6,6 @@ extern "C" { #endif extern void install_non32xfer_exception_handler(); -extern uint32_t mmu_non32xfer_count; #ifdef __cplusplus } diff --git a/cores/esp8266/heap.cpp b/cores/esp8266/heap.cpp index 2001579ef0..3f549716f4 100644 --- a/cores/esp8266/heap.cpp +++ b/cores/esp8266/heap.cpp @@ -164,7 +164,7 @@ void ICACHE_RAM_ATTR print_loc(size_t size, const char* file, int line) if (inISR && (uint32_t)file >= 0x40200000) { DEBUG_HEAP_PRINTF("File: %p", file); } else if (!inISR && (uint32_t)file >= 0x40200000) { - char buf[ets_strlen(file)] __attribute__ ((aligned(4))); + char buf[ets_strlen(file) + 1] __attribute__((aligned(4))); ets_strcpy(buf, file); DEBUG_HEAP_PRINTF(buf); } else { diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 8e5f037efb..6201e2216a 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -115,9 +115,10 @@ extern mmu_cre_status_t mmu_status; static inline __attribute__((always_inline)) bool mmu_is_iram(const void *addr) { #define IRAM_START 0x40100000UL - #ifndef MMU_IRAM_SIZE - #error "MMU_IRAM_SIZE was undefined!" - #endif +#ifndef MMU_IRAM_SIZE + #pragma warning("MMU_IRAM_SIZE was undefined, setting to 0x8000UL!") + #define MMU_IRAM_SIZE 0x8000UL +#endif #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) return (IRAM_START <= (uint32_t)addr && IRAM_END > (uint32_t)addr); diff --git a/cores/esp8266/umm_malloc/umm_info.c b/cores/esp8266/umm_malloc/umm_info.c index df879a1953..0860fe79ea 100644 --- a/cores/esp8266/umm_malloc/umm_info.c +++ b/cores/esp8266/umm_malloc/umm_info.c @@ -142,8 +142,8 @@ void *umm_info( void *ptr, bool force ) { DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); - DBGLOG_FORCE( force, "Usage Metric: %5d\n", umm_usage_metric()); - DBGLOG_FORCE( force, "Fragmentation Metric: %5d\n", umm_fragmentation_metric()); + DBGLOG_FORCE( force, "Usage Metric: %5d\n", umm_usage_metric_core(_context)); + DBGLOG_FORCE( force, "Fragmentation Metric: %5d\n", umm_fragmentation_metric_core(_context)); DBGLOG_FORCE( force, "+--------------------------------------------------------------+\n" ); @@ -170,8 +170,7 @@ void *umm_info( void *ptr, bool force ) { /* ------------------------------------------------------------------------ */ -size_t umm_free_heap_size_core( void ) { - umm_heap_context_t *_context = umm_get_current_heap(); +size_t umm_free_heap_size_core( umm_heap_context_t *_context ) { return (size_t)_context->info.freeBlocks * sizeof(umm_block); } @@ -180,21 +179,20 @@ size_t umm_free_heap_size( void ) { umm_info(NULL, false); #endif - return umm_free_heap_size_core(); + return umm_free_heap_size_core(umm_get_current_heap()); } //C Breaking change in upstream umm_max_block_size() was changed to //C umm_max_free_block_size() keeping old function name for (dot) releases. //C TODO: update at next major release. //C size_t umm_max_free_block_size( void ) { -size_t umm_max_block_size_core( void ) { - umm_heap_context_t *_context = umm_get_current_heap(); +size_t umm_max_block_size_core( umm_heap_context_t *_context ) { return _context->info.maxFreeContiguousBlocks * sizeof(umm_block); } size_t umm_max_block_size( void ) { umm_info(NULL, false); - return umm_max_block_size_core(); + return umm_max_block_size_core(umm_get_current_heap()); } /* @@ -202,13 +200,7 @@ size_t umm_max_block_size( void ) { umm_fragmentation_metric() must to be preceeded by a call to umm_info(NULL, false) for updated results. */ -int umm_usage_metric( void ) { -#ifndef UMM_INLINE_METRICS - umm_info(NULL, false); -#endif - - umm_heap_context_t *_context = umm_get_current_heap(); - +int umm_usage_metric_core( umm_heap_context_t *_context ) { //C Note, umm_metrics also appears in the upstrean w/o definition. I suspect it is suppose to be ummHeapInfo. // DBGLOG_DEBUG( "usedBlocks %d totalBlocks %d\n", umm_metrics.usedBlocks, ummHeapInfo.totalBlocks); DBGLOG_DEBUG( "usedBlocks %d totalBlocks %d\n", _context->info.usedBlocks, _context->info.totalBlocks); @@ -218,10 +210,16 @@ int umm_usage_metric( void ) { return -1; // no freeBlocks } +int umm_usage_metric( void ) { +#ifndef UMM_INLINE_METRICS + umm_info(NULL, false); +#endif + + return umm_usage_metric_core(umm_get_current_heap()); +} uint32_t sqrt32 (uint32_t n); -int umm_fragmentation_metric_core( void ) { - umm_heap_context_t *_context = umm_get_current_heap(); +int umm_fragmentation_metric_core( umm_heap_context_t *_context ) { // DBGLOG_DEBUG( "freeBlocks %d freeBlocksSquared %d\n", umm_metrics.freeBlocks, ummHeapInfo.freeBlocksSquared); DBGLOG_DEBUG( "freeBlocks %d freeBlocksSquared %d\n", _context->info.freeBlocks, _context->info.freeBlocksSquared); if (0 == _context->info.freeBlocks) { @@ -237,7 +235,7 @@ int umm_fragmentation_metric( void ) { umm_info(NULL, false); #endif - return umm_fragmentation_metric_core(); + return umm_fragmentation_metric_core(umm_get_current_heap()); } #ifdef UMM_INLINE_METRICS diff --git a/cores/esp8266/umm_malloc/umm_local.c b/cores/esp8266/umm_malloc/umm_local.c index 2e4e417b27..3eca39c6d8 100644 --- a/cores/esp8266/umm_malloc/umm_local.c +++ b/cores/esp8266/umm_malloc/umm_local.c @@ -209,7 +209,7 @@ int ICACHE_FLASH_ATTR umm_info_safe_printf_P(const char *fmt, ...) { the PROGMEM address must be word (4 bytes) aligned. The destination address for ets_memcpy must also be word-aligned. */ - char ram_buf[ets_strlen(fmt)] __attribute__ ((aligned(4))); + char ram_buf[ets_strlen(fmt) + 1] __attribute__((aligned(4))); ets_strcpy(ram_buf, fmt); va_list argPtr; va_start(argPtr, fmt); diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 12b22af5c5..57fa8eea53 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -129,7 +129,7 @@ size_t umm_get_current_heap_id(void) { return 0; } -static umm_heap_context_t *umm_get_current_heap(void) { +umm_heap_context_t *umm_get_current_heap(void) { return &heap_context[0]; } @@ -148,7 +148,7 @@ size_t umm_get_current_heap_id(void) { return umm_heap_cur; } -static umm_heap_context_t *umm_get_current_heap(void) { +umm_heap_context_t *umm_get_current_heap(void) { return &heap_context[umm_heap_cur]; } diff --git a/cores/esp8266/umm_malloc/umm_malloc.h b/cores/esp8266/umm_malloc/umm_malloc.h index cdc38899f8..1739cff2d1 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.h +++ b/cores/esp8266/umm_malloc/umm_malloc.h @@ -39,7 +39,7 @@ extern umm_heap_context_t *umm_push_heap( size_t heap_number ); extern umm_heap_context_t *umm_pop_heap( void ); extern umm_heap_context_t *umm_set_heap_by_id( size_t which ); extern size_t umm_get_current_heap_id(void); - +extern umm_heap_context_t *umm_get_current_heap(void); #ifdef __cplusplus } diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index 6d24bfb8f9..aa93255111 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -239,6 +239,8 @@ extern char _heap_start[]; UMM_HEAP_INFO; // extern UMM_HEAP_INFO ummHeapInfo; +struct UMM_HEAP_CONTEXT; +typedef struct UMM_HEAP_CONTEXT umm_heap_context_t; extern ICACHE_FLASH_ATTR void *umm_info( void *ptr, bool force ); #ifdef UMM_INLINE_METRICS @@ -250,9 +252,10 @@ extern char _heap_start[]; extern ICACHE_FLASH_ATTR size_t umm_max_block_size( void ); extern ICACHE_FLASH_ATTR int umm_usage_metric( void ); extern ICACHE_FLASH_ATTR int umm_fragmentation_metric( void ); - extern ICACHE_FLASH_ATTR size_t umm_free_heap_size_core( void ); - extern ICACHE_FLASH_ATTR size_t umm_max_block_size_core( void ); - extern ICACHE_FLASH_ATTR int umm_fragmentation_metric_core( void ); + extern ICACHE_FLASH_ATTR size_t umm_free_heap_size_core( umm_heap_context_t *_context ); + extern ICACHE_FLASH_ATTR size_t umm_max_block_size_core( umm_heap_context_t *_context ); + extern ICACHE_FLASH_ATTR int umm_usage_metric_core( umm_heap_context_t *_context ); + extern ICACHE_FLASH_ATTR int umm_fragmentation_metric_core( umm_heap_context_t *_context ); #else #define umm_info(p,b) #define umm_free_heap_size() (0) @@ -264,9 +267,6 @@ extern char _heap_start[]; #define umm_fragmentation_metric_core() (0) #endif -struct UMM_HEAP_CONTEXT; -typedef struct UMM_HEAP_CONTEXT umm_heap_context_t; - /* * -D UMM_STATS : * -D UMM_STATS_FULL diff --git a/doc/mmu.rst b/doc/mmu.rst index 6a5ebdfc07..f010a655bc 100644 --- a/doc/mmu.rst +++ b/doc/mmu.rst @@ -11,19 +11,18 @@ it can be used as a transparent cache for external flash memory. These blocks can either be used for IRAM or an instruction cache for executing code out of flash, ICACHE. -The instructions generated for a sketch are divided up into two groups -ICACHE and IRAM. IRAM offers faster access/execution. It is commonly -used for interrupt service routines, exception handling, and -time-critical code. ICACHE allows for the execution of up to 1MB of code -in flash. On a cache miss, a delay occurs as the instructions are read -from flash via the SPI bus. - -There is 96KB of DRAM space. This memory can be accessed as byte, short, -or a 32-bit word. Access must be aligned according to the data element -size. A 16bit short must be on a multiple of 2-byte address boundary, -likewise, a 32-bit word must be on a multiple of 4-byte address -boundary. In contrast, data access to IRAM or ICACHE must always be a -full 32-bit word and aligned. We will introduce a non32-bit exception +The code generated for a sketch is divided up into two groups, ICACHE +and IRAM. IRAM offers faster execution. It is used for interrupt service +routines, exception handling, and time-critical code. The ICACHE allows +for the execution of up to 1MB of code stored in flash. On a cache miss, +a delay occurs as the instructions are read from flash via the SPI bus. + +There is 98KB of DRAM space. This memory can be accessed as byte, short, +or a 32-bit word. Access must be aligned according to the data type +size. A 16bit short must be on a multiple of 2-byte address boundary. +Likewise, a 32-bit word must be on a multiple of 4-byte address +boundary. In contrast, data access in IRAM or ICACHE must always be a +full 32-bit word and aligned. We will discuss a non32-bit exception handler for this later. Option Summary @@ -42,17 +41,17 @@ The Arduino IDE Tools menu option, ``MMU`` has the following selections: - With just 16KB cache, execution of code out of flash may be slowed by more cache misses when compared to 32KB. The slowness will vary with the sketch. - - Use this if you need a little more IRAM space and you are good on + - Use this if you need a little more IRAM space, and you have enough DRAM space. 3. ``16KB cache + 48KB IRAM and 2nd Heap (shared)`` - - This option builds on the previous option and builds a 2nd Heap + - This option builds on the previous option and creates a 2nd Heap made with IRAM. - The 2nd Heap size will vary with free IRAM. - This option is flexible. IRAM usage for code can overflow into the - additional 16KB IRAM region shrinking the 2nd Heap below 16KB. Or - IRAM can be under 32KB allowing the 2nd Heap to be larger than + additional 16KB IRAM region, shrinking the 2nd Heap below 16KB. Or + IRAM can be under 32KB, allowing the 2nd Heap to be larger than 16KB. - Installs a Non-32-Bit Access handler for IRAM. This allows for byte and 16-bit aligned short access. @@ -66,14 +65,15 @@ The Arduino IDE Tools menu option, ``MMU`` has the following selections: 4. ``16KB cache + 32KB IRAM + 16KB 2nd Heap (not shared)`` - Not managed by the ``umm_malloc`` heap library - - Non-32-Bit Access for IRAM must be enabled separately - - A 16KB block of unmanaged memory. + - If required, non-32-Bit Access for IRAM must be enabled + separately. + - Enables a 16KB block of unmanaged IRAM memory - Data persist across reboots, but not deep sleep. - - This may be best for when you just need a large chunk of memory. - This option will free up the additional resources needed by - ``umm_malloc`` to support managing the 2nd Heap. + - Works well for when you need a simple large chunk of memory. This + option will reduce the resources required to support a shared 2nd + Heap. -MMU related build defines and possible values.These values change as +MMU related build defines and possible values. These values change as indicated with the menu options above: +-------------------------+--------------+--------------+------------------------------------+------------------------------+ @@ -101,10 +101,10 @@ The Arduino IDE Tools menu option, ``Non-32-Bit Access`` has the following selec - This option adds a non32-bit exception handler to your build. - Handles read/writes to IRAM and reads to ICACHE. - - Supports short and byte access to IRAM. + - Supports short and byte access to IRAM - Not recommended for high-frequency access data, use DRAM if you can. - - Expect it to be slower than DRAM, each character access will + - Expect it to be slower than DRAM, each character access, will require a complete save and restore of all 16+ registers. - Processing an exception uses 256 bytes of stack space just to get started. The actual handler will add a little more. @@ -113,9 +113,9 @@ The Arduino IDE Tools menu option, ``Non-32-Bit Access`` has the following selec IRAM, unlike DRAM, must be accessed as aligned full 32-bit words, no byte or short access. The pgm\_read macros are an option; however, the -store operation remains an issue. For a block copy ets\_memcpy - appears +store operation remains an issue. For a block copy, ets\_memcpy appears to work well as long as the byte count is rounded up to be evenly -divided by 4 and source and destination addresses are 4 bytes aligned. +divided by 4, and source and destination addresses are 4 bytes aligned. A word of caution, I have seen one case with the new toolchain 10.1 where code that reads a 32-bit word to extract a byte was optimized away @@ -137,9 +137,11 @@ For calls to ``umm_malloc`` with interrupts disabled. ``DRAM`` heap allocation. Note, calling ``realloc`` with interrupts disabled is **not** officially supported. You are on your own if you do this. -- If you must use IRAM memory in your ISR, allocate the memory ahead of - time. To reduce the time spent in the ISR, avoid non32-bit access - that would trigger the exception handler. +- If you must use IRAM memory in your ISR, allocate the memory in your + init code. To reduce the time spent in the ISR, avoid non32-bit + access that would trigger the exception handler. For short or byte + access, consider using the inline functions described in section + "Performance Functions" below. I think this block should go away and we always use ``USE_ISR_SAFE_EXC_WRAPPER`` with the exception handler. @@ -168,11 +170,11 @@ How to Select Heap The ``MMU`` selection ``16KB cache + 48KB IRAM and 2nd Heap (shared)`` allows you to use the standard heap API function calls (``malloc``, -``calloc``, ``free``, ... ). to allocate memory from DRAM or IRAM. The +``calloc``, ``free``, ... ). to allocate memory from DRAM or IRAM. This selection can be made by instantiating the class ``HeapSelectIram`` or -``HeapSelectDram``.The usage is similar to that of the ``InterruptLock`` -class. The default/initial heap source is DRAM. The class is in -``umm_malloc/umm_heap_select.h`` +``HeapSelectDram``. The usage is similar to that of the +``InterruptLock`` class. The default/initial heap source is DRAM. The +class is in ``umm_malloc/umm_heap_select.h``. :: @@ -196,7 +198,7 @@ for tracking and selecting before freeing. from the original heap it was allocated from. When the supplied pointer is NULL, then the current heap selection is used. -Low level primatives for selecting a heap. These are used by the above +Low-level primitives for selecting a heap. These are used by the above Classes: - ``umm_get_current_heap_id()`` @@ -205,8 +207,8 @@ Classes: - ``UMM_HEAP_DRAM`` - ``UMM_HEAP_IRAM`` -Also, an alternate stack select based API is available. This is not as -easy as the class method; however, for some small set of cases it may +Also, an alternate stack select method API is available. This is not as +easy as the class method; however, for some small set of cases, it may provide some additional control: - ``ESP.setIramHeap()`` Pushes current heap ID onto a stack and sets @@ -228,7 +230,7 @@ a pointer: Performance Functions ~~~~~~~~~~~~~~~~~~~~~ -While these, always inlined functions, will bypass the need for the +While these always inlined functions, will bypass the need for the exception handler reducing execution time and stack use, it comes at the cost of increased code size. diff --git a/libraries/esp8266/examples/IramReserve/IramReserve.ino b/libraries/esp8266/examples/IramReserve/IramReserve.ino new file mode 100644 index 0000000000..efcc63f76a --- /dev/null +++ b/libraries/esp8266/examples/IramReserve/IramReserve.ino @@ -0,0 +1,117 @@ +/* + This example show one way of maintaining a boot count across reboots. + We will store the value in IRAM after the 2nd Heap. + + The remaining IRAM out the 48KB, after your code, is mostly untouched during the reboot process. + For a given executable that does not do deep-sleep, it is possible to pass/hold + information between reboot cycles. + + The objective of this example is to show how to modify the 2nd Heap creation such that + a block of IRAM at the end of the 2nd Heap is left untouched and available for special use cases. + +*/ + +#include +#include +#include +//#include + + +#ifndef UMM_HEAP_IRAM +#error "This sketch requires Tools Option: 'MMU: 16KB cache + 48KB IRAM and 2nd Heap (shared)'" +#endif + +// durable - as in long life, persisting across reboots. +struct durable { + uint32_t bootCounter; + uint32_t chksum; +}; + + +// Leave a durable block of IRAM after the 2nd heap. + +// The block should be in 8-byte increments and fall on an 8-byte alignment. +#define IRAM_RESERVE_SZ ((sizeof(struct durable) + 7UL) & ~7UL) + +// Position its address just above the reduced 2nd Heap. +#define IRAM_RESERVE (0x40100000UL + 0xC000UL - IRAM_RESERVE_SZ) + +// Define a reference with the right properties to make access easier. +#define DURABLE ((struct durable *)IRAM_RESERVE) +#define INCREMENT_BOOTCOUNT() (DURABLE->bootCounter)++ + +extern struct rst_info resetInfo; + +/* + Define a function to determine if IRAM stored data is valid. The criteria used + here can vary with how exhaustively you want the process to be. + + In this example, we are just going to look at the reset cause and assume all + is well in certain situations. For this example, we include + REASON_EXT_SYS_RST as a possible case for IRAM not being valid. The problem + here is some devices will indicate REASON_EXT_SYS_RST for the Power-on case. + + If you wanted to be able to isolate the power-on case from a + REASON_EXT_SYS_RST, you could add additional logic to set and verify a CRC or + XOR sum on the IRAM data (or just a section of the IRAM data). +*/ +inline bool is_iram_valid(void) { + return(REASON_WDT_RST <= resetInfo.reason && + REASON_SOFT_RESTART >= resetInfo.reason); +} + + +void setup() { + WiFi.persistent(false); + WiFi.mode(WIFI_OFF); + Serial.begin(115200); + delay(10); + Serial.printf_P(PSTR("\r\nSetup ...\r\n")); + + if (!is_iram_valid()) { + DURABLE->bootCounter = 0; + } + + DURABLE->bootCounter++; + + Serial.printf("Number of reboots at %u\r\n", DURABLE->bootCounter); + Serial.printf("\r\nSome less than direct, ways to restart:\r\n"); + processKey(Serial, '?'); +} + +void loop(void) { + if (Serial.available() > 0) { + int hotKey = Serial.read(); + processKey(Serial, hotKey); + } +} + +////////////////////////////////////////////////////////////////////////////// + +#ifdef UMM_HEAP_IRAM +/* + Create a block of unmanaged IRAM for special uses. + + This is done by reducing the size of the managed 2nd Heap (Shared) at + initialization time. +*/ + +extern "C" void _text_end(void); + +extern "C" void umm_init_iram(void) { + /* + Calculate the start of 2nd heap, staying clear of possible segment alignment + adjustments and checksums. These can affect the persistence of data across + reboots. + */ + uint32_t sec_heap = (uint32_t)_text_end + 32; + sec_heap &= ~7; + size_t sec_heap_sz = 0xC000UL - (sec_heap - 0x40100000UL); + sec_heap_sz -= IRAM_RESERVE_SZ; // Shrink IRAM heap + if (0xC000UL > sec_heap_sz) { + + umm_init_iram_ex((void *)sec_heap, sec_heap_sz, true); + } +} + +#endif diff --git a/libraries/esp8266/examples/IramReserve/ProcessKey.ino b/libraries/esp8266/examples/IramReserve/ProcessKey.ino new file mode 100644 index 0000000000..9c12ac7c1c --- /dev/null +++ b/libraries/esp8266/examples/IramReserve/ProcessKey.ino @@ -0,0 +1,116 @@ +#include +void crashMeIfYouCan(void)__attribute__((weak)); +int divideA_B(int a, int b); + +int* nullPointer = NULL; + +void processKey(Print& out, int hotKey) { + switch (hotKey) { + case 'r': + out.printf_P(PSTR("Reset, ESP.reset(); ...\r\n")); + ESP.reset(); + break; + case 't': + out.printf_P(PSTR("Restart, ESP.restart(); ...\r\n")); + ESP.restart(); + break; + case 's': { + uint32_t startTime = millis(); + out.printf_P(PSTR("Now crashing with Software WDT. This will take about 3 seconds.\r\n")); + ets_install_putc1(ets_putc); + while (true) { + ets_printf("%9lu\r", (millis() - startTime)); + ets_delay_us(250000); + // stay in an loop blocking other system activity. + } + } + break; + case 'h': + out.printf_P(PSTR("Now crashing with Hardware WDT. This will take about 6 seconds.\r\n")); + asm volatile("mov.n a2, %0\n\t" + "mov.n a3, %1\n\t" + "mov.n a4, %2\n\t" + "mov.n a5, %3\n\t" + "mov.n a6, %4\n\t" + : : "r"(0xaaaaaaaa), "r"(0xaaaaaaaa), "r"(0xaaaaaaaa), "r"(0xaaaaaaaa), "r"(0xaaaaaaaa) : "memory"); + // Could not find these in the stack dump, unless interrupts were enabled. + { + uint32_t startTime = millis(); + // Avoid all the Core functions that play nice, so we can hog + // the system and crash. + ets_install_putc1(ets_putc); + xt_rsil(15); + while (true) { + ets_printf("%9lu\r", (millis() - startTime)); + ets_delay_us(250000); + // stay in an loop blocking other system activity. + // + // Note: + // Hardware WDT kicks in if Software WDT is unable to perform. + // With the Hardware WDT, nothing is saved on the stack, that I have seen. + } + } + break; + case 'p': + out.println(F("Time to panic()!")); + panic(); + break; + case 'z': + out.println(F("Crashing by dividing by zero. This should generate an exception(0).")); + out.printf_P(PSTR("This should not print %d\n"), divideA_B(1, 0)); + break; + case 'w': + out.println(F("Now calling: void crashMeIfYouCan(void)__attribute__((weak));")); + out.println(F("This function has a prototype but was missing when the sketch was linked. ...")); + crashMeIfYouCan(); + break; + case 'b': + out.println(F("Executing a break instruction w/o GDB will cause a HWDT reset.")); + asm volatile("break 1, 15;"); + out.println(F("This line will not be printable w/o running GDB")); + break; + case '0': + out.println(F("Crashing at an embeded 'break 1, 15' instruction that was generated")); + out.println(F("by the compiler after detecting a divide by zero.")); + out.printf_P(PSTR("This should not print %d\n"), divideA_B_bp(1, 0)); + break; + case '\r': + out.println(); + case '\n': + break; + case '?': + out.println(); + out.println(F("Press a key + ")); + out.println(F(" r - Reset, ESP.reset();")); + out.println(F(" t - Restart, ESP.restart();")); + out.println(F(" ? - Print Help")); + out.println(); + out.println(F("Crash with:")); + out.println(F(" s - Software WDT")); + out.println(F(" h - Hardware WDT - looping with interrupts disabled")); + out.println(F(" w - Hardware WDT - calling a missing (weak) function.")); + out.println(F(" 0 - Hardware WDT - a hard coded compiler breakpoint from a compile time detected divide by zero")); + out.println(F(" b - Hardware WDT - a forgotten hard coded 'break 1, 15;' and no GDB running.")); + out.println(F(" z - Divide by zero, exception(0);")); + out.println(F(" p - panic();")); + out.println(); + break; + default: + out.printf_P(PSTR("\"%c\" - Not an option? / ? - help"), hotKey); + out.println(); + processKey(out, '?'); + break; + } +} + +// With the current toolchain 10.1, using this to divide by zero will *not* be +// caught at compile time. +int __attribute__((noinline)) divideA_B(int a, int b) { + return (a / b); +} + +// With the current toolchain 10.1, using this to divide by zero *will* be +// caught at compile time. And a hard coded breakpoint will be inserted. +int divideA_B_bp(int a, int b) { + return (a / b); +} From a4d28e2dd0604ac235facb28aab5d10af94fe38a Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 26 Jul 2020 16:30:51 -0700 Subject: [PATCH 34/48] CI appeasement --- cores/esp8266/mmu_iram.h | 6 +++--- libraries/esp8266/examples/IramReserve/IramReserve.ino | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 6201e2216a..56c0c866e2 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -121,7 +121,7 @@ bool mmu_is_iram(const void *addr) { #endif #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) - return (IRAM_START <= (uint32_t)addr && IRAM_END > (uint32_t)addr); + return (IRAM_START <= (uintptr_t)addr && IRAM_END > (uintptr_t)addr); } static inline __attribute__((always_inline)) @@ -129,7 +129,7 @@ bool mmu_is_dram(const void *addr) { #define DRAM_START 0x3FF80000UL #define DRAM_END 0x40000000UL - return (DRAM_START <= (uint32_t)addr && DRAM_END > (uint32_t)addr); + return (DRAM_START <= (uintptr_t)addr && DRAM_END > (uintptr_t)addr); } static inline __attribute__((always_inline)) @@ -137,7 +137,7 @@ bool mmu_is_icache(const void *addr) { #define ICACHE_START 0x40200000UL #define ICACHE_END (ICACHE_START + 0x100000UL) - return (ICACHE_START <= (uint32_t)addr && ICACHE_END > (uint32_t)addr); + return (ICACHE_START <= (uintptr_t)addr && ICACHE_END > (uintptr_t)addr); } #ifdef DEBUG_ESP_MMU diff --git a/libraries/esp8266/examples/IramReserve/IramReserve.ino b/libraries/esp8266/examples/IramReserve/IramReserve.ino index efcc63f76a..9674817e14 100644 --- a/libraries/esp8266/examples/IramReserve/IramReserve.ino +++ b/libraries/esp8266/examples/IramReserve/IramReserve.ino @@ -17,7 +17,7 @@ //#include -#ifndef UMM_HEAP_IRAM +#if !defined(UMM_HEAP_IRAM) && !defined(MOCK) #error "This sketch requires Tools Option: 'MMU: 16KB cache + 48KB IRAM and 2nd Heap (shared)'" #endif @@ -56,8 +56,8 @@ extern struct rst_info resetInfo; XOR sum on the IRAM data (or just a section of the IRAM data). */ inline bool is_iram_valid(void) { - return(REASON_WDT_RST <= resetInfo.reason && - REASON_SOFT_RESTART >= resetInfo.reason); + return (REASON_WDT_RST <= resetInfo.reason && + REASON_SOFT_RESTART >= resetInfo.reason); } From d45ceb0e0260de10bd4cbbb828982bdcf544207d Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 26 Jul 2020 18:40:31 -0700 Subject: [PATCH 35/48] CI appeasement with comment correction. --- .../examples/IramReserve/IramReserve.ino | 31 ++++++++++++------- 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/libraries/esp8266/examples/IramReserve/IramReserve.ino b/libraries/esp8266/examples/IramReserve/IramReserve.ino index 9674817e14..d92477ff8a 100644 --- a/libraries/esp8266/examples/IramReserve/IramReserve.ino +++ b/libraries/esp8266/examples/IramReserve/IramReserve.ino @@ -2,24 +2,20 @@ This example show one way of maintaining a boot count across reboots. We will store the value in IRAM after the 2nd Heap. - The remaining IRAM out the 48KB, after your code, is mostly untouched during the reboot process. - For a given executable that does not do deep-sleep, it is possible to pass/hold - information between reboot cycles. + Of the 48KB of IRAM, the remaining IRAM after your code is mostly untouched + during the reboot process. For a given executable that does not do + deep-sleep, it is possible to pass/hold information between reboot cycles. - The objective of this example is to show how to modify the 2nd Heap creation such that - a block of IRAM at the end of the 2nd Heap is left untouched and available for special use cases. + The objective of this example is to show how to modify the 2nd Heap creation + such that a block of IRAM at the end of the 2nd Heap is left untouched and + available for special use cases. */ #include #include #include -//#include - - -#if !defined(UMM_HEAP_IRAM) && !defined(MOCK) -#error "This sketch requires Tools Option: 'MMU: 16KB cache + 48KB IRAM and 2nd Heap (shared)'" -#endif +#if defined(UMM_HEAP_IRAM) // durable - as in long life, persisting across reboots. struct durable { @@ -77,6 +73,7 @@ void setup() { Serial.printf("Number of reboots at %u\r\n", DURABLE->bootCounter); Serial.printf("\r\nSome less than direct, ways to restart:\r\n"); processKey(Serial, '?'); + } void loop(void) { @@ -88,7 +85,6 @@ void loop(void) { ////////////////////////////////////////////////////////////////////////////// -#ifdef UMM_HEAP_IRAM /* Create a block of unmanaged IRAM for special uses. @@ -114,4 +110,15 @@ extern "C" void umm_init_iram(void) { } } +#else +void setup() { + WiFi.persistent(false); + WiFi.mode(WIFI_OFF); + Serial.begin(115200); + delay(10); + Serial.println("\r\n\r\nThis sketch requires Tools Option: 'MMU: 16KB cache + 48KB IRAM and 2nd Heap (shared)'"); +} + +void loop(void) { +} #endif From 48314101e05a4af8749abd8198a87e35ae4470a7 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 28 Jul 2020 09:50:57 -0700 Subject: [PATCH 36/48] Ensure SYS always runs with DRAM Heap selected. --- cores/esp8266/core_esp8266_main.cpp | 8 ++++++++ cores/esp8266/umm_malloc/umm_malloc.cpp | 9 ++++++++- cores/esp8266/umm_malloc/umm_malloc.h | 5 +++-- cores/esp8266/umm_malloc/umm_malloc_cfg.h | 4 ++++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 1d62ea6d4c..f5b70d3aae 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -204,7 +204,14 @@ static void loop_wrapper() { static void loop_task(os_event_t *events) { (void) events; s_cycles_at_yield_start = ESP.getCycleCount(); + ESP.resetHeap(); cont_run(g_pcont, &loop_wrapper); + ESP.setDramHeap(); +#if defined(DEBUG_ESP_CORE) && (UMM_NUM_HEAPS > 1) + if (UMM_HEAP_STACK_DEPTH <= umm_get_heap_stack_index()) { + panic(); + } +#endif if (cont_check(g_pcont) != 0) { panic(); } @@ -256,6 +263,7 @@ void init_done() { std::set_terminate(__unhandled_exception_cpp); do_global_ctors(); esp_schedule(); + ESP.setDramHeap(); } /* This is the entry point of the application. diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index 57fa8eea53..a2c345c562 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -114,7 +114,6 @@ umm_heap_context_t heap_context[UMM_NUM_HEAPS] __attribute__((section(".noinit") #else static size_t umm_heap_cur = UMM_HEAP_DRAM; -#define UMM_HEAP_STACK_DEPTH 32 static int umm_heap_stack_ptr = 0; static unsigned char umm_heap_stack[UMM_HEAP_STACK_DEPTH]; #endif @@ -179,6 +178,9 @@ umm_heap_context_t *umm_pop_heap( void ) { return &heap_context[0]; } +int umm_get_heap_stack_index( void ) { + return 0; +} #else /* ------------------------------------------------------------------------ */ @@ -198,6 +200,11 @@ umm_heap_context_t *umm_pop_heap( void ) { } return NULL; } + +// Intended for diagnosic use +int umm_get_heap_stack_index( void ) { + return umm_heap_stack_ptr; +} #endif /* ------------------------------------------------------------------------ */ /* diff --git a/cores/esp8266/umm_malloc/umm_malloc.h b/cores/esp8266/umm_malloc/umm_malloc.h index 1739cff2d1..f7dcc72c1b 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.h +++ b/cores/esp8266/umm_malloc/umm_malloc.h @@ -37,9 +37,10 @@ extern void umm_free( void *ptr ); extern umm_heap_context_t *umm_push_heap( size_t heap_number ); extern umm_heap_context_t *umm_pop_heap( void ); +extern int umm_get_heap_stack_index( void ); extern umm_heap_context_t *umm_set_heap_by_id( size_t which ); -extern size_t umm_get_current_heap_id(void); -extern umm_heap_context_t *umm_get_current_heap(void); +extern size_t umm_get_current_heap_id( void ); +extern umm_heap_context_t *umm_get_current_heap( void ); #ifdef __cplusplus } diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfg.h b/cores/esp8266/umm_malloc/umm_malloc_cfg.h index aa93255111..7a90db0733 100644 --- a/cores/esp8266/umm_malloc/umm_malloc_cfg.h +++ b/cores/esp8266/umm_malloc/umm_malloc_cfg.h @@ -67,6 +67,10 @@ extern "C" { #define UMM_NUM_HEAPS (UMM_HEAP_DRAM_DEFINED + UMM_HEAP_IRAM_DEFINED + UMM_HEAP_EXTERNAL_DEFINED) +#if (UMM_NUM_HEAPS == 1) +#else +#define UMM_HEAP_STACK_DEPTH 32 +#endif /* * There are a number of defines you can set at compile time that affect how From f64a7d00d335df050f6b16b21432cf67d9523c6b Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 28 Jul 2020 10:59:07 -0700 Subject: [PATCH 37/48] Add/move heap stack overflow/underflow check to Esp.cpp where the event was discarded. --- cores/esp8266/Esp.cpp | 42 ++++++++++++++++++----------- cores/esp8266/core_esp8266_main.cpp | 5 ---- 2 files changed, 26 insertions(+), 21 deletions(-) diff --git a/cores/esp8266/Esp.cpp b/cores/esp8266/Esp.cpp index e21b43af8b..130499bd77 100644 --- a/cores/esp8266/Esp.cpp +++ b/cores/esp8266/Esp.cpp @@ -528,45 +528,45 @@ uint8_t *EspClass::random(uint8_t *resultArray, const size_t outputSizeBytes) co { /** * The ESP32 Technical Reference Manual v4.1 chapter 24 has the following to say about random number generation (no information found for ESP8266): - * + * * "When used correctly, every 32-bit value the system reads from the RNG_DATA_REG register of the random number generator is a true random number. * These true random numbers are generated based on the noise in the Wi-Fi/BT RF system. * When Wi-Fi and BT are disabled, the random number generator will give out pseudo-random numbers. - * + * * When Wi-Fi or BT is enabled, the random number generator is fed two bits of entropy every APB clock cycle (normally 80 MHz). * Thus, for the maximum amount of entropy, it is advisable to read the random register at a maximum rate of 5 MHz. * A data sample of 2 GB, read from the random number generator with Wi-Fi enabled and the random register read at 5 MHz, * has been tested using the Dieharder Random Number Testsuite (version 3.31.1). * The sample passed all tests." - * + * * Since ESP32 is the sequal to ESP8266 it is unlikely that the ESP8266 is able to generate random numbers more quickly than 5 MHz when run at a 80 MHz frequency. * A maximum random number frequency of 0.5 MHz is used here to leave some margin for possibly inferior components in the ESP8266. * It should be noted that the ESP8266 has no Bluetooth functionality, so turning the WiFi off is likely to cause RANDOM_REG32 to use pseudo-random numbers. - * - * It is possible that yield() must be called on the ESP8266 to properly feed the hardware random number generator new bits, since there is only one processor core available. + * + * It is possible that yield() must be called on the ESP8266 to properly feed the hardware random number generator new bits, since there is only one processor core available. * However, no feeding requirements are mentioned in the ESP32 documentation, and using yield() could possibly cause extended delays during number generation. * Thus only delayMicroseconds() is used below. - */ + */ constexpr uint8_t cooldownMicros = 2; static uint32_t lastCalledMicros = micros() - cooldownMicros; uint32_t randomNumber = 0; - + for(size_t byteIndex = 0; byteIndex < outputSizeBytes; ++byteIndex) { if(byteIndex % 4 == 0) { // Old random number has been used up (random number could be exactly 0, so we can't check for that) - + uint32_t timeSinceLastCall = micros() - lastCalledMicros; if(timeSinceLastCall < cooldownMicros) delayMicroseconds(cooldownMicros - timeSinceLastCall); - + randomNumber = RANDOM_REG32; lastCalledMicros = micros(); } - + resultArray[byteIndex] = randomNumber; randomNumber >>= 8; } @@ -789,19 +789,29 @@ void EspClass::setIramHeap() void EspClass::setDramHeap() { #if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM) - if (vmEnabled) - umm_push_heap(UMM_HEAP_DRAM); + if (vmEnabled) { + if (!umm_push_heap(UMM_HEAP_DRAM)) { + panic(); + } + } #elif defined(UMM_HEAP_IRAM) - umm_push_heap(UMM_HEAP_DRAM); + if (!umm_push_heap(UMM_HEAP_DRAM)) { + panic(); + } #endif } void EspClass::resetHeap() { #if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM) - if (vmEnabled) - umm_pop_heap(); + if (vmEnabled) { + if (!umm_pop_heap()) { + panic(); + } + } #elif defined(UMM_HEAP_IRAM) - umm_pop_heap(); + if (!umm_pop_heap()) { + panic(); + } #endif } diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index f5b70d3aae..5bb341ec59 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -207,11 +207,6 @@ static void loop_task(os_event_t *events) { ESP.resetHeap(); cont_run(g_pcont, &loop_wrapper); ESP.setDramHeap(); -#if defined(DEBUG_ESP_CORE) && (UMM_NUM_HEAPS > 1) - if (UMM_HEAP_STACK_DEPTH <= umm_get_heap_stack_index()) { - panic(); - } -#endif if (cont_check(g_pcont) != 0) { panic(); } From 2238535a586a064320c9b8e7f061854d24427d96 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Thu, 30 Jul 2020 07:44:40 -0700 Subject: [PATCH 38/48] Improved comment clarity of purpose for IramReserve.ino. Clean up MMU48K.ino --- .../examples/IramReserve/IramReserve.ino | 18 +++++++++--------- libraries/esp8266/examples/MMU48K/MMU48K.ino | 9 --------- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/libraries/esp8266/examples/IramReserve/IramReserve.ino b/libraries/esp8266/examples/IramReserve/IramReserve.ino index d92477ff8a..344622f958 100644 --- a/libraries/esp8266/examples/IramReserve/IramReserve.ino +++ b/libraries/esp8266/examples/IramReserve/IramReserve.ino @@ -1,15 +1,15 @@ /* - This example show one way of maintaining a boot count across reboots. - We will store the value in IRAM after the 2nd Heap. + Overview: Of the 48KB of IRAM, the remaining IRAM after your code is untouched + during the reboot process. For a sketch that does not use deep-sleep, it is + possible to pass/hold information across boot cycles in this area of IRAM. - Of the 48KB of IRAM, the remaining IRAM after your code is mostly untouched - during the reboot process. For a given executable that does not do - deep-sleep, it is possible to pass/hold information between reboot cycles. - - The objective of this example is to show how to modify the 2nd Heap creation - such that a block of IRAM at the end of the 2nd Heap is left untouched and - available for special use cases. + With the selection of Arduino IDE Tools Option: 'MMU: 16KB cache + 48KB IRAM + and 2nd Heap (shared)' all of this space goes into a managed 2nd Heap. + Managed, in this case, refers to using malloc, free, realloc, etc. API. + The objective of this example is to show how to modify the 2nd Heap creation + to omit a block of IRAM at the end of the 2nd Heap. In this example, we use + this block to store a boot count. */ #include diff --git a/libraries/esp8266/examples/MMU48K/MMU48K.ino b/libraries/esp8266/examples/MMU48K/MMU48K.ino index 0916e8e855..6acb3840f9 100644 --- a/libraries/esp8266/examples/MMU48K/MMU48K.ino +++ b/libraries/esp8266/examples/MMU48K/MMU48K.ino @@ -167,17 +167,12 @@ void setup() { } - -extern uint32_t mmu_non32xfer_count; - void processKey(Print& out, int hotKey) { switch (hotKey) { case 't': { uint32_t tmp; out.printf_P(PSTR("Test how much time is added by exception handling")); out.println(); - out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); - out.println(); out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read((char *)0x40200003, &tmp), tmp); out.println(); out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read((char *)0x40200003, &tmp), tmp); @@ -186,8 +181,6 @@ void processKey(Print& out, int hotKey) { out.println(); out.printf_P(PSTR("Timed byte read from dRAM %u cpu cycle count, 0x%02X."), timed_byte_read((char *)((uintptr_t)&read_var + 1), &tmp), tmp); out.println(); - out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); - out.println(); out.printf_P(PSTR("Test how much time is used by the inline function method")); out.println(); out.printf_P(PSTR("Timed byte read from iCACHE %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)0x40200003, &tmp), tmp); @@ -198,8 +191,6 @@ void processKey(Print& out, int hotKey) { out.println(); out.printf_P(PSTR("Timed byte read from dRAM %u cpu cycle count, 0x%02X."), timed_byte_read2((char *)((uintptr_t)&read_var + 1), &tmp), tmp); out.println(); - out.printf_P(PSTR("mmu_non32xfer_count %u"), mmu_non32xfer_count); - out.println(); out.println(); break; } From c070657685c780fada7239bc3c4d6ab72393a230 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 4 Aug 2020 11:51:38 -0700 Subject: [PATCH 39/48] Added missing #include --- cores/esp8266/mmu_iram.h | 1 + 1 file changed, 1 insertion(+) diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 56c0c866e2..249d8c9121 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -20,6 +20,7 @@ #include #include #include +#include /* * DEV_DEBUG_MMU_IRAM: From be71429f6ffa8497e7dbc1cb98f2b3b3febc77e8 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 4 Aug 2020 12:53:19 -0700 Subject: [PATCH 40/48] Corrected usage of warning --- cores/esp8266/mmu_iram.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 249d8c9121..b60677799d 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -117,7 +117,9 @@ static inline __attribute__((always_inline)) bool mmu_is_iram(const void *addr) { #define IRAM_START 0x40100000UL #ifndef MMU_IRAM_SIZE - #pragma warning("MMU_IRAM_SIZE was undefined, setting to 0x8000UL!") +#if defined(__GNUC__) && !defined(CORE_MOCK) + #warning "MMU_IRAM_SIZE was undefined, setting to 0x8000UL!" +#endif #define MMU_IRAM_SIZE 0x8000UL #endif #define IRAM_END (IRAM_START + MMU_IRAM_SIZE) From 61afce0daa3688a9123a67ae382be8c74533ca1d Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Fri, 7 Aug 2020 07:36:47 -0700 Subject: [PATCH 41/48] CI appeasement and use #message not #pragma message --- cores/esp8266/mmu_iram.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index b60677799d..56e69424a0 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -42,6 +42,10 @@ #define DEBUG_ESP_MMU #endif +#if defined(CORE_MOCK) +#define ets_uart_printf(...) do {} while(false) +#endif + /* The more I look at _xtos_c_wrapper_handler the more convinced I am that this USE_ISR_SAFE_EXC_WRAPPER is required. From 7d4a6000d39b7bc2118c5e6ace787cd4eff3b212 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 2 Sep 2020 11:07:37 -0700 Subject: [PATCH 42/48] Updated git version of eboot.elf to match build version. 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zDK<^22h(Q~ejixAGYS7WHmD|5Bs}5nq>6+m!ktu+@Dbc}%b!j71UXQXDiWRucTz>d zUk$>YRFUvRxRWXp9>hp?Qbod(5lyOyu-tnchzft-rc0Q(z&i!Jgq5uUjgYv*D{24{ z?(m8lKn~pD6*Yh)?(m8lKvCV{6*Yj=+~E~9K>ZDJr&kn#*C9GPcU->RQEyTa4>rj7 zymNV;TtDwPpC;$c@6jerdGGvlj9!DW-pr}_N6I~&K4cavmWPJJzU0ur70HglbzA#4 zZjyXooqS@*oAXUxy}a$xTlxE$+WwA+kn1p>OJx|8ycGu+kN{8qM2=58-+D1 zPHs*yd3bo{w+`gH4rx~A@Q$4^>rONVoxS_LtTKFGkv{F~A0XMYY17b#O>5Wn4Q@&H z5y3K3Zhw+z{<*(e%jwyA$t8V*7jNm`(U-Yk?3JJvOUjuOWyW7_V=O6`Pn2t)+$ncV lR2m)((ka=sG$fBs1hn)4`P@XM_ToYLF=TrmVC)`}{U2gcq$L0V From 3f415f8d6df0c15a62c96800ec1fd8bf35121179 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Mon, 5 Oct 2020 18:09:53 -0700 Subject: [PATCH 43/48] Remove conditional build option USE_ISR_SAFE_EXC_WRAPPER, always install. Use the replacement wrapper on non32xfer_exception_handler install. Added comments to code describing some exception handling issues. --- cores/esp8266/core_esp8266_non32xfer.cpp | 98 ++++++------------------ cores/esp8266/mmu_iram.cpp | 37 +-------- cores/esp8266/mmu_iram.h | 74 ++++-------------- cores/esp8266/umm_malloc/umm_malloc.cpp | 77 ++++++++++++++++--- 4 files changed, 107 insertions(+), 179 deletions(-) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index ce2fc02ccc..55dd5d1bbd 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -47,19 +47,6 @@ extern "C" { #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Non 32-bit read/write error */ -uint32_t mmu_non32xfer_count = 0; -uint32_t mmu_non32xfer_withinisr_count = 0; - - -// #define DEBUG_WARNING -//C Do we want to keep this warning -#ifdef DEBUG_WARNING -static void warning(void) -{ - DBG_MMU_PRINTF("WARNING: The Non-32-bit transfer hander has been invoked, and performance may suffer.\n"); -} -#endif - static fn_exception_handler_t old_handler = NULL; static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) @@ -73,14 +60,11 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, Register a15 was used for epc1, then clobbered for rsr. Maybe an __asm("":::"memory") before starting the asm would help for these cases. For this instance moved setting epc1 closer to where it was used. - Edit. "&"" on output register would have resolved the problem. + Edit. "&" on output register would have resolved the problem. Refactored to reduce and consolidate register usage. */ uint32_t insn; __asm( -#if !defined(USE_ISR_SAFE_EXC_WRAPPER) - "rsil %0, 15\n\t" /* Turn IRQs back off, let exit wrapper restore PS */ -#endif "movi %0, ~3\n\t" /* prepare a mask for the EPC */ "and %0, %0, %1\n\t" /* apply mask for 32bit aligned base */ "ssa8l %1\n\t" /* set up shift register for src op */ @@ -91,36 +75,6 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, :"r"(ef->epc) : ); - /* - This is a concern area - exception handlers are called with interrupts - turned back on by _xtos_c_wrapper_handler. Is there something about an - exception that would prevent the CPU from servicing an interrupt while in - an exception handler? - - New interrupts are blocked by EXCM being set. Once cleared, interrupts - above the current INTLEVEL and exceptions (w/o creating a DoubleException) - can occur. With USE_ISR_SAFE_EXC_WRAPPER, INTLEVEL is raised to 15 with - EXCM cleared. The original ROM _xtos_c_wrapper_handler: set INTLEVEL to 1 - with EXCM cleared, saved registers, then did an rsil 0, and called the - registerd C Exception handler with interrupts fully enabled! - Our replacement keeps INTLEVEL at 15. This must be done for umm_malloc to - safely work with an IRAM heap from an ISR call. - */ - //C Should we make defined(USE_ISR_SAFE_EXC_WRAPPER) the only build path - if (ef->ps & 0x0F) { -#if !defined(USE_ISR_SAFE_EXC_WRAPPER) - if (0 == mmu_non32xfer_withinisr_count) { - DBG_MMU_PRINTF("\nload/store exception with INTLEVEL 0x%02X\n", ef->ps & 0x0F); - #if 0 - continue; /* fail, not safe for IRQ disabled ?? */ - #endif - } -#endif - //C Do we want to keep this tracking - if (0 == ++mmu_non32xfer_withinisr_count) { - --mmu_non32xfer_withinisr_count; // saturated - } - } uint32_t what = insn & LOAD_MASK; uint32_t valmask = 0; @@ -140,20 +94,6 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, continue; /* fail */ } -#ifdef DEBUG_WARNING - //C Do we want to keep this warning - if (0 == mmu_non32xfer_count) { - // This may be causing some issues TODO retest with umm_malloc within - // interrupt context. - schedule_function(warning); - } -#endif - //C Do we want to keep this tracking - // Some accounting information so we know this is happending. - if (0 == ++mmu_non32xfer_count) { - --mmu_non32xfer_count; // saturated - } - int regno = (insn & 0x0000f0u) >> 4; if (regno == 1) { continue; /* we can't support storing into a1, just die */ @@ -226,7 +166,30 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, panic(); } -#if defined(USE_ISR_SAFE_EXC_WRAPPER) +/* + An issue, the Boot ROM "C" wrapper for exception handlers, + _xtos_c_wrapper_handler, turns interrupts back on. To address this issue we + use our replacement in file `exc-c-wrapper-handler.S`. + + An overview, of an exception at entry: New interrupts are blocked by EXCM + being set. Once cleared, interrupts above the current INTLEVEL and exceptions + (w/o creating a DoubleException) can occur. + + Using our replacement for _xtos_c_wrapper_handler, INTLEVEL is raised to 15 + with EXCM cleared. + + The original Boot ROM `_xtos_c_wrapper_handler` would set INTLEVEL to 1 with + EXCM cleared, saved registers, then do a `rsil 0`, and called the registered + "C" Exception handler with interrupts fully enabled! Our replacement keeps + INTLEVEL at 15. This is needed to support the Arduino model of interrupts + disabled while an ISR runs. + + And we also need it for umm_malloc to work safely with an IRAM heap from an + ISR call. While malloc() will supply DRAM for all allocation from an ISR, + we want free() to safely operate from an ISR to avoid a leak potential. + + This alternative "C" Wrapper is only applied to this exception handler. + */ #define ROM_xtos_c_wrapper_handler (reinterpret_cast<_xtos_handler>(0x40000598)) @@ -247,15 +210,4 @@ void IRAM_ATTR install_non32xfer_exception_handler(void) { } } -#else -void IRAM_ATTR install_non32xfer_exception_handler(void) -{ - if (NULL == old_handler) { - old_handler = - _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, - non32xfer_exception_handler); - } -} -#endif - }; diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 8de64d3571..488e596ccd 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -28,11 +28,6 @@ extern "C" { #define SOC_CACHE_SIZE 1 // 32KB #endif -#ifdef DEV_DEBUG_MMU_IRAM -// Is this set as part of segment data at load time? appears to be -mmu_cre_status_t mmu_status = {SOC_CACHE_SIZE, -1, 0, 0, 0, 0, 0}; -#endif - #if (MMU_ICACHE_SIZE == 0x4000) /* * "Cache_Read_Enable" as in Instruction Read Cache enable, ICACHE. @@ -104,24 +99,12 @@ typedef void (*fp_Cache_Read_Enable_t)(uint8_t map, uint8_t p, uint8_t v); void IRAM_ATTR Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v) { (void)v; -#ifdef DEV_DEBUG_MMU_IRAM - mmu_status.map = map; - mmu_status.p = p; - mmu_status.v = v; - mmu_status.enable_count++; - mmu_status.state = 1; - if (0 == mmu_status.enable_count) { - mmu_status.enable_count--; // keep saturated value - } -#endif - DBG_MMU_PRINT_IRAM_BANK_REG("before", "Enable"); - real_Cache_Read_Enable(map, p, SOC_CACHE_SIZE); - - DBG_MMU_PRINT_IRAM_BANK_REG("after", "Enable"); - DBG_MMU_PRINT_STATUS(); } +#ifdef DEV_DEBUG_PRINT + +#if 0 #ifndef ROM_Cache_Read_Disable #define ROM_Cache_Read_Disable 0x400047f0 #endif @@ -132,22 +115,10 @@ typedef void (*fp_Cache_Read_Disable_t)(void); * */ void IRAM_ATTR Cache_Read_Disable(void) { -#ifdef DEV_DEBUG_MMU_IRAM - mmu_status.disable_count++; - mmu_status.state = 0; - if (0 == mmu_status.disable_count) { - mmu_status.disable_count--; // keep saturated value - } -#endif - DBG_MMU_PRINT_IRAM_BANK_REG("before", "Disable"); - real_Cache_Read_Disable(); - - DBG_MMU_PRINT_IRAM_BANK_REG("after", "Disable"); - DBG_MMU_PRINT_STATUS(); } +#endif -#ifdef DEV_DEBUG_PRINT /* * Early adjustment for CPU crystal frequency, so debug printing will work. * This should not be left enabled all the time in Cashe_Read..., I am concerned diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 56e69424a0..1c3822fca4 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -22,21 +22,6 @@ #include #include -/* - * DEV_DEBUG_MMU_IRAM: - * Debug printing for developing mmu_iram. I don't think it would be usful for - * general debugging. - * - * DEV_DEBUG_PRINT: - * Debug printing macros for printing before before, during, and after - * NONOS SDK initializes. May or maynot be safe during NONOS SDK - * initialization. As in printing from functions called on by the SDK - * during the SDK initialization. - * - #define DEV_DEBUG_MMU_IRAM - #define DEV_DEBUG_PRINT - */ - //C This turns on range checking. Is this the value you want to trigger it? #ifdef DEBUG_ESP_CORE #define DEBUG_ESP_MMU @@ -47,17 +32,21 @@ #endif /* - The more I look at _xtos_c_wrapper_handler the more convinced I am that this - USE_ISR_SAFE_EXC_WRAPPER is required. -*/ -#define USE_ISR_SAFE_EXC_WRAPPER + * DEV_DEBUG_PRINT: + * Debug printing macros for printing before before, during, and after + * NONOS SDK initializes. May or maynot be safe during NONOS SDK + * initialization. As in printing from functions called on by the SDK + * during the SDK initialization. + * + #define DEV_DEBUG_PRINT + */ -#if defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) +#if defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU) #include #define DBG_MMU_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {} -#if defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) +#if defined(DEV_DEBUG_PRINT) extern "C" void set_pll(void); extern "C" void dbg_set_pll(void); @@ -67,56 +56,19 @@ uart_buff_switch(0); \ ets_uart_printf(fmt, ##__VA_ARGS__); \ DBG_MMU_FLUSH(0) -#else -// ! defined(DEBUG_ESP_MMU) +#else // ! defined(DEV_DEBUG_PRINT) #define DBG_MMU_PRINTF(fmt, ...) ets_uart_printf(fmt, ##__VA_ARGS__) #endif -#else // ! defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) +#else // ! defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU) #define DBG_MMU_FLUSH(...) do {} while(false) #define DBG_MMU_PRINTF(...) do {} while(false) -#endif // defined(DEV_DEBUG_PRINT) || defined(DEV_DEBUG_MMU_IRAM) || defined(DEBUG_ESP_MMU) - -#ifdef DEV_DEBUG_MMU_IRAM -#define DBG_MMU_PRINT_STATUS() { \ - DBG_MMU_PRINTF("\nmmu_status = {" \ - "v_cfg = %u, state = %d, enable/disable count = %u/%u, " \ - "map = 0x%02X, p = 0x%02X, v = 0x%02X}\n", \ - mmu_status.v_cfg, mmu_status.state, \ - mmu_status.enable_count, mmu_status.disable_count, \ - mmu_status.map, mmu_status.p, mmu_status.v); \ - DBG_MMU_FLUSH(0); \ -} - -#define DBG_MMU_PRINT_IRAM_BANK_REG(a, b) { \ - uint32_t iram_bank_reg = ESP8266_DREG(0x24); \ - DBG_MMU_PRINTF("\niram_bank_reg %s%s 0x%08X\n", (0 == a) ? "" : a, (0 == a) ? "" : " Cache_Read_" b, iram_bank_reg); \ -} - -#else // ! DEV_DEBUG_MMU_IRAM -#define DBG_MMU_PRINT_STATUS(...) do {} while(false) -#define DBG_MMU_PRINT_IRAM_BANK_REG(...) do {} while(false) -#endif // #if DEV_DEBUG_MMU_IRAM - +#endif // defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU) #ifdef __cplusplus extern "C" { #endif -#ifdef DEV_DEBUG_MMU_IRAM -typedef struct MMU_CRE_STATUS { - uint32_t v_cfg; - int32_t state; // -1 - not initialized, 0 - disabled, 1 - enabled - uint32_t enable_count; - uint32_t disable_count; - uint32_t map; - uint32_t p; - uint32_t v; -} mmu_cre_status_t; - -extern mmu_cre_status_t mmu_status; -#endif - static inline __attribute__((always_inline)) bool mmu_is_iram(const void *addr) { #define IRAM_START 0x40100000UL diff --git a/cores/esp8266/umm_malloc/umm_malloc.cpp b/cores/esp8266/umm_malloc/umm_malloc.cpp index a2c345c562..8c6cd5758a 100644 --- a/cores/esp8266/umm_malloc/umm_malloc.cpp +++ b/cores/esp8266/umm_malloc/umm_malloc.cpp @@ -730,6 +730,60 @@ void *umm_malloc( size_t size ) { UMM_INIT_HEAP; + /* + * "Is it safe" + * + * Is it safe to call from an ISR? Is there a point during a malloc that a + * an interrupt and subsequent call to malloc result in undesired results? + * + * Heap selection in managed by the functions umm_push_heap, umm_pop_heap, + * umm_get_current_heap_id, and umm_set_heap_by_id. These functions are + * responsible for getting/setting the module static variable umm_heap_cur. + * The umm_heap_cur variable is an index that is used to select the current + * heap context. Depending on the situation this selection can be overriddened. + * + * All variables for a specific Heap are in a single structure. `heap_context` + * is an array of these structures. Each heap API function uses a function + * local variable `_context` to hold a pointer to the selected heap structure. + * This local pointer is referenced for all the "selected heap" operations. + * Coupled with critical sections around global data should allow the API + * functions to be reentrant. + * + * Using the `_context` name throughout made it easy to incorporate the + * context into existing macros. + * + * For allocating APIs `umm_heap_cur` is used to index and select a value for + * `_context`. If an allocation is made from an ISR, this value is ignored and + * the heap context for DRAM is loaded. For APIs that require operating on an + * existing allcation such as realloc and free, the heap context selected is + * done by matching the allocation's address with that of one of the heap + * address ranges. + * + * I think we are safe with multiple heaps when the non32-bit exception + * handler is used, as long as interrupts don't get enabled. There was a + * window in the Boot ROM "C" Exception Wrapper that would enable interrupts + * when running our non32-exception handler; however, that should be resolved + * by our replacement wrapper. For more information on exception handling + * issues for IRAM see comments above `_set_exception_handler_wrapper()` in + * `core_esp8266_non32xfer.cpp`. + * + * ISRs should not try and change heaps. umm_malloc will ignore the change. + * All should be fine as long as the caller puts the heap back the way it was. + * On return, everything must be the same. The foreground thread will continue + * with the same information that was there before the interrupt. All malloc() + * requests made from an ISR are fulfilled with DRAM. + * + * For umm_malloc, heap selection involves changing a single variable that is + * on the calling context stack. From the umm_mallac side, that variable is + * used to load a context pointer by index, heap ID. While an umm_malloc API + * function is running, all heap related variables are in the context variable + * pointer, registers, or the current stack as the request is processed. With + * a single variable to reference for heap selection, I think it is unlikely + * that umm_malloc can be called, with things in an unusable transition state. + */ + + umm_heap_context_t *_context = umm_get_current_heap(); + /* * the very first thing we do is figure out if we're being asked to allocate * a size of 0 - and if we are we'll simply return a null pointer. if not @@ -737,8 +791,6 @@ void *umm_malloc( size_t size ) { * the number of blocks to allocate are easier... */ - umm_heap_context_t *_context = umm_get_current_heap(); - if( 0 == size ) { DBGLOG_DEBUG( "malloc a block of 0 bytes -> do nothing\n" ); STATS__ZERO_ALLOC_REQUEST(id_malloc, size); @@ -750,11 +802,19 @@ void *umm_malloc( size_t size ) { UMM_CRITICAL_ENTRY(id_malloc); -#if 1 // !defined(USE_ISR_SAFE_EXC_WRAPPER) + /* + * We handle the realloc of an existing IRAM allocation from an ISR with IRAM, + * while a new malloc from an ISR will always supply DRAM. That said, realloc + * from an ISR is not generally safe without special locking mechanisms and is + * not formally supported. + * + * Additionally, to avoid extending the IRQs disabled period, it is best to + * use DRAM for an ISR. Each 16-bit access to IRAM that umm_malloc has to make + * requires a pass through the exception handling logic. + */ if (UMM_CRITICAL_WITHINISR(id_malloc)) { _context = umm_get_heap_by_id(UMM_HEAP_DRAM); } -#endif ptr = umm_malloc_core( _context, size ); @@ -817,13 +877,6 @@ void *umm_realloc( void *ptr, size_t size ) { STATS__ALLOC_REQUEST(id_realloc, size); -#if !defined(USE_ISR_SAFE_EXC_WRAPPER) - // Require ISR use DRAM for now. - if (ETS_INTR_WITHINISR() && UMM_HEAP_DRAM != _context->id) { - return( (void *)NULL ); - } -#endif - /* * Otherwise we need to actually do a reallocation. A naiive approach * would be to malloc() a new block of the correct size, copy the old data @@ -1080,7 +1133,7 @@ void *umm_realloc( void *ptr, size_t size ) { } else { DBGLOG_DEBUG( "realloc a completely new block %d\n", blocks ); void *oldptr = ptr; - if( (ptr = umm_malloc_core( size )) ) { + if( (ptr = umm_malloc_core( _context, size )) ) { DBGLOG_DEBUG( "realloc %d to a bigger block %d, copy, and free the old\n", blockSize, blocks ); UMM_CRITICAL_SUSPEND(id_realloc); memcpy( ptr, oldptr, curSize ); From d7fb4ab4857090d8532f7a36ede8765c19030d22 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 6 Oct 2020 13:27:35 -0700 Subject: [PATCH 44/48] Updated mmu.rst --- doc/mmu.rst | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/doc/mmu.rst b/doc/mmu.rst index f010a655bc..41446cf76c 100644 --- a/doc/mmu.rst +++ b/doc/mmu.rst @@ -143,28 +143,6 @@ For calls to ``umm_malloc`` with interrupts disabled. access, consider using the inline functions described in section "Performance Functions" below. - I think this block should go away and we always use - ``USE_ISR_SAFE_EXC_WRAPPER`` with the exception handler. - - - ``realloc`` will fail if not built with - ``USE_ISR_SAFE_EXC_WRAPPER`` defined. - - The current build has ``USE_ISR_SAFE_EXC_WRAPPER`` defined in - ``mmu_iram.h``. - - .. rubric:: ISR/Exception Handler Issue - :name: isrexception-handler-issue - - The non-32-bit exception handler is called by a "C" wrapper function - in ROM. This ROM function enables interrupts before calling our - registered handler. Defining ``USE_ISR_SAFE_EXC_WRAPPER`` in - ``mmu_iram.h`` will install a replacement that does not enable - interrupts (now default). The effects on Network performance are - unknown. - - To keep ISR execution time with interrupts disabled at a minimum, - avoid the use of IRAM from ISRs. Especially the use of non-32-bit - read/writes on IRAM. - How to Select Heap ~~~~~~~~~~~~~~~~~~ From d3f9a0ade95911e8aad480f4f571d0514aece734 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Tue, 1 Dec 2020 13:08:29 -0800 Subject: [PATCH 45/48] Expanded and clarified comments. Limited access to some detailed typdefs/prototypes to .cpp modules, to avoid future build conflicts. Completed TODO for verifing that the "C" structure struct __exception_frame matches the ASM version. Fixed some typo's, code rot, and added some more cases in examaple irammem.ino. Refactored a little and reordered printing to ease comparison between methods. Corrected `#ifdef __cplusplus` coverage area. Cleaned up `extern "C" ...` usage. Fixes issues with including mmu_iram.h or esp8266_undocumented.h in .c files. --- cores/esp8266/core_esp8266_non32xfer.cpp | 20 +- cores/esp8266/esp8266_undocumented.h | 237 +++++++++++++----- cores/esp8266/exc-c-wrapper-handler.S | 73 ++++++ cores/esp8266/mmu_iram.h | 22 +- .../esp8266/examples/irammem/irammem.ino | 209 +++++++++------ 5 files changed, 403 insertions(+), 158 deletions(-) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 55dd5d1bbd..47e9f58f6f 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -30,8 +30,9 @@ */ #include -#include +#define VERIFY_C_ASM_EXCEPTION_FRAME_STRUCTURE #include +#include #include #include #include @@ -47,7 +48,7 @@ extern "C" { #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Non 32-bit read/write error */ -static fn_exception_handler_t old_handler = NULL; +static fn_c_exception_handler_t old_c_handler = NULL; static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) { @@ -151,9 +152,9 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, INTLEVEL != 0. I cannot create it any more. I thought I saw this as a problem; however, my test case shows no problem ?? Maybe I was confused. */ - if (old_handler) { // if (0 == (ef->ps & 0x0F)) { - DBG_MMU_PRINTF("\ncalling previous load/store handler(%p)\n", old_handler); - old_handler(ef, cause); + if (old_c_handler) { // if (0 == (ef->ps & 0x0F)) { + DBG_MMU_PRINTF("\ncalling previous load/store handler(%p)\n", old_c_handler); + old_c_handler(ef, cause); return; } @@ -188,7 +189,7 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, ISR call. While malloc() will supply DRAM for all allocation from an ISR, we want free() to safely operate from an ISR to avoid a leak potential. - This alternative "C" Wrapper is only applied to this exception handler. + This replacement "C" Wrapper is only applied to this exception handler. */ #define ROM_xtos_c_wrapper_handler (reinterpret_cast<_xtos_handler>(0x40000598)) @@ -201,11 +202,14 @@ static void IRAM_ATTR _set_exception_handler_wrapper(uint32_t cause) { } void IRAM_ATTR install_non32xfer_exception_handler(void) { - if (NULL == old_handler) { - old_handler = + if (NULL == old_c_handler) { + // Set the "C" exception handler the wrapper will call + old_c_handler = _xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, non32xfer_exception_handler); + // Set the replacement ASM based exception "C" wrapper function which will + // be calling `non32xfer_exception_handler`. _set_exception_handler_wrapper(EXCCAUSE_LOAD_STORE_ERROR); } } diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index f568f15427..fd40b8ac87 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -1,12 +1,17 @@ // ROM and blob calls without official headers available -#ifndef __ESP8266_UNDOCUMENTED_H +#if !defined(__ESP8266_UNDOCUMENTED_H) && !(defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)) #define __ESP8266_UNDOCUMENTED_H #ifdef __cplusplus extern "C" { #endif +#ifndef XCHAL_EXCCAUSE_NUM +// from tools/xtensa-lx106-elf/include/xtensa/config/core.h:629:#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_NUM 64 +#endif + // ROM extern void rom_i2c_writeReg_Mask(int, int, int, int, int, int); @@ -40,12 +45,15 @@ extern void ets_delay_us(uint32_t us); #ifndef GDBSTUB_H /* GDBSTUB duplicates these with some variances that are not compatible with our - references (offsets), which are synced with those used by the BootROM. In - particular, the BootROM does not have register "a1" in the structure where + references (offsets), which are synced with those used by the BootROM. + Specifically, the BootROM does not have register "a1" in the structure where GDBSTUB does. */ -/* The Xtensa OS code in ROM for handling hardware exceptions */ +/* + This structure is used in the argument list of "C" callable exception handlers. + See `_xtos_set_exception_handler` details below. +*/ struct __exception_frame { uint32_t epc; @@ -75,35 +83,7 @@ struct __exception_frame }; uint32_t cause; }; -/*? - TODO: A set of static_asserts to confim we are matching these. - - Extracted from information at - From https://github.com/fdivitto/ESPWebFramework/blob/master/SDK/xtensa-lx106-elf/xtensa-lx106-elf/lib/libhandlers-null.txt - -#define UEXC_pc 0x0000 -#define UEXC_ps 0x0004 -#define UEXC_sar 0x0008 -#define UEXC_vpri 0x000c -#define UEXC_a0 0x0010 -#define UEXC_a2 0x0014 -#define UEXC_a3 0x0018 -#define UEXC_a4 0x001c -#define UEXC_a5 0x0020 -#define UEXC_a6 0x0024 -#define UEXC_a7 0x0028 -#define UEXC_a8 0x002c -#define UEXC_a9 0x0030 -#define UEXC_a10 0x0034 -#define UEXC_a11 0x0038 -#define UEXC_a12 0x003c -#define UEXC_a13 0x0040 -#define UEXC_a14 0x0044 -#define UEXC_a15 0x0048 -#define UEXC_exccause 0x004c -#define UserFrameSize 0x0050 -#define UserFrameTotalSize 0x0100 -*/ +#endif /* Most of the comments here are gleamed from the xtensa files found at the site @@ -114,65 +94,186 @@ struct __exception_frame */ /* - ROM Function, _xtos_set_exception_handler(), installs a "C" callable exception handler. - * If reason is out of range, >=64, it returns NULL. - * If the new exception handler is installed, it returns the previous handler. - * If the previous handler was _xtos_unhandled_exception/_xtos_p_none, it - returns NULL. + The Boot ROM sets up a table of dispatch handlers at 0x3FFFC000. This table + has an entry for each of the EXCCAUSE values, 0 through 63. The exception + handler at the `User Exception Vector` uses EXCCAUSE with the base address + 0x3FFFC000 to build a jump address to the respective cause handler. Of the + cause handle functions, `_xtos_c_wrapper_handler` and `_xtos_unhandled_exception` + are of interest. - Note, the installed "C" exception handler is called from the - _xtos_c_wrapper_handler with IRQs enabled. - */ -typedef void (*fn_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); -fn_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_exception_handler_t fn); + Exception handler entries that do not have a specific handler are set to + `_xtos_unhandled_exception`. This handler will execute a `break 1, 1` + (0x4000DC4Bu) before doing a `rfe` (return from exception). Since the PC has + not changed, the event that caused the 1st exception will likely keep + repeating until the HWDT kicks in. + These exception handling functions are in assembly, and do not conform to the + typical "C" function conventions. However, some form of prototype/typedef is + needed to reference these function addresses in "C" code. In + `RTOS_SDK/components/esp8266/include/xtensa/xtruntime.h`, it uses a compounded + definition that equates to `void (*)(...)` for .cpp modules to use. I have + noticed this creates sufficient confusion at compilation to get your attention + when used in the wrong place. I have copied that definition here. + + Added to eagle.rom.addr.v6.ld: + PROVIDE ( _xtos_exc_handler_table = 0x3fffc000 ); + PROVIDE ( _xtos_c_handler_table = 0x3fffc100 ); +*/ +#ifndef XTRUNTIME_H +// This is copy/paste from RTOS_SDK/components/esp8266/include/xtensa/xtruntime.h +#ifdef __cplusplus +typedef void (_xtos_handler_func)(...); +#else +typedef void (_xtos_handler_func)(); #endif +typedef _xtos_handler_func *_xtos_handler; + +extern _xtos_handler _xtos_exc_handler_table[XCHAL_EXCCAUSE_NUM]; /* - Added to eagle.rom.addr.v6.ld - PROVIDE ( _xtos_exc_handler_table = 0x3fffc000 ); - PROVIDE ( _xtos_c_handler_table = 0x3fffc100 ); + Assembly-level handler, used in the _xtos_exc_handler_table[]. It is a wrapper + for calling registered "C" exception handlers. */ +_xtos_handler_func _xtos_c_wrapper_handler; + +/* + Assembly-level handler, used in the _xtos_exc_handler_table[]. It is the + default handler, for exceptions without a registered handler. +*/ +_xtos_handler_func _xtos_unhandled_exception; +#endif + + #ifdef __cplusplus -typedef void (_xtos_handler_func)(...); +// These definitions that try to be more precise for .cpp module usage. /* - Assembly-level handler, used in the _xtos_exc_handler_table[], a wrapper for - calling registered "C" exception handlers. + A detailed typdef for the "C" callable functions found in + `_xtos_c_handler_table[]` More details in `_xtos_set_exception_handler` + comments below. */ -void _xtos_c_wrapper_handler(...); +typedef void (*fn_c_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); /* - Assembly-level handler, used in the _xtos_exc_handler_table[], for exceptions - without a registered handler. + TMI maybe? However, it may be useful for a deep debugging session. + `_xtos_p_none` is the default "C" exception handler that fills the + _xtos_c_handler_table[]. It is present when an exception handler has not been + registered. It simply consist of a single instruction, `ret`. + It is also internally used by `_xtos_set_exception_handler(cause, NULL)` to + reset a "C" exception handler back to the unhandled state. The coresponding + `_xtos_exc_handler_table` entry will be set to `_xtos_unhandled_exception`. + Note, if nesting handlers is desired this must be implemented in the new "C" + exception handler(s) being registered. */ -void _xtos_unhandled_exception(...); +extern void _xtos_p_none(struct __exception_frame *ef, uint32_t cause); /* - The default/empty "C" exception handler, used in the _xtos_c_handler_table[], - when an exception handler has not been registered. - Supply this to _xtos_set_exception_handler() to reset an exception handler - back to the unhandled state, _xtos_unhandled_exception. - Note, if you have nesting handlers this is much more complicated than this. + TMI maybe? + For `extern _xtos_handler _xtos_c_handler_table[XCHAL_EXCCAUSE_NUM];`, defined + in in `xtensa/xtos/exc-sethandler.c`. _xtos_handler is a generalized + definition that doesn't match the actual function definition of those + assigned to `_xtos_c_handler_table` entries. + + At this time we do not require direct access to this table. We perform updates + by calling the ROM function `_xtos_set_exception_handler`. + + A corrected version for .cpp would look like this: */ -void _xtos_p_none(void); +extern fn_c_exception_handler_t _xtos_c_handler_table[XCHAL_EXCCAUSE_NUM]; -#else -typedef void (_xtos_handler_func)(); -void _xtos_c_wrapper_handler(); -void _xtos_unhandled_exception(); -void _xtos_p_none(); +/* + ROM API function `_xtos_set_exception_handler` registers a "C" callable + exception handler for a specified general exception, (EXCCAUSE value). (source + in xtensa/xtos/exc-sethandler.c) + * If `reason` (EXCCAUSE) is out of range, >=64, it returns NULL. + * If the new exception handler is installed, it returns the previous handler. + * If the previous handler was `_xtos_unhandled_exception`/`_xtos_p_none`, it + returns NULL. -#endif + Note, the installed "C" exception handler is noramlly called from the ROM + function _xtos_c_wrapper_handler with IRQs enabled. This build now includes a + replacement wrapper that is used with the "C" exception handler for + EXCCAUSE_LOAD_STORE_ERROR (3), Non 32-bit read/write error. -typedef _xtos_handler_func *_xtos_handler; + This prototype has been corrected (changed from a generalized to specific + argument list) for the .cpp files in this projects; however, it does not match + the over generalized version in some Xtensa .h files (not currently part of + this project) -extern _xtos_handler _xtos_exc_handler_table[]; -extern _xtos_handler _xtos_c_handler_table[]; + To aid against future conflicts, keep these new defines limited to .cpp with + `#ifdef __cplusplus`. +*/ +extern fn_c_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_c_exception_handler_t fn); +#endif #ifdef __cplusplus }; #endif +#endif + +#if defined(VERIFY_C_ASM_EXCEPTION_FRAME_STRUCTURE) || defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +/* + Extracted from information at + From https://github.com/fdivitto/ESPWebFramework/blob/master/SDK/xtensa-lx106-elf/xtensa-lx106-elf/lib/libhandlers-null.txt + The UEXC_... values are create by the macro STRUCT_FIELD in `xtruntime-frames.h` + + These VERIFY_... values are used to confirm that the "C" structure offsets + match those generated in exc-c-wrapper-handler.S. +*/ +#define VERIFY_UEXC_pc 0x0000 +#define VERIFY_UEXC_ps 0x0004 +#define VERIFY_UEXC_sar 0x0008 +#define VERIFY_UEXC_vpri 0x000c +#define VERIFY_UEXC_a0 0x0010 +#define VERIFY_UEXC_a2 0x0014 +#define VERIFY_UEXC_a3 0x0018 +#define VERIFY_UEXC_a4 0x001c +#define VERIFY_UEXC_a5 0x0020 +#define VERIFY_UEXC_a6 0x0024 +#define VERIFY_UEXC_a7 0x0028 +#define VERIFY_UEXC_a8 0x002c +#define VERIFY_UEXC_a9 0x0030 +#define VERIFY_UEXC_a10 0x0034 +#define VERIFY_UEXC_a11 0x0038 +#define VERIFY_UEXC_a12 0x003c +#define VERIFY_UEXC_a13 0x0040 +#define VERIFY_UEXC_a14 0x0044 +#define VERIFY_UEXC_a15 0x0048 +#define VERIFY_UEXC_exccause 0x004c +#define VERIFY_UserFrameSize 0x0050 +#define VERIFY_UserFrameTotalSize 0x0100 +#endif + +#if defined(VERIFY_C_ASM_EXCEPTION_FRAME_STRUCTURE) && !(defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)) +/* + A set of static_asserts test to confirm both "C" and ASM structures match. + + This only needs to be verified once. + We use `#define VERIFY_C_ASM_EXCEPTION_FRAME_STRUCTURE` to limit number of + times tested in a build. Testing is done from core_esp8266_non32xfer.cpp. + + ASM structure defines are verified in exc-c-wrapper-handler.S +*/ +static_assert(offsetof(struct __exception_frame, epc) == VERIFY_UEXC_pc, "offsetof(struct __exception_frame, epc) != VERIFY_UEXC_pc, expected 0x0000"); +static_assert(offsetof(struct __exception_frame, ps) == VERIFY_UEXC_ps, "offsetof(struct __exception_frame, ps) != VERIFY_UEXC_ps, expected 0x0004"); +static_assert(offsetof(struct __exception_frame, sar) == VERIFY_UEXC_sar, "offsetof(struct __exception_frame, sar) != VERIFY_UEXC_sar, expected 0x0008"); +static_assert(offsetof(struct __exception_frame, unused) == VERIFY_UEXC_vpri, "offsetof(struct __exception_frame, unused) != VERIFY_UEXC_vpri, expected 0x000c"); +static_assert(offsetof(struct __exception_frame, a0) == VERIFY_UEXC_a0, "offsetof(struct __exception_frame, a0) != VERIFY_UEXC_a0, expected 0x0010"); +static_assert(offsetof(struct __exception_frame, a2) == VERIFY_UEXC_a2, "offsetof(struct __exception_frame, a2) != VERIFY_UEXC_a2, expected 0x0014"); +static_assert(offsetof(struct __exception_frame, a3) == VERIFY_UEXC_a3, "offsetof(struct __exception_frame, a3) != VERIFY_UEXC_a3, expected 0x0018"); +static_assert(offsetof(struct __exception_frame, a4) == VERIFY_UEXC_a4, "offsetof(struct __exception_frame, a4) != VERIFY_UEXC_a4, expected 0x001c"); +static_assert(offsetof(struct __exception_frame, a5) == VERIFY_UEXC_a5, "offsetof(struct __exception_frame, a5) != VERIFY_UEXC_a5, expected 0x0020"); +static_assert(offsetof(struct __exception_frame, a6) == VERIFY_UEXC_a6, "offsetof(struct __exception_frame, a6) != VERIFY_UEXC_a6, expected 0x0024"); +static_assert(offsetof(struct __exception_frame, a7) == VERIFY_UEXC_a7, "offsetof(struct __exception_frame, a7) != VERIFY_UEXC_a7, expected 0x0028"); +static_assert(offsetof(struct __exception_frame, a8) == VERIFY_UEXC_a8, "offsetof(struct __exception_frame, a8) != VERIFY_UEXC_a8, expected 0x002c"); +static_assert(offsetof(struct __exception_frame, a9) == VERIFY_UEXC_a9, "offsetof(struct __exception_frame, a9) != VERIFY_UEXC_a9, expected 0x0030"); +static_assert(offsetof(struct __exception_frame, a10) == VERIFY_UEXC_a10, "offsetof(struct __exception_frame, a10) != VERIFY_UEXC_a10, expected 0x0034"); +static_assert(offsetof(struct __exception_frame, a11) == VERIFY_UEXC_a11, "offsetof(struct __exception_frame, a11) != VERIFY_UEXC_a11, expected 0x0038"); +static_assert(offsetof(struct __exception_frame, a12) == VERIFY_UEXC_a12, "offsetof(struct __exception_frame, a12) != VERIFY_UEXC_a12, expected 0x003c"); +static_assert(offsetof(struct __exception_frame, a13) == VERIFY_UEXC_a13, "offsetof(struct __exception_frame, a13) != VERIFY_UEXC_a13, expected 0x0040"); +static_assert(offsetof(struct __exception_frame, a14) == VERIFY_UEXC_a14, "offsetof(struct __exception_frame, a14) != VERIFY_UEXC_a14, expected 0x0044"); +static_assert(offsetof(struct __exception_frame, a15) == VERIFY_UEXC_a15, "offsetof(struct __exception_frame, a15) != VERIFY_UEXC_a15, expected 0x0048"); +static_assert(offsetof(struct __exception_frame, cause) == VERIFY_UEXC_exccause, "offsetof(struct __exception_frame, cause) != VERIFY_UEXC_exccause, expected 0x004c"); #endif diff --git a/cores/esp8266/exc-c-wrapper-handler.S b/cores/esp8266/exc-c-wrapper-handler.S index 1e63211ece..f1ec1c391e 100644 --- a/cores/esp8266/exc-c-wrapper-handler.S +++ b/cores/esp8266/exc-c-wrapper-handler.S @@ -34,6 +34,79 @@ // #endif #include "xtruntime-frames.h" +///////////////////////////////////////////////////////////////////////////// +// +// Verified that the ASM generated UEXC_xxx values match, the corresponding +// values in `struct __exception_frame` used in the "C" code. +// +#include "esp8266_undocumented.h" +.if (UEXC_pc != VERIFY_UEXC_pc) +.err +.endif +.if (UEXC_ps != VERIFY_UEXC_ps) +.err +.endif +.if (UEXC_sar != VERIFY_UEXC_sar) +.err +.endif +.if (UEXC_vpri != VERIFY_UEXC_vpri) +.err +.endif +.if (UEXC_a0 != VERIFY_UEXC_a0) +.err +.endif +.if (UEXC_a2 != VERIFY_UEXC_a2) +.err +.endif +.if (UEXC_a3 != VERIFY_UEXC_a3) +.err +.endif +.if (UEXC_a4 != VERIFY_UEXC_a4) +.err +.endif +.if (UEXC_a5 != VERIFY_UEXC_a5) +.err +.endif +.if (UEXC_a6 != VERIFY_UEXC_a6) +.err +.endif +.if (UEXC_a7 != VERIFY_UEXC_a7) +.err +.endif +.if (UEXC_a8 != VERIFY_UEXC_a8) +.err +.endif +.if (UEXC_a9 != VERIFY_UEXC_a9) +.err +.endif +.if (UEXC_a10 != VERIFY_UEXC_a10) +.err +.endif +.if (UEXC_a11 != VERIFY_UEXC_a11) +.err +.endif +.if (UEXC_a12 != VERIFY_UEXC_a12) +.err +.endif +.if (UEXC_a13 != VERIFY_UEXC_a13) +.err +.endif +.if (UEXC_a14 != VERIFY_UEXC_a14) +.err +.endif +.if (UEXC_a15 != VERIFY_UEXC_a15) +.err +.endif +.if (UEXC_exccause != VERIFY_UEXC_exccause) +.err +.endif +.if (UserFrameSize != VERIFY_UserFrameSize) +.err +.endif +.if (UserFrameTotalSize != VERIFY_UserFrameTotalSize) +.err +.endif +/////////////////////////////////////////////////////////////////////////////// /* * This is the general exception assembly-level handler that dispatches C handlers. diff --git a/cores/esp8266/mmu_iram.h b/cores/esp8266/mmu_iram.h index 1c3822fca4..e372fa1047 100644 --- a/cores/esp8266/mmu_iram.h +++ b/cores/esp8266/mmu_iram.h @@ -22,6 +22,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + //C This turns on range checking. Is this the value you want to trigger it? #ifdef DEBUG_ESP_CORE #define DEBUG_ESP_MMU @@ -47,8 +51,8 @@ #define DBG_MMU_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {} #if defined(DEV_DEBUG_PRINT) -extern "C" void set_pll(void); -extern "C" void dbg_set_pll(void); +extern void set_pll(void); +extern void dbg_set_pll(void); #define DBG_MMU_PRINTF(fmt, ...) \ set_pll(); \ @@ -65,10 +69,6 @@ DBG_MMU_FLUSH(0) #define DBG_MMU_PRINTF(...) do {} while(false) #endif // defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU) -#ifdef __cplusplus -extern "C" { -#endif - static inline __attribute__((always_inline)) bool mmu_is_iram(const void *addr) { #define IRAM_START 0x40100000UL @@ -197,12 +197,8 @@ int16_t mmu_set_int16(int16_t *p16, const int16_t val) { return val; } -#ifdef __cplusplus -} -#endif - #if (MMU_IRAM_SIZE > 32*1024) && !defined(MMU_SEC_HEAP) -extern "C" void _text_end(void); +extern void _text_end(void); #define MMU_SEC_HEAP mmu_sec_heap() #define MMU_SEC_HEAP_SIZE mmu_sec_heap_size() @@ -218,4 +214,8 @@ size_t mmu_sec_heap_size(void) { } #endif +#ifdef __cplusplus +} +#endif + #endif diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 1aed45c704..2b7d6cb8c3 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -14,61 +14,60 @@ #define ETS_PRINTF ets_uart_printf #endif -uint32_t cyclesToRead1Kx32(unsigned int *x, uint32_t *res) { +uint32_t cyclesToRead_nKx32(int n, unsigned int *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += *(x++); } *res = sum; return ESP.getCycleCount() - b; } -uint32_t cyclesToWrite1Kx32(unsigned int *x) { +uint32_t cyclesToWrite_nKx32(int n, unsigned int *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += i; *(x++) = sum; } return ESP.getCycleCount() - b; } - -uint32_t cyclesToRead1Kx16(unsigned short *x, uint32_t *res) { +uint32_t cyclesToRead_nKx16(int n, unsigned short *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += *(x++); } *res = sum; return ESP.getCycleCount() - b; } -uint32_t cyclesToWrite1Kx16(unsigned short *x) { +uint32_t cyclesToWrite_nKx16(int n, unsigned short *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += i; *(x++) = sum; } return ESP.getCycleCount() - b; } -uint32_t cyclesToRead1Kx8(unsigned char*x, uint32_t *res) { +uint32_t cyclesToRead_nKx8(int n, unsigned char*x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += *(x++); } *res = sum; return ESP.getCycleCount() - b; } -uint32_t cyclesToWrite1Kx8(unsigned char*x) { +uint32_t cyclesToWrite_nKx8(int n, unsigned char*x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += i; *(x++) = sum; } @@ -77,20 +76,20 @@ uint32_t cyclesToWrite1Kx8(unsigned char*x) { // Compare with Inline -uint32_t cyclesToRead1Kx16_viaInline(unsigned short *x, uint32_t *res) { +uint32_t cyclesToRead_nKx16_viaInline(int n, unsigned short *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += mmu_get_uint16(x++); //*(x++); } *res = sum; return ESP.getCycleCount() - b; } -uint32_t cyclesToWrite1Kx16_viaInline(unsigned short *x) { +uint32_t cyclesToWrite_nKx16_viaInline(int n, unsigned short *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += i; // *(x++) = sum; mmu_set_uint16(x++, sum); @@ -98,20 +97,20 @@ uint32_t cyclesToWrite1Kx16_viaInline(unsigned short *x) { return ESP.getCycleCount() - b; } -uint32_t cyclesToRead1Kx8_viaInline(unsigned char*x, uint32_t *res) { +uint32_t cyclesToRead_nKx8_viaInline(int n, unsigned char*x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += mmu_get_uint8(x++); //*(x++); } *res = sum; return ESP.getCycleCount() - b; } -uint32_t cyclesToWrite1Kx8_viaInline(unsigned char*x) { +uint32_t cyclesToWrite_nKx8_viaInline(int n, unsigned char*x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < 1024; i++) { + for (int i = 0; i < n*1024; i++) { sum += i; // *(x++) = sum; mmu_set_uint8(x++, sum); @@ -119,6 +118,41 @@ uint32_t cyclesToWrite1Kx8_viaInline(unsigned char*x) { return ESP.getCycleCount() - b; } +void perfTest_nK(int nK, uint32_t *mem, uint32_t *imem) { + uint32_t res; + uint32_t t; + + t = cyclesToWrite_nKx16(nK, (uint16_t*)imem); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx16(nK, (uint16_t*)imem, &res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx16_viaInline(nK, (uint16_t*)imem); + Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx16_viaInline(nK, (uint16_t*)imem, &res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx16(nK, (uint16_t*)mem); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx16(nK, (uint16_t*)mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx8(nK, (uint8_t*)imem); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx8(nK, (uint8_t*)imem, &res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx8_viaInline(nK, (uint8_t*)imem); + Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx8_viaInline(nK, (uint8_t*)imem, &res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx8(nK, (uint8_t*)mem); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx8(nK, (uint8_t*)mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); +} + void setup() { WiFi.persistent(false); WiFi.mode(WIFI_OFF); @@ -138,14 +172,17 @@ void setup() { // IRAM region. It will continue to use the builtin DRAM until we request // otherwise. Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); - uint32_t *mem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + uint32_t *mem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); Serial.printf("DRAM buffer: Address %p, free %d\n", mem, ESP.getFreeHeap()); + if (!mem) { + return; + } // Now request from the IRAM heap #ifdef USE_SET_IRAM_HEAP ESP.setIramHeap(); Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); - uint32_t *imem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + uint32_t *imem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); // Make sure we go back to the DRAM heap for other allocations. Don't forget to ESP.resetHeap()! ESP.resetHeap(); @@ -159,49 +196,32 @@ void setup() { // ... // umm_set_heap_by_id(_heap_id); Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); - imem = (uint32_t *)malloc(1024 * sizeof(uint32_t)); + imem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); } #endif + if (!imem) { + return; + } + uint32_t res; uint32_t t; - t = cyclesToWrite1Kx32(imem); - Serial.printf("IRAM Memory Write: %6d cycles for 4K\n", t); - t = cyclesToWrite1Kx32(mem); - Serial.printf("DRAM Memory Write: %6d cycles for 4K\n", t); - - t = cyclesToRead1Kx32(imem, &res); - Serial.printf_P(PSTR("IRAM Memory Read: %6d cycles for 4K (sum %08x)\n"), t, res); - t = cyclesToRead1Kx32(mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for 4K (sum %08x)\n", t, res); - - t = cyclesToWrite1Kx16((uint16_t*)imem); - Serial.printf("IRAM Memory Write: %6d cycles for 2K by 16\n", t); - t = cyclesToWrite1Kx16_viaInline((uint16_t*)imem); - Serial.printf("IRAM Memory Write Inline: %6d cycles for 2K by 16\n", t); - t = cyclesToWrite1Kx16((uint16_t*)mem); - Serial.printf("DRAM Memory Write: %6d cycles for 2K by 16\n", t); - - t = cyclesToRead1Kx16((uint16_t*)imem, &res); - Serial.printf("IRAM Memory Read: %6d cycles for 2K by 16 (sum %08x)\n", t, res); - t = cyclesToRead1Kx16_viaInline((uint16_t*)imem, &res); - Serial.printf("IRAM Memory Read Inline: %6d cycles for 2K by 16 (sum %08x)\n", t, res); - t = cyclesToRead1Kx16((uint16_t*)mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for 2K by 16 (sum %08x)\n", t, res); - - t = cyclesToWrite1Kx8((uint8_t*)imem); - Serial.printf("IRAM Memory Write: %6d cycles for 1K by 8\n", t); - t = cyclesToWrite1Kx8_viaInline((uint8_t*)imem); - Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 8\n", t); - t = cyclesToWrite1Kx8((uint8_t*)mem); - Serial.printf("DRAM Memory Write: %6d cycles for 1K by 8\n", t); - - t = cyclesToRead1Kx8((uint8_t*)imem, &res); - Serial.printf("IRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); - t = cyclesToRead1Kx8_viaInline((uint8_t*)imem, &res); - Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 8 (sum %08x)\n", t, res); - t = cyclesToRead1Kx8((uint8_t*)mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + int nK = 1; + Serial.println(); + t = cyclesToWrite_nKx32(nK, imem); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx32(nK, imem, &res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + + t = cyclesToWrite_nKx32(nK, mem); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + t = cyclesToRead_nKx32(nK, mem, &res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.println(); + perfTest_nK(1, mem, imem); + Serial.println(); + perfTest_nK(4, mem, imem); + Serial.println(); #ifdef USE_SET_IRAM_HEAP // Let's use IRAM heap to make a big ole' String @@ -243,10 +263,12 @@ void setup() { } #endif - // Note that free/realloc will all use the heap specified when the pointer was created. + // Note that free/realloc will use the heap specified when the pointer was created. // No need to change heaps to delete an object, only to create it. free(imem); free(mem); + imem = NULL; + mem = NULL; Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); #ifdef USE_SET_IRAM_HEAP @@ -270,17 +292,17 @@ void setup() { ESP.getHeapStats(&hfree, &hmax, &hfrag); ets_uart_printf("ESP.getHeapStats(free: %u, max: %u, frag: %u)\n", hfree, hmax, hfrag); + if (free_iram > UMM_OVERHEAD_ADJUST) { + void *all = malloc(free_iram - UMM_OVERHEAD_ADJUST); + ets_uart_printf("%p = malloc(%u)\n", all, free_iram); + umm_info(NULL, true); - void *all = malloc(free_iram); - ets_uart_printf("%p = malloc(%u)\n", all, free_iram); - umm_info(NULL, true); - - free_iram = ESP.getFreeHeap(); - ets_uart_printf("IRAM free: %6d\n", free_iram); - - free(all); - ets_uart_printf("IRAM free: %6d\n", ESP.getFreeHeap()); + free_iram = ESP.getFreeHeap(); + ets_uart_printf("IRAM free: %6d\n", free_iram); + free(all); + ets_uart_printf("IRAM free: %6d\n", ESP.getFreeHeap()); + } } } @@ -340,3 +362,48 @@ void loop(void) { processKey(Serial, hotKey); } } + + + // t = cyclesToWrite_nKx8(4, (uint8_t*)imem); + // Serial.printf("IRAM Memory Write: %6d cycles for 4K by 8\n", t); + // t = cyclesToWrite_nKx8_viaInline(4, (uint8_t*)imem); + // Serial.printf("IRAM Memory Write Inline: %6d cycles for 4K by 8\n", t); + // t = cyclesToWrite_nKx8(4, (uint8_t*)mem); + // Serial.printf("DRAM Memory Write: %6d cycles for 4K by 8\n", t); + // + // t = cyclesToRead_nKx8(4, (uint8_t*)imem, &res); + // Serial.printf("IRAM Memory Read: %6d cycles for 4K by 8 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx8_viaInline(4, (uint8_t*)imem, &res); + // Serial.printf("IRAM Memory Read Inline: %6d cycles for 4K by 8 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx8(4, (uint8_t*)mem, &res); + // Serial.printf("DRAM Memory Read: %6d cycles for 4K by 8 (sum %08x)\n", t, res); + // + // + // nK = 1; + // t = cyclesToWrite_nKx16(nK, (uint16_t*)imem); + // Serial.printf("IRAM Memory Write: %6d cycles for 1K by 16\n", t); + // t = cyclesToWrite_nKx16_viaInline(nK, (uint16_t*)imem); + // Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 16\n", t); + // t = cyclesToWrite_nKx16(nK, (uint16_t*)mem); + // Serial.printf("DRAM Memory Write: %6d cycles for 1K by 16\n", t); + // + // t = cyclesToRead_nKx16(nK, (uint16_t*)imem, &res); + // Serial.printf("IRAM Memory Read: %6d cycles for 1K by 16 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx16_viaInline(nK, (uint16_t*)imem, &res); + // Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 16 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx16(nK, (uint16_t*)mem, &res); + // Serial.printf("DRAM Memory Read: %6d cycles for 1K by 16 (sum %08x)\n", t, res); + // + // t = cyclesToWrite_nKx8(nK, (uint8_t*)imem); + // Serial.printf("IRAM Memory Write: %6d cycles for 1K by 8\n", t); + // t = cyclesToWrite_nKx8_viaInline(nK, (uint8_t*)imem); + // Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 8\n", t); + // t = cyclesToWrite_nKx8((uint8_t*)mem); + // Serial.printf("DRAM Memory Write: %6d cycles for 1K by 8\n", t); + // + // t = cyclesToRead_nKx8(nK, (uint8_t*)imem, &res); + // Serial.printf("IRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx8_viaInline(nK, (uint8_t*)imem, &res); + // Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 8 (sum %08x)\n", t, res); + // t = cyclesToRead_nKx8(nK, (uint8_t*)mem, &res); + // Serial.printf("DRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); From e48d95e022c86ec4f4f1ed7cbe621be2fb4ae1b5 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 2 Dec 2020 13:16:40 -0800 Subject: [PATCH 46/48] Style fixes and more cleanup --- .../esp8266/examples/irammem/irammem.ino | 147 ++++++------------ 1 file changed, 51 insertions(+), 96 deletions(-) diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 2b7d6cb8c3..8f16bc48ae 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -17,7 +17,7 @@ uint32_t cyclesToRead_nKx32(int n, unsigned int *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += *(x++); } *res = sum; @@ -27,7 +27,7 @@ uint32_t cyclesToRead_nKx32(int n, unsigned int *x, uint32_t *res) { uint32_t cyclesToWrite_nKx32(int n, unsigned int *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += i; *(x++) = sum; } @@ -37,7 +37,7 @@ uint32_t cyclesToWrite_nKx32(int n, unsigned int *x) { uint32_t cyclesToRead_nKx16(int n, unsigned short *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += *(x++); } *res = sum; @@ -47,7 +47,7 @@ uint32_t cyclesToRead_nKx16(int n, unsigned short *x, uint32_t *res) { uint32_t cyclesToWrite_nKx16(int n, unsigned short *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += i; *(x++) = sum; } @@ -57,7 +57,7 @@ uint32_t cyclesToWrite_nKx16(int n, unsigned short *x) { uint32_t cyclesToRead_nKx8(int n, unsigned char*x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += *(x++); } *res = sum; @@ -67,7 +67,7 @@ uint32_t cyclesToRead_nKx8(int n, unsigned char*x, uint32_t *res) { uint32_t cyclesToWrite_nKx8(int n, unsigned char*x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += i; *(x++) = sum; } @@ -79,7 +79,7 @@ uint32_t cyclesToWrite_nKx8(int n, unsigned char*x) { uint32_t cyclesToRead_nKx16_viaInline(int n, unsigned short *x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += mmu_get_uint16(x++); //*(x++); } *res = sum; @@ -89,7 +89,7 @@ uint32_t cyclesToRead_nKx16_viaInline(int n, unsigned short *x, uint32_t *res) { uint32_t cyclesToWrite_nKx16_viaInline(int n, unsigned short *x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += i; // *(x++) = sum; mmu_set_uint16(x++, sum); @@ -100,7 +100,7 @@ uint32_t cyclesToWrite_nKx16_viaInline(int n, unsigned short *x) { uint32_t cyclesToRead_nKx8_viaInline(int n, unsigned char*x, uint32_t *res) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += mmu_get_uint8(x++); //*(x++); } *res = sum; @@ -110,7 +110,7 @@ uint32_t cyclesToRead_nKx8_viaInline(int n, unsigned char*x, uint32_t *res) { uint32_t cyclesToWrite_nKx8_viaInline(int n, unsigned char*x) { uint32_t b = ESP.getCycleCount(); uint32_t sum = 0; - for (int i = 0; i < n*1024; i++) { + for (int i = 0; i < n * 1024; i++) { sum += i; // *(x++) = sum; mmu_set_uint8(x++, sum); @@ -123,34 +123,34 @@ void perfTest_nK(int nK, uint32_t *mem, uint32_t *imem) { uint32_t t; t = cyclesToWrite_nKx16(nK, (uint16_t*)imem); - Serial.printf("IRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx16(nK, (uint16_t*)imem, &res); - Serial.printf("IRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx16_viaInline(nK, (uint16_t*)imem); - Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx16_viaInline(nK, (uint16_t*)imem, &res); - Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx16(nK, (uint16_t*)mem); - Serial.printf("DRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 16, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx16(nK, (uint16_t*)mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 16, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx8(nK, (uint8_t*)imem); - Serial.printf("IRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx8(nK, (uint8_t*)imem, &res); - Serial.printf("IRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx8_viaInline(nK, (uint8_t*)imem); - Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("IRAM Memory Write Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx8_viaInline(nK, (uint8_t*)imem, &res); - Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("IRAM Memory Read Inline: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx8(nK, (uint8_t*)mem); - Serial.printf("DRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 8, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx8(nK, (uint8_t*)mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 8, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); } void setup() { @@ -159,7 +159,7 @@ void setup() { // Serial.begin(74880); Serial.begin(115200); delay(20); - Serial.printf_P(PSTR("\n\nSetup ...\n")); + Serial.printf_P(PSTR("\n\nSetup ...\r\n")); #ifndef UMM_HEAP_IRAM Serial.printf("\r\n" "This example needs IRAM Heap support enabled.\r\n" @@ -171,9 +171,9 @@ void setup() { // Compiling with Secondary Heap option does not change malloc to use the // IRAM region. It will continue to use the builtin DRAM until we request // otherwise. - Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("DRAM free: %6d\r\n", ESP.getFreeHeap()); uint32_t *mem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); - Serial.printf("DRAM buffer: Address %p, free %d\n", mem, ESP.getFreeHeap()); + Serial.printf("DRAM buffer: Address %p, free %d\r\n", mem, ESP.getFreeHeap()); if (!mem) { return; } @@ -181,9 +181,9 @@ void setup() { // Now request from the IRAM heap #ifdef USE_SET_IRAM_HEAP ESP.setIramHeap(); - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); uint32_t *imem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); - Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); + Serial.printf("IRAM buffer: Address %p, free %d\r\n", imem, ESP.getFreeHeap()); // Make sure we go back to the DRAM heap for other allocations. Don't forget to ESP.resetHeap()! ESP.resetHeap(); #else @@ -195,9 +195,9 @@ void setup() { // umm_set_heap_by_id(UMM_HEAP_IRAM); // ... // umm_set_heap_by_id(_heap_id); - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); imem = (uint32_t *)malloc(2 * 1024 * sizeof(uint32_t)); - Serial.printf("IRAM buffer: Address %p, free %d\n", imem, ESP.getFreeHeap()); + Serial.printf("IRAM buffer: Address %p, free %d\r\n", imem, ESP.getFreeHeap()); } #endif if (!imem) { @@ -209,14 +209,14 @@ void setup() { int nK = 1; Serial.println(); t = cyclesToWrite_nKx32(nK, imem); - Serial.printf("IRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("IRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx32(nK, imem, &res); - Serial.printf("IRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("IRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); t = cyclesToWrite_nKx32(nK, mem); - Serial.printf("DRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\n", t, nK, t/(nK*1024)); + Serial.printf("DRAM Memory Write: %6d cycles for %dK by 32, %3d AVG cycles/transfer\r\n", t, nK, t / (nK * 1024)); t = cyclesToRead_nKx32(nK, mem, &res); - Serial.printf("DRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\n", t, nK, t/(nK*1024), res); + Serial.printf("DRAM Memory Read: %6d cycles for %dK by 32, %3d AVG cycles/transfer (sum %08x)\r\n", t, nK, t / (nK * 1024), res); Serial.println(); perfTest_nK(1, mem, imem); Serial.println(); @@ -232,13 +232,13 @@ void setup() { s += ' '; } ESP.resetHeap(); - Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("DRAM free: %6d\r\n", ESP.getFreeHeap()); ESP.setIramHeap(); - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); ESP.resetHeap(); - Serial.printf("String: %s\n", s.c_str()); + Serial.printf("String: %s\r\n", s.c_str()); ESP.setIramHeap(); - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); ESP.resetHeap(); #else { @@ -251,15 +251,15 @@ void setup() { } { HeapSelectDram ephemeral; - Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("DRAM free: %6d\r\n", ESP.getFreeHeap()); } // Back to IRAM - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); - Serial.printf("String: %s\n", s.c_str()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); + Serial.printf("String: %s\r\n", s.c_str()); } { HeapSelectIram ephemeral; - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); } #endif @@ -270,38 +270,38 @@ void setup() { imem = NULL; mem = NULL; - Serial.printf("DRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("DRAM free: %6d\r\n", ESP.getFreeHeap()); #ifdef USE_SET_IRAM_HEAP ESP.setIramHeap(); - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); ESP.resetHeap(); #else { HeapSelectIram ephemeral; - Serial.printf("IRAM free: %6d\n", ESP.getFreeHeap()); + Serial.printf("IRAM free: %6d\r\n", ESP.getFreeHeap()); } #endif { - ets_uart_printf("Try and allocate all of the heap in one chunk\n"); + ETS_PRINTF("Try and allocate all of the heap in one chunk\n"); HeapSelectIram ephemeral; size_t free_iram = ESP.getFreeHeap(); - ets_uart_printf("IRAM free: %6d\n", free_iram); + ETS_PRINTF("IRAM free: %6d\n", free_iram); uint32_t hfree; uint16_t hmax; uint8_t hfrag; ESP.getHeapStats(&hfree, &hmax, &hfrag); - ets_uart_printf("ESP.getHeapStats(free: %u, max: %u, frag: %u)\n", + ETS_PRINTF("ESP.getHeapStats(free: %u, max: %u, frag: %u)\n", hfree, hmax, hfrag); if (free_iram > UMM_OVERHEAD_ADJUST) { void *all = malloc(free_iram - UMM_OVERHEAD_ADJUST); - ets_uart_printf("%p = malloc(%u)\n", all, free_iram); + ETS_PRINTF("%p = malloc(%u)\n", all, free_iram); umm_info(NULL, true); free_iram = ESP.getFreeHeap(); - ets_uart_printf("IRAM free: %6d\n", free_iram); + ETS_PRINTF("IRAM free: %6d\n", free_iram); free(all); - ets_uart_printf("IRAM free: %6d\n", ESP.getFreeHeap()); + ETS_PRINTF("IRAM free: %6d\n", ESP.getFreeHeap()); } } } @@ -325,7 +325,7 @@ void processKey(Print& out, int hotKey) { } { HeapSelectDram ephemeral; - Serial.printf(PSTR("DRAM ESP.getFreeHeap: %u\n"), ESP.getFreeHeap()); + Serial.printf(PSTR("DRAM ESP.getFreeHeap: %u\r\n"), ESP.getFreeHeap()); } break; } @@ -362,48 +362,3 @@ void loop(void) { processKey(Serial, hotKey); } } - - - // t = cyclesToWrite_nKx8(4, (uint8_t*)imem); - // Serial.printf("IRAM Memory Write: %6d cycles for 4K by 8\n", t); - // t = cyclesToWrite_nKx8_viaInline(4, (uint8_t*)imem); - // Serial.printf("IRAM Memory Write Inline: %6d cycles for 4K by 8\n", t); - // t = cyclesToWrite_nKx8(4, (uint8_t*)mem); - // Serial.printf("DRAM Memory Write: %6d cycles for 4K by 8\n", t); - // - // t = cyclesToRead_nKx8(4, (uint8_t*)imem, &res); - // Serial.printf("IRAM Memory Read: %6d cycles for 4K by 8 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx8_viaInline(4, (uint8_t*)imem, &res); - // Serial.printf("IRAM Memory Read Inline: %6d cycles for 4K by 8 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx8(4, (uint8_t*)mem, &res); - // Serial.printf("DRAM Memory Read: %6d cycles for 4K by 8 (sum %08x)\n", t, res); - // - // - // nK = 1; - // t = cyclesToWrite_nKx16(nK, (uint16_t*)imem); - // Serial.printf("IRAM Memory Write: %6d cycles for 1K by 16\n", t); - // t = cyclesToWrite_nKx16_viaInline(nK, (uint16_t*)imem); - // Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 16\n", t); - // t = cyclesToWrite_nKx16(nK, (uint16_t*)mem); - // Serial.printf("DRAM Memory Write: %6d cycles for 1K by 16\n", t); - // - // t = cyclesToRead_nKx16(nK, (uint16_t*)imem, &res); - // Serial.printf("IRAM Memory Read: %6d cycles for 1K by 16 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx16_viaInline(nK, (uint16_t*)imem, &res); - // Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 16 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx16(nK, (uint16_t*)mem, &res); - // Serial.printf("DRAM Memory Read: %6d cycles for 1K by 16 (sum %08x)\n", t, res); - // - // t = cyclesToWrite_nKx8(nK, (uint8_t*)imem); - // Serial.printf("IRAM Memory Write: %6d cycles for 1K by 8\n", t); - // t = cyclesToWrite_nKx8_viaInline(nK, (uint8_t*)imem); - // Serial.printf("IRAM Memory Write Inline: %6d cycles for 1K by 8\n", t); - // t = cyclesToWrite_nKx8((uint8_t*)mem); - // Serial.printf("DRAM Memory Write: %6d cycles for 1K by 8\n", t); - // - // t = cyclesToRead_nKx8(nK, (uint8_t*)imem, &res); - // Serial.printf("IRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx8_viaInline(nK, (uint8_t*)imem, &res); - // Serial.printf("IRAM Memory Read Inline: %6d cycles for 1K by 8 (sum %08x)\n", t, res); - // t = cyclesToRead_nKx8(nK, (uint8_t*)mem, &res); - // Serial.printf("DRAM Memory Read: %6d cycles for 1K by 8 (sum %08x)\n", t, res); From a3bf35cff7abc0bd89090601b112efc218c07f33 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 2 Dec 2020 14:03:50 -0800 Subject: [PATCH 47/48] Style fix --- libraries/esp8266/examples/irammem/irammem.ino | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/esp8266/examples/irammem/irammem.ino b/libraries/esp8266/examples/irammem/irammem.ino index 8f16bc48ae..57b1b31b44 100644 --- a/libraries/esp8266/examples/irammem/irammem.ino +++ b/libraries/esp8266/examples/irammem/irammem.ino @@ -291,7 +291,7 @@ void setup() { uint8_t hfrag; ESP.getHeapStats(&hfree, &hmax, &hfrag); ETS_PRINTF("ESP.getHeapStats(free: %u, max: %u, frag: %u)\n", - hfree, hmax, hfrag); + hfree, hmax, hfrag); if (free_iram > UMM_OVERHEAD_ADJUST) { void *all = malloc(free_iram - UMM_OVERHEAD_ADJUST); ETS_PRINTF("%p = malloc(%u)\n", all, free_iram); From 1ff2aef5c912b3196686c5ea964f72d90f4fddb8 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 5 Dec 2020 09:45:19 -0800 Subject: [PATCH 48/48] Remove unnessasary IRAM_ATTR from install_non32xfer_exception_handler Some comment tuning. In the context of _xtos_set_exception_handler and the functions it registers, changed to type int for exception cause type. This is also the type used by gdbstub and some other Xtensa files I found. --- cores/esp8266/core_esp8266_non32xfer.cpp | 6 +++--- cores/esp8266/esp8266_undocumented.h | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp index 47e9f58f6f..eb4741e1ed 100644 --- a/cores/esp8266/core_esp8266_non32xfer.cpp +++ b/cores/esp8266/core_esp8266_non32xfer.cpp @@ -50,7 +50,7 @@ extern "C" { static fn_c_exception_handler_t old_c_handler = NULL; -static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, uint32_t cause) +static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, int cause) { do { /* @@ -194,14 +194,14 @@ static IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, #define ROM_xtos_c_wrapper_handler (reinterpret_cast<_xtos_handler>(0x40000598)) -static void IRAM_ATTR _set_exception_handler_wrapper(uint32_t cause) { +static void _set_exception_handler_wrapper(int cause) { _xtos_handler old_wrapper = _xtos_exc_handler_table[cause]; if (old_wrapper == ROM_xtos_c_wrapper_handler) { _xtos_exc_handler_table[cause] = _xtos_c_wrapper_handler; } } -void IRAM_ATTR install_non32xfer_exception_handler(void) { +void install_non32xfer_exception_handler(void) { if (NULL == old_c_handler) { // Set the "C" exception handler the wrapper will call old_c_handler = diff --git a/cores/esp8266/esp8266_undocumented.h b/cores/esp8266/esp8266_undocumented.h index fd40b8ac87..a19835218b 100644 --- a/cores/esp8266/esp8266_undocumented.h +++ b/cores/esp8266/esp8266_undocumented.h @@ -145,14 +145,14 @@ _xtos_handler_func _xtos_unhandled_exception; #ifdef __cplusplus -// These definitions that try to be more precise for .cpp module usage. +// For these definitions, try to be more precise for .cpp module usage. /* A detailed typdef for the "C" callable functions found in `_xtos_c_handler_table[]` More details in `_xtos_set_exception_handler` comments below. */ -typedef void (*fn_c_exception_handler_t)(struct __exception_frame *ef, uint32_t cause); +typedef void (*fn_c_exception_handler_t)(struct __exception_frame *ef, int cause); /* TMI maybe? However, it may be useful for a deep debugging session. @@ -165,7 +165,7 @@ typedef void (*fn_c_exception_handler_t)(struct __exception_frame *ef, uint32_t Note, if nesting handlers is desired this must be implemented in the new "C" exception handler(s) being registered. */ -extern void _xtos_p_none(struct __exception_frame *ef, uint32_t cause); +extern void _xtos_p_none(struct __exception_frame *ef, int cause); /* TMI maybe? @@ -185,7 +185,7 @@ extern fn_c_exception_handler_t _xtos_c_handler_table[XCHAL_EXCCAUSE_NUM]; ROM API function `_xtos_set_exception_handler` registers a "C" callable exception handler for a specified general exception, (EXCCAUSE value). (source in xtensa/xtos/exc-sethandler.c) - * If `reason` (EXCCAUSE) is out of range, >=64, it returns NULL. + * If `cause`/reason (EXCCAUSE) is out of range, >=64, it returns NULL. * If the new exception handler is installed, it returns the previous handler. * If the previous handler was `_xtos_unhandled_exception`/`_xtos_p_none`, it returns NULL. @@ -203,7 +203,7 @@ extern fn_c_exception_handler_t _xtos_c_handler_table[XCHAL_EXCCAUSE_NUM]; To aid against future conflicts, keep these new defines limited to .cpp with `#ifdef __cplusplus`. */ -extern fn_c_exception_handler_t _xtos_set_exception_handler(uint32_t reason, fn_c_exception_handler_t fn); +extern fn_c_exception_handler_t _xtos_set_exception_handler(int cause, fn_c_exception_handler_t fn); #endif #ifdef __cplusplus