From 8874ea8a125961a835db9718a9535675c361c322 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 20 Aug 2022 08:47:52 -0700 Subject: [PATCH 1/5] Enable SPI_CS_SETUP for early ICACHE use The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK as part of flash init/configuration. It may be necessary for some flash chips to perform correctly with ICACHE hardware access. Turning on and leaving it on should be okay. --- cores/esp8266/mmu_iram.cpp | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 9f1b05d455..b2a3df2e01 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -197,9 +197,31 @@ extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v); #endif // #if (MMU_ICACHE_SIZE == 0x4000) /* - * This wrapper is for running code from IROM (flash) before the SDK starts. + * This wrapper is for running code early from IROM (flash) before the SDK starts. + * Since the NONOS SDK will do a full/proper init for handling the flash device, + * we only do a minimum to make ICACHE functional, keeping IRAM use to a minimum. */ void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) { + // The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK + // as part of flash init/configuration. It may be necessary for some flash + // chips to perform correctly with ICACHE hardware access. Turning on and + // leaving it on should be okay. + // + // Upon reflection, most ESP8266 boards have a series resistor to the Flash + // CLK pin. While reducing ringing, it causes a slight delay of the CLK signal + // due to the effective RC circuit formed with the chip's input capacitance. + // This narrows the gap between #CS active and the rising CLK edge as seen by + // the chip. SPI_CS_SETUP can restore the safety margin for the #CS to CLK. + // + // One SPI bus clock cycle time is inserted between #CS active and 1st SPI bus + // clock cycle. The number of clock cycles is in SPI_CNTRL2 SPI_SETUP_TIME, + // defaults to 1. + SPI0U |= SPIUCSSETUP; // SPI_CS_SETUP or BIT5 + + // For early Cache_Read_Enable only do ICACHE_SIZE_16. The affected registers + // are fully restored when Cache_Read_Disable is called. With ICACHE_SIZE_32 + // one bit is missed at disable. Leave the full commitment to ICACHE_SIZE_32 + // for the NONOS SDK. Cache_Read_Enable(0, 0, ICACHE_SIZE_16); fn(); Cache_Read_Disable(); From f19c3db709fd26c6bb099664243a4130bc4750b7 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 20 Aug 2022 19:29:27 -0700 Subject: [PATCH 2/5] Cleanup comment --- cores/esp8266/mmu_iram.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index b2a3df2e01..7c752da40f 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -207,12 +207,6 @@ void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) { // chips to perform correctly with ICACHE hardware access. Turning on and // leaving it on should be okay. // - // Upon reflection, most ESP8266 boards have a series resistor to the Flash - // CLK pin. While reducing ringing, it causes a slight delay of the CLK signal - // due to the effective RC circuit formed with the chip's input capacitance. - // This narrows the gap between #CS active and the rising CLK edge as seen by - // the chip. SPI_CS_SETUP can restore the safety margin for the #CS to CLK. - // // One SPI bus clock cycle time is inserted between #CS active and 1st SPI bus // clock cycle. The number of clock cycles is in SPI_CNTRL2 SPI_SETUP_TIME, // defaults to 1. From f04dedf4df83be6ac131fd4fa508618722faa97d Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Wed, 24 Aug 2022 18:32:12 -0700 Subject: [PATCH 3/5] Change umm_init to default to IRAM Some flash chips (PUYA) have some unknown requirements for running with early `Cache_Read_Enable`. They work fine after the SDK is started. For now, change umm_init to default to IRAM. Define UMM_INIT_USE_ICACHE to move to ICACHE and free up IRAM. Added some experimental code that may indirectly support PUYA. Note, until this issue is resolved, that HWDT Stack Dump is not going to work with PUYA flash. --- cores/esp8266/hwdt_app_entry.cpp | 1 + cores/esp8266/mmu_iram.cpp | 27 ++++++++++++++++--- cores/esp8266/umm_malloc/umm_malloc_cfgport.h | 14 +++++++--- 3 files changed, 35 insertions(+), 7 deletions(-) diff --git a/cores/esp8266/hwdt_app_entry.cpp b/cores/esp8266/hwdt_app_entry.cpp index 28b8914d90..d0e8fc1e25 100644 --- a/cores/esp8266/hwdt_app_entry.cpp +++ b/cores/esp8266/hwdt_app_entry.cpp @@ -277,6 +277,7 @@ #include #include #include +#include " Date: Mon, 29 Aug 2022 21:24:35 -0700 Subject: [PATCH 4/5] typo --- cores/esp8266/hwdt_app_entry.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp8266/hwdt_app_entry.cpp b/cores/esp8266/hwdt_app_entry.cpp index d0e8fc1e25..0f0bee8d4e 100644 --- a/cores/esp8266/hwdt_app_entry.cpp +++ b/cores/esp8266/hwdt_app_entry.cpp @@ -277,7 +277,7 @@ #include #include #include -#include " Date: Tue, 30 Aug 2022 09:36:40 -0700 Subject: [PATCH 5/5] Finalize fix for PUYA flash and preSDK use of Cache_Read_Enable. This resolves the exception 0 issue with PUYA flash when using flash/ICACHE for umm_init and/or using HWDT Stack Dump. --- cores/esp8266/mmu_iram.cpp | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp index 50d4df5802..c54e9994c8 100644 --- a/cores/esp8266/mmu_iram.cpp +++ b/cores/esp8266/mmu_iram.cpp @@ -196,17 +196,17 @@ extern void Cache_Read_Disable(void); extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v); #endif // #if (MMU_ICACHE_SIZE == 0x4000) -#if 1 // New experimental code /* * This wrapper is for running code early from IROM (flash) before the SDK * starts. Since the NONOS SDK will do a full and proper flash device init for * speed and mode, we only do a minimum to make ICACHE functional, keeping IRAM * use to a minimum. After the SDK has started, this function is not needed and - * should not be called. + * must not be called. */ void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) { - //?? If the problem is not resolved add this line back. - //?? Cache_Read_Disable(); + // Cache Read must be disabled. This is always the case on entry when called + // from the right context. + // Cache_Read_Disable(); // The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK // as part of flash init/configuration. It may be necessary for some flash @@ -218,28 +218,20 @@ void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) { // defaults to 1. SPI0U |= SPIUCSSETUP; // SPI_CS_SETUP or BIT5 - // I am not sure what this is does. It appears to be the key function called - // from `fix_cache_bug` in the NONOS SDK - Will this help PUYA Flash work? - // It appears to do some, lowlevel undocumented register maniplation and - // device specific init based on OTP CHIPID model bits. + // phy_get_bb_evm is the key function, called from fix_cache_bug in the NONOS + // SDK. This addition resolves the PUYA Flash issue with exception 0, when + // early Cache_Read_Enable is used. extern uint32_t phy_get_bb_evm(void); // undocumented phy_get_bb_evm(); - // For early Cache_Read_Enable only do ICACHE_SIZE_16. The affected registers - // are fully restored when Cache_Read_Disable is called. With ICACHE_SIZE_32 - // one bit is missed at disable. Leave the full commitment to ICACHE_SIZE_32 - // for the NONOS SDK. + // For early Cache_Read_Enable, only do ICACHE_SIZE_16. With this option, + // Cache_Read_Disable will fully restore the original register states. With + // ICACHE_SIZE_32, one bit is missed when disabling. Leave the full access + // calls for the NONOS SDK. // This only works with image slice 0, which is all we do presently. Cache_Read_Enable(0, 0, ICACHE_SIZE_16); fn(); Cache_Read_Disable(); } -#else -void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) { - Cache_Read_Enable(0, 0, ICACHE_SIZE_16); - fn(); - Cache_Read_Disable(); -} -#endif };