From 3ef2ff443fc6d4c9db2ad0bee8e243e8dad1a19e Mon Sep 17 00:00:00 2001 From: 8785benjamin <39658811+8785benjamin@users.noreply.github.com> Date: Fri, 8 Jun 2018 22:00:14 +0200 Subject: [PATCH 1/5] Add files via upload --- gas/config/tc-esp32ulp.c | 45 ++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 29 deletions(-) diff --git a/gas/config/tc-esp32ulp.c b/gas/config/tc-esp32ulp.c index 412c884c04..4b18c68faa 100755 --- a/gas/config/tc-esp32ulp.c +++ b/gas/config/tc-esp32ulp.c @@ -166,9 +166,8 @@ This is called for every line that contains real assembly code. */ void md_assemble(char *line) { - char *toP = 0; - int size, insn_size; - struct esp32ulp_insn *tmp_insn; + char *toP ; + int insn_size; size_t len; static size_t buffer_len = 0; static char *current_inputline; @@ -184,47 +183,35 @@ md_assemble(char *line) current_inputline[len] = ';'; current_inputline[len + 1] = '\0'; - //if (insn) //DEBUG_TRACE("dya_pass 222 insn old =%08x\n", (unsigned int)insn->value); + // run the parser on the instruction + // it will return a list of chained "insn", + // the first contains the opcode of the instruction + // and may be followed by other "insn" like an address state = parse(current_inputline); - //if (insn) //DEBUG_TRACE("dya_pass 222 insn new =%08x\n", (unsigned int)insn->value); - if (state == NO_INSN_GENERATED) + if (state == NO_INSN_GENERATED || !insn) return; - for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next) - if (!tmp_insn->reloc || !tmp_insn->exp->symbol) - insn_size += 2; - // TODO:DYA insn_size - must be 4 in any case + // add 4 bytes to the fragment code buffer to put the new instruction + // and get buffer pointer (toP) on where to write the instruction insn_size = 4; - if (insn_size) - toP = frag_more(insn_size); - - last_insn_size = insn_size; + toP = frag_more(insn_size); #ifdef DEBUG printf("INS: %s\n", line); #endif + md_number_to_chars(toP, insn->value, insn_size); // put the 4-byte instruction into the current fragment code buffer + while (insn) { if (insn->reloc && insn->exp->symbol) { - size = 4; //DEBUG_TRACE("insn->reloc && insn->exp->symbol BFD_ARELOC_ESP32ULP_PUSH size =%i, insn->exp->value=%i, insn->pcrel=%i, insn->reloc=%i\n", size, (unsigned int)insn->exp->value, insn->pcrel, insn->reloc); - //char *prev_toP = toP - 2; - //fix_new(frag_now, (prev_toP - frag_now->fr_literal), size, insn->exp->symbol, insn->exp->value, insn->pcrel, insn->reloc); - // were - shift from current word... - fix_new(frag_now, 0, size, insn->exp->symbol, insn->exp->value, insn->pcrel, insn->reloc); - } - else - { - //DEBUG_TRACE("md_number_to_chars insn->value =%08x\n", (unsigned int)insn->value); - //md_number_to_chars(toP, insn->value, 2); - //toP += 2; - // TODO:DYA - this is main changes for 32 bit words!!!!! changes stop work - md_number_to_chars(toP, insn->value, 4); - toP += 4; + // generate a relocation request for this instruction so that linker will put the right address + // toP is the pointer on this instruction in the buffer of the current code fragment + // frag_now->fr_literal is the pointer on the begining of the buffer of the current code fragment + fix_new(frag_now, toP - frag_now->fr_literal, insn_size, insn->exp->symbol, insn->exp->value, insn->pcrel, insn->reloc); } - size = 4; #ifdef DEBUG //DEBUG_TRACE(" reloc : value = %08x, pc=%08x, reloc=%08x BFD_RELOC_ESP32ULP_PLTPC = %08x\n", (unsigned int)insn->value, (unsigned int)insn->pcrel, (unsigned int)insn->reloc, BFD_RELOC_ESP32ULP_PLTPC); if (insn->exp != ((void*)(0))) From bf4e7b01e2a78b8a33f8ed77057f2ac61ed774e7 Mon Sep 17 00:00:00 2001 From: 8785benjamin <39658811+8785benjamin@users.noreply.github.com> Date: Fri, 8 Jun 2018 22:03:03 +0200 Subject: [PATCH 2/5] Add files via upload --- binutils/stabs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/binutils/stabs.c b/binutils/stabs.c index f5c5d2d8e0..d3fc4afe24 100644 --- a/binutils/stabs.c +++ b/binutils/stabs.c @@ -2702,7 +2702,7 @@ parse_stab_members (void *dhandle, struct stab_handle *info, ++*pp; voffset &= 0x7fffffff; - if (**pp == ';' || *pp == '\0') + if (**pp == ';' || **pp == '\0') { /* Must be g++ version 1. */ context = DEBUG_TYPE_NULL; From 61bfe2ca5f540145b739e6a651ee1569884f3452 Mon Sep 17 00:00:00 2001 From: 8785benjamin <39658811+8785benjamin@users.noreply.github.com> Date: Fri, 8 Jun 2018 22:05:18 +0200 Subject: [PATCH 3/5] Add files via upload --- opcodes/disassemble.c | 6 + opcodes/esp32ulp-dis.c | 561 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 567 insertions(+) diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 1b1524247a..c4cd1af1d0 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -35,6 +35,7 @@ #define ARCH_d30v #define ARCH_dlx #define ARCH_epiphany +#define ARCH_esp32ulp #define ARCH_fr30 #define ARCH_frv #define ARCH_ft32 @@ -242,6 +243,11 @@ disassembler (bfd *abfd) disassemble = print_insn_epiphany; break; #endif +#ifdef ARCH_esp32ulp + case bfd_arch_esp32ulp: + disassemble = print_insn_esp32ulp; + break; +#endif #ifdef ARCH_fr30 case bfd_arch_fr30: disassemble = print_insn_fr30; diff --git a/opcodes/esp32ulp-dis.c b/opcodes/esp32ulp-dis.c index b174cda9c5..541177d68d 100755 --- a/opcodes/esp32ulp-dis.c +++ b/opcodes/esp32ulp-dis.c @@ -16,3 +16,564 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Disassembler for ESP32 ULP processor + file to be put in folder opcodes/disassemble + + don't forget to add: + 1)opcodes/disassemble.c: + #define ARCH_esp32ulp + .. + #ifdef ARCH_esp32ulp + case bfd_arch_esp32ulp: + disassemble = print_insn_esp32ulp; + break; + #endif + + 2) include/dis-asm.h: + extern int print_insn_esp32ulp (bfd_vma, disassemble_info *); + +*/ + +#include "sysdep.h" +#include "dis-asm.h" +#include "floatformat.h" +#include "libiberty.h" +#include "opintl.h" + + +typedef struct +{ + unsigned int operand: 28; + unsigned int opcode : 4; +} esp32ulp_inst; + +static void disasm_esp32ulp_instruction(esp32ulp_inst inst, unsigned int addr); +static void unknown(void); +static void regwr(unsigned int operand); +static void regrd(unsigned int operand); +static void i2c(unsigned int operand); +static void wait(unsigned int operand); +static void adc(unsigned int operand); +static void store(unsigned int operand); +static void operation(unsigned int operand); +static void operation_reg(unsigned int operand); +static void operation_imm(unsigned int operand); +static void operation_stage(unsigned int operand); +static void jmp(unsigned int operand, unsigned int address); +static void jump(unsigned int operand, unsigned int address); +static void jumpr(unsigned int operand, unsigned int address); +static void jumps(unsigned int operand, unsigned int address); +static void wakesleep(unsigned int operand); +static void tsens(unsigned int operand); +static void halt(unsigned int operand); +static void load(unsigned int operand); + + +#define ESP32ULP_INSTR_SIZE 4 +#define INST_TO_ADDR(inst) ((inst)*ESP32ULP_INSTR_SIZE) +#define ADDR_TO_INST(addr) ((addr)/ESP32ULP_INSTR_SIZE) + +#define COPY(a,b) memcpy(&a, &b, sizeof(a)); + +/* Maximum length of an instruction. */ +#define MAXLEN ESP32ULP_INSTR_SIZE + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + + + struct private *priv = (struct private *)info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + return 0; + } + else + priv->max_fetched = addr; + return 1; +} + +struct disassemble_info* dinfo ; + +int +print_insn_esp32ulp (bfd_vma memaddr, disassemble_info *info) +{ + dinfo = info; + + struct private priv; + bfd_byte *buffer = priv.the_buffer; + + dinfo->private_data = & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + + FETCH_DATA (dinfo, buffer + ESP32ULP_INSTR_SIZE); + + esp32ulp_inst inst; + COPY(inst, *buffer); + disasm_esp32ulp_instruction(inst, (unsigned int)memaddr); + + return ESP32ULP_INSTR_SIZE; +} + + + + + + + +static void disasm_esp32ulp_instruction(esp32ulp_inst inst, unsigned int addr) +{ +// dinfo->fprintf_func(dinfo->stream, "%04x %04x %01x%07x ", ADDR_TO_INST(addr), addr, inst.opcode, inst.operand); + + unsigned int operand = inst.operand; + switch(inst.opcode) + { + case 1: regwr(operand); break; + case 2: regrd(operand); break; + case 3: i2c(operand); break; + case 4: wait(operand); break; + case 5: adc(operand); break; + case 6: store(operand); break; + case 7: operation(operand); break; + case 8: jmp(operand, addr); break; + case 9: wakesleep(operand); break; + case 10: tsens(operand); break; + case 11: halt(operand); break; + case 13: load(operand); break; + default: unknown(); break; + } +} + +static void unknown(void) +{ + dinfo->fprintf_func(dinfo->stream, "????"); +} + +// from soc.h +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 + +typedef struct { +unsigned int addr:10; +unsigned int data:8; +unsigned int low: 5; +unsigned int high: 5; +} fregwr; + + +static void regwr(unsigned int operand) +{ + fregwr op; + COPY(op, operand); + + unsigned int addr = INST_TO_ADDR(op.addr)+DR_REG_RTCCNTL_BASE; + unsigned int base; + unsigned int offset; + char* pstr; + + if (addr>=DR_REG_RTC_I2C_BASE) { base = DR_REG_RTC_I2C_BASE; pstr = "RTC_I2C_BASE"; } + else if (addr>=DR_REG_SENS_BASE) { base = DR_REG_SENS_BASE; pstr = "SENS_BASE"; } + else if (addr>=DR_REG_RTCIO_BASE) { base = DR_REG_RTCIO_BASE; pstr = "RTCIO_BASE"; } + else { base = DR_REG_RTCCNTL_BASE ;pstr = "RTCCNTL_BASE"; } + + offset = addr - base; + + dinfo->fprintf_func(dinfo->stream, "REG_WR "); + dinfo->fprintf_func(dinfo->stream, "0x%x+0x%x, %d, %d, 0x%x", base, offset, op.high, op.low, op.data ); + dinfo->fprintf_func(dinfo->stream, "\t // REG(%s+0x%x)[%d:%d]=0x%x", pstr, offset, op.high, op.low, op.data); +} + +typedef struct { +unsigned int addr:10; +unsigned int dummy:8; +unsigned int low: 5; +unsigned int high: 5; +} fregrd; + +static void regrd(unsigned int operand) +{ + fregrd op; + COPY(op, operand); + + unsigned int addr = INST_TO_ADDR(op.addr)+DR_REG_RTCCNTL_BASE; + unsigned int base; + unsigned int offset; + char* pstr; + + if (addr>=DR_REG_RTC_I2C_BASE) { base = DR_REG_RTC_I2C_BASE; pstr = "RTC_I2C_BASE"; } + else if (addr>=DR_REG_SENS_BASE) { base = DR_REG_SENS_BASE; pstr = "SENS_BASE"; } + else if (addr>=DR_REG_RTCIO_BASE) { base = DR_REG_RTCIO_BASE; pstr = "RTCIO_BASE"; } + else { base = DR_REG_RTCCNTL_BASE ;pstr = "RTCCNTL_BASE"; } + + offset = addr - base; + + dinfo->fprintf_func(dinfo->stream, "REG_RD "); + dinfo->fprintf_func(dinfo->stream, "0x%x+0x%x, %d, %d", base, offset, op.high, op.low); + dinfo->fprintf_func(dinfo->stream, "\t\t // REG(%s+0x%x)[%d:%d]=0x%x", pstr, offset, op.high, op.low); +} + +typedef struct { +unsigned int subaddr:8; +unsigned int data:8; +unsigned int low: 3; +unsigned int high: 3; +unsigned int sel: 4; +unsigned int dummy:1; +unsigned int rw: 1; +} fi2c; + +static void i2c(unsigned int operand) +{ + fi2c op; + COPY(op, operand); + + if (op.rw == 0) + dinfo->fprintf_func(dinfo->stream, "I2C_RD 0x%x, %d, %d, %d \t\t // I2C_READ SLAVE_ADDR 0x%x, REG%d [%d:%d]", op.subaddr, op.high, op.low, op.sel, op.subaddr, op.sel, op.low, op.high); + else + dinfo->fprintf_func(dinfo->stream, "I2C_WR 0x%x, 0x%x, %d, %d, %d \t // I2C_WRITE SLAVE_ADDR 0x%x, REG%d [%d:%d]=%x", op.subaddr, op.data, op.high, op.low, op.sel, op.subaddr, op.sel, op.low, op.high, op.data); +} + +typedef struct { +unsigned int cycles:16; +unsigned int dummy:8; +} fwait; + +static void wait(unsigned int operand) +{ + fwait op; + COPY(op, operand); + + if (op.cycles == 0) + dinfo->fprintf_func(dinfo->stream, "NOP", op.cycles); + else + dinfo->fprintf_func(dinfo->stream, "WAIT %d", op.cycles); +} + +typedef struct { +unsigned int Rdst:2; +unsigned int Sarmux:4; +unsigned int sel:1; +unsigned int dummy:21; +} fadc; + +static void adc(unsigned int operand) +{ + fadc op; + COPY(op, operand); + + dinfo->fprintf_func(dinfo->stream, "ADC R%d, %d, %d\t\t\t\t\t // R%d=ADC%d pad%d", op.Rdst, op.Sarmux, op.sel, op.Rdst, op.Sarmux+1, op.sel+1); +} + +typedef struct +{ + unsigned int operand:25; + unsigned int choice: 3; +} fop; + + +typedef struct +{ + unsigned int Rdst: 2; + unsigned int Rsrc1: 2; + unsigned int Rsrc2: 2; + unsigned int dummy:15; + unsigned int sel: 4; + unsigned int choice:3; // 0 +} fop_reg; + +typedef struct +{ + unsigned int Rdst: 2; + unsigned int Rsrc1: 2; + unsigned int imm: 16; + unsigned int dummy1:1; + unsigned int sel: 4; + unsigned int choice:3; // 1 +} fop_imm; + +typedef struct +{ + unsigned int dummy: 4; + unsigned int imm: 8; + unsigned int dummy2:9; + unsigned int sel: 4; + unsigned int choice:3; // 2 +} fop_stage; + +static void operation(unsigned int operand) +{ + fop op; + COPY(op, operand); + + switch(op.choice) + { + case 0: operation_reg(operand); break; + case 1: operation_imm(operand); break; + case 2: operation_stage(operand); break; + default: dinfo->fprintf_func(dinfo->stream, "ALU ???"); break; + } +} + +static void operation_reg(unsigned int operand) +{ + fop_reg opr; + COPY(opr, operand); + + switch(opr.sel) + { + case 0: dinfo->fprintf_func(dinfo->stream, "ADD R%d, R%d, R%d \t\t\t\t\t // R%d = R%d + R%d", opr.Rdst, opr.Rsrc1, opr.Rsrc2, opr.Rdst, opr.Rsrc1, opr.Rsrc2); break; + case 1: dinfo->fprintf_func(dinfo->stream, "SUB R%d, R%d, R%d \t\t\t\t\t // R%d = R%d - R%d", opr.Rdst, opr.Rsrc1, opr.Rsrc2, opr.Rdst, opr.Rsrc1, opr.Rsrc2); break; + case 2: dinfo->fprintf_func(dinfo->stream, "AND R%d, R%d, R%d \t\t\t\t\t // R%d = R%d & R%d", opr.Rdst, opr.Rsrc1, opr.Rsrc2, opr.Rdst, opr.Rsrc1, opr.Rsrc2); break; + case 3: dinfo->fprintf_func(dinfo->stream, "OR R%d, R%d, R%d \t\t\t\t\t // R%d = R%d | R%d", opr.Rdst, opr.Rsrc1, opr.Rsrc2, opr.Rdst, opr.Rsrc1, opr.Rsrc2); break; + case 4: dinfo->fprintf_func(dinfo->stream, "MOVE R%d, R%d \t\t\t\t\t // R%d = R%d", opr.Rdst, opr.Rsrc1, opr.Rdst, opr.Rsrc1); break; + case 5: dinfo->fprintf_func(dinfo->stream, "LSH R%d, R%d, R%d \t\t\t\t\t // R%d = R%d<fprintf_func(dinfo->stream, "RSH R%d, R%d, R%d \t\t\t\t\t // R%d = R%d>>R%d", opr.Rdst, opr.Rsrc1, opr.Rsrc2, opr.Rdst, opr.Rsrc1, opr.Rsrc2); break; + default: dinfo->fprintf_func(dinfo->stream, "ALU ????"); break; + } +} + +static void operation_imm(unsigned int operand) +{ + fop_imm opi; + COPY(opi, operand); + + switch(opi.sel) + { + case 0: dinfo->fprintf_func(dinfo->stream, "ADD R%d, R%d, %d \t\t\t\t\t // R%d = R%d + %d", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + case 1: dinfo->fprintf_func(dinfo->stream, "SUB R%d, R%d, %d \t\t\t\t\t // R%d = R%d - %d", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + case 2: dinfo->fprintf_func(dinfo->stream, "AND R%d, R%d, 0x%04x \t\t\t\t // R%d = R%d & 0x%x", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + case 3: dinfo->fprintf_func(dinfo->stream, "OR R%d, R%d, 0x%04x \t\t\t\t // R%d = R%d | 0x%x", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + case 4: dinfo->fprintf_func(dinfo->stream, "MOVE R%d, %d \t\t\t\t\t // R%d = %d \t\t\t (can also be pointer to address 0x%04x)", opi.Rdst, opi.imm, opi.Rdst, opi.imm, INST_TO_ADDR(opi.imm)); break; + case 5: dinfo->fprintf_func(dinfo->stream, "LSH R%d, R%d, %d \t\t\t\t\t // R%d = R%d<<%d", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + case 6: dinfo->fprintf_func(dinfo->stream, "RSH R%d, R%d, %d \t\t\t\t\t // R%d = R%d>>%d", opi.Rdst, opi.Rsrc1, opi.imm, opi.Rdst, opi.Rsrc1, opi.imm); break; + default: dinfo->fprintf_func(dinfo->stream, "ALU ????"); break; + } +} + +static void operation_stage(unsigned int operand) +{ + fop_stage ops; + COPY(ops, operand); + + switch(ops.sel) + { + case 0: dinfo->fprintf_func(dinfo->stream, "STAGE_INC %d", ops.imm); break; + case 1: dinfo->fprintf_func(dinfo->stream, "STAGE_DEC %d", ops.imm); break; + case 2: dinfo->fprintf_func(dinfo->stream, "STAGE_RST"); break; + + default: dinfo->fprintf_func(dinfo->stream, "ALU ????"); break; + } +} + + +typedef struct +{ + unsigned int operand:25; + unsigned int choice:3; +} fjmp; + +typedef struct +{ + unsigned int rdest:2; + unsigned int addr:11; + unsigned int dummy:8; + unsigned int sel: 1; + unsigned int type: 2; + unsigned int choice:3; // 0 +} fjump; + +typedef struct +{ + unsigned int thres:16; + unsigned int cond: 1; + unsigned int step: 8; + unsigned int choice:3; // 1 +} fjumpr; + +typedef struct +{ + unsigned int thres: 8; + unsigned int dummy: 7; + unsigned int cond: 2; + unsigned int step: 8; + unsigned int choice:3; // 2 +} fjumps; + +static void jmp(unsigned int operand, unsigned int address) +{ + fjmp op; + COPY(op, operand); + + switch(op.choice) + { + case 0: jump(operand, address); break; + case 1: jumpr(operand, address); break; + case 2: jumps(operand, address); break; + default: dinfo->fprintf_func(dinfo->stream, "JUMP????"); break; + } +} + +static void jump(unsigned int operand, unsigned int address) +{ + fjump op; + COPY(op, operand); + + address = address; // fake instruction to astatic void compiler warning (unused parameter) + + dinfo->fprintf_func(dinfo->stream, "JUMP "); + + if (op.sel==0) + dinfo->fprintf_func(dinfo->stream, "0x%04x", INST_TO_ADDR(op.addr)); + else + dinfo->fprintf_func(dinfo->stream, "R%d", op.rdest); + + switch(op.type) + { + case 1: dinfo->fprintf_func(dinfo->stream, ",EQ \t\t\t\t\t // if operation==0 THEN JUMP"); break; + case 2: dinfo->fprintf_func(dinfo->stream, ",OV \t\t\t\t\t // if overflow THEN JUMP"); break; + } +} + +static void jumpr(unsigned int operand, unsigned int address) +{ + fjumpr op; + COPY(op, operand); + + unsigned int relative = INST_TO_ADDR(op.step&0x7F); + int sign = (op.step&0x80 ? -1 : +1); + + dinfo->fprintf_func(dinfo->stream, "JUMPR "); + dinfo->fprintf_func(dinfo->stream, "0x%04x, %d, %s", address+sign*relative, op.thres, (op.cond==0?"lt":"ge") ); + + dinfo->fprintf_func(dinfo->stream, "\t\t\t\t\t // IF R0%s%d THEN JUMP TO [0x%04x%c0x%02x]", (op.cond==0?"<":">="), op.thres, address, (sign>0?'+':'-'), relative); +} + +static void jumps(unsigned int operand, unsigned int address) +{ + fjumps op; + COPY(op, operand); + + unsigned int relative = INST_TO_ADDR(op.step&0x7F); + int sign = (op.step&0x80 ? -1 : +1); + + dinfo->fprintf_func(dinfo->stream, "JUMPS "); + dinfo->fprintf_func(dinfo->stream, "0x%04x, ", address+sign*relative); + + switch(op.cond) + { + case 0: dinfo->fprintf_func(dinfo->stream, "%d, lt", op.thres); break; + case 1: dinfo->fprintf_func(dinfo->stream, "%d, gt", op.thres); break; + default: dinfo->fprintf_func(dinfo->stream, "%d, eq", op.thres); break; + } + + dinfo->fprintf_func(dinfo->stream, "\t\t\t\t\t // "); + + switch(op.cond) + { + case 0: dinfo->fprintf_func(dinfo->stream, "IF COUNT<%d ", op.thres); break; + case 1: dinfo->fprintf_func(dinfo->stream, "IF COUNT>%d ", op.thres); break; + default: dinfo->fprintf_func(dinfo->stream, "IF COUNT==%d ", op.thres); break; + } + + dinfo->fprintf_func(dinfo->stream,"THEN JUMP TO [0x%04x%c0x%02x]", address, (sign>0?'+':'-'), relative); +} + + + +typedef struct { +unsigned int reg:4; +unsigned int dummy:19; +unsigned int wakeorsleep:1; +} fwakesleep; + +static void wakesleep(unsigned int operand) +{ + fwakesleep op; + COPY(op, operand); + + if (op.wakeorsleep==0) + dinfo->fprintf_func(dinfo->stream, "WAKE"); + else + dinfo->fprintf_func(dinfo->stream, "SLEEP R%d", op.reg); +} + +typedef struct { +unsigned int Rdst:2; +unsigned int delay:14; +unsigned int dummy:12; +} ftsens; + +static void tsens(unsigned int operand) +{ + ftsens op; + COPY(op, operand); + + dinfo->fprintf_func(dinfo->stream, "TSENS R%d, %d\t\t\t\t\t // delay=%d", op.Rdst, op.delay, op.delay); +} + +static void halt(unsigned int operand) +{ + operand = operand; // fake instruction to astatic void compiler warning (unused parameter) + + dinfo->fprintf_func(dinfo->stream, "HALT"); +} + +typedef struct { +unsigned int Rdst:2; +unsigned int Rsrc:2; +unsigned int dummy:6; +unsigned int offset:11; +unsigned int dummy2: 7; +} fload; + +static void load(unsigned int operand) +{ + fload op; + COPY(op, operand); + + dinfo->fprintf_func(dinfo->stream, "LD R%d, R%d, %d \t\t\t\t\t // R%d = MEM[R%d+%d]", op.Rdst, op.Rsrc, INST_TO_ADDR(op.offset), op.Rdst, op.Rsrc, INST_TO_ADDR(op.offset)); +} + +typedef struct { +unsigned int Rdst:2; +unsigned int Rsrc:2; +unsigned int null:6; +unsigned int offset:11; +unsigned int null2: 4; +unsigned int cent: 3; +} fstore; + +static void store(unsigned int operand) +{ + fstore op; + COPY(op, operand); + + dinfo->fprintf_func(dinfo->stream, "ST R%d, R%d, %d \t\t\t\t\t // MEM[R%d+%d] = R%d", op.Rdst, op.Rsrc, INST_TO_ADDR(op.offset), op.Rsrc, INST_TO_ADDR(op.offset), op.Rdst); +} \ No newline at end of file From 5e66e0dc8a0efbd9b0b89114cf303b213e1a3ff2 Mon Sep 17 00:00:00 2001 From: 8785benjamin <39658811+8785benjamin@users.noreply.github.com> Date: Fri, 8 Jun 2018 22:05:52 +0200 Subject: [PATCH 4/5] Add files via upload From 733446e3186d46f8a292e5e9e153c78b82e3ad23 Mon Sep 17 00:00:00 2001 From: 8785benjamin <39658811+8785benjamin@users.noreply.github.com> Date: Fri, 8 Jun 2018 22:18:07 +0200 Subject: [PATCH 5/5] Add files via upload