diff --git a/espefuse/efuse/esp32h2/emulate_efuse_controller.py b/espefuse/efuse/esp32h2/emulate_efuse_controller.py
index e314b3058..c4c839da6 100644
--- a/espefuse/efuse/esp32h2/emulate_efuse_controller.py
+++ b/espefuse/efuse/esp32h2/emulate_efuse_controller.py
@@ -33,7 +33,7 @@ def get_minor_chip_version(self):
         return 0
 
     def get_crystal_freq(self):
-        return 40  # MHz (common for all chips)
+        return 32  # MHz
 
     def get_security_info(self):
         return {
diff --git a/espefuse/efuse/esp32h2/fields.py b/espefuse/efuse/esp32h2/fields.py
index 79630ab0c..45bd29f01 100644
--- a/espefuse/efuse/esp32h2/fields.py
+++ b/espefuse/efuse/esp32h2/fields.py
@@ -244,9 +244,10 @@ def set_efuse_timing(self):
         """Set timing registers for burning efuses"""
         # Configure clock
         apb_freq = self.get_crystal_freq()
-        if apb_freq != 40:
+        # Based on `CONFIG_SOC_XTAL_SUPPORT_32M=y` for this target from ESP-IDF configuration
+        if apb_freq != 32:
             raise esptool.FatalError(
-                "The eFuse supports only xtal=40M (xtal was %d)" % apb_freq
+                "The eFuse supports only xtal=32M (xtal was %d)" % apb_freq
             )
 
         self.update_reg(