From 15867d670d2a3d02125cf1a3f0ba92bd8053e175 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Wed, 3 Apr 2024 09:02:07 +0300
Subject: [PATCH] target/espressif: add riscv read only regs to the register
 list

---
 src/target/espressif/esp32c6.c   |  2 +-
 src/target/espressif/esp32h2.c   |  2 +-
 src/target/espressif/esp_riscv.c | 16 ++++++++++++++--
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/target/espressif/esp32c6.c b/src/target/espressif/esp32c6.c
index 74f5b307b..746873fab 100644
--- a/src/target/espressif/esp32c6.c
+++ b/src/target/espressif/esp32c6.c
@@ -125,7 +125,7 @@ static const struct esp_flash_breakpoint_ops esp32c6_flash_brp_ops = {
 
 static const char *esp32c6_existent_regs[] = {
 	"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
-	"fp", "pc", "mstatus", "misa", "mtvec", "mscratch", "mepc", "mcause", "mtval", "priv",
+	"fp", "pc", "mstatus", "misa", "mideleg", "mie", "mtvec", "mscratch", "mepc", "mcause", "mtval", "mip", "priv",
 	"s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
 	"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
 	"pmpcfg0", "pmpcfg1", "pmpcfg2", "pmpcfg3",
diff --git a/src/target/espressif/esp32h2.c b/src/target/espressif/esp32h2.c
index 3be89e08d..633c9be4f 100644
--- a/src/target/espressif/esp32h2.c
+++ b/src/target/espressif/esp32h2.c
@@ -129,7 +129,7 @@ static const struct esp_flash_breakpoint_ops esp32h2_flash_brp_ops = {
 
 static const char *esp32h2_existent_regs[] = {
 	"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
-	"fp", "pc", "mstatus", "misa", "mtvec", "mscratch", "mepc", "mcause", "mtval", "priv",
+	"fp", "pc", "mstatus", "misa", "mideleg", "mie", "mtvec", "mscratch", "mepc", "mcause", "mtval", "mip", "priv",
 	"s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
 	"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
 	"pmpcfg0", "pmpcfg1", "pmpcfg2", "pmpcfg3",
diff --git a/src/target/espressif/esp_riscv.c b/src/target/espressif/esp_riscv.c
index 0191cbfff..a93b6e284 100644
--- a/src/target/espressif/esp_riscv.c
+++ b/src/target/espressif/esp_riscv.c
@@ -188,6 +188,10 @@ static bool esp_riscv_is_bp_set_by_program(struct target *target)
 	return false;
 }
 
+static const char *esp_riscv_ro_regs[] = {
+	"mvendorid", "marchid", "mimpid", "mhartid",
+};
+
 int esp_riscv_examine(struct target *target)
 {
 	int ret = riscv_target.examine(target);
@@ -206,11 +210,19 @@ int esp_riscv_examine(struct target *target)
 	for (unsigned int i = 0; i < target->reg_cache->num_regs; i++) {
 		if (target->reg_cache->reg_list[i].exist) {
 			target->reg_cache->reg_list[i].exist = false;
+			target->reg_cache->reg_list[i].caller_save = true;
 			for (unsigned int j = 0; j < esp_riscv->existent_regs_size; j++)
 				if (!strcmp(target->reg_cache->reg_list[i].name, esp_riscv->existent_regs[j])) {
 					target->reg_cache->reg_list[i].exist = true;
 					break;
 				}
+			for (unsigned int j = 0; j < ARRAY_SIZE(esp_riscv_ro_regs); j++) {
+				if (!strcmp(target->reg_cache->reg_list[i].name, esp_riscv_ro_regs[j])) {
+					target->reg_cache->reg_list[i].exist = true;
+					target->reg_cache->reg_list[i].caller_save = false;
+					break;
+				}
+			}
 		}
 	}
 	return ERROR_OK;
@@ -582,7 +594,7 @@ int esp_riscv_start_algorithm(struct target *target,
 		struct reg *r = &target->reg_cache->reg_list[number];
 
 		algorithm_info->valid_saved_registers[r->number] = r->exist;
-		if (!r->exist)
+		if (!r->exist || !r->caller_save)
 			continue;
 
 		LOG_DEBUG("save %s", r->name);
@@ -743,7 +755,7 @@ int esp_riscv_wait_algorithm(struct target *target,
 		number <= max_saved_reg && number < target->reg_cache->num_regs; number++) {
 		struct reg *r = &target->reg_cache->reg_list[number];
 
-		if (!algorithm_info->valid_saved_registers[r->number])
+		if (!algorithm_info->valid_saved_registers[r->number] || !r->caller_save)
 			continue;
 
 		LOG_DEBUG("restore %s", r->name);