From 47af42f463a4d6049498f4602e77c16b676c8503 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 17 Jul 2024 10:36:59 +0200 Subject: [PATCH] tcl/espressif: fix tab and space alignments --- tcl/target/esp32.cfg | 29 ++++------ tcl/target/esp32c2.cfg | 108 ++++++++++++++++++------------------ tcl/target/esp32c3.cfg | 114 +++++++++++++++++++------------------- tcl/target/esp32c5.cfg | 100 ++++++++++++++++----------------- tcl/target/esp32c6.cfg | 114 +++++++++++++++++++------------------- tcl/target/esp32h2.cfg | 104 ++++++++++++++++------------------ tcl/target/esp32s2.cfg | 18 +++--- tcl/target/esp32s3.cfg | 23 +++----- tcl/target/esp_common.cfg | 24 ++++---- 9 files changed, 309 insertions(+), 325 deletions(-) diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg index aa3152e38..6d643f95f 100755 --- a/tcl/target/esp32.cfg +++ b/tcl/target/esp32.cfg @@ -5,39 +5,34 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32" -set _CPUTAPID 0x120034e5 -set _ESP_ARCH "xtensa" -set _ESP_SMP_TARGET 1 -set _ESP_SMP_BREAK 1 -set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004 - -if { [info exists ESP32_ONLYCPU] } { - echo "ESP32_ONLYCPU command will be deprecated! Use ESP_ONLYCPU instead." - set _ONLYCPU $ESP32_ONLYCPU -} +set _CHIPNAME "esp32" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004 # if not set until now, set as default dual core if { ![info exists _ONLYCPU] } { - set _ONLYCPU 3 + set _ONLYCPU 3 } set _FLASH_VOLTAGE 3.3 if { [info exists ESP32_FLASH_VOLTAGE] } { - set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE + set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE } # Set workarea address and size # Keep in mind 32KB area (0x3FFF8000-0x3FFFFFFF) is reserved for the apptrace blocks -set _WA_ADDR 0x3FFE0000 -set _WA_SIZE 0x18000 +set _WA_ADDR 0x3FFE0000 +set _WA_SIZE 0x18000 proc esp32_memprot_is_enabled { } { - return 0 + return 0 } proc esp32_soc_reset { } { - soft_reset_halt + soft_reset_halt } create_esp_target $_ESP_ARCH diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg index c02f3343a..1088e7e96 100644 --- a/tcl/target/esp32c2.cfg +++ b/tcl/target/esp32c2.cfg @@ -5,13 +5,13 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32c2" -set _CPUTAPID 0x0000cc25 -set _ESP_ARCH "riscv" -set _ONLYCPU 1 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 0 -set _ESP_EFUSE_MAC_ADDR_REG 0x60008840 +set _CHIPNAME "esp32c2" +set _CPUTAPID 0x0000cc25 +set _ESP_ARCH "riscv" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 0 +set _ESP_EFUSE_MAC_ADDR_REG 0x60008840 # Set workarea address and size # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB): @@ -19,56 +19,56 @@ set _ESP_EFUSE_MAC_ADDR_REG 0x60008840 # - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs # TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data. # In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one. -set _WA_ADDR 0x3FCA0000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x3FCA0000 +set _WA_SIZE 0x24000 # Target specific functions should be implemented for each riscv chips. proc esp32c2_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. - if { [string compare [command mode] config] == 0 } { - return - } - - # Timer Group 0 WDT - mww 0x6001f064 0x50D83AA1 - mww 0x6001F048 0 - # RTC WDT - mww 0x6000809C 0x50D83AA1 - mww 0x60008084 0 - # SWD - mww 0x600080A4 0x8F1D312A - mww 0x600080A0 0x84B00000 + if { [string compare [command mode] config] == 0 } { + return + } + + # Timer Group 0 WDT + mww 0x6001f064 0x50D83AA1 + mww 0x6001F048 0 + # RTC WDT + mww 0x6000809C 0x50D83AA1 + mww 0x60008084 0 + # SWD + mww 0x600080A4 0x8F1D312A + mww 0x600080A0 0x84B00000 } proc esp32c2_soc_reset { } { global _RISCV_DMCONTROL - # This procedure does "digital system reset", i.e. resets - # all the peripherals except for the RTC block. - # It is called from reset-assert-post target event callback, - # after assert_reset procedure was called. - # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST, - # temporarily take it out of reset. Save the dmcontrol state before - # doing so. - riscv dmi_write $_RISCV_DMCONTROL 0x80000001 - # Trigger the reset - mww 0x60008000 0x9c00a000 - # Workaround for stuck in cpu start during calibration. - # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration - mww 0x6001F068 0 - # Wait for the reset to happen - sleep 10 - poll - # Disable the watchdogs again - esp32c2_wdt_disable - - # Here debugger reads allresumeack and allhalted bits as set (0x330a2) - # We will clean allhalted state by resuming the core. - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - - # Put the hart back into reset state. Note that we need to keep haltreq set. - riscv dmi_write $_RISCV_DMCONTROL 0x80000003 + # This procedure does "digital system reset", i.e. resets + # all the peripherals except for the RTC block. + # It is called from reset-assert-post target event callback, + # after assert_reset procedure was called. + # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST, + # temporarily take it out of reset. Save the dmcontrol state before + # doing so. + riscv dmi_write $_RISCV_DMCONTROL 0x80000001 + # Trigger the reset + mww 0x60008000 0x9c00a000 + # Workaround for stuck in cpu start during calibration. + # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration + mww 0x6001F068 0 + # Wait for the reset to happen + sleep 10 + poll + # Disable the watchdogs again + esp32c2_wdt_disable + + # Here debugger reads allresumeack and allhalted bits as set (0x330a2) + # We will clean allhalted state by resuming the core. + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + + # Put the hart back into reset state. Note that we need to keep haltreq set. + riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } proc esp32c2_memprot_is_enabled { } { @@ -96,26 +96,26 @@ proc esp32c2_memprot_is_enabled { } { riscv dmi_write $_RISCV_ABS_CMD 0x2203b3 set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}] - set IRAM_LOW 0x40380000 - set IRAM_HIGH 0x403C0000 - set DRAM_LOW 0x3FCA0000 - set DRAM_HIGH 0x3FCE0000 + set IRAM_LOW 0x40380000 + set IRAM_HIGH 0x403C0000 + set DRAM_LOW 0x3FCA0000 + set DRAM_HIGH 0x3FCE0000 set PMP_RWX 0x07 - set PMP_RW 0x03 + set PMP_RW 0x03 # The lock bit remains unset during the execution of the 2nd stage bootloader. # Thus we do not perform a lock bit check for IRAM and DRAM regions. # Check OpenOCD can write and execute from IRAM. if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} { - if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} { + if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} { return 1 } } # Check OpenOCD can read/write entire DRAM region. if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} { - if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} { + if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} { return 1 } } diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg index 455186053..f95ca7dde 100644 --- a/tcl/target/esp32c3.cfg +++ b/tcl/target/esp32c3.cfg @@ -5,13 +5,13 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32c3" -set _CPUTAPID 0x00005c25 -set _ESP_ARCH "riscv" -set _ONLYCPU 1 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 0 -set _ESP_EFUSE_MAC_ADDR_REG 0x60008844 +set _CHIPNAME "esp32c3" +set _CPUTAPID 0x00005c25 +set _ESP_ARCH "riscv" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 0 +set _ESP_EFUSE_MAC_ADDR_REG 0x60008844 # Set workarea address and size # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB): @@ -19,70 +19,70 @@ set _ESP_EFUSE_MAC_ADDR_REG 0x60008844 # - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs # TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data. # In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one. -set _WA_ADDR 0x3FC80000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x3FC80000 +set _WA_SIZE 0x24000 # Target specific functions should be implemented for each riscv chips. proc esp32c3_wdt_disable { } { - # Halt event can occur during config phase (before "init" is done). - # Ignore it since mww commands don't work at that time. - if { [string compare [command mode] config] == 0 } { - return - } + # Halt event can occur during config phase (before "init" is done). + # Ignore it since mww commands don't work at that time. + if { [string compare [command mode] config] == 0 } { + return + } - # Timer Group 0 & 1 WDTs - mww 0x6001f064 0x50D83AA1 - mww 0x6001F048 0 - mww 0x60020064 0x50D83AA1 - mww 0x60020048 0 - # RTC WDT - mww 0x600080a8 0x50D83AA1 - mww 0x60008090 0 - # SWD - mww 0x600080b0 0x8F1D312A - mww 0x600080ac 0x84B00000 + # Timer Group 0 & 1 WDTs + mww 0x6001f064 0x50D83AA1 + mww 0x6001F048 0 + mww 0x60020064 0x50D83AA1 + mww 0x60020048 0 + # RTC WDT + mww 0x600080a8 0x50D83AA1 + mww 0x60008090 0 + # SWD + mww 0x600080b0 0x8F1D312A + mww 0x600080ac 0x84B00000 } proc esp32c3_soc_reset { } { global _RISCV_DMCONTROL - # This procedure does "digital system reset", i.e. resets - # all the peripherals except for the RTC block. - # It is called from reset-assert-post target event callback, - # after assert_reset procedure was called. - # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST, - # temporarily take it out of reset. Save the dmcontrol state before - # doing so. - riscv dmi_write $_RISCV_DMCONTROL 0x80000001 - # Trigger the reset - mww 0x60008000 0x9c00a000 - # Workaround for stuck in cpu start during calibration. - # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration - mww 0x6001F068 0 - # Wait for the reset to happen - sleep 10 - poll - # Disable the watchdogs again - esp32c3_wdt_disable + # This procedure does "digital system reset", i.e. resets + # all the peripherals except for the RTC block. + # It is called from reset-assert-post target event callback, + # after assert_reset procedure was called. + # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST, + # temporarily take it out of reset. Save the dmcontrol state before + # doing so. + riscv dmi_write $_RISCV_DMCONTROL 0x80000001 + # Trigger the reset + mww 0x60008000 0x9c00a000 + # Workaround for stuck in cpu start during calibration. + # By writing zero to TIMG_RTCCALICFG_REG, we are disabling calibration + mww 0x6001F068 0 + # Wait for the reset to happen + sleep 10 + poll + # Disable the watchdogs again + esp32c3_wdt_disable - # Here debugger reads allresumeack and allhalted bits as set (0x330a2) - # We will clean allhalted state by resuming the core. - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads allresumeack and allhalted bits as set (0x330a2) + # We will clean allhalted state by resuming the core. + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Put the hart back into reset state. Note that we need to keep haltreq set. - riscv dmi_write $_RISCV_DMCONTROL 0x80000003 + # Put the hart back into reset state. Note that we need to keep haltreq set. + riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } proc esp32c3_memprot_is_enabled { } { - # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG - if { [get_mmr_bit 0x600C10A8 0] != 0 } { - return 1 - } - # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG - if { [get_mmr_bit 0x600C10C0 0] != 0 } { - return 1 - } - return 0 + # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10A8 0] != 0 } { + return 1 + } + # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10C0 0] != 0 } { + return 1 + } + return 0 } create_esp_target $_ESP_ARCH diff --git a/tcl/target/esp32c5.cfg b/tcl/target/esp32c5.cfg index caf031c44..d1f91eb1e 100644 --- a/tcl/target/esp32c5.cfg +++ b/tcl/target/esp32c5.cfg @@ -6,13 +6,13 @@ set ESP_FLASH_SIZE 0 source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32c5" -set _CPUTAPID 0x00017c25 -set _ESP_ARCH "riscv" -set _ONLYCPU 2 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 0 -set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 +set _CHIPNAME "esp32c5" +set _CPUTAPID 0x00017c25 +set _ESP_ARCH "riscv" +set _ONLYCPU 2 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 0 +set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Set workarea address and size # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB): @@ -20,63 +20,63 @@ set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs # TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data. # In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one. -set _WA_ADDR 0x40800000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x40800000 +set _WA_SIZE 0x24000 # Target specific functions should be implemented for each riscv chips. proc esp32c5_wdt_disable { } { - # Halt event can occur during config phase (before "init" is done). - # Ignore it since mww commands don't work at that time. - if { [string compare [command mode] config] == 0 } { - return - } - - # Timer Group 0 & 1 WDTs - mww 0x60008064 0x50D83AA1 - mww 0x60008048 0 - mww 0x60009064 0x50D83AA1 - mww 0x60009048 0 - # LP_WDT_RTC - mww 0x600b1c18 0x50D83AA1 - mww 0x600B1C00 0 - # LP_WDT_SWD - mww 0x600b1c20 0x50D83AA1 - mww 0x600b1c1c 0x40000000 + # Halt event can occur during config phase (before "init" is done). + # Ignore it since mww commands don't work at that time. + if { [string compare [command mode] config] == 0 } { + return + } + + # Timer Group 0 & 1 WDTs + mww 0x60008064 0x50D83AA1 + mww 0x60008048 0 + mww 0x60009064 0x50D83AA1 + mww 0x60009048 0 + # LP_WDT_RTC + mww 0x600b1c18 0x50D83AA1 + mww 0x600B1C00 0 + # LP_WDT_SWD + mww 0x600b1c20 0x50D83AA1 + mww 0x600b1c1c 0x40000000 } proc esp32c5_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 - riscv dmi_write $_RISCV_DMCONTROL 0x80000001 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 - riscv dmi_write $_RISCV_SB_DATA0 0x80000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x80000001 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 + riscv dmi_write $_RISCV_SB_DATA0 0x80000000 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 - riscv dmi_write $_RISCV_SB_DATA0 0x10000000 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 + riscv dmi_write $_RISCV_SB_DATA0 0x10000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Here debugger reads dmstatus as 0xc03a2 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads dmstatus as 0xc03a2 - # Wait for the reset to happen - sleep 10 - poll - # Here debugger reads dmstatus as 0x3a2 + # Wait for the reset to happen + sleep 10 + poll + # Here debugger reads dmstatus as 0x3a2 - # Disable the watchdogs again - esp32c5_wdt_disable + # Disable the watchdogs again + esp32c5_wdt_disable - # Here debugger reads anyhalted and allhalted bits as set (0x3a2) - # We will clean allhalted state by resuming the core. - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads anyhalted and allhalted bits as set (0x3a2) + # We will clean allhalted state by resuming the core. + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Put the hart back into reset state. Note that we need to keep haltreq set. - riscv dmi_write $_RISCV_DMCONTROL 0x80000003 + # Put the hart back into reset state. Note that we need to keep haltreq set. + riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } proc esp32c5_memprot_is_enabled { } { diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg index 6fde65321..03a23e634 100644 --- a/tcl/target/esp32c6.cfg +++ b/tcl/target/esp32c6.cfg @@ -5,13 +5,13 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32c6" -set _CPUTAPID 0x0000dc25 -set _ESP_ARCH "riscv" -set _ONLYCPU 1 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 0 -set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 +set _CHIPNAME "esp32c6" +set _CPUTAPID 0x0000dc25 +set _ESP_ARCH "riscv" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 0 +set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Set workarea address and size # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB): @@ -19,70 +19,70 @@ set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs # TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data. # In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one. -set _WA_ADDR 0x40800000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x40800000 +set _WA_SIZE 0x24000 # Target specific functions should be implemented for each riscv chips. proc esp32c6_wdt_disable { } { - # Halt event can occur during config phase (before "init" is done). - # Ignore it since mww commands don't work at that time. - if { [string compare [command mode] config] == 0 } { - return - } - - # Timer Group 0 & 1 WDTs - mww 0x60008064 0x50D83AA1 - mww 0x60008048 0 - mww 0x60009064 0x50D83AA1 - mww 0x60009048 0 - # LP_WDT_RTC - mww 0x600b1c18 0x50D83AA1 - mww 0x600B1C00 0 - # LP_WDT_SWD - mww 0x600b1c20 0x50D83AA1 - mww 0x600b1c1c 0x40000000 + # Halt event can occur during config phase (before "init" is done). + # Ignore it since mww commands don't work at that time. + if { [string compare [command mode] config] == 0 } { + return + } + + # Timer Group 0 & 1 WDTs + mww 0x60008064 0x50D83AA1 + mww 0x60008048 0 + mww 0x60009064 0x50D83AA1 + mww 0x60009048 0 + # LP_WDT_RTC + mww 0x600b1c18 0x50D83AA1 + mww 0x600B1C00 0 + # LP_WDT_SWD + mww 0x600b1c20 0x50D83AA1 + mww 0x600b1c1c 0x40000000 } proc esp32c6_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 - riscv dmi_write $_RISCV_DMCONTROL 0x80000001 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 - riscv dmi_write $_RISCV_SB_DATA0 0x80000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x80000001 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 + riscv dmi_write $_RISCV_SB_DATA0 0x80000000 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 - riscv dmi_write $_RISCV_SB_DATA0 0x10000000 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 + riscv dmi_write $_RISCV_SB_DATA0 0x10000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Here debugger reads dmstatus as 0xc03a2 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads dmstatus as 0xc03a2 - # Wait for the reset to happen - sleep 10 - poll - # Here debugger reads dmstatus as 0x3a2 + # Wait for the reset to happen + sleep 10 + poll + # Here debugger reads dmstatus as 0x3a2 - # Disable the watchdogs again - esp32c6_wdt_disable + # Disable the watchdogs again + esp32c6_wdt_disable - # Here debugger reads anyhalted and allhalted bits as set (0x3a2) - # We will clean allhalted state by resuming the core. - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads anyhalted and allhalted bits as set (0x3a2) + # We will clean allhalted state by resuming the core. + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Put the hart back into reset state. Note that we need to keep haltreq set. - riscv dmi_write $_RISCV_DMCONTROL 0x80000003 + # Put the hart back into reset state. Note that we need to keep haltreq set. + riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } proc esp32c6_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 # If IRAM/DRAM split is enabled TOR address match mode is used. - # If IRAM/DRAM split is disabled NAPOT mode is used. + # If IRAM/DRAM split is disabled NAPOT mode is used. # In order to determine if the IRAM/DRAM regions are protected against RWX/RW, # it is necessary to first read the mode and then apply the appropriate method for checking. # We can understand the mode reading pmp5cfg in pmpcfg1 register. @@ -96,13 +96,13 @@ proc esp32c6_memprot_is_enabled { } { set pmp6cfg [expr {($pmpcfg1 >> (8 * 2)) & 0xFF}] set pmp7cfg [expr {($pmpcfg1 >> (8 * 3)) & 0xFF}] - set IRAM_LOW 0x40800000 - set IRAM_HIGH 0x40880000 - set DRAM_LOW 0x40800000 - set DRAM_HIGH 0x40880000 + set IRAM_LOW 0x40800000 + set IRAM_HIGH 0x40880000 + set DRAM_LOW 0x40800000 + set DRAM_HIGH 0x40880000 set PMP_RWX 0x07 - set PMP_RW 0x03 - set PMP_A [expr {($pmp5cfg >> 3) & 0x03}] + set PMP_RW 0x03 + set PMP_A [expr {($pmp5cfg >> 3) & 0x03}] if {$PMP_A == 0} { # TOR mode used to protect valid address space. diff --git a/tcl/target/esp32h2.cfg b/tcl/target/esp32h2.cfg index b7f07d66a..67c3dced0 100644 --- a/tcl/target/esp32h2.cfg +++ b/tcl/target/esp32h2.cfg @@ -5,13 +5,13 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32h2" -set _CPUTAPID 0x00010c25 -set _ESP_ARCH "riscv" -set _ONLYCPU 1 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 0 -set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 +set _CHIPNAME "esp32h2" +set _CPUTAPID 0x00010c25 +set _ESP_ARCH "riscv" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 0 +set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # Set workarea address and size # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB): @@ -19,63 +19,57 @@ set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844 # - for uncompression: 32KB for unzip buffer size + 11KB for inflator data structs # TODO: In general when up buffers are swapped apptrace copies `host->target` data from new up buffer to down buffer to free space for `target->host` data. # In case of flash writes we use apptrace transfers in one direction only. So we can avoid copying and re-use up buffer instead of down one. -set _WA_ADDR 0x40800000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x40800000 +set _WA_SIZE 0x24000 # Target specific functions should be implemented for each riscv chips. proc esp32h2_wdt_disable { } { - # Halt event can occur during config phase (before "init" is done). - # Ignore it since mww commands don't work at that time. - if { [string compare [command mode] config] == 0 } { - return - } - - # Timer Group 0 & 1 WDTs - mww 0x60009064 0x50D83AA1 - mww 0x60009048 0 - mww 0x6000A064 0x50D83AA1 - mww 0x6000A048 0 - # WDT_RTC - #mww 0x600b1c18 0x50D83AA1 - #mww 0x600B1C00 0 - # WDT_SWD - #mww 0x600b1c20 0x8F1D312A - #mww 0x600b1c1c 0x84B00000 + # Halt event can occur during config phase (before "init" is done). + # Ignore it since mww commands don't work at that time. + if { [string compare [command mode] config] == 0 } { + return + } + + # Timer Group 0 & 1 WDTs + mww 0x60009064 0x50D83AA1 + mww 0x60009048 0 + mww 0x6000A064 0x50D83AA1 + mww 0x6000A048 0 } proc esp32h2_soc_reset { } { global _RISCV_DMCONTROL _RISCV_SB_CS _RISCV_SB_ADDR0 _RISCV_SB_DATA0 - riscv dmi_write $_RISCV_DMCONTROL 0x80000001 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 - riscv dmi_write $_RISCV_SB_DATA0 0x80000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x80000001 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1034 + riscv dmi_write $_RISCV_SB_DATA0 0x80000000 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_SB_CS 0x48000 - riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 - riscv dmi_write $_RISCV_SB_DATA0 0x10000000 + riscv dmi_write $_RISCV_SB_CS 0x48000 + riscv dmi_write $_RISCV_SB_ADDR0 0x600b1038 + riscv dmi_write $_RISCV_SB_DATA0 0x10000000 - # clear dmactive to clear sbbusy otherwise debug module gets stuck - riscv dmi_write $_RISCV_DMCONTROL 0 - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Here debugger reads dmstatus as 0xc03a2 + # clear dmactive to clear sbbusy otherwise debug module gets stuck + riscv dmi_write $_RISCV_DMCONTROL 0 + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads dmstatus as 0xc03a2 - # Wait for the reset to happen - sleep 10 - poll - # Here debugger reads dmstatus as 0x3a2 + # Wait for the reset to happen + sleep 10 + poll + # Here debugger reads dmstatus as 0x3a2 - # Disable the watchdogs again - esp32h2_wdt_disable + # Disable the watchdogs again + esp32h2_wdt_disable - # Here debugger reads anyhalted and allhalted bits as set (0x3a2) - # We will clean allhalted state by resuming the core. - riscv dmi_write $_RISCV_DMCONTROL 0x40000001 + # Here debugger reads anyhalted and allhalted bits as set (0x3a2) + # We will clean allhalted state by resuming the core. + riscv dmi_write $_RISCV_DMCONTROL 0x40000001 - # Put the hart back into reset state. Note that we need to keep haltreq set. - riscv dmi_write $_RISCV_DMCONTROL 0x80000003 + # Put the hart back into reset state. Note that we need to keep haltreq set. + riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } proc esp32h2_memprot_is_enabled { } { @@ -99,13 +93,13 @@ proc esp32h2_memprot_is_enabled { } { riscv dmi_write $_RISCV_ABS_CMD 0x2203b7 set pmpaddr7 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}] - set IRAM_LOW 0x40800000 - set IRAM_HIGH 0x40850000 - set DRAM_LOW 0x40800000 - set DRAM_HIGH 0x40850000 + set IRAM_LOW 0x40800000 + set IRAM_HIGH 0x40850000 + set DRAM_LOW 0x40800000 + set DRAM_HIGH 0x40850000 set PMP_RWX 0x07 - set PMP_RW 0x03 + set PMP_RW 0x03 # The lock bit remains unset during the execution of the 2nd stage bootloader. # Thus, we do not perform a lock bit check for IRAM and DRAM regions. diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg index 880e328a2..a1b89febf 100644 --- a/tcl/target/esp32s2.cfg +++ b/tcl/target/esp32s2.cfg @@ -5,18 +5,18 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32s2" -set _CPUTAPID 0x120034e5 -set _ESP_ARCH "xtensa" -set _ONLYCPU 1 -set _ESP_SMP_TARGET 0 -set _ESP_SMP_BREAK 1 -set _ESP_EFUSE_MAC_ADDR_REG 0x3f41A004 +set _CHIPNAME "esp32s2" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3f41A004 # Set workarea address and size # Keep in mind 32KB area (0x3FFF4000-0x3FFFBFFF) is reserved for the apptrace blocks -set _WA_ADDR 0x3FFB8000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x3FFB8000 +set _WA_SIZE 0x24000 proc esp32s2_memprot_is_enabled { } { # IRAM0, DPORT_PMS_PRO_IRAM0_0_REG diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg index 36730da09..4441b36e9 100644 --- a/tcl/target/esp32s3.cfg +++ b/tcl/target/esp32s3.cfg @@ -5,27 +5,22 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "esp32s3" -set _CPUTAPID 0x120034e5 -set _ESP_ARCH "xtensa" -set _ESP_SMP_TARGET 1 -set _ESP_SMP_BREAK 1 -set _ESP_EFUSE_MAC_ADDR_REG 0x60007044 - -if { [info exists ESP32_S3_ONLYCPU] } { - echo "ESP32_S3_ONLYCPU command will be deprecated! Use ESP_ONLYCPU instead." - set _ONLYCPU $ESP32_S3_ONLYCPU -} +set _CHIPNAME "esp32s3" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x60007044 # if not set until now, set as default dual core if { ![info exists _ONLYCPU] } { - set _ONLYCPU 3 + set _ONLYCPU 0x03 } # Set workarea address and size # Keep in mind 2x16KB area (0x3FCD0000..0x3FCD3FFF and 0x3FCE0000..0x3FCE3FFF) is reserved for the apptrace blocks -set _WA_ADDR 0x3FC9C000 -set _WA_SIZE 0x24000 +set _WA_ADDR 0x3FC9C000 +set _WA_SIZE 0x24000 proc esp32s3_memprot_is_enabled { } { # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg index 9fa570f2a..a884fd33b 100644 --- a/tcl/target/esp_common.cfg +++ b/tcl/target/esp_common.cfg @@ -55,21 +55,21 @@ proc set_esp_common_variables { } { # For now we support dual core at most. if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0 } { - set _TARGETNAME_0 $_CHIPNAME - set _CPUNAME_0 cpu - set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0 + set _TARGETNAME_0 $_CHIPNAME + set _CPUNAME_0 cpu + set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0 } else { - set _CPUNAME_0 cpu0 - set _CPUNAME_1 cpu1 - set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0 - set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1 - set _TAPNAME_0 $_TARGETNAME_0 - set _TAPNAME_1 $_TARGETNAME_1 + set _CPUNAME_0 cpu0 + set _CPUNAME_1 cpu1 + set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0 + set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1 + set _TAPNAME_0 $_TARGETNAME_0 + set _TAPNAME_1 $_TARGETNAME_1 } - set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable" - set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset" - set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled" + set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable" + set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset" + set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled" } proc create_esp_jtag { } {