From fb23840eab7a33249eaa23cad7bed4137055e8dd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 4 Jan 2023 01:28:11 -0800 Subject: [PATCH] Bump to scala 2.13/chisel 3.5.5/latest rocketchip --- build.sbt | 2 +- src/main/scala/DMA.scala | 9 ++++++--- src/main/scala/NIC.scala | 11 +++++++---- src/main/scala/NICTests.scala | 18 ++++++++++++------ 4 files changed, 26 insertions(+), 14 deletions(-) diff --git a/build.sbt b/build.sbt index 3266950..9248042 100644 --- a/build.sbt +++ b/build.sbt @@ -4,4 +4,4 @@ version := "1.0" name := "icenet" -scalaVersion := "2.12.10" +scalaVersion := "2.13.10" diff --git a/src/main/scala/DMA.scala b/src/main/scala/DMA.scala index d2a859a..b71cd5f 100644 --- a/src/main/scala/DMA.scala +++ b/src/main/scala/DMA.scala @@ -19,7 +19,8 @@ class StreamReader(nXacts: Int, outFlits: Int, maxBytes: Int) val core = LazyModule(new StreamReaderCore(nXacts, outFlits, maxBytes)) val node = core.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val dataBits = core.module.dataBits val io = IO(new Bundle { @@ -46,7 +47,8 @@ class StreamReaderCore(nXacts: Int, outFlits: Int, maxBytes: Int) val node = TLHelper.makeClientNode( name = "stream-reader", sourceId = IdRange(0, nXacts)) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val (tl, edge) = node.out(0) val dataBits = tl.params.dataBits val beatBytes = dataBits / 8 @@ -182,7 +184,8 @@ class StreamWriter(nXacts: Int, maxBytes: Int) val node = TLHelper.makeClientNode( name = "stream-writer", sourceId = IdRange(0, nXacts)) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val (tl, edge) = node.out(0) val dataBits = tl.params.dataBits val beatBytes = dataBits / 8 diff --git a/src/main/scala/NIC.scala b/src/main/scala/NIC.scala index f6df53d..374ad2a 100644 --- a/src/main/scala/NIC.scala +++ b/src/main/scala/NIC.scala @@ -179,7 +179,8 @@ class IceNicSendPath(nInputTaps: Int = 0)(implicit p: Parameters) nMemXacts, outBufFlits, maxAcquireBytes)) val node = reader.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val send = Flipped(new IceNicSendIO) val tap = Flipped(Vec(nInputTaps, Decoupled(new StreamChannel(NET_IF_WIDTH)))) @@ -246,7 +247,8 @@ class IceNicWriter(implicit p: Parameters) extends NICLazyModule { val writer = LazyModule(new StreamWriter(nMemXacts, maxAcquireBytes)) val node = writer.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) val in = Flipped(Decoupled(new StreamChannel(NET_IF_WIDTH))) @@ -287,7 +289,7 @@ class IceNicRecvPath(val tapFuncs: Seq[EthernetHeader => Bool] = Nil) lazy val module = new IceNicRecvPathModule(this) } -class IceNicRecvPathModule(outer: IceNicRecvPath) +class IceNicRecvPathModule(val outer: IceNicRecvPath) extends LazyModuleImp(outer) with HasNICParameters { val io = IO(new Bundle { val recv = Flipped(new IceNicRecvIO) @@ -433,7 +435,8 @@ class IceNIC(address: BigInt, beatBytes: Int = 8, dmanode := TLWidthWidget(NET_IF_BYTES) := sendPath.node dmanode := TLWidthWidget(NET_IF_BYTES) := recvPath.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ext = new NICIO val tapOut = Vec(tapOutFuncs.length, Decoupled(new StreamChannel(NET_IF_WIDTH))) diff --git a/src/main/scala/NICTests.scala b/src/main/scala/NICTests.scala index f49f182..1beb0ed 100644 --- a/src/main/scala/NICTests.scala +++ b/src/main/scala/NICTests.scala @@ -19,7 +19,8 @@ class IceNicTestSendDriver( val node = TLHelper.makeClientNode( name = "test-send-driver", sourceId = IdRange(0, 1)) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO { val send = new IceNicSendIO }) @@ -111,7 +112,8 @@ class IceNicTestRecvDriver(recvReqs: Seq[Int], recvData: Seq[BigInt]) val node = TLHelper.makeClientNode( name = "test-recv-driver", sourceId = IdRange(0, 1)) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO { val recv = new IceNicRecvIO }) @@ -209,7 +211,8 @@ class IceNicRecvTest(implicit p: Parameters) extends NICLazyModule { mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) := TLHelper.latency(MEM_LATENCY, xbar.node) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO) val gen = Module(new PacketGen(recvLens, testData)) @@ -260,7 +263,8 @@ class IceNicSendTest(implicit p: Parameters) extends LazyModule { val RLIMIT_PERIOD = 0 val RLIMIT_SIZE = 8 - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO) val sendPathIO = sendPath.module.io @@ -330,7 +334,8 @@ class IceNicTest(implicit p: Parameters) extends NICLazyModule { mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) := TLHelper.latency(MEM_LATENCY, xbar.node) - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO) sendPath.module.io.send <> sendDriver.module.io.send @@ -478,7 +483,8 @@ class MisalignedTest(implicit p: Parameters) extends NICLazyModule { mem.node := TLFragmenter(NET_IF_BYTES, maxAcquireBytes) := TLBuffer() := xbar.node - lazy val module = new LazyModuleImp(this) { + lazy val module = new Impl + class Impl extends LazyModuleImp(this) { val io = IO(new Bundle with UnitTestIO) val driver = Module(new MisalignedTestDriver)