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1. BIST_IP_CORE BIST_IP_CORE Public

   Development of a SoC for testing an IP Core. The project has been developped in VHDL, using Xilinx ISE and IP Core. In order to test the correct functionalities(simulation in presence of faults and…

   VHDL 1 2

2. mats mats Public

   Controller that implements MATS March Algorithm for testing SRAM. It has been designed with generics, in order to use any single port SRAM.

   VHDL 1 1

3. DLX DLX Public

   This project consist in the design and implementation of an advanced DLX processor.

   Verilog 1

4. dissertation dissertation Public

   Source codes

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5. micrium_os_projects micrium_os_projects Public

   Projects developped during lab sessions.

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6. embeddedlinux embeddedlinux Public

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