ARCv3: mm: initial bits for MMUv6

vineetgarc · Sergey Matyukevich · commit 266c85f171f9 · 2022-02-21T12:24:21.000+03:00
TODO From squashed fixups: _PAGE_KERNEL created from scratch (iso _PAGE_BASE based) to avoid clearing multiple bits With this change, the static kernel image (code/data) which in older MMUs used to be unstranslated is now translated using an "Identity Mapping". It still crashes later when handling kernel vmalloc translations. - This is the commit message #2: ARCv3: mm: retain AF bit to avoid Access Fault exceptions Signed-off-by: Vineet Gupta <vgupta@synopsys.com> - This is the commit message #3: ARCv3: mm: fix pte_modify() not clearing exec related bits: _PAGE_NOTEXEC_U This showed up a LTP mprotect04 looping on same ProtV fault when trying to exeute self-modifying code after an mprotect(PROT_EXEC) pte_modify() needs to clear out existing access/permission bits and set the ones per mprotect(), while leaving the rest of pte bits intact. The old code used a mask to "keep" existing bits and supposedly cleared the rest (since it used PAGE_MASK which cleared everything). However in ARC64, PAGE_MASK misses the high bits NXU and NXK. So invert the mask strategy - clear out everything not needed explicitly and rely on newprot to DTRT. Implementation wise we are clearing AP.RO and AP.UK so it would seem that we are making them read-write and user-n-kernel but that is just an intermeduate step as OR with newprot brings in any '1' bits - so __P001 will reinstate AP.RO thus DTRT. This is just an implementation detail worth noting here. - This is the commit message #4: ARCv3: mm: Initialize MMUv6 registers - MMU_TTBC with T0SZ/T1SZ (ATM kernel linked under 4GB so uses RTP0) - MMU_MEM_ATTR with 3 attributes: normal, uncached, volatile - MMU_CTRL set to enable MMU Signed-off-by: Vineet Gupta <vgupta@synopsys.com> - This is the commit message #5: ARC: Force to use correct MMUv6 version Some tools doesn't work properly when mmu version is set to 6. We can catch it early in Linux and fail to boot, since MMU version is changed to 16 in HW for a long time now. Signed-off-by: Vladimir Isaev <isaev@synopsys.com>
diff --git a/arch/arc/include/asm/mmu-arcv2.h b/arch/arc/include/asm/mmu-arcv2.h
@@ -12,8 +12,6 @@
 /*
  * TLB Management regs
  */
-#define ARC_REG_MMU_BCR		0x06f
-
 #ifdef CONFIG_ARC_MMU_V3
 #define ARC_REG_TLBPD0		0x405
 #define ARC_REG_TLBPD1		0x406
diff --git a/arch/arc/include/asm/mmu-arcv3.h b/arch/arc/include/asm/mmu-arcv3.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * MMUv6 hardware page walked
+ * This file contains the TLB access registers and commands
+ */
+
+#ifndef _ASM_ARC_MMUV6_H
+#define _ASM_ARC_MMUV6_H
+
+#define ARC_REG_MMU_CTRL	0x468
+#define ARC_REG_MMU_RTP0	0x460
+#define ARC_REG_MMU_RTP1	0x462
+#define ARC_REG_MMU_TTBC	0x469
+#define ARC_REG_MMU_FAULT_STS	0x46b
+#define ARC_REG_MMU_MEM_ATTR	0x46a
+
+#define ARC_REG_MMU_TLB_CMD	0x465
+#define ARC_REG_MMU_TLB_DATA0	0x466
+#define ARC_REG_MMU_TLB_DATA1	0x467
+
+#ifndef __ASSEMBLY__
+
+extern void mmu_setup_asid(struct mm_struct *mm, unsigned long asid);
+
+static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd)
+{
+	/*
+	 * Only called by switch_mm() which apriori calls get_new_mmu_context()
+	 * which unconditionally calls mmu_setup_asid() to set the ASID
+	 * Since on this MMU both ASID and pgd are in same register, we program
+	 * both there and do nothing here.
+	 */
+}
+
+#endif
+
+#endif
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_ARC_MMU_H
 #define _ASM_ARC_MMU_H
 
+#define ARC_REG_MMU_BCR		0x06f
+
 #ifndef __ASSEMBLY__
 
 #include <linux/threads.h>	/* NR_CPUS */
@@ -16,6 +18,10 @@ typedef struct {
 
 #endif
 
+#ifdef CONFIG_ARC_MMU_V6
+#include <asm/mmu-arcv3.h>
+#else
 #include <asm/mmu-arcv2.h>
+#endif
 
 #endif
diff --git a/arch/arc/include/asm/pgtable-bits-arcv3.h b/arch/arc/include/asm/pgtable-bits-arcv3.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Synopsys, Inc. (www.synopsys.com)
+ */
+
+
+#ifndef _ASM_ARC_PGTABLE_BITS_ARCV3_H
+#define _ASM_ARC_PGTABLE_BITS_ARCV3_H
+
+#include <linux/sizes.h>
+
+#define _PAGE_VALID		(_UL(1) <<  0)
+#define _PAGE_LINK		(_UL(1) <<  1)
+#define _PAGE_MEMATTR_MASK	(_UL(7) <<  2)
+#define _PAGE_MEMATTR(idx)	((idx) << 2)
+
+/* PAGE_USER is only relevant for data r/w accesses  */
+#define _PAGE_AP_U_N_K		(_UL(1) <<  6)  /* 1: User + Kernel, 0: Kernel only) */
+#define _PAGE_AP_READONLY	(_UL(1) <<  7)  /* 1: Read only, 0: Read + Write) */
+
+#define __SHR_NONE		0
+#define __SHR_OUTER		2
+#define __SHR_INNER		3
+
+#define _PAGE_SHARED_NONE	(_UL(__SHR_NONE)  <<  8)
+#define _PAGE_SHARED_OUTER	(_UL(__SHR_OUTER) <<  8)  /* Outer Shareable */
+#define _PAGE_SHARED_INNER	(_UL(__SHR_INNER) <<  8)  /* Inner Shareable */
+
+#define _PAGE_ACCESSED		(_UL(1) << 10)  /* software managed, exception if clear */
+#define _PAGE_NOTGLOBAL		(_UL(1) << 11)  /* ASID */
+
+#define _PAGE_DIRTY		(_UL(1) << 51)  /* software managed */
+#define _PAGE_NOTEXEC_K		(_UL(1) << 53)  /* Execute User */
+#define _PAGE_NOTEXEC_U		(_UL(1) << 54)  /* Execute Kernel */
+
+#define _PAGE_SPECIAL		(_UL(1) << 55)
+
+/* TBD: revisit if this needs to be standalone for PROT_NONE */
+#define _PAGE_PRESENT		_PAGE_VALID
+
+/*
+ * PAGE_LINK indicates to hw walker to keep going down.
+ *  - Set for all intermediate Table Descriptors (pgd, pud, pmd)
+ *  - Set for last level Table descriptor (ptr) pointing to 4KB page frame
+ *  - Not set for "Block descriptors", where intermediate levels point to
+ *    bigger page frames.
+ */
+
+#define _PAGE_TABLE		(_PAGE_VALID | _PAGE_LINK)
+#define _PAGE_BLOCK		_PAGE_VALID
+
+
+#define MEMATTR_NORMAL		0x69
+#define MEMATTR_UNCACHED	0x01
+#define MEMATTR_VOLATILE	0x00 /* Uncached + No Early Write Ack + Strict Ordering */
+
+#define MEMATTR_IDX_NORMAL	0
+#define MEMATTR_IDX_UNCACHED	1
+#define MEMATTR_IDX_VOLATILE	2
+
+/* Read is always set since AP is specified as RO; !RO == R+W */
+#define _PAGE_BASE	(_PAGE_VALID        | _PAGE_LINK      |	\
+			 _PAGE_AP_READONLY  | 			\
+			 _PAGE_NOTEXEC_U    | _PAGE_NOTEXEC_K |	\
+			 _PAGE_AP_U_N_K     | _PAGE_NOTGLOBAL |	\
+			 _PAGE_ACCESSED     |			\
+			 _PAGE_SHARED_INNER |			\
+			 _PAGE_MEMATTR(MEMATTR_IDX_NORMAL))
+
+/* Exec implies Read since Read is always set */
+#define _PAGE_RW	(_PAGE_BASE & ~_PAGE_AP_READONLY)
+#define _PAGE_RX	(_PAGE_BASE & ~_PAGE_NOTEXEC_U)
+#define _PAGE_RWX	(_PAGE_BASE & ~_PAGE_AP_READONLY  & ~_PAGE_NOTEXEC_U)
+
+/* TBD: kernel is RWX by default, split it to code/data */
+#define _PAGE_KERNEL	(_PAGE_VALID        |			\
+			 /* writable */				\
+			 _PAGE_NOTEXEC_U    | 	/* exec k */	\
+			 /* AP kernel only  |      global */	\
+			 _PAGE_ACCESSED     |			\
+			 _PAGE_SHARED_INNER |			\
+			 _PAGE_MEMATTR(MEMATTR_IDX_NORMAL))
+
+#define PAGE_NONE	__pgprot(_PAGE_BASE)	/* TBD */
+#define PAGE_TABLE	__pgprot(_PAGE_TABLE)
+#define PAGE_BLOCK	__pgprot(_PAGE_BLOCK)
+#define PAGE_KERNEL	__pgprot(_PAGE_KERNEL)
+
+#define PAGE_R		__pgprot(_PAGE_BASE)
+#define PAGE_RW		__pgprot(_PAGE_RW)
+#define PAGE_RX		__pgprot(_PAGE_RX)
+#define PAGE_RWX	__pgprot(_PAGE_RWX)
+
+	/* xwr */
+#define __P000		PAGE_NONE
+#define __P001		PAGE_R
+#define __P010		PAGE_R
+#define __P011		PAGE_R
+#define __P100		PAGE_RX
+#define __P101		PAGE_RX
+#define __P110		PAGE_RX
+#define __P111		PAGE_RX
+
+#define __S000		PAGE_NONE
+#define __S001		PAGE_R
+#define __S010		PAGE_RW
+#define __S011		PAGE_RW
+#define __S100		PAGE_RX
+#define __S101		PAGE_RX
+#define __S110		PAGE_RWX
+#define __S111		PAGE_RWX
+
+#ifndef __ASSEMBLY__
+
+#define pgprot_noncached(prot)	__pgprot((pgprot_val(prot) & ~_PAGE_MEMATTR_MASK) | \
+					  _PAGE_MEMATTR(MEMATTR_IDX_UNCACHED))
+
+#define pte_write(pte)		(!(pte_val(pte) & _PAGE_AP_READONLY))
+#define pte_dirty(pte)		(pte_val(pte) & _PAGE_DIRTY)
+#define pte_young(pte)		(pte_val(pte) & _PAGE_ACCESSED)
+#define pte_special(pte) 	(pte_val(pte) & _PAGE_SPECIAL)
+
+#define PTE_BIT_FUNC(fn, op) \
+	static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+PTE_BIT_FUNC(wrprotect,	|=  (_PAGE_AP_READONLY));
+PTE_BIT_FUNC(mkwrite,	&= ~(_PAGE_AP_READONLY));
+PTE_BIT_FUNC(mkclean,	&= ~(_PAGE_DIRTY));
+PTE_BIT_FUNC(mkdirty,	|=  (_PAGE_DIRTY));
+/* Accessed bit is always set */
+PTE_BIT_FUNC(mkold,	|=  (_PAGE_ACCESSED));
+PTE_BIT_FUNC(mkyoung,	|=  (_PAGE_ACCESSED));
+PTE_BIT_FUNC(mkspecial,	|=  (_PAGE_SPECIAL));
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+	const unsigned long mask = _PAGE_VALID       |
+				   _PAGE_NOTEXEC_K   | _PAGE_NOTEXEC_U |
+				   _PAGE_AP_READONLY | _PAGE_AP_U_N_K;
+
+	return __pte((pte_val(pte) & ~mask) | pgprot_val(newprot));
+}
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	set_pte(ptep, pteval);
+}
+
+/*
+ * Encode and decode a swap entry
+ *
+ * Format of swap PTE:
+ *	bits 0-1:	_PAGE_VALID (must be zero)
+ *	bits 2-7:	swap type
+ *	bits 8-57:	swap offset
+ *	bit  58:	PROT_NONE (must be zero)
+ *
+ * Note: swap bits needed even if !CONFIG_SWAP
+ */
+#define __SWP_TYPE_SHIFT	2
+#define __SWP_TYPE_BITS		6
+#define __SWP_OFFSET_BITS	50
+#define __SWP_TYPE_MASK		((1UL << __SWP_TYPE_BITS) - 1)
+#define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
+#define __SWP_OFFSET_MASK	((1UL << __SWP_OFFSET_BITS) - 1)
+
+#define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
+#define __swp_offset(x)		(((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
+
+#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(swp)	((pte_t) { (swp).val })
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
+		      pte_t *ptep);
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
@@ -9,7 +9,13 @@
 #include <linux/bits.h>
 
 #include <asm/pgtable-levels.h>
+
+#ifndef CONFIG_ARC_MMU_V6
 #include <asm/pgtable-bits-arcv2.h>
+#else
+#include <asm/pgtable-bits-arcv3.h>
+#endif
+
 #include <asm/page.h>
 #include <asm/mmu.h>
 
diff --git a/arch/arc/mm/tlb-arcv3.c b/arch/arc/mm/tlb-arcv3.c
@@ -16,26 +16,31 @@ static struct cpuinfo_arc_mmu {
 
 int arc_mmu_mumbojumbo(int c, char *buf, int len)
 {
+	const unsigned int mmu_version = 0x10;
 	unsigned int lookups, pg_sz_k, ntlb, u_dtlb, u_itlb;
 	char *variant_nm[] = { "MMU32", "MMU48", "MMU52" };
 	struct bcr_mmu_6 mmu6;
-	int n= 0;
+	int n = 0;
 
 	READ_BCR(ARC_REG_MMU_BCR, mmu6);
-	if (!mmu6.ver)
-		return n;
-
-	if (mmu6.variant == 0) {	/* MMUv32 */
-		lookups = 3;
-		pg_sz_k = 4;
+	if (mmu6.ver != mmu_version) {
+		panic("Bad version of MMUv6 %#x (expected %#x)\n",
+		      mmu6.ver, mmu_version);
+		return 0;
+	} else if (!mmu6.ver) {
+		panic("Only MMU48 supported currently\n");
+		return 0;
 	}
 
+	lookups = 4;	/* 4 levels */
+	pg_sz_k = 4;	/* 4KB */
+
 	u_dtlb = 2 << mmu6.u_dtlb;  /* 8, 16 */
 	u_itlb = 2 << mmu6.u_itlb;  /* 4, 8, 16 */
 	ntlb = 256 << mmu6.n_tlb;    /* Fixed 4w */
 
 	n += scnprintf(buf + n, len - n,
-		      "MMU [v%x] \t\t: %s hwalk %d levels, %dk PAGE, JTLB %d uD/I %d/%d\n",
+		      "MMU [v%x]\t: %s hwalk %d levels, %dk PAGE, JTLB %d uD/I %d/%d\n",
 		       mmu6.ver, variant_nm[mmu6.variant], lookups,
 		       pg_sz_k, ntlb, u_dtlb, u_itlb);
 
@@ -46,9 +51,40 @@ int arc_mmu_mumbojumbo(int c, char *buf, int len)
 
 void arc_mmu_init(void)
 {
-	return;
+	struct mmu_ttbc {
+		u32 t0sz:5, t0sh:2, t0c:1, res0:7, a1:1,
+		    t1sz:5, t1sh:2, t1c:1, res1:8;
+	} ttbc;
+
+	struct mmu_mem_attr {
+		u8 attr[8];
+	} memattr;
+
 	if (mmuinfo.pg_sz_k != TO_KB(PAGE_SIZE))
 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
+
+	arc_paging_init();
+
+	ttbc.t0sz = 16;
+	ttbc.t1sz = 16;	/* Not relevant since kernel linked under 4GB hits T0SZ */
+	ttbc.t0sh = __SHR_INNER;
+	ttbc.t1sh = __SHR_INNER;
+	ttbc.t0c = 1;
+	ttbc.t1c = 1;
+	ttbc.a1 = 0;  /* ASID used is from MMU_RTP0 */
+
+	WRITE_AUX(ARC_REG_MMU_TTBC, ttbc);
+
+	memattr.attr[MEMATTR_IDX_NORMAL] = MEMATTR_NORMAL;
+	memattr.attr[MEMATTR_IDX_UNCACHED] = MEMATTR_UNCACHED;
+	memattr.attr[MEMATTR_IDX_VOLATILE] = MEMATTR_VOLATILE;
+
+	WRITE_AUX64(ARC_REG_MMU_MEM_ATTR, memattr);
+
+	write_aux_64(ARC_REG_MMU_RTP0, __pa(swapper_pg_dir));
+	write_aux_64(ARC_REG_MMU_RTP1, 0);	/* to catch bugs */
+
+	write_aux_reg(ARC_REG_MMU_CTRL, 0x7);
 }
 
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
@@ -57,6 +93,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 
 }
 
+noinline void mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
+{
+#ifdef CONFIG_64BIT
+	unsigned long rtp0 = (asid << 48) | __pa(mm->pgd);
+
+	BUG_ON(__pa(mm->pgd) >> 48);
+	write_aux_64(ARC_REG_MMU_RTP0, rtp0);
+
+#else
+#error "Need to implement 2 SR ops"
+#endif
+}
+
 noinline void local_flush_tlb_all(void)
 {
 }
