640 ????? 639 ????? 638 ????? 637 ????? 636 ????? 635 ????? 634 ????? 633 ????? 632 ????? 631 ????? 630 ????? 629 ????? 628 ????? 627 ????? 626 ????? 625 ????? 624 ????? 623 ????? 622 ????? 621 ????? 620 ????? 619 ????? 618 ????? 617 ????? 616 ????? 615 ????? 614 ????? 613 ????? 612 ????? 611 ????? 610 ????? 609 ????? 608 ????? 607 ????? 606 ????? 605 ????? 604 ????? 603 ????? 602 ????? 601 ????? 600 ????? 599 ????? 598 ????? 597 ????? 596 ????? 595 ????? 594 ????? 593 ????? 592 ????? 591 ????? 590 ????? 589 ????? 588 ????? 587 ????? 586 ????? 585 ????? 584 ????? 583 ????? 582 ????? 581 ????? 580 ????? 579 ????? 578 ????? 577 ????? 576 ????? 575 ????? 574 ????? 573 ????? 572 ????? 571 ????? 570 ????? 569 ????? 568 ????? 567 ????? 566 ????? 565 ????? 564 ????? 563 ????? 562 ????? 561 ????? 560 ????? 559 ????? 558 ????? 557 ????? 556 ????? 555 ????? 554 ????? 553 ????? 552 ????? 551 ????? 550 ????? 549 ????? 548 ????? 547 ????? 546 ????? 545 ????? 544 ????? 543 ????? 542 ????? 541 ????? 540 ????? 539 ????? 538 ????? 537 ????? 536 ????? 535 ????? 534 ????? 533 ????? 532 ????? 531 ????? 530 ????? 529 ????? 528 ????? 527 ????? 526 ????? 525 ????? 524 ????? 523 ????? 522 ????? 521 ????? 520 ????? 519 ????? 518 ????? 517 ????? 516 ????? 515 ????? 514 ????? 513 ????? 512 ????? 511 ????? 510 ????? 509 ????? 508 ????? 507 ????? 506 ????? 505 ????? 504 ????? 503 ????? 502 ????? 501 ????? 500 ????? 499 ????? 498 ????? 497 ????? 496 ????? 495 ????? 494 ????? 493 ????? 492 ????? 491 ????? 490 ????? 489 ????? 488 ????? 487 ????? 486 ????? 485 ????? 484 ????? 483 ????? 482 ????? 481 ????? 480 ????? 479 ????? 478 ????? 477 ????? 476 ????? 475 ????? 474 ????? 473 ????? 472 ????? 471 ????? 470 ????? 469 ????? 468 ????? 467 ????? 466 ????? 465 ????? 464 ????? 463 ????? 462 ????? 461 ????? 460 ????? 459 ????? 458 ????? 457 ????? 456 ????? 455 ????? 454 ????? 453 ????? 452 ????? 451 ????? 450 ????? 449 ????? 448 ????? 447 ????? 446 ????? 445 ????? 444 ????? 443 ????? 442 ????? 441 ????? 440 ????? 439 ????? 438 ????? 437 ????? 436 ????? 435 ????? 434 ????? 433 ????? 432 ????? 431 ????? 430 ????? 429 81530c90 ) multi_cpu_stop+0xf4 b_s 0x8153_0c76 = multi_cpu_stop+0xda 428 81530c76 multi_cpu_stop+0xda bl.d stop_machine_yield 427 81530c7a ) multi_cpu_stop+0xde mov_s %r0,%r19 426 81530b98 ) stop_machine_yield j_s [%blink] 425 81530c7c multi_cpu_stop+0xe0 ld_s %r14,[%r15,16] 424 81530c7e multi_cpu_stop+0xe2 brne %r17,%r14,0x8153_0c18 = multi_cpu_stop+0x7c 423 81530c82 multi_cpu_stop+0xe6 brlo %r14,2,0x8153_0c8a = multi_cpu_stop+0xee 422 81530c86 ) multi_cpu_stop+0xea bl touch_softlockup_watchdog 421 815317a4 touch_softlockup_watchdog and %r0,0xffff_e000,%sp 420 815317ac touch_softlockup_watchdog+0x08 mov_s %r1,0x8148_aa44 ; watchdog_report_ts 419 815317b2 touch_softlockup_watchdog+0x0e ld_s %r2,[%r0,12] 418 815317b4 touch_softlockup_watchdog+0x10 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 417 815317ba touch_softlockup_watchdog+0x16 ld.as %r0,[%r0,%r2] 416 815317be touch_softlockup_watchdog+0x1a add_s %r0,%r0,%r1 415 815317c0 touch_softlockup_watchdog+0x1c j_s.d [%blink] 414 815317c2 ) touch_softlockup_watchdog+0x1e st -1,[%r0] 413 81530c8a multi_cpu_stop+0xee bl.d rcu_momentary_dyntick_idle 412 81530c8e ) multi_cpu_stop+0xf2 mov_s %r17,%r14 411 8150c58c rcu_momentary_dyntick_idle push_s %r14 410 8150c58e rcu_momentary_dyntick_idle+0x02 push_s %blink 409 8150c590 rcu_momentary_dyntick_idle+0x04 and %r2,0xffff_e000,%sp 408 8150c598 rcu_momentary_dyntick_idle+0x0c mov_s %r1,0x8148_c680 ; rcu_data 407 8150c59e rcu_momentary_dyntick_idle+0x12 mov_s %r0,2 406 8150c5a0 rcu_momentary_dyntick_idle+0x14 ld_s %r3,[%r2,12] 405 8150c5a2 rcu_momentary_dyntick_idle+0x16 mov_s %r2,0x81d8_eb84 ; __per_cpu_offset 404 8150c5a8 rcu_momentary_dyntick_idle+0x1c add3 %r1,%r1,19 403 8150c5ac rcu_momentary_dyntick_idle+0x20 ld.as %r2,[%r2,%r3] 402 8150c5b0 rcu_momentary_dyntick_idle+0x24 add_s %r1,%r1,%r2 401 8150c5b2 rcu_momentary_dyntick_idle+0x26 bl.d rcu_dynticks_inc 400 8150c5b6 ) rcu_momentary_dyntick_idle+0x2a stb 0,[%r1] 399 81af5b28 rcu_dynticks_inc std.aw %r14,[%sp,-8] 398 81af5b2c rcu_dynticks_inc+0x04 push_s %blink 397 81af5b2e rcu_dynticks_inc+0x06 mov_s %r14,0x8148_c680 ; rcu_data 396 81af5b34 rcu_dynticks_inc+0x0c bl.d debug_smp_processor_id 395 81af5b38 ) rcu_dynticks_inc+0x10 mov_s %r15,%r0 394 81af5f18 debug_smp_processor_id mov_s %r1,0x81c0_95ec 393 81af5f1e debug_smp_processor_id+0x06 mov_s %r0,0x81c1_e28c 392 81af5f24 ) debug_smp_processor_id+0x0c b check_preemption_disabled 391 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 390 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 389 81af5e54 check_preemption_disabled+0x08 push_s %blink 388 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 387 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 386 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 385 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 384 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 383 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 382 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 381 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 380 81af5e74 check_preemption_disabled+0x28 pop_s %blink 379 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 378 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 377 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 376 81af5b3a rcu_dynticks_inc+0x12 mov_s %r1,0x81d8_eb84 ; __per_cpu_offset 375 81af5b40 rcu_dynticks_inc+0x18 add2 %r14,%r14,37 374 81af5b44 rcu_dynticks_inc+0x1c ld.as %r0,[%r1,%r0] 373 81af5b48 rcu_dynticks_inc+0x20 add_s %r14,%r14,%r0 372 81af5b4a rcu_dynticks_inc+0x22 dmb 3,0 371 81af5b4e rcu_dynticks_inc+0x26 clri %r3 370 81af5b52 rcu_dynticks_inc+0x2a dmb 3,0 369 81af5b56 rcu_dynticks_inc+0x2e mov_s %r2,0x81d6_609c ; smp_atomic_ops_lock 368 81af5b5c rcu_dynticks_inc+0x34 mov_s %r0,1 367 81af5b5e rcu_dynticks_inc+0x36 ex %r0,[%r2] 366 81af5b62 rcu_dynticks_inc+0x3a breq %r0,1,0x81af_5b5e = rcu_dynticks_inc+0x36 365 81af5b66 rcu_dynticks_inc+0x3e dmb 3,0 364 81af5b6a rcu_dynticks_inc+0x42 mov_s %r0,%r15 363 81af5b6c rcu_dynticks_inc+0x44 atld.add %r0,[%r14] 362 81af5b70 rcu_dynticks_inc+0x48 add %r0,%r0,%r15 361 81af5b74 rcu_dynticks_inc+0x4c dmb 3,0 360 81af5b78 rcu_dynticks_inc+0x50 mov_s %r1,0 359 81af5b7a rcu_dynticks_inc+0x52 ex %r1,[%r2] 358 81af5b7e rcu_dynticks_inc+0x56 dmb 3,0 357 81af5b82 rcu_dynticks_inc+0x5a seti %r3 356 81af5b86 rcu_dynticks_inc+0x5e dmb 3,0 355 81af5b8a rcu_dynticks_inc+0x62 pop_s %blink 354 81af5b8c rcu_dynticks_inc+0x64 j_s.d [%blink] 353 81af5b8e ) rcu_dynticks_inc+0x66 ldd.ab %r14,[%sp,8] 352 8150c5ba rcu_momentary_dyntick_idle+0x2e xbfu.f 0,%r0,0,1 351 8150c5be rcu_momentary_dyntick_idle+0x32 bz_s 0x8150_c5e2 = rcu_momentary_dyntick_idle+0x56 350 8150c5c0 rcu_momentary_dyntick_idle+0x34 mov %r0,%gp 349 8150c5c4 rcu_momentary_dyntick_idle+0x38 bl.d rcu_preempt_need_deferred_qs 348 8150c5c8 ) rcu_momentary_dyntick_idle+0x3c mov %r14,%gp 347 815095e0 rcu_preempt_need_deferred_qs push_s %r14 346 815095e2 rcu_preempt_need_deferred_qs+0x02 push_s %blink 345 815095e4 rcu_preempt_need_deferred_qs+0x04 mov_s %r14,%r0 344 815095e6 rcu_preempt_need_deferred_qs+0x06 mov_s %r0,0x81c1_3068 343 815095ec ) rcu_preempt_need_deferred_qs+0x0c bl __this_cpu_preempt_check 342 81af5f28 __this_cpu_preempt_check mov_s %r1,%r0 341 81af5f2a __this_cpu_preempt_check+0x02 mov_s %r0,0x81c1_e2a0 340 81af5f30 ) __this_cpu_preempt_check+0x08 b check_preemption_disabled 339 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 338 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 337 81af5e54 check_preemption_disabled+0x08 push_s %blink 336 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 335 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 334 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 333 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 332 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 331 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 330 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 329 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 328 81af5e74 check_preemption_disabled+0x28 pop_s %blink 327 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 326 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 325 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 324 815095f0 rcu_preempt_need_deferred_qs+0x10 and %r0,0xffff_e000,%sp 323 815095f8 rcu_preempt_need_deferred_qs+0x18 mov_s %r1,0x8148_c680 ; rcu_data 322 815095fe rcu_preempt_need_deferred_qs+0x1e ld_s %r2,[%r0,12] 321 81509600 rcu_preempt_need_deferred_qs+0x20 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 320 81509606 rcu_preempt_need_deferred_qs+0x26 add %r1,%r1,13 319 8150960a rcu_preempt_need_deferred_qs+0x2a ld.as %r0,[%r0,%r2] 318 8150960e rcu_preempt_need_deferred_qs+0x2e ldb_s %r0,[%r0,%r1] 317 81509610 rcu_preempt_need_deferred_qs+0x30 brnz_s %r0,0,0x8150_9618 = rcu_preempt_need_deferred_qs+0x38 316 81509612 rcu_preempt_need_deferred_qs+0x32 ld %r1,[%r14,0x2a0] 315 81509616 ) rcu_preempt_need_deferred_qs+0x36 brz_s %r1,0,0x8150_9620 = rcu_preempt_need_deferred_qs+0x40 314 81509620 rcu_preempt_need_deferred_qs+0x40 pop_s %blink 313 81509622 rcu_preempt_need_deferred_qs+0x42 j_s.d [%blink] 312 81509624 ) rcu_preempt_need_deferred_qs+0x44 pop_s %r14 311 8150c5cc rcu_momentary_dyntick_idle+0x40 brnz_s %r0,0,0x8150_c5d4 = rcu_momentary_dyntick_idle+0x48 310 8150c5ce rcu_momentary_dyntick_idle+0x42 pop_s %blink 309 8150c5d0 rcu_momentary_dyntick_idle+0x44 j_s.d [%blink] 308 8150c5d2 ) rcu_momentary_dyntick_idle+0x46 pop_s %r14 307 81530c90 ) multi_cpu_stop+0xf4 b_s 0x8153_0c76 = multi_cpu_stop+0xda 306 81530c76 multi_cpu_stop+0xda bl.d stop_machine_yield 305 81530c7a ) multi_cpu_stop+0xde mov_s %r0,%r19 304 81530b98 ) stop_machine_yield j_s [%blink] 303 81530c7c multi_cpu_stop+0xe0 ld_s %r14,[%r15,16] 302 81530c7e multi_cpu_stop+0xe2 brne %r17,%r14,0x8153_0c18 = multi_cpu_stop+0x7c 301 81530c82 multi_cpu_stop+0xe6 brlo %r14,2,0x8153_0c8a = multi_cpu_stop+0xee 300 81530c86 ) multi_cpu_stop+0xea bl touch_softlockup_watchdog 299 815317a4 touch_softlockup_watchdog and %r0,0xffff_e000,%sp 298 815317ac touch_softlockup_watchdog+0x08 mov_s %r1,0x8148_aa44 ; watchdog_report_ts 297 815317b2 touch_softlockup_watchdog+0x0e ld_s %r2,[%r0,12] 296 815317b4 touch_softlockup_watchdog+0x10 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 295 815317ba touch_softlockup_watchdog+0x16 ld.as %r0,[%r0,%r2] 294 815317be touch_softlockup_watchdog+0x1a add_s %r0,%r0,%r1 293 815317c0 touch_softlockup_watchdog+0x1c j_s.d [%blink] 292 815317c2 ) touch_softlockup_watchdog+0x1e st -1,[%r0] 291 81530c8a multi_cpu_stop+0xee bl.d rcu_momentary_dyntick_idle 290 81530c8e ) multi_cpu_stop+0xf2 mov_s %r17,%r14 289 8150c58c rcu_momentary_dyntick_idle push_s %r14 288 8150c58e rcu_momentary_dyntick_idle+0x02 push_s %blink 287 8150c590 rcu_momentary_dyntick_idle+0x04 and %r2,0xffff_e000,%sp 286 8150c598 rcu_momentary_dyntick_idle+0x0c mov_s %r1,0x8148_c680 ; rcu_data 285 8150c59e rcu_momentary_dyntick_idle+0x12 mov_s %r0,2 284 8150c5a0 rcu_momentary_dyntick_idle+0x14 ld_s %r3,[%r2,12] 283 8150c5a2 rcu_momentary_dyntick_idle+0x16 mov_s %r2,0x81d8_eb84 ; __per_cpu_offset 282 8150c5a8 rcu_momentary_dyntick_idle+0x1c add3 %r1,%r1,19 281 8150c5ac rcu_momentary_dyntick_idle+0x20 ld.as %r2,[%r2,%r3] 280 8150c5b0 rcu_momentary_dyntick_idle+0x24 add_s %r1,%r1,%r2 279 8150c5b2 rcu_momentary_dyntick_idle+0x26 bl.d rcu_dynticks_inc 278 8150c5b6 ) rcu_momentary_dyntick_idle+0x2a stb 0,[%r1] 277 81af5b28 rcu_dynticks_inc std.aw %r14,[%sp,-8] 276 81af5b2c rcu_dynticks_inc+0x04 push_s %blink 275 81af5b2e rcu_dynticks_inc+0x06 mov_s %r14,0x8148_c680 ; rcu_data 274 81af5b34 rcu_dynticks_inc+0x0c bl.d debug_smp_processor_id 273 81af5b38 ) rcu_dynticks_inc+0x10 mov_s %r15,%r0 272 81af5f18 debug_smp_processor_id mov_s %r1,0x81c0_95ec 271 81af5f1e debug_smp_processor_id+0x06 mov_s %r0,0x81c1_e28c 270 81af5f24 ) debug_smp_processor_id+0x0c b check_preemption_disabled 269 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 268 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 267 81af5e54 check_preemption_disabled+0x08 push_s %blink 266 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 265 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 264 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 263 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 262 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 261 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 260 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 259 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 258 81af5e74 check_preemption_disabled+0x28 pop_s %blink 257 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 256 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 255 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 254 81af5b3a rcu_dynticks_inc+0x12 mov_s %r1,0x81d8_eb84 ; __per_cpu_offset 253 81af5b40 rcu_dynticks_inc+0x18 add2 %r14,%r14,37 252 81af5b44 rcu_dynticks_inc+0x1c ld.as %r0,[%r1,%r0] 251 81af5b48 rcu_dynticks_inc+0x20 add_s %r14,%r14,%r0 250 81af5b4a rcu_dynticks_inc+0x22 dmb 3,0 249 81af5b4e rcu_dynticks_inc+0x26 clri %r3 248 81af5b52 rcu_dynticks_inc+0x2a dmb 3,0 247 81af5b56 rcu_dynticks_inc+0x2e mov_s %r2,0x81d6_609c ; smp_atomic_ops_lock 246 81af5b5c rcu_dynticks_inc+0x34 mov_s %r0,1 245 81af5b5e rcu_dynticks_inc+0x36 ex %r0,[%r2] 244 81af5b62 rcu_dynticks_inc+0x3a breq %r0,1,0x81af_5b5e = rcu_dynticks_inc+0x36 243 81af5b66 rcu_dynticks_inc+0x3e dmb 3,0 242 81af5b6a rcu_dynticks_inc+0x42 mov_s %r0,%r15 241 81af5b6c rcu_dynticks_inc+0x44 atld.add %r0,[%r14] 240 81af5b70 rcu_dynticks_inc+0x48 add %r0,%r0,%r15 239 81af5b74 rcu_dynticks_inc+0x4c dmb 3,0 238 81af5b78 rcu_dynticks_inc+0x50 mov_s %r1,0 237 81af5b7a rcu_dynticks_inc+0x52 ex %r1,[%r2] 236 81af5b7e rcu_dynticks_inc+0x56 dmb 3,0 235 81af5b82 rcu_dynticks_inc+0x5a seti %r3 234 81af5b86 rcu_dynticks_inc+0x5e dmb 3,0 233 81af5b8a rcu_dynticks_inc+0x62 pop_s %blink 232 81af5b8c rcu_dynticks_inc+0x64 j_s.d [%blink] 231 81af5b8e ) rcu_dynticks_inc+0x66 ldd.ab %r14,[%sp,8] 230 8150c5ba rcu_momentary_dyntick_idle+0x2e xbfu.f 0,%r0,0,1 229 8150c5be rcu_momentary_dyntick_idle+0x32 bz_s 0x8150_c5e2 = rcu_momentary_dyntick_idle+0x56 228 8150c5c0 rcu_momentary_dyntick_idle+0x34 mov %r0,%gp 227 8150c5c4 rcu_momentary_dyntick_idle+0x38 bl.d rcu_preempt_need_deferred_qs 226 8150c5c8 ) rcu_momentary_dyntick_idle+0x3c mov %r14,%gp 225 815095e0 rcu_preempt_need_deferred_qs push_s %r14 224 815095e2 rcu_preempt_need_deferred_qs+0x02 push_s %blink 223 815095e4 rcu_preempt_need_deferred_qs+0x04 mov_s %r14,%r0 222 815095e6 rcu_preempt_need_deferred_qs+0x06 mov_s %r0,0x81c1_3068 221 815095ec ) rcu_preempt_need_deferred_qs+0x0c bl __this_cpu_preempt_check 220 81af5f28 __this_cpu_preempt_check mov_s %r1,%r0 219 81af5f2a __this_cpu_preempt_check+0x02 mov_s %r0,0x81c1_e2a0 218 81af5f30 ) __this_cpu_preempt_check+0x08 b check_preemption_disabled 217 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 216 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 215 81af5e54 check_preemption_disabled+0x08 push_s %blink 214 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 213 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 212 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 211 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 210 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 209 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 208 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 207 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 206 81af5e74 check_preemption_disabled+0x28 pop_s %blink 205 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 204 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 203 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 202 815095f0 rcu_preempt_need_deferred_qs+0x10 and %r0,0xffff_e000,%sp 201 815095f8 rcu_preempt_need_deferred_qs+0x18 mov_s %r1,0x8148_c680 ; rcu_data 200 815095fe rcu_preempt_need_deferred_qs+0x1e ld_s %r2,[%r0,12] 199 81509600 rcu_preempt_need_deferred_qs+0x20 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 198 81509606 rcu_preempt_need_deferred_qs+0x26 add %r1,%r1,13 197 8150960a rcu_preempt_need_deferred_qs+0x2a ld.as %r0,[%r0,%r2] 196 8150960e rcu_preempt_need_deferred_qs+0x2e ldb_s %r0,[%r0,%r1] 195 81509610 rcu_preempt_need_deferred_qs+0x30 brnz_s %r0,0,0x8150_9618 = rcu_preempt_need_deferred_qs+0x38 194 81509612 rcu_preempt_need_deferred_qs+0x32 ld %r1,[%r14,0x2a0] 193 81509616 ) rcu_preempt_need_deferred_qs+0x36 brz_s %r1,0,0x8150_9620 = rcu_preempt_need_deferred_qs+0x40 192 81509620 rcu_preempt_need_deferred_qs+0x40 pop_s %blink 191 81509622 rcu_preempt_need_deferred_qs+0x42 j_s.d [%blink] 190 81509624 ) rcu_preempt_need_deferred_qs+0x44 pop_s %r14 189 8150c5cc rcu_momentary_dyntick_idle+0x40 brnz_s %r0,0,0x8150_c5d4 = rcu_momentary_dyntick_idle+0x48 188 8150c5ce rcu_momentary_dyntick_idle+0x42 pop_s %blink 187 8150c5d0 rcu_momentary_dyntick_idle+0x44 j_s.d [%blink] 186 8150c5d2 ) rcu_momentary_dyntick_idle+0x46 pop_s %r14 185 81530c90 ) multi_cpu_stop+0xf4 b_s 0x8153_0c76 = multi_cpu_stop+0xda 184 81530c76 multi_cpu_stop+0xda bl.d stop_machine_yield 183 81530c7a ) multi_cpu_stop+0xde mov_s %r0,%r19 182 81530b98 ) stop_machine_yield j_s [%blink] 181 81530c7c multi_cpu_stop+0xe0 ld_s %r14,[%r15,16] 180 81530c7e multi_cpu_stop+0xe2 brne %r17,%r14,0x8153_0c18 = multi_cpu_stop+0x7c 179 81530c82 multi_cpu_stop+0xe6 brlo %r14,2,0x8153_0c8a = multi_cpu_stop+0xee 178 81530c86 ) multi_cpu_stop+0xea bl touch_softlockup_watchdog 177 815317a4 touch_softlockup_watchdog and %r0,0xffff_e000,%sp 176 815317ac touch_softlockup_watchdog+0x08 mov_s %r1,0x8148_aa44 ; watchdog_report_ts 175 815317b2 touch_softlockup_watchdog+0x0e ld_s %r2,[%r0,12] 174 815317b4 touch_softlockup_watchdog+0x10 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 173 815317ba touch_softlockup_watchdog+0x16 ld.as %r0,[%r0,%r2] 172 815317be touch_softlockup_watchdog+0x1a add_s %r0,%r0,%r1 171 815317c0 touch_softlockup_watchdog+0x1c j_s.d [%blink] 170 815317c2 ) touch_softlockup_watchdog+0x1e st -1,[%r0] 169 81530c8a multi_cpu_stop+0xee bl.d rcu_momentary_dyntick_idle 168 81530c8e ) multi_cpu_stop+0xf2 mov_s %r17,%r14 167 8150c58c rcu_momentary_dyntick_idle push_s %r14 166 8150c58e rcu_momentary_dyntick_idle+0x02 push_s %blink 165 8150c590 rcu_momentary_dyntick_idle+0x04 and %r2,0xffff_e000,%sp 164 8150c598 rcu_momentary_dyntick_idle+0x0c mov_s %r1,0x8148_c680 ; rcu_data 163 8150c59e rcu_momentary_dyntick_idle+0x12 mov_s %r0,2 162 8150c5a0 rcu_momentary_dyntick_idle+0x14 ld_s %r3,[%r2,12] 161 8150c5a2 rcu_momentary_dyntick_idle+0x16 mov_s %r2,0x81d8_eb84 ; __per_cpu_offset 160 8150c5a8 rcu_momentary_dyntick_idle+0x1c add3 %r1,%r1,19 159 8150c5ac rcu_momentary_dyntick_idle+0x20 ld.as %r2,[%r2,%r3] 158 8150c5b0 rcu_momentary_dyntick_idle+0x24 add_s %r1,%r1,%r2 157 8150c5b2 rcu_momentary_dyntick_idle+0x26 bl.d rcu_dynticks_inc 156 8150c5b6 ) rcu_momentary_dyntick_idle+0x2a stb 0,[%r1] 155 81af5b28 rcu_dynticks_inc std.aw %r14,[%sp,-8] 154 81af5b2c rcu_dynticks_inc+0x04 push_s %blink 153 81af5b2e rcu_dynticks_inc+0x06 mov_s %r14,0x8148_c680 ; rcu_data 152 81af5b34 rcu_dynticks_inc+0x0c bl.d debug_smp_processor_id 151 81af5b38 ) rcu_dynticks_inc+0x10 mov_s %r15,%r0 150 81af5f18 debug_smp_processor_id mov_s %r1,0x81c0_95ec 149 81af5f1e debug_smp_processor_id+0x06 mov_s %r0,0x81c1_e28c 148 81af5f24 ) debug_smp_processor_id+0x0c b check_preemption_disabled 147 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 146 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 145 81af5e54 check_preemption_disabled+0x08 push_s %blink 144 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 143 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 142 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 141 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 140 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 139 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 138 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 137 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 136 81af5e74 check_preemption_disabled+0x28 pop_s %blink 135 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 134 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 133 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 132 81af5b3a rcu_dynticks_inc+0x12 mov_s %r1,0x81d8_eb84 ; __per_cpu_offset 131 81af5b40 rcu_dynticks_inc+0x18 add2 %r14,%r14,37 130 81af5b44 rcu_dynticks_inc+0x1c ld.as %r0,[%r1,%r0] 129 81af5b48 rcu_dynticks_inc+0x20 add_s %r14,%r14,%r0 128 81af5b4a rcu_dynticks_inc+0x22 dmb 3,0 127 81af5b4e rcu_dynticks_inc+0x26 clri %r3 126 81af5b52 rcu_dynticks_inc+0x2a dmb 3,0 125 81af5b56 rcu_dynticks_inc+0x2e mov_s %r2,0x81d6_609c ; smp_atomic_ops_lock 124 81af5b5c rcu_dynticks_inc+0x34 mov_s %r0,1 123 81af5b5e rcu_dynticks_inc+0x36 ex %r0,[%r2] 122 81af5b62 rcu_dynticks_inc+0x3a breq %r0,1,0x81af_5b5e = rcu_dynticks_inc+0x36 121 81af5b66 rcu_dynticks_inc+0x3e dmb 3,0 120 81af5b6a rcu_dynticks_inc+0x42 mov_s %r0,%r15 119 81af5b6c rcu_dynticks_inc+0x44 atld.add %r0,[%r14] 118 81af5b70 rcu_dynticks_inc+0x48 add %r0,%r0,%r15 117 81af5b74 rcu_dynticks_inc+0x4c dmb 3,0 116 81af5b78 rcu_dynticks_inc+0x50 mov_s %r1,0 115 81af5b7a rcu_dynticks_inc+0x52 ex %r1,[%r2] 114 81af5b7e rcu_dynticks_inc+0x56 dmb 3,0 113 81af5b82 rcu_dynticks_inc+0x5a seti %r3 112 81af5b86 rcu_dynticks_inc+0x5e dmb 3,0 111 81af5b8a rcu_dynticks_inc+0x62 pop_s %blink 110 81af5b8c rcu_dynticks_inc+0x64 j_s.d [%blink] 109 81af5b8e ) rcu_dynticks_inc+0x66 ldd.ab %r14,[%sp,8] 108 8150c5ba rcu_momentary_dyntick_idle+0x2e xbfu.f 0,%r0,0,1 107 8150c5be rcu_momentary_dyntick_idle+0x32 bz_s 0x8150_c5e2 = rcu_momentary_dyntick_idle+0x56 106 8150c5c0 rcu_momentary_dyntick_idle+0x34 mov %r0,%gp 105 8150c5c4 rcu_momentary_dyntick_idle+0x38 bl.d rcu_preempt_need_deferred_qs 104 8150c5c8 ) rcu_momentary_dyntick_idle+0x3c mov %r14,%gp 103 815095e0 rcu_preempt_need_deferred_qs push_s %r14 102 815095e2 rcu_preempt_need_deferred_qs+0x02 push_s %blink 101 815095e4 rcu_preempt_need_deferred_qs+0x04 mov_s %r14,%r0 100 815095e6 rcu_preempt_need_deferred_qs+0x06 mov_s %r0,0x81c1_3068 99 815095ec ) rcu_preempt_need_deferred_qs+0x0c bl __this_cpu_preempt_check 98 81af5f28 __this_cpu_preempt_check mov_s %r1,%r0 97 81af5f2a __this_cpu_preempt_check+0x02 mov_s %r0,0x81c1_e2a0 96 81af5f30 ) __this_cpu_preempt_check+0x08 b check_preemption_disabled 95 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 94 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 93 81af5e54 check_preemption_disabled+0x08 push_s %blink 92 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 91 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 90 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 89 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 88 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 87 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 86 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 85 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 84 81af5e74 check_preemption_disabled+0x28 pop_s %blink 83 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 82 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 81 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 80 815095f0 rcu_preempt_need_deferred_qs+0x10 and %r0,0xffff_e000,%sp 79 815095f8 rcu_preempt_need_deferred_qs+0x18 mov_s %r1,0x8148_c680 ; rcu_data 78 815095fe rcu_preempt_need_deferred_qs+0x1e ld_s %r2,[%r0,12] 77 81509600 rcu_preempt_need_deferred_qs+0x20 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 76 81509606 rcu_preempt_need_deferred_qs+0x26 add %r1,%r1,13 75 8150960a rcu_preempt_need_deferred_qs+0x2a ld.as %r0,[%r0,%r2] 74 8150960e rcu_preempt_need_deferred_qs+0x2e ldb_s %r0,[%r0,%r1] 73 81509610 rcu_preempt_need_deferred_qs+0x30 brnz_s %r0,0,0x8150_9618 = rcu_preempt_need_deferred_qs+0x38 72 81509612 rcu_preempt_need_deferred_qs+0x32 ld %r1,[%r14,0x2a0] 71 81509616 ) rcu_preempt_need_deferred_qs+0x36 brz_s %r1,0,0x8150_9620 = rcu_preempt_need_deferred_qs+0x40 70 81509620 rcu_preempt_need_deferred_qs+0x40 pop_s %blink 69 81509622 rcu_preempt_need_deferred_qs+0x42 j_s.d [%blink] 68 81509624 ) rcu_preempt_need_deferred_qs+0x44 pop_s %r14 67 8150c5cc rcu_momentary_dyntick_idle+0x40 brnz_s %r0,0,0x8150_c5d4 = rcu_momentary_dyntick_idle+0x48 66 8150c5ce rcu_momentary_dyntick_idle+0x42 pop_s %blink 65 8150c5d0 rcu_momentary_dyntick_idle+0x44 j_s.d [%blink] 64 8150c5d2 ) rcu_momentary_dyntick_idle+0x46 pop_s %r14 63 81530c90 ) multi_cpu_stop+0xf4 b_s 0x8153_0c76 = multi_cpu_stop+0xda 62 81530c76 multi_cpu_stop+0xda bl.d stop_machine_yield 61 81530c7a ) multi_cpu_stop+0xde mov_s %r0,%r19 60 81530b98 ) stop_machine_yield j_s [%blink] 59 81530c7c multi_cpu_stop+0xe0 ld_s %r14,[%r15,16] 58 81530c7e multi_cpu_stop+0xe2 brne %r17,%r14,0x8153_0c18 = multi_cpu_stop+0x7c 57 81530c82 multi_cpu_stop+0xe6 brlo %r14,2,0x8153_0c8a = multi_cpu_stop+0xee 56 81530c86 ) multi_cpu_stop+0xea bl touch_softlockup_watchdog 55 815317a4 touch_softlockup_watchdog and %r0,0xffff_e000,%sp 54 815317ac touch_softlockup_watchdog+0x08 mov_s %r1,0x8148_aa44 ; watchdog_report_ts 53 815317b2 touch_softlockup_watchdog+0x0e ld_s %r2,[%r0,12] 52 815317b4 touch_softlockup_watchdog+0x10 mov_s %r0,0x81d8_eb84 ; __per_cpu_offset 51 815317ba touch_softlockup_watchdog+0x16 ld.as %r0,[%r0,%r2] 50 815317be touch_softlockup_watchdog+0x1a add_s %r0,%r0,%r1 49 815317c0 touch_softlockup_watchdog+0x1c j_s.d [%blink] 48 815317c2 ) touch_softlockup_watchdog+0x1e st -1,[%r0] 47 81530c8a multi_cpu_stop+0xee bl.d rcu_momentary_dyntick_idle 46 81530c8e ) multi_cpu_stop+0xf2 mov_s %r17,%r14 45 8150c58c rcu_momentary_dyntick_idle push_s %r14 44 8150c58e rcu_momentary_dyntick_idle+0x02 push_s %blink 43 8150c590 rcu_momentary_dyntick_idle+0x04 and %r2,0xffff_e000,%sp 42 8150c598 rcu_momentary_dyntick_idle+0x0c mov_s %r1,0x8148_c680 ; rcu_data 41 8150c59e rcu_momentary_dyntick_idle+0x12 mov_s %r0,2 40 8150c5a0 rcu_momentary_dyntick_idle+0x14 ld_s %r3,[%r2,12] 39 8150c5a2 rcu_momentary_dyntick_idle+0x16 mov_s %r2,0x81d8_eb84 ; __per_cpu_offset 38 8150c5a8 rcu_momentary_dyntick_idle+0x1c add3 %r1,%r1,19 37 8150c5ac rcu_momentary_dyntick_idle+0x20 ld.as %r2,[%r2,%r3] 36 8150c5b0 rcu_momentary_dyntick_idle+0x24 add_s %r1,%r1,%r2 35 8150c5b2 rcu_momentary_dyntick_idle+0x26 bl.d rcu_dynticks_inc 34 8150c5b6 ) rcu_momentary_dyntick_idle+0x2a stb 0,[%r1] 33 81af5b28 rcu_dynticks_inc std.aw %r14,[%sp,-8] 32 81af5b2c rcu_dynticks_inc+0x04 push_s %blink 31 81af5b2e rcu_dynticks_inc+0x06 mov_s %r14,0x8148_c680 ; rcu_data 30 81af5b34 rcu_dynticks_inc+0x0c bl.d debug_smp_processor_id 29 81af5b38 ) rcu_dynticks_inc+0x10 mov_s %r15,%r0 28 81af5f18 debug_smp_processor_id mov_s %r1,0x81c0_95ec 27 81af5f1e debug_smp_processor_id+0x06 mov_s %r0,0x81c1_e28c 26 81af5f24 ) debug_smp_processor_id+0x0c b check_preemption_disabled 25 81af5e4c check_preemption_disabled std.aw %r16,[%sp,-8] 24 81af5e50 check_preemption_disabled+0x04 std.aw %r14,[%sp,-8] 23 81af5e54 check_preemption_disabled+0x08 push_s %blink 22 81af5e56 check_preemption_disabled+0x0a sub2 %sp,%sp,1 21 81af5e5a check_preemption_disabled+0x0e and %r14,0xffff_e000,%sp 20 81af5e62 check_preemption_disabled+0x16 ld_s %r2,[%r14,8] 19 81af5e64 check_preemption_disabled+0x18 tst_s %r2,%r2 18 81af5e66 check_preemption_disabled+0x1a bz.d 0x81af_5e80 = check_preemption_disabled+0x34 17 81af5e6a check_preemption_disabled+0x1e ld %r16,[%r14,12] 16 81af5e6e check_preemption_disabled+0x22 add2 %sp,%sp,1 15 81af5e72 check_preemption_disabled+0x26 mov_s %r0,%r16 14 81af5e74 check_preemption_disabled+0x28 pop_s %blink 13 81af5e76 check_preemption_disabled+0x2a ldd.ab %r14,[%sp,8] 12 81af5e7a check_preemption_disabled+0x2e j_s.d [%blink] 11 81af5e7c ) check_preemption_disabled+0x30 ldd.ab %r16,[%sp,8] 10 81af5b3a rcu_dynticks_inc+0x12 mov_s %r1,0x81d8_eb84 ; __per_cpu_offset 9 81af5b40 rcu_dynticks_inc+0x18 add2 %r14,%r14,37 8 81af5b44 rcu_dynticks_inc+0x1c ld.as %r0,[%r1,%r0] 7 81af5b48 rcu_dynticks_inc+0x20 add_s %r14,%r14,%r0 6 81af5b4a rcu_dynticks_inc+0x22 dmb 3,0 5 81af5b4e rcu_dynticks_inc+0x26 clri %r3 4 81af5b52 rcu_dynticks_inc+0x2a dmb 3,0 3 81af5b56 rcu_dynticks_inc+0x2e mov_s %r2,0x81d6_609c ; smp_atomic_ops_lock 2 81af5b5c rcu_dynticks_inc+0x34 mov_s %r0,1 1 81af5b5e rcu_dynticks_inc+0x36 ex %r0,[%r2] 0 81af5b62 rcu_dynticks_inc+0x3a breq %r0,1,0x81af_5b5e = rcu_dynticks_inc+0x36