From dfc8e5f6595b90bb3f3c4064b7d9d06853a81e48 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Tue, 23 Jan 2024 10:27:15 +0530 Subject: [PATCH 01/15] soc: zynqmp: Add the IDcode for dr_SE and eg_SE variants ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE variants. SE is the select edition of restricted devices with the capabilities. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20240123045715.893652-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/soc/soc_xilinx_zynqmp.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index d9a5944965b..786825d920c 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -35,13 +35,15 @@ static const char zynqmp_family[] = "ZynqMP"; #define IDCODE2_PL_INIT_SHIFT 9 #define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) -#define ZYNQMP_VERSION_SIZE 7 +#define ZYNQMP_VERSION_SIZE 10 enum { ZYNQMP_VARIANT_EG = BIT(0), ZYNQMP_VARIANT_EV = BIT(1), ZYNQMP_VARIANT_CG = BIT(2), ZYNQMP_VARIANT_DR = BIT(3), + ZYNQMP_VARIANT_DR_SE = BIT(4), + ZYNQMP_VARIANT_EG_SE = BIT(5), }; struct zynqmp_device { @@ -105,6 +107,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 11, .variants = ZYNQMP_VARIANT_EG, }, + { + .id = 0x04741093, + .device = 11, + .variants = ZYNQMP_VARIANT_EG_SE, + }, { .id = 0x04750093, .device = 15, @@ -120,6 +127,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 19, .variants = ZYNQMP_VARIANT_EG, }, + { + .id = 0x0475C093, + .device = 19, + .variants = ZYNQMP_VARIANT_EG_SE, + }, { .id = 0x047E1093, .device = 21, @@ -170,6 +182,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 47, .variants = ZYNQMP_VARIANT_DR, }, + { + .id = 0x047FA093, + .device = 47, + .variants = ZYNQMP_VARIANT_DR_SE, + }, { .id = 0x047FB093, .device = 48, @@ -185,6 +202,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 67, .variants = ZYNQMP_VARIANT_DR, }, + { + .id = 0x046d7093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR_SE, + }, { .id = 0x04712093, .device = 24, @@ -271,8 +293,12 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, "cg" : "eg", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_EG) { strlcat(priv->machine, "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG_SE) { + strlcat(priv->machine, "eg_SE", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR) { strlcat(priv->machine, "dr", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { + strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); } return 0; From 958526f250cb0752ed639f7d98e10b29a26f06e0 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 26 Jan 2024 13:39:00 +0530 Subject: [PATCH 02/15] configs: versal: Enable CONFIG_LTO for mini qspi/ospi Adding a tiny bit more code for mini u-boot leads to a OCM image overflow. Fix this by enabling LTO for this board, so that such changes still can be made to the common U-Boot code. Enable building mini u-boot image with LTO, which results in about 8KB reduction in size. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20240126080900.3209323-1-venkatesh.abbarapu@amd.com --- configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 72a123d9654..7a110350c2c 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index d9fbac986c8..58945a1cac9 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set From 8a58aed145754742000df2fca9d6c56570d6a4f0 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 26 Jan 2024 13:41:39 +0530 Subject: [PATCH 03/15] configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi Adding a tiny bit more code for mini u-boot leads to a OCM image overflow. Fix this by enabling LTO for this board, so that such changes still can be made to the common U-Boot code. Enable building mini u-boot image with LTO, which results in about 8KB reduction in size. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20240126081139.3210211-1-venkatesh.abbarapu@amd.com --- configs/xilinx_versal_net_mini_ospi_defconfig | 1 + configs/xilinx_versal_net_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 5f42243d22b..d78c9f80599 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 4fa83faa401..b0567f857a3 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set From 98f7bf5da4c1669f07ab3b6a5eca03a3930df004 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 24 Jan 2024 11:58:40 +0100 Subject: [PATCH 04/15] arm64: xilinx: Enable EFI_HTTP_BOOT by default Enable EFI_HTTP_BOOT to be able to booting OS via http. In case of that dhcp server is not providing dns server IP set it up via setenv dnsip . Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com --- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_kria_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 371d14eb89b..0f1d990936f 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -146,3 +146,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 5f76a305ab3..3c55dd8dcde 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -153,3 +153,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 0dc6c5b6877..28b28f68411 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -224,3 +224,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2742e38b599..1fcae45e95d 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -242,3 +242,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y From cbd87dae91b41db4685b18a53739bd8cd54e79f5 Mon Sep 17 00:00:00 2001 From: Saeed Nowshadi Date: Thu, 25 Jan 2024 09:07:58 +0100 Subject: [PATCH 05/15] arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes Without 'silabs,skip-recall' property, the driver on System Controller re-calibrates the output clock frequency at probe() time based on the NVRAM setting. This re-calibration causes a glitch on the output clock. At power-on, Versal is also booting and expecting a glitch-free clock for its correct operation. System Controller should skip the re-calibration step to prevent any clock instability for Versal. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f1b0a4aa65d..0b97fa3f28a 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -449,6 +449,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; + silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ @@ -463,6 +464,7 @@ factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; + silabs,skip-recall; }; }; @@ -560,6 +562,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; + silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ @@ -574,6 +577,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; + silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ @@ -588,6 +592,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; + silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ From 0845f5c803f191db6992837da2faa1396861eaa4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 26 Jan 2024 08:24:41 +0100 Subject: [PATCH 06/15] arm64: zynqmp: Sync clock labels with kr260 revB Board description describes the hard part of chip (PS) but programmable logic (PL) part is not described in this file. But clocks on the board are not only connected to PS but also wired to PL. And because two revisions are available where revA is using one si5332 and revB multiple clock chips using the same clock labels helping with keeping only one device tree overlay which targets PL. That's why synchronize clock labels and use labels from revB which are more generic. Unfortunately if there is driver for si5332 chip split could happen again but it is still worth to do it now and solve this issue when occurs. Reported-by: Sagar Karmarkar Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/abac6069e6029ed4076ec7b9d6b33604b6072aa3.1706253871.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 7717abf7bd8..39ca98a9d47 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -25,37 +25,37 @@ io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - si5332_0: si5332-0 { /* u17 - GEM0/1 */ + clk_125: si5332-0 { /* u17 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332-1 { /* u17 - DP */ + clk_27: si5332-1 { /* u17 - DP */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; - si5332_2: si5332-2 { /* u17 - USB */ + clk_26: si5332-2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_3: si5332-3 { /* u17 - SFP+ */ + clk_156: si5332-3 { /* u17 - SFP+ */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <156250000>; }; - si5332_4: si5332-4 { /* u17 - GEM2 */ + clk_25_0: si5332-4 { /* u17 - GEM2 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_5: si5332-5 { /* u17 - GEM3 */ + clk_25_1: si5332-5 { /* u17 - GEM3 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -115,7 +115,7 @@ &psgtr { status = "okay"; /* gem0/1, dp, usb */ - clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clocks = <&clk_125>, <&clk_27>, <&clk_26>; clock-names = "ref0", "ref1", "ref2"; }; From 8e9566c98118fa66d663f65b13aa5577844224b8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 29 Jan 2024 08:46:43 +0100 Subject: [PATCH 07/15] arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs Describe 25Mhz fixed oscilator which is providing clock for PL based ethernet IPs. Physicially it is one chip but it is described as 2 fixed clock to be aligned with other SOM versions which were using integrated clock generators where clocks could be adjusted via i2c (si5332 chips). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 766f78303ee..b3fc17cbd57 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -32,6 +32,18 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &can0 { From f8e125c995384771a2dcd33d299e21ff8879e3bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 30 Jan 2024 15:51:06 +0100 Subject: [PATCH 08/15] arm64: zynqmp: Fix kr260 clock wiring kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for other clocks but clocks are different compare to kv260 that's why fix it to aligned with the latest schematics. On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete clock chip for SLVC-EC output which is not defined. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 14 ++++++++++---- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 6 ++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 39ca98a9d47..afcf8a8ee6b 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -25,16 +25,22 @@ io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; + clk_27: clock0 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + clk_125: si5332-0 { /* u17 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - clk_27: si5332-1 { /* u17 - DP */ + clk_74: si5332-5 { /* u17 - SLVC-EC */ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <27000000>; + clock-frequency = <74250000>; }; clk_26: si5332-2 { /* u17 - USB */ @@ -49,13 +55,13 @@ clock-frequency = <156250000>; }; - clk_25_0: si5332-4 { /* u17 - GEM2 */ + clk_25_0: si5332-1 { /* u17 - GEM2 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - clk_25_1: si5332-5 { /* u17 - GEM3 */ + clk_25_1: si5332-4 { /* u17 - GEM3 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 21187396326..24be5dd84e1 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -60,6 +60,12 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ From fb16d9321fe06d75eea6fdd66660ee747a47ec95 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 1 Feb 2024 13:38:40 +0100 Subject: [PATCH 09/15] xilinx: Fix fpga region DT nodes name fpga-full is not aligned with the latest dt-schema. Generic name fpga-region should be used. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/78e6e3f287f79917eb92c6c74accbaf955526aad.1706791116.git.michal.simek@amd.com --- arch/arm/dts/zynq-7000.dtsi | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f8c786ab0b7..75dfd2f069d 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -44,7 +44,7 @@ }; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 63238c08780..ee2fbcaedc5 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -307,7 +307,7 @@ compatible = "arm,cortex-a53-edac"; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; From e0cce114348be1fed2b4e96b6948f31b123a143d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 1 Feb 2024 13:38:41 +0100 Subject: [PATCH 10/15] arm64: zynqmp: Remove arm,cortex-a53-edac node There is no dt schema associated with it. Also Linux driver have been removed in Xilinx Linux tree and never gets to upstream that's why remove description for it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6685ee980d9b475f95eef6b2a74795adc4ac4619.1706791116.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ee2fbcaedc5..e539fa329e1 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -303,10 +303,6 @@ ; }; - edac { - compatible = "arm,cortex-a53-edac"; - }; - fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; From f1c24bdf7b1980e1f2b1be1d5a9dbb29e92fd07e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 1 Feb 2024 13:38:42 +0100 Subject: [PATCH 11/15] arm64: zynqmp: Align nvmem-fw node with dt-schema Node name has to be renamed to be aligned with dt-schema and also xlnx,zynqmp-nvmem-fw switched to fixed-layout. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/32899b20c1e282aab16c32074b1c9a3f45f6dac8.1706791116.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 125 ++++++++++++++++++++------------------- 1 file changed, 64 insertions(+), 61 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e539fa329e1..b50b83b7723 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -207,68 +207,71 @@ mbox-names = "tx", "rx"; }; - nvmem-firmware { + soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc-revision@0 { - reg = <0x0 0x4>; - }; - /* efuse access */ - efuse_dna: efuse-dna@c { - reg = <0xc 0xc>; - }; - efuse_usr0: efuse-usr0@20 { - reg = <0x20 0x4>; - }; - efuse_usr1: efuse-usr1@24 { - reg = <0x24 0x4>; - }; - efuse_usr2: efuse-usr2@28 { - reg = <0x28 0x4>; - }; - efuse_usr3: efuse-usr3@2c { - reg = <0x2c 0x4>; - }; - efuse_usr4: efuse-usr4@30 { - reg = <0x30 0x4>; - }; - efuse_usr5: efuse-usr5@34 { - reg = <0x34 0x4>; - }; - efuse_usr6: efuse-usr6@38 { - reg = <0x38 0x4>; - }; - efuse_usr7: efuse-usr7@3c { - reg = <0x3c 0x4>; - }; - efuse_miscusr: efuse-miscusr@40 { - reg = <0x40 0x4>; - }; - efuse_chash: efuse-chash@50 { - reg = <0x50 0x4>; - }; - efuse_pufmisc: efuse-pufmisc@54 { - reg = <0x54 0x4>; - }; - efuse_sec: efuse-sec@58 { - reg = <0x58 0x4>; - }; - efuse_spkid: efuse-spkid@5c { - reg = <0x5c 0x4>; - }; - efuse_aeskey: efuse-aeskey@60 { - reg = <0x60 0x20>; - }; - efuse_ppk0hash: efuse-ppk0hash@a0 { - reg = <0xa0 0x30>; - }; - efuse_ppk1hash: efuse-ppk1hash@d0 { - reg = <0xd0 0x30>; - }; - efuse_pufuser: efuse-pufuser@100 { - reg = <0x100 0x7F>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse-aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse-pufuser@100 { + reg = <0x100 0x7F>; + }; }; }; From 04dca75ae3dbb4ec009cd9ff3e5602698f85544d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 1 Feb 2024 13:38:43 +0100 Subject: [PATCH 12/15] arm64: zynqmp: Do not expose usbhub nodes on kr260 usb1 usb0 is already updated but forget to also update usb1. Fixes: 4ff083f09bc2 ("arm64: zynqmp: Do not expose usbhub nodes") Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/862ca748670f18f25d88aa5b43c37e3dd6aa35eb.1706791116.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 3 ++- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index afcf8a8ee6b..ce7c5eb6d34 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -174,12 +174,13 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - +#if 0 usbhub1: usb-hub { /* u84 */ i2c-bus = <&usbhub_i2c1>; compatible = "microchip,usb5744"; reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 24be5dd84e1..6c29f657413 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -175,11 +175,13 @@ reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; +#if 0 usbhub1: usb-hub { /* u84 */ i2c-bus = <&usbhub_i2c1>; compatible = "microchip,usb5744"; reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; +#endif }; &dwc3_1 { From a0a24194bcb02b8efab0ec3c783b42e8c828c2b6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 1 Feb 2024 13:38:44 +0100 Subject: [PATCH 13/15] arm64: zynqmp: Disable DP on kd240 When SOM dt is combined with kd240 overlay DPSUB is enabled but kd240 has no DP wired that's why change disable it via status property. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f6de217b3350c9d59032ef54800882e48f240398.1706791116.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index b3fc17cbd57..5202b7c4819 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -366,3 +366,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; + +&zynqmp_dpsub { + status = "disabled"; +}; From db23e67bbd231c02b3a1cdf900b45efda45410d4 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 7 Feb 2024 14:03:28 +0530 Subject: [PATCH 14/15] xilinx: zynqmp: Add the missing function prototype Add missing prototype to fix the below sparse warning warning: no previous prototype for 'spl_spi_get_uboot_offs' [-Wmissing-prototypes] Fixes: 2c8a09219cdb ("arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation") Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20240207083328.1673752-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 9f500907202..ba49eb7be22 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include From c2ad5fb616d4e8aa2ac00e224030589847731fbe Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 6 Feb 2024 12:51:39 +0100 Subject: [PATCH 15/15] arm64: versal-net: Setup correct addresses of GICR/GICD Previous addresses where used in past in emulation environment but never gets to silicon that's why use correct addresses. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5d3d0e1afb1f673ffeb4a1c5d7f040475c806a30.1707220293.git.michal.simek@amd.com --- include/configs/xilinx_versal_net.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 2b441da91a1..9cb6b2bfea3 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -16,8 +16,8 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF9000000 -#define GICR_BASE 0xF9060000 +#define GICD_BASE 0xe2000000 +#define GICR_BASE 0xe2060000 /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \