diff --git a/autogen/external/SPIRV-Headers b/autogen/external/SPIRV-Headers index e867c06..1c6bb27 160000 --- a/autogen/external/SPIRV-Headers +++ b/autogen/external/SPIRV-Headers @@ -1 +1 @@ -Subproject commit e867c06631767a2d96424cbec530f9ee5e78180f +Subproject commit 1c6bb2743599e6eb6f37b2969acc0aef812e32e3 diff --git a/rspirv/Cargo.toml b/rspirv/Cargo.toml index a0d0194..a1f8e2b 100644 --- a/rspirv/Cargo.toml +++ b/rspirv/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "rspirv" -version = "0.12.0+sdk-1.3.268.0" +version = "0.12.0+sdk-1.3.275.0" authors = ["Lei Zhang "] edition = "2018" diff --git a/rspirv/binary/autogen_parse_operand.rs b/rspirv/binary/autogen_parse_operand.rs index a8d4004..12cab68 100644 --- a/rspirv/binary/autogen_parse_operand.rs +++ b/rspirv/binary/autogen_parse_operand.rs @@ -515,6 +515,12 @@ impl<'c, 'd> Parser<'c, 'd> { spirv::Decoration::ForcePow2DepthINTEL => { vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] } + spirv::Decoration::StridesizeINTEL => { + vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] + } + spirv::Decoration::WordsizeINTEL => { + vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] + } spirv::Decoration::CacheSizeINTEL => { vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] } @@ -546,16 +552,6 @@ impl<'c, 'd> Parser<'c, 'd> { dr::Operand::LiteralBit32(self.decoder.bit32()?), dr::Operand::FPOperationMode(self.decoder.fp_operation_mode()?), ], - spirv::Decoration::InitModeINTEL => vec![dr::Operand::InitializationModeQualifier( - self.decoder.initialization_mode_qualifier()?, - )], - spirv::Decoration::ImplementInRegisterMapINTEL => { - vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] - } - spirv::Decoration::HostAccessINTEL => vec![ - dr::Operand::HostAccessQualifier(self.decoder.host_access_qualifier()?), - dr::Operand::LiteralString(self.decoder.string()?), - ], spirv::Decoration::FPMaxErrorDecorationINTEL => { vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] } @@ -587,6 +583,16 @@ impl<'c, 'd> Parser<'c, 'd> { spirv::Decoration::MMHostInterfaceWaitRequestINTEL => { vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] } + spirv::Decoration::HostAccessINTEL => vec![ + dr::Operand::HostAccessQualifier(self.decoder.host_access_qualifier()?), + dr::Operand::LiteralString(self.decoder.string()?), + ], + spirv::Decoration::InitModeINTEL => vec![dr::Operand::InitializationModeQualifier( + self.decoder.initialization_mode_qualifier()?, + )], + spirv::Decoration::ImplementInRegisterMapINTEL => { + vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)] + } spirv::Decoration::CacheControlLoadINTEL => vec![ dr::Operand::LiteralBit32(self.decoder.bit32()?), dr::Operand::LoadCacheControl(self.decoder.load_cache_control()?), diff --git a/rspirv/dr/autogen_operand.rs b/rspirv/dr/autogen_operand.rs index c383225..c5f60c8 100644 --- a/rspirv/dr/autogen_operand.rs +++ b/rspirv/dr/autogen_operand.rs @@ -1369,6 +1369,9 @@ impl Operand { s::Decoration::StallEnableINTEL => { vec![spirv::Capability::FPGAClusterAttributesINTEL] } + s::Decoration::StallFreeINTEL => { + vec![spirv::Capability::FPGAClusterAttributesV2INTEL] + } s::Decoration::MathOpDSPModeINTEL => vec![spirv::Capability::FPGADSPControlINTEL], s::Decoration::InitiationIntervalINTEL | s::Decoration::MaxConcurrencyINTEL @@ -1394,7 +1397,10 @@ impl Operand { | s::Decoration::SimpleDualPortINTEL | s::Decoration::MergeINTEL | s::Decoration::BankBitsINTEL - | s::Decoration::ForcePow2DepthINTEL => { + | s::Decoration::ForcePow2DepthINTEL + | s::Decoration::StridesizeINTEL + | s::Decoration::WordsizeINTEL + | s::Decoration::TrueDualPortINTEL => { vec![spirv::Capability::FPGAMemoryAttributesINTEL] } s::Decoration::FPMaxErrorDecorationINTEL => { @@ -1797,21 +1803,24 @@ impl Operand { | s::Capability::BitInstructions | s::Capability::AtomicFloat32AddEXT | s::Capability::AtomicFloat64AddEXT - | s::Capability::LongConstantCompositeINTEL + | s::Capability::LongCompositesINTEL | s::Capability::OptNoneINTEL | s::Capability::AtomicFloat16AddEXT | s::Capability::DebugInfoModuleINTEL | s::Capability::BFloat16ConversionINTEL | s::Capability::SplitBarrierINTEL - | s::Capability::GlobalVariableFPGADecorationsINTEL - | s::Capability::GlobalVariableHostAccessINTEL | s::Capability::FPMaxErrorINTEL | s::Capability::FPGALatencyControlINTEL | s::Capability::FPGAArgumentInterfacesINTEL + | s::Capability::GlobalVariableHostAccessINTEL + | s::Capability::GlobalVariableFPGADecorationsINTEL | s::Capability::GroupUniformArithmeticKHR | s::Capability::CacheControlsINTEL => vec![], s::Capability::GenericPointer => vec![spirv::Capability::Addresses], s::Capability::SubgroupDispatch => vec![spirv::Capability::DeviceEnqueue], + s::Capability::FPGAClusterAttributesV2INTEL => { + vec![spirv::Capability::FPGAClusterAttributesINTEL] + } s::Capability::FPGAKernelAttributesv2INTEL => { vec![spirv::Capability::FPGAKernelAttributesINTEL] } @@ -1913,7 +1922,6 @@ impl Operand { | s::Capability::FragmentShadingRateKHR | s::Capability::DrawParameters | s::Capability::WorkgroupMemoryExplicitLayoutKHR - | s::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR | s::Capability::MultiView | s::Capability::VariablePointersStorageBuffer | s::Capability::RayQueryProvisionalKHR @@ -1968,7 +1976,8 @@ impl Operand { vec![spirv::Capability::VariablePointersStorageBuffer] } s::Capability::VectorComputeINTEL => vec![spirv::Capability::VectorAnyINTEL], - s::Capability::WorkgroupMemoryExplicitLayout8BitAccessKHR => { + s::Capability::WorkgroupMemoryExplicitLayout8BitAccessKHR + | s::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR => { vec![spirv::Capability::WorkgroupMemoryExplicitLayoutKHR] } }, @@ -2467,6 +2476,9 @@ impl Operand { | s::Decoration::UserSemantic | s::Decoration::FunctionRoundingModeINTEL | s::Decoration::FunctionDenormModeINTEL + | s::Decoration::StridesizeINTEL + | s::Decoration::WordsizeINTEL + | s::Decoration::TrueDualPortINTEL | s::Decoration::BurstCoalesceINTEL | s::Decoration::CacheSizeINTEL | s::Decoration::DontStaticallyCoalesceINTEL @@ -2485,9 +2497,7 @@ impl Operand { | s::Decoration::SingleElementVectorINTEL | s::Decoration::VectorComputeCallableFunctionINTEL | s::Decoration::MediaBlockIOINTEL - | s::Decoration::InitModeINTEL - | s::Decoration::ImplementInRegisterMapINTEL - | s::Decoration::HostAccessINTEL + | s::Decoration::StallFreeINTEL | s::Decoration::FPMaxErrorDecorationINTEL | s::Decoration::LatencyControlLabelINTEL | s::Decoration::LatencyControlConstraintINTEL @@ -2500,6 +2510,9 @@ impl Operand { | s::Decoration::MMHostInterfaceMaxBurstINTEL | s::Decoration::MMHostInterfaceWaitRequestINTEL | s::Decoration::StableKernelArgumentINTEL + | s::Decoration::HostAccessINTEL + | s::Decoration::InitModeINTEL + | s::Decoration::ImplementInRegisterMapINTEL | s::Decoration::CacheControlLoadINTEL | s::Decoration::CacheControlStoreINTEL => vec![], s::Decoration::ExplicitInterpAMD => { @@ -2855,7 +2868,8 @@ impl Operand { vec!["SPV_INTEL_fpga_argument_interfaces"] } s::Capability::FPGABufferLocationINTEL => vec!["SPV_INTEL_fpga_buffer_location"], - s::Capability::FPGAClusterAttributesINTEL => { + s::Capability::FPGAClusterAttributesINTEL + | s::Capability::FPGAClusterAttributesV2INTEL => { vec!["SPV_INTEL_fpga_cluster_attributes"] } s::Capability::FPGADSPControlINTEL => vec!["SPV_INTEL_fpga_dsp_control"], @@ -2883,9 +2897,7 @@ impl Operand { s::Capability::KernelAttributesINTEL | s::Capability::FPGAKernelAttributesINTEL | s::Capability::FPGAKernelAttributesv2INTEL => vec!["SPV_INTEL_kernel_attributes"], - s::Capability::LongConstantCompositeINTEL => { - vec!["SPV_INTEL_long_constant_composite"] - } + s::Capability::LongCompositesINTEL => vec!["SPV_INTEL_long_composites"], s::Capability::LoopFuseINTEL => vec!["SPV_INTEL_loop_fuse"], s::Capability::SubgroupImageMediaBlockIOINTEL => vec!["SPV_INTEL_media_block_io"], s::Capability::MemoryAccessAliasingINTEL => { @@ -3600,6 +3612,10 @@ impl Operand { kind: crate::grammar::OperandKind::LiteralInteger, quantifier: crate::grammar::OperandQuantifier::One, }], + s::Decoration::StridesizeINTEL => vec![crate::grammar::LogicalOperand { + kind: crate::grammar::OperandKind::LiteralInteger, + quantifier: crate::grammar::OperandQuantifier::One, + }], s::Decoration::FunctionDenormModeINTEL => vec![ crate::grammar::LogicalOperand { kind: crate::grammar::OperandKind::LiteralInteger, @@ -3636,6 +3652,10 @@ impl Operand { quantifier: crate::grammar::OperandQuantifier::One, }] } + s::Decoration::WordsizeINTEL => vec![crate::grammar::LogicalOperand { + kind: crate::grammar::OperandKind::LiteralInteger, + quantifier: crate::grammar::OperandQuantifier::One, + }], s::Decoration::XfbBuffer => vec![crate::grammar::LogicalOperand { kind: crate::grammar::OperandKind::LiteralInteger, quantifier: crate::grammar::OperandQuantifier::One, diff --git a/rspirv/dr/build/autogen_norm_insts.rs b/rspirv/dr/build/autogen_norm_insts.rs index 09c96e0..680c182 100644 --- a/rspirv/dr/build/autogen_norm_insts.rs +++ b/rspirv/dr/build/autogen_norm_insts.rs @@ -19436,6 +19436,47 @@ impl Builder { self.insert_into_block(insert_point, inst)?; Ok(_id) } + #[doc = "Appends an OpCompositeConstructContinuedINTEL instruction to the current block."] + pub fn composite_construct_continued_intel( + &mut self, + result_type: spirv::Word, + result_id: Option, + constituents: impl IntoIterator, + ) -> BuildResult { + let _id = result_id.unwrap_or_else(|| self.id()); + #[allow(unused_mut)] + let mut inst = dr::Instruction::new( + spirv::Op::CompositeConstructContinuedINTEL, + Some(result_type), + Some(_id), + vec![], + ); + inst.operands + .extend(constituents.into_iter().map(dr::Operand::IdRef)); + self.insert_into_block(InsertPoint::End, inst)?; + Ok(_id) + } + #[doc = "Appends an OpCompositeConstructContinuedINTEL instruction to the current block."] + pub fn insert_composite_construct_continued_intel( + &mut self, + insert_point: InsertPoint, + result_type: spirv::Word, + result_id: Option, + constituents: impl IntoIterator, + ) -> BuildResult { + let _id = result_id.unwrap_or_else(|| self.id()); + #[allow(unused_mut)] + let mut inst = dr::Instruction::new( + spirv::Op::CompositeConstructContinuedINTEL, + Some(result_type), + Some(_id), + vec![], + ); + inst.operands + .extend(constituents.into_iter().map(dr::Operand::IdRef)); + self.insert_into_block(insert_point, inst)?; + Ok(_id) + } #[doc = "Appends an OpConvertFToBF16INTEL instruction to the current block."] pub fn convert_f_to_bf16intel( &mut self, diff --git a/rspirv/grammar/autogen_table.rs b/rspirv/grammar/autogen_table.rs index 5f491f8..2228812 100644 --- a/rspirv/grammar/autogen_table.rs +++ b/rspirv/grammar/autogen_table.rs @@ -6989,22 +6989,28 @@ static INSTRUCTION_TABLE: &[Instruction<'static>] = &[ ), inst!( TypeStructContinuedINTEL, - [LongConstantCompositeINTEL], + [LongCompositesINTEL], [], [(IdRef, ZeroOrMore)] ), inst!( ConstantCompositeContinuedINTEL, - [LongConstantCompositeINTEL], + [LongCompositesINTEL], [], [(IdRef, ZeroOrMore)] ), inst!( SpecConstantCompositeContinuedINTEL, - [LongConstantCompositeINTEL], + [LongCompositesINTEL], [], [(IdRef, ZeroOrMore)] ), + inst!( + CompositeConstructContinuedINTEL, + [LongCompositesINTEL], + [], + [(IdResultType, One), (IdResult, One), (IdRef, ZeroOrMore)] + ), inst!( ConvertFToBF16INTEL, [BFloat16ConversionINTEL], diff --git a/rspirv/lift/autogen_context.rs b/rspirv/lift/autogen_context.rs index 045d7e2..aedc22f 100644 --- a/rspirv/lift/autogen_context.rs +++ b/rspirv/lift/autogen_context.rs @@ -12058,6 +12058,19 @@ impl LiftContext { }) .ok_or(OperandError::Missing)?, }), + 6096u32 => Ok(ops::Op::CompositeConstructContinuedINTEL { + constituents: { + let mut vec = Vec::new(); + while let Some(item) = match operands.next() { + Some(dr::Operand::IdRef(value)) => Some(*value), + Some(_) => return Err(OperandError::WrongType.into()), + None => None, + } { + vec.push(item); + } + vec + }, + }), 6116u32 => Ok(ops::Op::ConvertFToBF16INTEL { float_value: (match operands.next() { Some(dr::Operand::IdRef(value)) => Some(*value), diff --git a/rspirv/sr/autogen_decoration.rs b/rspirv/sr/autogen_decoration.rs index 92a2fd2..273e716 100644 --- a/rspirv/sr/autogen_decoration.rs +++ b/rspirv/sr/autogen_decoration.rs @@ -111,6 +111,9 @@ pub enum Decoration { MergeINTEL(String, String), BankBitsINTEL(Vec), ForcePow2DepthINTEL(u32), + StridesizeINTEL(u32), + WordsizeINTEL(u32), + TrueDualPortINTEL, BurstCoalesceINTEL, CacheSizeINTEL(u32), DontStaticallyCoalesceINTEL, @@ -129,9 +132,7 @@ pub enum Decoration { SingleElementVectorINTEL, VectorComputeCallableFunctionINTEL, MediaBlockIOINTEL, - InitModeINTEL(spirv::InitializationModeQualifier), - ImplementInRegisterMapINTEL(u32), - HostAccessINTEL(spirv::HostAccessQualifier, String), + StallFreeINTEL, FPMaxErrorDecorationINTEL(u32), LatencyControlLabelINTEL(u32), LatencyControlConstraintINTEL(u32, u32, u32), @@ -144,6 +145,9 @@ pub enum Decoration { MMHostInterfaceMaxBurstINTEL(u32), MMHostInterfaceWaitRequestINTEL(u32), StableKernelArgumentINTEL, + HostAccessINTEL(spirv::HostAccessQualifier, String), + InitModeINTEL(spirv::InitializationModeQualifier), + ImplementInRegisterMapINTEL(u32), CacheControlLoadINTEL(u32, spirv::LoadCacheControl), CacheControlStoreINTEL(u32, spirv::StoreCacheControl), } diff --git a/rspirv/sr/autogen_ops.rs b/rspirv/sr/autogen_ops.rs index 2188fb8..642bd39 100644 --- a/rspirv/sr/autogen_ops.rs +++ b/rspirv/sr/autogen_ops.rs @@ -3013,6 +3013,9 @@ pub enum Op { semantics: spirv::Word, value: spirv::Word, }, + CompositeConstructContinuedINTEL { + constituents: Vec, + }, ConvertFToBF16INTEL { float_value: spirv::Word, }, diff --git a/spirv/Cargo.toml b/spirv/Cargo.toml index 223c785..6731db5 100644 --- a/spirv/Cargo.toml +++ b/spirv/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "spirv" -version = "0.3.0+sdk-1.3.268.0" +version = "0.3.0+sdk-1.3.275.0" authors = ["Lei Zhang "] edition = "2018" @@ -20,4 +20,4 @@ path = "lib.rs" [dependencies] bitflags = "2.0" -serde = {version = "1", optional = true, features = ["derive"]} +serde = { version = "1", optional = true, features = ["derive"] } diff --git a/spirv/autogen_spirv.rs b/spirv/autogen_spirv.rs index b0d4c7b..6debf70 100644 --- a/spirv/autogen_spirv.rs +++ b/spirv/autogen_spirv.rs @@ -1320,6 +1320,9 @@ pub enum Decoration { MergeINTEL = 5834u32, BankBitsINTEL = 5835u32, ForcePow2DepthINTEL = 5836u32, + StridesizeINTEL = 5883u32, + WordsizeINTEL = 5884u32, + TrueDualPortINTEL = 5885u32, BurstCoalesceINTEL = 5899u32, CacheSizeINTEL = 5900u32, DontStaticallyCoalesceINTEL = 5901u32, @@ -1338,9 +1341,7 @@ pub enum Decoration { SingleElementVectorINTEL = 6085u32, VectorComputeCallableFunctionINTEL = 6087u32, MediaBlockIOINTEL = 6140u32, - InitModeINTEL = 6147u32, - ImplementInRegisterMapINTEL = 6148u32, - HostAccessINTEL = 6168u32, + StallFreeINTEL = 6151u32, FPMaxErrorDecorationINTEL = 6170u32, LatencyControlLabelINTEL = 6172u32, LatencyControlConstraintINTEL = 6173u32, @@ -1353,6 +1354,9 @@ pub enum Decoration { MMHostInterfaceMaxBurstINTEL = 6181u32, MMHostInterfaceWaitRequestINTEL = 6182u32, StableKernelArgumentINTEL = 6183u32, + HostAccessINTEL = 6188u32, + InitModeINTEL = 6190u32, + ImplementInRegisterMapINTEL = 6191u32, CacheControlLoadINTEL = 6442u32, CacheControlStoreINTEL = 6443u32, } @@ -1384,6 +1388,7 @@ impl Decoration { 5634u32..=5636u32 => unsafe { core::mem::transmute::(n) }, 5822u32..=5823u32 => unsafe { core::mem::transmute::(n) }, 5825u32..=5836u32 => unsafe { core::mem::transmute::(n) }, + 5883u32..=5885u32 => unsafe { core::mem::transmute::(n) }, 5899u32..=5902u32 => unsafe { core::mem::transmute::(n) }, 5905u32 => unsafe { core::mem::transmute::(5905u32) }, 5907u32 => unsafe { core::mem::transmute::(5907u32) }, @@ -1396,11 +1401,12 @@ impl Decoration { 6085u32 => unsafe { core::mem::transmute::(6085u32) }, 6087u32 => unsafe { core::mem::transmute::(6087u32) }, 6140u32 => unsafe { core::mem::transmute::(6140u32) }, - 6147u32..=6148u32 => unsafe { core::mem::transmute::(n) }, - 6168u32 => unsafe { core::mem::transmute::(6168u32) }, + 6151u32 => unsafe { core::mem::transmute::(6151u32) }, 6170u32 => unsafe { core::mem::transmute::(6170u32) }, 6172u32..=6173u32 => unsafe { core::mem::transmute::(n) }, 6175u32..=6183u32 => unsafe { core::mem::transmute::(n) }, + 6188u32 => unsafe { core::mem::transmute::(6188u32) }, + 6190u32..=6191u32 => unsafe { core::mem::transmute::(n) }, 6442u32..=6443u32 => unsafe { core::mem::transmute::(n) }, _ => return None, }) @@ -1525,6 +1531,9 @@ impl core::str::FromStr for Decoration { "MergeINTEL" => Ok(Self::MergeINTEL), "BankBitsINTEL" => Ok(Self::BankBitsINTEL), "ForcePow2DepthINTEL" => Ok(Self::ForcePow2DepthINTEL), + "StridesizeINTEL" => Ok(Self::StridesizeINTEL), + "WordsizeINTEL" => Ok(Self::WordsizeINTEL), + "TrueDualPortINTEL" => Ok(Self::TrueDualPortINTEL), "BurstCoalesceINTEL" => Ok(Self::BurstCoalesceINTEL), "CacheSizeINTEL" => Ok(Self::CacheSizeINTEL), "DontStaticallyCoalesceINTEL" => Ok(Self::DontStaticallyCoalesceINTEL), @@ -1543,9 +1552,7 @@ impl core::str::FromStr for Decoration { "SingleElementVectorINTEL" => Ok(Self::SingleElementVectorINTEL), "VectorComputeCallableFunctionINTEL" => Ok(Self::VectorComputeCallableFunctionINTEL), "MediaBlockIOINTEL" => Ok(Self::MediaBlockIOINTEL), - "InitModeINTEL" => Ok(Self::InitModeINTEL), - "ImplementInRegisterMapINTEL" => Ok(Self::ImplementInRegisterMapINTEL), - "HostAccessINTEL" => Ok(Self::HostAccessINTEL), + "StallFreeINTEL" => Ok(Self::StallFreeINTEL), "FPMaxErrorDecorationINTEL" => Ok(Self::FPMaxErrorDecorationINTEL), "LatencyControlLabelINTEL" => Ok(Self::LatencyControlLabelINTEL), "LatencyControlConstraintINTEL" => Ok(Self::LatencyControlConstraintINTEL), @@ -1558,6 +1565,9 @@ impl core::str::FromStr for Decoration { "MMHostInterfaceMaxBurstINTEL" => Ok(Self::MMHostInterfaceMaxBurstINTEL), "MMHostInterfaceWaitRequestINTEL" => Ok(Self::MMHostInterfaceWaitRequestINTEL), "StableKernelArgumentINTEL" => Ok(Self::StableKernelArgumentINTEL), + "HostAccessINTEL" => Ok(Self::HostAccessINTEL), + "InitModeINTEL" => Ok(Self::InitModeINTEL), + "ImplementInRegisterMapINTEL" => Ok(Self::ImplementInRegisterMapINTEL), "CacheControlLoadINTEL" => Ok(Self::CacheControlLoadINTEL), "CacheControlStoreINTEL" => Ok(Self::CacheControlStoreINTEL), _ => Err(()), @@ -2234,18 +2244,19 @@ pub enum Capability { GroupNonUniformRotateKHR = 6026u32, AtomicFloat32AddEXT = 6033u32, AtomicFloat64AddEXT = 6034u32, - LongConstantCompositeINTEL = 6089u32, + LongCompositesINTEL = 6089u32, OptNoneINTEL = 6094u32, AtomicFloat16AddEXT = 6095u32, DebugInfoModuleINTEL = 6114u32, BFloat16ConversionINTEL = 6115u32, SplitBarrierINTEL = 6141u32, - GlobalVariableFPGADecorationsINTEL = 6146u32, + FPGAClusterAttributesV2INTEL = 6150u32, FPGAKernelAttributesv2INTEL = 6161u32, - GlobalVariableHostAccessINTEL = 6167u32, FPMaxErrorINTEL = 6169u32, FPGALatencyControlINTEL = 6171u32, FPGAArgumentInterfacesINTEL = 6174u32, + GlobalVariableHostAccessINTEL = 6187u32, + GlobalVariableFPGADecorationsINTEL = 6189u32, GroupUniformArithmeticKHR = 6400u32, CacheControlsINTEL = 6441u32, } @@ -2333,12 +2344,13 @@ impl Capability { 6094u32..=6095u32 => unsafe { core::mem::transmute::(n) }, 6114u32..=6115u32 => unsafe { core::mem::transmute::(n) }, 6141u32 => unsafe { core::mem::transmute::(6141u32) }, - 6146u32 => unsafe { core::mem::transmute::(6146u32) }, + 6150u32 => unsafe { core::mem::transmute::(6150u32) }, 6161u32 => unsafe { core::mem::transmute::(6161u32) }, - 6167u32 => unsafe { core::mem::transmute::(6167u32) }, 6169u32 => unsafe { core::mem::transmute::(6169u32) }, 6171u32 => unsafe { core::mem::transmute::(6171u32) }, 6174u32 => unsafe { core::mem::transmute::(6174u32) }, + 6187u32 => unsafe { core::mem::transmute::(6187u32) }, + 6189u32 => unsafe { core::mem::transmute::(6189u32) }, 6400u32 => unsafe { core::mem::transmute::(6400u32) }, 6441u32 => unsafe { core::mem::transmute::(6441u32) }, _ => return None, @@ -2672,18 +2684,19 @@ impl core::str::FromStr for Capability { "GroupNonUniformRotateKHR" => Ok(Self::GroupNonUniformRotateKHR), "AtomicFloat32AddEXT" => Ok(Self::AtomicFloat32AddEXT), "AtomicFloat64AddEXT" => Ok(Self::AtomicFloat64AddEXT), - "LongConstantCompositeINTEL" => Ok(Self::LongConstantCompositeINTEL), + "LongCompositesINTEL" => Ok(Self::LongCompositesINTEL), "OptNoneINTEL" => Ok(Self::OptNoneINTEL), "AtomicFloat16AddEXT" => Ok(Self::AtomicFloat16AddEXT), "DebugInfoModuleINTEL" => Ok(Self::DebugInfoModuleINTEL), "BFloat16ConversionINTEL" => Ok(Self::BFloat16ConversionINTEL), "SplitBarrierINTEL" => Ok(Self::SplitBarrierINTEL), - "GlobalVariableFPGADecorationsINTEL" => Ok(Self::GlobalVariableFPGADecorationsINTEL), + "FPGAClusterAttributesV2INTEL" => Ok(Self::FPGAClusterAttributesV2INTEL), "FPGAKernelAttributesv2INTEL" => Ok(Self::FPGAKernelAttributesv2INTEL), - "GlobalVariableHostAccessINTEL" => Ok(Self::GlobalVariableHostAccessINTEL), "FPMaxErrorINTEL" => Ok(Self::FPMaxErrorINTEL), "FPGALatencyControlINTEL" => Ok(Self::FPGALatencyControlINTEL), "FPGAArgumentInterfacesINTEL" => Ok(Self::FPGAArgumentInterfacesINTEL), + "GlobalVariableHostAccessINTEL" => Ok(Self::GlobalVariableHostAccessINTEL), + "GlobalVariableFPGADecorationsINTEL" => Ok(Self::GlobalVariableFPGADecorationsINTEL), "GroupUniformArithmeticKHR" => Ok(Self::GroupUniformArithmeticKHR), "CacheControlsINTEL" => Ok(Self::CacheControlsINTEL), _ => Err(()), @@ -3697,6 +3710,7 @@ pub enum Op { TypeStructContinuedINTEL = 6090u32, ConstantCompositeContinuedINTEL = 6091u32, SpecConstantCompositeContinuedINTEL = 6092u32, + CompositeConstructContinuedINTEL = 6096u32, ConvertFToBF16INTEL = 6116u32, ConvertBF16ToFINTEL = 6117u32, ControlBarrierArriveINTEL = 6142u32, @@ -3780,6 +3794,7 @@ impl Op { 6035u32 => unsafe { core::mem::transmute::(6035u32) }, 6086u32 => unsafe { core::mem::transmute::(6086u32) }, 6090u32..=6092u32 => unsafe { core::mem::transmute::(n) }, + 6096u32 => unsafe { core::mem::transmute::(6096u32) }, 6116u32..=6117u32 => unsafe { core::mem::transmute::(n) }, 6142u32..=6143u32 => unsafe { core::mem::transmute::(n) }, 6401u32..=6408u32 => unsafe { core::mem::transmute::(n) },