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Qsys_tb.spd
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Qsys_tb.spd
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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/verbosity_pkg.sv"
type="SYSTEM_VERILOG"
library="altera_common_sv_packages"
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys_car_voltage_data.v"
type="VERILOG"
library="car_voltage_data" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys_car_led.v"
type="VERILOG"
library="car_led" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys_buzzer_out.v"
type="VERILOG"
library="buzzer_out" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys_bts_tmd_connect_state.v"
type="VERILOG"
library="bts_tmd_connect_state" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys_LED.v"
type="VERILOG"
library="LED" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0010.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_uart_bt_external_interface_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0009.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_sonic_distance_0_conduit_end_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_avalon_reset_source.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_reset_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0008.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_mpu_i2c_export_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0007.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_motor_measure_left_conduit_end_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0006.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_led_external_connection_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0005.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_dc_motor_left_conduit_end_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_avalon_clock_source.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_clk_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0004.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_car_voltage_data_external_connection_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0003.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_car_led_external_connection_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm_0002.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_buzzer_out_external_connection_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/altera_conduit_bfm.sv"
type="SYSTEM_VERILOG"
library="Qsys_inst_bts_tmd_connect_state_external_connection_bfm" />
<file
path="Qsys/testbench/Qsys_tb/simulation/submodules/Qsys.v"
type="VERILOG"
library="Qsys_inst" />
<file path="Qsys/testbench/Qsys_tb/simulation/Qsys_tb.v" type="VERILOG" />
<topLevel name="Qsys_tb" />
<deviceFamily name="cyclonev" />
<modelMap
controllerPath="Qsys_tb.Qsys_inst.onchip_memory2_0"
modelPath="Qsys_tb.Qsys_inst.onchip_memory2_0" />
</simPackage>