From 92624788d6a1eaed3413036b64385605fd7a750a Mon Sep 17 00:00:00 2001
From: ejchung0406 <joykang71@gmail.com>
Date: Wed, 28 Feb 2024 20:28:05 -0500
Subject: [PATCH] bug fix (gpu barrier)

---
 src/process_manager.cc  |  5 +++--
 src/trace_read_nvbit.cc | 24 +++++++++++++-----------
 2 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/process_manager.cc b/src/process_manager.cc
index b6b65e8..fc6c0a7 100644
--- a/src/process_manager.cc
+++ b/src/process_manager.cc
@@ -522,7 +522,7 @@ void process_manager_c::setup_process(process_s *process) {
   } else if (trace_type == "nvbit") {
     if (!(trace_config_file >> process->m_max_block))
       ASSERTM(0, "error reading from file:%s", trace_info_file_name.c_str());
-    // process->m_max_block = *m_simBase->m_knobs->KNOB_MAX_BLOCK_PER_CORE;
+    process->m_max_block = *m_simBase->m_knobs->KNOB_MAX_BLOCK_PER_CORE;
   }
 
   // get thread count
@@ -639,7 +639,8 @@ void process_manager_c::setup_process(process_s *process) {
 
   // TODO (jaekyu, 1-30-2009)
   // FIXME
-  if (trace_type == "ptx" && *KNOB(KNOB_BLOCKS_TO_SIMULATE)) {
+  // euijun
+  if ((trace_type == "ptx" || trace_type == "nvbit") && *KNOB(KNOB_BLOCKS_TO_SIMULATE)) {
     if ((*KNOB(KNOB_BLOCKS_TO_SIMULATE) * m_simBase->m_no_threads_per_block) <
         static_cast<unsigned int>(thread_count)) {
       uns temp = thread_count;
diff --git a/src/trace_read_nvbit.cc b/src/trace_read_nvbit.cc
index c218a39..537d1b8 100644
--- a/src/trace_read_nvbit.cc
+++ b/src/trace_read_nvbit.cc
@@ -636,15 +636,16 @@ inst_info_s *nvbit_decoder_c::convert_pinuop_to_t_uop(void *trace_info,
         trace_uop[ii]->m_num_dest_regs += 1;
       }
 
-      // the last uop
-      if (ii == (num_uop - 1) &&
-          trace_uop[num_uop - 1]->m_mem_type == NOT_MEM) {
-        if (pi->m_opcode == NVBIT_BAR) {
-          // only the last instruction will have bar type - this is in case of
-          // CPU, in case of GPU there is always only one uop?
-          trace_uop[(num_uop - 1)]->m_bar_type = BAR_FETCH;
-        }
-      }
+      // NVBit trace tool does not support yet... (euijun Feb 28 2024)
+      // // the last uop
+      // if (ii == (num_uop - 1) &&
+      //     trace_uop[num_uop - 1]->m_mem_type == NOT_MEM) {
+      //   if (pi->m_opcode == NVBIT_BAR) {
+      //     // only the last instruction will have bar type - this is in case of
+      //     // CPU, in case of GPU there is always only one uop?
+      //     trace_uop[(num_uop - 1)]->m_bar_type = BAR_FETCH;
+      //   }
+      // }
 
       // update instruction information with MacSim trace
       convert_t_uop_to_info(trace_uop[ii], info);
@@ -765,6 +766,7 @@ bool nvbit_decoder_c::get_uops_from_traces(int core_id, uop_c *uop,
   ///
   /// BOM (beginning of macro) : need to get a next instruction
   ///
+  
   if (thread_trace_info->m_bom) {
     bool inst_read;  // indicate new instruction has been read from a trace file
 
@@ -1006,8 +1008,8 @@ bool nvbit_decoder_c::get_uops_from_traces(int core_id, uop_c *uop,
         ASSERT((index + 1) < MAX_PUP);
         if (thread_trace_info->m_trace_uop_array[++index]->m_mem_type) {
           ASSERTM(0,
-                  "this condition is not handled in the code (and should never "
-                  "occur?)!");
+          "this condition is not handled in the code (and should never "
+          "occur?)!");
         }
         if (thread_trace_info->m_trace_uop_array[++index]->m_eom) {
           break;