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hpm_sdk: update ADC-related codes
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- sync with hpm_sdk repo

Signed-off-by: Jiading Xu <Jiading.Xu@hpmicro.com>
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@jiadingxu @chenzhihong007
jiadingxu authored and chenzhihong007 committed Jan 17, 2024
1 parent d0d9d78 commit 6ee4764
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Showing 7 changed files with 254 additions and 52 deletions.
58 changes: 49 additions & 9 deletions arch/risc-v/src/hpmicro/hpm_sdk/drivers/inc/hpm_adc12_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
#define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count)

/** @brief Define ADC12 validity check for the channel number */
#define ADC12_IS_CHANNEL_INVALID(PTR, CH) (CH > ADC12_SOC_MAX_CH_NUM)
#define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM)

/** @brief Define ADC12 validity check for the trigger number */
#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC12_SOC_MAX_TRIG_CH_NUM)
Expand Down Expand Up @@ -96,12 +96,32 @@ typedef enum {
adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK
} adc12_irq_event_t;

/** @brief Define ADC12 Clock Divider */
typedef enum {
adc12_clock_divider_1 = 1,
adc12_clock_divider_2,
adc12_clock_divider_3,
adc12_clock_divider_4,
adc12_clock_divider_5,
adc12_clock_divider_6,
adc12_clock_divider_7,
adc12_clock_divider_8,
adc12_clock_divider_9,
adc12_clock_divider_10,
adc12_clock_divider_11,
adc12_clock_divider_12,
adc12_clock_divider_13,
adc12_clock_divider_14,
adc12_clock_divider_15,
adc12_clock_divider_16,
} adc12_clock_divider_t;

/** @brief ADC12 common configuration struct. */
typedef struct {
uint8_t res;
uint8_t conv_mode;
uint8_t wait_dis;
uint32_t adc_clk_div;
bool wait_dis;
bool sel_sync_ahb;
bool adc_ahb_en;
} adc12_config_t;
Expand Down Expand Up @@ -316,16 +336,25 @@ static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr)
}

/**
* @brief Get the setting value of the WAIT_DIS bit.
* @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus
* until the ADC has completed its conversion.
*
* @param[in] ptr An ADC12 peripheral base address.
*/
static inline void adc12_disable_busywait(ADC12_Type *ptr)
{
ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_SET(1);
}

/**
* @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus
* until the ADC completes the conversion.
*
* @param[in] ptr An ADC12 peripheral base address.
* @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled.
* @retval true It means that the WAIT_DIS bit is 1.
* @retval false It means that the WAIT_DIS bit is 0.
*/
static inline bool adc12_get_wait_dis_status(ADC12_Type *ptr)
static inline void adc12_enable_busywait(ADC12_Type *ptr)
{
return ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0);
ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK;
}

/**
Expand Down Expand Up @@ -393,7 +422,7 @@ static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask)
*/

/**
* @brief Trigger ADC conversions by software
* @brief Trigger ADC conversions by software in sequence mode
*
* @param[in] ptr An ADC12 peripheral base address.
* @return An implementation result of getting an ADC12 software trigger.
Expand All @@ -402,6 +431,17 @@ static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask)
*/
hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr);

/**
* @brief Trigger ADC conversions by software in preemption mode
*
* @param[in] ptr An ADC12 peripheral base address.
* @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...).
* @return An implementation result of getting an ADC12 software trigger.
* @retval status_success ADC12 software triggers successfully. Please refer to @ref hpm_stat_t.
* @retval status_fail ADC12 software triggers unsuccessfully. Please refer to @ref hpm_stat_t.
*/
hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch);

/**
* @brief Get the result in oneshot mode.
*
Expand Down
66 changes: 58 additions & 8 deletions arch/risc-v/src/hpmicro/hpm_sdk/drivers/inc/hpm_adc16_drv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,14 @@
/** @brief Define ADC16 validity check for the DMA buffer length in the preemption mode */
#define ADC16_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES))

/** @brief Define ADC16 resolutions. */
typedef enum {
adc16_res_8_bits = 9,
adc16_res_10_bits = 11,
adc16_res_12_bits = 14,
adc16_res_16_bits = 21
} adc16_resolution_t;

/** @brief Define ADC16 conversion modes. */
typedef enum {
adc16_conv_mode_oneshot = 0,
Expand All @@ -49,6 +57,26 @@ typedef enum {
adc16_conv_mode_preemption
} adc16_conversion_mode_t;

/** @brief Define adc16 Clock Divider */
typedef enum {
adc16_clock_divider_1 = 1,
adc16_clock_divider_2,
adc16_clock_divider_3,
adc16_clock_divider_4,
adc16_clock_divider_5,
adc16_clock_divider_6,
adc16_clock_divider_7,
adc16_clock_divider_8,
adc16_clock_divider_9,
adc16_clock_divider_10,
adc16_clock_divider_11,
adc16_clock_divider_12,
adc16_clock_divider_13,
adc16_clock_divider_14,
adc16_clock_divider_15,
adc16_clock_divider_16,
} adc16_clock_divider_t;

/** @brief Define ADC16 irq events. */
typedef enum {
/** This mask indicates that a trigger conversion is complete. */
Expand Down Expand Up @@ -84,11 +112,12 @@ typedef enum {

/** @brief ADC16 common configuration struct. */
typedef struct {
uint8_t res;
uint8_t conv_mode;
uint8_t wait_dis;
uint32_t adc_clk_div;
uint16_t conv_duration;
bool port3_rela_time;
bool wait_dis;
bool sel_sync_ahb;
bool adc_ahb_en;
} adc16_config_t;
Expand Down Expand Up @@ -312,16 +341,25 @@ static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr)
}

/**
* @brief Get the setting value of the WAIT_DIS bit.
* @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus
* until the ADC has completed its conversion.
*
* @param[in] ptr An ADC16 peripheral base address.
*/
static inline void adc16_disable_busywait(ADC16_Type *ptr)
{
ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_SET(1);
}

/**
* @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus
* until the ADC completes the conversion.
*
* @param[in] ptr An ADC16 peripheral base address.
* @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled.
* @retval true It means that the WAIT_DIS bit is 1.
* @retval false It means that the WAIT_DIS bit is 0.
*/
static inline bool adc16_get_wait_dis_status(ADC16_Type *ptr)
static inline void adc16_enable_busywait(ADC16_Type *ptr)
{
return ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0);
ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK;
}

/**
Expand Down Expand Up @@ -389,7 +427,7 @@ static inline void adc16_disable_interrupts(ADC16_Type *ptr, uint32_t mask)
*/

/**
* @brief Trigger ADC conversions by software
* @brief Trigger ADC conversions by software in sequence mode
*
* @param[in] ptr An ADC16 peripheral base address.
* @return An implementation result of getting an ADC16 software trigger.
Expand All @@ -398,6 +436,18 @@ static inline void adc16_disable_interrupts(ADC16_Type *ptr, uint32_t mask)
*/
hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr);

/**
* @brief Trigger ADC conversions by software in preemption mode
*
* @param[in] ptr An ADC16 peripheral base address.
* @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...).
* @return An implementation result of getting an ADC16 software trigger.
* @retval status_success ADC16 software triggers successfully. Please refer to @ref hpm_stat_t.
* @retval status_fail ADC16 software triggers unsuccessfully. Please refer to @ref hpm_stat_t.
*/
hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch);


/**
* @brief Get the result in oneshot mode.
*
Expand Down
38 changes: 27 additions & 11 deletions arch/risc-v/src/hpmicro/hpm_sdk/drivers/src/hpm_adc12_drv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@ void adc12_get_default_config(adc12_config_t *config)
{
config->res = adc12_res_12_bits;
config->conv_mode = adc12_conv_mode_oneshot;
config->adc_clk_div = 1;
config->wait_dis = 0;
config->adc_clk_div = adc12_clock_divider_1;
config->wait_dis = true;
config->sel_sync_ahb = true;
config->adc_ahb_en = false;
}
Expand Down Expand Up @@ -102,13 +102,13 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config)
| ADC12_ANA_CTRL1_SELRES_SET(config->res);

/* Set convert clock number and clock period */
if (config->adc_clk_div > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) {
if ((config->adc_clk_div - 1) > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) {
return status_invalid_argument;
}

/* Set ADC minimum conversion cycle and ADC clock divider */
ptr->CONV_CFG1 = ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(2 * config->res + 7)
| ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div);
| ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div - 1);

/* Set ADC Config0 */
ptr->ADC_CFG0 = ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb)
Expand Down Expand Up @@ -162,7 +162,7 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config)
hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config)
{
/* Check the specified channel number */
if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) {
if (ADC12_IS_CHANNEL_INVALID(config->ch)) {
return status_invalid_argument;
}

Expand Down Expand Up @@ -216,7 +216,7 @@ hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config)
hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config)
{
/* Check the specified channel number */
if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) {
if (ADC12_IS_CHANNEL_INVALID(config->ch)) {
return status_invalid_argument;
}

Expand Down Expand Up @@ -264,7 +264,7 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config)
/* Set sequence queue */
for (int i = 0; i < config->seq_len; i++) {
/* Check the specified channel number */
if (ADC12_IS_CHANNEL_INVALID(ptr, config->queue[i].ch)) {
if (ADC12_IS_CHANNEL_INVALID(config->queue[i].ch)) {
return status_invalid_argument;
}

Expand All @@ -275,6 +275,13 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config)
return status_success;
}

hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch)
{
ptr->TRG_SW_STA = ADC12_TRG_SW_STA_TRG_SW_STA_MASK | ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(trig_ch);

return status_success;
}

hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config)
{
uint32_t temp = 0;
Expand All @@ -287,7 +294,7 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config)
temp |= ADC12_CONFIG_TRIG_LEN_SET(config->trig_len - 1);

for (int i = 0; i < config->trig_len; i++) {
if (ADC12_IS_CHANNEL_INVALID(ptr, config->trig_ch)) {
if (ADC12_IS_CHANNEL_INVALID(config->trig_ch)) {
return status_invalid_argument;
}

Expand All @@ -302,20 +309,29 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config)

hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result)
{
uint32_t bus_res;

/* Check the specified channel number */
if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) {
if (ADC12_IS_CHANNEL_INVALID(ch)) {
return status_invalid_argument;
}

*result = ADC12_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]);
bus_res = ptr->BUS_RESULT[ch];
*result = ADC12_BUS_RESULT_CHAN_RESULT_GET(bus_res);

if (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) {
if (!ADC12_BUS_RESULT_VALID_GET(bus_res)) {
return status_fail;
}
}

return status_success;
}

hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result)
{
/* Check the specified channel number */
if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) {
if (ADC12_IS_CHANNEL_INVALID(ch)) {
return status_invalid_argument;
}

Expand Down
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