Reduce duplication, simplify re-exports, and general cleanup/organiza…

…tion (esp-rs#424)

* Move some linker scripts into `esp-hal-common` and update the build script

* Move `EspDefaultHandler` and `DefaultHandler` definitions into `esp-hal-common`

* Re-export everything from `esp-hal-common`

* Add a couple cfg symbols, cleanup/organize some exports/modules

esp-hal-common/build.rs

@@ -1,3 +1,5 @@
+use std::{env, fs, path::PathBuf};
+
 fn main() {
     let esp32 = cfg!(feature = "esp32");
     let esp32c2 = cfg!(feature = "esp32c2");
@@ -32,124 +34,133 @@ fn main() {
     //   - the core count ('single_core' or 'multi_core')
     //
     // Additionally, the following symbols MAY be defined if present:
+    //   - 'aes'
     //   - 'dac'
     //   - 'gdma'
     //   - 'i2c1'
     //   - 'i2s'
     //   - 'mcpwm'
+    //   - 'pcnt'
     //   - 'pdma'
+    //   - 'plic'
+    //   - 'radio'
     //   - 'rmt'
     //   - 'spi3'
     //   - 'systimer'
     //   - 'timg0'
     //   - 'timg1'
+    //   - 'twai'
     //   - 'uart2'
     //   - 'usb_otg'
     //   - 'usb_serial_jtag'
-    //   - 'aes'
-    //   - 'plic'
-    //   - 'radio'
     //
     // New symbols can be added as needed, but please be sure to update both this
     // comment and the required vectors below.
     let symbols = if esp32 {
         vec![
             "esp32",
             "xtensa",
-            "mcpwm",
             "multi_core",
+            "aes",
             "dac",
             "i2c1",
             "i2s",
+            "mcpwm",
+            "pcnt",
             "pdma",
+            "radio",
             "rmt",
             "spi3",
             "timg0",
             "timg1",
             "uart2",
-            "aes",
-            "radio",
         ]
     } else if esp32c2 {
         vec![
             "esp32c2",
             "riscv",
             "single_core",
             "gdma",
+            "radio",
             "systimer",
             "timg0",
-            "radio",
         ]
     } else if esp32c3 {
         vec![
             "esp32c3",
             "riscv",
             "single_core",
+            "aes",
             "gdma",
             "i2s",
+            "radio",
             "rmt",
             "spi3",
             "systimer",
             "timg0",
             "timg1",
+            "twai",
             "usb_serial_jtag",
-            "aes",
-            "radio",
         ]
     } else if esp32c6 {
         vec![
             "esp32c6",
             "riscv",
             "single_core",
+            "aes",
             "gdma",
             "i2s",
             "mcpwm",
+            "pcnt",
+            "plic",
+            "radio",
             "rmt",
             "systimer",
             "timg0",
             "timg1",
+            "twai",
             "usb_serial_jtag",
-            "plic",
-            "aes",
-            "radio",
         ]
     } else if esp32s2 {
         vec![
             "esp32s2",
             "xtensa",
             "single_core",
+            "aes",
             "dac",
             "i2c1",
             "i2s",
+            "pcnt",
             "pdma",
+            "radio",
             "rmt",
             "spi3",
             "systimer",
             "timg0",
             "timg1",
             "usb_otg",
-            "aes",
-            "radio",
         ]
     } else if esp32s3 {
         vec![
             "esp32s3",
             "xtensa",
             "multi_core",
+            "aes",
             "gdma",
             "i2c1",
             "i2s",
             "mcpwm",
+            "pcnt",
+            "radio",
             "rmt",
             "spi3",
             "systimer",
             "timg0",
             "timg1",
+            "twai",
             "uart2",
             "usb_otg",
             "usb_serial_jtag",
-            "aes",
-            "radio",
         ]
     } else {
         unreachable!(); // We've already confirmed exactly one chip was selected
@@ -158,4 +169,16 @@ fn main() {
     for symbol in symbols {
         println!("cargo:rustc-cfg={symbol}");
     }
+
+    // Place all linker scripts in `OUT_DIR`, and instruct Cargo how to find these
+    // files:
+    let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    println!("cargo:rustc-link-search={}", out.display());
+
+    if esp32 || esp32s2 || esp32s3 {
+        fs::copy("ld/xtensa/hal-defaults.x", out.join("hal-defaults.x")).unwrap();
+        fs::copy("ld/xtensa/rom.x", out.join("alias.x")).unwrap();
+    } else {
+        fs::copy("ld/riscv/hal-defaults.x", out.join("hal-defaults.x")).unwrap();
+    }
 }

esp-hal-common/src/interrupt/mod.rs

@@ -0,0 +1,9 @@
+#[cfg(riscv)]
+pub use riscv::*;
+#[cfg(xtensa)]
+pub use xtensa::*;
+
+#[cfg(riscv)]
+mod riscv;
+#[cfg(xtensa)]
+mod xtensa;

esp-hal-common/src/lib.rs

@@ -22,39 +22,35 @@
 
 #![no_std]
 #![cfg_attr(xtensa, feature(asm_experimental_arch))]
-#![cfg_attr(feature = "async", allow(incomplete_features))]
-#![cfg_attr(feature = "async", feature(async_fn_in_trait))]
-#![cfg_attr(feature = "async", feature(impl_trait_projections))]
+#![cfg_attr(
+    feature = "async",
+    allow(incomplete_features),
+    feature(async_fn_in_trait),
+    feature(impl_trait_projections)
+)]
 
 #[cfg(riscv)]
-pub use esp_riscv_rt;
-#[cfg(riscv)]
-pub use esp_riscv_rt::entry;
-#[cfg(riscv)]
-pub use esp_riscv_rt::riscv;
+pub use esp_riscv_rt::{self, entry, riscv};
 pub use procmacros as macros;
 #[cfg(xtensa)]
 pub use xtensa_lx;
 #[cfg(xtensa)]
-pub use xtensa_lx_rt;
-#[cfg(xtensa)]
-pub use xtensa_lx_rt::entry;
-
-/// State of the CPU saved when entering exception or interrupt
-pub mod trapframe {
-    #[cfg(riscv)]
-    pub use esp_riscv_rt::TrapFrame;
-    #[cfg(xtensa)]
-    pub use xtensa_lx_rt::exception::Context as TrapFrame;
-}
-
+pub use xtensa_lx_rt::{self, entry};
+
+#[cfg(dac)]
+pub use self::analog::dac::implementation as dac;
+#[cfg(gdma)]
+pub use self::dma::gdma;
+#[cfg(pdma)]
+pub use self::dma::pdma;
 #[cfg(rmt)]
 pub use self::pulse_control::PulseControl;
 #[cfg(any(esp32, esp32s3))]
 pub use self::soc::cpu_control;
 #[cfg(usb_serial_jtag)]
 pub use self::usb_serial_jtag::UsbSerialJtag;
 pub use self::{
+    analog::adc::implementation as adc,
     delay::Delay,
     interrupt::*,
     rng::Rng,
@@ -77,12 +73,13 @@ pub mod gpio;
 pub mod i2c;
 #[cfg(i2s)]
 pub mod i2s;
+pub mod interrupt;
 pub mod ledc;
 #[cfg(mcpwm)]
 pub mod mcpwm;
 #[cfg(usb_otg)]
 pub mod otg_fs;
-#[cfg(any(esp32, esp32s2, esp32s3, esp32c6))]
+#[cfg(pcnt)]
 pub mod pcnt;
 pub mod peripheral;
 pub mod prelude;
@@ -100,17 +97,28 @@ pub mod system;
 #[cfg(systimer)]
 pub mod systimer;
 pub mod timer;
-#[cfg(any(esp32c3, esp32c6, esp32s3))]
+#[cfg(any(twai))]
 pub mod twai;
 pub mod uart;
 #[cfg(usb_serial_jtag)]
 pub mod usb_serial_jtag;
 #[cfg(rmt)]
 pub mod utils;
 
-#[cfg_attr(riscv, path = "interrupt/riscv.rs")]
-#[cfg_attr(xtensa, path = "interrupt/xtensa.rs")]
-pub mod interrupt;
+/// State of the CPU saved when entering exception or interrupt
+pub mod trapframe {
+    #[cfg(riscv)]
+    pub use esp_riscv_rt::TrapFrame;
+    #[cfg(xtensa)]
+    pub use xtensa_lx_rt::exception::Context as TrapFrame;
+}
+
+#[no_mangle]
+extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) {}
+
+#[cfg(xtensa)]
+#[no_mangle]
+extern "C" fn DefaultHandler() {}
 
 #[cfg(esp32c6)]
 pub fn disable_apm_filter() {

esp32-hal/build.rs

@@ -9,16 +9,6 @@ fn main() {
         .write_all(include_bytes!("ld/memory.x"))
         .unwrap();
 
-    File::create(out.join("alias.x"))
-        .unwrap()
-        .write_all(include_bytes!("ld/rom.x"))
-        .unwrap();
-
-    File::create(out.join("hal-defaults.x"))
-        .unwrap()
-        .write_all(include_bytes!("ld/hal-defaults.x"))
-        .unwrap();
-
     File::create(out.join("rom-functions.x"))
         .unwrap()
         .write_all(include_bytes!("ld/rom-functions.x"))

esp32-hal/examples/multicore.rs

@@ -10,10 +10,10 @@ use core::cell::RefCell;
 use critical_section::Mutex;
 use esp32_hal::{
     clock::ClockControl,
+    cpu_control::CpuControl,
     peripherals::{Peripherals, TIMG1},
     prelude::*,
     timer::{Timer, Timer0, TimerGroup},
-    CpuControl,
     Rtc,
 };
 use esp_backtrace as _;

esp32-hal/src/lib.rs

@@ -4,45 +4,7 @@ pub use embedded_hal as ehal;
 #[cfg(feature = "embassy")]
 pub use esp_hal_common::embassy;
 #[doc(inline)]
-pub use esp_hal_common::{
-    aes,
-    analog::adc::implementation as adc,
-    analog::dac::implementation as dac,
-    clock,
-    cpu_control::CpuControl,
-    dma,
-    dma::pdma,
-    efuse,
-    entry,
-    gpio,
-    i2c,
-    i2s,
-    interrupt,
-    ledc,
-    macros,
-    mcpwm,
-    pcnt,
-    peripheral::Peripheral,
-    peripherals,
-    prelude,
-    pulse_control,
-    sha,
-    spi,
-    system,
-    timer,
-    trapframe,
-    uart,
-    utils,
-    xtensa_lx,
-    xtensa_lx_rt,
-    Cpu,
-    Delay,
-    PulseControl,
-    Rng,
-    Rtc,
-    Rwdt,
-    Uart,
-};
+pub use esp_hal_common::*;
 
 pub use self::gpio::IO;
 
@@ -51,12 +13,6 @@ pub mod analog {
     pub use esp_hal_common::analog::{AvailableAnalog, SensExt};
 }
 
-#[no_mangle]
-extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) {}
-
-#[no_mangle]
-extern "C" fn DefaultHandler() {}
-
 /// Function initializes ESP32 specific memories (RTC slow and fast) and
 /// then calls original Reset function
 ///

esp32c2-hal/build.rs

@@ -75,11 +75,6 @@ fn check_features() {
 fn add_defaults() {
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
 
-    File::create(out.join("hal-defaults.x"))
-        .unwrap()
-        .write_all(include_bytes!("ld/hal-defaults.x"))
-        .unwrap();
-
     File::create(out.join("rom-functions.x"))
         .unwrap()
         .write_all(include_bytes!("ld/rom-functions.x"))