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Improve cocotb tests
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LucasKl committed Oct 31, 2024
1 parent 24d20e8 commit 3271083
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Showing 9 changed files with 83 additions and 12 deletions.
2 changes: 1 addition & 1 deletion src/top_ihp.v
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ module top_ihp(
// 0100000000000000_0000000000000000 SPI_ROM (0x40000000)
// 0010000000000000_0000000000000000 UART (0x20000000)
// 0001000000000000_0000000000000000 GPIO (0x10000000)
// 0000100000000000_0000000000000000 BRAM (0x08000000)
// 0000100000000000_0000000000000000 COPROC (0x08000000)
// 0000010000000000_0000000000000000 SPI (0x04000000)

wb_oisc oisc(.clk(clk),
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1 change: 0 additions & 1 deletion src/wb_gpio.v
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@@ -1,5 +1,4 @@
/*
* Copyright (c) 2022 Daniel Pekarek
* Copyright (c) 2022 Lucas Klemmer
* Copyright (c) 2022 Felix Roithmayr
* SPDX-License-Identifier: Apache-2.0
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9 changes: 3 additions & 6 deletions test/spi_imem.py
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Expand Up @@ -2,7 +2,7 @@
import struct

class SpiIMem(SpiSlaveBase):
def __init__(self, bus):
def __init__(self, bus, program):
self._config = SpiConfig(
word_width = 32,
cpha = True,
Expand All @@ -11,11 +11,8 @@ def __init__(self, bus):
self.content = 0
super().__init__(bus)

self.mem = [
0x93000000,
0x93801000,
0x6ff0dfff,
]
with open(program) as f:
self.mem = list(map(lambda x: int(x, 16), f.readlines()))

async def get_content(self):
await self.idle.wait()
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13 changes: 13 additions & 0 deletions test/sw/Makefile
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@@ -0,0 +1,13 @@
SRCS=$(wildcard *.S)
HEX=$(SRCS:.S=.hex)

all: $(HEX)

%.hex: %.S
riscv32-unknown-elf-as $< -o a.out
riscv32-unknown-elf-objcopy -O binary -j .text -j .rodata a.out a.bin
xxd -c 4 a.bin | awk '{print $$2$$3}' > $@
rm a.*

clean:
rm *.hex
22 changes: 22 additions & 0 deletions test/sw/coproc.S
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
main:
li a0, 0x08000000 # coproc
li a1, 0x10000000 # gpio
# reset gpio pin 0
sw x0, 0(a1)
sw x0, 1(a1)
sw x0, 2(a1)
sw x0, 3(a1)

li a2, 0b1
li a3, 0b1

# send to coproc
sw a2, 0(a0)
sw a3, 4(a0)
# read results
lw t0, 12(a0) # a & b
# write to gpio bit 0
sw t0, 0(a1)

loop:
j loop
13 changes: 13 additions & 0 deletions test/sw/coproc.hex
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@@ -0,0 +1,13 @@
37050008
b7050010
23a00500
a3a00500
23a10500
a3a10500
13061000
93061000
2320c500
2322d500
8322c500
23a05500
6f000000
11 changes: 11 additions & 0 deletions test/sw/gpio.S
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@@ -0,0 +1,11 @@
main:
li s0, 0x10000000
li t0, 1

sw t0, 0(s0)
sw t0, 1(s0)
sw t0, 2(s0)
sw t0, 3(s0)

loop:
j loop
7 changes: 7 additions & 0 deletions test/sw/gpio.hex
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@@ -0,0 +1,7 @@
37040010
93021000
23205400
a3205400
23215400
a3215400
6f000000
17 changes: 13 additions & 4 deletions test/test.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,16 +9,16 @@
from spi_imem import SpiIMem


@cocotb.test()
async def test_project(dut):
#@cocotb.test()
async def test_project(dut, program, cycles, test):
dut._log.info("Start")

# Set the clock period to 10 us (100 KHz)
clock = Clock(dut.clk, 50, units="ns")
cocotb.start_soon(clock.start())

spi_bus = SpiBus.from_prefix(dut, "spi")
spi_imem = SpiIMem(spi_bus)
spi_imem = SpiIMem(spi_bus, program)

# Reset
dut._log.info("Reset")
Expand All @@ -27,4 +27,13 @@ async def test_project(dut):
await ClockCycles(dut.clk, 10)
dut.rst_n.value = 1

await ClockCycles(dut.clk, 900)
await ClockCycles(dut.clk, cycles)
assert(test(dut))

@cocotb.test()
async def test_gpio(dut):
await test_project(dut, "sw/gpio.hex", 800, lambda dut: dut.uio_out.value[0:3].integer == 0b1111)

@cocotb.test()
async def test_coproc(dut):
await test_project(dut, "sw/coproc.hex", 1800, lambda dut: dut.uio_out.value[0:3].integer == 0b0001)

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