diff --git a/src/uart_rx.v b/src/uart_rx.v
index c2935ae..fd097c5 100644
--- a/src/uart_rx.v
+++ b/src/uart_rx.v
@@ -31,7 +31,6 @@ module uart_rx #(
   reg [    2:0] next_state;
   reg [   31:0] cycle_cnt;
   reg [    3:0] bit_cnt;
-  reg           rx_reg;
 
   // FSM: next state latch
   always @(posedge clk or negedge rst_n) begin
@@ -92,4 +91,4 @@ module uart_rx #(
   end
 
 endmodule
-`endif
\ No newline at end of file
+`endif
diff --git a/src/uart_tx.v b/src/uart_tx.v
index 49b5fa7..3b1c20a 100644
--- a/src/uart_tx.v
+++ b/src/uart_tx.v
@@ -104,4 +104,4 @@ module uart_tx #(
   end
 
 endmodule
-`endif
\ No newline at end of file
+`endif
diff --git a/src/wb_gpio.v b/src/wb_gpio.v
index 687c0a5..96d3695 100644
--- a/src/wb_gpio.v
+++ b/src/wb_gpio.v
@@ -16,8 +16,17 @@ module wb_gpio(
                output wire [3:0]  gpio_o
                );
 
+   /* verilator lint_off UNUSEDSIGNAL */
+  wire [31:2] dummy1;
+  assign dummy1 = adr_i[31:2];
+  wire [31:1] dummy2;
+  assign dummy2 = dat_i[31:1];
+   wire [3:0] dummy3;
+   assign dummy3 = sel_i;
+   /* verilator lint_on UNUSEDSIGNAL */
+
    reg    [3:0]                       data_o;
-   reg    [3:0]                       data_i;
+   wire   [3:0]                       data_i;
    
    assign gpio_o = data_o;
    assign data_i = gpio_i;
@@ -40,4 +49,4 @@ module wb_gpio(
    end
 
 endmodule
-`endif
\ No newline at end of file
+`endif
diff --git a/src/wb_imem.v b/src/wb_imem.v
index 3015fb6..d9f3de0 100644
--- a/src/wb_imem.v
+++ b/src/wb_imem.v
@@ -20,6 +20,15 @@ module wb_imem(
                output wire        spi_data_o
                );
 
+   /* verilator lint_off UNUSEDSIGNAL */
+  wire [31:24] dummy1;
+  assign dummy1 = adr_i[31:24];
+   wire [31:0] dummy2;
+   assign dummy2 = dat_i[31:0];
+   wire [3:0] dummy3;
+   assign dummy3 = sel_i;
+   /* verilator lint_on UNUSEDSIGNAL */
+
    localparam                     S_IDLE = 2'd0;
    localparam                     S_SENDING = 2'd1;
    localparam                     S_RECEIVING = 2'd2;
@@ -74,4 +83,4 @@ module wb_imem(
    assign spi_data_o = (state == S_SENDING) ? cmd[31] : 1'b0;
 
 endmodule
-`endif
\ No newline at end of file
+`endif
diff --git a/src/wb_spi.v b/src/wb_spi.v
index 149cac3..5be5380 100644
--- a/src/wb_spi.v
+++ b/src/wb_spi.v
@@ -25,6 +25,13 @@ module wb_spi(
                output wire        spi_data_o
                );
 
+   /* verilator lint_off UNUSEDSIGNAL */
+   wire [31:7] dummy1;
+   assign dummy1 = adr_i[31:7];
+   wire [3:0] dummy2;
+   assign dummy2 = adr_i[3:0];
+   /* verilator lint_on UNUSEDSIGNAL */
+
    localparam                     S_IDLE = 0;
    localparam                     S_SENDING = 1;
 
@@ -95,4 +102,4 @@ module wb_spi(
    assign spi_data_o = (state == S_SENDING) ? cmd[31] : 1'b0;
 
 endmodule
-`endif
\ No newline at end of file
+`endif
diff --git a/src/wb_uart.v b/src/wb_uart.v
index aaa69be..067ff4e 100644
--- a/src/wb_uart.v
+++ b/src/wb_uart.v
@@ -18,7 +18,14 @@ module wb_uart(
                input wire         rx
                );
 
-   
+   /* verilator lint_off UNUSEDSIGNAL */
+   wire [15:0] dummy1;
+   assign dummy1 = adr_i;
+   wire [31:8] dummy2;
+   assign dummy2 = dat_i[31:8];
+   wire [3:0] dummy3;
+   assign dummy3 = sel_i;
+   /* verilator lint_on UNUSEDSIGNAL */
 
    wire [7:0] dat_tmp;
    assign dat_o = {24'b0, dat_tmp};
@@ -27,7 +34,6 @@ module wb_uart(
    wire                           rx_start = stb_i & cyc_i & ~we_i & sel_i[0];
    wire                           tx_ready;
    wire                           rx_ready;
-   reg                            working;
 
    localparam                     S_IDLE = 0;
    localparam                     S_WORKING_TX = 1;
@@ -77,4 +83,4 @@ module wb_uart(
 		   .rx_pin(rx));
 
 endmodule
-`endif
\ No newline at end of file
+`endif