revert back to reg optimization and fix multidriven

ics-jku · Oct 30, 2024 · a8c1659 · a8c1659
1 parent b2abea4
commit a8c1659
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Showing 2 changed files with 5 additions and 26 deletions.
diff --git a/src/decoder.v b/src/decoder.v
@@ -95,8 +95,6 @@ module decoder (
 
    //wire is_jalr = instruction[6:2] == 5'b11001;
    assign decoder_pc = decoded[7:0];
-   // assign decoder_funct7 = ((opcode == 7'b0010011) && (funct3 == 3'b101)) || 
-   //                         ((opcode == 7'b0110011) && ((funct3 == 3'b000) || (funct3 == 3'b101))) ? instruction[30] : 0;
    assign decoder_funct7 = ((opcode == opcode_R) || (opcode == opcode_I && (decoder_inst[14:12] == 3'b001 || decoder_inst[14:12] == 3'b101))) ? instruction[30] : 1'b0;
    assign decoder_funct3 = instruction[14:12];
    assign decoder_rs2 = (itype == 3'd5 ? 5'b0 : instruction[24:20]);

diff --git a/src/wb_oisc.v b/src/wb_oisc.v
@@ -38,7 +38,7 @@ module wb_oisc (
    wire dummy1;
    assign dummy1 = decoder_sign_extend;
    wire dummy2;
-   assign dummy1 = decoder_funct7;
+   assign dummy2 = decoder_funct7;
    wire dummy3;
    assign dummy3 = res[32];
    /* verilator lint_on UNUSEDSIGNAL */
@@ -153,8 +153,8 @@ module wb_oisc (
 
    // ----------------------------------------
 
-   //wire [31:0] wire_a = (reg_ra > 6'd15) && (reg_ra < 6'd33) ? 32'd0 : regs[reg_ra];
-   //wire [31:0] wire_b = (reg_rb > 6'd15) && (reg_rb < 6'd33) ? 32'd0 : regs[reg_rb];
+   wire [31:0] wire_a = (reg_ra > 6'd15) && (reg_ra < 6'd33) ? 32'd0 : regs[reg_ra];
+   wire [31:0] wire_b = (reg_rb > 6'd15) && (reg_rb < 6'd33) ? 32'd0 : regs[reg_rb];
 
    reg [3:0]                  micro_res_addr;
 
@@ -203,8 +203,8 @@ module wb_oisc (
          op_b <= 0;
       end else begin
          if (!(state[FETCH_INSTR_BIT] && !wb_ack_i)) begin
-            op_a <= regs[reg_ra];
-            op_b <= regs[reg_rb];
+            op_a <= wire_a;
+            op_b <= wire_b;
          end
       end
 
@@ -263,25 +263,6 @@ module wb_oisc (
          regs[61] <= 32'd0;         // X29
          regs[62] <= 32'd0;         // X30
          regs[63] <= 32'd0;         // X31
-
-         // all unused/zero registers
-         regs[16] <= 32'd0;         // 
-         regs[17] <= 32'd0;         // 
-         regs[18] <= 32'd0;         // 
-         regs[19] <= 32'd0;         // 
-         regs[20] <= 32'd0;         // 
-         regs[21] <= 32'd0;         // 
-         regs[22] <= 32'd0;         // 
-         regs[23] <= 32'd0;         // 
-         regs[24] <= 32'd0;         // 
-         regs[25] <= 32'd0;         // 
-         regs[26] <= 32'd0;         // 
-         regs[27] <= 32'd0;         // 
-         regs[28] <= 32'd0;         // 
-         regs[29] <= 32'd0;         // 
-         regs[30] <= 32'd0;         // 
-         regs[31] <= 32'd0;         // 
-         regs[32] <= 32'd0;         // X0
       end else begin
          if (reg_we) begin
             regs[reg_wa] <= reg_wdata;