From 43b0fc27a0a19f880ebe59994ca85dd0d77d565e Mon Sep 17 00:00:00 2001 From: Victor Lomuller Date: Wed, 3 Jun 2020 14:35:16 +0100 Subject: [PATCH] [SYCL-PTX] Add builtins for the relational category Signed-off-by: Victor Lomuller Co-authored-by: David Wood --- .../generic/include/clc/relational/floatn.inc | 7 + libclc/generic/include/relational.h | 251 ++- .../generic/include/spirv/float/definitions.h | 98 - .../generic/include/spirv/integer/gentype.inc | 539 ----- .../include/spirv/integer/integer-gentype.inc | 55 - libclc/generic/include/spirv/relational/all.h | 26 - libclc/generic/include/spirv/relational/any.h | 23 - .../include/spirv/relational/floatn.inc | 129 -- .../include/spirv/relational/isequal.h | 32 - .../generic/include/spirv/relational/isinf.h | 33 - .../include/spirv/relational/islessequal.h | 15 - .../include/spirv/relational/islessgreater.h | 15 - .../generic/include/spirv/relational/isnan.h | 33 - .../include/spirv/relational/isnormal.h | 17 - .../include/spirv/relational/isnotequal.h | 17 - .../include/spirv/relational/isordered.h | 17 - .../include/spirv/relational/isunordered.h | 17 - .../generic/include/spirv/relational/select.h | 19 - .../include/spirv/relational/select.inc | 33 - .../include/spirv/relational/signbit.h | 17 - libclc/generic/include/spirv/spirv.h | 24 +- libclc/generic/include/spirv/spirv_builtins.h | 1826 ++++++++++++++--- libclc/generic/libspirv/SOURCES | 16 + libclc/generic/libspirv/math/fract.cl | 1 + libclc/generic/libspirv/math/fract.inc | 40 +- libclc/generic/libspirv/relational/all.cl | 34 + libclc/generic/libspirv/relational/any.cl | 34 + .../generic/libspirv/relational/bitselect.cl | 53 + .../relational/bitselect.inc} | 11 +- .../libspirv/relational/genbinrelational.inc | 31 + .../generic/libspirv/relational/genunary.inc | 30 + libclc/generic/libspirv/relational/isequal.cl | 20 + .../relational/isfinite.cl} | 7 +- .../relational/isgreater.cl} | 17 +- .../relational/isgreaterequal.cl} | 17 +- libclc/generic/libspirv/relational/isinf.cl | 32 +- .../relational/isless.cl} | 15 +- .../relational/islessequal.cl} | 17 +- .../libspirv/relational/islessgreater.cl | 14 + libclc/generic/libspirv/relational/isnan.cl | 34 +- .../relational/isnormal.cl} | 7 +- .../generic/libspirv/relational/isnotequal.cl | 20 + .../generic/libspirv/relational/isordered.cl | 14 + .../relational/isunordered.cl} | 7 +- libclc/generic/libspirv/relational/select.cl | 15 + libclc/generic/libspirv/relational/select.inc | 35 + .../relational/signbit.cl} | 7 +- libclc/test/binding/core/All.cl | 41 + libclc/test/binding/core/Any.cl | 41 + libclc/test/binding/core/FOrdEqual.cl | 131 ++ libclc/test/binding/core/FOrdGreaterThan.cl | 146 ++ .../test/binding/core/FOrdGreaterThanEqual.cl | 146 ++ libclc/test/binding/core/FOrdLessThan.cl | 134 ++ libclc/test/binding/core/FOrdLessThanEqual.cl | 146 ++ libclc/test/binding/core/FOrdNotEqual.cl | 134 ++ libclc/test/binding/core/FUnordEqual.cl | 131 ++ libclc/test/binding/core/FUnordGreaterThan.cl | 146 ++ .../binding/core/FUnordGreaterThanEqual.cl | 146 ++ libclc/test/binding/core/FUnordLessThan.cl | 146 ++ .../test/binding/core/FUnordLessThanEqual.cl | 146 ++ libclc/test/binding/core/FUnordNotEqual.cl | 146 ++ libclc/test/binding/core/IsFinite.cl | 131 ++ libclc/test/binding/core/IsInf.cl | 131 ++ libclc/test/binding/core/IsNan.cl | 131 ++ libclc/test/binding/core/IsNormal.cl | 131 ++ libclc/test/binding/core/LessOrGreater.cl | 134 ++ libclc/test/binding/core/Ordered.cl | 131 ++ libclc/test/binding/core/SignBitSet.cl | 131 ++ libclc/test/binding/core/Unordered.cl | 131 ++ libclc/test/binding/ocl/bitselect.cl | 456 ++++ libclc/test/binding/ocl/select.cl | 863 ++++++++ libclc/utils/gen-libclc-test.py | 18 + sycl/test/basic_tests/scalar_vec_access.cpp | 2 - sycl/test/basic_tests/stream/stream.cpp | 3 - sycl/test/built-ins/scalar_relational.cpp | 3 - sycl/test/built-ins/vector_relational.cpp | 5 +- 76 files changed, 6327 insertions(+), 1625 deletions(-) delete mode 100644 libclc/generic/include/spirv/float/definitions.h delete mode 100644 libclc/generic/include/spirv/integer/gentype.inc delete mode 100644 libclc/generic/include/spirv/integer/integer-gentype.inc delete mode 100644 libclc/generic/include/spirv/relational/all.h delete mode 100644 libclc/generic/include/spirv/relational/any.h delete mode 100644 libclc/generic/include/spirv/relational/floatn.inc delete mode 100644 libclc/generic/include/spirv/relational/isequal.h delete mode 100644 libclc/generic/include/spirv/relational/isinf.h delete mode 100644 libclc/generic/include/spirv/relational/islessequal.h delete mode 100644 libclc/generic/include/spirv/relational/islessgreater.h delete mode 100644 libclc/generic/include/spirv/relational/isnan.h delete mode 100644 libclc/generic/include/spirv/relational/isnormal.h delete mode 100644 libclc/generic/include/spirv/relational/isnotequal.h delete mode 100644 libclc/generic/include/spirv/relational/isordered.h delete mode 100644 libclc/generic/include/spirv/relational/isunordered.h delete mode 100644 libclc/generic/include/spirv/relational/select.h delete mode 100644 libclc/generic/include/spirv/relational/select.inc delete mode 100644 libclc/generic/include/spirv/relational/signbit.h create mode 100644 libclc/generic/libspirv/relational/all.cl create mode 100644 libclc/generic/libspirv/relational/any.cl create mode 100644 libclc/generic/libspirv/relational/bitselect.cl rename libclc/generic/{include/spirv/relational/bitselect.h => libspirv/relational/bitselect.inc} (57%) create mode 100644 libclc/generic/libspirv/relational/genbinrelational.inc create mode 100644 libclc/generic/libspirv/relational/genunary.inc create mode 100644 libclc/generic/libspirv/relational/isequal.cl rename libclc/generic/{include/spirv/relational/unary_decl.inc => libspirv/relational/isfinite.cl} (69%) rename libclc/generic/{include/spirv/relational/isfinite.h => libspirv/relational/isgreater.cl} (51%) rename libclc/generic/{include/spirv/relational/isgreaterequal.h => libspirv/relational/isgreaterequal.cl} (50%) rename libclc/generic/{include/spirv/relational/isless.h => libspirv/relational/isless.cl} (52%) rename libclc/generic/{include/spirv/relational/isgreater.h => libspirv/relational/islessequal.cl} (50%) create mode 100644 libclc/generic/libspirv/relational/islessgreater.cl rename libclc/generic/{include/spirv/relational/bitselect.inc => libspirv/relational/isnormal.cl} (69%) create mode 100644 libclc/generic/libspirv/relational/isnotequal.cl create mode 100644 libclc/generic/libspirv/relational/isordered.cl rename libclc/generic/{include/spirv/integer/unary.inc => libspirv/relational/isunordered.cl} (67%) create mode 100644 libclc/generic/libspirv/relational/select.cl create mode 100644 libclc/generic/libspirv/relational/select.inc rename libclc/generic/{include/spirv/relational/binary_decl.inc => libspirv/relational/signbit.cl} (69%) create mode 100644 libclc/test/binding/core/All.cl create mode 100644 libclc/test/binding/core/Any.cl create mode 100644 libclc/test/binding/core/FOrdEqual.cl create mode 100644 libclc/test/binding/core/FOrdGreaterThan.cl create mode 100644 libclc/test/binding/core/FOrdGreaterThanEqual.cl create mode 100644 libclc/test/binding/core/FOrdLessThan.cl create mode 100644 libclc/test/binding/core/FOrdLessThanEqual.cl create mode 100644 libclc/test/binding/core/FOrdNotEqual.cl create mode 100644 libclc/test/binding/core/FUnordEqual.cl create mode 100644 libclc/test/binding/core/FUnordGreaterThan.cl create mode 100644 libclc/test/binding/core/FUnordGreaterThanEqual.cl create mode 100644 libclc/test/binding/core/FUnordLessThan.cl create mode 100644 libclc/test/binding/core/FUnordLessThanEqual.cl create mode 100644 libclc/test/binding/core/FUnordNotEqual.cl create mode 100644 libclc/test/binding/core/IsFinite.cl create mode 100644 libclc/test/binding/core/IsInf.cl create mode 100644 libclc/test/binding/core/IsNan.cl create mode 100644 libclc/test/binding/core/IsNormal.cl create mode 100644 libclc/test/binding/core/LessOrGreater.cl create mode 100644 libclc/test/binding/core/Ordered.cl create mode 100644 libclc/test/binding/core/SignBitSet.cl create mode 100644 libclc/test/binding/core/Unordered.cl create mode 100644 libclc/test/binding/ocl/bitselect.cl create mode 100644 libclc/test/binding/ocl/select.cl diff --git a/libclc/generic/include/clc/relational/floatn.inc b/libclc/generic/include/clc/relational/floatn.inc index fc0d6878b4aa7..0dd23c6415527 100644 --- a/libclc/generic/include/clc/relational/floatn.inc +++ b/libclc/generic/include/clc/relational/floatn.inc @@ -1,3 +1,10 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// #define __CLC_FLOATN float #define __CLC_INTN int diff --git a/libclc/generic/include/relational.h b/libclc/generic/include/relational.h index f36f3ec918f0a..104634b8bd2a4 100644 --- a/libclc/generic/include/relational.h +++ b/libclc/generic/include/relational.h @@ -1,122 +1,149 @@ #ifndef CLC_RELATIONAL #define CLC_RELATIONAL +#include + /* * Contains relational macros that have to return 1 for scalar and -1 for vector * when the result is true. */ -#define _CLC_DEFINE_RELATIONAL_UNARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_NAME, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x){ \ - return BUILTIN_NAME(x); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC2(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ - return (RET_TYPE)( (RET_TYPE){FUNCTION(x.lo), FUNCTION(x.hi)} != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC3(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ - return (RET_TYPE)( (RET_TYPE){FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2)} != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC4(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), FUNCTION(x.s3) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC8(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), FUNCTION(x.s3), \ - FUNCTION(x.s4), FUNCTION(x.s5), FUNCTION(x.s6), FUNCTION(x.s7) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC16(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), FUNCTION(x.s3), \ - FUNCTION(x.s4), FUNCTION(x.s5), FUNCTION(x.s6), FUNCTION(x.s7), \ - FUNCTION(x.s8), FUNCTION(x.s9), FUNCTION(x.sa), FUNCTION(x.sb), \ - FUNCTION(x.sc), FUNCTION(x.sd), FUNCTION(x.se), FUNCTION(x.sf) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(RET_TYPE, FUNCTION, ARG_TYPE) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC2(RET_TYPE##2, FUNCTION, ARG_TYPE##2) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC3(RET_TYPE##3, FUNCTION, ARG_TYPE##3) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC4(RET_TYPE##4, FUNCTION, ARG_TYPE##4) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC8(RET_TYPE##8, FUNCTION, ARG_TYPE##8) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC16(RET_TYPE##16, FUNCTION, ARG_TYPE##16) - -#define _CLC_DEFINE_RELATIONAL_UNARY(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, ARG_TYPE) \ -_CLC_DEFINE_RELATIONAL_UNARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, ARG_TYPE) \ -_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(RET_TYPE, FUNCTION, ARG_TYPE) \ - -#define _CLC_DEFINE_RELATIONAL_BINARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_NAME, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y){ \ - return BUILTIN_NAME(x, y); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( (RET_TYPE){FUNCTION(x.lo, y.lo), FUNCTION(x.hi, y.hi)} != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC2(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( (RET_TYPE){FUNCTION(x.lo, y.lo), FUNCTION(x.hi, y.hi)} != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC3(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( (RET_TYPE){FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2)} != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC4(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2), FUNCTION(x.s3, y.s3) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC8(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2), FUNCTION(x.s3, y.s3), \ - FUNCTION(x.s4, y.s4), FUNCTION(x.s5, y.s5), FUNCTION(x.s6, y.s6), FUNCTION(x.s7, y.s7) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC16(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ - return (RET_TYPE)( \ - (RET_TYPE){ \ - FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2), FUNCTION(x.s3, y.s3), \ - FUNCTION(x.s4, y.s4), FUNCTION(x.s5, y.s5), FUNCTION(x.s6, y.s6), FUNCTION(x.s7, y.s7), \ - FUNCTION(x.s8, y.s8), FUNCTION(x.s9, y.s9), FUNCTION(x.sa, y.sa), FUNCTION(x.sb, y.sb), \ - FUNCTION(x.sc, y.sc), FUNCTION(x.sd, y.sd), FUNCTION(x.se, y.se), FUNCTION(x.sf, y.sf) \ - } != (RET_TYPE)0); \ -} - -#define _CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC2(RET_TYPE##2, FUNCTION, ARG0_TYPE##2, ARG1_TYPE##2) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC3(RET_TYPE##3, FUNCTION, ARG0_TYPE##3, ARG1_TYPE##3) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC4(RET_TYPE##4, FUNCTION, ARG0_TYPE##4, ARG1_TYPE##4) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC8(RET_TYPE##8, FUNCTION, ARG0_TYPE##8, ARG1_TYPE##8) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC16(RET_TYPE##16, FUNCTION, ARG0_TYPE##16, ARG1_TYPE##16) - -#define _CLC_DEFINE_RELATIONAL_BINARY(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEFINE_RELATIONAL_BINARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, ARG0_TYPE, ARG1_TYPE) \ -_CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(RET_TYPE, FUNCTION, ARG0_TYPE, ARG1_TYPE) +#define _CLC_DEFINE_RELATIONAL_UNARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_NAME, \ + ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return BUILTIN_NAME(x); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC2(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.lo), FUNCTION(x.hi)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC3(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return as_##RET_TYPE(((RET_TYPE){FUNCTION(x.s0), FUNCTION(x.s1), \ + FUNCTION(x.s2)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC4(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), \ + FUNCTION(x.s3)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC8(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), \ + FUNCTION(x.s3), FUNCTION(x.s4), FUNCTION(x.s5), \ + FUNCTION(x.s6), FUNCTION(x.s7)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC16(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG_TYPE x) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.s0), FUNCTION(x.s1), FUNCTION(x.s2), \ + FUNCTION(x.s3), FUNCTION(x.s4), FUNCTION(x.s5), \ + FUNCTION(x.s6), FUNCTION(x.s7), FUNCTION(x.s8), \ + FUNCTION(x.s9), FUNCTION(x.sa), FUNCTION(x.sb), \ + FUNCTION(x.sc), FUNCTION(x.sd), FUNCTION(x.se), \ + FUNCTION(x.sf)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(RET_TYPE, FUNCTION, ARG_TYPE) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC2(RET_TYPE##2, FUNCTION, ARG_TYPE##2) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC3(RET_TYPE##3, FUNCTION, ARG_TYPE##3) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC4(RET_TYPE##4, FUNCTION, ARG_TYPE##4) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC8(RET_TYPE##8, FUNCTION, ARG_TYPE##8) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC16(RET_TYPE##16, FUNCTION, ARG_TYPE##16) + +#define _CLC_DEFINE_RELATIONAL_UNARY(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, \ + ARG_TYPE) \ + _CLC_DEFINE_RELATIONAL_UNARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, \ + ARG_TYPE) \ + _CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(RET_TYPE, FUNCTION, ARG_TYPE) + +#define _CLC_DEFINE_RELATIONAL_BINARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_NAME, \ + ARG0_TYPE, ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return BUILTIN_NAME(x, y); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE( \ + (RET_TYPE)((RET_TYPE){FUNCTION(x.lo, y.lo), FUNCTION(x.hi, y.hi)} != \ + (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC2(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE(((RET_TYPE){FUNCTION(x.lo, y.lo), \ + FUNCTION(x.hi, y.hi)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC3(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), \ + FUNCTION(x.s2, y.s2)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC4(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), \ + FUNCTION(x.s2, y.s2), \ + FUNCTION(x.s3, y.s3)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC8(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){ \ + FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2), \ + FUNCTION(x.s3, y.s3), FUNCTION(x.s4, y.s4), FUNCTION(x.s5, y.s5), \ + FUNCTION(x.s6, y.s6), FUNCTION(x.s7, y.s7)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC16(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEF _CLC_OVERLOAD RET_TYPE FUNCTION(ARG0_TYPE x, ARG1_TYPE y) { \ + return as_##RET_TYPE( \ + ((RET_TYPE){ \ + FUNCTION(x.s0, y.s0), FUNCTION(x.s1, y.s1), FUNCTION(x.s2, y.s2), \ + FUNCTION(x.s3, y.s3), FUNCTION(x.s4, y.s4), FUNCTION(x.s5, y.s5), \ + FUNCTION(x.s6, y.s6), FUNCTION(x.s7, y.s7), FUNCTION(x.s8, y.s8), \ + FUNCTION(x.s9, y.s9), FUNCTION(x.sa, y.sa), FUNCTION(x.sb, y.sb), \ + FUNCTION(x.sc, y.sc), FUNCTION(x.sd, y.sd), FUNCTION(x.se, y.se), \ + FUNCTION(x.sf, y.sf)} != (RET_TYPE)0)); \ + } + +#define _CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC2(RET_TYPE##2, FUNCTION, ARG0_TYPE##2, \ + ARG1_TYPE##2) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC3(RET_TYPE##3, FUNCTION, ARG0_TYPE##3, \ + ARG1_TYPE##3) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC4(RET_TYPE##4, FUNCTION, ARG0_TYPE##4, \ + ARG1_TYPE##4) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC8(RET_TYPE##8, FUNCTION, ARG0_TYPE##8, \ + ARG1_TYPE##8) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC16(RET_TYPE##16, FUNCTION, ARG0_TYPE##16, \ + ARG1_TYPE##16) + +#define _CLC_DEFINE_RELATIONAL_BINARY(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, \ + ARG0_TYPE, ARG1_TYPE) \ + _CLC_DEFINE_RELATIONAL_BINARY_SCALAR(RET_TYPE, FUNCTION, BUILTIN_FUNCTION, \ + ARG0_TYPE, ARG1_TYPE) \ + _CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(RET_TYPE, FUNCTION, ARG0_TYPE, \ + ARG1_TYPE) #endif // CLC_RELATIONAL diff --git a/libclc/generic/include/spirv/float/definitions.h b/libclc/generic/include/spirv/float/definitions.h deleted file mode 100644 index 4f8d3176bc865..0000000000000 --- a/libclc/generic/include/spirv/float/definitions.h +++ /dev/null @@ -1,98 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define MAXFLOAT 0x1.fffffep127f -#define HUGE_VALF __builtin_huge_valf() -#define INFINITY __builtin_inff() -#define NAN __builtin_nanf("") - -#define FLT_DIG 6 -#define FLT_MANT_DIG 24 -#define FLT_MAX_10_EXP +38 -#define FLT_MAX_EXP +128 -#define FLT_MIN_10_EXP -37 -#define FLT_MIN_EXP -125 -#define FLT_RADIX 2 -#define FLT_MAX MAXFLOAT -#define FLT_MIN 0x1.0p-126f -#define FLT_EPSILON 0x1.0p-23f - -#define FP_ILOGB0 (-2147483647 - 1) -#define FP_ILOGBNAN (-2147483647 - 1) - -#define M_E_F 0x1.5bf0a8p+1f -#define M_LOG2E_F 0x1.715476p+0f -#define M_LOG10E_F 0x1.bcb7b2p-2f -#define M_LN2_F 0x1.62e430p-1f -#define M_LN10_F 0x1.26bb1cp+1f -#define M_PI_F 0x1.921fb6p+1f -#define M_PI_2_F 0x1.921fb6p+0f -#define M_PI_4_F 0x1.921fb6p-1f -#define M_1_PI_F 0x1.45f306p-2f -#define M_2_PI_F 0x1.45f306p-1f -#define M_2_SQRTPI_F 0x1.20dd76p+0f -#define M_SQRT2_F 0x1.6a09e6p+0f -#define M_SQRT1_2_F 0x1.6a09e6p-1f - -#ifdef __CLC_INTERNAL -#define M_LOG210_F 0x1.a934f0p+1f -#endif - -#ifdef cl_khr_fp64 - -#define HUGE_VAL __builtin_huge_val() - -#define DBL_DIG 15 -#define DBL_MANT_DIG 53 -#define DBL_MAX_10_EXP +308 -#define DBL_MAX_EXP +1024 -#define DBL_MIN_10_EXP -307 -#define DBL_MIN_EXP -1021 -#define DBL_MAX 0x1.fffffffffffffp1023 -#define DBL_MIN 0x1.0p-1022 -#define DBL_EPSILON 0x1.0p-52 - -#define M_E 0x1.5bf0a8b145769p+1 -#define M_LOG2E 0x1.71547652b82fep+0 -#define M_LOG10E 0x1.bcb7b1526e50ep-2 -#define M_LN2 0x1.62e42fefa39efp-1 -#define M_LN10 0x1.26bb1bbb55516p+1 -#define M_PI 0x1.921fb54442d18p+1 -#define M_PI_2 0x1.921fb54442d18p+0 -#define M_PI_4 0x1.921fb54442d18p-1 -#define M_1_PI 0x1.45f306dc9c883p-2 -#define M_2_PI 0x1.45f306dc9c883p-1 -#define M_2_SQRTPI 0x1.20dd750429b6dp+0 -#define M_SQRT2 0x1.6a09e667f3bcdp+0 -#define M_SQRT1_2 0x1.6a09e667f3bcdp-1 - -#ifdef __CLC_INTERNAL -#define M_LOG210 0x1.a934f0979a371p+1 -#endif - -#endif - -#ifdef cl_khr_fp16 - -#if __OPENCL_VERSION__ >= 120 - -#define HALF_DIG 3 -#define HALF_MANT_DIG 11 -#define HALF_MAX_10_EXP +4 -#define HALF_MAX_EXP +16 -#define HALF_MIN_10_EXP -4 -#define HALF_MIN_EXP -13 - -#define HALF_RADIX 2 -#define HALF_MAX 0x1.ffcp15h -#define HALF_MIN 0x1.0p-14h -#define HALF_EPSILON 0x1.0p-10h - -#endif - -#endif diff --git a/libclc/generic/include/spirv/integer/gentype.inc b/libclc/generic/include/spirv/integer/gentype.inc deleted file mode 100644 index 869a29b8bf9b3..0000000000000 --- a/libclc/generic/include/spirv/integer/gentype.inc +++ /dev/null @@ -1,539 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -//These 2 defines only change when switching between data sizes or base types to -//keep this file manageable. -#define __SPIRV_GENSIZE 8 -#define __SPIRV_SCALAR_GENTYPE char - -#define __SPIRV_GENTYPE char -#define __SPIRV_U_GENTYPE uchar -#define __SPIRV_S_GENTYPE char -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE char2 -#define __SPIRV_U_GENTYPE uchar2 -#define __SPIRV_S_GENTYPE char2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE char3 -#define __SPIRV_U_GENTYPE uchar3 -#define __SPIRV_S_GENTYPE char3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE char4 -#define __SPIRV_U_GENTYPE uchar4 -#define __SPIRV_S_GENTYPE char4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE char8 -#define __SPIRV_U_GENTYPE uchar8 -#define __SPIRV_S_GENTYPE char8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE char16 -#define __SPIRV_U_GENTYPE uchar16 -#define __SPIRV_S_GENTYPE char16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE uchar - -#define __SPIRV_GENTYPE uchar -#define __SPIRV_U_GENTYPE uchar -#define __SPIRV_S_GENTYPE char -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uchar2 -#define __SPIRV_U_GENTYPE uchar2 -#define __SPIRV_S_GENTYPE char2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uchar3 -#define __SPIRV_U_GENTYPE uchar3 -#define __SPIRV_S_GENTYPE char3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uchar4 -#define __SPIRV_U_GENTYPE uchar4 -#define __SPIRV_S_GENTYPE char4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uchar8 -#define __SPIRV_U_GENTYPE uchar8 -#define __SPIRV_S_GENTYPE char8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uchar16 -#define __SPIRV_U_GENTYPE uchar16 -#define __SPIRV_S_GENTYPE char16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_GENSIZE -#define __SPIRV_GENSIZE 16 -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE short - -#define __SPIRV_GENTYPE short -#define __SPIRV_U_GENTYPE ushort -#define __SPIRV_S_GENTYPE short -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE short2 -#define __SPIRV_U_GENTYPE ushort2 -#define __SPIRV_S_GENTYPE short2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE short3 -#define __SPIRV_U_GENTYPE ushort3 -#define __SPIRV_S_GENTYPE short3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE short4 -#define __SPIRV_U_GENTYPE ushort4 -#define __SPIRV_S_GENTYPE short4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE short8 -#define __SPIRV_U_GENTYPE ushort8 -#define __SPIRV_S_GENTYPE short8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE short16 -#define __SPIRV_U_GENTYPE ushort16 -#define __SPIRV_S_GENTYPE short16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE ushort - -#define __SPIRV_GENTYPE ushort -#define __SPIRV_U_GENTYPE ushort -#define __SPIRV_S_GENTYPE short -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ushort2 -#define __SPIRV_U_GENTYPE ushort2 -#define __SPIRV_S_GENTYPE short2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ushort3 -#define __SPIRV_U_GENTYPE ushort3 -#define __SPIRV_S_GENTYPE short3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ushort4 -#define __SPIRV_U_GENTYPE ushort4 -#define __SPIRV_S_GENTYPE short4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ushort8 -#define __SPIRV_U_GENTYPE ushort8 -#define __SPIRV_S_GENTYPE short8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ushort16 -#define __SPIRV_U_GENTYPE ushort16 -#define __SPIRV_S_GENTYPE short16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_GENSIZE -#define __SPIRV_GENSIZE 32 -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE int - -#define __SPIRV_GENTYPE int -#define __SPIRV_U_GENTYPE uint -#define __SPIRV_S_GENTYPE int -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE int2 -#define __SPIRV_U_GENTYPE uint2 -#define __SPIRV_S_GENTYPE int2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE int3 -#define __SPIRV_U_GENTYPE uint3 -#define __SPIRV_S_GENTYPE int3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE int4 -#define __SPIRV_U_GENTYPE uint4 -#define __SPIRV_S_GENTYPE int4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE int8 -#define __SPIRV_U_GENTYPE uint8 -#define __SPIRV_S_GENTYPE int8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE int16 -#define __SPIRV_U_GENTYPE uint16 -#define __SPIRV_S_GENTYPE int16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE uint - -#define __SPIRV_GENTYPE uint -#define __SPIRV_U_GENTYPE uint -#define __SPIRV_S_GENTYPE int -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uint2 -#define __SPIRV_U_GENTYPE uint2 -#define __SPIRV_S_GENTYPE int2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uint3 -#define __SPIRV_U_GENTYPE uint3 -#define __SPIRV_S_GENTYPE int3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uint4 -#define __SPIRV_U_GENTYPE uint4 -#define __SPIRV_S_GENTYPE int4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uint8 -#define __SPIRV_U_GENTYPE uint8 -#define __SPIRV_S_GENTYPE int8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE uint16 -#define __SPIRV_U_GENTYPE uint16 -#define __SPIRV_S_GENTYPE int16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_GENSIZE -#define __SPIRV_GENSIZE 64 -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE long - -#define __SPIRV_GENTYPE long -#define __SPIRV_U_GENTYPE ulong -#define __SPIRV_S_GENTYPE long -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE long2 -#define __SPIRV_U_GENTYPE ulong2 -#define __SPIRV_S_GENTYPE long2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE long3 -#define __SPIRV_U_GENTYPE ulong3 -#define __SPIRV_S_GENTYPE long3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE long4 -#define __SPIRV_U_GENTYPE ulong4 -#define __SPIRV_S_GENTYPE long4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE long8 -#define __SPIRV_U_GENTYPE ulong8 -#define __SPIRV_S_GENTYPE long8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE long16 -#define __SPIRV_U_GENTYPE ulong16 -#define __SPIRV_S_GENTYPE long16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_SCALAR_GENTYPE -#define __SPIRV_SCALAR_GENTYPE ulong - -#define __SPIRV_GENTYPE ulong -#define __SPIRV_U_GENTYPE ulong -#define __SPIRV_S_GENTYPE long -#define __SPIRV_SCALAR 1 -#define __SPIRV_VECSIZE -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_SCALAR -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ulong2 -#define __SPIRV_U_GENTYPE ulong2 -#define __SPIRV_S_GENTYPE long2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ulong3 -#define __SPIRV_U_GENTYPE ulong3 -#define __SPIRV_S_GENTYPE long3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ulong4 -#define __SPIRV_U_GENTYPE ulong4 -#define __SPIRV_S_GENTYPE long4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ulong8 -#define __SPIRV_U_GENTYPE ulong8 -#define __SPIRV_S_GENTYPE long8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#define __SPIRV_GENTYPE ulong16 -#define __SPIRV_U_GENTYPE ulong16 -#define __SPIRV_S_GENTYPE long16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_U_GENTYPE -#undef __SPIRV_S_GENTYPE - -#undef __SPIRV_GENSIZE -#undef __SPIRV_SCALAR_GENTYPE -#undef __SPIRV_BODY diff --git a/libclc/generic/include/spirv/integer/integer-gentype.inc b/libclc/generic/include/spirv/integer/integer-gentype.inc deleted file mode 100644 index 69369bb6f90db..0000000000000 --- a/libclc/generic/include/spirv/integer/integer-gentype.inc +++ /dev/null @@ -1,55 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_GENTYPE int -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE int2 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE int3 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE int4 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE int8 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE int16 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint2 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint3 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint4 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint8 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE - -#define __SPIRV_GENTYPE uint16 -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE diff --git a/libclc/generic/include/spirv/relational/all.h b/libclc/generic/include/spirv/relational/all.h deleted file mode 100644 index 6830ec8faecaf..0000000000000 --- a/libclc/generic/include/spirv/relational/all.h +++ /dev/null @@ -1,26 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_ALL_DECL(TYPE) \ - _CLC_OVERLOAD _CLC_DECL int __spirv_All(TYPE v); - -#define _SPIRV_VECTOR_ALL_DECL(TYPE) \ - _SPIRV_ALL_DECL(TYPE) \ - _SPIRV_ALL_DECL(TYPE##2) \ - _SPIRV_ALL_DECL(TYPE##3) \ - _SPIRV_ALL_DECL(TYPE##4) \ - _SPIRV_ALL_DECL(TYPE##8) \ - _SPIRV_ALL_DECL(TYPE##16) - -_SPIRV_VECTOR_ALL_DECL(char) -_SPIRV_VECTOR_ALL_DECL(short) -_SPIRV_VECTOR_ALL_DECL(int) -_SPIRV_VECTOR_ALL_DECL(long) - -#undef _SPIRV_ALL_DECL -#undef _SPIRV_VECTOR_ALL_DECL diff --git a/libclc/generic/include/spirv/relational/any.h b/libclc/generic/include/spirv/relational/any.h deleted file mode 100644 index 859e94375f95b..0000000000000 --- a/libclc/generic/include/spirv/relational/any.h +++ /dev/null @@ -1,23 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_ANY_DECL(TYPE) \ - _CLC_OVERLOAD _CLC_DECL int __spirv_Any(TYPE v); - -#define _SPIRV_VECTOR_ANY_DECL(TYPE) \ - _SPIRV_ANY_DECL(TYPE) \ - _SPIRV_ANY_DECL(TYPE##2) \ - _SPIRV_ANY_DECL(TYPE##3) \ - _SPIRV_ANY_DECL(TYPE##4) \ - _SPIRV_ANY_DECL(TYPE##8) \ - _SPIRV_ANY_DECL(TYPE##16) - -_SPIRV_VECTOR_ANY_DECL(char) -_SPIRV_VECTOR_ANY_DECL(short) -_SPIRV_VECTOR_ANY_DECL(int) -_SPIRV_VECTOR_ANY_DECL(long) diff --git a/libclc/generic/include/spirv/relational/floatn.inc b/libclc/generic/include/spirv/relational/floatn.inc deleted file mode 100644 index a7b5d087c90c3..0000000000000 --- a/libclc/generic/include/spirv/relational/floatn.inc +++ /dev/null @@ -1,129 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FLOATN float -#define __SPIRV_INTN int -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN float2 -#define __SPIRV_INTN int2 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN float3 -#define __SPIRV_INTN int3 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN float4 -#define __SPIRV_INTN int4 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN float8 -#define __SPIRV_INTN int8 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN float16 -#define __SPIRV_INTN int16 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#undef __SPIRV_FLOAT -#undef __SPIRV_INT - -#ifdef cl_khr_fp64 -#pragma OPENCL EXTENSION cl_khr_fp64 : enable - -#define __SPIRV_FLOATN double -#define __SPIRV_INTN int -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN double2 -#define __SPIRV_INTN long2 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN double3 -#define __SPIRV_INTN long3 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN double4 -#define __SPIRV_INTN long4 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN double8 -#define __SPIRV_INTN long8 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN double16 -#define __SPIRV_INTN long16 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#endif -#ifdef cl_khr_fp16 -#pragma OPENCL EXTENSION cl_khr_fp16 : enable - -#define __SPIRV_FLOATN half -#define __SPIRV_INTN int -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN half2 -#define __SPIRV_INTN short2 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN half3 -#define __SPIRV_INTN short3 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN half4 -#define __SPIRV_INTN short4 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN half8 -#define __SPIRV_INTN short8 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#define __SPIRV_FLOATN half16 -#define __SPIRV_INTN short16 -#include __SPIRV_BODY -#undef __SPIRV_INTN -#undef __SPIRV_FLOATN - -#endif - -#undef __SPIRV_BODY diff --git a/libclc/generic/include/spirv/relational/isequal.h b/libclc/generic/include/spirv/relational/isequal.h deleted file mode 100644 index 1e7afb68c9445..0000000000000 --- a/libclc/generic/include/spirv/relational/isequal.h +++ /dev/null @@ -1,32 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_ISEQUAL_DECL(TYPE, RETTYPE) \ - _CLC_OVERLOAD _CLC_DECL RETTYPE __spirv_FOrdEqual(TYPE x, TYPE y); - -#define _SPIRV_VECTOR_ISEQUAL_DECL(TYPE, RETTYPE) \ - _SPIRV_ISEQUAL_DECL(TYPE##2, RETTYPE##2) \ - _SPIRV_ISEQUAL_DECL(TYPE##3, RETTYPE##3) \ - _SPIRV_ISEQUAL_DECL(TYPE##4, RETTYPE##4) \ - _SPIRV_ISEQUAL_DECL(TYPE##8, RETTYPE##8) \ - _SPIRV_ISEQUAL_DECL(TYPE##16, RETTYPE##16) - -_SPIRV_ISEQUAL_DECL(float, int) -_SPIRV_VECTOR_ISEQUAL_DECL(float, int) - -#ifdef cl_khr_fp64 -_SPIRV_ISEQUAL_DECL(double, int) -_SPIRV_VECTOR_ISEQUAL_DECL(double, long) -#endif -#ifdef cl_khr_fp16 -_SPIRV_ISEQUAL_DECL(half, int) -_SPIRV_VECTOR_ISEQUAL_DECL(half, short) -#endif - -#undef _SPIRV_ISEQUAL_DECL -#undef _SPIRV_VECTOR_ISEQUAL_DEC diff --git a/libclc/generic/include/spirv/relational/isinf.h b/libclc/generic/include/spirv/relational/isinf.h deleted file mode 100644 index 1e1f6ef1271a5..0000000000000 --- a/libclc/generic/include/spirv/relational/isinf.h +++ /dev/null @@ -1,33 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_ISINF_DECL(RET_TYPE, ARG_TYPE) \ - _CLC_OVERLOAD _CLC_DECL RET_TYPE __spirv_IsInf(ARG_TYPE); - -#define _SPIRV_VECTOR_ISINF_DECL(RET_TYPE, ARG_TYPE) \ - _SPIRV_ISINF_DECL(RET_TYPE##2, ARG_TYPE##2) \ - _SPIRV_ISINF_DECL(RET_TYPE##3, ARG_TYPE##3) \ - _SPIRV_ISINF_DECL(RET_TYPE##4, ARG_TYPE##4) \ - _SPIRV_ISINF_DECL(RET_TYPE##8, ARG_TYPE##8) \ - _SPIRV_ISINF_DECL(RET_TYPE##16, ARG_TYPE##16) - -_SPIRV_ISINF_DECL(int, float) -_SPIRV_VECTOR_ISINF_DECL(int, float) - -#ifdef cl_khr_fp64 -_SPIRV_ISINF_DECL(int, double) -_SPIRV_VECTOR_ISINF_DECL(long, double) -#endif - -#ifdef cl_khr_fp16 -_SPIRV_ISINF_DECL(int, half) -_SPIRV_VECTOR_ISINF_DECL(short, half) -#endif - -#undef _SPIRV_ISINF_DECL -#undef _SPIRV_VECTOR_ISINF_DECL diff --git a/libclc/generic/include/spirv/relational/islessequal.h b/libclc/generic/include/spirv/relational/islessequal.h deleted file mode 100644 index 6144a48bb32df..0000000000000 --- a/libclc/generic/include/spirv/relational/islessequal.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_FOrdLessThanEqual -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/islessgreater.h b/libclc/generic/include/spirv/relational/islessgreater.h deleted file mode 100644 index b2693d43d1fa1..0000000000000 --- a/libclc/generic/include/spirv/relational/islessgreater.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_LessOrGreater -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/isnan.h b/libclc/generic/include/spirv/relational/isnan.h deleted file mode 100644 index 7886796abefd9..0000000000000 --- a/libclc/generic/include/spirv/relational/isnan.h +++ /dev/null @@ -1,33 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_ISNAN_DECL(RET_TYPE, ARG_TYPE) \ - _CLC_OVERLOAD _CLC_DECL RET_TYPE __spirv_IsNan(ARG_TYPE); - -#define _SPIRV_VECTOR_ISNAN_DECL(RET_TYPE, ARG_TYPE) \ - _SPIRV_ISNAN_DECL(RET_TYPE##2, ARG_TYPE##2) \ - _SPIRV_ISNAN_DECL(RET_TYPE##3, ARG_TYPE##3) \ - _SPIRV_ISNAN_DECL(RET_TYPE##4, ARG_TYPE##4) \ - _SPIRV_ISNAN_DECL(RET_TYPE##8, ARG_TYPE##8) \ - _SPIRV_ISNAN_DECL(RET_TYPE##16, ARG_TYPE##16) - -_SPIRV_ISNAN_DECL(int, float) -_SPIRV_VECTOR_ISNAN_DECL(int, float) - -#ifdef cl_khr_fp64 -_SPIRV_ISNAN_DECL(int, double) -_SPIRV_VECTOR_ISNAN_DECL(long, double) -#endif - -#ifdef cl_khr_fp16 -_SPIRV_ISNAN_DECL(int, half) -_SPIRV_VECTOR_ISNAN_DECL(short, half) -#endif - -#undef _SPIRV_ISNAN_DECL -#undef _SPIRV_VECTOR_ISNAN_DECL diff --git a/libclc/generic/include/spirv/relational/isnormal.h b/libclc/generic/include/spirv/relational/isnormal.h deleted file mode 100644 index 280cf770083b3..0000000000000 --- a/libclc/generic/include/spirv/relational/isnormal.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_IsNormal - -#define __SPIRV_FUNCTION __spirv_IsNormal -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/isnotequal.h b/libclc/generic/include/spirv/relational/isnotequal.h deleted file mode 100644 index 2f1183614c7ed..0000000000000 --- a/libclc/generic/include/spirv/relational/isnotequal.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_FUnordNotEqual - -#define __SPIRV_FUNCTION __spirv_FUnordNotEqual -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/isordered.h b/libclc/generic/include/spirv/relational/isordered.h deleted file mode 100644 index 59660a4640ea6..0000000000000 --- a/libclc/generic/include/spirv/relational/isordered.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_Ordered - -#define __SPIRV_FUNCTION __spirv_Ordered -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/isunordered.h b/libclc/generic/include/spirv/relational/isunordered.h deleted file mode 100644 index ab35d14a845eb..0000000000000 --- a/libclc/generic/include/spirv/relational/isunordered.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_Unordered - -#define __SPIRV_FUNCTION __spirv_Unordered -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/relational/select.h b/libclc/generic/include/spirv/relational/select.h deleted file mode 100644 index 1e79c656ddfe5..0000000000000 --- a/libclc/generic/include/spirv/relational/select.h +++ /dev/null @@ -1,19 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -/* Duplicate these so we don't have to distribute utils.h */ -#define __SPIRV_CONCAT(x, y) x ## y -#define __SPIRV_XCONCAT(x, y) __SPIRV_CONCAT(x, y) - -#define __SPIRV_BODY -#include -#define __SPIRV_BODY -#include - -#undef __SPIRV_CONCAT -#undef __SPIRV_XCONCAT diff --git a/libclc/generic/include/spirv/relational/select.inc b/libclc/generic/include/spirv/relational/select.inc deleted file mode 100644 index 50a8fecbe15ff..0000000000000 --- a/libclc/generic/include/spirv/relational/select.inc +++ /dev/null @@ -1,33 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifdef __SPIRV_SCALAR -#define __SPIRV_VECSIZE -#endif - -#if __SPIRV_FPSIZE == 64 -#define __SPIRV_S_GENTYPE __SPIRV_XCONCAT(long, __SPIRV_VECSIZE) -#define __SPIRV_U_GENTYPE __SPIRV_XCONCAT(ulong, __SPIRV_VECSIZE) -#elif __SPIRV_FPSIZE == 32 -#define __SPIRV_S_GENTYPE __SPIRV_XCONCAT(int, __SPIRV_VECSIZE) -#define __SPIRV_U_GENTYPE __SPIRV_XCONCAT(uint, __SPIRV_VECSIZE) -#elif __SPIRV_FPSIZE == 16 -#define __SPIRV_S_GENTYPE __SPIRV_XCONCAT(short, __SPIRV_VECSIZE) -#define __SPIRV_U_GENTYPE __SPIRV_XCONCAT(ushort, __SPIRV_VECSIZE) -#endif - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_select(__SPIRV_GENTYPE x, __SPIRV_GENTYPE y, __SPIRV_S_GENTYPE z); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_select(__SPIRV_GENTYPE x, __SPIRV_GENTYPE y, __SPIRV_U_GENTYPE z); - -#ifdef __SPIRV_FPSIZE -#undef __SPIRV_S_GENTYPE -#undef __SPIRV_U_GENTYPE -#endif -#ifdef __SPIRV_SCALAR -#undef __SPIRV_VECSIZE -#endif diff --git a/libclc/generic/include/spirv/relational/signbit.h b/libclc/generic/include/spirv/relational/signbit.h deleted file mode 100644 index e9488a726461e..0000000000000 --- a/libclc/generic/include/spirv/relational/signbit.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_SignBitSet - -#define __SPIRV_FUNCTION __spirv_SignBitSet -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/spirv.h b/libclc/generic/include/spirv/spirv.h index 3c6e03d205058..6b966a00e0d4a 100644 --- a/libclc/generic/include/spirv/spirv.h +++ b/libclc/generic/include/spirv/spirv.h @@ -167,40 +167,20 @@ #include #include -/* 6.11.6 Relational Functions */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - /* 6.11.11 Atomic Functions */ #include #include #include #include #include +#include #include #include #include +#include #include #include #include -#include -#include /* cl_khr extension atomics are omitted from __spirv */ diff --git a/libclc/generic/include/spirv/spirv_builtins.h b/libclc/generic/include/spirv/spirv_builtins.h index 5e63e7c7cce0b..e7919cf9a9d30 100644 --- a/libclc/generic/include/spirv/spirv_builtins.h +++ b/libclc/generic/include/spirv/spirv_builtins.h @@ -12,6 +12,48 @@ #ifndef CLC_SPIRV_BINDING #define CLC_SPIRV_BINDING +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec8_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec16_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec8_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_All(__clc_vec16_int8_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec8_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec16_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec8_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Any(__clc_vec16_int8_t); + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_BitCount(__clc_char_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t @@ -9244,240 +9286,756 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t #endif #endif -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_char_t __local *, __clc_char_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_char_t __global *, __clc_char_t const __local *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __local *, - __clc_vec2_char_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __global *, - __clc_vec2_char_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __local *, - __clc_vec3_char_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __global *, - __clc_vec3_char_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __local *, - __clc_vec4_char_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __global *, - __clc_vec4_char_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __local *, - __clc_vec8_char_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __global *, - __clc_vec8_char_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __local *, - __clc_vec16_char_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __global *, - __clc_vec16_char_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int8_t __local *, __clc_int8_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int8_t __global *, __clc_int8_t const __local *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __local *, - __clc_vec2_int8_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __global *, - __clc_vec2_int8_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __local *, - __clc_vec3_int8_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __global *, - __clc_vec3_int8_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __local *, - __clc_vec4_int8_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __global *, - __clc_vec4_int8_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __local *, - __clc_vec8_int8_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __global *, - __clc_vec8_int8_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __local *, - __clc_vec16_int8_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __global *, - __clc_vec16_int8_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int16_t __local *, __clc_int16_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int16_t __global *, __clc_int16_t const __local *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __local *, - __clc_vec2_int16_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __global *, - __clc_vec2_int16_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __local *, - __clc_vec3_int16_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __global *, - __clc_vec3_int16_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __local *, - __clc_vec4_int16_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __global *, - __clc_vec4_int16_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __local *, - __clc_vec8_int16_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __global *, - __clc_vec8_int16_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __local *, - __clc_vec16_int16_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __global *, - __clc_vec16_int16_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int32_t __local *, __clc_int32_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int32_t __global *, __clc_int32_t const __local *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __local *, - __clc_vec2_int32_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __global *, - __clc_vec2_int32_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __local *, - __clc_vec3_int32_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __global *, - __clc_vec3_int32_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __local *, - __clc_vec4_int32_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __global *, - __clc_vec4_int32_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __local *, - __clc_vec8_int32_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __global *, - __clc_vec8_int32_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __local *, - __clc_vec16_int32_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __global *, - __clc_vec16_int32_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int64_t __local *, __clc_int64_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_int64_t __global *, __clc_int64_t const __local *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __local *, - __clc_vec2_int64_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __global *, - __clc_vec2_int64_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __local *, - __clc_vec3_int64_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __global *, - __clc_vec3_int64_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __local *, - __clc_vec4_int64_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __global *, - __clc_vec4_int64_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __local *, - __clc_vec8_int64_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __global *, - __clc_vec8_int64_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __local *, - __clc_vec16_int64_t const __global *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t -__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __global *, - __clc_vec16_int64_t const __local *, __clc_size_t, - __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( - __clc_uint32_t, __clc_uint8_t __local *, __clc_uint8_t const __global *, - __clc_size_t, __clc_size_t, __clc_event_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThan(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThan(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThan(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThan(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThan(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThan(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThan(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThan(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThan(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThan(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThan(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThan(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThan(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThan(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThan(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThan(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThan(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThan(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThanEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThanEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdGreaterThanEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdGreaterThanEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThan(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThan(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThan(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThan(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThan(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThan(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThan(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThan(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThan(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThan(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThan(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThan(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThan(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThan(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThan(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThan(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThan(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThan(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThanEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThanEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThanEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThanEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThanEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThanEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThanEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThanEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThanEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThanEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThanEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThanEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdLessThanEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdLessThanEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdLessThanEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdLessThanEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdLessThanEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdLessThanEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdNotEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdNotEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdNotEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdNotEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdNotEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdNotEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdNotEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdNotEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdNotEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdNotEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdNotEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdNotEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FOrdNotEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FOrdNotEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FOrdNotEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FOrdNotEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FOrdNotEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FOrdNotEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThan(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThan(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThan(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThan(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThan(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThan(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThan(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThan(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThan(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThan(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThan(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThan(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThan(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThan(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThan(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThan(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThan(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThan(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThanEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThanEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordGreaterThanEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordGreaterThanEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThan(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThan(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThan(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThan(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThan(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThan(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThan(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThan(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThan(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThan(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThan(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThan(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThan(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThan(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThan(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThan(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThan(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThan(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThanEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThanEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThanEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThanEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThanEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThanEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThanEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThanEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThanEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThanEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThanEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThanEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordLessThanEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordLessThanEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordLessThanEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordLessThanEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordLessThanEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordLessThanEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordNotEqual(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordNotEqual(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordNotEqual(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordNotEqual(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordNotEqual(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordNotEqual(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordNotEqual(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordNotEqual(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordNotEqual(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordNotEqual(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordNotEqual(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordNotEqual(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_FUnordNotEqual(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_FUnordNotEqual(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_FUnordNotEqual(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_FUnordNotEqual(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_FUnordNotEqual(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_FUnordNotEqual(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_char_t __local *, __clc_char_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_char_t __global *, __clc_char_t const __local *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __local *, + __clc_vec2_char_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_char_t __global *, + __clc_vec2_char_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __local *, + __clc_vec3_char_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_char_t __global *, + __clc_vec3_char_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __local *, + __clc_vec4_char_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_char_t __global *, + __clc_vec4_char_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __local *, + __clc_vec8_char_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_char_t __global *, + __clc_vec8_char_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __local *, + __clc_vec16_char_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_char_t __global *, + __clc_vec16_char_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int8_t __local *, __clc_int8_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int8_t __global *, __clc_int8_t const __local *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __local *, + __clc_vec2_int8_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int8_t __global *, + __clc_vec2_int8_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __local *, + __clc_vec3_int8_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int8_t __global *, + __clc_vec3_int8_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __local *, + __clc_vec4_int8_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int8_t __global *, + __clc_vec4_int8_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __local *, + __clc_vec8_int8_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int8_t __global *, + __clc_vec8_int8_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __local *, + __clc_vec16_int8_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int8_t __global *, + __clc_vec16_int8_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int16_t __local *, __clc_int16_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int16_t __global *, __clc_int16_t const __local *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __local *, + __clc_vec2_int16_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int16_t __global *, + __clc_vec2_int16_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __local *, + __clc_vec3_int16_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int16_t __global *, + __clc_vec3_int16_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __local *, + __clc_vec4_int16_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int16_t __global *, + __clc_vec4_int16_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __local *, + __clc_vec8_int16_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int16_t __global *, + __clc_vec8_int16_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __local *, + __clc_vec16_int16_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int16_t __global *, + __clc_vec16_int16_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int32_t __local *, __clc_int32_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int32_t __global *, __clc_int32_t const __local *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __local *, + __clc_vec2_int32_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int32_t __global *, + __clc_vec2_int32_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __local *, + __clc_vec3_int32_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int32_t __global *, + __clc_vec3_int32_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __local *, + __clc_vec4_int32_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int32_t __global *, + __clc_vec4_int32_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __local *, + __clc_vec8_int32_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int32_t __global *, + __clc_vec8_int32_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __local *, + __clc_vec16_int32_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int32_t __global *, + __clc_vec16_int32_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int64_t __local *, __clc_int64_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_int64_t __global *, __clc_int64_t const __local *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __local *, + __clc_vec2_int64_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec2_int64_t __global *, + __clc_vec2_int64_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __local *, + __clc_vec3_int64_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec3_int64_t __global *, + __clc_vec3_int64_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __local *, + __clc_vec4_int64_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec4_int64_t __global *, + __clc_vec4_int64_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __local *, + __clc_vec8_int64_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec8_int64_t __global *, + __clc_vec8_int64_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __local *, + __clc_vec16_int64_t const __global *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t +__spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_int64_t __global *, + __clc_vec16_int64_t const __local *, __clc_size_t, + __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( + __clc_uint32_t, __clc_uint8_t __local *, __clc_uint8_t const __global *, + __clc_size_t, __clc_size_t, __clc_event_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t __spirv_GroupAsyncCopy( __clc_uint32_t, __clc_uint8_t __global *, __clc_uint8_t const __local *, __clc_size_t, __clc_size_t, __clc_event_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT __clc_event_t @@ -9803,12 +10361,264 @@ __spirv_GroupAsyncCopy(__clc_uint32_t, __clc_vec16_fp16_t __global *, __clc_size_t, __clc_event_t); #endif -_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void -__spirv_GroupWaitEvents(__clc_uint32_t, __clc_int32_t, __clc_event_t *); +_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void +__spirv_GroupWaitEvents(__clc_uint32_t, __clc_int32_t, __clc_event_t *); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsFinite(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsFinite(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsFinite(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsFinite(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsFinite(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsFinite(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsFinite(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsFinite(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsFinite(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsFinite(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsFinite(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsFinite(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsFinite(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsFinite(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsFinite(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsFinite(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsFinite(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsFinite(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsInf(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsInf(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsInf(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsInf(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsInf(__clc_vec8_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsInf(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsInf(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsInf(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsInf(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsInf(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsInf(__clc_vec8_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsInf(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsInf(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsInf(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsInf(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsInf(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsInf(__clc_vec8_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsInf(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNan(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsNan(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsNan(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsNan(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsNan(__clc_vec8_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsNan(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNan(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsNan(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsNan(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsNan(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsNan(__clc_vec8_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsNan(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNan(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_IsNan(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_IsNan(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_IsNan(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_IsNan(__clc_vec8_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_IsNan(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNormal(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsNormal(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsNormal(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsNormal(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsNormal(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsNormal(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNormal(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsNormal(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsNormal(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsNormal(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsNormal(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsNormal(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_IsNormal(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_IsNormal(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_IsNormal(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_IsNormal(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_IsNormal(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_IsNormal(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_LessOrGreater(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_LessOrGreater(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_LessOrGreater(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_LessOrGreater(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_LessOrGreater(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_LessOrGreater(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_LessOrGreater(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_LessOrGreater(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_LessOrGreater(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_LessOrGreater(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_LessOrGreater(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_LessOrGreater(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_LessOrGreater(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_LessOrGreater(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_LessOrGreater(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_LessOrGreater(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_LessOrGreater(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_LessOrGreater(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(__clc_uint32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Ordered(__clc_fp32_t, + __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Ordered(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Ordered(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Ordered(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Ordered(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Ordered(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Ordered(__clc_fp64_t, + __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Ordered(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Ordered(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Ordered(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Ordered(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Ordered(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Ordered(__clc_fp16_t, + __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Ordered(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Ordered(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Ordered(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Ordered(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Ordered(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_SConvert_Rchar(__clc_int16_t); _CLC_OVERLOAD @@ -10865,6 +11675,49 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_SatConvertUToS_Rshort8(__clc_vec8_uint64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_SignBitSet(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_SignBitSet(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_SignBitSet(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_SignBitSet(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_SignBitSet(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_SignBitSet(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_SignBitSet(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_SignBitSet(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_SignBitSet(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_SignBitSet(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_SignBitSet(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_SignBitSet(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_SignBitSet(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_SignBitSet(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_SignBitSet(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_SignBitSet(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_SignBitSet(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_SignBitSet(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_UConvert_Ruchar(__clc_int16_t); _CLC_OVERLOAD @@ -11489,6 +12342,200 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_UConvert_Rushort_sat(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_Unordered(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Unordered(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Unordered(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Unordered(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Unordered(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Unordered(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_Unordered(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Unordered(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Unordered(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Unordered(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Unordered(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Unordered(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t + __spirv_Unordered(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_Unordered(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_Unordered(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_Unordered(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_Unordered(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_Unordered(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t + __spirv_ocl_bitselect(__clc_char_t, __clc_char_t, __clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_bitselect( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_bitselect( + __clc_vec3_char_t, __clc_vec3_char_t, __clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_bitselect( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_bitselect( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_bitselect( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t + __spirv_ocl_bitselect(__clc_int8_t, __clc_int8_t, __clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_bitselect( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_bitselect( + __clc_vec3_int8_t, __clc_vec3_int8_t, __clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_bitselect( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_bitselect( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_bitselect( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec16_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int16_t + __spirv_ocl_bitselect(__clc_int16_t, __clc_int16_t, __clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_bitselect( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t __spirv_ocl_bitselect( + __clc_vec3_int16_t, __clc_vec3_int16_t, __clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_bitselect( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_bitselect( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_bitselect( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int32_t + __spirv_ocl_bitselect(__clc_int32_t, __clc_int32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_bitselect( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t __spirv_ocl_bitselect( + __clc_vec3_int32_t, __clc_vec3_int32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_bitselect( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_bitselect( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_bitselect( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int64_t + __spirv_ocl_bitselect(__clc_int64_t, __clc_int64_t, __clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_bitselect( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t __spirv_ocl_bitselect( + __clc_vec3_int64_t, __clc_vec3_int64_t, __clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_bitselect( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_bitselect( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_bitselect( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t + __spirv_ocl_bitselect(__clc_uint8_t, __clc_uint8_t, __clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_bitselect( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t __spirv_ocl_bitselect( + __clc_vec3_uint8_t, __clc_vec3_uint8_t, __clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_bitselect( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_bitselect( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_bitselect( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t + __spirv_ocl_bitselect(__clc_uint16_t, __clc_uint16_t, __clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_bitselect( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t __spirv_ocl_bitselect( + __clc_vec3_uint16_t, __clc_vec3_uint16_t, __clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_bitselect( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_bitselect( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_bitselect( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint32_t + __spirv_ocl_bitselect(__clc_uint32_t, __clc_uint32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_bitselect( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t __spirv_ocl_bitselect( + __clc_vec3_uint32_t, __clc_vec3_uint32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_bitselect( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_bitselect( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_bitselect( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint64_t + __spirv_ocl_bitselect(__clc_uint64_t, __clc_uint64_t, __clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_bitselect( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t __spirv_ocl_bitselect( + __clc_vec3_uint64_t, __clc_vec3_uint64_t, __clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_bitselect( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_bitselect( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_bitselect( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_bitselect(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_bitselect( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_bitselect( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_bitselect( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_bitselect( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_bitselect( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_bitselect(__clc_fp64_t, __clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_bitselect( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_bitselect( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_bitselect( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_bitselect( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_bitselect( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_bitselect(__clc_fp16_t, __clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_bitselect( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_bitselect( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_bitselect( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_bitselect( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_bitselect( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_clz(__clc_char_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_clz(__clc_vec2_char_t); @@ -12766,6 +13813,313 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_s_upsample(__clc_vec16_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t + __spirv_ocl_select(__clc_char_t, __clc_char_t, __clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t + __spirv_ocl_select(__clc_char_t, __clc_char_t, __clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_select(__clc_vec2_char_t, __clc_vec2_char_t, __clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_select( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t + __spirv_ocl_select(__clc_vec3_char_t, __clc_vec3_char_t, __clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_select( + __clc_vec3_char_t, __clc_vec3_char_t, __clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_select(__clc_vec4_char_t, __clc_vec4_char_t, __clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_select( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_select(__clc_vec8_char_t, __clc_vec8_char_t, __clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_select( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_select( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_select( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t + __spirv_ocl_select(__clc_int8_t, __clc_int8_t, __clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t + __spirv_ocl_select(__clc_int8_t, __clc_int8_t, __clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_select(__clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_select( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_ocl_select(__clc_vec3_int8_t, __clc_vec3_int8_t, __clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_select( + __clc_vec3_int8_t, __clc_vec3_int8_t, __clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_select(__clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_select( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_select(__clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_select( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_select( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec16_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_select( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int16_t + __spirv_ocl_select(__clc_int16_t, __clc_int16_t, __clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int16_t + __spirv_ocl_select(__clc_int16_t, __clc_int16_t, __clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_select( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_select( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t __spirv_ocl_select( + __clc_vec3_int16_t, __clc_vec3_int16_t, __clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t __spirv_ocl_select( + __clc_vec3_int16_t, __clc_vec3_int16_t, __clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_select( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_select( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_select( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_select( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_select( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_select( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int32_t + __spirv_ocl_select(__clc_int32_t, __clc_int32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int32_t + __spirv_ocl_select(__clc_int32_t, __clc_int32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_select( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_select( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t __spirv_ocl_select( + __clc_vec3_int32_t, __clc_vec3_int32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t __spirv_ocl_select( + __clc_vec3_int32_t, __clc_vec3_int32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_select( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_select( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_select( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_select( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_select( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_select( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int64_t + __spirv_ocl_select(__clc_int64_t, __clc_int64_t, __clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int64_t + __spirv_ocl_select(__clc_int64_t, __clc_int64_t, __clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_select( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_select( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t __spirv_ocl_select( + __clc_vec3_int64_t, __clc_vec3_int64_t, __clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t __spirv_ocl_select( + __clc_vec3_int64_t, __clc_vec3_int64_t, __clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_select( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_select( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_select( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_select( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_select( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_select( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t + __spirv_ocl_select(__clc_uint8_t, __clc_uint8_t, __clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t + __spirv_ocl_select(__clc_uint8_t, __clc_uint8_t, __clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t + __spirv_ocl_select(__clc_uint8_t, __clc_uint8_t, __clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_select( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_select( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_select( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t __spirv_ocl_select( + __clc_vec3_uint8_t, __clc_vec3_uint8_t, __clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t __spirv_ocl_select( + __clc_vec3_uint8_t, __clc_vec3_uint8_t, __clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t __spirv_ocl_select( + __clc_vec3_uint8_t, __clc_vec3_uint8_t, __clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_select( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_select( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_select( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_select( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_select( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_select( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_select( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_select( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec16_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_select( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t + __spirv_ocl_select(__clc_uint16_t, __clc_uint16_t, __clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t + __spirv_ocl_select(__clc_uint16_t, __clc_uint16_t, __clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_select( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_select( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t __spirv_ocl_select( + __clc_vec3_uint16_t, __clc_vec3_uint16_t, __clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t __spirv_ocl_select( + __clc_vec3_uint16_t, __clc_vec3_uint16_t, __clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_select( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_select( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_select( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_select( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_select( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_select( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint32_t + __spirv_ocl_select(__clc_uint32_t, __clc_uint32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint32_t + __spirv_ocl_select(__clc_uint32_t, __clc_uint32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_select( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_select( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t __spirv_ocl_select( + __clc_vec3_uint32_t, __clc_vec3_uint32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t __spirv_ocl_select( + __clc_vec3_uint32_t, __clc_vec3_uint32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_select( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_select( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_select( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_select( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_select( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_select( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint64_t + __spirv_ocl_select(__clc_uint64_t, __clc_uint64_t, __clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint64_t + __spirv_ocl_select(__clc_uint64_t, __clc_uint64_t, __clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_select( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_select( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t __spirv_ocl_select( + __clc_vec3_uint64_t, __clc_vec3_uint64_t, __clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t __spirv_ocl_select( + __clc_vec3_uint64_t, __clc_vec3_uint64_t, __clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_select( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_select( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_select( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_select( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_select( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_select( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_select(__clc_fp32_t, __clc_fp32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_select(__clc_fp32_t, __clc_fp32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_select( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_select( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_select( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_select( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_select( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_select( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_select( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_select( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_select( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_select( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_uint32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_select(__clc_fp64_t, __clc_fp64_t, __clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_select(__clc_fp64_t, __clc_fp64_t, __clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_select( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_select( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_select( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_select( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_select( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_select( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_select( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_select( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_select( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_select( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_uint64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_select(__clc_fp16_t, __clc_fp16_t, __clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_select(__clc_fp16_t, __clc_fp16_t, __clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_select( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_select( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_select( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_select( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_select( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_select( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_select( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_select( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_select( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_select( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_uint16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_u_abs(__clc_uint8_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t diff --git a/libclc/generic/libspirv/SOURCES b/libclc/generic/libspirv/SOURCES index 7189035ae092d..6676ff1fa5f59 100644 --- a/libclc/generic/libspirv/SOURCES +++ b/libclc/generic/libspirv/SOURCES @@ -104,8 +104,24 @@ math/sinpi.cl math/sqrt.cl math/tables.cl math/trunc.cl +relational/all.cl +relational/any.cl +relational/bitselect.cl +relational/isequal.cl +relational/isfinite.cl +relational/isgreater.cl +relational/isgreaterequal.cl relational/isinf.cl +relational/isless.cl +relational/islessequal.cl +relational/islessgreater.cl relational/isnan.cl +relational/isnormal.cl +relational/isnotequal.cl +relational/isordered.cl +relational/isunordered.cl +relational/select.cl +relational/signbit.cl shared/clamp.cl shared/max.cl shared/min.cl diff --git a/libclc/generic/libspirv/math/fract.cl b/libclc/generic/libspirv/math/fract.cl index cca55c7a60bbe..93b2f97683bb8 100644 --- a/libclc/generic/libspirv/math/fract.cl +++ b/libclc/generic/libspirv/math/fract.cl @@ -21,6 +21,7 @@ */ #include +#include #define __CLC_BODY #include diff --git a/libclc/generic/libspirv/math/fract.inc b/libclc/generic/libspirv/math/fract.inc index e7ff1958cdf50..55fbe4edaad39 100644 --- a/libclc/generic/libspirv/math/fract.inc +++ b/libclc/generic/libspirv/math/fract.inc @@ -8,34 +8,46 @@ #if __CLC_FPSIZE == 64 #define MIN_CONSTANT 0x1.fffffffffffffp-1 -#define ZERO 0.0 +#define ZERO (__CLC_GENTYPE)0.0 +#define __CLC_BOOLN __CLC_XCONCAT(long, __CLC_VECSIZE) #elif __CLC_FPSIZE == 32 #define MIN_CONSTANT 0x1.fffffep-1f -#define ZERO 0.0f +#define ZERO (__CLC_GENTYPE)0.0f +#define __CLC_BOOLN __CLC_XCONCAT(int, __CLC_VECSIZE) #elif __CLC_FPSIZE == 16 #define MIN_CONSTANT 0x1.ffcp-1h -#define ZERO 0.0h +#define ZERO (__CLC_GENTYPE)0.0h +#define __CLC_BOOLN __CLC_XCONCAT(short, __CLC_VECSIZE) #endif -_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fract(__CLC_GENTYPE x, private __CLC_GENTYPE *iptr) { +#ifdef __CLC_SCALAR +#define __CLC_CONVERT +#else +#define __CLC_CONVERT __CLC_XCONCAT(__spirv_SConvert_R, __CLC_BOOLN) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_fract(__CLC_GENTYPE x, private __CLC_GENTYPE *iptr) { *iptr = __spirv_ocl_floor(x); __CLC_GENTYPE r = __spirv_ocl_fmin(x - *iptr, MIN_CONSTANT); - r = __spirv_IsInf(x) ? ZERO : r; - r = __spirv_IsNan(x) ? x : r; + r = __CLC_CONVERT(__spirv_IsInf(x)) ? ZERO : r; + r = __CLC_CONVERT(__spirv_IsNan(x)) ? x : r; return r; } - -#define FRACT_DEF(addrspace) \ - _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fract(__CLC_GENTYPE x, addrspace __CLC_GENTYPE *iptr) { \ - __CLC_GENTYPE private_iptr; \ - __CLC_GENTYPE ret = __spirv_ocl_fract(x, &private_iptr); \ - *iptr = private_iptr; \ - return ret; \ - } +#define FRACT_DEF(addrspace) \ + _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fract( \ + __CLC_GENTYPE x, addrspace __CLC_GENTYPE *iptr) { \ + __CLC_GENTYPE private_iptr; \ + __CLC_GENTYPE ret = __spirv_ocl_fract(x, &private_iptr); \ + *iptr = private_iptr; \ + return ret; \ + } FRACT_DEF(local); FRACT_DEF(global); #undef MIN_CONSTANT #undef ZERO +#undef __CLC_CONVERT +#undef __CLC_BOOLN diff --git a/libclc/generic/libspirv/relational/all.cl b/libclc/generic/libspirv/relational/all.cl new file mode 100644 index 0000000000000..f611c59b8e216 --- /dev/null +++ b/libclc/generic/libspirv/relational/all.cl @@ -0,0 +1,34 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define _CLC_ALL(v) (((v) >> ((sizeof(v) * 8) - 1)) & 0x1) +#define _CLC_ALL2(v) (_CLC_ALL((v).s0) & _CLC_ALL((v).s1)) +#define _CLC_ALL3(v) (_CLC_ALL2((v)) & _CLC_ALL((v).s2)) +#define _CLC_ALL4(v) (_CLC_ALL3((v)) & _CLC_ALL((v).s3)) +#define _CLC_ALL8(v) \ + (_CLC_ALL4((v)) & _CLC_ALL((v).s4) & _CLC_ALL((v).s5) & _CLC_ALL((v).s6) & \ + _CLC_ALL((v).s7)) +#define _CLC_ALL16(v) \ + (_CLC_ALL8((v)) & _CLC_ALL((v).s8) & _CLC_ALL((v).s9) & _CLC_ALL((v).sA) & \ + _CLC_ALL((v).sB) & _CLC_ALL((v).sC) & _CLC_ALL((v).sD) & _CLC_ALL((v).sE) & \ + _CLC_ALL((v).sf)) + +#define ALL_ID(TYPE) _CLC_OVERLOAD _CLC_DEF bool __spirv_All(TYPE v) + +bool __spirv_All(bool v) { return v; } + +#define ALL_VECTORIZE(TYPE) \ + ALL_ID(TYPE##2) { return _CLC_ALL2(v); } \ + ALL_ID(TYPE##3) { return _CLC_ALL3(v); } \ + ALL_ID(TYPE##4) { return _CLC_ALL4(v); } \ + ALL_ID(TYPE##8) { return _CLC_ALL8(v); } \ + ALL_ID(TYPE##16) { return _CLC_ALL16(v); } + +ALL_VECTORIZE(schar) diff --git a/libclc/generic/libspirv/relational/any.cl b/libclc/generic/libspirv/relational/any.cl new file mode 100644 index 0000000000000..5885f48361533 --- /dev/null +++ b/libclc/generic/libspirv/relational/any.cl @@ -0,0 +1,34 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define _CLC_ANY(v) (((v) >> ((sizeof(v) * 8) - 1)) & 0x1) +#define _CLC_ANY2(v) (_CLC_ANY((v).s0) | _CLC_ANY((v).s1)) +#define _CLC_ANY3(v) (_CLC_ANY2((v)) | _CLC_ANY((v).s2)) +#define _CLC_ANY4(v) (_CLC_ANY3((v)) | _CLC_ANY((v).s3)) +#define _CLC_ANY8(v) \ + (_CLC_ANY4((v)) | _CLC_ANY((v).s4) | _CLC_ANY((v).s5) | _CLC_ANY((v).s6) | \ + _CLC_ANY((v).s7)) +#define _CLC_ANY16(v) \ + (_CLC_ANY8((v)) | _CLC_ANY((v).s8) | _CLC_ANY((v).s9) | _CLC_ANY((v).sA) | \ + _CLC_ANY((v).sB) | _CLC_ANY((v).sC) | _CLC_ANY((v).sD) | _CLC_ANY((v).sE) | \ + _CLC_ANY((v).sf)) + +#define ANY_ID(TYPE) _CLC_OVERLOAD _CLC_DEF bool __spirv_Any(TYPE v) + +bool __spirv_Any(bool v) { return v; } + +#define ANY_VECTORIZE(TYPE) \ + ANY_ID(TYPE##2) { return _CLC_ANY2(v); } \ + ANY_ID(TYPE##3) { return _CLC_ANY3(v); } \ + ANY_ID(TYPE##4) { return _CLC_ANY4(v); } \ + ANY_ID(TYPE##8) { return _CLC_ANY8(v); } \ + ANY_ID(TYPE##16) { return _CLC_ANY16(v); } + +ANY_VECTORIZE(schar) diff --git a/libclc/generic/libspirv/relational/bitselect.cl b/libclc/generic/libspirv/relational/bitselect.cl new file mode 100644 index 0000000000000..ee89d13f27630 --- /dev/null +++ b/libclc/generic/libspirv/relational/bitselect.cl @@ -0,0 +1,53 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_BODY +#include +#undef __CLC_BODY + +#define FLOAT_BITSELECT(f_type, i_type, width) \ + _CLC_OVERLOAD _CLC_DEF f_type##width __spirv_ocl_bitselect( \ + f_type##width x, f_type##width y, f_type##width z) { \ + return as_##f_type##width(__spirv_ocl_bitselect( \ + as_##i_type##width(x), as_##i_type##width(y), as_##i_type##width(z))); \ + } + +FLOAT_BITSELECT(float, uint, ) +FLOAT_BITSELECT(float, uint, 2) +FLOAT_BITSELECT(float, uint, 3) +FLOAT_BITSELECT(float, uint, 4) +FLOAT_BITSELECT(float, uint, 8) +FLOAT_BITSELECT(float, uint, 16) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +FLOAT_BITSELECT(double, ulong, ) +FLOAT_BITSELECT(double, ulong, 2) +FLOAT_BITSELECT(double, ulong, 3) +FLOAT_BITSELECT(double, ulong, 4) +FLOAT_BITSELECT(double, ulong, 8) +FLOAT_BITSELECT(double, ulong, 16) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +FLOAT_BITSELECT(half, ushort, ) +FLOAT_BITSELECT(half, ushort, 2) +FLOAT_BITSELECT(half, ushort, 3) +FLOAT_BITSELECT(half, ushort, 4) +FLOAT_BITSELECT(half, ushort, 8) +FLOAT_BITSELECT(half, ushort, 16) + +#endif diff --git a/libclc/generic/include/spirv/relational/bitselect.h b/libclc/generic/libspirv/relational/bitselect.inc similarity index 57% rename from libclc/generic/include/spirv/relational/bitselect.h rename to libclc/generic/libspirv/relational/bitselect.inc index 20a0e4f9dd462..939b3c9650593 100644 --- a/libclc/generic/include/spirv/relational/bitselect.h +++ b/libclc/generic/libspirv/relational/bitselect.inc @@ -6,9 +6,8 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#include -#define __SPIRV_BODY -#include - -#undef __SPIRV_BODY +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_bitselect(__CLC_GENTYPE x, + __CLC_GENTYPE y, + __CLC_GENTYPE z) { + return ((x) ^ ((z) & ((y) ^ (x)))); +} diff --git a/libclc/generic/libspirv/relational/genbinrelational.inc b/libclc/generic/libspirv/relational/genbinrelational.inc new file mode 100644 index 0000000000000..14a41401839ac --- /dev/null +++ b/libclc/generic/libspirv/relational/genbinrelational.inc @@ -0,0 +1,31 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +_CLC_DEFINE_RELATIONAL_BINARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, + _CLC_BUILTIN_IMPL, float, float) +_CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, float, float) + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_DEFINE_RELATIONAL_BINARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, + _CLC_BUILTIN_IMPL, double, double) +_CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, double, double) + +#endif + +#ifdef cl_khr_fp16 + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEFINE_RELATIONAL_BINARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, + _CLC_BUILTIN_IMPL, half, half) +_CLC_DEFINE_RELATIONAL_BINARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, half, half) + +#endif diff --git a/libclc/generic/libspirv/relational/genunary.inc b/libclc/generic/libspirv/relational/genunary.inc new file mode 100644 index 0000000000000..80137ca3bc629 --- /dev/null +++ b/libclc/generic/libspirv/relational/genunary.inc @@ -0,0 +1,30 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +_CLC_DEFINE_RELATIONAL_UNARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, _CLC_BUILTIN_IMPL, + float) +_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, float) + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_DEFINE_RELATIONAL_UNARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, _CLC_BUILTIN_IMPL, + double) +_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, double) + +#endif +#ifdef cl_khr_fp16 + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEFINE_RELATIONAL_UNARY_SCALAR(bool, _CLC_SPIRV_BUILTIN, _CLC_BUILTIN_IMPL, + half) +_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(schar, _CLC_SPIRV_BUILTIN, half) + +#endif diff --git a/libclc/generic/libspirv/relational/isequal.cl b/libclc/generic/libspirv/relational/isequal.cl new file mode 100644 index 0000000000000..8d4158a1d3722 --- /dev/null +++ b/libclc/generic/libspirv/relational/isequal.cl @@ -0,0 +1,20 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_FUnordEqual +#define _CLC_BUILTIN_IMPL(X, Y) ((__spirv_Unordered(X, Y)) || (X == Y)) +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL + +#define _CLC_SPIRV_BUILTIN __spirv_FOrdEqual +#define _CLC_BUILTIN_IMPL(X, Y) ((__spirv_Ordered(X, Y)) && (X == Y)) +#include "genbinrelational.inc" diff --git a/libclc/generic/include/spirv/relational/unary_decl.inc b/libclc/generic/libspirv/relational/isfinite.cl similarity index 69% rename from libclc/generic/include/spirv/relational/unary_decl.inc rename to libclc/generic/libspirv/relational/isfinite.cl index a4f79d050bc27..39240689334d6 100644 --- a/libclc/generic/include/spirv/relational/unary_decl.inc +++ b/libclc/generic/libspirv/relational/isfinite.cl @@ -6,4 +6,9 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_INTN __SPIRV_FUNCTION(__SPIRV_FLOATN x); +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_IsFinite +#define _CLC_BUILTIN_IMPL __builtin_isfinite +#include "genunary.inc" diff --git a/libclc/generic/include/spirv/relational/isfinite.h b/libclc/generic/libspirv/relational/isgreater.cl similarity index 51% rename from libclc/generic/include/spirv/relational/isfinite.h rename to libclc/generic/libspirv/relational/isgreater.cl index bad4968126f87..e8612dede4b47 100644 --- a/libclc/generic/include/spirv/relational/isfinite.h +++ b/libclc/generic/libspirv/relational/isgreater.cl @@ -6,12 +6,15 @@ // //===----------------------------------------------------------------------===// -#undef __spirv_IsFinite +#include +#include -#define __SPIRV_FUNCTION __spirv_IsFinite -#define __SPIRV_BODY +#define _CLC_SPIRV_BUILTIN __spirv_FOrdGreaterThan +#define _CLC_BUILTIN_IMPL __builtin_isgreater +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define _CLC_SPIRV_BUILTIN __spirv_FUnordGreaterThan +#define _CLC_BUILTIN_IMPL(X, Y) X > Y +#include "genbinrelational.inc" diff --git a/libclc/generic/include/spirv/relational/isgreaterequal.h b/libclc/generic/libspirv/relational/isgreaterequal.cl similarity index 50% rename from libclc/generic/include/spirv/relational/isgreaterequal.h rename to libclc/generic/libspirv/relational/isgreaterequal.cl index 01465c8d75e75..1c046b93b6975 100644 --- a/libclc/generic/include/spirv/relational/isgreaterequal.h +++ b/libclc/generic/libspirv/relational/isgreaterequal.cl @@ -6,12 +6,15 @@ // //===----------------------------------------------------------------------===// -#undef __spirv_FOrdGreaterThanEqual +#include +#include -#define __SPIRV_FUNCTION __spirv_FOrdGreaterThanEqual -#define __SPIRV_BODY +#define _CLC_SPIRV_BUILTIN __spirv_FOrdGreaterThanEqual +#define _CLC_BUILTIN_IMPL __builtin_isgreaterequal +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define _CLC_SPIRV_BUILTIN __spirv_FUnordGreaterThanEqual +#define _CLC_BUILTIN_IMPL(X, Y) X >= Y +#include "genbinrelational.inc" diff --git a/libclc/generic/libspirv/relational/isinf.cl b/libclc/generic/libspirv/relational/isinf.cl index 9e23bd48ef159..0e3ccfcf4ad76 100644 --- a/libclc/generic/libspirv/relational/isinf.cl +++ b/libclc/generic/libspirv/relational/isinf.cl @@ -6,33 +6,9 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "relational.h" -_CLC_DEFINE_RELATIONAL_UNARY(int, __spirv_IsInf, __builtin_isinf, float) - -#ifdef cl_khr_fp64 - -#pragma OPENCL EXTENSION cl_khr_fp64 : enable - -// The scalar version of isinf(double) returns an int, but the vector versions -// return long. -_CLC_DEF _CLC_OVERLOAD int __spirv_IsInf(double x) { - return __builtin_isinf(x); -} - -_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(long, __spirv_IsInf, double) -#endif - -#ifdef cl_khr_fp16 - -#pragma OPENCL EXTENSION cl_khr_fp16 : enable - -// The scalar version of isinf(half) returns an int, but the vector versions -// return short. -_CLC_DEF _CLC_OVERLOAD int __spirv_IsInf(half x) { - return __builtin_isinf(x); -} - -_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(short, __spirv_IsInf, half) -#endif +#define _CLC_SPIRV_BUILTIN __spirv_IsInf +#define _CLC_BUILTIN_IMPL __builtin_isinf +#include "genunary.inc" diff --git a/libclc/generic/include/spirv/relational/isless.h b/libclc/generic/libspirv/relational/isless.cl similarity index 52% rename from libclc/generic/include/spirv/relational/isless.h rename to libclc/generic/libspirv/relational/isless.cl index e482d35cdca37..16b436b091c3a 100644 --- a/libclc/generic/include/spirv/relational/isless.h +++ b/libclc/generic/libspirv/relational/isless.cl @@ -6,10 +6,15 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_FUNCTION __spirv_FOrdLessThan -#define __SPIRV_BODY +#include +#include -#include +#define _CLC_SPIRV_BUILTIN __spirv_FOrdLessThan +#define _CLC_BUILTIN_IMPL __builtin_isless +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define _CLC_SPIRV_BUILTIN __spirv_FUnordLessThan +#define _CLC_BUILTIN_IMPL(X, Y) X < Y +#include "genbinrelational.inc" diff --git a/libclc/generic/include/spirv/relational/isgreater.h b/libclc/generic/libspirv/relational/islessequal.cl similarity index 50% rename from libclc/generic/include/spirv/relational/isgreater.h rename to libclc/generic/libspirv/relational/islessequal.cl index 0fce32f42268f..cebdcf6651a2f 100644 --- a/libclc/generic/include/spirv/relational/isgreater.h +++ b/libclc/generic/libspirv/relational/islessequal.cl @@ -6,12 +6,15 @@ // //===----------------------------------------------------------------------===// -#undef __spirv_FOrdGreaterThan +#include +#include -#define __SPIRV_FUNCTION __spirv_FOrdGreaterThan -#define __SPIRV_BODY +#define _CLC_SPIRV_BUILTIN __spirv_FOrdLessThanEqual +#define _CLC_BUILTIN_IMPL __builtin_islessequal +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define _CLC_SPIRV_BUILTIN __spirv_FUnordLessThanEqual +#define _CLC_BUILTIN_IMPL(X, Y) X <= Y +#include "genbinrelational.inc" diff --git a/libclc/generic/libspirv/relational/islessgreater.cl b/libclc/generic/libspirv/relational/islessgreater.cl new file mode 100644 index 0000000000000..fe70f62c7cbea --- /dev/null +++ b/libclc/generic/libspirv/relational/islessgreater.cl @@ -0,0 +1,14 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_LessOrGreater +#define _CLC_BUILTIN_IMPL __spirv_FOrdNotEqual +#include "genbinrelational.inc" diff --git a/libclc/generic/libspirv/relational/isnan.cl b/libclc/generic/libspirv/relational/isnan.cl index 9876cb9febffa..5251f7a442e58 100644 --- a/libclc/generic/libspirv/relational/isnan.cl +++ b/libclc/generic/libspirv/relational/isnan.cl @@ -6,35 +6,9 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "relational.h" -_CLC_DEFINE_RELATIONAL_UNARY(int, __spirv_IsNan, __builtin_isnan, float) - -#ifdef cl_khr_fp64 - -#pragma OPENCL EXTENSION cl_khr_fp64 : enable - -// The scalar version of isnan(double) returns an int, but the vector versions -// return long. -_CLC_DEF _CLC_OVERLOAD int __spirv_IsNan(double x) { - return __builtin_isnan(x); -} - -_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(long, __spirv_IsNan, double) - -#endif - -#ifdef cl_khr_fp16 - -#pragma OPENCL EXTENSION cl_khr_fp16 : enable - -// The scalar version of isnan(half) returns an int, but the vector versions -// return short. -_CLC_DEF _CLC_OVERLOAD int __spirv_IsNan(half x) { - return __builtin_isnan(x); -} - -_CLC_DEFINE_RELATIONAL_UNARY_VEC_ALL(short, __spirv_IsNan, half) - -#endif +#define _CLC_SPIRV_BUILTIN __spirv_IsNan +#define _CLC_BUILTIN_IMPL __builtin_isnan +#include "genunary.inc" diff --git a/libclc/generic/include/spirv/relational/bitselect.inc b/libclc/generic/libspirv/relational/isnormal.cl similarity index 69% rename from libclc/generic/include/spirv/relational/bitselect.inc rename to libclc/generic/libspirv/relational/isnormal.cl index 561558b605cea..ed546b3cd3ab4 100644 --- a/libclc/generic/include/spirv/relational/bitselect.inc +++ b/libclc/generic/libspirv/relational/isnormal.cl @@ -6,4 +6,9 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_bitselect(__SPIRV_GENTYPE x, __SPIRV_GENTYPE y, __SPIRV_GENTYPE z); +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_IsNormal +#define _CLC_BUILTIN_IMPL __builtin_isnormal +#include "genunary.inc" diff --git a/libclc/generic/libspirv/relational/isnotequal.cl b/libclc/generic/libspirv/relational/isnotequal.cl new file mode 100644 index 0000000000000..07aab633073be --- /dev/null +++ b/libclc/generic/libspirv/relational/isnotequal.cl @@ -0,0 +1,20 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_FUnordNotEqual +#define _CLC_BUILTIN_IMPL(X, Y) ((__spirv_Unordered(X, Y)) || (X != Y)) +#include "genbinrelational.inc" +#undef _CLC_SPIRV_BUILTIN +#undef _CLC_BUILTIN_IMPL + +#define _CLC_SPIRV_BUILTIN __spirv_FOrdNotEqual +#define _CLC_BUILTIN_IMPL(X, Y) ((__spirv_Ordered(X, Y)) && (X != Y)) +#include "genbinrelational.inc" diff --git a/libclc/generic/libspirv/relational/isordered.cl b/libclc/generic/libspirv/relational/isordered.cl new file mode 100644 index 0000000000000..b741026dc3ec3 --- /dev/null +++ b/libclc/generic/libspirv/relational/isordered.cl @@ -0,0 +1,14 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_Ordered +#define _CLC_BUILTIN_IMPL(X, Y) !__spirv_Unordered(x, y) +#include "genbinrelational.inc" diff --git a/libclc/generic/include/spirv/integer/unary.inc b/libclc/generic/libspirv/relational/isunordered.cl similarity index 67% rename from libclc/generic/include/spirv/integer/unary.inc rename to libclc/generic/libspirv/relational/isunordered.cl index ed40a507bb317..5214b2e171d9b 100644 --- a/libclc/generic/include/spirv/integer/unary.inc +++ b/libclc/generic/libspirv/relational/isunordered.cl @@ -6,4 +6,9 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE x); +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_Unordered +#define _CLC_BUILTIN_IMPL __builtin_isunordered +#include "genbinrelational.inc" diff --git a/libclc/generic/libspirv/relational/select.cl b/libclc/generic/libspirv/relational/select.cl new file mode 100644 index 0000000000000..dfc93df1d835c --- /dev/null +++ b/libclc/generic/libspirv/relational/select.cl @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define __CLC_BODY +#include +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/relational/select.inc b/libclc/generic/libspirv/relational/select.inc new file mode 100644 index 0000000000000..8cbeca8ff92be --- /dev/null +++ b/libclc/generic/libspirv/relational/select.inc @@ -0,0 +1,35 @@ +#ifdef __CLC_SCALAR +#define __CLC_VECSIZE +#endif + +#if __CLC_FPSIZE == 64 +#define __CLC_S_GENTYPE __CLC_XCONCAT(long, __CLC_VECSIZE) +#define __CLC_U_GENTYPE __CLC_XCONCAT(ulong, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 32 +#define __CLC_S_GENTYPE __CLC_XCONCAT(int, __CLC_VECSIZE) +#define __CLC_U_GENTYPE __CLC_XCONCAT(uint, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 16 +#define __CLC_S_GENTYPE __CLC_XCONCAT(short, __CLC_VECSIZE) +#define __CLC_U_GENTYPE __CLC_XCONCAT(ushort, __CLC_VECSIZE) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_select(__CLC_GENTYPE x, + __CLC_GENTYPE y, + __CLC_S_GENTYPE z) { + return z ? y : x; +} + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_select(__CLC_GENTYPE x, + __CLC_GENTYPE y, + __CLC_U_GENTYPE z) { + return z ? y : x; +} + +#ifdef __CLC_FPSIZE +#undef __CLC_S_GENTYPE +#undef __CLC_U_GENTYPE +#endif + +#ifdef __CLC_SCALAR +#undef __CLC_VECSIZE +#endif diff --git a/libclc/generic/include/spirv/relational/binary_decl.inc b/libclc/generic/libspirv/relational/signbit.cl similarity index 69% rename from libclc/generic/include/spirv/relational/binary_decl.inc rename to libclc/generic/libspirv/relational/signbit.cl index 164ba2f741667..0c0dd1106dd21 100644 --- a/libclc/generic/include/spirv/relational/binary_decl.inc +++ b/libclc/generic/libspirv/relational/signbit.cl @@ -6,4 +6,9 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_INTN __SPIRV_FUNCTION(__SPIRV_FLOATN a, __SPIRV_FLOATN b); +#include +#include + +#define _CLC_SPIRV_BUILTIN __spirv_SignBitSet +#define _CLC_BUILTIN_IMPL __builtin_signbitf +#include "genunary.inc" diff --git a/libclc/test/binding/core/All.cl b/libclc/test/binding/core/All.cl new file mode 100644 index 0000000000000..79619baafb4c1 --- /dev/null +++ b/libclc/test/binding/core/All.cl @@ -0,0 +1,41 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_All(__clc_vec2_int8_t args_0) { + return __spirv_All(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_All(__clc_vec3_int8_t args_0) { + return __spirv_All(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_All(__clc_vec4_int8_t args_0) { + return __spirv_All(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_All(__clc_vec8_int8_t args_0) { + return __spirv_All(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_All(__clc_vec16_int8_t args_0) { + return __spirv_All(args_0); +} diff --git a/libclc/test/binding/core/Any.cl b/libclc/test/binding/core/Any.cl new file mode 100644 index 0000000000000..896c0386f99a1 --- /dev/null +++ b/libclc/test/binding/core/Any.cl @@ -0,0 +1,41 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_Any(__clc_vec2_int8_t args_0) { + return __spirv_Any(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_Any(__clc_vec3_int8_t args_0) { + return __spirv_Any(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_Any(__clc_vec4_int8_t args_0) { + return __spirv_Any(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_Any(__clc_vec8_int8_t args_0) { + return __spirv_Any(args_0); +} + +__attribute__((overloadable)) __clc_bool_t +test___spirv_Any(__clc_vec16_int8_t args_0) { + return __spirv_Any(args_0); +} diff --git a/libclc/test/binding/core/FOrdEqual.cl b/libclc/test/binding/core/FOrdEqual.cl new file mode 100644 index 0000000000000..0a00f2a1dadee --- /dev/null +++ b/libclc/test/binding/core/FOrdEqual.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdEqual(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdEqual(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdEqual(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdEqual(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdEqual(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdEqual(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdEqual(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdEqual(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdEqual(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdEqual(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdEqual(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdEqual(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdEqual(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdEqual(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdEqual(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_FOrdEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FOrdGreaterThan.cl b/libclc/test/binding/core/FOrdGreaterThan.cl new file mode 100644 index 0000000000000..201193935e917 --- /dev/null +++ b/libclc/test/binding/core/FOrdGreaterThan.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThan(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThan(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThan(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThan(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThan(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThan(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThan(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThan(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThan(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThan(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThan(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThan(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThan(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThan(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThan(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThan(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThan(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThan(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FOrdGreaterThan(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FOrdGreaterThanEqual.cl b/libclc/test/binding/core/FOrdGreaterThanEqual.cl new file mode 100644 index 0000000000000..1e5fdaa737c05 --- /dev/null +++ b/libclc/test/binding/core/FOrdGreaterThanEqual.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThanEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThanEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdGreaterThanEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdGreaterThanEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FOrdGreaterThanEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FOrdLessThan.cl b/libclc/test/binding/core/FOrdLessThan.cl new file mode 100644 index 0000000000000..bd705b79dc1ae --- /dev/null +++ b/libclc/test/binding/core/FOrdLessThan.cl @@ -0,0 +1,134 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThan(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThan(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThan(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThan(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThan(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThan(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThan(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThan(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThan(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThan(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThan(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThan(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThan(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThan(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThan(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThan(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThan(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThan(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FOrdLessThan(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FOrdLessThanEqual.cl b/libclc/test/binding/core/FOrdLessThanEqual.cl new file mode 100644 index 0000000000000..57ff4a408e507 --- /dev/null +++ b/libclc/test/binding/core/FOrdLessThanEqual.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThanEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThanEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdLessThanEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdLessThanEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FOrdLessThanEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FOrdNotEqual.cl b/libclc/test/binding/core/FOrdNotEqual.cl new file mode 100644 index 0000000000000..4d3909b283981 --- /dev/null +++ b/libclc/test/binding/core/FOrdNotEqual.cl @@ -0,0 +1,134 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdNotEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdNotEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FOrdNotEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdNotEqual(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdNotEqual(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdNotEqual(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdNotEqual(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdNotEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdNotEqual(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdNotEqual(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdNotEqual(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdNotEqual(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdNotEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FOrdNotEqual(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FOrdNotEqual(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FOrdNotEqual(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FOrdNotEqual(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FOrdNotEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FOrdNotEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordEqual.cl b/libclc/test/binding/core/FUnordEqual.cl new file mode 100644 index 0000000000000..33b08a874174f --- /dev/null +++ b/libclc/test/binding/core/FUnordEqual.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordEqual(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordEqual(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordEqual(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordEqual(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordEqual(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordEqual(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordEqual(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordEqual(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordEqual(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordEqual(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordEqual(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordEqual(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordEqual(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordEqual(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordEqual(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_FUnordEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordGreaterThan.cl b/libclc/test/binding/core/FUnordGreaterThan.cl new file mode 100644 index 0000000000000..c33e6e1a7d8ab --- /dev/null +++ b/libclc/test/binding/core/FUnordGreaterThan.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThan(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThan(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThan(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThan(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThan(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThan(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThan(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThan(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThan(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThan(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThan(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThan(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThan(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThan(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThan(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThan(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThan(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThan(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FUnordGreaterThan(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordGreaterThanEqual.cl b/libclc/test/binding/core/FUnordGreaterThanEqual.cl new file mode 100644 index 0000000000000..def02747bacd6 --- /dev/null +++ b/libclc/test/binding/core/FUnordGreaterThanEqual.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThanEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThanEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordGreaterThanEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordGreaterThanEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FUnordGreaterThanEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordLessThan.cl b/libclc/test/binding/core/FUnordLessThan.cl new file mode 100644 index 0000000000000..d4e4c818c6475 --- /dev/null +++ b/libclc/test/binding/core/FUnordLessThan.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThan(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThan(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThan(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThan(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThan(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThan(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThan(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThan(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThan(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThan(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThan(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThan(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThan(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThan(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThan(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThan(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThan(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThan(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FUnordLessThan(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordLessThanEqual.cl b/libclc/test/binding/core/FUnordLessThanEqual.cl new file mode 100644 index 0000000000000..6eb3d65807328 --- /dev/null +++ b/libclc/test/binding/core/FUnordLessThanEqual.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThanEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThanEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordLessThanEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordLessThanEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FUnordLessThanEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/FUnordNotEqual.cl b/libclc/test/binding/core/FUnordNotEqual.cl new file mode 100644 index 0000000000000..1b5123bd6cf72 --- /dev/null +++ b/libclc/test/binding/core/FUnordNotEqual.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordNotEqual(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordNotEqual(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_FUnordNotEqual(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordNotEqual(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordNotEqual(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordNotEqual(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordNotEqual(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordNotEqual(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordNotEqual(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordNotEqual(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordNotEqual(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordNotEqual(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordNotEqual(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_FUnordNotEqual(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_FUnordNotEqual(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_FUnordNotEqual(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_FUnordNotEqual(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_FUnordNotEqual(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_FUnordNotEqual(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/IsFinite.cl b/libclc/test/binding/core/IsFinite.cl new file mode 100644 index 0000000000000..67015ef8fbcef --- /dev/null +++ b/libclc/test/binding/core/IsFinite.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsFinite(__clc_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsFinite(__clc_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsFinite(__clc_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsFinite(__clc_vec2_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsFinite(__clc_vec3_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsFinite(__clc_vec4_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsFinite(__clc_vec8_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsFinite(__clc_vec16_fp32_t args_0) { + return __spirv_IsFinite(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsFinite(__clc_vec2_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsFinite(__clc_vec3_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsFinite(__clc_vec4_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsFinite(__clc_vec8_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsFinite(__clc_vec16_fp64_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsFinite(__clc_vec2_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsFinite(__clc_vec3_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsFinite(__clc_vec4_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsFinite(__clc_vec8_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsFinite(__clc_vec16_fp16_t args_0) { + return __spirv_IsFinite(args_0); +} + +#endif diff --git a/libclc/test/binding/core/IsInf.cl b/libclc/test/binding/core/IsInf.cl new file mode 100644 index 0000000000000..f1909161090e2 --- /dev/null +++ b/libclc/test/binding/core/IsInf.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsInf(__clc_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsInf(__clc_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsInf(__clc_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsInf(__clc_vec2_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsInf(__clc_vec3_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsInf(__clc_vec4_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsInf(__clc_vec8_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsInf(__clc_vec16_fp32_t args_0) { + return __spirv_IsInf(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsInf(__clc_vec2_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsInf(__clc_vec3_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsInf(__clc_vec4_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsInf(__clc_vec8_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsInf(__clc_vec16_fp64_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsInf(__clc_vec2_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsInf(__clc_vec3_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsInf(__clc_vec4_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsInf(__clc_vec8_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsInf(__clc_vec16_fp16_t args_0) { + return __spirv_IsInf(args_0); +} + +#endif diff --git a/libclc/test/binding/core/IsNan.cl b/libclc/test/binding/core/IsNan.cl new file mode 100644 index 0000000000000..ffdc4b70cf0e4 --- /dev/null +++ b/libclc/test/binding/core/IsNan.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNan(__clc_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNan(__clc_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNan(__clc_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNan(__clc_vec2_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNan(__clc_vec3_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNan(__clc_vec4_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNan(__clc_vec8_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNan(__clc_vec16_fp32_t args_0) { + return __spirv_IsNan(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNan(__clc_vec2_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNan(__clc_vec3_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNan(__clc_vec4_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNan(__clc_vec8_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNan(__clc_vec16_fp64_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNan(__clc_vec2_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNan(__clc_vec3_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNan(__clc_vec4_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNan(__clc_vec8_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNan(__clc_vec16_fp16_t args_0) { + return __spirv_IsNan(args_0); +} + +#endif diff --git a/libclc/test/binding/core/IsNormal.cl b/libclc/test/binding/core/IsNormal.cl new file mode 100644 index 0000000000000..861223c2f3f87 --- /dev/null +++ b/libclc/test/binding/core/IsNormal.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNormal(__clc_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNormal(__clc_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_IsNormal(__clc_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNormal(__clc_vec2_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNormal(__clc_vec3_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNormal(__clc_vec4_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNormal(__clc_vec8_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNormal(__clc_vec16_fp32_t args_0) { + return __spirv_IsNormal(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNormal(__clc_vec2_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNormal(__clc_vec3_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNormal(__clc_vec4_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNormal(__clc_vec8_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNormal(__clc_vec16_fp64_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_IsNormal(__clc_vec2_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_IsNormal(__clc_vec3_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_IsNormal(__clc_vec4_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_IsNormal(__clc_vec8_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_IsNormal(__clc_vec16_fp16_t args_0) { + return __spirv_IsNormal(args_0); +} + +#endif diff --git a/libclc/test/binding/core/LessOrGreater.cl b/libclc/test/binding/core/LessOrGreater.cl new file mode 100644 index 0000000000000..3173bd3d11ea3 --- /dev/null +++ b/libclc/test/binding/core/LessOrGreater.cl @@ -0,0 +1,134 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_LessOrGreater(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_LessOrGreater(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_LessOrGreater(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_LessOrGreater(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_LessOrGreater(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_LessOrGreater(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_LessOrGreater(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_LessOrGreater(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_LessOrGreater(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_LessOrGreater(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_LessOrGreater(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_LessOrGreater(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_LessOrGreater(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_LessOrGreater(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_LessOrGreater(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_LessOrGreater(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_LessOrGreater(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_LessOrGreater(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_LessOrGreater(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/Ordered.cl b/libclc/test/binding/core/Ordered.cl new file mode 100644 index 0000000000000..890639c8e5640 --- /dev/null +++ b/libclc/test/binding/core/Ordered.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_Ordered(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_Ordered(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_Ordered(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Ordered(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Ordered(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Ordered(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Ordered(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Ordered(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Ordered(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Ordered(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Ordered(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Ordered(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Ordered(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Ordered(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Ordered(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Ordered(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Ordered(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Ordered(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_Ordered(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/core/SignBitSet.cl b/libclc/test/binding/core/SignBitSet.cl new file mode 100644 index 0000000000000..cda96cbb6384d --- /dev/null +++ b/libclc/test/binding/core/SignBitSet.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_SignBitSet(__clc_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_SignBitSet(__clc_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_SignBitSet(__clc_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SignBitSet(__clc_vec2_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SignBitSet(__clc_vec3_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SignBitSet(__clc_vec4_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SignBitSet(__clc_vec8_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SignBitSet(__clc_vec16_fp32_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SignBitSet(__clc_vec2_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SignBitSet(__clc_vec3_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SignBitSet(__clc_vec4_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SignBitSet(__clc_vec8_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SignBitSet(__clc_vec16_fp64_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SignBitSet(__clc_vec2_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SignBitSet(__clc_vec3_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SignBitSet(__clc_vec4_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SignBitSet(__clc_vec8_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SignBitSet(__clc_vec16_fp16_t args_0) { + return __spirv_SignBitSet(args_0); +} + +#endif diff --git a/libclc/test/binding/core/Unordered.cl b/libclc/test/binding/core/Unordered.cl new file mode 100644 index 0000000000000..1a49d13fe5cc3 --- /dev/null +++ b/libclc/test/binding/core/Unordered.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_bool_t +test___spirv_Unordered(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_bool_t +test___spirv_Unordered(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_bool_t +test___spirv_Unordered(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Unordered(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Unordered(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Unordered(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Unordered(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Unordered(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Unordered(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Unordered(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Unordered(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Unordered(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Unordered(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_Unordered(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_Unordered(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_Unordered(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_Unordered(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_Unordered(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_Unordered(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/bitselect.cl b/libclc/test/binding/ocl/bitselect.cl new file mode 100644 index 0000000000000..7d31d3336dd7c --- /dev/null +++ b/libclc/test/binding/ocl/bitselect.cl @@ -0,0 +1,456 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_bitselect(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_bitselect(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_bitselect(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_bitselect(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_bitselect(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_bitselect(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_bitselect(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_bitselect(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_bitselect(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_bitselect(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_bitselect(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_bitselect(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_bitselect(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_bitselect(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_bitselect(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_bitselect(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_bitselect(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_bitselect(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_bitselect(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_bitselect(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_bitselect(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_bitselect(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_bitselect(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_bitselect(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_bitselect(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_bitselect(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_bitselect(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_bitselect(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_bitselect(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_bitselect(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_bitselect(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_bitselect(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_bitselect(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_bitselect(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_bitselect(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_bitselect(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_bitselect(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_bitselect(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_bitselect(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_bitselect(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_bitselect(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_bitselect(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_bitselect(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_bitselect(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_bitselect(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_bitselect(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_bitselect(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_bitselect(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_bitselect(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_bitselect(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_bitselect(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_bitselect(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_bitselect(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_bitselect(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_fp32_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_bitselect(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_bitselect(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_bitselect(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_bitselect(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_bitselect(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_bitselect(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_fp64_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_bitselect(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_bitselect(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_bitselect(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_bitselect(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_bitselect(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_bitselect(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_fp16_t args_2) { + return __spirv_ocl_bitselect(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/test/binding/ocl/select.cl b/libclc/test/binding/ocl/select.cl new file mode 100644 index 0000000000000..93acb44e20881 --- /dev/null +++ b/libclc/test/binding/ocl/select.cl @@ -0,0 +1,863 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_select(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_select(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_select(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_select(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_select(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_select(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_select(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_select(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_select(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_select(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_select(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_select(__clc_vec16_int16_t args_0, __clc_vec16_int16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_select(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_select(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_select(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_select(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_select(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_select(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_select(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_select(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_select(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_select(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_select(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_select(__clc_vec16_int64_t args_0, __clc_vec16_int64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_select(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_select(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_select(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_select(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_select(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_select(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_select(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_select(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_select(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_select(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_select(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_select(__clc_vec16_int16_t args_0, __clc_vec16_int16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_select(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_select(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_select(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_select(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_select(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_select(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_select(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_select(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_select(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_select(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_select(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_select(__clc_vec16_int64_t args_0, __clc_vec16_int64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_select(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_select(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_select(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_select(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_select(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_select(__clc_vec16_uint8_t args_0, __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_select(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_select(__clc_vec2_uint16_t args_0, __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_select(__clc_vec3_uint16_t args_0, __clc_vec3_uint16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_select(__clc_vec4_uint16_t args_0, __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_select(__clc_vec8_uint16_t args_0, __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_select(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_select(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_select(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_select(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_select(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_select(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_select(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_select(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_select(__clc_vec2_uint64_t args_0, __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_select(__clc_vec3_uint64_t args_0, __clc_vec3_uint64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_select(__clc_vec4_uint64_t args_0, __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_select(__clc_vec8_uint64_t args_0, __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_select(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_select(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_select(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_select(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_select(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_select(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_select(__clc_vec16_uint8_t args_0, __clc_vec16_uint8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_select(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_select(__clc_vec2_uint16_t args_0, __clc_vec2_uint16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_select(__clc_vec3_uint16_t args_0, __clc_vec3_uint16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_select(__clc_vec4_uint16_t args_0, __clc_vec4_uint16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_select(__clc_vec8_uint16_t args_0, __clc_vec8_uint16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_select(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_select(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_select(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_select(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_select(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_select(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_select(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_select(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_select(__clc_vec2_uint64_t args_0, __clc_vec2_uint64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_select(__clc_vec3_uint64_t args_0, __clc_vec3_uint64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_select(__clc_vec4_uint64_t args_0, __clc_vec4_uint64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_select(__clc_vec8_uint64_t args_0, __clc_vec8_uint64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_select(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_select(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_select(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_select(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_select(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_select(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_select(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_select(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_select(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_select(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_select(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_select(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_select(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_select(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_select(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_select(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_select(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_select(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_select(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_select(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_select(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_select(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_select(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_select(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_select(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_select(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_select(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_select(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_select(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_select(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_select(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_select(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_select(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_select(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_select(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_select(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_select(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_select(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/utils/gen-libclc-test.py b/libclc/utils/gen-libclc-test.py index 3bf5e5c2186b3..bfbfe1525c797 100755 --- a/libclc/utils/gen-libclc-test.py +++ b/libclc/utils/gen-libclc-test.py @@ -13,27 +13,45 @@ def ignore_function(fun): whitelist = [ + "_All", + "_Any", "abs", "abs_diff", "add_sat", "BitCount", + "bitselect", "clz", "ControlBarrier", "ctz", + "Equal", + "GreaterThan", + "GreaterThanEqual", "GroupAsyncCopy", "GroupWaitEvents", "hadd", + "IsFinite", + "IsInf", + "IsNan", + "IsNormal", + "LessOrGreater", + "LessThan", + "LessThanEqual", "mad24", "mad_hi", "mad_sat", "MemoryBarrier", "mul24", "mul_hi", + "NotEqual", + "Ordered", "popcount", "prefetch", "rhadd", "rotate", + "select", + "SignBitSet", "sub_sat", + "Unordered", "upsample", "vload", "vstore" diff --git a/sycl/test/basic_tests/scalar_vec_access.cpp b/sycl/test/basic_tests/scalar_vec_access.cpp index df3f07f69b456..e0e793d93d174 100644 --- a/sycl/test/basic_tests/scalar_vec_access.cpp +++ b/sycl/test/basic_tests/scalar_vec_access.cpp @@ -4,8 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out %GPU_CHECK_PLACEHOLDER // RUN: %ACC_RUN_PLACEHOLDER %t.out %ACC_CHECK_PLACEHOLDER -// XFAIL: cuda - //==------- scalar_vec_access.cpp - SYCL scalar access to vec test ---------==// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. diff --git a/sycl/test/basic_tests/stream/stream.cpp b/sycl/test/basic_tests/stream/stream.cpp index 532b57d126091..6b5e6925298d1 100644 --- a/sycl/test/basic_tests/stream/stream.cpp +++ b/sycl/test/basic_tests/stream/stream.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_ON_LINUX_PLACEHOLDER %t.out %GPU_CHECK_ON_LINUX_PLACEHOLDER // RUN: %ACC_RUN_PLACEHOLDER %t.out %ACC_CHECK_PLACEHOLDER -// TODO: ptxas fatal : Unresolved extern function '_Z18__spirv_SignBitSetf' -// XFAIL: cuda - //==------------------ stream.cpp - SYCL stream basic test -----------------==// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. diff --git a/sycl/test/built-ins/scalar_relational.cpp b/sycl/test/built-ins/scalar_relational.cpp index cc30491581506..f6e362855cf83 100644 --- a/sycl/test/built-ins/scalar_relational.cpp +++ b/sycl/test/built-ins/scalar_relational.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z17__spirv_FOrdEqualff' -// XFAIL: cuda - #include #include diff --git a/sycl/test/built-ins/vector_relational.cpp b/sycl/test/built-ins/vector_relational.cpp index c8f3fc494ea88..cc279fbc109e0 100644 --- a/sycl/test/built-ins/vector_relational.cpp +++ b/sycl/test/built-ins/vector_relational.cpp @@ -4,14 +4,11 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Ptx assembly aborted due to errors -// XFAIL: cuda - #include -#include #include #include +#include namespace s = cl::sycl;